A B C D E

1 1

Compal Confidential
2 2

JALA0 M/B Schematics Document

Intel Penryn Processor with Cantiga + DDRII + ICH9M

(With Ati & nVidia MXM/B)

3
2008-04-18 3

REV:1.0

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDEN IAL
SCHEMATIC MB A4221
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401552
Date Friday, May 16, 2008 Sheet 1 of 50
A B C D E
 A B C D E

Compal Confidential
Intel Penryn Processor Thermal Sensor Clock Generator
Fan Control
Model Name : JALA0 page 36
SMSC EMC1402-1 ICS9LPRS387
uPGA-478 Package page 4 page 16
File Name : LA-4221P
(Socket P) page 4,5,6
1 1
FSB
H_A#(3..35) 667/800/1066MHz H_D#(0..63)
HDMI Conn. LCD Conn. CRT Conn.
page 20 page 18 page 19

LVDS Intel Cantiga Memory BUS(DDRII) 200pin DDRII-SO-DIMM X2

CH7318 Dual Channel
(HDMI/B) SDVO (PM / GM / GL) BANK 0, 1, 2, 3 page 14,15

page 25 1.8V DDRII 667 / 800

LVDS uFCBGA-1329
PCI-Express page 7,8,9,10,11,12,13
TMDS MXM II VGA/B 16X
nVidia 9MGS(256MB/GDDR2)
nVidia 9PGE2(256MB/GDDR3) DMI C-Link USB conn x2 Bluetooth CMOS Finger Print
Ati M82M(256MB/GDDR2) USB port 0, 2 Conn Camera Upek TCS4EA
page 17

PCI-Express
2
Intel ICH9-M 3.3V 48MHz USB
2

Card Reader
JMB385 3.3V 24.576MHz/48Mhz HD Audio
page 26 S-ATA
BGA-676
MINI Card x2 LAN(GbE)
Broadcom page 21,22,23,24
5 in 1 WLAN, Robson2 BCM5764M port 0 port 1
socket page 29 page 27 GMCH HDA MDC 1.5 HDA Codec
page 26 Conn ALC268
page 08 page 33 page 34
SATA HDD CDROM
Conn. page 30
Conn. page 30 PCI Bus
DOCKING RJ45
3.3V 33MHz
page 28
(DVI/LAN/ Audio AMP
CRT/USB/AUDIO) page 35
page 38
SPI FLASH ROM (2MB)
3
ME for iTPM only page 23 CardBus 3

PWR/B Conn. LPC BUS OZ601 Phone Jack x3

RTC CKT. page 25 page 35
page 32
page 22

ENE KB926
Power On/Off CKT. FUN/B Conn. page 31
Slot 0
page 32 page 25
page 33 SPI FLASH ROM (2MB)
EC BIOS / SYS BIOS / FP(PBA)
USB/B Conn. / HDCP page 32
DC/DC Interface CKT.
USB port 4
page 37 page 29 Touch Pad Int.KBD
page 32

Power Circuit DC/DC EC I/O Buffer

page 39,40,41,42
43,44,45,46 page 32

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDEN IAL
SCHEMATIC MB A4221
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401552
Date Friday, May 16, 2008 Sheet 2 of 50
A B C D E
 A B C D E

SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Voltage Rails
Full ON HIGH HIGH HIGH HIGH ON ON ON ON

Power Plane Description S1 S3 S5 S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW

VIN Adapter power supply (19V) N/A N/A N/A S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
B+ AC or battery power rail for power circuit. N/A N/A N/A
1
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF 1
+CPU_CORE Core voltage for CPU ON OFF OFF
+0.9VS 0.9V switched power rail for DDR terminator ON OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+1.05VS 1.05V switched power rail ON OFF OFF
+1.25VS 1.25V switched power rail ON OFF OFF
+1.5VS 1.5V switched power rail ON OFF OFF Board ID / SKU ID Table for AD channel
+1.8V 1.8V power rail for DDR ON ON OFF Vcc 3.3V +/- 5%
+1.8VS 1.8V switched power rail ON OFF OFF Ra/Rc/Re 100K +/- 5%
+2.5VS 2.5V switched power rail ON OFF OFF Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
+3VALW 3.3V always on power rail ON ON ON* 0 0 0 V 0 V 0 V
+3V 3.3V power rail for SB ON ON X 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
+3V_LAN 3.3V power rail for LAN ON ON X 2 18K +/- 5% 0.436 V 0.503 V 0.538 V
+3VS 3.3V switched power rail ON OFF OFF 3 33K +/- 5% 0.712 V 0.819 V 0.875 V
+5VALW 5V always on power rail ON ON ON* 4 56K +/- 5% 1.036 V 1.185 V 1.264 V
+5VS 5V switched power rail ON OFF OFF 5 100K +/- 5% 1.453 V 1.650 V 1.759 V
+VSB VSB always on power rail ON ON ON* 6 200K +/- 5% 1.935 V 2.200 V 2.341 V
+RTCVCC RTC power ON ON ON 7 NC 2.500 V 3.300 V 3.300 V
2 2

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

BOARD ID Table BTO Option Table

External PCI Devices Board ID PCB Revision BTO Item BOM Structure
Device IDSEL# REQ#/GNT# Interrupts
0 0.1 Discrete_H PM@
Cardbus OZ601 AD16 0 PIRQE
1 0.2 UMA GM@
2 0.3 UMA_H UMAGM@
3 1.0 UMA_L UMAGL@
4 1A Kinabalu_H MAIN@
5 Kinabalu_L VALUE@
6 RTC Batt 45@
7 ICH9M BASE ICH9MB@
ICH9M ENHANCE ICH9ME@
SB ROM(2MB) SPI2MB@
EC SM Bus1 address EC SM Bus2 address SB ROM(4MB) SPI4MB@
3 3
Device Address Device Address Kinabalu_L : UMA(GL) & w/o Dock & w/o Mini card 2
Smart Battery 0001 011X b ADT7421 1001 100X b & w/o iTPM
EEPROM(24C16/02) 1010 000X b (LAN BCM5764M) Reserved
GPU(MXM/B) 1001 111X b

ICH9M SM Bus address

Device Address
Clock Generator
(ICS9LPRS387) 1101 001Xb

DDR DIMM0 1001 000Xb

DDR DIMM1 1001 010Xb
LAN BCM5764M Reserved
(MINI CARD_WL_Robson) Reserved

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDEN IAL
SCHEMATIC MB A4221
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401552
Date Friday, May 16, 2008 Sheet 3 of 50
A B C D E
 5 4 3 2 1

H_A#[3..35]
7 H_A#[3..35]
H_REQ#[0..4]
7 H_REQ#[0..4]
H_RS#[0..2]
7 H_RS#[0..2]
JCPU1A
H_A#3 J4 H1 H_ADS# 7
A[3]# ADS#

ADDR GROUP_0
H_A#4 L5 E2 H_BNR# 7
H_A#5 A[4]# BNR#
D L4 A[5]# BPRI# G5 H_BPRI# 7 D
H_A#6 K5
H_A#7 A[6]#
M3 A[7]# DEFER# H5 H_DEFER# 7
H_A#8 N2 F21
A[8]# DRDY# H_DRDY# 7
H_A#9 J1 E1
A[9]# DBSY# H_DBSY# 7
H_A#10 N3
H_A#11 A[10]#
P5 A[11]# BR0# F1 H_BR0# 7
H_A#12 P2 A[12]#

CONTROL
H_A#13 L2 D20 H_IERR#
H_A#14 A[13]# IERR#
P4 A[14]# INIT# B3 H_INIT# 22
H_A#15 P1
H_A#16 A[15]#
R1 A[16]# LOCK# H4 H_LOCK# 7
7 H_ADSTB#0 M1 ADSTB[0]#
C1 H_RESET# H_RESET# 7
H_REQ#0 RESET# H_RS#0
K3 REQ[0]# RS[0]# F3
H_REQ#1 H2 F4 H_RS#1
H_REQ#2 REQ[1]# RS[1]# H_RS#2
K2 REQ[2]# RS[2]# G3
H_REQ#3 J3 G2 H_TRDY# 7
H_REQ#4 REQ[3]# TRDY#
L1 REQ[4]#
HIT# G6 H_HIT# 7
H_A#17 Y2 E4
A[17]# HITM# H_HITM# 7
H_A#18 U5
H_A#19 A[18]#
R3 A[19]# BPM[0]# AD4

ADDR GROUP_1
H_A#20 W6 AD3
H_A#21 A[20]# BPM[1]#
U4 A[21]# BPM[2]# AD1
H_A#22 Y5 AC4
A[22]# BPM[3]#
XDP/ITP SIGNALS
H_A#23 U1 AC2
H_A#24 A[23]# PRDY# XDP_BPM#5
R4 A[24]# PREQ# AC1
H_A#25 T5 AC5 XDP_TCK
C H_A#26 A[25]# TCK XDP_TDI C
T3 A[26]# TDI AA6
H_A#27 W2 AB3
H_A#28 A[27]# TDO XDP_TMS
W5 A[28]# TMS AB5
H_A#29 Y4 AB6 XDP_TRST#
H_A#30 A[29]# TRST# XDP_DBRESET#
U2 A[30]# DBR# C20 XDP_DBRESET# 23
H_A#31 V4
H_A#32 A[31]# 1.05VS
W3 A[32]#
H_A#33 AA4 THERMAL
H_A#34 A[33]#
AB2 A[34]#
H_A#35 AA3 D21 H_PROCHOT#
A[35]# PROCHOT# H_THERMDA_R
7 H_ADSTB#1 V1 ADSTB[1]# THERMDA A24 DVT
B25 H_THERMDC_R XDP_TDI R25 1 2 54.9_0402_1%
THERMDC
22 H_A20M# A6 A20M#
ICH

22 H_FERR# A5 FERR# THERMTRIP# C7 H_THERMTRIP# 8,22 left NC if no ITP

22 H_IGNNE# C4 IGNNE# DVT
XDP_TMS R18 1 2 54.9_0402_1% 39Ohm
22 H_STPCLK# D5 STPCLK#
C6 H CLK XDP_BPM#5 R10 1 2 54.9_0402_1%
22 H_INTR LINT0
B4 A22 DEL_DVT(ESD) @
22 H_NMI LINT1 BCLK[0] CLK_CPU_BCLK 16
22 H_SMI# A3 SMI# BCLK[1] A21 CLK_CPU_BCLK# 16
M4 H_PROCHOT# R42 2 1 56_0402_5%
RSVD[01]
N5 RSVD[02]
T2 H_IERR# R41 2 1 56_0402_5%
RSVD[03]
V3 RSVD[04]
RESERVED

B2 RSVD[05] Layout Note:

D2 RSVD[06]
D22 H_THERMDA&H_THERMDC Trace / Space = 10 / 10 mil DVT
RSVD[07]
D3 RSVD[08]
B XDP_TRST# R11 54.9_0402_1% B
F6 RSVD[09] 2 1

XDP_TCK R9 1 2 54.9_0402_1%

Penryn
CONN@
3VS
C107
0.1U_0402_16V4Z
1 2
JALA0

2
R64 DVT
1.05VS R56 0_0402_5% 10K_0402_5%
BSEL2 BSEL1 BSEL0 BCLK H_THERMDA_R 1 2 H THERMDA @
U9

1
0 0 0 266 1 VDD SCLK 8 EC_SMB_CK2 27,31
1

1
R60 C108 2 7
D+ SDATA EC_SMB_DA2 27,31
0 1 0 200 56_0402_5%
2200P_0402_50V7K
@ 3 D- ALERT/THERM2 6 1 2 3VS
2 @ R652
2

0 1 1 166 R55 0_0402_5% THERM# 4 5 10K_0402_5% DVT(JALA0)

H_THERMDC_R THERM GND
1 2 H THERMDC
2
B

EMC1402-1-ACZL-TR_MSOP8
DVT
E

H_PROCHOT# 3 1 OCP# 23
A A
C

Q5 DVT(JALA0) SMSC : SA00001Z700(S IC EMC1402-1-ACZL-TR MSOP 8P SENSOR)

MMBT3904_SOT23-3
@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT AL
SCHEMATIC MB A4221
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401552
Date: Friday, May 16, 2008 Sheet 4 of 50
5 4 3 2 1
 5 4 3 2 1

H_D#[0..63] JCPU1C
H_D#[0..63] 7
CPU_CORE A7 VCC[001] VCC[068] AB20 CPU_CORE
JCPU1B A9 AB7
H_D#0 H_D#32 VCC[002] VCC[069]
E22 D[0]# D[32]# Y22 A10 VCC[003] VCC[070] AC7
D H_D#1 F24 AB24 H_D#33 A12 AC9 D
H_D#2 D[1]# D[33]# H_D#34 VCC[004] VCC[071]
E26 D[2]# D[34]# V24 A13 VCC[005] VCC[072] AC12

DATA GRP 0
H_D#3 G22 V26 H_D#35 A15 AC13

DATA GRP 2
H_D#4 D[3]# D[35]# H_D#36 VCC[006] VCC[073]
F23 D[4]# D[36]# V23 A17 VCC[007] VCC[074] AC15
H_D#5 G25 T22 H_D#37 A18 AC17
H_D#6 D[5]# D[37]# H_D#38 VCC[008] VCC[075]
E25 D[6]# D[38]# U25 A20 VCC[009] VCC[076] AC18
H_D#7 E23 U23 H_D#39 B7 AD7
H_D#8 D[7]# D[39]# H_D#40 VCC[010] VCC[077]
K24 D[8]# D[40]# Y25 B9 VCC[011] VCC[078] AD9
H_D#9 G24 W22 H_D#41 B10 AD10
H_D#10 D[9]# D[41]# H_D#42 VCC[012] VCC[079]
J24 D[10]# D[42]# Y23 B12 VCC[013] VCC[080] AD12
H_D#11 J23 W24 H_D#43 B14 AD14
H_D#12 D[11]# D[43]# H_D#44 VCC[014] VCC[081]
H22 D[12]# D[44]# W25 B15 VCC[015] VCC[082] AD15
H_D#13 F26 AA23 H_D#45 B17 AD17
H_D#14 D[13]# D[45]# H_D#46 VCC[016] VCC[083]
K22 D[14]# D[46]# AA24 B18 VCC[017] VCC[084] AD18
H_D#15 H23 AB25 H_D#47 B20 AE9
D[15]# D[47]# VCC[018] VCC[085]
7 H_DSTBN#0 J26 DSTBN[0]# DSTBN[2]# Y26 H_DSTBN#2 7 C9 VCC[019] VCC[086] AE10
7 H_DSTBP#0 H26 DSTBP[0]# DSTBP[2]# AA26 H_DSTBP#2 7 C10 VCC[020] VCC[087] AE12
7 H_DINV#0 H25 DINV[0]# DINV[2]# U22 H_DINV#2 7 C12 VCC[021] VCC[088] AE13
C13 VCC[022] VCC[089] AE15
C15 VCC[023] VCC[090] AE17
H_D#16 N22 AE24 H_D#48 C17 AE18
H_D#17 D[16]# D[48]# H_D#49 VCC[024] VCC[091]
K25 D[17]# D[49]# AD24 C18 VCC[025] VCC[092] AE20
H_D#18 P26 AA21 H_D#50 D9 AF9
H_D#19 D[18]# D[50]# H_D#51 VCC[026] VCC[093]
R23 D[19]# D[51]# AB22 D10 VCC[027] VCC[094] AF10
H_D#20 L23 AB21 H_D#52 D12 AF12
D[20]# D[52]# VCC[028] VCC[095]

DATA GRP 1
H_D#21 M24 AC26 H_D#53 D14 AF14

DATA GRP 3
H_D#22 D[21]# D[53]# H_D#54 VCC[029] VCC[096]
L22 D[22]# D[54]# AD20 D15 VCC[030] VCC[097] AF15
H_D#23 M23 AE22 H_D#55 D17 AF17
H_D#24 D[23]# D[55]# H_D#56 VCC[031] VCC[098]
P25 D[24]# D[56]# AF23 D18 VCC[032] VCC[099] AF18
C H_D#25 P23 AC25 H_D#57 E7 AF20 C
1.05VS H_D#26 D[25]# D[57]# H_D#58 VCC[033] VCC[100]
P22 D[26]# D[58]# AE21 E9 VCC[034]
H_D#27 T24 AD21 H_D#59 E10 G21 1.05VS
H_D#28 D[27]# D[59]# H_D#60 VCC[035] VCCP[01]
R24 D[28]# D[60]# AC22 E12 VCC[036] VCCP[02] V6
H_D#29 L25 AD23 H_D#61 E13 J6
D[29]# D[61]# VCC[037] VCCP[03]
2

H_D#30 T25 AF22 H_D#62 E15 K6

R318 H_D#31 D[30]# D[62]# H_D#63 VCC[038] VCCP[04]
N25 D[31]# D[63]# AC23 E17 VCC[039] VCCP[05] M6
1K_0402_1% 7 H_DSTBN#1 L26 DSTBN[1]# DSTBN[3]# AE25 H_DSTBN#3 7 E18 VCC[040] VCCP[06] J21
7 H_DSTBP#1 M26 DSTBP[1]# DSTBP[3]# AF24 H_DSTBP#3 7 E20 VCC[041] VCCP[07] K21
7 H_DINV#1 N24 AC20 H_DINV#3 7 F7 M21
1

DINV[1]# DINV[3]# VCC[042] VCCP[08]

Trace Close CPU < 0.5' GTL_REF0 COMP0 R334 27.4_0402_1%
F9 VCC[043] VCCP[09] N21
AD26 GTLREF COMP[0] R26 1 2 F10 VCC[044] VCCP[10] N6
Width=4 mil , R366 2 1 @ 1K_0402_5% TEST1 C23 MISC U26 COMP1 R330 1 2 54.9_0402_1% F12 R21
R365 TEST1 COMP[1] VCC[045] VCCP[11]
2 1 @ 1K_0402_5% TEST2 D25 AA1 COMP2 R12 1 2 27.4_0402_1% F14 R6
Spacing: 15mil TEST2 COMP[2] VCC[046] VCCP[12]
2

T3 PAD @ TEST3 C24 TEST3 COMP[3] Y1 COMP3 R15 1 2 54.9_0402_1% F15 VCC[047] VCCP[13] T21
(55Ohm) R319 C385 1 2 @ 0.1U_0402_16V4Z TEST4 AF26 F17 T6
TEST4 VCC[048] VCCP[14]
2K_0402_1% T2 PAD @ TEST5 AF1 TEST5 DPRSTP# E5 H_DPRSTP# 8,22,46 F18 VCC[049] VCCP[15] V21
@ TEST6 A26 B5 F20 W21
T18 PAD TEST6 DPSLP# H_DPSLP# 22 VCC[050] VCCP[16]
C3 D24 H_DPWR# 7 AA7 20mils
1

TEST7 DPWR# H_PWRGOOD VCC[051]

16 CPU_BSEL0 B22 BSEL[0] PWRGOOD D6 H_PWRGOOD 22 AA9 VCC[052] VCCA[01] B26 1.5VS
16 CPU_BSEL1 B23 D7 H_CPUSLP# AA10 C26
BSEL[1] SLP# H_CPUSLP# 7 VCC[053] VCCA[02]
16 CPU_BSEL2 C21 BSEL[2] PSI# AE6 PSI# 46 AA12 VCC[054] 1 1
AA13 AD6 CPU_VID0 46 C101 C102
Penryn VCC[055] VID[0]
AA15 VCC[056] VID[1] AF5 CPU_VID1 46
CONN@ AA17 AE5 CPU_VID2 46 0.01U_0402_16V7K
VCC[057] VID[2] 2 2
TRACE CLOSELY CPU < 0.5' AA18 VCC[058] VID[3] AF4 CPU_VID3 46
AA20 VCC[059] VID[4] AE3 CPU_VID4 46
COMP0, COMP2 layout : Width 18mils and Space 25mils (27.4Ohms) AB9 AF3 CPU_VID5 46 10U_0805_10V4Z
VCC[060] VID[5]
COMP1, COMP3 layout : Width 4mils and Space 25mils (55Ohms) AC10 VCC[061] VID[6] AE2 CPU_VID6 46
B B
AB10 VCC[062] 1 2 CPU_CORE
AB12 R315 100_0402_1%
VCC[063] VCCSENSE
AB14 VCC[064] VCCSENSE AF7 VCCSENSE 46
AB15 VCC[065]
AB17 VCC[066]
AB18 AE7 VSSSENSE VSSSENSE 46
VCC[067] VSSSENSE
Penryn 1 2
CONN@ . R316 100_0402_1%

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT AL
SCHEMATIC MB A4221
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401552
Date: Friday, May 16, 2008 Sheet 5 of 50
5 4 3 2 1
 5 4 3 2 1

CPU_CORE CPU_CORE
2 x 330uF(6mOhm/2) 2 x 330uF(6mOhm/2)
JCPU1D 1 1 1 1
A4 VSS[001] VSS[082] P6
A8 P21 C380 + C2 + C106 + C381 +
VSS[002] VSS[083]
A11 VSS[003] VSS[084] P24
A14 R2 330U_D2E_2.5VM_R9 330U_D2E_2.5VM_R9 330U_D2E_2.5VM_R9 330U_D2E_2.5VM_R9
VSS[004] VSS[085] 2 2 2 2
A16 VSS[005] VSS[086] R5
A19 VSS[006] VSS[087] R22
D A23 VSS[007] VSS[088] R25 D
AF2 VSS[008] VSS[089] T1 South Side Secondary North Side Secondary
B6 VSS[009] VSS[090] T4
B8 VSS[010] VSS[091] T23
B11 T26 CPU_CORE
VSS[011] VSS[092]
B13 VSS[012] VSS[093] U3
B16 VSS[013] VSS[094] U6
B19 VSS[014] VSS[095] U21
B21 VSS[015] VSS[096] U24 1 1 1 1 1 1 1 1
B24 V2 C407 C406 C397 C73 C74 C66 C29 C400
VSS[016] VSS[097]
C5 VSS[017] VSS[098] V5
C8 V22 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
VSS[018] VSS[099] 2 2 2 2 2 2 2 2
C11 VSS[019] VSS[100] V25
C14 W1 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
VSS[020] VSS[101]
C16 VSS[021] VSS[102] W4
C19 VSS[022] VSS[103] W23 (Place these capacitors on South side,Secondary Layer)
C2 VSS[023] VSS[104] W26
C22 VSS[024] VSS[105] Y3
C25 Y6 CPU_CORE
VSS[025] VSS[106]
D1 VSS[026] VSS[107] Y21
D4 VSS[027] VSS[108] Y24
D8 VSS[028] VSS[109] AA2
D11 VSS[029] VSS[110] AA5 1 1 1 1 1 1 1 1
D13 AA8 C15 C14 C13 C12 C11 C395 C398 C90
VSS[030] VSS[111]
D16 VSS[031] VSS[112] AA11
D19 AA14 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
VSS[032] VSS[113] 2 2 2 2 2 2 2 2
D23 VSS[033] VSS[114] AA16
D26 AA19 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
VSS[034] VSS[115]
E3 VSS[035] VSS[116] AA22
C E6 AA25 (Place these capacitors on North side,Secondary Layer) C
VSS[036] VSS[117]
E8 VSS[037] VSS[118] AB1
E11 VSS[038] VSS[119] AB4
E14 AB8 CPU_CORE
VSS[039] VSS[120]
E16 VSS[040] VSS[121] AB11
E19 VSS[041] VSS[122] AB13
E21 VSS[042] VSS[123] AB16
E24 VSS[043] VSS[124] AB19 1 1 1 1 1 1 1 1
F5 AB23 C89 C88 C87 C86 C394 C390 C67 C30
VSS[044] VSS[125]
F8 VSS[045] VSS[126] AB26
F11 AC3 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
VSS[046] VSS[127] 2 2 2 2 2 2 2 2
F13 VSS[047] VSS[128] AC6
F16 AC8 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
VSS[048] VSS[129]
F19 VSS[049] VSS[130] AC11
F2 VSS[050] VSS[131] AC14 (Place these capacitors on South side,Primary Layer)
F22 VSS[051] VSS[132] AC16
F25 VSS[052] VSS[133] AC19
G4 AC21 CPU_CORE
VSS[053] VSS[134]
G1 VSS[054] VSS[135] AC24
G23 VSS[055] VSS[136] AD2
G26 VSS[056] VSS[137] AD5
H3 VSS[057] VSS[138] AD8 1 1 1 1 1 1 1 1
H6 AD11 C399 C396 C392 C393 C403 C391 C404 C405
VSS[058] VSS[139]
H21 VSS[059] VSS[140] AD13
H24 AD16 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
VSS[060] VSS[141] 2 2 2 2 2 2 2 2
J2 VSS[061] VSS[142] AD19
J5 AD22 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
VSS[062] VSS[143]
J22 VSS[063] VSS[144] AD25
B
J25 VSS[064] VSS[145] AE1 (Place these capacitors on North side,Primary Layer) B
K1 VSS[065] VSS[146] AE4
K4 VSS[066] VSS[147] AE8
K23 VSS[067] VSS[148] AE11
K26 VSS[068] VSS[149] AE14 +CPU-CORE C,uF ESR, mohm ESL,nH
L3 AE16
L6
VSS[069] VSS[150]
AE19 Decoupling
VSS[070] VSS[151]
L21 VSS[071] VSS[152] AE23 SPCAP,Polymer 4X330uF 6m ohm/4 1.8nH/6
L24 VSS[072] VSS[153] AE26
M2 VSS[073] VSS[154] A2 32X22uF 3m ohm/32 0.6nH/32
M5 VSS[074] VSS[155] AF6 MLCC 0805 X5R
M22 VSS[075] VSS[156] AF8 32X10uF 3m ohm/32 0.6nH/32
M25 VSS[076] VSS[157] AF11
N1 VSS[077] VSS[158] AF13
N4 VSS[078] VSS[159] AF16
N23 VSS[079] VSS[160] AF19
N26 VSS[080] VSS[161] AF21
P3 A25 1.05VS
VSS[081] VSS[162]
VSS[163] AF25
Penryn 1
CONN@ . 1 1 1 1 1 1
+ C33 C17 C52 C79 C72 C63 C85

330U_D2E_2.5VM_R15 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

2 2 2 2 2 2 2
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT AL
SCHEMATIC MB A4221
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401552
Date: Friday, May 16, 2008 Sheet 6 of 50
5 4 3 2 1
 5 4 3 2 1

H_A#[3..35] 4
5 H_D#[0..63] U30A
A14 H_A#3
H_D#0 H_A#_3 H_A#4
F2 H_D#_0 H_A#_4 C15
H_D#1 G8 F16 H_A#5
H_D#2 H_D#_1 H_A#_5 H_A#6
F8 H_D#_2 H_A#_6 H13
H_D#3 E6 C18 H_A#7
H_D#4 H_D#_3 H_A#_7 H_A#8
G2 H_D#_4 H_A#_8 M16
D H_D#5 H6 J13 H_A#9 D
H_D#6 H_D#_5 H_A#_9 H_A#10
H2 H_D#_6 H_A#_10 P16
H_D#7 F6 R16 H_A#11
H_D#8 H_D#_7 H_A#_11 H_A#12
D4 H_D#_8 H_A#_12 N17
H_D#9 H3 M13 H_A#13
H_D#10 H_D#_9 H_A#_13 H_A#14
M9 H_D#_10 H_A#_14 E17
H_D#11 M11 P17 H_A#15
H_D#12 H_D#_11 H_A#_15 H_A#16
J1 H_D#_12 H_A#_16 F17
H_D#13 J2 G20 H_A#17
H_D#14 H_D#_13 H_A#_17 H_A#18
N12 H_D#_14 H_A#_18 B19
H_D#15 J6 J16 H_A#19
H_D#16 H_D#_15 H_A#_19 H_A#20
P2 H_D#_16 H_A#_20 E20
H_D#17 L2 H16 H_A#21
H_D#18 H_D#_17 H_A#_21 H_A#22
R2 H_D#_18 H_A#_22 J20
H_D#19 N9 L17 H_A#23
H_D#20 H_D#_19 H_A#_23 H_A#24
L6 H_D#_20 H_A#_24 A17
H_D#21 M5 B17 H_A#25
1.05VS H_D#22 H_D#_21 H_A#_25 H_A#26
J3 H_D#_22 H_A#_26 L16
H_D#23 N2 C21 H_A#27
H_D#24 H_D#_23 H_A#_27 H_A#28
R1 H_D#_24 H_A#_28 J17
1

H_D#25 N5 H20 H_A#29

R88 H_D#26 H_D#_25 H_A#_29 H_A#30
N6 H_D#_26 H_A#_30 B18
H_D#27 P13 K17 H_A#31
221_0402_1% H_D#28 H_D#_27 H_A#_31 H_A#32
N8 H_D#_28 H_A#_32 B20
H_D#29 L7 F21 H_A#33
2

H_SWING H_D#30 H_D#_29 H_A#_33 H_A#34

N10 H_D#_30 H_A#_34 K21
H_D#31 M3 L20 H_A#35
H_D#32 H_D#_31 H_A#_35
wid h=10mil Y3 H_D#_32
2

1 H_D#33 AD14 H12 H_ADS#

H_D#_33 H_ADS# H_ADS# 4
C R87 C164 H_D#34 Y6 B16 H_ADSTB#0 C
H_D#_34 H_ADSTB#_0 H_ADSTB#0 4
H_D#35 Y10 G17 H_ADSTB#1
H_D#_35 H_ADSTB#_1 H_ADSTB#1 4
100_0402_1% 0.1U_0402_16V4Z H_D#36 Y12 A9 H_BNR#
2 H_D#_36 H_BNR# H_BNR# 4

HOST
H_D#37 Y14 F11 H_BPRI#
H_BPRI# 4
1

H_D#38 H_D#_37 H_BPRI# H_BR0#

Y7 H_D#_38 H_BREQ# G12 H_BR0# 4
H_D#39 W2 E9 H_DEFER#
H_D#_39 H_DEFER# H_DEFER# 4
H_D#40 AA8 B10 H_DBSY#
H_D#_40 H_DBSY# H_DBSY# 4
H_D#41 Y9 AH7 CLK_MCH_BCLK
H_D#_41 HPLL_CLK CLK_MCH_BCLK 16
H_RCOMP H_D#42 AA13 AH6 CLK_MCH_BCLK#
H_D#_42 HPLL_CLK# CLK_MCH_BCLK# 16
H_D#43 AA9 J11 H_DPWR#
H_D#_43 H_DPWR# H_DPWR# 5
wid h=10mil H_D#44 AA11 F9 H_DRDY#
H_D#_44 H_DRDY# H_DRDY# 4
1

H_D#45 AD11 H9 H_HIT#

H_D#_45 H_HIT# H_HIT# 4
R409 H_D#46 AD10 E12 H_HITM#
H_D#_46 H_HITM# H_HITM# 4
H_D#47 AD13 H11 H_LOCK#
H_D#_47 H_LOCK# H_LOCK# 4
24.9_0402_1% H_D#48 AE12 C9 H_TRDY#
H_D#_48 H_TRDY# H_TRDY# 4
H_D#49 AE9
2

H_D#50 H_D#_49
AA2 H_D#_50
H_D#51 AD8
H_D#52 H_D#_51
AA3 H_D#_52
H_D#53 AD3 J8 H_DINV#0
H_D#54 H_D#_53 H_DINV#_0 H_DINV#1 H_DINV#0 5
AD7 H_D#_54 H_DINV#_1 L3 H_DINV#1 5
H_D#55 AE14 Y13 H_DINV#2
H_D#56 H_D#_55 H_DINV#_2 H_DINV#3 H_DINV#2 5
AF3 H_D#_56 H_DINV#_3 Y1 H_DINV#3 5
H_D#57 AC1
H_D#58 H_D#_57 H_DSTBN#0
AE3 H_D#_58 H_DSTBN#_0 L10 H_DSTBN#0 5
H_D#59 AC3 M7 H_DSTBN#1
H_D#60 H_D#_59 H_DSTBN#_1 H_DSTBN#2 H_DSTBN#1 5
AE11 H_D#_60 H_DSTBN#_2 AA5 H_DSTBN#2 5
H_D#61 AE8 AE6 H_DSTBN#3
H_D#62 H_D#_61 H_DSTBN#_3 H_DSTBN#3 5
AG2 H_D#_62
B H_D#63 H_DSTBP#0 B
AD6 H_D#_63 H_DSTBP#_0 L9 H_DSTBP#0 5
M8 H_DSTBP#1
H_DSTBP#_1 H_DSTBP#2 H_DSTBP#1 5
H_DSTBP#_2 AA6 H_DSTBP#2 5
H_SWING C5 AE5 H_DSTBP#3
H_RCOMP H_SWING H_DSTBP#_3 H_DSTBP#3 5
E3 H_RCOMP H_REQ#[0..4] 4
1.05VS B15 H_REQ#0
H_REQ#_0 H_REQ#1
H_REQ#_1 K13
F13 H_REQ#2
H_REQ#_2
2

B13 H_REQ#3
R100 H_RESET# H_REQ#_3 H_REQ#4
4 H_RESET# C12 H_CPURST# H_REQ#_4 B14
H_CPUSLP# E11
5 H_CPUSLP# H_CPUSLP# H_RS#[0..2] 4
1K_0402_1% B6 H_RS#0
H_RS#_0 H_RS#1
F12
1

H_AVREF H_RS#_1 H_RS#2

wid h:spacing=10mil:20mil (<0.5") A11 H_AVREF H_RS#_2 C8
B11 H_DVREF
1

1
R96 C172 CANTIGA ES_FCBGA1329
UMAGM@
2K_0402_1% 0.1U_0402_16V4Z
2
DVT CANTIGA GM: SA00001P930
2

(S IC EB88CTGM QR32 B0 FCBGA 1329 MCH GM)

PVT CANTIGA GM: SA00002JT10
within 100mil to Ball A9,B9 (S IC AC88CTGM QT62 B2 FCBGA 1329 GMCH GM)
PVT2 CANTIGA GM: SA00002JT50
A
(S IC AC88CTGM QU36 B3 FCBGA 1329 GMCH GM) A

Pre-MP CANTIGA GM: SA00002JTB0

(S IC AC82GM45 SLB94 B3 FCBGA1329 GM ABO!)
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT AL
SCHEMATIC MB A4221
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401552
Date: Friday, May 16, 2008 Sheet 7 of 50
5 4 3 2 1
 5 3 2 1

U30B +1.8V

M36 RSVD1 SA_CK_0 AP24 DDRA_CLK0 14

1
N36 RSVD2 SA_CK_1 AT21 DDRA_CLK1 14
R33 AV24 R445
RSVD3 SB_CK_0 DDRB_CLK0 15
T33 AU20

COMPENSATION
RSVD4 SB_CK_1 DDRB_CLK1 15
AH9 1K_0402_1%
RSVD5
AH10 AR24 DDRA_CLK0# 14

2
RSVD6 SA_CK#_0 SM_RCOMP_VOH
AH12 RSVD7 SA_CK#_1 AR21 DDRA_CLK1# 14
AH13 RSVD8 SB_CK#_0 AU24 DDRB_CLK0# 15
K12 RSVD9 SB_CK#_1 AV20 DDRB_CLK1# 15 1 1

1
JTAG_TCK T39 PAD @ AL34 C489 C488
T40 @ RSVD10 R442 <BOM Structure>
JTAG_TDI PAD AK34 BC28 DDRA_CKE0 14
T41 @ RSVD11 SA_CKE_0 2.2U_0603_6.3V6K 0.01U_0402_16V7K
JTAG_TDO PAD AN35 AY28 DDRA_CKE1 14
D T42 @ RSVD12 SA_CKE_1 2 2 D
JTAG_TMS PAD AM35 RSVD13 SB_CKE_0 AY36 DDRB_CKE0 15 SM_DRAMRST# would be 3.01K_0402_1%
PVT2 JALA0 (Add Management Engine JTAG pins) T24 BB36 DDRB_CKE1 15 needed for DDR3 only

2
RSVD14 SB_CKE_1

SA_CS#_0 BA17 DDRA_SCS0# 14

All RSVD balls on GMCH should be left No AY16 SM_RCOMP_VOL
SA_CS#_1 DDRA_SCS1# 14
Connect. B31 RSVD15 SB_CS#_0 AV16 DDRB_SCS0# 15 For Cantiga 80 Ohm

1
B2 RSVD16 SB_CS#_1 AR13 DDRB_SCS1# 15 1 1

DDR CLK/ CONTROL/

M1 R441 C483 C484
RSVD17

RSVD
BD17 <BOM Structure>
SA_ODT_0 DDRA_ODT0 14
AY17 1K_0402_1% 2.2U_0603_6.3V6K 0.01U_0402_16V7K
+1.05VS SA_ODT_1 DDRA_ODT1 14 2 2
AY21 BF15 DDRB_ODT0 15

2
+3VS +1.05VS RSVD20 SB_ODT_O +1.8V +1.8V
SB_ODT_1 AY13 DDRB_ODT1 15 JALA0
BG22 SMRCOMP R438 1 2 80.6_0402_1%
SM_RCOMP

2
R682 BG23 BH21 SMRCOMP# R437 1 2 80.6_0402_1%
1K_0402_1% RSVD22 SM_RCOMP# R187
BF23 RSVD23
BH18 BF28 SM_RCOMP_VOH 1K_0402_1% DVT
RSVD24 SM_RCOMP_VOH

2
BF18 BH28 SM_RCOMP_VOL @
T43 RSVD25 SM_RCOMP_VOL
1

20mil CLK_DREF_96M R528 1 2PM@ 0_0402_5%

1
R679 R680 PAD AV42 SM_VREF 1 2 CLK_DREF_96M# R527 1 2PM@ 0_0402_5%
SM_VREF +DIMM_VREF
10K_0402_5% 10K_0402_5% @ R681 R683 AR36 SM_PWROK R157 1 2 0_0402_5% R185 0_0402_5%
SM_PWROK

2
1K_0402_1% 1K_0402_1% BF17 SM_REXT R434 1 2 499_0402_1% 1
1

1
U41 SM_REXT C227 R180 CLK_DREF_SSC R526 1
BC36 2PM@ 0_0402_5%
2

SM_DRAMRST# 1K_0402_1% CLK_DREF_SSC# R525 1

1 NC TDO 8 2PM@ 0_0402_5%
2 7 0.1U_0402_16V4Z @
GND TCK CLK_DREF_96M 2
3 6 B38 CLK_DREF_96M 16

1
+1.05VS TMS DPLL_REF_CLK CLK_DREF_96M#
4 +3VS TDI 5 DPLL_REF_CLK# A38 CLK_DREF_96M# 16
CLK_DREF_SSC
JTAG CONN DPLL_REF_SSCLK E41
F41 CLK_DREF_SSC#
CLK_DREF_SSC 16 as close as possible to the related balls
DPLL_REF_SSCLK# CLK_DREF_SSC# 16
1

CLK
R684 JTAG@ F43 CLK_MCH_3GPLL
PEG_CLK CLK_MCH_3GPLL 16
0_0402_5% R685 E43 CLK_MCH_3GPLL#
C 22.1K_0402_1% PEG_CLK# CLK_MCH_3GPLL# 16
Strap Pin Table C
2

011 = FSB667
AE41 DMI_ITX_MRX_N0 CFG[2 0] 010 = FSB800
DMI_RXN_0 DMI_ITX_MRX_N0 23
AE37 DMI_ITX_MRX_N1 000 = FSB1067
DMI_RXN_1 DMI_ITX_MRX_N1 23
AE47 DMI_ITX_MRX_N2
DMI_RXN_2 DMI_ITX_MRX_N2 23
AH39 DMI_ITX_MRX_N3 0 = DMI x 2
DMI_RXN_3 DMI_ITX_MRX_N3 23
DMI_ITX_MRX_P0
CFG5 1 = DMI x 4 * (Default)
DMI_RXP_0 AE40 DMI_ITX_MRX_P0 23
MCH_CLKSEL0 T25 AE38 DMI_ITX_MRX_P1 0 = iTPM Host Interface is enabled
16 MCH_CLKSEL0 CFG_0 DMI_RXP_1 DMI_ITX_MRX_P1 23
MCH_CLKSEL1 DMI_ITX_MRX_P2 CFG6
16 MCH_CLKSEL1
MCH_CLKSEL2
R25
P25
CFG_1 DMI_RXP_2 AE48
AH40 DMI_ITX_MRX_P3
DMI_ITX_MRX_P2 23 1 = iTPM Host Interface is Disabled *(Default)
16 MCH_CLKSEL2 CFG_2 DMI_RXP_3 DMI_ITX_MRX_P3 23
P20 CFG_3 DMI_MTX_IRX_N0
0 = Lane Reversal Enable
P24 CFG_4 DMI_TXN_0 AE35 DMI_MTX_IRX_N0 23 CFG9 1 = Normal Operation * (Default)
2 PM_EXTTS#0 MCH_CFG_5 DMI_MTX_IRX_N1

DMI
+3VS 1 C25 CFG_5 DMI_TXN_1 AE43 DMI_MTX_IRX_N1 23
R142 10K_0402_5% MCH_CFG_6 N24 AE46 DMI_MTX_IRX_N2 0 = PCIe Loopback Enable
CFG_6 DMI_TXN_2 DMI_MTX_IRX_N2 23
1 2 PM_EXTTS#1 MCH_CFG_7 M24 CFG_7 CFG DMI_TXN_3 AH42 DMI_MTX_IRX_N3
DMI_MTX_IRX_N3 23 CFG10 1 = Disable * (Default)
R145 10K_0402_5% E21 CFG_8
1 2 MCH_CLKREQ# MCH_CFG_9 C23 CFG_9 DMI_TXP_0 AD35 DMI_MTX_IRX_P0
DMI_MTX_IRX_P0 23 01 = All Z Mode Enabled
R151 10K_0402_5% MCH_CFG_10 C24 AE44 DMI_MTX_IRX_P1 CFG[13 12] 00 = Reserved
CFG_10 DMI_TXP_1 DMI_MTX_IRX_P1 23
N21 AF46 DMI_MTX_IRX_P2 10 = XOR Mode Enabled
CFG_11 DMI_TXP_2 DMI_MTX_IRX_P2 23
Use VGATE for GMCH_PWROK MCH_CFG_12 P21 AH43 DMI_MTX_IRX_P3 11 = Normal Operation * (Default)
CFG_12 DMI_TXP_3 DMI_MTX_IRX_P3 23
MCH_CFG_13 T21
VGATE GMCH_PWROK CFG_13
16,23,46 VGATE 1
R182
2
@ 0_0402_5%
R20 CFG_14 0 = Dynamic ODT Disabled
ICH_PWROK 1 MCH_CFG_16
M20 CFG_15 CFG16 1 = Dynamic ODT Enabled * (Default)
23 ICH_PWROK 2 L21 CFG_16
R183 0_0402_5% 0 = Normal Operation
H21 CFG_17 *(Default)
P29 CFG19 1 = DMI Lane Reversal Enable
GRAPHICS VID

MCH_CFG_19 CFG_18
R28 CFG_19
MCH_CFG_20 T28 B33 0 = Only PCIE or SDVO is operational.
CFG_20 GFX_VID_0
GFX_VID_1 B32 CFG20 * (Default)
G33
B GFX_VID_2
F33 (PCIE/SDVO select) 1 = PCIE/SDVO are operating simu. B
R109 1 PM_SYNC#_R GFX_VID_3
23 PM_SYNC# 2 0_0402_5% R29 PM_SYNC# GFX_VID_4 E33
R94 1 2 0_0402_5% PM_DPRSTP#_R 0 = No SDVO Card Present
5,22,46 H_DPRSTP#
PM_EXTTS#0
B7 PM_DPRSTP# * (Default)
14 PM_EXTTS#0 N33 PM_EXT_TS#_0 SDVO CTRLDATA 1 = SDVO Card Present
PM

15 PM_EXTTS#1 PM_EXTTS#1 P32

GMCH_PWROK PM_EXT_TS#_1
AT40 PWROK GFX_VR_EN C34 0 = LFP Disable * (Default)
21,23,26,27,31 PLT_RST# R98 1 2 100_0402_5% MCH_RSTIN# AT11 RSTIN# L DDC DATA 1 = LFP Card Present PCIE disable
R112 1 2 0_0402_5% THERMTRIP#_R T20 +1.05VS
4,22 H_THERMTRIP# THERMTRIP#
R107 1 0_0402_5% DPRSLPVR_R 0 = Digital DisplayPort Disable
23,46 PM_DPRSLPVR 2 R32 DPRSLPVR * (Default)
1 = Digital DisplayPort Device Present
DDPC CTRLDATA

2
BG48 AH37 R153
NC_1 CL_CLK CL_CLK0 23
BF48 AH36 1K_0402_1% JALA0 (MCH Enable Strap for iTPM)
NC_2 CL_DATA CL_DATA0 23
ME

BD48 AN36 ICH_PWROK

+3VS NC_3 CL_PWROK MCH_CFG_5
BC48 AJ35 CL_RST#0 23 2 1

1
NC_4 CL_RST# CL_VREF R134 @ 2.21K_0402_1%
BH47 NC_5 CL_VREF AH34
BG47 MCH_CFG_6 2 1
NC_6
1

2
+3VS BE47 R113 MAIN@ 2.21K_0402_1%
R241 NC_7 C210 1 R154 MCH_CFG_7
BH46 NC_8 DDPC_CTRLCLK N28 2 1
NC

1K_0402_5% BF46 M28 511_0402_1% R118 @ 2.21K_0402_1%

NC_9 DDPC_CTRLDATA
1

+1.05VS BG45 G36 SDVO_SCLK MCH_CFG_9 2 1

NC_10 SDVO_CTRLCLK SDVO_SCLK 17
R231 BH44 E36 SDVO_SDATA 0.1U_0402_16V4Z R127 @ 2.21K_0402_1%
SDVO_SDATA 17
2

1
1K_0402_5% NC_11 SDVO_CTRLDATA MCH_CLKREQ# 2 MCH_CFG_10
MCH_TSATN_EC# 31 BH43 NC_12 CLKREQ# K36 MCH_CLKREQ# 16 2 1
1

MISC

BH6 H36 MCH_ICH_SYNC# 23 R123 @ 2.21K_0402_1%

NC_13 ICH_SYNC#
1

R429 C BH5 MCH_CFG_12 2 1

2

54.9_0402_1% Q25 NC_14 R115 @ 2.21K_0402_1%

2 BG4 NC_15
B MMBT3904_SOT23-3 BH3 B12 MCH_TSATN# MCH_CFG_13 2 1
R425 NC_16 TSATN#
1

C E BF3 R116 @ 2.21K_0402_1%

2

MCH_TSATN# Q24 NC_17 MCH_CFG_16

1 2 2 BH2 NC_18 2 1
B MMBT3904_SOT23-3 BG2 R114 @ 2.21K_0402_1%
330_0402_5% E NC_19 HDA_BITCLK_MCH
BE2 B28 HDA_BITCLK_MCH 22
3

NC_20 HDA_BCLK HDA_RST_MCH#

BG1 NC_21 HDA_RST# B30 HDA_RST_MCH# 22
A HDA_SDIN2_MCH A
BF1 NC_22 HDA_SDI B29 1 GM@ 2 HDA_SDIN2 22
BD1 C29 HDA_SDOUT_MCH HDA_SDOUT_MCH 22 R126 33_0402_5% MCH_CFG_19 2 1 +3VS
NC_23 HDA_SDO HDA_SYNC_MCH R121 @ 4.02K_0402_1%
BC1 A28
HDA

NC_24 HDA_SYNC HDA_SYNC_MCH 22

F1 MCH_CFG_20 2 1
NC_25 R120 @ 4.02K_0402_1%
A47 NC_26 Notice: Please check HDA power rail to select HDA controller.
CANTIGA ES_FCBGA1329

Pre-MP CANTIGA GM: SA00002JTB0

UMAGM@ Security Classification Compal Secret Data Compal Electronics, Inc.
DVT CANTIGA GM: SA00001P930 Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title
(S IC AC82GM45 SLB94 B3 FCBGA1329 GM ABO!)
(S IC EB88CTGM QR32 B0 FCBGA 1329 MCH GM)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDEN IAL
SCHEMATIC MB A4221
PVT2 CANTIGA GM: SA00002JT50 PVT CANTIGA GM: SA00002JT10 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401552 C
(S IC AC88CTGM QU36 B3 FCBGA 1329 GMCH GM) (S IC AC88CTGM QT62 B2 FCBGA 1329 GMCH GM) MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date Friday, May 16, 2008 Sheet 8 of 50
5 3 2 1
 5 4 3 2 1

DDRA_SDQ[0..63] DDRB_SDQ[0..63]
14 DDRA_SDQ[0..63] 15 DDRB_SDQ[0..63]
DDRA_SDM[0..7] DDRB_SDM[0..7]
14 DDRA_SDM[0..7] 15 DDRB_SDM[0..7]

D DDRA_SMA[0..14] DDRB_SMA[0..14] D
14 DDRA_SMA[0..14] 15 DDRB_SMA[0..14]

U30D U30E
DDRA_SDQ0 AJ38 BD21 DDRB_SDQ0 AK47 BC16
SA_DQ_0 SA_BS_0 DDRA_SBS0# 14 SB_DQ_0 SB_BS_0 DDRB_SBS0# 15
DDRA_SDQ1 AJ41 BG18 DDRB_SDQ1 AH46 BB17
SA_DQ_1 SA_BS_1 DDRA_SBS1# 14 SB_DQ_1 SB_BS_1 DDRB_SBS1# 15
DDRA_SDQ2 AN38 AT25 DDRB_SDQ2 AP47 BB33
SA_DQ_2 SA_BS_2 DDRA_SBS2# 14 SB_DQ_2 SB_BS_2 DDRB_SBS2# 15
DDRA_SDQ3 AM38 DDRB_SDQ3 AP46
DDRA_SDQ4 SA_DQ_3 DDRB_SDQ4 SB_DQ_3
AJ36 SA_DQ_4 SA_RAS# BB20 DDRA_SRAS# 14 AJ46 SB_DQ_4
DDRA_SDQ5 AJ40 BD20 DDRB_SDQ5 AJ48 AU17
SA_DQ_5 SA_CAS# DDRA_SCAS# 14 SB_DQ_5 SB_RAS# DDRB_SRAS# 15
DDRA_SDQ6 AM44 AY20 DDRB_SDQ6 AM48 BG16
SA_DQ_6 SA_WE# DDRA_SWE# 14 SB_DQ_6 SB_CAS# DDRB_SCAS# 15
DDRA_SDQ7 AM42 DDRB_SDQ7 AP48 BF14
SA_DQ_7 SB_DQ_7 SB_WE# DDRB_SWE# 15
DDRA_SDQ8 AN43 DDRB_SDQ8 AU47
DDRA_SDQ9 SA_DQ_8 DDRB_SDQ9 SB_DQ_8
AN44 SA_DQ_9 AU46 SB_DQ_9
DDRA_SDQ10 AU40 DDRB_SDQ10 BA48
DDRA_SDQ11 SA_DQ_10 DDRB_SDQ11 SB_DQ_10
AT38 SA_DQ_11 AY48 SB_DQ_11
DDRA_SDQ12 AN41 DDRB_SDQ12 AT47
DDRA_SDQ13 SA_DQ_12 DDRA_SDM0 DDRB_SDQ13 SB_DQ_12
AN39 SA_DQ_13 SA_DM_0 AM37 AR47 SB_DQ_13
DDRA_SDQ14 AU44 AT41 DDRA_SDM1 DDRB_SDQ14 BA47
DDRA_SDQ15 SA_DQ_14 SA_DM_1 DDRA_SDM2 DDRB_SDQ15 SB_DQ_14 DDRB_SDM0
AU42 SA_DQ_15 SA_DM_2 AY41 BC47 SB_DQ_15 SB_DM_0 AM47
DDRA_SDQ16 AV39 AU39 DDRA_SDM3 DDRB_SDQ16 BC46 AY47 DDRB_SDM1
DDRA_SDQ17 SA_DQ_16 SA_DM_3 DDRA_SDM4 DDRB_SDQ17 SB_DQ_16 SB_DM_1 DDRB_SDM2
AY44 SA_DQ_17 SA_DM_4 BB12 BC44 SB_DQ_17 SB_DM_2 BD40
DDRA_SDQ18 BA40 AY6 DDRA_SDM5 DDRB_SDQ18 BG43 BF35 DDRB_SDM3
C DDRA_SDQ19 SA_DQ_18 SA_DM_5 DDRA_SDM6 DDRB_SDQ19 SB_DQ_18 SB_DM_3 DDRB_SDM4 C
BD43 SA_DQ_19 SA_DM_6 AT7 BF43 SB_DQ_19 SB_DM_4 BG11
DDRA_SDQ20 AV41 AJ5 DDRA_SDM7 DDRB_SDQ20 BE45 BA3 DDRB_SDM5
DDRA_SDQ21 SA_DQ_20 SA_DM_7 DDRB_SDQ21 SB_DQ_20 SB_DM_5 DDRB_SDM6
AY43 BC41 AP1

B
SA_DQ_21 SB_DQ_21 SB_DM_6
A

DDRA_SDQ22 BB41 DDRB_SDQ22 BF40 AK2 DDRB_SDM7

DDRA_SDQ23 SA_DQ_22 DDRA_SDQS0 DDRB_SDQ23 SB_DQ_22 SB_DM_7
BC40 SA_DQ_23 SA_DQS_0 AJ44 DDRA_SDQS0 14 BF41 SB_DQ_23
DDRA_SDQ24 AY37 AT44 DDRA_SDQS1 DDRB_SDQ24 BG38
SA_DQ_24 SA_DQS_1 DDRA_SDQS1 14 SB_DQ_24
DDRA_SDQ25 BD38 BA43 DDRA_SDQS2 DDRB_SDQ25 BF38 AL47 DDRB_SDQS0
SA_DQ_25 SA_DQS_2 DDRA_SDQS2 14 SB_DQ_25 SB_DQS_0 DDRB_SDQS0 15

MEMORY
DDRA_SDQ26 DDRA_SDQS3 DDRB_SDQ26 DDRB_SDQS1
MEMORY

AV37 SA_DQ_26 SA_DQS_3 BC37 DDRA_SDQS3 14 BH35 SB_DQ_26 SB_DQS_1 AV48 DDRB_SDQS1 15
DDRA_SDQ27 AT36 AW12 DDRA_SDQS4 DDRB_SDQ27 BG35 BG41 DDRB_SDQS2
SA_DQ_27 SA_DQS_4 DDRA_SDQS4 14 SB_DQ_27 SB_DQS_2 DDRB_SDQS2 15
DDRA_SDQ28 AY38 BC8 DDRA_SDQS5 DDRB_SDQ28 BH40 BG37 DDRB_SDQS3
SA_DQ_28 SA_DQS_5 DDRA_SDQS5 14 SB_DQ_28 SB_DQS_3 DDRB_SDQS3 15
DDRA_SDQ29 BB38 AU8 DDRA_SDQS6 DDRB_SDQ29 BG39 BH9 DDRB_SDQS4
SA_DQ_29 SA_DQS_6 DDRA_SDQS6 14 SB_DQ_29 SB_DQS_4 DDRB_SDQS4 15
DDRA_SDQ30 AV36 AM7 DDRA_SDQS7 DDRB_SDQ30 BG34 BB2 DDRB_SDQS5
SA_DQ_30 SA_DQS_7 DDRA_SDQS7 14 SB_DQ_30 SB_DQS_5 DDRB_SDQS5 15
DDRA_SDQ31 AW36 DDRB_SDQ31 BH34 AU1 DDRB_SDQS6
SA_DQ_31 SB_DQ_31 SB_DQS_6 DDRB_SDQS6 15
DDRA_SDQ32 BD13 DDRB_SDQ32 BH14 AN6 DDRB_SDQS7
SA_DQ_32 SB_DQ_32 SB_DQS_7 DDRB_SDQS7 15
DDRA_SDQ33 AU11 AJ43 DDRA_SDQS0# DDRB_SDQ33 BG12
SA_DQ_33 SA_DQS#_0 DDRA_SDQS0# 14 SB_DQ_33
DDRA_SDQ34 BC11 AT43 DDRA_SDQS1# DDRB_SDQ34 BH11
SA_DQ_34 SA_DQS#_1 DDRA_SDQS1# 14 SB_DQ_34
DDRA_SDQ35 BA12 BA44 DDRA_SDQS2# DDRB_SDQ35 BG8 AL46 DDRB_SDQS0#
SA_DQ_35 SA_DQS#_2 DDRA_SDQS2# 14 SB_DQ_35 SB_DQS#_0 DDRB_SDQS0# 15

SYSTEM
DDRA_SDQ36
SYSTEM

AU13 BD37 DDRA_SDQS3# DDRB_SDQ36 BH12 AV47 DDRB_SDQS1#

SA_DQ_36 SA_DQS#_3 DDRA_SDQS3# 14 SB_DQ_36 SB_DQS#_1 DDRB_SDQS1# 15
DDRA_SDQ37 AV13 AY12 DDRA_SDQS4# DDRB_SDQ37 BF11 BH41 DDRB_SDQS2#
SA_DQ_37 SA_DQS#_4 DDRA_SDQS4# 14 SB_DQ_37 SB_DQS#_2 DDRB_SDQS2# 15
DDRA_SDQ38 BD12 BD8 DDRA_SDQS5# DDRB_SDQ38 BF8 BH37 DDRB_SDQS3#
SA_DQ_38 SA_DQS#_5 DDRA_SDQS5# 14 SB_DQ_38 SB_DQS#_3 DDRB_SDQS3# 15
DDRA_SDQ39 BC12 AU9 DDRA_SDQS6# DDRB_SDQ39 BG7 BG9 DDRB_SDQS4#
SA_DQ_39 SA_DQS#_6 DDRA_SDQS6# 14 SB_DQ_39 SB_DQS#_4 DDRB_SDQS4# 15
DDRA_SDQ40 BB9 AM8 DDRA_SDQS7# DDRB_SDQ40 BC5 BC2 DDRB_SDQS5#
SA_DQ_40 SA_DQS#_7 DDRA_SDQS7# 14 SB_DQ_40 SB_DQS#_5 DDRB_SDQS5# 15
DDRA_SDQ41 BA9 DDRB_SDQ41 BC6 AT2 DDRB_SDQS6#
SA_DQ_41 SB_DQ_41 SB_DQS#_6 DDRB_SDQS6# 15
DDRA_SDQ42 AU10 DDRB_SDQ42 AY3 AN5 DDRB_SDQS7#
SA_DQ_42 SB_DQ_42 SB_DQS#_7 DDRB_SDQS7# 15
DDRA_SDQ43 AV9 DDRB_SDQ43 AY1
DDRA_SDQ44 SA_DQ_43 DDRA_SMA0 DDRB_SDQ44 SB_DQ_43
BA11 SA_DQ_44 SA_MA_0 BA21 BF6 SB_DQ_44
DDRA_SDQ45 BD9 BC24 DDRA_SMA1 DDRB_SDQ45 BF5 AV17 DDRB_SMA0

DDR
SA_DQ_45 SA_MA_1 SB_DQ_45 SB_MA_0
DDR

DDRA_SDQ46 AY8 BG24 DDRA_SMA2 DDRB_SDQ46 BA1 BA25 DDRB_SMA1

DDRA_SDQ47 SA_DQ_46 SA_MA_2 DDRA_SMA3 DDRB_SDQ47 SB_DQ_46 SB_MA_1 DDRB_SMA2
BA6 SA_DQ_47 SA_MA_3 BH24 BD3 SB_DQ_47 SB_MA_2 BC25
B DDRA_SDQ48 DDRA_SMA4 DDRB_SDQ48 DDRB_SMA3 B
AV5 SA_DQ_48 SA_MA_4 BG25 AV2 SB_DQ_48 SB_MA_3 AU25
DDRA_SDQ49 AV7 BA24 DDRA_SMA5 DDRB_SDQ49 AU3 AW25 DDRB_SMA4
DDRA_SDQ50 SA_DQ_49 SA_MA_5 DDRA_SMA6 DDRB_SDQ50 SB_DQ_49 SB_MA_4 DDRB_SMA5
AT9 SA_DQ_50 SA_MA_6 BD24 AR3 SB_DQ_50 SB_MA_5 BB28
DDRA_SDQ51 AN8 BG27 DDRA_SMA7 DDRB_SDQ51 AN2 AU28 DDRB_SMA6
DDRA_SDQ52 SA_DQ_51 SA_MA_7 DDRA_SMA8 DDRB_SDQ52 SB_DQ_51 SB_MA_6 DDRB_SMA7
AU5 SA_DQ_52 SA_MA_8 BF25 AY2 SB_DQ_52 SB_MA_7 AW28
DDRA_SDQ53 AU6 AW24 DDRA_SMA9 DDRB_SDQ53 AV1 AT33 DDRB_SMA8
DDRA_SDQ54 SA_DQ_53 SA_MA_9 DDRA_SMA10 DDRB_SDQ54 SB_DQ_53 SB_MA_8 DDRB_SMA9
AT5 SA_DQ_54 SA_MA_10 BC21 AP3 SB_DQ_54 SB_MA_9 BD33
DDRA_SDQ55 AN10 BG26 DDRA_SMA11 DDRB_SDQ55 AR1 BB16 DDRB_SMA10
DDRA_SDQ56 SA_DQ_55 SA_MA_11 DDRA_SMA12 DDRB_SDQ56 SB_DQ_55 SB_MA_10 DDRB_SMA11
AM11 SA_DQ_56 SA_MA_12 BH26 AL1 SB_DQ_56 SB_MA_11 AW33
DDRA_SDQ57 AM5 BH17 DDRA_SMA13 DDRB_SDQ57 AL2 AY33 DDRB_SMA12
DDRA_SDQ58 SA_DQ_57 SA_MA_13 DDRA_SMA14 DDRB_SDQ58 SB_DQ_57 SB_MA_12 DDRB_SMA13
AJ9 SA_DQ_58 SA_MA_14 AY25 AJ1 SB_DQ_58 SB_MA_13 BH15
DDRA_SDQ59 AJ8 DDRB_SDQ59 AH1 AU33 DDRB_SMA14
DDRA_SDQ60 SA_DQ_59 DDRB_SDQ60 SB_DQ_59 SB_MA_14
AN12 SA_DQ_60 AM2 SB_DQ_60
DDRA_SDQ61 AM13 DDRB_SDQ61 AM3
DDRA_SDQ62 SA_DQ_61 DDRB_SDQ62 SB_DQ_61
AJ11 SA_DQ_62 AH3 SB_DQ_62
DDRA_SDQ63 AJ12 DDRB_SDQ63 AJ3
SA_DQ_63 SB_DQ_63
CANTIGA ES_FCBGA1329 CANTIGA ES_FCBGA1329
UMAGM@ UMAGM@
DVT CANTIGA GM: SA00001P930 Pre-MP CANTIGA GM: SA00002JTB0
(S IC EB88CTGM QR32 B0 FCBGA 1329 MCH GM) (S IC AC82GM45 SLB94 B3 FCBGA1329 GM ABO!)
PVT CANTIGA GM: SA00002JT10
(S IC AC88CTGM QT62 B2 FCBGA 1329 GMCH GM)
PVT2 CANTIGA GM: SA00002JT50
A
(S IC AC88CTGM QU36 B3 FCBGA 1329 GMCH GM) A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT AL
SCHEMATIC MB A4221
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401552
Date: Friday, May 16, 2008 Sheet 9 of 50
5 4 3 2 1
 5 4 3 2 1

U30C

18 DPST_PWM L32 L_BKLT_CTRL

17,31 ENBKL 1 2 LBKLT_EN G32 T37 PEG_COMP 1 2 1.05VS
R141 GM@ 0_0402_5% LCTLA_CLK L_BKLT_EN PEG_COMPI R156 49.9_0402_1%
LCTLB_DATA
M32 L_CTRL_CLK PEG_COMPO T36 10mils
M33 L_CTRL_DATA
18 GMCH_LCD_CLK GMCH_LCD_CLK K33
GMCH_LCD_DATA L_DDC_CLK PCIE_GTX_C_MRX_N0 PCIE_MTX_C_GRX_N[0..15]
D 18 GMCH_LCD_DATA J33 L_DDC_DATA PEG_RX#_0 H44 PCIE_MTX_C_GRX_N[0..15] 17 D
M29 J46 PCIE_GTX_C_MRX_N1
18 GMCH_ENVDD L_VDD_EN PEG_RX#_1 PCIE_MTX_C_GRX_P[0..15]
L44 PCIE_GTX_C_MRX_N2
PEG_RX#_2 PCIE_MTX_C_GRX_P[0..15] 17
1 2 LVDS_IBG C44 L40 PCIE_GTX_C_MRX_N3
R455 GM@ 2.37K_0402_1% LVDS_IBG PEG_RX#_3 PCIE_GTX_C_MRX_N4 PCIE_GTX_C_MRX_N[0..15]
B43 LVDS_VBG PEG_RX#_4 N41 PCIE_GTX_C_MRX_N[0..15] 17
2 1 E37 P48 PCIE_GTX_C_MRX_N5
R579 GM@ LVDS_VREFH PEG_RX#_5 PCIE_GTX_C_MRX_N6 PCIE_GTX_C_MRX_P[0..15]
E38 LVDS_VREFL PEG_RX#_6 N44 PCIE_GTX_C_MRX_P[0..15] 17
0_0402_5% T43 PCIE_GTX_C_MRX_N7
GMCH_TXCLK- PEG_RX#_7 PCIE_GTX_C_MRX_N8
18 GMCH_TXCLK- C41 LVDSA_CLK# PEG_RX#_8 U43
GMCH_TXCLK C40 Y43 PCIE_GTX_C_MRX_N9
18 GMCH_TXCLK LVDSA_CLK PEG_RX#_9
GMCH_TZCLK- B37 Y48 PCIE_GTX_C_MRX_N10
18 GMCH_TZCLK- LVDSB_CLK# PEG_RX#_10
GMCH_TZCLK A37 Y36 PCIE_GTX_C_MRX_N11
18 GMCH_TZCLK LVDSB_CLK PEG_RX#_11

LVDS
AA43 PCIE_GTX_C_MRX_N12
GMCH_TXOUT0- PEG_RX#_12 PCIE_GTX_C_MRX_N13
18 GMCH_TXOUT0- H47 LVDSA_DATA#_0 PEG_RX#_13 AD37
GMCH_TXOUT1- E46 AC47 PCIE_GTX_C_MRX_N14
18 GMCH_TXOUT1- LVDSA_DATA#_1 PEG_RX#_14
GMCH_TXOUT2- G40 AD39 PCIE_GTX_C_MRX_N15
18 GMCH_TXOUT2- LVDSA_DATA#_2 PEG_RX#_15
A40 LVDSA_DATA#_3
H43 PCIE_GTX_C_MRX_P0
GMCH_TXOUT0 PEG_RX_0 PCIE_GTX_C_MRX_P1
18 GMCH_TXOUT0 H48 LVDSA_DATA_0 PEG_RX_1 J44
GMCH_TXOUT1 D45 L43 PCIE_GTX_C_MRX_P2
18 GMCH_TXOUT1 LVDSA_DATA_1 PEG_RX_2

GRAPHICS
GMCH_TXOUT2 F40 L41 PCIE_GTX_C_MRX_P3
18 GMCH_TXOUT2 LVDSA_DATA_2 PEG_RX_3
B40 N40 PCIE_GTX_C_MRX_P4
LVDSA_DATA_3 PEG_RX_4 PCIE_GTX_C_MRX_P5
PEG_RX_5 P47
GMCH_TZOUT0- A41 N43 PCIE_GTX_C_MRX_P6
18 GMCH_TZOUT0- LVDSB_DATA#_0 PEG_RX_6
GMCH_TZOUT1- H38 T42 PCIE_GTX_C_MRX_P7
18 GMCH_TZOUT1- LVDSB_DATA#_1 PEG_RX_7
GMCH_TZOUT2- G37 U42 PCIE_GTX_C_MRX_P8
18 GMCH_TZOUT2- LVDSB_DATA#_2 PEG_RX_8
J37 Y42 PCIE_GTX_C_MRX_P9
LVDSB_DATA#_3 PEG_RX_9 PCIE_GTX_C_MRX_P10
PEG_RX_10 W47
GMCH_TZOUT0 B42 Y37 PCIE_GTX_C_MRX_P11
18 GMCH_TZOUT0 LVDSB_DATA_0 PEG_RX_11
C GMCH_TZOUT1 G38 AA42 PCIE_GTX_C_MRX_P12 C
18 GMCH_TZOUT1 LVDSB_DATA_1 PEG_RX_12
GMCH_TZOUT2 F37 AD36 PCIE_GTX_C_MRX_P13
18 GMCH_TZOUT2 LVDSB_DATA_2 PEG_RX_13
K37 AC48 PCIE_GTX_C_MRX_P14
LVDSB_DATA_3 PEG_RX_14

PCI-EXPRESS
AD40 PCIE_GTX_C_MRX_P15
PEG_RX_15
J41 PCIE_MTX_GRX_N0 C225 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_N0
PEG_TX#_0 PCIE_MTX_GRX_N1 C236 1 0.1U_0402_16V7K PCIE_MTX_C_GRX_N1
PEG_TX#_1 M46 2
GMCH_TV_COMPS F25 M47 PCIE_MTX_GRX_N2 C239 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_N2
GMCH_TV_LUMA TVA_DAC PEG_TX#_2 PCIE_MTX_GRX_N3 C241 1 0.1U_0402_16V7K PCIE_MTX_C_GRX_N3
H25 TVB_DAC PEG_TX#_3 M40 2
GMCH_TV_CRMA K25 M42 PCIE_MTX_GRX_N4 C243 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N4
TVC_DAC PEG_TX#_4 PCIE_MTX_GRX_N5 C246 1
PEG_TX#_5 R48 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N5
2

TV
H24 N38 PCIE_MTX_GRX_N6 C251 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N6
R128 R129 R119 TV_RTN PEG_TX#_6 PCIE_MTX_GRX_N7 C256 1
PEG_TX#_7 T40 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N7
U37 PCIE_MTX_GRX_N8 C257 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N8
GM@ GM@ GM@ PEG_TX#_8 PCIE_MTX_GRX_N9 C267 1
PEG_TX#_9 U40 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N9
75_0402_1% TV_DCONSEL_0 C31 Y40 PCIE_MTX_GRX_N10 C272 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N10
1

75_0402_1% TV_DCONSEL_1 TV_DCONSEL_0 PEG_TX#_10 PCIE_MTX_GRX_N11 C274 1

E32 TV_DCONSEL_1 PEG_TX#_11 AA46 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N11
75_0402_1% AA37 PCIE_MTX_GRX_N12 C266 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N12
PEG_TX#_12 PCIE_MTX_GRX_N13 C258 1
PEG_TX#_13 AA40 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N13
AD43 PCIE_MTX_GRX_N14 C269 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N14
PEG_TX#_14 PCIE_MTX_GRX_N15 C271 1
PEG_TX#_15 AC46 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N15
Change to 0Ohm when use PM chip PCIE_MTX_GRX_P0 C220 0.1U_0402_16V7K PCIE_MTX_C_GRX_P0
19 GMCH_CRT_B E28 CRT_BLUE PEG_TX_0 J42 1 2
2 1 L46 PCIE_MTX_GRX_P1 C233 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_P1
R138 GM@ 150_0402_1% PEG_TX_1 PCIE_MTX_GRX_P2 C238 0.1U_0402_16V7K PCIE_MTX_C_GRX_P2
19 GMCH_CRT_G G28 CRT_GREEN PEG_TX_2 M48 1 2
2 1 M39 PCIE_MTX_GRX_P3 C240 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_P3
PEG_TX_3

VGA
R139 GM@ 150_0402_1% J28 M43 PCIE_MTX_GRX_P4 C242 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P4
19 GMCH_CRT_R CRT_RED PEG_TX_4
2 1 R47 PCIE_MTX_GRX_P5 C244 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P5
R140 GM@ 150_0402_1% PEG_TX_5 PCIE_MTX_GRX_P6 C247
G29 CRT_IRTN PEG_TX_6 N37 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P6
B PCIE_MTX_GRX_P7 C252 1 B
PEG_TX_7 T39 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P7
GMCH_CRT_CLK H32 U36 PCIE_MTX_GRX_P8 C253 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P8
19 GMCH_CRT_CLK CRT_DDC_CLK PEG_TX_8
GMCH_CRT_DATA J32 U39 PCIE_MTX_GRX_P9 C260 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P9
19 GMCH_CRT_DATA CRT_DDC_DATA PEG_TX_9
J29 Y39 PCIE_MTX_GRX_P10 C263 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P10
19 GMCH_CRT_HSYNC CRT_HSYNC PEG_TX_10
2 1 CRT_IREF E29 Y46 PCIE_MTX_GRX_P11 C273 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P11
R131 PM@ 0_0402_5% CRT_TVO_IREF PEG_TX_11 PCIE_MTX_GRX_P12 C262
PEG_TX_12 AA36 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P12
AA39 PCIE_MTX_GRX_P13 C255 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P13
PEG_TX_13 PCIE_MTX_GRX_P14 C268
19 GMCH_CRT_VSYNC L29 CRT_VSYNC PEG_TX_14 AD42 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P14
2 1 AD46 PCIE_MTX_GRX_P15 C270 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P15
3VS R125 PM@ 0_0402_5% PEG_TX_15
2

R143 CANTIGA ES_FCBGA1329

R147 1 GM@ 2 2.2K_0402_5% GMCH_LCD_CLK 1K_0402_1% DVT UMAGM@ Pre-MP
GM@
R146 1 GM@ 2 2.2K_0402_5% GMCH_LCD_DATA CANTIGA GM: SA00001P930 CANTIGA GM: SA00002JTB0
1

R152 1 GM@ 2 10K_0402_5% LCTLB_DATA (S IC EB88CTGM QR32 B0 FCBGA 1329 MCH GM) (S IC AC82GM45 SLB94 B3 FCBGA1329 GM ABO!)
R144 1 GM@ 2 10K_0402_5% LCTLA_CLK

R132 1 GM@
Change to 0Ohm when use PM chip
2 2.2K_0402_5% GMCH_CRT_CLK
PVT
R124 1 GM@ 2 2.2K_0402_5% GMCH_CRT_DATA
CANTIGA GM: SA00002JT10
(S IC AC88CTGM QT62 B2 FCBGA 1329 GMCH GM)

A PVT2 A

R149 GM@ 0_0402_5% TV_DCONSEL_0

CANTIGA GM: SA00002JT50
(S IC AC88CTGM QU36 B3 FCBGA 1329 GMCH GM)
R133 GM@ 0_0402_5% TV_DCONSEL_1

R136 1 2 100K_0402_5% LBKLT_EN Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT AL
SCHEMATIC MB A4221
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401552
Date: Friday, May 16, 2008 Sheet 10 of 50
5 4 3 2 1
 5 3 2 1

U30F
+VGFX_CORE
+1.8V

2600mA VCC_AXG_NTCF_1 W28

AP33 VCC_SM_1 VCC_AXG_NCTF_2 V28
AN33 VCC_SM_2 VCC_AXG_NCTF_3 W26 Place close to the GMCH
BH32 VCC_SM_3 VCC_AXG_NCTF_4 V26
D
BG32 VCC_SM_4 VCC_AXG_NCTF_5 W25
+1.05VS
VCC: 1930.4mA (GMCH), 1210 34mA (MCH) D
BF32 V25
BD32
VCC_SM_5 VCC_AXG_NCTF_6
W24 (270UF*1, 22UF*1, 0.22UF*2, 0.1UF*1)
VCC_SM_6 VCC_AXG_NCTF_7
BC32 VCC_SM_7 VCC_AXG_NCTF_8 V24
BB32 W23 +1.05VS
VCC_SM_8 VCC_AXG_NCTF_9 1

VCC
BA32 V23 1 1 U30G
VCC_SM_9 VCC_AXG_NCTF_10 + C139 C203 C207 C206 C202
AY32 VCC_SM_10 VCC_AXG_NCTF_11 AM21
AW32 VCC_SM_11 VCC_AXG_NCTF_12 AL21 AG34 VCC_1
AV32 AK21 220U_D2_4VM_R15 0.22U_0603_16V7K 0.1U_0402_16V4Z AC34
VCC_SM_12 VCC_AXG_NCTF_13 2 2 2 VCC_2
AU32 VCC_SM_13 VCC_AXG_NCTF_14 W21 AB34 VCC_3
AT32 V21 10U_0805_10V4Z 0.22U_0603_16V7K AA34

SM
VCC_SM_14 VCC_AXG_NCTF_15 VCC_4
AR32 VCC_SM_15 VCC_AXG_NCTF_16 U21 Y34 VCC_5
AP32 AM20 Cavity Capacitors V34

VCC CORE
VCC_SM_16 VCC_AXG_NCTF_17 VCC_6
AN32 VCC_SM_17 VCC_AXG_NCTF_18 AK20 U34 VCC_7
BH31 VCC_SM_18 VCC_AXG_NCTF_19 W20 AM33 VCC_8
BG31 VCC_SM_19 VCC_AXG_NCTF_20 U20 AK33 VCC_9
BF31 VCC_SM_20 VCC_AXG_NCTF_21 AM19 AJ33 VCC_10
BG30 VCC_SM_21 VCC_AXG_NCTF_22 AL19 AG33 VCC_11
BH29 VCC_SM_22 VCC_AXG_NCTF_23 AK19 AF33 VCC_12
BG29 VCC_SM_23 VCC_AXG_NCTF_24 AJ19
BF29 VCC_SM_24 VCC_AXG_NCTF_25 AH19
+VGFX_CORE
VCC_AXG: 6326 84mA
BD29 AG19
BC29
VCC_SM_25 VCC_AXG_NCTF_26
AF19 (330UF*2, 22UF*1, 10UF*1, 1U*1, 0.47U*1, 0.1UF*2) AE33
VCC_SM_26 VCC_AXG_NCTF_27 VCC_13
BB29 VCC_SM_27 VCC_AXG_NCTF_28 AE19 +1.05VS 1 2 AC33 VCC_14
Reference PILLAR_ROCK CRB Rev1.0 BA29 AB19 R103 GM@ 0_1206_5% AA33
VCC_SM_28 VCC_AXG_NCTF_29 C189 C188 C181 1 C183 1 C177 1 C186 1 VCC_15
AY29 VCC_SM_29 VCC_AXG_NCTF_30 AA19 1 2 Y33 VCC_16
GFX NCTF
AW29 Y19 R135 GM@ 0_0805_5% W33
VCC_SM_30 VCC_AXG_NCTF_31 GM@ VCC_17
Pins BA36, BB24, BD16,

POWER
AV29 VCC_SM_31 VCC_AXG_NCTF_32 W19 1 2 V33 VCC_18
BB21, AW16, AW13, AT13 AU29 V19 R137 GM@ 0_0805_5% 0.47U_0603_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z U33
VCC_SM_32 VCC_AXG_NCTF_33 GM@ GM@ 2 2 GM@ 2 2 VCC_19
AT29 U19 AH28
could be left NC for DDR2 VCC_SM_33 VCC_AXG_NCTF_34 R111 1U_0402_6.3V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z VCC_20
board.
AR29 VCC_SM_34 VCC_AXG_NCTF_35 AM17 JALA0 0_0402_5% GM@ GM@
AF28 VCC_21
AP29 VCC_SM_35 VCC_AXG_NCTF_36 AK17 AC28 VCC_22
AH17 PM@ Cavity Capacitors AA28
C VCC_AXG_NCTF_37 VCC_23 C
VCC_AXG_NCTF_38 AG17 AJ26 VCC_24
VCC_AXG_NCTF_39 AF17 AG26 VCC_25
VCC_SM_BA36 BA36 AE17 AE26
VCC_SM_BB24 VCC_SM_36/NC VCC_AXG_NCTF_40 VCC_26
BB24 VCC_SM_37/NC VCC_AXG_NCTF_41 AC17 AC26 VCC_27 +1.05VS
VCC

VCC_SM_BD16 BD16 AB17 AH25

VCC_SM_38/NC VCC_AXG_NCTF_42 VCC_28
BB21 VCC_SM_39/NC VCC_AXG_NCTF_43 Y17 AG25 VCC_29
VCC_SM_AW16 AW16 W17 1 AF25
VCC_SM_40/NC VCC_AXG_NCTF_44 C134 VCC_30
AW13 VCC_SM_41/NC VCC_AXG_NCTF_45 V17 AG24 VCC_31 VCC_NCTF_1 AM32
VCC_SM_AT13 AT13 AM16 + AJ23 AL32
VCC_SM_42/NC VCC_AXG_NCTF_46 VCC_32 VCC_NCTF_2
VCC_AXG_NCTF_47 AL16 AH23 VCC_33 VCC_NCTF_3 AK32
AK16 330U_D2E_2.5VM_R15 AF23 AJ32
POWER

VCC_AXG_NCTF_48 GM@ 2 VCC_34 VCC_NCTF_4

VCC_AXG_NCTF_49 AJ16 T32 VCC_35 VCC_NCTF_5 AH32
+VGFX_CORE AH16 AG32
VCC_AXG_NCTF_50 VCC_NCTF_6
VCC_AXG_NCTF_51 AG16 VCC_NCTF_7 AE32
VCC_AXG_NCTF_52 AF16 Place close to the GMCH VCC_NCTF_8 AC32
Y26 VCC_AXG_1 VCC_AXG_NCTF_53 AE16 VCC_NCTF_9 AA32
AE25 VCC_AXG_2 VCC_AXG_NCTF_54 AC16 VCC_NCTF_10 Y32
AB25 VCC_AXG_3 VCC_AXG_NCTF_55 AB16 VCC_NCTF_11 W32
AA25 VCC_AXG_4 VCC_AXG_NCTF_56 AA16 VCC_NCTF_12 U32
AE24 VCC_AXG_5 VCC_AXG_NCTF_57 Y16 VCC_NCTF_13 AM30
AC24 VCC_AXG_6 VCC_AXG_NCTF_58 W16 VCC_SM: 2600mA VCC_NCTF_14 AL30
AA24 V16 AK30
Y24
VCC_AXG_7 VCC_AXG_NCTF_59
U16 +1.8V (330UF*1, 22UF*2, 0.1UF*1) VCC_NCTF_15
AH30
VCC_AXG_8 VCC_AXG_NCTF_60 VCC_NCTF_16
AE23 VCC_AXG_9 VCC_NCTF_17 AG30
AC23 VCC_AXG_10 VCC_NCTF_18 AF30
AB23 VCC_AXG_11 1 VCC_NCTF_19 AE30
AA23 C157 1 1 1 AC30

NCTF
VCC_AXG_12 + C201 C211 C208 VCC_NCTF_20
AJ21 VCC_AXG_13 VCC_NCTF_21 AB30
AG21 VCC_AXG_14 VCC_NCTF_22 AA30
AE21 330U_D2E_2.5VM_R15 10U_0805_10V4Z Y30
VCC_AXG_15 2 2 2 2 VCC_NCTF_23
AC21 VCC_AXG_16 VCC_NCTF_24 W30
AA21 10U_0805_10V4Z 0.1U_0402_16V4Z V30
B VCC_AXG_17 VCC_NCTF_25 B
Y21 VCC_AXG_18 VCC_NCTF_26 U30
VCC

VCC
AH20 VCC_AXG_19 Place on the edge VCC_NCTF_27 AL29
AF20 VCC_AXG_20 VCC_NCTF_28 AK29
AE20 VCC_AXG_21 VCC_NCTF_29 AJ29
AC20 VCC_AXG_22 Reference PILLAR_ROCK CRB Rev1.0 VCC_NCTF_30 AH29
AB20 VCC_AXG_23 VCC_NCTF_31 AG29
AA20 AE29
GFX

VCC_AXG_24 VCC_SM_BA36 VCC_NCTF_32

T17 VCC_AXG_25 VCC_NCTF_33 AC29
T16 VCC_SM_BB24 AA29
VCC_AXG_26 VCC_SM_BD16 VCC_NCTF_34
AM15 VCC_AXG_27 VCC_NCTF_35 Y29
AL15 VCC_SM_AW16 W29
VCC_AXG_28 VCC_SM_AT13 VCC_NCTF_36
AE15 VCC_AXG_29 VCC_NCTF_37 V29
AJ15 VCC_AXG_30 VCC_NCTF_38 AL28
AH15 VCC_AXG_31 1 1 1 1 1 VCC_NCTF_39 AK28
AG15 C173 C174 C176 C192 C213 AL26
VCC_AXG_32 @ @ @ @ @ VCC_NCTF_40
AF15 VCC_AXG_33 VCC_NCTF_41 AK26
AB15 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K AK25
VCC_AXG_34 2 2 2 2 2 VCC_NCTF_42
AA15 VCC_AXG_35 VCC_NCTF_43 AK24
Y15 0.1U_0402_16V7K 0.1U_0402_16V7K AK23
VCC_AXG_36 VCC_NCTF_44
V15 VCC_AXG_37
U15 VCC_AXG_38
AN14 VCC_AXG_39
AM14 VCC_AXG_40
U14 AV44 VCCSM_LF1
VCC SM LF

VCC_AXG_41 VCC_SM_LF1 VCCSM_LF2

T14 VCC_AXG_42 VCC_SM_LF2 BA37
AM40 VCCSM_LF3
VCC_SM_LF3 VCCSM_LF4
VCC_SM_LF4 AV21
AY5 VCCSM_LF5
@ VCC_AXG_SENSE VCC_SM_LF5 VCCSM_LF6 CANTIGA ES_FCBGA1329
T9 PAD AJ14 VCC_AXG_SENSE VCC_SM_LF6 AM10
PAD @ VSS_AXG_SENSE AH14 BB13 VCCSM_LF7 UMAGM@
T10 VSS_AXG_SENSE VCC_SM_LF7
1 1 1 1 1 1 1
C169 C168 C166 C185 C214 C212 C226
A A
PVT2 Pre-MP
0.1U_0402_16V7K 0.22U_0402_6.3V6K 0.47U_0603_16V4Z 1U_0402_6.3V4Z
2 2 2 2 2 2 2
CANTIGA GM: SA00002JT50 CANTIGA GM: SA00002JTB0
0.1U_0402_16V7K 0.22U_0402_6.3V6K 1U_0402_6.3V4Z
CANTIGA ES_FCBGA1329 (S IC AC88CTGM QU36 B3 FCBGA 1329 GMCH GM) (S IC AC82GM45 SLB94 B3 FCBGA1329 GM ABO!)
UMAGM@ DVT
CANTIGA GM: SA00001P930 Security Classification Compal Secret Data Compal Electronics, Inc.
(S IC EB88CTGM QR32 B0 FCBGA 1329 MCH GM) Issued Date 2007/09/20 2008/09/20 Title
Deciphered Date
PVT SCHEMATIC MB A4221
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDEN IAL
CANTIGA GM: SA00002JT10 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C
(S IC AC88CTGM QT62 B2 FCBGA 1329 GMCH GM) DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401552
Date Friday, May 16, 2008 Sheet 11 of 50
5 3 2 1
 5 3 2 1

+1.05VS_HPLL
+1.05VS_DPLLA
+1.05VS L32 1 2
MBK1608121YZF_0603 1 1 +1.05VS 1 2

1
VCCA_HPLL: 24mA C429 C436 L42 1 1 U30H VTT: 852mA
0_1210_5% C229 R596 +1.05VS
(4.7UF*1, 0.1UF*1) 4.7U_0805_10V4Z GM@ C499 + GM@ PM@ (270UF*1, 4.7UF*2, 2.2UF*1, 0.47UF*1)
2 2 852mA
Please check Power GM@ 73mA U13
0.1U_0402_16V4Z 220U_D2_4VM_R15 2 0_0402_5% +3VS_CRTDAC VTT_1
source if want VCCA_DPLLA B27 T13 1

2
2 0.1U_0402_16V4Z VCCA_CRT_DAC_1 VTT_2
Please che k Power VCCA_DPLLB: 64.8mA A26 VCCA_CRT_DAC_2 VTT_3 U12 1 1 1 1
support IAMT T12 C113 + C143 C132 C109 C119
+1.05VS_MPLL source if w nt (220UF*1, 0.1UF*1) VTT_4
VTT_5 U11
120Ohm@100MHz support IAMT 2.69mA T11 220U_D2 4VM_R15 4.7U_0805_10V4Z 0.47U_0603_16V4Z
+1.05VS_DPLLB VTT_6 2 2 2 2 2

CRT
D L13 1 D
2 +3VS_DACBG A25 VCCA_DAC_BG VTT_7 U10
MBK1608121YZF_0603 1 T10 4.7U_0805_10V4Z 2.2U_0805_10V6K
VTT_8

1
VCCA_MPLL: 139.2mA C156 1 2 B25 U9
VSSA_DAC_BG VTT_9

1
R410 L18 1 1 T9
(22UF*1, 0.1UF*1) 0.5_0603_1% 0_1210_5% C232 R597 VTT_10
U8
2 GM@ GM@ PM@ VTT_11
64.8mA VTT_12 T8

VTT
0.1U_0402_16V4Z C280 +1.05VS_DPLLA F47 U7

2
2
10U_0805_10V4Z 2 0_0402_5% VCCA_DPLLA VTT_13
1 T7

2
GM@ 0.1U_0402_16V4Z VTT_14
C432
DVT +1.05VS_DPLLB L48 VCCA_DPLLB VTT_15 U6
VTT_16 T6
24mA

PLL
22U_0805_6.3V6M +1.05VS_HPLL AD1 VCCA_HPLL VTT_17 U5
2 R179 +1.8V_TX_LVDS VTT_18 T5
@ 0_0402_5% 1 AE1 139.2mA V3
+1.05VS_MPLL VCCA_MPLL VTT_19
+3VS 1 2 C231 U3
GM@ VTT_20
+VCCA_PEG_BG
VCCA_LVDS: 13.2mA 13.2mA VTT_21 V2

A PEG A LVDS
R184 1000P_0402_50V7K J48 U2
0_0402_5% 2 (1000PF*1) VCCA_LVDS VTT_22
T2
VTT_23
+1.5VS 1 2 J47 VSSA_LVDS VTT_24 V1
VCCA_CRT_DAC: 73mA (0.1UF*1, 0.01UF*1) +3VS_CRTDAC U1
1 VTT_25
Please check Power C234 VCCA_PEG_BG: 0.414mA 0.414mA Please check Power
+3VS 1 2 source if want (0.1UF*1) AD48 VCCA_PEG_BG source if want
L41 GM@ 0.1U_0402_16V4Z VCC_AXF: 321.35mA
1

MBK1608221YZF_0603 1 1
support IAMT 2 +1.05VS_AXF support IAMT
C487 C486 R443 (10UF*1, 1UF*1)
1 50mA
GM@ GM@ 0_0402_5% No CIS Symbol AA48 1 2 +1.05VS
C597 + 0.1U_0402_16V4Z PM@ L17 1 +1.05VS_PEGPLL VCCA_PEG_PLL R435
+1.05VS 2
GM@ 2 2 MBK1608221YZF_0603 0_0603_5%
1 VCCA_PEG_PLL: 50mA 1 1
2

220U_D2 4VM_R15 0.01U_0402_16V7K 2 1 1 2 C507 C471 C470

2 C245 R181 (0.1UF*1) @
Close to Ball A26, B27 10U_0805_6.3V6M 1_0402_1% 0.1U_0402_16V4Z 480mA 10U_0805_6.3V6M
2
AR20 VCCA_SM_1
POWER 2 2
+1.05VS_A_SM 1U_0402_6.3V4Z
C
DVT AP20 VCCA_SM_2 C
VCCA_SM: AN20 VCCA_SM_3
+1.05VS 1 2 (22UF*2, 4.7UF*1, 1UF*1) AR17 VCCA_SM_4 +1.8V_SM_CK
VCC_SM_CK: 119.85mA

A SM
1 R122 1 1 1 AP17
0_0805_5% C182 C175 C184 AN17
VCCA_SM_5
B22
(10UF*1, 0.1UF*1) 1uH 30%
VCCA_SM_6 VCC_AXF_1

AXF
Please check Power C431 + AT16 B21 1 2
VCCA_SM_7 VCC_AXF_2 +1.8V
@ 4.7U_0805_10V4Z AR16 A21 L37
source if want 220U_D2 4VM_R15 2 2 2 VCCA_SM_8 VCC_AXF_3 MBK1608121YZF_0603
AP16 VCCA_SM_9 1
support IAMT 2 22U_0805_6.3V6M 1U_0402_6.3V4Z C466
DVT 0.1U_0402_16V4Z
1
R436
2 1
C461
2
P ease check Power 2
BF21 1_0402_1% 10U_0603_6.3V6M
source if want VCC_SM_CK_1

SM CK
VCCA_DAC_BG: 2.6833333mA support IAMT +1.05VS_A_SM_CK VCC_SM_CK_2 BH20
(0.1UF*1, 0.01UF*1) +3VS_DACBG
VCCA_SM_CK: 24mA VCC_SM_CK_3 BG20
(22UF*1, 2.2UF*1, 0.1UF*1) 24mA VCC_SM_CK_4 BF20
+1.8V_TX_LVDS DVT(JALA0)
+1.05VS 1 2 AP28 VCCA_SM_CK_1 +1.8V_TX_LVDS: 118.8mA
1 2 R130 1 1 1 AN28 0.1uH 20%
+3VS
L40 GM@ 0_0603_5% C205 C200 C190 AP25
VCCA_SM_CK_2 (22UF*1, 1000PF*1) 2 1
VCCA_SM_CK_3 +1.8V
1

MBK1608221YZF_0603 1 1 1 @ AN25 118.8mA 1 1 R198

VCCA_SM_CK_4

1
C482 C481 C480 R440 2.2U_0805_10V6K 0.1U_0402_16V4Z AN24 K47 C278 C282 0_0603_5%
2 2 2 VCCA_SM_CK_5 VCC_TX_LVDS

A CK
GM@ GM@ @ 0_0402_5% AM28 R193 GM@ GM@ GM@
0.1U_0402_16V4Z 10U_0805_6.3V6M PM@ 22U_0805_6.3V6M VCCA_SM_CK_NCTF_1 PM@ 1000P_0402_50V7K
AM26 VCCA_SM_CK_NCTF_2
2 2 2 0_0402_5% 2 2 10U_0805_10V4Z
AM25 105.3mA VCC_HV: 105.3mA
2

0.01U_0402_16V7K VCCA_SM_CK_NCTF_3
NO_STUFF AL25 C35 +3VS

2
VCCA_SM_CK_NCTF_4 VCC_HV_1
AM24 VCCA_SM_CK_NCTF_5 VCC_HV_2 B35 1

HV
Close to Ball A25 AL24 A35 C209
VCCA_SM_CK_NCTF_6 VCC_HV_3
AM23 VCCA_SM_CK_NCTF_7 Please check Power
AL23 0.1U_0402_16V4Z
VCCA_SM_CK_NCTF_8 2 source if want
1782mA support IAMT
VCC_PEG_1 V48 +1.05VS_PEG: 1782mA +1.05VS_PEG
VCC_PEG_2 U48 (220UF*1, 22UF*1, 4.7UF*1)

PEG
VCCA_TV_DAC: 40mA (0.1UF*1, VCC_PEG_3 V47 1 2 +1.05VS
87.79mA U47 1 R194
B 0.01UF*1 for each DAC) B24
VCC_PEG_4
U46 0_0805_5% B
+3VS_TVDAC VCCA_TV_DAC_1 VCC_PEG_5 1
+3VS_TVDAC A24 C248 + C261
VCCA_TV_DAC_2

TV
+3VS L38 1 2 VCCD_HDA: 50mA 10U_0805_10V4Z 220U_D2_4VM_R15
MBK1608221YZF_0603 2 2
(0.1UF*1) 50mA 456mA
1

180Ohm@100MHz GM@ 1 1 +1.5VS 1 2 +1.5VS_HDA A32 VCC_HDA VCC_DMI_1 AH48

HDA
C475 C474 R439 R447 1 AF48
VCC_DMI_2
1

DMI
GM@ GM@ 0_0402_5% 0_0402_5% C493 Close to A32 AH47
0.1U_0402_16V4Z PM@ GM@ R446 VCC_DMI_3
VCC_DMI_4 AG47
2 2 0_0402_5% 0.1U_0402_16V4Z +1.05VS_DMI
58.696mA 1 2 +1.05VS
2

0.01U_0402_16V7K PM@ GM@ 2 +1.5VS_TVDAC M25 VCC_DMI: 456mA 1 R186

VCCD_TVDAC

D TV/CRT
C237 0_0603_5%
(0.1UF*1)
2

L28 48.363mA
+1.5VS_QDAC VCCD_QDAC 0.1U_0402_16V4Z
2
VCCD_HPLL: 157.2mA (0.1UF*1) 157.2mA
+1.05VS_HPLL AF1 VCCD_HPLL Pre-MP
A8 VTTLF_CAP1
+1.05VS_PEGPLL 50mA VTTLF1 VTTLF_CAP2
Please check Power AA47 VCCD_PEG_PLL VTTLF2 L1 CANTIGA GM: SA00002JTB0

VTTLF
VCCD_TVDAC: 58.696mA source if want AB2 VTTLF_CAP3
+1.5VS_TVDAC Close to AA47 60.31mA
VTTLF3 (S IC AC82GM45 SLB94 B3 FCBGA1329 GM ABO!)
(0.1UF*1, 0.01UF*1) support IAMT M38 VCCD_LVDS_1 1 1 1
LVDS

+1.5VS 1 2 L37 C153 C434 C450 PVT2

L14 VCCD_LVDS_2
1 1 Close to AF1
MBK1608221YZF_0603 C191 C193 Also power for internal VCCD_PEG_PLL: 50mA 0.47U_0603_16V4Z 0.47U_0603_16V4Z CANTIGA GM: SA00002JT50
2 2 2
0.1U_0402_16V4Z
Thermal Sensor (0.1UF*1) CANTIGA ES_FCBGA1329 0.47U_0603_16V4Z (S IC AC88CTGM QU36 B3 FCBGA 1329 GMCH GM)
2 2 +1.8V_LVDS UMAGM@ DVT
+1.8V 1 2 PVT
0.022U_0402_16V7K R160 CANTIGA GM: SA00001P930
1

0_0603_5% 1 1 CANTIGA GM: SA00002JT10

GM@ C216 C217 R159 (S IC EB88CTGM QR32 B0 FCBGA 1329 MCH GM)
GM@ GM@ 0_0402_5% (S IC AC88CTGM QT62 B2 FCBGA 1329 GMCH GM)
10U_0805_6.3V6M PM@
A 2 2 A
VCCD_QDAC: 48.363mA +1.5VS_QDAC R54
2

1U_0402_6.3V4Z D6
(0.1UF*1, 0.01UF*1) 2 1 1 2
+1.05VS +3VS
+1.5VS 1 2 VCCD_LVDS: 60 311111mA
R110 1 1 10_0603_5%
(1UF*1)
1

100_0603_1% C187 C196 CH751H-40PT_SOD323-2

180Ohm@100MHz R117
0.1U_0402_16V4Z 0_0402_5%
2 2 @ Security Classification Compal Secret Data Compal Electronics, Inc.
0.01U_0402_16V7K 2007/09/20 2008/09/20 Title
Issued Date Deciphered Date
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A4221
DVT (Check) AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401552
Date Friday, May 16, 2008 Sheet 12 of 50
5 3 2 1
 5 3 2 1

U30I U30J

AU48 VSS_1 VSS_100 AM36 BG21 VSS_199 VSS_297 AH8

AR48 VSS_2 VSS_101 AE36 L12 VSS_200 VSS_298 Y8
AL48 VSS_3 VSS_102 P36 AW21 VSS_201 VSS_299 L8
BB47 VSS_4 VSS_103 L36 AU21 VSS_202 VSS_300 E8
AW47 VSS_5 VSS_104 J36 AP21 VSS_203 VSS_301 B8
AN47 VSS_6 VSS_105 F36 AN21 VSS_204 VSS_302 AY7
AJ47 VSS_7 VSS_106 B36 AH21 VSS_205 VSS_303 AU7
AF47 VSS_8 VSS_107 AH35 AF21 VSS_206 VSS_304 AN7
AD47 VSS_9 VSS_108 AA35 AB21 VSS_207 VSS_305 AJ7
AB47 VSS_10 VSS_109 Y35 R21 VSS_208 VSS_306 AE7
Y47 VSS_11 VSS_110 U35 M21 VSS_209 VSS_307 AA7
T47 VSS_12 VSS_111 T35 J21 VSS_210 VSS_308 N7
D D
N47 VSS_13 VSS_112 BF34 G21 VSS_211 VSS_309 J7
L47 VSS_14 VSS_113 AM34 BC20 VSS_212 VSS_310 BG6
G47 VSS_15 VSS_114 AJ34 BA20 VSS_213 VSS_311 BD6
BD46 VSS_16 VSS_115 AF34 AW20 VSS_214 VSS_312 AV6
BA46 VSS_17 VSS_116 AE34 AT20 VSS_215 VSS_313 AT6
AY46 VSS_18 VSS_117 W34 AJ20 VSS_216 VSS_314 AM6
AV46 VSS_19 VSS_118 B34 AG20 VSS_217 VSS_315 M6
AR46 VSS_20 VSS_119 A34 Y20 VSS_218 VSS_316 C6
AM46 VSS_21 VSS_120 BG33 N20 VSS_219 VSS_317 BA5
V46 VSS_22 VSS_121 BC33 K20 VSS_220 VSS_318 AH5
R46 VSS_23 VSS_122 BA33 F20 VSS_221 VSS_319 AD5
P46 VSS_24 VSS_123 AV33 C20 VSS_222 VSS_320 Y5
H46 VSS_25 VSS_124 AR33 A20 VSS_223 VSS_321 L5
F46 VSS_26 VSS_125 AL33 BG19 VSS_224 VSS_322 J5
BF44 VSS_27 VSS_126 AH33 A18 VSS_225 VSS_323 H5
AH44 VSS_28 VSS_127 AB33 BG17 VSS_226 VSS_324 F5
AD44 VSS_29 VSS_128 P33 BC17 VSS_227 VSS_325 BE4
AA44 VSS_30 VSS_129 L33 AW17 VSS_228
Y44 VSS_31 VSS_130 H33 AT17 VSS_229 VSS_327 BC3
U44 VSS_32 VSS_131 N32 R17 VSS_230 VSS_328 AV3
T44 VSS_33 VSS_132 K32 M17 VSS_231 VSS_329 AL3
M44 VSS_34 VSS_133 F32 H17 VSS_232 VSS_330 R3
F44
BC43
VSS_35
VSS_36
VSS_134
VSS_135
C32
A31
C17 VSS_233 VSS VSS_331
VSS_332
P3
F3
AV43 VSS_37 VSS_136 AN29 BA16 VSS_235 VSS_333 BA2
AU43 VSS_38 VSS_137 T29 VSS_334 AW2
AM43 VSS_39 VSS_138 N29 AU16 VSS_237 VSS_335 AU2
J43 VSS_40 VSS_139 K29 AN16 VSS_238 VSS_336 AR2
C43 VSS_41 VSS_140 H29 N16 VSS_239 VSS_337 AP2
BG42
AY42
VSS_42
VSS_43
VSS VSS_141
VSS_142
F29
A29
K16
G16
VSS_240
VSS_241
VSS_338
VSS_339
AJ2
AH2
AT42 VSS_44 VSS_143 BG28 E16 VSS_242 VSS_340 AF2
C C
AN42 VSS_45 VSS_144 BD28 BG15 VSS_243 VSS_341 AE2
AJ42 VSS_46 VSS_145 BA28 AC15 VSS_244 VSS_342 AD2
AE42 VSS_47 VSS_146 AV28 W15 VSS_245 VSS_343 AC2
N42 VSS_48 VSS_147 AT28 A15 VSS_246 VSS_344 Y2
L42 VSS_49 VSS_148 AR28 BG14 VSS_247 VSS_345 M2
BD41 VSS_50 VSS_149 AJ28 AA14 VSS_248 VSS_346 K2
AU41 VSS_51 VSS_150 AG28 C14 VSS_249 VSS_347 AM1
AM41 VSS_52 VSS_151 AE28 BG13 VSS_250 VSS_348 AA1
AH41 VSS_53 VSS_152 AB28 BC13 VSS_251 VSS_349 P1
AD41 VSS_54 VSS_153 Y28 BA13 VSS_252 VSS_350 H1
AA41 VSS_55 VSS_154 P28
Y41 VSS_56 VSS_155 K28 VSS_351 U24
U41 VSS_57 VSS_156 H28 AN13 VSS_255 VSS_352 U28
T41 VSS_58 VSS_157 F28 AJ13 VSS_256 VSS_353 U25
M41 VSS_59 VSS_158 C28 AE13 VSS_257 VSS_354 U29
G41 VSS_60 VSS_159 BF26 N13 VSS_258
B41 VSS_61 VSS_160 AH26 L13 VSS_259 VSS_NCTF_1 AF32
BG40 VSS_62 VSS_161 AF26 G13 VSS_260 VSS_NCTF_2 AB32
BB40 VSS_63 VSS_162 AB26 E13 VSS_261 VSS_NCTF_3 V32
AV40 VSS_64 VSS_163 AA26 BF12 VSS_262 VSS_NCTF_4 AJ30
AN40 VSS_65 VSS_164 C26 AV12 VSS_263 VSS_NCTF_5 AM29
H40 VSS_66 VSS_165 B26 AT12 VSS_264 VSS_NCTF_6 AF29
E40 VSS_67 VSS_166 BH25 AM12 VSS_265 VSS_NCTF_7 AB29
AT39 BD25 AA12 U26

VSS NCTF
VSS_68 VSS_167 VSS_266 VSS_NCTF_8
AM39 VSS_69 VSS_168 BB25 J12 VSS_267 VSS_NCTF_9 U23
AJ39 VSS_70 VSS_169 AV25 A12 VSS_268 VSS_NCTF_10 AL20
AE39 VSS_71 VSS_170 AR25 BD11 VSS_269 VSS_NCTF_11 V20
N39 VSS_72 VSS_171 AJ25 BB11 VSS_270 VSS_NCTF_12 AC19
L39 VSS_73 VSS_172 AC25 AY11 VSS_271 VSS_NCTF_13 AL17
B39 VSS_74 VSS_173 Y25 AN11 VSS_272 VSS_NCTF_14 AJ17
BH38 VSS_75 VSS_174 N25 AH11 VSS_273 VSS_NCTF_15 AA17
BC38 VSS_76 VSS_175 L25 VSS_NCTF_16 U17
B B
BA38 VSS_77 VSS_176 J25 Y11 VSS_275
AU38 VSS_78 VSS_177 G25 N11 VSS_276
AH38 VSS_79 VSS_178 E25 G11 VSS_277 VSS_SCB_1 BH48
AD38 VSS_80 VSS_179 BF24 C11 VSS_278 VSS_SCB_2 BH1
AA38 VSS_81 VSS_180 AD12 BG10 VSS_279 VSS_SCB_3 A48
Y38 AY24 AV10 C1
VSS SCB

VSS_82 VSS_181 VSS_280 VSS_SCB_4

U38 VSS_83 VSS_182 AT24 AT10 VSS_281 VSS_SCB_5 A3
T38 VSS_84 VSS_183 AJ24 AJ10 VSS_282
J38 VSS_85 VSS_184 AH24 AE10 VSS_283
F38 VSS_86 VSS_185 AF24 AA10 VSS_284
C38 VSS_87 VSS_186 AB24 M10 VSS_285
BF37 VSS_88 VSS_187 R24 BF9 VSS_286 NC_26 E1
BB37 VSS_89 VSS_188 L24 BC9 VSS_287 NC_27 D2
AW37 VSS_90 VSS_189 K24 AN9 VSS_288 NC_28 C3
AT37 VSS_91 VSS_190 J24 AM9 VSS_289 NC_29 B4
AN37 VSS_92 VSS_191 G24 AD9 VSS_290 NC_30 A5
AJ37 VSS_93 VSS_192 F24 G9 VSS_291 NC_31 A6
H37 VSS_94 VSS_193 E24 B9 VSS_292 NC_32 A43
C37 VSS_95 VSS_194 BH23 BH8 VSS_293 NC_33 A44
BG36 VSS_96 VSS_195 AG23 BB8 VSS_294 NC_34 B45
BD36 Y23 AV8 C46
NC

VSS_97 VSS_196 VSS_295 NC_35

AK15 VSS_98 VSS_197 B23 AT8 VSS_296 NC_36 D47
AU36 VSS_99 VSS_198 A23 NC_37 B47
VSS_199 AJ6 NC_38 A46
NC_39 F48
CANTIGA ES_FCBGA1329 E48
UMAGM@ NC_40
NC_41 C48
NC_42 B48

CANTIGA ES_FCBGA1329
UMAGM@
A A
PVT2 DVT
CANTIGA GM: SA00002JT50 CANTIGA GM: SA00001P930
(S IC AC88CTGM QU36 B3 FCBGA 1329 GMCH GM) (S IC EB88CTGM QR32 B0 FCBGA 1329 MCH GM)

Pre-MP PVT Security Classification Compal Secret Data Compal Electronics, Inc.
CANTIGA GM: SA00002JTB0 CANTIGA GM: SA00002JT10 Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title
(S IC AC82GM45 SLB94 B3 FCBGA1329 GM ABO!) (S IC AC88CTGM QT62 B2 FCBGA 1329 GMCH GM)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDEN IAL
SCHEMATIC MB A4221
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401552
Date Friday, May 16, 2008 Sheet 13 of 50
5 3 2 1
 5 3 2 1

+1.8V +1.8V

JDIMM2 +1.8V
+DIMM_VREF 1 VREF VSS 2
3 4 DDRA_SDQ4 +DIMM_VREF
VSS DQ4

1
DDRA_SDQ0 5 6 DDRA_SDQ5 20mils
DDRA_SDQ1 DQ0 DQ5 R174
7 DQ1 VSS 8
9 10 DDRA_SDM0
DDRA_SDQS0# VSS DM0 1K_0402_1%
9 DDRA_SDQS0# DDRA_SDQS0
11 DQS0# VSS 12
DDRA_SDQ6
1
C218
20mils
13 14 To SODIMM and GMCH

2
9 DDRA_SDQS0 DQS0 DQ6 DDRA_SDQ7
15 VSS DQ7 16 +DIMM_VREF
DDRA_SDQ2 17 18 0.1U_0402_16V4Z
DQ2 VSS

1
DDRA_SDQ3 DDRA_SDQ12 2
19 DQ3 DQ12 20
D DDRA_SDQ13 R161 D
21 VSS DQ13 22
DDRA_SDQ8 23 24
DDRA_SDQ9 DQ8 VSS DDRA_SDM1 1K_0402_1%
25 DQ9 DM1 26
27 28

2
DDRA_SDQS1# VSS VSS
9 DDRA_SDQS1# 29 DQS1# CK0 30 DDRA_CLK0 8
DDRA_SDQS1 31 32
9 DDRA_SDQS1 DQS1 CK0# DDRA_CLK0# 8
33 VSS VSS 34
DDRA_SDQ10 35 36 DDRA_SDQ14
DDRA_SDQ11 DQ10 DQ14 DDRA_SDQ15
37 DQ11 DQ15 38
39 40 DDRA_SMA[0..14]
VSS VSS 9 DDRA_SMA[0..14]
DDRA_SDQ[0..63]
9 DDRA_SDQ[0..63] +1.8V
41 VSS VSS 42
DDRA_SDQ16 43 44 DDRA_SDQ20 DDRA_SDM[0..7]
DQ16 DQ20 9 DDRA_SDM[0..7]
DDRA_SDQ17 45 46 DDRA_SDQ21
DQ17 DQ21
47 VSS VSS 48
DDRA_SDQS2# 49 50 1 1 1 1 1
9 DDRA_SDQS2# DQS2# NC PM_EXTTS#0 8
DDRA_SDQS2 51 52 DDRA_SDM2 C159 C140 C149 C110 C123
9 DDRA_SDQS2 DQS2 DM2
53 VSS VSS 54
DDRA_SDQ18 55 56 DDRA_SDQ22 2.2U_0603_6.3V6K 2.2U_0603_6.3V6K 2.2U_0603_6.3V6K
DDRA_SDQ19 DQ18 DQ22 DDRA_SDQ23 2 2 2 2 2
57 DQ19 DQ23 58
59 60 2.2U_0603_6.3V6K 2.2U_0603_6.3V6K
DDRA_SDQ24 VSS VSS DDRA_SDQ28
61 DQ24 DQ28 62
DDRA_SDQ25 63 64 DDRA_SDQ29
DQ25 DQ29
65 VSS VSS 66
DDRA_SDM3 67 68 DDRA_SDQS3#
DM3 DQS3# DDRA_SDQS3 DDRA_SDQS3# 9
69 NC DQS3 70 DDRA_SDQS3 9
71 VSS VSS 72
DDRA_SDQ26 73 74 DDRA_SDQ30 +1.8V
DDRA_SDQ27 DQ26 DQ30 DDRA_SDQ31 +0.9VS
75 DQ27 DQ31 76
77 VSS VSS 78
DDRA_CKE0 79 80 DDRA_CKE1 DDRA_CKE0 1 4
C 8 DDRA_CKE0 CKE0 NC/CKE1 DDRA_CKE1 8 C
81 82 DDRA_SBS2# 2 3 1 1 1 1
VDD VDD RP43 56_0404_4P2R_5% C427 C424 C440 C444
83 NC NC/A15 84
DDRA_SBS2# 85 86 DDRA_SMA14
9 DDRA_SBS2# BA2 NC/A14
87 88 DDRA_SMA12 1 4 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDRA_SMA12 VDD VDD DDRA_SMA11 DDRA_SMA9 2 2 2 2
89 A12 A11 90 2 3
DDRA_SMA9 91 92 DDRA_SMA7 RP39 56_0404_4P2R_5% 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDRA_SMA8 A9 A7 DDRA_SMA6
93 A8 A6 94
95 96 DDRA_SMA8 1 4
DDRA_SMA5 VDD VDD DDRA_SMA4 DDRA_SMA5
97 A5 A4 98 2 3
DDRA_SMA3 99 100 DDRA_SMA2 RP35 56_0404_4P2R_5%
DDRA_SMA1 A3 A2 DDRA_SMA0
101 A1 A0 102
103 104 DDRA_SMA3 1 4
DDRA_SMA10 VDD VDD DDRA_SBS1# DDRA_SMA1 +0.9VS
105 A10/AP BA1 106 DDRA_SBS1# 9 2 3
DDRA_SBS0# 107 108 DDRA_SRAS# RP31 56_0404_4P2R_5%
9 DDRA_SBS0# BA0 RAS# DDRA_SRAS# 9
DDRA_SWE# 109 110 DDRA_SCS0#
9 DDRA_SWE# WE# S0# DDRA_SCS0# 8
111 112 DDRA_SMA10 1 4
DDRA_SCAS# VDD VDD DDRA_ODT0 DDRA_SBS0#
9 DDRA_SCAS# 113 CAS# ODT0 114 DDRA_ODT0 8 2 3 1 1 1 1 1
DDRA_SCS1# 115 116 DDRA_SMA13 RP27 56_0404_4P2R_5% C111 C112 C124 C135 C144
8 DDRA_SCS1# NC/S1# NC/A13
117 VDD VDD 118
DDRA_ODT1 119 120 DDRA_SWE# 1 4 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
8 DDRA_ODT1 NC/ODT1 NC 2 2 2 2 2
121 122 DDRA_SCAS# 2 3
DDRA_SDQ32 VSS VSS DDRA_SDQ36 RP23 56_0404_4P2R_5% 0.1U_0402_16V4Z 0.1U_0402_16V4Z
123 DQ32 DQ36 124
DDRA_SDQ33 125 126 DDRA_SDQ37
DQ33 DQ37 DDRA_SCS1#
127 VSS VSS 128 1 4
DDRA_SDQS4# 129 130 DDRA_SDM4 DDRA_ODT1 2 3
9 DDRA_SDQS4# DDRA_SDQS4 DQS4# DM4 RP19 56_0404_4P2R_5% +0.9VS
9 DDRA_SDQS4 131 DQS4 VSS 132
133 134 DDRA_SDQ38
DDRA_SDQ34 VSS DQ38 DDRA_SDQ39
135 DQ34 DQ39 136
DDRA_SDQ35 137 138
DQ35 VSS DDRA_SDQ44 DDRA_SMA11
139 VSS DQ44 140 1 4 1 1 1 1 1
DDRA_SDQ40 141 142 DDRA_SDQ45 DDRA_SMA14 2 3 C122 C131 C141 C162 C154
DDRA_SDQ41 DQ40 DQ45 RP40 56_0404_4P2R_5%
143 DQ41 VSS 144
B DDRA_SDQS5# 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z B
145 VSS DQS5# 146 DDRA_SDQS5# 9
DDRA_SDM5 DDRA_SDQS5 DDRA_SMA6 2 2 2 2 2
147 DM5 DQS5 148 DDRA_SDQS5 9 1 4
149 150 DDRA_SMA7 2 3 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDRA_SDQ42 VSS VSS DDRA_SDQ46 RP36 56_0404_4P2R_5%
151 DQ42 DQ46 152
DDRA_SDQ43 153 154 DDRA_SDQ47
DQ43 DQ47 DDRA_SMA2
155 VSS VSS 156 1 4
DDRA_SDQ48 157 158 DDRA_SDQ52 DDRA_SMA4 2 3 +0.9VS
DDRA_SDQ49 DQ48 DQ52 DDRA_SDQ53 RP32 56_0404_4P2R_5%
159 DQ49 DQ53 160
161 VSS VSS 162
163 164 DDRA_SBS1# 1 4
NC,TEST CK1 DDRA_CLK1 8
165 166 DDRA_SMA0 2 3 1 1 1
VSS CK1# DDRA_CLK1# 8
DDRA_SDQS6# 167 168 RP28 56_0404_4P2R_5% C150 C147 C160
9 DDRA_SDQS6# DDRA_SDQS6 DQS6# VSS DDRA_SDM6
9 DDRA_SDQS6 169 DQS6 DM6 170
171 172 DDRA_SCS0# 1 4 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDRA_SDQ50 VSS VSS DDRA_SDQ54 DDRA_SRAS# 2 2 2
173 DQ50 DQ54 174 2 3
DDRA_SDQ51 175 176 DDRA_SDQ55 RP24 56_0404_4P2R_5% 0.1U_0402_16V4Z
DQ51 DQ55
177 VSS VSS 178
DDRA_SDQ56 179 180 DDRA_SDQ60 DDRA_SMA13 1 4
DDRA_SDQ57 DQ56 DQ60 DDRA_SDQ61 DDRA_ODT0
181 DQ57 DQ61 182 2 3
183 184 RP20 56_0404_4P2R_5%
DDRA_SDM7 VSS VSS DDRA_SDQS7#
185 DM7 DQS7# 186 DDRA_SDQS7# 9
187 188 DDRA_SDQS7 DDRA_CKE1 1 2
DDRA_SDQ58 VSS DQS7 DDRA_SDQS7 9 R92 56_0402_5%
189 DQ58 VSS 190
DDRA_SDQ59 191 192 DDRA_SDQ62
DQ59 DQ62 DDRA_SDQ63
193 VSS DQ63 194
D_CK_SDATA 195 196
15,16,20 D_CK_SDATA SDA VSS
D_CK_SCLK 197 198 R32 1 2 10K_0402_5%
15,16,20 D_CK_SCLK SCL SAO
+3VS 199 200 R26 1 2 10K_0402_5%
VDDSPD SA1
203 GND GND 204

FOX_AS0A426-N2RN-7F
CONN@
A +3VS A

1 1
DIMM0 REV H:5.2mm (BOT)
C19 C18

0.1U_0402_16V4Z
2
2.2U_0805_10V6K 2 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDEN IAL
SCHEMATIC MB A4221
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401552
Date Friday, May 16, 2008 Sheet 14 of 50
5 3 2 1
 A B C D E

+DIMM_VREF +1.8V

+1.8V +1.8V
1 1
1 1
JDIMM1 C224 C219 + C171 + C100
+DIMM_VREF 1 VREF VSS 2
3 4 DDRB_SDQ4 2.2U_0805_10V6K @
DDRB_SDQ0 VSS DQ4 DDRB_SDQ1 2 2
0.1U_0402_16V4Z 2 2
5 DQ0 DQ5 6
DDRB_SDQ5 7 8 330U_D2E_2.5VM_R15
DQ1 VSS DDRB_SDM0 330U_D2E_2.5VM_R15
9 VSS DM0 10
DDRB_SDQS0# 11 12
1 9 DDRB_SDQS0# DDRB_SDQS0 DQS0# VSS DDRB_SDQ6 1
9 DDRB_SDQS0 13 DQS0 DQ6 14
15 16 DDRB_SDQ7
DDRB_SDQ2 VSS DQ7
17 DQ2 VSS 18
DDRB_SDQ3 19 20 DDRB_SDQ12
DQ3 DQ12 DDRB_SDQ13
21 VSS DQ13 22
DDRB_SDQ8 23 24
DDRB_SDQ9 DQ8 VSS DDRB_SDM1
25 DQ9 DM1 26
27 VSS VSS 28
DDRB_SDQS1# 29 30
9 DDRB_SDQS1# DQS1# CK0 DDRB_CLK0 8
DDRB_SDQS1 31 32
9 DDRB_SDQS1 DQS1 CK0# DDRB_CLK0# 8
33 VSS VSS 34
DDRB_SDQ10 35 36 DDRB_SDQ14 DDRB_SMA[0..14]
DQ10 DQ14 9 DDRB_SMA[0..14]
DDRB_SDQ11 37 38 DDRB_SDQ15
DQ11 DQ15 DDRB_SDQ[0..63]
39 VSS VSS 40 9 DDRB_SDQ[0..63]
DDRB_SDM[0..7]
9 DDRB_SDM[0..7]
41 VSS VSS 42
DDRB_SDQ16 43 44 DDRB_SDQ20
DDRB_SDQ17 DQ16 DQ20 DDRB_SDQ21
45 DQ17 DQ21 46
47 VSS VSS 48
DDRB_SDQS2# 49 50
9 DDRB_SDQS2# DQS2# NC PM_EXTTS#1 8
DDRB_SDQS2 51 52 DDRB_SDM2
9 DDRB_SDQS2 DQS2 DM2
53 VSS VSS 54
DDRB_SDQ18 55 56 DDRB_SDQ22
DDRB_SDQ19 DQ18 DQ22 DDRB_SDQ23
57 DQ19 DQ23 58
59 VSS VSS 60
DDRB_SDQ24 61 62 DDRB_SDQ28
DDRB_SDQ25 DQ24 DQ28 DDRB_SDQ29 +1.8V
63 DQ25 DQ29 64
65 VSS VSS 66
DDRB_SDM3 67 68 DDRB_SDQS3#
DM3 DQS3# DDRB_SDQS3 DDRB_SDQS3# 9 +0.9VS
69 NC DQS3 70 DDRB_SDQS3 9
71 VSS VSS 72 1 1 1 1 1
2 DDRB_SDQ26 DDRB_SDQ30 C161 C152 C136 C105 C126 2
73 DQ26 DQ30 74
DDRB_SDQ27 75 76 DDRB_SDQ31 DDRB_CKE0 1 4
DQ27 DQ31 DDRB_SBS2# 2.2U_0603_6.3V6K 2.2U_0603_6.3V6K 2.2U_0603_6.3V6K
77 VSS VSS 78 2 3
DDRB_CKE0 DDRB_CKE1 RP42 56_0404_4P2R_5% 2 2
2.2U_0603_6.3V6K 2 2
2.2U_0603_6.3V6K 2
8 DDRB_CKE0 79 CKE0 NC/CKE1 80 DDRB_CKE1 8
81 VDD VDD 82
83 84 DDRB_SMA12 1 4
DDRB_SBS2# NC NC/A15 DDRB_SMA14 DDRB_SMA9
9 DDRB_SBS2# 85 BA2 NC/A14 86 2 3
87 88 RP38 56_0404_4P2R_5%
DDRB_SMA12 VDD VDD DDRB_SMA11
89 A12 A11 90
DDRB_SMA9 91 92 DDRB_SMA7 DDRB_SMA8 1 4
DDRB_SMA8 A9 A7 DDRB_SMA6 DDRB_SMA5 +1.8V
93 A8 A6 94 2 3
95 96 RP34 56_0404_4P2R_5%
DDRB_SMA5 VDD VDD DDRB_SMA4
97 A5 A4 98
DDRB_SMA3 99 100 DDRB_SMA2 DDRB_SMA3 1 4
DDRB_SMA1 A3 A2 DDRB_SMA0 DDRB_SMA1
101 A1 A0 102 2 3 1 1 1 1
103 104 RP30 56_0404_4P2R_5% C115 C104 C165 C145
DDRB_SMA10 VDD VDD DDRB_SBS1#
105 A10/AP BA1 106 DDRB_SBS1# 9
DDRB_SBS0# 107 108 DDRB_SRAS# DDRB_SMA10 1 4 0.1U_0402_16V4Z 0.1U_0402_16V4Z
9 DDRB_SBS0# BA0 RAS# DDRB_SRAS# 9 2 2 2 2
DDRB_SWE# 109 110 DDRB_SCS0# DDRB_SBS0# 2 3 0.1U_0402_16V4Z 0.1U_0402_16V4Z
9 DDRB_SWE# WE# S0# DDRB_SCS0# 8
111 112 RP26 56_0404_4P2R_5%
DDRB_SCAS# VDD VDD DDRB_ODT0
9 DDRB_SCAS# 113 CAS# ODT0 114 DDRB_ODT0 8
DDRB_SCS1# 115 116 DDRB_SMA13 DDRB_SWE# 1 4
8 DDRB_SCS1# NC/S1# NC/A13
117 118 DDRB_SCAS# 2 3
DDRB_ODT1 VDD VDD RP22 56_0404_4P2R_5%
8 DDRB_ODT1 119 NC/ODT1 NC 120
121 VSS VSS 122
DDRB_SDQ32 123 124 DDRB_SDQ36 DDRB_SCS1# 1 4
DDRB_SDQ33 DQ32 DQ36 DDRB_SDQ37 DDRB_ODT1 +0.9VS
125 DQ33 DQ37 126 2 3
127 128 RP18 56_0404_4P2R_5%
DDRB_SDQS4# VSS VSS DDRB_SDM4
9 DDRB_SDQS4# 129 DQS4# DM4 130
DDRB_SDQS4 131 132
9 DDRB_SDQS4 DQS4 VSS DDRB_SDQ38
133 VSS DQ38 134 1 1 1 1 1
DDRB_SDQ34 135 136 DDRB_SDQ39 DDRB_SMA11 1 4 C125 C133 C130 C116 C146
3 DDRB_SDQ35 DQ34 DQ39 DDRB_SMA14 3
137 DQ35 VSS 138 2 3
139 140 DDRB_SDQ44 RP41 56_0404_4P2R_5% 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDRB_SDQ40 VSS DQ44 DDRB_SDQ45 2
0.1U_0402_16V4Z 2 2
0.1U_0402_16V4Z 2 2
0.1U_0402_16V4Z
141 DQ40 DQ45 142
DDRB_SDQ41 143 144 DDRB_SMA6 1 4
DQ41 VSS DDRB_SDQS5# DDRB_SMA7
145 VSS DQS5# 146 DDRB_SDQS5# 9 2 3
DDRB_SDM5 147 148 DDRB_SDQS5 RP37 56_0404_4P2R_5%
DM5 DQS5 DDRB_SDQS5 9
149 VSS VSS 150
DDRB_SDQ42 151 152 DDRB_SDQ46 DDRB_SMA2 1 4 +0.9VS
DDRB_SDQ43 DQ42 DQ46 DDRB_SDQ47 DDRB_SMA4
153 DQ43 DQ47 154 2 3
155 156 RP33 56_0404_4P2R_5%
DDRB_SDQ48 VSS VSS DDRB_SDQ52
157 DQ48 DQ52 158
DDRB_SDQ49 159 160 DDRB_SDQ53 DDRB_SBS1# 1 4 1 1 1 1 1
DQ49 DQ53 DDRB_SMA0 C155 C137 C158 C114 C103
161 VSS VSS 162 2 3
163 164 RP29 56_0404_4P2R_5%
NC,TEST CK1 DDRB_CLK1 8
165 166 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
VSS CK1# DDRB_CLK1# 8 2 2 2 2 2
DDRB_SDQS6# 167 168 DDRB_SCS0# 1 4 0.1U_0402_16V4Z 0.1U_0402_16V4Z
9 DDRB_SDQS6# DDRB_SDQS6 DQS6# VSS DDRB_SDM6 DDRB_SRAS#
9 DDRB_SDQS6 169 DQS6 DM6 170 2 3
171 172 RP25 56_0404_4P2R_5%
DDRB_SDQ50 VSS VSS DDRB_SDQ54
173 DQ50 DQ54 174
DDRB_SDQ51 175 176 DDRB_SDQ55 DDRB_SMA13 1 4 +0.9VS
DQ51 DQ55 DDRB_ODT0
177 VSS VSS 178 2 3
DDRB_SDQ56 179 180 DDRB_SDQ60 RP21 56_0404_4P2R_5%
DDRB_SDQ57 DQ56 DQ60 DDRB_SDQ61
181 DQ57 DQ61 182
183 184 DDRB_CKE1 1 2 1 1 1
DDRB_SDM7 VSS VSS DDRB_SDQS7# R90 56_0402_5% C163 C148 C142
185 DM7 DQS7# 186 DDRB_SDQS7# 9
187 188 DDRB_SDQS7
DDRB_SDQ58 VSS DQS7 DDRB_SDQS7 9 0.1U_0402_16V4Z 0.1U_0402_16V4Z
189 DQ58 VSS 190
DDRB_SDQ59 DDRB_SDQ62 2 2
0.1U_0402_16V4Z 2
191 DQ59 DQ62 192
193 194 DDRB_SDQ63
D_CK_SDATA VSS DQ63
14,16,20 D_CK_SDATA 195 SDA VSS 196
D_CK_SCLK 197 198 R35 1 2 10K_0402_5%
14,16,20 D_CK_SCLK SCL SAO
+3VS 199 200 R31 1 2 10K_0402_5% +3VS
VDDSPD SA1
201 GND GND 202

FOX_AS0A426-NARN-7F
CONN@

DIMM1 REV H:9.2mm (BOT)

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDEN IAL
SCHEMATIC MB A4221
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401552
Date Friday, May 16, 2008 Sheet 15 of 50
A B C D E
 A B C D E F G H

FSLC FSLB FSLA CPU SRC PCI

CLK_VDDSRC CLK_VDD
Clock Generator
CLKSEL2 CLKSEL1 CLKSEL0 L22 2 L21 2
MHz MHz MHz 1.05VS 1
KC FBM-L11-201209-221LMAT_0805
3VS 1
KC FBM-L11-201209-221LMAT_0805
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 266 100 33.3 C340 C302 C301 C323 C335 C309 C337 C339 C303 C320 C316 C338 C304 C336
C343 C342
10U_0805_10V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
0 1 0 200 100 33.3 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
0.1U_0402_16V4Z
0 1 1 166 100 33.3 U18
1 1
CLK_VDD
Table : ICS9LPRS387 D_CK_SDATA
SDATA 9 D_CK_SDATA 14,15,20
CLK_REQ# Control Free-Run 6 VDDREF D_CK_SCLK
SCLK 10 D_CK_SCLK 14,15,20
CR#_10(WLAN) PCIEX10 PC EX0 19 VDD48
CR#_6(MCH) PCIEX6 PC EX1 72 71 CLK_CPU_BCLK
VDDCPU CPUT0_LPR_F CLK_CPU_BCLK 4
CR#_4(NEW CARD) PCIEX4 12 70 CLK_CPU_BCLK#
VDDPCI CPUC0_LPR_F CLK_CPU_BCLK# 4
3VS
CR#_9(MINI CARDII) PCIEX9 27 VDDPLL3
68 CLK_MCH_BCLK
CPUT1_LPR_F CLK_MCH_BCLK 7
SRC7(VGA_CLK): Discrete VGA[Enable] UMA[Disable] 55 VDDSRC

2
3VS 67 CLK_MCH_BCLK#
CPUC1_LPR_F CLK_MCH_BCLK# 7
R228
1 2 CLK_PCI2 10K_0402_5% CLK_VDDSRC 52
R514 10K_0402_5% VDDSRC_IO CLK_DREF_96M
@ SRCT0_LPR/DOTT_96_LPR 24 CLK_DREF_96M 8
CLK_PCI2=1, Trusted Mode Enable(No overclocking allowed) 38

1
CK505_PWRGD VDDSRC_IO CLK_DREF_96M#
SRCC0_LPR/DOTC_96_LPR 25 CLK_DREF_96M# 8
mount to Enable ITP_CLK 62 VDDSRC_IO

1
D
1
R256
2
@ 10K_0402_5% CLK_DREF_SSC
VGA: disable this pair by BIOS
2 CLK_ENABLE# 46 31 VDDPLL3_IO 27MHz_NonSS/SRCT1_LPR/SE1 28 CLK_DREF_SSC 8
G
1 2 CLK_PCI5 S Q22 66 29 CLK_DREF_SSC#
CLK_DREF_SSC# 8

3
R251 10K_0402_5% VDDCPU_IO 27MHz_SS/SRCC1_LPR/SE2
2N7002_SOT23
@ 23 VDD96_IO CLK_PCIE_SATA
VGA: disable this pair by BIOS
CLK_PCI5=0, Pin63,64 is SRC_CLK SRCT2_LPR/SATAT_LPR 32 CLK_PCIE_SATA 22
CLK_PCI5=1, Pin63,64 is ITP_CLK
2 33 CLK_PCIE_SATA# 2
SRCC2_LPR/SATAC_LPR CLK_PCIE_SATA# 22
H_STP_CPU# 53
23 H_STP_CPU# CPU_STOP#
1 2 CLK_PCI4
R247 10K_0402_5% H_STP_PCI# 54 35 CLK_PCIE_ICH
23 H_STP_PCI# PCI_STOP# SRCT3_LPR CLK_PCIE_ICH 23
CLK_PCI4=0, Pin28, 29 is SRC_CLK
36 CLK_PCIE_ICH#
Pin24, 25 is DOT96_CLK SRCC3_LPR CLK_PCIE_ICH# 23
1 2 CK_PWRGD
R217 @ 10K_0402_5% Cardbus usage for JALA0 13 39
PCI1 SRCT4_LPR
CLK_PCI_PCM R513 2
New Card usage for JAL90
25 CLK_PCI_PCM 1 33_0402_5% CLK_PCI2 14 PCI2/TME SRCC4_LPR 40
C300 1 2 @ 10P_0402_50V8J CLK_PCI_LPC CLK_PCI_LPC R515 2 1 33_0402_5% CLK_PCI3 15
31 CLK_PCI_LPC PCI3
57 CLK_MCH_3GPLL
SRCT6_LPR CLK_MCH_3GPLL 8
C552 1 2 @ 10P_0402_50V8J CLK_PCI_ICH CLK_PCI4 16 PCI4/27_SELECT CLK_MCH_3GPLL#
SRCC6_LPR 56 CLK_MCH_3GPLL# 8
For EMI Requrie 10/9 CLK_PCI_ICH R516 2 1 33_0402_5% CLK_PCI5 17
21 CLK_PCI_ICH PCI_F5/ITP_EN
61 CLK_PCIE_VGA
1.05VS SRCT7_LPR CLK_PCIE_VGA 17
0_0402_5% 2 1 R215 CK505_PWRGD1
23 CK_PWRGD CK_PWRGD/PD#
0_0402_5% 2 @ 1 R221 60 CLK_PCIE_VGA#
8,23,46 VGATE SRCC7_LPR CLK_PCIE_VGA# 17
2

R266 C311 UMA: disable this pair by BIOS

@ 56_0402_5% PVT 1 2 CLK_XTALIN 5 64 CLK_PCIE_READER
X1 CPUT2_ITP_LPR/SRCT8_LPR CLK_PCIE_READER 26
1

R264 R269 27P_0402_50V8J CLK_XTALOUT 4 63 CLK_PCIE_READER#

X2 CPUC2_ITP_LPR/SRCC8_LPR CLK_PCIE_READER# 26
2.2K_0402_5% 1K_0402_5% Y1
1

CLKSEL0 1 2 1 2 14.31818MHz_20P_FSX8L14.318181M20FDB
MCH_CLKSEL0 8
C308 11 44 CLK_PCIE_MINI2
CLK_PCIE_MINI2 29
2

3 NC SRCT9_LPR 3
1 2
1 2 1 2 CPU_BSEL0 5 45 CLK_PCIE_MINI2#
SRCC9_LPR CLK_PCIE_MINI2# 29
R265 R270 27P_0402_50V8J
@ 1K_0402_5% 0_0402_5% CLK_ICH_48M R529 2 1 33_0402_5% CLKSEL0 20
23 CLK_ICH_48M USB_48MHz/FSLA
50 CLK_PCIE_MINI1
SRCT10_LPR CLK_PCIE_MINI1 29
CLKSEL1 2 FSLB/TEST_MODE CLK_PCIE_MINI1#
SRCC10_LPR 51 CLK_PCIE_MINI1# 29
1.05VS CLK_ICH_14M R506 2 1 33_0402_5% CLKSEL2 7
23 CLK_ICH_14M FSLC/TEST_SEL/REF0
8 48 CLK_PCIE_LAN
REF1 SRCT11_LPR CLK_PCIE_LAN 27
2

R500 DVT
@ 1K_0402_5% 47 CLK_PCIE_LAN#
SRCC11_LPR CLK_PCIE_LAN# 27
R499 3VS 69
1K_0402_5% R259 GNDCPU
1

CLKSEL1 1 2 4.7K_0402_5% 3 37
MCH_CLKSEL1 8 GNDREF CR#3
2
G

1 2 3VS
D_CK_SDATA
18 GNDPCI CR#4 41 New Card usage for JAL90
1 2 1 2 CPU_BSEL1 5 23,27,29 ICH_SMBDATA 1 3
R502 R501 22 58
D

GND48 CR#6 MCH_CLKREQ# 8

@ 0_0402_5% 0_0402_5% Q48 (Pull High to +3VS at Page8)
2N7002_SOT23 30 65
GND CR7#
1 2 3VS
3VS 26 43 R246 10K_0402_5%
1.05VS GND CR#9 MINI2_CLKREQ# 29
R254 1 2 3VS
4.7K_0402_5% 34 DVT 49 R244 10K_0402_5%
GNDSRC CR10# MINI1_CLKREQ# 29
2
G

1 2 3VS 1 2 3VS
2

R512 59 SA000020H10 46 2 1 R690

GNDSRC CR#11 LAN_CLKREQ# 27
@ 1K_0402_5% 1 3 D_CK_SCLK R689 0_0402_5% 10K_0402_5% PVT2(JALA0)
4 23,27,29 ICH_SMBCLK (S IC ICS9LPRS387BKLFT MLF 72P CLK GEN) 4
42 21
D

GNDSRC CR#A SATA_CLKREQ# 23

R504 R505 Q49 73 (Pull High to +3VS at ICH side) MP(JALA0) add part
10K_0402_5% 1K_0402_5% 2N7002_SOT23 GND_THERMAL_PAD
1

CLKSEL2 1 2 1 2 ICS9LPRS387AKLFT_MLF72_10x10
MCH_CLKSEL2 8

1 2 1 2 CPU_BSEL2 5
Security Classification Compal Secret Data Compal Electronics, Inc.
R507 R503 2007/09/20 2008/09/20 Title
@ 0_0402_5% 0_0402_5%
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT AL
SCHEMATIC MB A4221
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401552
Date: Friday, May 16, 2008 Sheet 16 of 50
A B C D E F G H
 5 4 3 2 1

MXM_B

PCIE_MTX_C_GRX_N[0..15] L43 2
10 PCIE_MTX_C_GRX_N[0..15] 160mil(4A) 1
KC FBM-L11-201209-221LMAT_0805
B
SDVO_SCLK R392 1 GM@ 2 0_0402_5% D_EC_SMB_CK1
PCIE_MTX_C_GRX_P[0..15] 8 SDVO_SCLK
DVT(JALA0) PM@ 2 160mil(4A) SDVO_SDATA R400 1 GM@ 2 0_0402_5% D_EC_SMB_DA1
10 PCIE_MTX_C_GRX_P[0..15] 8 SDVO_SDATA
L44 2 1 C503
PCIE_GTX_C_MRX_N[0..15] KC FBM-L11-201209-221LMAT_0805 PM@
10 PCIE_GTX_C_MRX_N[0..15]
1 1 PM@
PCIE_GTX_C_MRX_P[0..15] C500 C498 1
0.1U_0603_25V7K
10 PCIE_GTX_C_MRX_P[0..15]
D 680P_0402_50V7K 68P_0402_50V8J D
PM@ 2 2 PM@

DVT(JALA0)
JMXM1A 140mil(3.5A) JMXM1B

MXM_B 1 2 1V8RUN L57 2 1 1.8VS PCIE_GTX_C_MRX_N1 109 110

PWR_SRC 1V8RUN KC FBM-L11-201209-221LMAT_0805 PCIE_GTX_C_MRX_P1 PEX_RX1# GND PCIE_MTX_C_GRX_N1
3 PWR_SRC 1V8RUN 4 111 PEX_RX1 PEX_TX1# 112
5 6 PM@ 113 114 PCIE_MTX_C_GRX_P1
PWR_SRC 1V8RUN L58 2 PCIE_GTX_C_MRX_N0 GND PEX_TX1
7 PWR_SRC 1V8RUN 8 1 115 PEX_RX0# GND 116
9 10 KC FBM-L11-201209-221LMAT_0805 PCIE_GTX_C_MRX_P0 117 118 PCIE_MTX_C_GRX_N0
PWR_SRC 1V8RUN PM@ PEX_RX0 PEX_TX0# PCIE_MTX_C_GRX_P0
11 PWR_SRC 1V8RUN 12 119 GND PEX_TX0 120
13 14 CLK_PCIE_VGA# 121 122
PWR_SRC 1V8RUN 16 CLK_PCIE_VGA# PEX_REFCLK# PRSNT1#
15 16 CLK_PCIE_VGA 123 124
PWR_SRC RUNPWROK VGA_ON 33 16 CLK_PCIE_VGA PEX_REFCLK TV_C/HDTV_Pr
17 GND 5VRUN 18 5VS 125 CLK_REQ# GND 126
19 GND GND 20 21 PLTRST_VGA# 127 PEX_RST# TV_Y/HDTV_Y/TV_CVBS 128
21 GND GND 22 22 HDA_SYNC_VGA 129 HDA_SYNC GND 130
23 GND GND 24 22 HDA_BITCLK_VGA 131 HDA_BCLK TV_CVBS/HDTV_Pb 132
D_EC_SMB_DA1 133 134 HDA_RST_VGA# 22
D_EC_SMB_CK1 SMB_DAT GND VGA_CRT_R
ACER MXM Design Guide V0.5 VGA_THERM_ALERT#
135 SMB_CLK VGA_RED 136 VGA_CRT_R 19
31 VGA_THERM_ALERT# 137 THERM# GND 138
9 VGA_CRT_HSYNC VGA_CRT_HSYNC 139 140 VGA_CRT_G VGA_CRT_G 19
VGA_CRT_VSYNC VGA_HSYNC VGA_GRN
19 VGA_CRT_VSYNC 141 VGA_VSYNC GND 142
19 VGA_DDC_CLK VGA_DDC_CLK 143 144 VGA_CRT_B VGA_CRT_B 19
PCIE_GTX_C_MRX_N15 VGA_DDC_DATA HDA_SDI VGA_BLU
25 PEX_RX15# PRSNT2# 26 19 VGA_DDC_DATA 145 HDA_SDO GND 146
PCIE_GTX_C_MRX_P15 27 28 PCIE_MTX_C_GRX_N15 22 HDA_SDIN3 1 2HDA_SDIN3_VGA 147 148 VGA_TZCLK- VGA_TZCLK- 18
PEX_RX15 PEX_TX15# PCIE_MTX_C_GRX_P15 R371 33_0402_5% IGP_UCLK# LVDS_UCLK# VGA_TZCLK
29 GND PEX_TX15 30 22 HDA_SDOUT_VGA 149 IGP_UCLK LVDS_UCLK 150 VGA_TZCLK 18
PCIE_GTX_C_MRX_N14 31 32 PM@ 151 152
PCIE_GTX_C_MRX_P14 PEX_RX14# GND PCIE_MTX_C_GRX_N14 R5981 GND GND
33 PEX_RX14 PEX_TX14# 34 JALA0 3VS 2 100K_0402_5% 153 DP_L3# LVDS_UTX3# 154
C 35 36 PCIE_MTX_C_GRX_P14 @ 155 156 C
PCIE_GTX_C_MRX_N13 GND PEX_TX14 ACIN_R DP_L3 LVDS_UTX3
37 PEX_RX13# GND 38 31 EC_ACIN 1 2 157 AC/BATT# GND 158
PCIE_GTX_C_MRX_P13 39 40 PCIE_MTX_C_GRX_N13 159 160 VGA_TZOUT2- VGA_TZOUT2- 18
PEX_RX13 PEX_TX13# PCIE_MTX_C_GRX_P13 D31 CH751H-40PT_SOD323-2 DP_L2# LVDS_UTX2# VGA_TZOUT2
41 GND PEX_TX13 42 161 DP_L2 LVDS_UTX2 162 VGA_TZOUT2 18
PCIE_GTX_C_MRX_N12 43 44 @ 163 164
PCIE_GTX_C_MRX_P12 PEX_RX12# GND PCIE_MTX_C_GRX_N12 GND GND VGA_TZOUT1-
45 PEX_RX12 PEX_TX12# 46 1 2 165 DP_L1# LVDS_UTX1# 166 VGA_TZOUT1- 18
47 48 PCIE_MTX_C_GRX_P12 167 168 VGA_TZOUT1 VGA_TZOUT1 18
PCIE_GTX_C_MRX_N11 GND PEX_TX12 R599 0_0402_5% DP_L1 LVDS_UTX1
49 PEX_RX11# GND 50 169 GND GND 170
PCIE_GTX_C_MRX_P11 51 52 PCIE_MTX_C_GRX_N11 @ 171 172 VGA_TZOUT0- VGA_TZOUT0- 18
PEX_RX11 PEX_TX11# PCIE_MTX_C_GRX_P11 DP_L0# LVDS_UTX0# VGA_TZOUT0
PCIE_GTX_C_MRX_N10
53 GND PEX_TX11 54 PVT(Check) 173 DP_L0 LVDS_UTX0 174 VGA_TZOUT0 18
55 PEX_RX10# GND 56 175 GND GND 176
PCIE_GTX_C_MRX_P10 57 58 PCIE_MTX_C_GRX_N10 177 178 VGA_TXCLK- VGA_TXCLK- 18
PEX_RX10 PEX_TX10# PCIE_MTX_C_GRX_P10 DVI_B_CLK LVDS_LCLK# VGA_TXCLK
59 GND PEX_TX10 60 179 DVI_B_CLK LVDS_LCLK 180 VGA_TXCLK 18
PCIE_GTX_C_MRX_N9 61 62 181 182
PCIE_GTX_C_MRX_P9 PEX_RX9# GND PCIE_MTX_C_GRX_N9 DVI_B_HPD/DVI_C_HPD/GND GND
63 PEX_RX9 PEX_TX9# 64 183 DP_AUX# LVDS_LTX3# 184
65 66 PCIE_MTX_C_GRX_P9 185 186
PCIE_GTX_C_MRX_N8 GND PEX_TX9 DP_AUX LVDS_LTX3
67 PEX_RX8# GND 68 187 GND DP_HPD 188
PCIE_GTX_C_MRX_P8 69 70 PCIE_MTX_C_GRX_N8 189 190 VGA_TXOUT2- VGA_TXOUT2- 18
PEX_RX8 PEX_TX8# PCIE_MTX_C_GRX_P8 DVI_B_TX2# LVDS_LTX2#/DVI_C_TX2# VGA_TXOUT2
71 GND PEX_TX8 72 191 DVI_B_TX2 LVDS_LTX2/DVI_C_TX2 192 VGA_TXOUT2 18
PCIE_GTX_C_MRX_N7 73 74 193 194
PCIE_GTX_C_MRX_P7 PEX_RX7# GND PCIE_MTX_C_GRX_N7 GND GND VGA_TXOUT1-
75 PEX_RX7 PEX_TX7# 76 195 DVI_B_TX1# LVDS_LTX1#/DVI_C_LTX1# 196 VGA_TXOUT1- 18
77 78 PCIE_MTX_C_GRX_P7 197 198 VGA_TXOUT1 VGA_TXOUT1 18
PCIE_GTX_C_MRX_N6 GND PEX_TX7 DVI_B_TX1 LVDS_LTX1/DVI_C_LTX1
79 PEX_RX6# GND 80 199 GND GND 200
PCIE_GTX_C_MRX_P6 81 82 PCIE_MTX_C_GRX_N6 201 202 VGA_TXOUT0- VGA_TXOUT0- 18
PEX_RX6 PEX_TX6# PCIE_MTX_C_GRX_P6 DVI_B_TX0# LVDS_LTX0#/DVI_C_LTX0# VGA_TXOUT0
83 GND PEX_TX6 84 203 DVI_B_TX0 LVDS_LTX0/DVI_C_LTX0 204 VGA_TXOUT0 18
PCIE_GTX_C_MRX_N5 85 86 20,31 DVI_DET DVI_DET 205 206
PCIE_GTX_C_MRX_P5 PEX_RX5# GND PCIE_MTX_C_GRX_N5 VGA_DVI_TXC- DVI_A_HPD GND I2CC_SDA
87 PEX_RX5 PEX_TX5# 88 20 VGA_DVI_TXC- 207 DVI_A_CLK# DDCC_DAT 208 I2CC_SDA 18
89 90 PCIE_MTX_C_GRX_P5 20 VGA_DVI_TXC VGA_DVI_TXC 209 210 I2CC_SCL I2CC_SCL 18
PCIE_GTX_C_MRX_N4 GND PEX_TX5 DVI_A_CLK DDCC_CLK ENVDD
91 PEX_RX4# GND 92 211 GND LVDS_PPEN 212 ENVDD 18
B PCIE_GTX_C_MRX_P4 PCIE_MTX_C_GRX_N4 VGA_DVI_TXD2- B
93 PEX_RX4 PEX_TX4# 94 20 VGA_DVI_TXD2- 213 DVI_A_TX2# LVDS_BL_BRGHT 214
95 96 PCIE_MTX_C_GRX_P4 20 VGA_DVI_TXD2 VGA_DVI_TXD2 215 216 ENBKL
GND PEX_TX4 DVI_A_TX2 LVDS_BLEN ENBKL 10,31
PCIE_GTX_C_MRX_N3 97 98 217 218 VGA_DVI_SDATA VGA_DVI_SDATA 20
PCIE_GTX_C_MRX_P3 PEX_RX3# GND PCIE_MTX_C_GRX_N3 VGA_DVI_TXD1- GND DDCB_DAT VGA_DVI_SCLK
99 PEX_RX3 PEX_TX3# 100 20 VGA_DVI_TXD1- 219 DVI_A_TX1# DDCB_CLK 220 VGA_DVI_SCLK 20
101 102 PCIE_MTX_C_GRX_P3 20 VGA_DVI_TXD1 VGA_DVI_TXD1 221 222 2.5VS
PCIE_GTX_C_MRX_N2 GND PEX_TX3 DVI_A_TX1 2V5RUN
103 PEX_RX2# GND 104 223 GND GND 224
PCIE_GTX_C_MRX_P2 105 106 PCIE_MTX_C_GRX_N2 20 VGA_DVI_TXD0- VGA_DVI_TXD0- 225 226 3VS
PEX_RX2 PEX_TX2# PCIE_MTX_C_GRX_P2 VGA_DVI_TXD0 DVI_A_TX0# 3V3RUN
107 GND PEX_TX2 108 20 VGA_DVI_TXD0 227 DVI_A_TX0 3V3RUN 228
229 GND 3V3RUN 230

231 GND GND 232

QUASA_CA0481-230N00
CONN@ QUASA_CA0481-230N00 3VS
DVT CONN@
DVT
DVT(JALA0)

2
1V8RUN 2.5VS 5VS

G
1 3 D_EC_SMB_DA1
31,40 EC_SMB_DA1

S
1 1 1 1 Q50
C598 C599 C76 C504 2N7002_SOT23
1.05VS 1.05VS 1.05VS 1.05VS 1.05VS PM@

2
4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

G
PM@ 2 2 PM@ PM@ 2 PM@ 2
1 1 1 1 1 1 3 D EC_SMB_CK1
31,40 EC_SMB_CK1
C179 C230 C138 C459 C170

S
@ @ @ @ @ Q51
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2N7002_SOT23
A 2 2 2 2 2 A
PM@ DVT

For Return Path between GND and 1.05V Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT AL
SCHEMATIC MB A4221
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401552
Date: Friday, May 16, 2008 Sheet 17 of 50
5 4 3 2 1
 5 3 2 1

D +3VS D

LCD POWER CIRCUIT

5
U22
+LCDVDD

P
NC
+3V +3VS INVTPWM 4 Y A 2 DPST_PWM 10
W=60mils

G
R313 NC7SZ14P5X_NL_SC70-5

3
1
300_0603_5% 1 @
R312 C370
100K_0402_5%

3 2
4.7U_0805_10V4Z

2
2

G
R302

2
Q39B

3
S
G +3VS 1 2 INVTPWM 1 3
2N7002DW-T/R7_SOT363-6 5 2 1 2 Q38

S
R309 1K_0402_5% AO3413_SOT23-3 10K_0402_5%
D
1
4

1
Q37

6
C373 +LCDVDD @
W=60mils 2N7002_SOT23 For GMCH DPST
GM@ Q39A 0.047U_0402_16V7K @
R310 1 2
10 GMCH_ENVDD 2 0_0402_5% 2
PM@ 2N7002DW-T/R7_SOT363-6 1 1
R311 1 2 0_0402_5% C372 C369
17 ENVDD

1
1

4.7U 0805_10V4Z 0.1U_0402_16V4Z

R307 2 2
100K_0402_5%
2

C C
TXOUT0- 1 4 VGA_TXOUT0-
VGA_TXOUT0- 17
TXOUT0+ 2 3 VGA_TXOUT0+
VGA_TXOUT0+ 17
RP2 PM@ 0_0404_4P2R_5%
TXOUT1- 1 4 VGA_TXOUT1-
VGA_TXOUT1- 17
TXOUT1+ 2 3 VGA_TXOUT1+
VGA_TXOUT1+ 17
RP4 PM@ 0_0404_4P2R_5%
TXOUT2- 1 4 VGA_TXOUT2-
+3VS VGA_TXOUT2- 17
TXOUT2+ 2 3 VGA_TXOUT2+
VGA_TXOUT2+ 17
RP6 PM@ 0_0404_4P2R_5%
TXCLK- 1 4 VGA_TXCLK-
VGA_TXCLK- 17

1
TXCLK+ 2 3 VGA_TXCLK+
VGA_TXCLK+ 17
R303 RP8 PM@ 0_0404_4P2R_5%
TZOUT0- 1 4 VGA_TZOUT0-
VGA_TZOUT0- 17
4.7K_0402_5% TZOUT0+ 2 3 VGA_TZOUT0+
D18 VGA_TZOUT0+ 17
2 RP10 PM@ 0_0404_4P2R_5%
BKOFF# 1 2 DISPOFF# TZOUT1- 1 4 VGA_TZOUT1-
31 BKOFF# VGA_TZOUT1- 17
TZOUT1+ 2 3 VGA_TZOUT1+
VGA_TZOUT1+ 17
EMI RP12 PM@ 0_0404_4P2R_5%
+INVPWR_B+ CH751H-40PT_SOD323-2 TZOUT2- VGA_TZOUT2-
1 4 VGA_TZOUT2- 17
TZOUT2+ 2 3 VGA_TZOUT2+
VGA_TZOUT2+ 17
L24 2 1 B+ RP14 PM@ 0_0404_4P2R_5%
W=40mils KC FBM-L11-201209-221LMAT_0805 C367 820P_0402_50V7K TZCLK- 1 4 VGA_TZCLK-
VGA_TZCLK- 17
DAC_BR G 1 2 TZCLK+ 2 3 VGA_TZCLK+
VGA_TZCLK+ 17
L23 2 1 C366 820P_0402_50V7K RP16 PM@ 0_0404_4P2R_5%
KC FBM-L11-201209-221LMAT_0805 INVTPW 1 2
1 1 C365 820P_0402_50V7K
C364 C363 DISPOF # 1 2
I2CC_SCL 1 4 GMCH_LCD_CLK GMCH_LCD_CLK 10
680P_0402_50V7K 68P_0402_50V8J I2CC_SDA 2 3 GMCH_LCD_DATA GMCH_LCD_DATA 10
2 2 RP1 GM@ 0_0404_4P2R_5%

B B
Change 220P to 820P DVT(JALA0)
DVT(JALA0) LCD/PANEL BD. Conn. TXOUT0- 2 3 GMCH_TXOUT0-
GMCH_TXOUT0- 10
TXOUT0+ 1 4 GMCH_TXOUT0+
GMCH_TXOUT0+ 10
RP3 GM@ 0_0404_4P2R_5%
TXOUT1- 2 3 GMCH_TXOUT1-
GMCH_TXOUT1- 10
JLVDS1 TXOUT1+ 1 4 GMCH_TXOUT1+
GMCH_TXOUT1+ 10
42 41 DAC_BRIG RP5 GM@ 0_0404_4P2R_5%
GND GND DAC_BRIG 31
+INVPWR_B+ 40 39 TXOUT2- 2 3 GMCH_TXOUT2-
40 39 GMCH_TXOUT2- 10
38 37 INVTPWM R301 1 2 0_0402_5% TXOUT2+ 1 4 GMCH_TXOUT2+
38 37 INVT_PWM 31 GMCH_TXOUT2+ 10
+3VS 36 35 DISPOFF# RP7 GM@ 0_0404_4P2R_5%
I2CC_SCL 36 35 TXCLK- GMCH_TXCLK-
17 I2CC_SCL 34 34 33 33 +LCDVDD 2 3 GMCH_TXCLK- 10
I2CC_SDA 32 31 TXCLK+ 1 4 GMCH_TXCLK+
17 I2CC_SDA 32 31 GMCH_TXCLK+ 10
30 29 W=60mils RP9 GM@ 0_0404_4P2R_5%
TZOUT0- 30 29 TZOUT0- GMCH_TZOUT0-
28 28 27 27 2 3 GMCH_TZOUT0- 10
TZOUT0+ 26 25 TXOUT0- +LCDVDD TZOUT0+ 1 4 GMCH_TZOUT0+
26 25 +3VS GMCH_TZOUT0+ 10
24 23 TXOUT0+ RP11 GM@ 0_0404_4P2R_5%
TZOUT1+ 24 23 TZOUT1- GMCH_TZOUT1-
22 22 21 21 2 3 GMCH_TZOUT1- 10
TZOUT1- 20 19 TXOUT1- TZOUT1+ 1 4 GMCH_TZOUT1+
20 19 GMCH_TZOUT1+ 10
18 17 TXOUT1+ 1 1 1 RP13 GM@ 0_0404_4P2R_5%
TZOUT2+ 18 17 C1 C371 C368 TZOUT2- GMCH_TZOUT2-
16 16 15 15 2 3 GMCH_TZOUT2- 10
TZOUT2- 14 13 TXOUT2+ TZOUT2+ 1 4 GMCH_TZOUT2+
14 13 GMCH_TZOUT2+ 10
12 11 TXOUT2- 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z RP15 GM@ 0_0404_4P2R_5%
TZCLK- 12 11 2 2 2 TZCLK- GMCH_TZCLK-
10 10 9 9 2 3 GMCH_TZCLK- 10
TZCLK+ 8 7 TXCLK- TZCLK+ 1 4 GMCH_TZCLK+
8 7 GMCH_TZCLK+ 10
0_0402_5% 6 5 TXCLK+ RP17 GM@ 0_0404_4P2R_5%
6 5
23 USB20_N6
R298 1 2USB20_CMOS_N6 4 4 3 3
R297 1 2USB20_CMOS_P6 2 1 +3VS
23 USB20_P6 2 1
0_0402_5%
ACES_88242-4001
CONN@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDEN IAL
SCHEMATIC MB A4221
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401552
Date Friday, May 16, 2008 Sheet 18 of 50
5 3 2 1
 A B C D E

CRT Connector D24 D23 D22

W=40mils
+5VS +R_CRT_VCC +CRT_VCC
DAN217_SC59 DAN217_SC59 DAN217_SC59
D5 F1 W=40mils

1
2 1 1 2

RB491D_SC59-3 1.1A_6VDC_FUSE
1

JALA0 DVT C65

3
0.1U_0402_16V4Z
2
1
+3VS 1

CRT_R 1 2 CRT_R_1 1 2 CRT_R_2 JCRT1

L30 FCM2012C-800_0805 L31 FCM2012C-800_0805 6
11
CRT_G 1 2 CRT G 1 1 2 CRT_G_2 1
L28 FCM2012C-800_0805 L29 FCM2012C-800_0805 7
12
CRT_B 1 2 CRT_B_1 1 2 CRT_B_2 2
L26 FCM2012C-800_0805 L27 FCM2012C-800_0805 8

1
13

1
R368 R362 1 1 1 1 1 1 1 1 1 3
R348 C419 C409 C401 C423 C418 C408 9
C420 C410 C402 14
150_0402_1% GM@ GM@ GM@ 10P_0402_50V8J 10P_0402_50V8J 10P_0402_50V8J 4

2
2 2 2 GM@ 2 GM@ 2 GM@ 2 GM@ 2 GM@ 2 2 GM@ 10 16

2
150_0402_1% 10P_0402_50V8J 10P_0402_50V8J 22P_0402_50V8J DVT(Check) 15 17
150_0402_1% 22P_0402_50V8J 22P_0402_50V8J 1 5
10P_0402_50V8J change to 12pf for Discrete C28
DVT(Check) DVT(Check) SUYIN_070549FR015S208CR
1 2 CRT_HSYNC_2 CONN@
L2 10_0603_5% 2
change to 15pf for Discrete change to 15pf for ATI M82 100P_0402_50V8J
CRT_DET# 23
1 2 CRT_VSYNC_2
L1 10_0603_5% 1 1 DSUB_12

2
+CRT_VCC C34
DVT(Check) C69 1 R19
1 2 2 1 10P_0402_50V8J 10P_0402_50V8J 100K_0402_5%
C71 0.1U_0402_16V4Z R39 10K_0402_5% 2 2
DSUB_15

1
5

1
2 U5 C75 2 2
68P_0402_50V8J 1

OE#
CRT_HSYNC 2 4 CRT_HSYNC_1 2 1
A Y D_CRT_HSYNC 38
R653 C20 +CRT_VCC

G
MAIN@ 0_0402_5% 68P_0402_50V8J
SN74AHCT1G125DCKR_SC70-5 2

3
+CRT_VCC

1 2 DVT
C35 0.1U_0402_16V4Z

1
U3

OE#
CRT_VSYNC 2 4 CRT_VSYNC_1 2 1
A Y D_CRT_VSYNC 38
R654

G
MAIN@ 0_0402_5%
SN74AHCT1G125DCKR_SC70-5

3
+CRT_VCC

Place closed to chipset

+3VS pull-up 10k on AMD M82M MXM side

1
pull-up 2.2k on GPU side
R40 R23 1 2 R373
4.7K_0402_5% 4.7K_0402_5% PM@ 0_0402_5% VGA_DDC_DATA 17

2
3 3

G
NOTE: L : A-->B1
R372 GM@ 0_0402_5%
R67 1 2 GM@ 30.1_0402_1% CRT_VSYNC H: A-->B2 DSUB_12 1 3 2 1
10 GMCH_CRT_VSYNC 38 D_DDC_DATA GMCH_CRT_DATA 10

S
R83 +5VS
10 GMCH_CRT_HSYNC 1 2 GM@ 30.1_0402_1% CRT_HSYNC Q52

2
2N7002_SOT23

G
R374 1 2 GM@ 0_0402_5% CRT_B_S U26
10 GMCH_CRT_B
16 DSUB_15 1 3 2 1
R378 1 CRT_G_S VCC 38 D_DDC_CLK GMCH_CRT_CLK 10
2 GM@ 0_0402_5% 1 R377

S
10 GMCH_CRT_G 28,31,34,38 EC_DOCKIN# SEL
15 2 Q53 GM@ 0_0402_5%
OE# 1B1 D_CRT_R 38
R390 1 2 GM@ 0_0402_5% CRT_R_S 5 2N7002_SOT23
10 GMCH_CRT_R 2B1 D_CRT_G 38
3B1 11 D_CRT_B 38 1 2 R380 VGA_DDC_CLK 17
CRT_R S 4 14 PM@ 0_0402_5%
CRT_G S 7 1A 4B1
CRT_B S 9 2A DVT
3A CRT_R
pull-up 2.2k on GPU side
12 4A 1B2 3
6 CRT_G pull-up 10k on AMD M82M MXM side
R66 2B2
17 VGA_CRT_VSYNC 1 2 PM@ 0_0402_5% CRT_VSYNC
3B2 10 CRT_B
4B2 13
R82 1 2 PM@ 0_0402_5% CRT_HSYNC 8
17 VGA_CRT_HSYNC GND
R375 1 2 PM@ 0_0402_5% CRT_B_S FSAV330MTC_TSSOP16
17 VGA_CRT_B
MAIN@
R379 1 2 PM@ 0_0402_5% CRT_G_S
17 VGA_CRT_G
R391 1 2 PM@ 0_0402_5% CRT_R_S R583 0_0402_5%
17 VGA_CRT_R
1 2 VALUE@
R584 0_0402_5%
1 2 VALUE@
R585 0_0402_5%
1 2 VALUE@

JALA0

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDEN IAL
SCHEMATIC MB A4221
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401552
Date Friday, May 16, 2008 Sheet 19 of 50
A B C D E
 5 4 3 2 1

HDMI_5V_OUT HDMI_5V_OUT
DDC to Docking DDC to HDMI CONN
3.3V Level JHDMI1
3.3V Level HDMI_HPD 19
MP MP HDMI_5V_OUT 18
HP_DET
+5V

1
EC_DOCKIN EC_DOCKIN#_S0 17
38 EC_DOCKIN 38 EC_DOCKIN#_S0 DDC/CEC_GND
R85 R84 R86 R91 HDMI_SDATA 16
R600 1 PM@ SDA
3VS 2 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5% HDMI_SCLK 15 SCL

2
G

G
D 5VS R601 1 @ 2 2.2K_0402_5% 14 D
Reserved
13

2
VGA_DVI_SCLK VGA_DVI_SCLK HDMI_SCLK HDMI_R_CK- CEC
17 VGA_DVI_SCLK 3 1 D_DVI_SCLK 38 3 1 12 CK- GND 20

D
11 CK_shield GND 21
3VS R602 1 PM@ 2 4.7K_0402_5% HDMI_R_CK 10 22
CK+ GND

2
G

G
5VS R603 1 @ 2 2.2K_0402_5% Q7 Q8 HDMI_R_D0- 9 23
BSH111_SOT23 BSH111_SOT23 D0- GND
8 D0_shield
17 VGA_DVI_SDATA VGA_DVI_SDATA 3 1 D_DVI_SDATA 38 VGA_DVI_SDATA 3 1 HDMI_SDATA HDMI_R_D0 7
HDMI_R_D1- D0+

D
6 D1-
5
DVT Q47 DVT Q6 Place closed to JHDMI1 HDMI_R_D1 4
D1_shield
D1+
BSH111_SOT23 BSH111_SOT23 HDMI_R_D2- 3 D2-
2 D2_shield
HDMI_R_D2 1 D2+
TYCO_1939864-1
MP:Update HDMI Hot Plug DET circuit. CONN@

HDMI_5V_OUT 1 2 D_DVI_DET 38
R414 0_0402_5%
HDMI_HPD
1
C435 2 1 HDMI_5V_OUT
3VS

1
R396 R412 1 W=40mils
5

0.1U_0402_16V4Z 2.2K_0402_5% 100K_0402_5% C430 D35 D7 F2

2 CH751H-40PT_SOD323-2 HDMI_5V
2 1 1 2
P

OE#

5VS
2 4 1 2 DVI DET 17 31 0.1U_0402_16V4Z @ 1 HDMI_CLK- 1 2 HDMI_R_CK-
A Y R686 0_0402_5% 2 RB491D_SC59-3 1.1A_6VDC_FUSE R415 0_0402_5%

2
G

PM@ C441
C U29 1 2 OE 0.1U_0402_16V4Z L33 C
MP
3

74AHCT1G125GW_SOT353-5 R672 @ 0_0402_5% 2

1 1 2 2
PVT2 EC_DVI_DET 31
4 4 3 3
@ WCM-2012-900T_0805
U39 HDMI_5V_OUT
VGA_DVI_SCLK 2 8 HDMI_CLK 1 2 HDMI_R_CK
VGA_DVI_SDATA 1A VCC D_DVI_SCLK R418 0_0402_5%
5 2A 1B 3
EC_DOCKIN# S0 1 6 D_DVI_SDATA 3VS
1OE# 2B
7 2OE# GND 4
HDMI_TX0- 1 2 HDMI_R_D0-

2
SN74CBTD3306CPWR_TSSOP8 R419 0_0402_5%
@
HDMI_5V_OUT D25 L34
U40 SS1040_SOD123 1 1 2 2
VGA_DVI_SCLK 2 8

1
VGA_DVI_SDATA 1A VCC HDMI_SCLK
5 2A 1B 3
EC_DOCKIN 1 6 HDMI_SDATA 3VS_D80 4 3
1OE# 2B 4 3
7 2OE# GND 4
@ WCM-2012-900T_0805
SN74CBTD3306CPWR_TSSOP8

11
15
24
36
48

22
DVT 1 1

2
6
@ U24 C421 C417 HDMI_TX0 1 2 HDMI_R_D0
R421 0_0402_5%

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7

AVDD
0.1U_0402_ 6V4Z
VGA_DVI_TXC 2 2
17 VGA_DVI_TXC 4 D0+
3VS 1 2 VGA_DVI_TXC- 5 0.1U_0402_16V4Z HDMI_TX1- 1 2 HDMI_R_D1-
17 VGA_DVI_TXC- D0-
R357 4.7K_0402_5% VGA_DVI_TXD0 7 R422 0_0402_5%
B 17 VGA_DVI_TXD0 D1+ B
1 2 MS VGA_DVI_TXD0- 8 25 HDMI_TX2-
17 VGA_DVI_TXD0- D1- D3-_B
R359 @ 0_0402_5% VGA_DVI_TXD1 9 26 HDMI_TX2 L35
17 VGA_DVI_TXD1 D2+ D3+_B
VGA_DVI_TXD1- 10 28 HDMI_TX1- 1 2
17 VGA_DVI_TXD1- D2- D2-_B 1 2
3VS 2 1 OE VGA_DVI_TXD2 12 29 HDMI_TX1
17 VGA_DVI_TXD2 D3+ D2+_B
D21 CH751H-40PT_SOD323-2 VGA_DVI_TXD2- 13 31 HDMI_TX0-
17 VGA_DVI_TXD2- D3- D1-_B
1 2 32 HDMI_TX0 4 3
DVT R349 4.7K_0402_5%
T16 PAD @ 16 SEL_OUT
D1+_B
D0-_B 34 HDMI_CLK- 4 3
PAD @ 55 35 HDMI_CLK @ WCM-2012-900T_0805
T15 SEL_IN D0+_B
3VS 1 2 19 HDMI_TX1 1 2 HDMI_R_D1
14,15,16 D_CK_SCLK SCL/S3
R343 @ 4.7K_0402_5% 20 37 D_DVI_TXD2- 38 R426 0_0402_5%
14,15,16 D_CK_SDATA SDA/S2 D3-_A
1 2 A2 38 D_DVI_TXD2 38
R351 0_0402_5% MS D3+_A
1 MS D2-_A 40 D_DVI_TXD1- 38
3VS 1 2 PAD @ 17 41 D_DVI_TXD1 38 HDMI_TX2- 1 2 HDMI_R_D2-
T17 TEST_OUT D2+_A
R342 @ 4.7K_0402_5% 54 43 D_DVI_TXD0- 38 R430 0_0402_5%
A3 OE TEST_IN D1-_A
1 2 56 OE D1+_A 44 D_DVI_TXD0 38
R350 0_0402_5% 46 D_DVI_TXC- 38 L36
A0 D0-_A
49 A0/S4 D0+_A 47 D_DVI_TXC 38 1 1 2 2
A1 50
A2 A1/S5
3VS 1 2 51 A2/S6 NC 18
R345 @ 4.7K_0402_5% A3 52 57 4 3
A0 A3/S7 T-pad 4 3
1 2
VSS10

AVSS

R353 0_0402_5% @ WCM-2012-900T_0805

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9

NOTE: L : D-->A
3VS 1 2
R344 @ 4.7K_0402_5% H: D-->B HDMI_TX2 1 2 HDMI_R_D2
1 2 A1 PI3HDMI412ADZBE_TQFN56_8X8 R433 0_0402_5%
3
14
21
27
30
33
39
42
45
53

23

R352 0_0402_5%

A A
SMBus Address: 1100 000X (b)

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT AL
SCHEMATIC MB A4221
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401552
Date: Friday, May 16, 2008 Sheet 20 of 50
5 4 3 2 1
 5 4 3 2 1

3VS
DMI for ESI-compatible operation
RP44 Low= DMI for ESI-compatible operation
1 8 PCI_REQ#2 PCI_GNT#1 High= Default* (Internal pull-up)
2 7 PCI_FRAME#
3 6 PCI_DEVSEL#
4 5 PCI_REQ#1
D D
8.2K_1206_8P4R_5%
25 PCI_AD[0..31] U10B
RP46 PCI_AD0 D11 F1 PCI_REQ#0
AD0 REQ0# PCI_REQ#0 25
1 8 PCI_PIRQE# PCI_AD1 C8 G4 PCI_GNT#0
AD1 GNT0# PCI_GNT#0 25
PCI_PERR# PCI_AD2 PCI_REQ#1
2
3
7
6 PCI_IRDY# PCI_AD3
D9
E12
AD2 PCI REQ1#/GPIO50 B6
A7 PCI_GNT#1 @
AD3 GNT1#/GPIO51 PAD T4
4 5 PCI_PLOCK# PCI_AD4 E9 F13 PCI_REQ#2
PCI_AD5 AD4 REQ2#/GPIO52 PCI_GNT#2 @
C9 AD5 GNT2#/GPIO53 F12 PAD T22
8.2K_1206_8P4R_5% PCI_AD6 E10 E6 PCI_REQ#3
PCI_AD7 AD6 REQ3#/GPIO54 PCI_GNT#3
B7 AD7 GNT3#/GPIO55 F6
PCI_AD8 C7
PCI_AD9 AD8 PCI_CBE#0
C5 AD9 C/BE0# D8 PCI_CBE#0 25
PCI_AD10 G11 B4 PCI_CBE#1
3VS AD10 C/BE1# PCI_CBE#1 25
PCI_AD11 F8 D6 PCI_CBE#2
AD11 C/BE2# PCI_CBE#2 25
PCI_AD12 F11 A5 PCI_CBE#3
AD12 C/BE3# PCI_CBE#3 25
RP47 PCI_AD13 E7
PCI_PIRQH# PCI_AD14 AD13 PCI_IRDY#
1 8 A3 AD14 IRDY# D3 PCI_IRDY# 25
2 7 PCI_REQ#0 PCI_AD15 D2 E3 PCI_PAR
AD15 PAR PCI_PAR 25
3 6 PCI_PIRQG# PCI_AD16 F10 R1 PCI_RST#
AD16 PCIRST# PCI_RST# 25
4 5 PCI_PIRQB# PCI_AD17 D5 C6 PCI_DEVSEL#
AD17 DEVSEL# PCI_DEVSEL# 25
PCI_AD18 D10 E4 PCI_PERR# Place closely pin B10
8.2K_1206_8P4R_5% PCI_AD19 AD18 PERR# PCI_PLOCK#
B3 AD19 PLOCK# C2
PCI_AD20 F7 J4 PCI_SERR#
RP48 PCI_AD21 AD20 SERR# PCI_STOP# CLK_PCI_ICH
C3 AD21 STOP# A4 PCI_STOP# 25
1 8 PCI_SERR# PCI_AD22 F3 F5 PCI_TRDY#
AD22 TRDY# PCI_TRDY# 25

2
2 7 PCI_PIRQA# PCI_AD23 F4 D7 PCI_FRAME#
AD23 FRAME# PCI_FRAME# 25
3 6 PCI_PIRQC# PCI_AD24 C1
PCI_PIRQF# PCI_AD25 AD24 PLT_RST# R388
4 5 G7 AD25 PLTRST# C14 PLT_RST# 8,23,26,27,31
C PCI_AD26 H7 D4 CLK_PCI_ICH 10_0402_5% C
AD26 PCICLK CLK_PCI_ICH 16
8.2K_1206_8P4R_5% PCI_AD27 D1 R2 @

1
PCI_AD28 AD27 PME#
G5 AD28
RP45 PCI_AD29 H6 1
PCI_REQ#3 PCI_AD30 AD29 C425
1 8 G1 AD30
2 7 PCI_TRDY# PCI_AD31 H3 10P_0402_50V8J
PCI_STOP# AD31 @
3 6
PCI_PIRQD# 2
4 5

8.2K_1206_8P4R_5% PCI_PIRQA# J5
Interrupt I/F H4 PCI_PIRQE#
PIRQA# PIRQE#/GPIO2 PCI_PIRQE# 25
PCI_PIRQB# E1 K6 PCI_PIRQF#
PCI_PIRQC# PIRQB# PIRQF#/GPIO3 PCI_PIRQG#
J6 PIRQC# PIRQG#/GPIO4 F2
PCI_PIRQD# C4 G2 PCI_PIRQH#
PIRQD# PIRQH#/GPIO5
ICH9-M ES_FCBGA676
ICH9MB@
DVT ICH9-M: SA00002AN10
(S IC NH82801IBM QP23 A2 FCBGA 676P ICH9M)
A16 Swap Override Strap PVT ICH9-M: SA00002JH00
Low= A16 swap override Enable (S IC AF82801IBM QT09 A3 PBG 676P ICH9M)
PCI_GNT#3 High= Default*
Pre-MP ICH9-M: SA00002JH70
(S IC AF82801IBM SLB8Q A3 676P ICH9M ABO!)
R420 1 2 1K_0402_5% PCI_GNT#3
@
B B

3VS

5
U7
Boot BIOS Strap PLT_RST# 2 B

P
Y 4 PLT_RST_BUF# 29
PCI_GNT#0 SPI_CS#1 Boot BIOS Loaction 1 A

1
NC7SZ08P5X_NL_SC70-5

3
R57
0 1 SPI 100K_0402_5%

1 0 PCI

2
3VS

1 1 LPC*

5
U8
2 B

P
1
Y 4 2
R59
1
100_0402_5%
PLTRST_VGA# 17 For VGA/B
A
G
R93 1 2 1K_0402_5% PCI_GNT#0 PM@

1
@ NC7SZ08P5X_NL_SC70-5
3

PM@ R58
R382 1 2 1K_0402_5% 100K_0402_5%
SPI_CS#1 23
@ PM@

2
A A

JALA0

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT AL
SCHEMATIC MB A4221
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401552
Date: Friday, May 16, 2008 Sheet 21 of 50
5 4 3 2 1
 5 4 3 2 1

RTCVCC CMOS Settings R376 TPM Settings R381

C117
18P_0402_50V8J Clear CMOS SHORT Clear ME RTC Registers SHORT
2 1 ICH_RTCX1 1.05VS

1
Keep CMOS OPEN Keep ME RTC Registers OPEN

10M_0402_5%
R411 X1 H_DPRSTP# 2 1

1
3 4 R476 @ 56_0402_5%
1M_0402_5% NC OUT H_DPSLP# 2 1

R78
32.768KHZ_12.5P_MC-306 2 1 R477 @ 56_0402_5%
2

SM_INTRUDER# NC IN
C118 U10A

2
D 18P_0402_50V8J C23 K5 LPC_AD0 D
RTCX1 FWH0/LAD0 LPC_AD0 31
2 1 ICH_RTCX2 C24 K4 LPC_AD1
RTCVCC RTCX2 FWH1/LAD1 LPC_AD1 31
L6 LPC_AD2
FWH2/LAD2 LPC_AD2 31
RTCVCC 1 2 ICH_RTCRST# A25 K2 LPC_AD3
RTCRST# FWH3/LAD3 LPC_AD3 31
R394 RTCVCC 1 2 ICH_SRTCRST# F20
20K_0402_5% R395 SM_INTRUDER# SRTCRST# LPC_FRAME#
C22 INTRUDER# FWH4/LFRAME# K3 LPC_FRAME# 31
1

20K_0402_5%

RTC

LPC
R408 close to RAM door close to RAM door ICH_INTVRMEN B22 J3
332K_0402_1% INTVRMEN LDRQ0#
A22 LAN100_SLP LDRQ1#/GPIO23 J1
1 2 1 2 R423 2 1 10K_0402_5% 3VS
R376 @ R381 @ E25 N7 EC_GA20
EC_GA20 31
2

10K_0603_5% 10K_0603_5% GLAN_CLK A20GATE H_A20M#

A20M# AJ27 H_A20M# 4
ICH_INTVRMEN C426 C453 C13
1U_0603_10V6K 1U_0603_10V6K LAN_RSTSYNC DPRSTP# R462 1 0_0402_5% H_DPRSTP#
High = Internal VR Enable DPRSTP# AJ25
DPSLP# R463 1
2
0_0402_5% H_DPSLP#
H_DPRSTP# 5,8,46
1 2 1 2 F14 LAN_RXD0 DPSLP# AE23 2 H_DPSLP# 5
G13 LAN_RXD1
D14 AJ26 FERR# 1 2 H_FERR#
LAN_RXD2 FERR# H_FERR# 4

LAN / GLAN
R461 56_0402_5%
3VS D13 AD22 H_PWRGOOD 2 1
LAN_TXD_0 CPUPWRGD H_PWRGOOD 5 1.05VS
D12 R475 56_0402_5%
LAN_TXD_1 H_IGNNE#
E13 LAN_TXD_2 IGNNE# AF25 H_IGNNE# 4
1

R163 Need check ICH_GPIO56 B10 AE22 H_INIT# 2 1

GPIO56 INIT# H_INIT# 4 3VS
AG25 H_INTR R428 10K_0402_5%

CPU
INTR H_INTR 4
10K_0402_5% 1.5VS_PCIE_ICH 1 2 GLAN_COMP B28 L3 EC_KBRST#
GLAN_COMPI RCIN# EC_KBRST# 31
R397 24.9_0402_1% B27
2

HDA_BITCLK_ICH GLAN_COMPO H_NMI

33 HDA_BITCLK_MDC 1 2 NMI AF23 H_NMI 4
SATA_LED# R467 33_0402_5% AF6 AF24 H_SMI#
HDA_BIT_CLK SMI# H_SMI# 4
33 HDA_SYNC_MDC 1 2 HDA_SYNC_ICH AH4 R258 need to place within 2" of ICH9M
R469 33_0402_5% HDA_SYNC H_STPCLK#
C
STPCLK# AH27 H_STPCLK# 4 R257 must be place within 2" of R258 w/o stub. C
1 2 HDA_RST_ICH# AE7
33 HDA_RST_MDC# HDA_RST#
R470 33_0402_5% AG26 THRMTRIP_ICH# R460 1 2 54.9_0402_1% H_THERMTRIP#
3V THRMTRIP# H_THERMTRIP# 4,8
34 HDA_SDIN0 AF4 HDA_SDIN0
33 HDA_SDIN1 AG4 HDA_SDIN1 TP12 AG27 2 1 1.05VS
8 HDA_SDIN2 AH3 R474 56_0402_5%
HDA_SDIN2
AE5

IHDA
17 HDA_SDIN3 HDA_SDIN3
1

SATA4RXN AH11
R77 1 2 HDA_SDOUT_ICH AG5 AJ11
33 HDA_SDOUT_MDC HDA_SDOUT SATA4RXP
R468 33_0402_5% AG12
10K_0402_5% SATA4TXN
AG7 HDA_DOCK_EN#/GPIO33 SATA4TXP AF12
AE8
2

HDA_DOCK_RST#/GPIO34
ICH_GPIO56 32 SATA_LED# SATA_LED# AG8 SATALED#
SATA5RXN AH9
30 SATA_DTX_C_IRX_N0 SATA_DTX_C_IRX_N0 AJ16 AJ9
SATA_DTX_C_IRX_P0 SATA0RXN SATA5RXP
SATA for HDD 30 SATA_DTX_C_IRX_P0
SATA_ITX_DRX_N0
AH16 SATA0RXP SATA5TXN AE10
AF17 SATA0TXN SATA5TXP AF10
SATA_ITX_DRX_P0 AG17 SATA0TXP CLK_PCIE_SATA#
SATA_CLKN AH18 CLK_PCIE_SATA# 16

SATA
30 SATA_DTX_C_IRX_N1 SATA_DTX_C_IRX_N1 AH13 AJ18 CLK_PCIE_SATA
SATA1RXN SATA_CLKP CLK_PCIE_SATA 16
SATA for ODD 30 SATA_DTX_C_IRX_P1 SATA_DTX_C_IRX_P1 AJ13 AJ7 SATARBIAS
SATA_ITX_DRX_N1 SATA1RXP SATARBIAS# R162 1
AG14 SATA1TXN SATARBIAS AH7 2 24.9_0402_1%
SATA_ITX_DRX_P1 AF14 10mils width less than 500mils
SATA1TXP

ICH9-M ES_FCBGA676 ICH9MB@ DVT ICH9-M: SA00002AN10 PVT ICH9-M: SA00002JH00

(S IC NH82801IBM QP23 A2 FCBGA 676P (S IC AF82801IBM QT09 A3 PBG 676P ICH9M)
B HDA_BITCLK_ICH B
34 HDA_BITCLK_AUDIO 1
R471
2
33_0402_5%
close ICH9 ICH9M)
Pre-MP ICH9-M: SA00002JH70
34 HDA_SYNC_AUDIO 1 2 HDA_SYNC_ICH SATA_ITX_DRX_N0 1 2 SATA_ITX_C_DRX_N0
HDA for AUDIO R473 33_0402_5% C506 0.01U_0402_16V7K SATA_ITX_C_DRX_N0 30 (S IC AF82801IBM SLB8Q A3 676P ICH9M ABO!)
1 2 HDA_RST_ICH# SATA_ITX_DRX_P0 1 2 SATA_ITX_C_DRX_P0
34 HDA_RST_AUDIO# SATA_ITX_C_DRX_P0 30
R456 33_0402_5% C505 0.01U_0402_16V7K
34 HDA_SDOUT_AUDIO 1 2 HDA_SDOUT_ICH
R472 33_0402_5%
SATA_ITX_DRX_N1 1 2 SATA_ITX_C_DRX_N1
C502 0.01U_0402_16V7K SATA_ITX_C_DRX_N1 30
GM@ 1 2 HDA_BITCLK_ICH SATA_ITX_DRX_P1 1 2 SATA_ITX_C_DRX_P1
8 HDA_BITCLK_MCH SATA_ITX_C_DRX_P1 30
R457 33_0402_5% C501 0.01U_0402_16V7K
8 HDA_SYNC_MCH GM@ 1 2 HDA_SYNC_ICH
R459 33_0402_5%
MAINPWON 40,41
HDA for GMCH GM@ 1 2 HDA_RST_ICH#
8 HDA_RST_MCH#
R466 33_0402_5%
8 HDA_SDOUT_MCH GM@ 1 2 HDA_SDOUT_ICH R175

1
R458 33_0402_5% @ 330_0402_5% C
1.05VS 1 2 2 Q14
B
PM@ 1 2 HDA_BITCLK_ICH E 2SC2411K_SOT23
17 HDA_BITCLK_VGA

3
R480 33_0402_5% @
17 HDA_SYNC_VGA PM@ 1 2 HDA_SYNC_ICH
VCC_HDA_ICH R479 33_0402_5% H_THERMTRIP#
HDA for VGA PM@ 1 HDA_RST_ICH#
DVT(Check)
17 HDA_RST_VGA# 2
R478 1K_0402_5%
17 HDA_SDOUT_VGA PM@ 1 2 HDA_SDOUT_ICH
R454 R481 33_0402_5%
A
1K_0402_5% Flash Descriptor Security Override Strap A
@ Low= Descriptor Security override
XOR Chain Entrance Strap GPIO33
HDA_SDOUT_ICH High= Default* (Internal pull-up)
ICH_TP3 HDA_SDOUT Description
ICH_TP3 23
0 0 RSVD Security Classification Compal Secret Data Compal Electronics, Inc.
R72 0 1 Enter XOR Chain 2007/09/20 2008/09/20 Title
1K_0402_5%
Issued Date Deciphered Date
@ 1 0 Normal Operation THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT AL
SCHEMATIC MB A4221
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1 1 Set PCIE port config bit 1 C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401552
Date: Friday, May 16, 2008 Sheet 22 of 50
5 4 3 2 1
 5 3 2 1

+3VS

SERIRQ
Place closely pin B2 Place closely pin AC1
1 2
R432 10K_0402_5% U10C
1 2 PM_CLKRUN# 16,27,29 ICH_SMBCLK ICH_SMBCLK G16 AH23 PROJECT_ID1 CLK_ICH_48M CLK_ICH_14M
R427 8.2K_0402_5% ICH_SMBDATA SMBCLK SATA0GP/GPIO21 PROJECT_ID0
EC_THERM#
16,27,29 ICH_SMBDATA
LINKALERT#
A13 SMBDATA SMB SATA1GP/GPIO19 AF19
R449 1 2 10K_0402_5%

SATA
GPIO
1 2 E17 LINKALERT#/GPIO60/CLGPIO4 SATA4GP/GPIO36 AE21

1
R167 8.2K_0402_5% ICH_SMLINK0 C17 AD20
H_STP_PCI# ICH_SMLINK1 SMLINK0 SATA5GP/GPIO37 R448 R99
1 2 B18 SMLINK1
R69 @ 10K_0402_5% H1 CLK_ICH_14M 10_0402_5% 10_0402_5%
CLK14 CLK_ICH_14M 16
H_STP_CPU# EC_SWI# CLK_ICH_48M @ @
R387
1
@
2
10K_0402_5% 31 EC_SWI# F19 RI# clocks CLK48 AF3 CLK_ICH_48M 16

2
1 2 SB SPKR PAD @ SUS_STAT# R4 P1 SUS_CLK PAD 1 1
T23 SUS_STAT#/LPCPD# SUSCLK T11
R424 @ 1K_0402_5% XDP_DBRESET# G19 @ C494 C167
4 XDP_DBRESET# SYS_RESET#
1 2 CR_WAKE# C16 PM_SLP_S3# 10P_0402_50V8J 10P_0402_50V8J
D SLP_S3# PM_SLP_S3# 31 D
R166 10K_0402_5% PM_SYNC# M6 E16 PM_SLP_S4# @ @
8 PM_SYNC# PMSYNC#/GPIO0 SLP_S4# PM_SLP_S4# 31 2 2
G17 PM_SLP_S5#

SYS / GPIO
SLP_S5# PM_SLP_S5# 31
DVT EC_LID_OUT# A17
31 EC_LID_OUT# SMBALERT#/GPIO11
1 2 OCP# C10 S4_STATE#
R453 10K_0402_5% H_STP_PCI# S4_STATE#/GPIO26
16 H_STP_PCI# A14 STP_PCI#
1 2 CR_CPPE# H_STP_CPU# E19 G20 ICH_PWROK LAN_RST# 1 2
16 H_STP_CPU# STP_CPU# PWROK ICH_PWROK 8
R452 10K_0402_5% DVT R389 10K_0402_5%
1 2 ICH_GPIO17 PM_CLKRUN# L4 M2 DPRSLPVR 1 2 No used Integrated LAN,

Power MGT
25,31 PM_CLKRUN# CLKRUN# DPRSLPVR/GPIO16 PM_DPRSLPVR 8,46
R444 @ 10K_0402_5% R106 100_0402_5%
1 2 ICH_GPIO18
27,29 ICH_PCIE_WAKE#
ICH_PCIE_WAKE# E20 B13 PM_BATLOW# connecting to GND
R101 @ 10K_0402_5% SERIRQ WAKE# BATLOW#
25,31 SERIRQ M5 SERIRQ
1 2 ICH_GPIO20 EC_THERM# AJ23 R3 PBTN_OUT# ICH_PWROK 1 2
31 EC_THERM# THRM# PWRBTN# PBTN_OUT# 31
R164 @ 10K_0402_5% R386 10K_0402_5%
1 2 SATA_CLKREQ# VGATE 2 1 ICH_VGATE D21 D20 LAN_RST# 1 2
8,16,46 VGATE VRMPWRGD LAN_RST# PLT_RST# 8,21,26,27,31
R104 10K_0402_5% R383 0_0402_5% R407 @ 0_0402_5%
1 2 ICH_GPIO38 PAD @ ICH_TP11 A20 D22 SB_RSMRST# DVT EC_PWROK 1 2
T8 TP11 RSMRST#
R465 @ 10K_0402_5% R384 @ 10K_0402_5%
1 2 ICH_GPIO39 OCP# AG19 R5 CK_PWRGD
4 OCP# GPIO1 CK_PWRGD CK_PWRGD 16
R450 @ 10K_0402_5% CRT_DET AH21
ICH_GPIO48 CR_CPPE# GPIO6 ICH_PWROK R385 2
1 2 26 CR_CPPE# AG21 GPIO7 CLPWROK R6 1 0_0402_5%
R451 10K_0402_5% EC_SMI# A21
31 EC_SMI# GPIO8 +3V
C12 B16 PM_SLP_M# PAD @
+3V 31 EC_SCI# GPIO12 SLP_M# T6
ICH_GPIO13 C21 @
ICH_GPIO17 GPIO13
DVT AE18 GPIO17 CL_CLK0 F24 CL_CLK0 8

5
1 2 ICH_SMBCLK ICH_GPIO18 K1 B19 U28

GPIO
Controller Link
R406 2.2K_0402_5% ICH_GPIO20 GPIO18 CL_CLK1 EC_PWROK
AF8 2

P
GPIO20 B EC_PWROK 31,33
1 2 ICH_SMBDATA CR_WAKE# AJ22 F22 ICH_PWROK 4
+3V 26 CR_WAKE# SCLOCK/GPIO22 CL_DATA0 CL_DATA0 8 Y
R62 2.2K_0402_5% PAD @ ICH_GPIO27 A9 C19 1 VGATE
T7 GPIO27 CL_DATA1 A

G
1 2 EC_SWI# @ ICH_GPIO28 D19 JALA0
T20 PAD GPIO28

1
R417 10K_0402_5% SATA_CLKREQ# L1 C25 CL_VREF0_ICH NC7SZ08P5X_NL_SC70-5
16 SATA_CLKREQ#

3
SATACLKREQ#/GPIO35 CL_VREF0
1

1 2 ICH_SMLINK0 ICH_GPIO38 AE19 A19 CL_VREF1_ICH R176

R404 10K_0402_5% R75 ICH_GPIO39 SLOAD/GPIO38 CL_VREF1
AG22 SDATAOUT0/GPIO39 10K_0402_5%
C ICH_SMLINK1 10K_0402_5% ICH_GPIO48 <BOM Structure> C
1 2 AF21 SDATAOUT1/GPIO48 CL_RST0# F21 CL_RST#0 8
R403 10K_0402_5% MAIN@ ICH_GPIO49 AH24 D18 DVT @

2
LINKALERT# ICH_GPIO57 GPIO49 CL_RST1# R199 2
1 2 A8 1 0_0402_5%
2

R405 10K_0402_5% ICH_GPIO57 GPIO57/CLGPIO5 ICH_GPIO24 @ Q18

MEM_LED/GPIO24 A16 PAD T5 2 1 +3V
1 2 XDP_DBRESET# SB_SPKR M7 C18 ICH_GPIO10 R393 100K_0402_5% MMBT3906_SOT23-3
34 SB_SPKR SPKR GPIO10/SUS_PWR_ACK
1

R95 10K_0402_5% AJ24 C11 ICH_ACIN 2 1 SB_RSMRST# 1 3

C
MISC
8 MCH_ICH_SYNC# MCH_SYNC# GPIO14/AC_PRESENT ACIN 31,39,42 EC_RSMRST# 31
1 2 ICH_PCIE_WAKE# R74 B21 C20 ICH_GPIO9 @ D26

E
22 ICH_TP3 TP3 WOL_EN/GPIO9 PAD T19
R416 1K_0402_5% 100K_0402_5% PAD @ ICH_TP8 AH20 CH751H-40PT_SOD323-2
T12 TP8

1
1 2 PM_BATLOW# VALUE@ @ ICH_TP9 AJ20 ICH9-M: SA00002JH70
Pre-MP

B
T13 PAD

2
R68 8.2K_0402_5% @ ICH_TP10 TP9 R200
T14 PAD AJ21 1 2 +3V
2

1 2 EC_LID_OUT# TP10 (S IC AF82801 BM SLB8Q A3 676P ICH9M ABO!) 10K_0402_5% R197 4.7K_0402_5%
R402 10K_0402_5% ICH9-M ES_FCBGA676 DVT ICH9-M: SA00002AN10 PVT ICH9-M: SA00002JH00
1 2 ICH_GPIO10 ICH9MB@ PVT D12A
U10D(S IC NH82801IBM QP23 A2 FCBGA 676P ICH9M) (S IC AF82801IBM QT09 A3 PBG 676P ICH9M)

2
R401 10K_0402_5% 1
1 2 ICH_GPIO13 JALA0 (iTPM physical presence) PAD @ N29 V27 DMI_MTX_IRX_N0 6
T32 PERN1 DMI0RXN DMI_MTX_IRX_N0 8
R413 10K_0402_5% New Card usage for JAL90 PAD @ N28 V26 DMI_MTX_IRX_P0 2
T33 PERP1 DMI0RXP DMI_MTX_IRX_P0 8
1 2 S4_STATE# PAD @ P27 U29 DMI_ITX_MRX_N0
T34 PETN1 DMI0TXN DMI_ITX_MRX_N0 8
R76 @ 10K_0402_5% @ P26 U28 DMI_ITX_MRX_P0 BAV99DW-7_SOT363

Direct Media Interface

T35 PAD PETP1 DMI0TXP DMI_ITX_MRX_P0 8

JALA0 (Project ID 0/1 01) PCIE_PTX_C_IRX_N2 L29 Y27 DMI_MTX_IRX_N1 D12B

29 PCIE_PTX_C_IRX_N2 PERN2 DMI1RXN DMI_MTX_IRX_N1 8
PCIE_PTX_C_IRX_P2 L28 Y26 DMI_MTX_IRX_P1 4
29 PCIE_PTX_C_IRX_P2 PERP2 DMI1RXP DMI_MTX_IRX_P1 8
For Wireless LAN 29 PCIE_ITX_C_PRX_N2 C462 2 1 0.1U_0402_16V7K PCIE_ITX_PRX_N2 M27 W29 DMI_ITX_MRX_N1 3
PETN2 DMI1TXN DMI_ITX_MRX_N1 8
1 2 PROJECT_ID1 29 PCIE_ITX_C_PRX_P2 C465 2 1 0.1U_0402_16V7K PCIE_ITX_PRX_P2 M26 W28 DMI_ITX_MRX_P1 5
PETP2 DMI1TXP DMI_ITX_MRX_P1 8

1
R168 10K_0402_5% DVT

PCI - Express
PCIE_PTX_C_IRX_N3 J29 AB27 DMI_MTX_IRX_N2 BAV99DW-7_SOT363 R196
27 PCIE_PTX_C_IRX_N3 PERN3 DMI2RXN DMI_MTX_IRX_N2 8
PCIE_PTX_C_IRX_P3 J28 AB26 DMI_MTX_IRX_P2 2.2K_0402_5%
27 PCIE_PTX_C_IRX_P3 PERP3 DMI2RXP DMI_MTX_IRX_P2 8
1 2 PROJECT_ID0 For PCIE LAN 27 PCIE_ITX_C_PRX_N3 C457 2 1 0.1U_0402_16V7K PCIE_ITX_PRX_N3 K27 AA29 DMI_ITX_MRX_N2
PETN3 DMI2TXN DMI_ITX_MRX_N2 8
R464 10K_0402_5% 27 PCIE_ITX_C_PRX_P3 C456 2 1 0.1U_0402_16V7K PCIE_ITX_PRX_P3 K26 AA28 DMI_ITX_MRX_P2
DMI_ITX_MRX_P2 8

2
PM_DPRSLPVR PETP3 DMI2TXP
1 2
R105 100K_0402_5% PCIE_PTX_C_IRX_N4 G29 AD27 DMI_MTX_IRX_N3
29 PCIE_PTX_C_IRX_N4 PERN4 DMI3RXN DMI_MTX_IRX_N3 8
1 2 ICH_GPIO49 PCIE_PTX_C_IRX_P4 G28 AD26 DMI_MTX_IRX_P3
29 PCIE_PTX_C_IRX_P4 PERP4 DMI3RXP DMI_MTX_IRX_P3 8
R169 1K_0402_5% For Robson2 29 PCIE_ITX_C_PRX_N4 C455 2 1 0.1U_0402_16V7K PCIE_ITX_PRX_N4 H27 AC29 DMI_ITX_MRX_N3
B PETN4 DMI3TXN DMI_ITX_MRX_N3 8 B
@ DVT(JALA0) 29 PCIE_ITX_C_PRX_P4 C452 2 1 0.1U_0402_16V7K PCIE_ITX_PRX_P4 H26 AC28 DMI_ITX_MRX_P3
PETP4 DMI3TXP DMI_ITX_MRX_P3 8 +3VS
DVT PCIE_PTX_C_IRX_N5 CLK_PCIE_ICH#
26 PCIE_PTX_C_IRX_N5 E29 PERN5 DMI_CLKN T26 CLK_PCIE_ICH# 16
PCIE_PTX_C_IRX_P5 E28 T25 CLK_PCIE_ICH
26 PCIE_PTX_C_IRX_P5 PERP5 DMI_CLKP CLK_PCIE_ICH 16
+3V 1 2 USB_OC#1 For Card Reader 26 PCIE_ITX_C_PRX_N5 C443 2 1 0.1U_0402_16V7K PCIE_ITX_PRX_N5 F27 PETN5
R431 10K_0402_5% 26 PCIE_ITX_C_PRX_P5 C445 2 1 0.1U_0402_16V7K PCIE_ITX_PRX_P5 F26 AF29 R150 24.9_0402_1% Within 500 mils R398
PETP5 DMI_ZCOMP
1 2 USB_OC#4 DMI_IRCOMP AF28 DMI_IRCOMP 1 2 +1.5VS_PCIE_ICH 3.24K_0402_1%
R108 10K_0402_5% JALA0 (ICH Enable Strap for iTPM) C29
+3VS PERN6/GLAN_RXN USB20_N0
C28 PERP6/GLAN_RXP USBP0N AC5 USB20_N0 30
D27 AC4 USB20_P0 USB Conn. CL_VREF0_ICH
+3VS PETN6/GLAN_TXN USBP0P USB20_P0 30
RP49 D26 AD3
PETP6/GLAN_TXP USBP1N
1

1 8 USB_OC#9 AD2 New Card usage for JAL90 1

USB_OC#5 R27 ICH_SPI_CLK R52 USBP1P
2 7 1 2 15_0402_5% ICH_SPI_CLK_R D23 SPI_CLK USBP2N AC1 USB20_N2
USB20_N2 30
C428 R399
2

3 6 USB_OC#6 ICH_SPI_CS0 R79 1 2 15_0402_5% ICH_SPI_CS0#_R D24 AC2 USB20_P2 USB Conn. 453_0402_1%
SPI_CS0# USBP2P USB20_P2 30
4 5 USB_OC#7 1K_0402_1% F23 AA5 USB20_N3 0.1U_0402_16V4Z
21 SPI_CS#1 SPI_CS1#GPIO58/CLGPIO6 USBP3N USB20_N3 38 2
AA4 USB20_P3 CMOS Camera
USB20_P3 38
2

ICH SPI_MOSI USBP3P

10K_1206_8P4R_5% High: CRT Plugged R165 R61 1 2 15_0402_5% ICH_SPI_MOSI_R D25 SPI_MOSI SPI USBP4N AB2 USB20_N4
USB20_N4 29
10K_0402_5% CH_SPI_MISO R80 1 2 15_0402_5% ICH_SPI_MISO_R E23 AB3 USB20_P4 USB/B
USB20_P4 29
1

RP50 CRT_DET MAIN@ SPI_MISO USBP4P USB20_N5

USBP5N AA1 USB20_N5 30
1 8 USB_OC#3 USB_OC#0 N4 AA2 USB20_P5 Bluetooth
30 USB_OC#0 OC0#/GPIO59 USBP5P USB20_P5 30
1

USB_OC#10 D USB_OC#1 USB20_N6 +3V

2 7 N5 OC1#/GPIO40 USBP6N W5 USB20_N6 18
USB_OC#11 JALA0 USB_OC#2 USB20_P6
3
4
6
5 USB_OC#8
19 CRT_DET# 2
Q13G
30 USB_OC#2
USB_OC#3
N6
P6
OC2#/GPIO41 USB USBP6P W4
Y3 USB20_N7
USB20_P6 18 DOCKING Conn.
OC3#/GPIO42 USBP7N USB20_N7 29
2N7002_SOT23 S USB_OC#4 M1 Y2 USB20_P7 Mini Card(Robson)
29 USB_OC#4 USB20_P7 29
3

10K_1206_8P4R_5% USB_OC#5 OC4#/GPIO43 USBP7P USB20_N8 R70

N2 OC5#/GPIO29 USBP8N W1 USB20_N8 29
USB_OC#6 M4 W2 USB20_P8 Mini Card(WLAN) 3.24K_0402_1%
OC6#/GPIO30 USBP8P USB20_P8 29
USB_OC#7 M3 V2
USB_OC#8 OC7#/GPIO31 USBP9N
N3 V3
Internal TPM Strap DMI Termination Voltage USB_OC#9 N1
OC8#/GPIO44
OC9#/GPIO45
USBP9P
USBP10N U5 USB20_N10
USB20_N10 30
CL_VREF1_ICH
USB_OC#10 USB20_P10 Finger Print
Low= Disable* Low= Desktop used USB_OC#11
P5
P3
OC10#/GPIO46 USBP10P U4
U1
USB20_P10 30
SPI_MOSI High= iTPM enable by MCH strap GPIO49 High= Mobile* (Internal pull-up) OC11#/GPIO47 USBP11N
USBP11P U2 C127
1
R71
A USBRBIAS 453_0402_1% A
AG2 USBRBIAS
2 1 AG1 0.1U_0402_16V4Z
R158 USBRBIAS# 2
R81 3.3K_0402_5%
SPI ROM Footprint 200mil 22.6_0402_1%
Within 500 mils ICH9-M ES_FCBGA676
+3VS 1 2
R51 1 2 3.3K_0402_5% 4MB Flash ICH9MB@
+3VS
SA000021A00 ( MX25L3205DM2I-12G / 32M bit / 86MHz )
U6
ICH_SPI_CS0#
32 ICH_SPI_CS0#
ICH_SPI_WP#
1
3
CE# VDD 8
6 ICH_SPI_CLK Security Classification Compal Secret Data Compal Electronics, Inc.
32 ICH_SPI_WP#
32 ICH_SPI_HOLD#
ICH_SPI_HOLD# 7
WP#
HOLD#
SCK
SI 5 ICH_SPI_MOSI
ICH_SPI_CLK 32
ICH_SPI_MOSI 32
No Reboot Strap Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title
ICH_SPI_MISO
PVT(Add inner pad length for 150mil)
4 VSS SO 2 ICH_SPI_MISO 32 Low= Default* SCHEMATIC MB A4221
MX25L3205DM2I-12G_SO8-S SPI4MB@ SB_SPKRHigh= "No Reboot" THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
ICH SPI ROM for iTPM & ME JALA0 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401552 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date Friday, May 16, 2008 Sheet 23 of 50
5 3 2 1
 5 3 2 1

+5VS +3VS U10F

+RTCVCC A23 A15 +1.05VS U10E
VCCRTC VCC1_05[01]
1 1 VCC1_05[02] B15 AA26 VSS[001] VSS[107] H5

2
R73 C433 +ICH_V5REF A6 C15 1 1 AA27 J23
D8 C437 V5REF VCC1_05[03] C468 C467 VSS[002] VSS[108]
VCC1_05[04] D15 AA3 VSS[003] VSS[109] J26
100_0402_5% CH751H-40PT_SOD323-2 0.1U_0402_16V4Z E15 AA6 J27
0.1U_0402_16V4Z 2 2 +ICH_V5REF_SUS VCC1_05[05] 0.1U_0402_16V4Z VSS[004] VSS[110]
AE1 V5REF_SUS VCC1_05[06] F15 AB1 VSS[005] VSS[111] AC22
2 2
L11 AA23 K28
1

1
+ICH_V5REF VCC1_05[07] 0.1U_0402_16V4Z VSS[006] VSS[112]
JALA0 AA24 VCC1_5_B[01] VCC1_05[08] L12 AB28 VSS[007] VSS[113] K29
MP C128
2 AA25 VCC1_5_B[02] VCC1_05[09] L14 AB29 VSS[008] VSS[114] L13
AB24 VCC1_5_B[03] VCC1_05[10] L16 AB4 VSS[009] VSS[115] L15
AB25 VCC1_5_B[04] VCC1_05[11] L17 AB5 VSS[010] VSS[116] L2
1U_0402_6.3V4Z AC24 L18 AC17 L26
1 VCC1_5_B[05] VCC1_05[12] +1.5VS_DMIPLL_ICH VSS[011] VSS[117]
AC25 VCC1_5_B[06] VCC1_05[13] M11 AC26 VSS[012] VSS[118] L27
AD24 VCC1_5_B[07] VCC1_05[14] M18 AC27 VSS[013] VSS[119] L5
L15 1

CORE
D AD25 VCC1_5_B[08] VCC1_05[15] P11 2 +1.5VS AC3 VSS[014] VSS[120] L7 D
+5VALW +5V +3V MBK1608301YZF_0603
AE25 VCC1_5_B[09] VCC1_05[16] P18 AD1 VSS[015] VSS[121] M12
AE26 VCC1_5_B[10] VCC1_05[17] T11 1 (10UF*1, 0.01UF*1) AD10 VSS[016] VSS[122] M13
AE27 T18 C180 AD12 M14
VCC1_5_B[11] VCC1_05[18] VSS[017] VSS[123]
2

R148 AE28 U11 C178 AD13 M15

R155 D11 VCC1_5_B[12] VCC1_05[19] VSS[018] VSS[124]
AE29 VCC1_5_B[13] VCC1_05[20] U18 10U_0805_10V4Z AD14 VSS[019] VSS[125] M16
100_0402_5% 2
CH751H-40PT_SOD323-2 F25 VCC1_5_B[14] VCC1_05[21] V11 AD17 VSS[020] VSS[126] M17
10_0402_5% G25 V12 0.01U_0402_16V7K AD18 M23
@ VCC1_5_B[15] VCC1_05[22] VSS[021] VSS[127]
H24 V14 AD21 M28
1

+ICH_V5REF_SUS VCC1_5_B[16] VCC1_05[23] VSS[022] VSS[128]

H25 VCC1_5_B[17] VCC1_05[24] V16 AD28 VSS[023] VSS[129] M29
MP 2 J24 VCC1_5_B[18] VCC1_05[25] V17 +1.05VS AD29 VSS[024] VSS[130] N11

VCCA3GP
C204 J25 V18 AD4 N12
VCC1_5_B[19] VCC1_05[26] VSS[025] VSS[131]
K24 VCC1_5_B[20] 1 (4.7UF*1) AD5 VSS[026] VSS[132] N13
1U_0402_6.3V4Z K25 C463 AD6 N14
1 VCC1_5_B[21] VSS[027] VSS[133]
L23 VCC1_5_B[22] AD7 VSS[028] VSS[134] N15
+1.5VS_PCIE_ICH L24 R29 4.7U_0805_10V4Z AD9 N16
VCC1_5_B[23] VCCDMIPLL 2 VSS[029] VSS[135]
L39 2
(220UF*1, 22UF*2, 2 2UF*1) L25 VCC1_5_B[24] AE12 VSS[030] VSS[136] N17
+1.5VS 1 M24 VCC1_5_B[25] VCC_DMI[1] W23 AE13 VSS[031] VSS[137] N18
KC FBM-L11-201209-221LMAT_0805 M25 Y23 AE14 N26
VCC1_5_B[26] VCC_DMI[2] VSS[032] VSS[138]
1 1 N23 VCC1_5_B[27] AE16 VSS[033] VSS[139] N27
C469 + C460 C473 C464 N24 AB23 AE17 P12
VCC1_5_B[28] V_CPU_IO[1] +1.05VS VSS[034] VSS[140]
N25 VCC1_5_B[29] V_CPU_IO[2] AC23 1 1 AE2 VSS[035] VSS[141] P13
220U_D2_4VM_R15 10U_0805 10V4Z P24 C454 C476 C479 (4.7UF*1, 0.1UF*2) AE20 P14
2 2 2 VCC1_5_B[30] VSS[036] VSS[142]
P25 VCC1_5_B[31] VCC3_3[01] AG29 AE24 VSS[037] VSS[143] P15
10U_0805_10V4Z 2.2U_0805_10V6K R24 AJ6 4.7U_0805_10V4Z 0.1U_0402_16V4Z AE3 P16
VCC1_5_B[32] VCC3_3[02] 2 2 VSS[038] VSS[144]
R25 VCC1_5_B[33] VCC3_3[07] AC10 AE4 VSS[039] VSS[145] P17
R26 0.1U_0402_16V4Z AE6 P2
VCC1_5_B[34] VSS[040] VSS[146]
R27 VCC1_5_B[35] VCC3_3[03] AD19 AE9 VSS[041] VSS[147] P23

VCCP_CORE
T24 VCC1_5_B[36] VCC3_3[04] AF20 AF13 VSS[042] VSS[148] P28
T27 VCC1_5_B[37] VCC3_3[05] AG24 close to AG29 close to AD19 close to G6 AF16 VSS[043] VSS[149] P29
T28 VCC1_5_B[38] VCC3_3[06] AC20 AF18 VSS[044] VSS[150] P4
T29 VCC1_5_B[39] +3VS AF22 VSS[045] VSS[151] P7
+1.5VS_SATAPLL_ICH U24 AH26 R11
C VCC1_5_B[40] VSS[046] VSS[152] C
U25 VCC1_5_B[41] VCC3_3[08] B9 1 1 1 1 1 1 AF26 VSS[047] VSS[153] R12
+1.5VS L16 1 2 V24 F9 C492 C495 C496 C458 C451 C449 AF27 R13
MBK1608301YZF_0603 VCC1_5_B[42] VCC3_3[09] VSS[048] VSS[154]
V25 VCC1_5_B[43] VCC3_3[10] G3 AF5 VSS[049] VSS[155] R14
1 1 U23 G6 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z AF7 R15
VCC1_5_B[44] VCC3_3[11] 2 2 2 2 2 2 VSS[050] VSS[156]

PCI
C223 W24 J2 AF9 R16
C228 VCC1_5_B[45] VCC3_3[12] 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z VSS[051] VSS[157]
W25 VCC1_5_B[46] VCC3_3[13] J7 AG13 VSS[052] VSS[158] R17
10U_0805 10V4Z K23 VCC1_5_B[47] VCC3_3[14] K7 AG16 VSS[053] VSS[159] R18
2 1U_0402_6.3V4Z
2
(10UF*1, 1UF*1) Y24 VCC1_5_B[48] close to AJ6 close to B9 close to K7 AG18 VSS[054] VSS[160] R28
Y25 VCC1_5_B[49] AG20 VSS[055] VSS[161] T12
AJ4 +VCC_HDA_ICH AG23 T13
VCCHDA +3VS VSS[056] VSS[162]
R173 PM@ 0_0603_5% AG3 T14
VSS[057] VSS[163]
VCCSUSHDA AJ3 +1.5VS AG6 VSS[058] VSS[164] T15
+5VALW R172 GM@ 0_0603_5%
AJ19 VCCSATAPLL 1 AG9 VSS[059] VSS[165] T16
C222 AH12 T17
VSS[060] VSS[166]
VCCSUS1_05[1] AC8 TP_VCCSUS1_05_ICH_1 @ PAD T24 AH14 VSS[061] VSS[167] T23
+1.5VS AC16 VCC1_5_A[01] VCCSUS1_05[2] F17 TP_VCCSUS1_05_ICH_2 @ PAD T21
0.1U_0402_16V4Z AH17 VSS[062] VSS[168] B26
3

S 2
G AD15 VCC1_5_A[02] AH19 VSS[063] VSS[169] U12
37 SBPWR_EN# 2 Q10 1 1 AD16 AH2 U13
VCC1_5_A[03] +VCCSUS_HDA_ICH VSS[064] VSS[170]
AO3413_SOT23-3 C491 C485 AE15 VCC1_5_A[04] VCCSUS1_5[1] AD8 TP_VCCSUS1_5_ICH_1 @ PAD T25 +3V AH22 VSS[065] VSS[171] U14
ARX

1
D AF15 R171 PM@ 0_0603_5% AH25 U15
1

C215 1U_0402_6.3V4Z VCC1_5_A[05] +VCCSUS1_5_ICH_INT_2 VSS[066] VSS[172]

AG15 VCC1_5_A[06] VCCSUS1_5[2] F18 +1.5V AH28 VSS[067] VSS[173] U16
2 2 R170 GM@ 0_0603_5%
AH15 VCC1_5_A[07] 1 1 AH5 VSS[068] VSS[174] U17
0.1U_0402_ 6V4Z AJ15 C448 C221 AH8 AD23
2 +5V VCC1_5_A[08] VSS[069] VSS[175]
1U_0402_6.3V4Z VCCSUS3_3[01] A18
0.1U_0402_16V4Z 0.1U_0402_16V4Z
Check Power Source AJ12 VSS[070] VSS[176] U26
AC11 D16 AJ14 U27
VCCPSUS

VCC1_5_A[09] VCCSUS3_3[02] 2 2 VSS[071] VSS[177]

AD11 VCC1_5_A[10] VCCSUS3_3[03] D17 AJ17 VSS[072] VSS[178] U3
AE11 VCC1_5_A[11] VCCSUS3_3[04] E22 AJ8 VSS[073] VSS[179] V1
AF11 VCC1_5_A[12] B11 VSS[074] VSS[180] V13
ATX

AG10 VCC1_5_A[13] B14 VSS[075] VSS[181] V15

AG11 VCC1_5_A[14] B17 VSS[076] VSS[182] V23
AH10 VCC1_5_A[15] B2 VSS[077] VSS[183] V28
AJ10 VCC1_5_A[16] VCCSUS3_3[05] AF1 +3V B20 VSS[078] VSS[184] V29
B B23 VSS[079] VSS[185] V4 B
AC9 VCC1_5_A[17] 1 1 B5 VSS[080] VSS[186] V5
C439 C472 C477 B8 W26
VSS[081] VSS[187]
AC18 VCC1_5_A[18] C26 VSS[082] VSS[188] W27
AC19 0.022U_0402_16V7K 0.1U_0402_16V4Z (0.1UF*1, 0.022UF*2) C27 W3
VCC1_5_A[19] 2 2 VSS[083] VSS[189]
VCCSUS3_3[06] T1 E11 VSS[084] VSS[190] Y1
AC21 T2 0.022U_0402_16V7K E14 Y28
VCC1_5_A[20] VCCSUS3_3[07] VSS[085] VSS[191]
VCCSUS3_3[08] T3 E18 VSS[086] VSS[192] Y29
G10 VCC1_5_A[21] VCCSUS3_3[09] T4 E2 VSS[087] VSS[193] Y4
G9 VCC1_5_A[22] VCCSUS3_3[10] T5 close to A18 close to T1 E21 VSS[088] VSS[194] Y5
VCCSUS3_3[11] T6 E24 VSS[089] VSS[195] AG28
AC12 U6 E5 AH6
VCCPUSB

VCC1_5_A[23] VCCSUS3_3[12] VSS[090] VSS[196]

AC13 VCC1_5_A[24] VCCSUS3_3[13] U7 E8 VSS[091] VSS[197] AF2
close to AC7 AC14 VCC1_5_A[25] VCCSUS3_3[14] V6 F16 VSS[092] VSS[198] B25
VCCSUS3_3[15] V7 DVT ICH9-M: SA00002AN10 F28 VSS[093]
+1.5VS AJ5 W6 F29
1 1
VCCUSBPLL VCCSUS3_3[16]
W7 (S IC NH82801 BM QP23 A2 FCBGA 676P ICH9M) G12
VSS[094]
VCCSUS3_3[17] VSS[095]
USB CORE

C497 C490 AA7 Y6 G14 A1

VCC1_5_A[26] VCCSUS3_3[18] VSS[096] VSS_NCTF[01]
close to AJ5 AB6 VCC1_5_A[27] VCCSUS3_3[19] Y7 G18 VSS[097] VSS_NCTF[02] A2
0.1U_0402_16V4Z AB7 T7 PVT ICH9-M: SA00002JH00 G21 A28
2 2 VCC1_5_A[28] VCCSUS3_3[20] VSS[098] VSS_NCTF[03]
AC6 G24 A29
0.1U_0402_16V4Z AC7
VCC1_5_A[29] (S IC AF82801 BM QT09 A3 PBG 676P ICH9M) G26
VSS[099] VSS_NCTF[04]
AH1
VCC1_5_A[30] VSS[100] VSS_NCTF[05]
G27 VSS[101] VSS_NCTF[06] AH29
2 1 +VCCLAN1_05_INT_ICH A10 VCCLAN1_05[1] G8 VSS[102] VSS_NCTF[07] AJ1
C438 A11 G22 +VCCCL1_05_INT_ICH H2 AJ2
0.1U_0402_16V4Z VCCLAN1_05[2] VCCCL1_05 +VCCCL1_5_INT_ICH VSS[103] VSS_NCTF[08]
VCCCL1_5 G23 H23 VSS[104] VSS_NCTF[09] AJ28
+3VS +VCCLAN_ICH A12 H28 AJ29
R65 0_0603_5% VCCLAN3_3[1] VSS[105] VSS_NCTF[10]
1 B12 VCCLAN3_3[2] 1 1 1 H29 VSS[106] VSS_NCTF[11] B1
C129 A24 +3VS C447 C442 C446 B29
VCCCL3_3[1] @ @ VSS_NCTF[12]
VCCCL3_3[2] B24 (0.1UF*1)
GLAN POWER

+1.5VS +VCC_GLANPLL_ICH A27 1U_0402_6.3V4Z

2 R63 0_0603_5% VCCGLANPLL 2 2 2 ICH9-M ES_FCBGA676
1
0.1U_0402_16V4Z C121 D28 0.1U_0402_16V4Z 0.1U_0402_16V4Z ICH9MB@
A
C120 VCCGLAN1_5[1] A
D29 VCCGLAN1_5[2]
(10UF*1, 2.2UF*1)10U_0805210V4Z E26 VCCGLAN1_5[3]
E27 VCCGLAN1_5[4] (1UF*1, 0.1UF*1)
2.2U_0805_10V6K
A26 VCCGLAN3_3 Pre-MP ICH9-M: SA00002JH70
+1.5VS +VCCGLAN_ICH
R89 0_0603_5% ICH9-M ES_FCBGA676 (S IC AF82801 BM SLB8Q A3 676P ICH9M ABO!)
C151 ICH9MB@
(4.7UF*1)
+3VS Security Classification Compal Secret Data Compal Electronics, Inc.
4.7U_0805_10V4Z 2007/09/20 2008/09/20 Title
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A4221
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401552
Date Friday May 16 2008 Sheet 24 of 50
5 3 2 1
 A B C D

21 PCI_AD[0..31] PCI_AD[0..31]

21 PCI_CBE#[0..3] PCI_CBE#[0..3] 3VS

0.1U_0402_16V4Z

5VS
1 1 0.1U_0402_16V4Z
IDSEL SELECT POWER-ON-STRAPPING C528 C525
(SEE NOTE & TABLE FOR OPTIONS)

2 2 1 1
10U_0805_10V4Z 0.1U_0402_16V4Z C524 C527
3VS R510 1 2 33K_0402_5%
1 1 1 1 4.7U_0805_10V4Z
C537 C526 C514 C515 R509 2 2
1 2 33K_0402_5%
S1_VCC
2 2 2 2 U35 4.7U_0805_10V4Z
5 VCC/VPP +3.3V 1
0.1U_0402_16V4Z 0.1U_0402_16V4Z U34 6 2
VCC/VPP +3.3V
7 3
64
77
CORE_VCC VCC5#/VCCD0#/SDATA 124
125
8
VCC5#
VCC3#
+5V
GND 4 PCMCIA Socket
CORE_VCC VCC3#/VCCD1#/SCLK OZ2210GN-B1_SO8
97 CORE_VCC VPP_PGM/VPPD0/SLATCH 123
10U_0805_10V4Z 0.1U_0402_16V4Z 115 CONN@
CORE_VCC JPCM1
3VS PVT
1 1 1 1 103 S1_D10 1
C540 C541 C523 PCI_VCC D10/CAD31 S1_D9 GND
20 PCI_VCC D9/CAD30 102
S1_D1
SA000026P10 (S IC OZ2210GN-B1 SO 8P) S1_D3
35 GND
33 PCI_VCC D1/CAD29 101 2 DATA3
100 S1_D8 S1_CD1# 36
2 2 2 PCI_AD31 D8/CAD28 S1_D0 S1_D4 CD1#
4 AD31 D0/CAD27 99 3 DATA4
PCI_AD30 5 110 S1_A0 S1_D11 37
0.1U_0402_16V4Z PCI_AD29 AD30 A0/CAD26 S1_A1 S1_VCC S1_D5 DATA11
6 AD29 A1/CAD25 109 4 DATA5
PCI_AD28 7 108 S1_A2 S1_D12 38
PCI_AD27 AD28 A2/CAD24 S1_A3 S1_D6 DATA12
8 106 5
NOTE: IDSEL SELECTION! PCI_AD26
PCI_AD25
9
AD27
AD26
A3/CAD23
A4/CAD22 105 S1_A4
S1_A5 0.1U_0402_16V4Z 4.7U_0805_10V4Z
S1_D13
S1_D7
39
DATA6
DATA13
10 AD25 A5/CAD21 104 6 DATA7
THIS DEVICE UTILIZES A "SELECTABLE IDSEL" SCHEME. PCI_AD24 13 118 S1_A6 1 1 S1_D14 40
IDSEL CAN BE CONNECTED INTERNALLY TO ONE OF THREE PCI_AD23 AD24 A6/CAD20 S1_A25 C543 C542 S1_CE1# DATA14
2 14 AD23 A25/CAD19 95 7 CE1#
2

PCI AD LINES OR EXTERNAL IDSEL SIGNAL. PCI_AD22 15 94 S1_A7 S1_D15 41

PCI_AD21 AD22 A7/CAD18 S1_A24 S1_A10 DATA15
16 AD21 A24/CAD17 93 8 ADD10
22K TO 47K PULL-UP & PULL-DOWN RESISTORS ARE PCI_AD20 S1_A17 2 2 S1_CE2#
17 AD20 A17/CAD16 75 42 CE2#
REQUIRED TO BE CONNECTED TO PINS 123 & 124 TO PCI_AD19 18 73 S1_IOWR# S1_OE# 9
SELECT ONE OF THE 4 POSSIBLE IDSEL CONNECTIONS. PCI_AD18 AD19 IOW#/CAD15 S1_A9 S1_VS1 OE#
19 AD18 A9/CAD14 74 43 VS1#
THE TABLE BELOW SHOWS THE 4 POSSIBLE COMBINATIONS. PCI_AD17 21 71 S1_IORD# S1_A11 10
PCI_AD16 AD17 IORD#/CAD13 S1_A11 S1_IORD# ADD11
22 AD16 A11/CAD12 72 44 IORD#
CONFIGURING IDSEL TO BE INTERNALLY CONNECTED ALLOWS PCI_AD15 28 70 S1_OE# S1_A9 11
FOR A FULL PARALLEL POWER MODE. IF AN EXTERNALLY PCI_AD14 AD15 OE#/CAD11 S1_CE2# S1_IOWR# ADD9
29 AD14 CE2#/CAD10 69 45 IOWR#
CONNECTED IDSEL IS REQUIRED THEN AN INVERTER MUST PCI_AD13 30 68 S1_A10 S1_A8 12
BE CONNECTED TO VPP_PGM TO CREATE VPP_VCC. PCI_AD12 AD13 A10/CAD9 S1_D15 S1_A17 ADD8
31 AD12 D15/CAD8 85 46 ADD17
PCI_AD11 34 84 S1_D7 S1_A13 13
PCI_AD10 AD11 D7/CAD7 S1_D13 S1_A18 ADD13
35 AD10 D13/CAD6 82 47 ADD18
PCI_AD9 36 83 S1_D6 S1_A14 14
VCC5# VPP_PGM IDSEL SELECT PCI_AD8 AD9 D6/CAD5 S1_D12 S1_A19 ADD14
37 AD8 D12/CAD4 80 48 ADD19
(124) (123) PCI_AD7 38 81 S1_D5 S1_WE# 15
PCI_AD6 AD7 D5/CAD3 S1_D11 S1_A20 WE#
39 AD6 D11/CAD2 78 49 ADD20
PCI_AD5 40 79 S1_D4 S1_RDY# 16
DOWN DOWN AD18 PCI_AD4 AD5 D4/CAD1 S1_D3 S1_A21 READY
DVT PCI_AD3
41 AD4 D3/CAD0 76 50 ADD21
42 AD3 S1_VCC 17 VCC
PCI_AD2 43 R508 33_0402_5% 51
DOWN UP AD20 PCI_AD1 AD2 S1_A16 VCC
44 AD1 A16/CCLK 107 1 2 18 VPP
R651 PCI_AD0 46 114 S1_A23 52
PCI_AD16 IDSEL AD0 A23/CFRAME# S1_A15 S1_A16 VPP
1 2 127 VPP_VCC/VPPD1/IDSEL A15/CIRDY# 117 19 ADD16
UP DOWN AD25 PCI_CBE#3 11 116 S1_A22 S1_A22 53
100_0402_5% PCI_CBE#2 C/BE3# A22/CTRDY# S1_A21 S1_A15 ADD22
12 C/BE2# A21/CDEVSEL# 113 20 ADD15
PCI_CBE#1 49 61 S1_A20 S1_A23 54
UP UP PIN F4 PCI_CBE#0 C/BE1# A20/CSTOP# S1_A13 S1_A12 ADD23
50 C/BE0# A13/CPAR 58 21 ADD12
3 60 S1_A14 S1_A24 55 3
A14/CPERR# S1_WAIT# S1_A7 ADD24
16 CLK_PCI_PCM 26 PCI_CLK WAIT#/CSERR# 91 22 ADD7
27 89 S1_INPACK# S1_A25 56
21 PCI_DEVSEL# DEVSEL# INPACK#/CREQ# ADD25
21 PCI_FRAME# 23 62 S1_WE# S1_A6 23
FRAME# WE#/CGNT# S1_RDY# S1_VS2 ADD6
21 PCI_IRDY# 24 IRDY# RDY/IREQ#/CINT# 88 57 VS2#
21 PCI_TRDY# 25 59 S1_A19 S1_A5 24
TRDY# A19/CBLOCK# S1_WP S1_RST ADD5
21 PCI_STOP# 47 STOP# WP/CCLKRUN# 87 58 RESET
21 PCI_PAR 48 119 S1_RST S1_A4 25
PAR RESET/CRST# S1_D2 S1_WAIT# ADD4
D2/RFU 98 59 WAIT#
PCM_SPK# 51 86 S1_D14 S1_A3 26
34 PCM_SPK# PERR#/SPKR_OUT D14/RFU ADD3
63 S1_A18 S1_INPACK# 60
A18/RFU S1_VS1 S1_A2 INPACK#
21 PCI_REQ#0 2 REQ# VS1/CVS1 57 27 ADD2
3 121 S1_VS2 S1_REG# 61
21 PCI_GNT#0 GNT# VS2/CVS2 REG#
56 S1_CD1# S1_A1 28
CD1#/CCD1# S1_CD2# S1_BVD2 ADD1
21 PCI_RST# 126 RST# CD2#/CCD2# 122 62 BVD2
120 92 S1_BVD2 S1_A0 29
PME#/RI_OUT# BVD2/LED/CAUDIO S1_BVD1 S1_BVD1 ADD0
BVD1/STSCHG#/RI#/CSTSCHG 90 63 BVD1
PM_CLKRUN# 2 1 55 S1_D0 30
23,31 PM_CLKRUN# R489 0_0402_5% MF6 S1_REG# S1_D8 DATA0
54 MF4 REG#CCBE3# 111 64 DATA8
@ 53 112 S1_A12 S1_D1 31
23,31 SERIRQ MF3 A12/CCBE2# DATA1
52 66 S1_A8 S1_D9 65 69
21 PCI_PIRQE# MF0 A8/CCBE1# DATA9 GND
67 S1_CE1# S1_D2 32 70
CE1/CCBE0# S1_D10 DATA2 GND
66 71
GND
GND
GND
GND
GND

S1_WP DATA10 GND

DVT(Check) S1_CD2#
33 WP GND 72
67 CD2#
OZ601TN_TQFP128~D 34
32
45
65
96
128

GND
68 GND
22K TO 47K PULL-UPS MUST BE PLACED SANTA_130651-E_68P_LT-S
4 ON INTA#, PME#, SERIRQ# & CLKRUN#. 4

Footprint as SANTA_130651-E_68P_LT-S
DVT(JALA0)
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A4221
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401552
Date: Friday, May 16, 2008 Sheet 25 of 50
A B C D
 5 4 3 2 1

MDIO PULL HIGH/LOW ?

3VS L45 1.8VS_APVDD
40mil MBK1608121YZF_0603
0.1U_0402_16V4Z 0.1U_0402_16V4Z
40mil 0.1U_0402_16V4Z
1.8VS 1 2
@ 3V_MCVCC
1 1 1 1 1 1 1 1 1
C534 C521 C511 C532 C529 C512 C519 C522 C531
XDWP_SDWP 1 2
D 0.1U_0402_16V4Z R494 10K_0402_5% D
2 2 2 2 2 2 2 2 2
10U_0805_10V4Z XD_RB 1 2
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1000P_0402_50V7K R485 10K_0402_5%

3VS

XD_CLE 1 2
U32 R496 10K_0402_5%

3 5 1.8VS_APVDD XDCD0#_SDCD# 1 2
16 CLK_PCIE_READER# APCLKN APVDD
4 10 R487 4.7K_0402_5%
16 CLK_PCIE_READER APCLKP APV18
TAV33 30 3VS
PCIE_ITX_C_PRX_N5 9 XDCD1#_MSCD# 1 2
23 PCIE_ITX_C_PRX_N5 APRXN
PCIE_ITX_C_PRX_P5 8 19 R488 4.7K_0402_5%
23 PCIE_ITX_C_PRX_P5 APRXP DV33
DV33 20
23 PCIE_PTX_C_IRX_N5 C517 1 2 0.1U_0402_16V7K PCIE_PTX_IRX_N5 11 44
C516 1 0.1U_0402_16V7K PCIE_PTX_IRX_P5 APTXN DV33
23 PCIE_PTX_C_IRX_P5 2 12 APTXP DV18 18 1.8VS_APVDD
DV18 37
R491 1 2 8.2K_0402_5% APREXT 7 APREXT XD_SD_MS_D0
APREXT 15 mil MDIO0 48
47 XD_SD_MS_D1
MDIO1 XD_SD_MS_D2
3VS 38 PCIES_EN MDIO2 46
39 45 XD_SD_MS_D3 XD_RE 1 2
PCIES JMB385 MDIO3
MDIO4 43 SDCMD_MSBS_XDWE# R497 R490 200K_0402_5%
42 XDCE_SDCLK_MSCLK_R 1 2 XDCE_SDCLK_MSCLK
MDIO5 XDWP_SDWP 33_0402_5% XD_ALE
MDIO6 41 1 2
40 XD_CLE JALA0 R486 200K_0402_5%
C
MDIO7 XD_D4 C
MDIO8 29
8,21,23,27,31 PLT_RST# 1 28 XD_D5
XRSTN MDIO9 XD_D6
2 XTEST MDIO10 27
26 XD_D7
R655 MDIO11 XD_RE
MDIO12 25
23 CR_CPPE# 1 @ 2 0_0402_5% TP_SEEDAT 13 23 XD_RB
@ TP_SEECLK SEEDAT MDIO13 XD_ALE
T26 PAD 14 SEECLK MDIO14 22
D33 34
CH751H-40PT_SOD323-2 XDCD1#_MSCD# NC
15 CR1_CD1N NC 35
23 CR_WAKE# 1 2 XDCD0#_SDCD# 16 36
@ CR1_CD0N NC
1 @ 2 6
R656 MC_PWREN# APGND D28
DVT 0_0402_5%
17 CR1_PCTLN XDCD0#_SDCD#
MC_PWREN# 40 mil GND 24 2
31 1 XD_CD#
GND XDCD1#_MSCD#
32 5IN1_LED# 21 CR1_LEDN GND 32 3
GND 33
DAN202UT106_SC70-3 C510

270P_0402_50V7K
JMB385-LGEZ0A_LQFP48_7X7

DVT SA00001W910 (S IC JMB385-LGEZ0B LQFP 48P)

4 IN 1 Socket Push Type(New)
B JREAD1 B

3V_MCVCC 3 XD-VCC SD-VCC 21 3V_MCVCC

28
Memory Card Power Switch XD_SD_MS_D0
XD_SD_MS_D1
32
10
XD-D0
7 IN 1 CONN
MS-VCC
20 XDCE_SDCLK_MSCLK
XD_SD_MS_D2 XD-D1 SD_CLK XD_SD_MS_D0
9 XD-D2 SD-DAT0 14
XD_SD_MS_D3 8 12 XD_SD_MS_D1
3VS 3V_MCVCC XD_D4 XD-D3 SD-DAT1 XD_SD_MS_D2 XDCE_SDCLK_MSCLK
7 XD-D4 SD-DAT2 30
XD_D5 6 29 XD_SD_MS_D3
U33 XD_D6 XD-D5 SD-DAT3 XD_D4 (MMC Data Bit 4)
40mil 5 XD-D6 SD-DAT4 27

4.7P_0402_50V8C10_0402_5%
1 8 XD_D7 4 23 XD_D5 (MMC Data Bit 5)
GND OUT XD-D7 SD-DAT5

R498
2 7 18 XD_D6 (MMC Data Bit 6)
IN OUT C536 1 C530 1 C535 1 SDCMD_MSBS_XDWE# 34 SD-DAT6 XD_D7 (MMC Data Bit 7)
3 IN OUT 6 XD-WE SD-DAT7 16
MC_PWREN# 4 5 XDWP_SDWP 33 25 SDCMD_MSBS_XDWE# @
EN# FLG XD_ALE XD-WP SD-CMD XDCD0#_SDCD#
35 1

2
XD-ALE SD-CD-SW
1

TPS2061DRG4_SO8 4.7U_0805_10V4Z 0.1U_0402_16V4Z XD_CD# 40

R493 2 2 2 XD_RB XD-CD XDWP_SDWP
@ 39 XD-R/B SD-WP-SW 2
300_0603_5% 0.1U_0402_16V4Z XD_RE 38 2
XDCE_SDCLK_MSCLK 37 XD-RE
@ XD-CE

C533
XD_CLE 36 26 XDCE_SDCLK_MSCLK
1 2

XD-CLE MS-SCLK XD_SD_MS_D0

D MS-DATA0 17
XD_SD_MS_D1 1 @
11 7IN1 GND MS-DATA1 15
MC_PWREN# 2 Q42 31 19 XD_SD_MS_D2 JALA0
G 2N7002_SOT23 7IN1 GND MS-DATA2 XD_SD_MS_D3
MS-DATA3 24
S @ 22 XDCD1#_MSCD#
3

MS-INS SDCMD_MSBS_XDWE#
MS-BS 13
41 7IN1 GND
42 7IN1 GND
A A
TAITW_R015-B10-LM
MC_PWREN# 1 2 3V_MCVCC CONN@

1 R492 0_0805_5%
C520

2
4.7U_0805_10V4Z Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT AL
SCHEMATIC MB A4221
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401552
Date: Friday, May 16, 2008 Sheet 26 of 50
5 4 3 2 1
 5 3 2 1

+3VALW 1 2 +3V_LAN
R45 0_1206_5% +3V_LAN R339 1 2 1_1206_1%

R338 1 2 1_1206_1% +3V_LAN R

1 1
+3V_LAN 1 2 LAN_PM # C9 C21

3
R347 4.7K_0402_5%
0.1U_0402_16V4Z
LAN_REGCTL12 1 2 2
4.7U 0805_10V4Z
Q2 +1.2V_LAN
+3V_LAN MMJT9435T1G_SOT223

2
4
60mil
D D
1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 C6 C7 C389 C387 C386 C388 C78 C95 C414 C413 C61
C31 C68 C62 C96
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
4.7U_0805_10V4Z 0.1U_0402_16V4Z 2 2 2 2 2 2 2 2 2 2 2
2 2 2 2 4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
0.1U_0402_16V4Z 0.1U_0402_16V4Z

+3V_LAN

U23

2
41 LAN_MIDI0-
TRD0_N LAN_MIDI0- 28 R364
28 40 LAN_MIDI0+ R369 R367
16 CLK_PCIE_LAN# PCIE_REFCLK_N TRD0_P LAN_MIDI0+ 28
42 +LAN_AVDD 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5%
TRD1_N/AVDD LAN_MIDI1- +3V_LAN
16 CLK_PCIE_LAN 29 PCIE_REFCLK_P TRD1_P/T1_N 43
+LAN_AVDD
LAN_MIDI1- 28 1Mb Flash
48

1
TRD2_N/AVDD LAN_MIDI2-
16 LAN_CLKREQ# 11 CLKREQ TRD2_P/T2_N 47 LAN_MIDI2- 28
PVT2(JALA0) 49 LAN_MIDI3- U25
TRD3_N LAN_MIDI3- 28
R333 1 2 0_0402_5% 50 LAN_MIDI3+ SPROM_DOU 1 8 SPROM_DIN
31 LAN_LOWPWR TRD3_P LAN_MIDI3+ 28 SI SO
@ SPROM_CLK 2 7
R336 1 SCK GND
2 10K_0402_5% 3 LOW PWR 3 RESET# VCC 6 +3V_LAN
SPROM_CS 4 5 1
R328 1 CS# WP#
+3VS 2 1K_0402_5% 53 VMAIN_PRSNT LINKLED 2 2 1 LAN_LINK# 28
C98
1 R321 AT45DB011B-SU_SO8~N 0.1U_0402_16V4Z
C R327 1 SPD100LED C
+3V_LAN 2 1K_0402_5% 54 VAUX_PRSNT SPD1000LED 67 0_0402_5% DVT 2
TRAFFICLED 66 2 1 LAN_ACTIVITY# 28
R322 Use Flash if support ASF2.0
0_0402_5%
31 ENERGY_DET 59 65 SPROM_CLK
ENERGY_DET SCLK(EECLK) SPROM_DIN R323 1
SI 63 2 4.7K_0402_5%
+LAN_GPHYPLLVDD 35 64 SPROM_DOUT
GPHY_PLLVDD SO(EEDATA) SPROM_CS
PCIE_ITX_C_PRX_N3 CS 62 PVT
23 PCIE_ITX_C_PRX_N3 32 PCIE_RXD_N
PCIE_ITX_C_PRX_P3 31 +Lan_VDDIO_1.2
23 PCIE_ITX_C_PRX_P3 PCIE_RXD_P
14 LAN_REGCTL12
C411 1 PCIE_PTX_IRX_N3 REGCTL12
23 PCIE_PTX_C_IRX_N3 2 25 PCIE_TXD_N REGCTL25/12_IO 18
0.1U_0402_16V7K 37 LAN_RDAC 1 2
C412 1 PCIE_PTX_IRX_P3 RDAC R356 1.18K_0402_1%
23 PCIE_PTX_C_IRX_P3 2
0.1U_0402_16V7K
26 PCIE_TXD_P PVT 20mil L4
L11 +LAN_PCIEPLLVDD 1 2 +1.2V_LAN
23 +LAN_XTALVDD 1 2 +3V_LAN 1 1 BLM18AG601SN1D_0603
R341 1 0_0402_5% LAN_RESET# XTALVDD BLM18AG601SN1D_0603 C81 C82
8,21,23,26,31 PLT_RST# 2 10 PERST VDDIO 6 +3V_LAN
R354 1 @ LAN_PME# VDDIO 15 1 PVT +Lan_VDDIO_1.2
23,29 ICH_PCIE_WAKE# 2 0_0402_5% 12 WAKE VDDIO 19 C94 0.1U_0402_ 6V4Z
R355 1 2 2
31 EC_PME# 2 0_0402_5% VDDIO 56 PVT
61 4.7U_0805_10V4Z
VDDIO 2
0.1U_0402_16V4Z
+3V_LAN +Lan_VDDIO_1.2
R20 LAN_SMBCLK
58 SMB_CLK VDDP 17 1
C606
1
C607
20mil L3
VDDP/DC 68
4.7K_0402_5% LAN_SMBDATA 57 +LAN_PCIEVDD 1 2 +1.2V_LAN
SMB_DATA
2

1 2 +3V_LAN PVT(JALA0) 5 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1 1 BLM18AG601SN1D_0603

R13 0_0402_5% VDDC 2 2 C80 C84
VDDC 13 +1.2V_LAN
1 2 6 1 LAN_SMBDATA 20
16,23,29 ICH_SMBDATA VDDC
4 34 0.1U_0402_ 6V4Z
Q3A 2N7002DW-T/R7_SOT363-6 GPIO_0(SERIAL_DO) VDDC 2 2
VDDC 55
B 4.7U 0805_10V4Z B
4,31 EC_SMB_DA2 1 2 1 2 7 GPIO_1(SERIAL_DI) VDDC 60
R16 0_0402_5% R673 0_0402_5% L8
@ @ 8 36 +LAN_BIASVDD 1 2 +3V_LAN 20mil
GPIO_2 BIASVDD
PVT PCIE_PLLVDD 30 +LAN_PCIEPLLVDD 1 BLM18AG601SN1D_0603 L7
+3V_ AN C91 +LAN_AVDD
JALA0 R14
9 UART_MODE PCIE_VDD/PLL 27 1 1 1 2 +3V_LAN
PCIE_VDD 33 +LAN_PCIEVDD C611 C613 1 1 BLM18AG601SN1D_0603
4.7K_0402_5% 0.1U_0402_16V4Z C83 C27
5

2 0.1U_0402_16V4Z
1 2 +3V_LAN AVDD/DC 38
LAN_XTALI 2 2
R21 0_0402_5% 21 XTALI AVDD/AVDDL 45 +LAN_AVDDL 0.1U_0402_ 6V4Z
LAN_SMBCLK 0.1U 0402_16V4Z 2 2
1 ,23,29 ICH_SMBCLK 1 2 3 4
XTALO AVDD/DC 52 PVT 0.1U_0402_16V4Z
22 XTALO
Q3B 2N7002DW-T/R7_SOT363-6 39 +LAN_AVDDL
AVDDL LAN_MIDI1+
4,31 EC_SMB_CK2 1 2 1 2
R674 0_0402_5% AVDDL/T1_P 44
LAN_MIDI2+
LAN_MIDI1+ 28 20mil L5
R17 0_0402_5% 1 2 16 REG_GND/S_IDDQ AVDDL/T2_P 46 LAN_MIDI2+ 28
@ @ R358 39K_0402_5% 51 +LAN_AVDDL +LAN_AVDDL 1 2 +1.2V_LAN
+LAN PCIEVDD AVDDL BLM18AG601SN1D_0603
PVT 24 PCIE_GND/VDD E- PAD 69
C77
1
C70
1

PVT2 BCM5764MKML_QFN68 0.1U_0402_ 6V4Z

2 2
4.7U_0805_10V4Z

DVT SA000025P00 20mil L9

LAN_XTALI (S IC BCM5764MA0KMLG QFN 68P E-LAN CTRL) +LAN_GPHYPLLVDD 1 2 +1.2V_LAN
1 1 BLM18AG601SN1D_0603
XTALO PVT SA000025P20 C97 C99
(S IC BCM5764MKMLG P20 QFN 68P E-L)
1

0.1U_0402_ 6V4Z
R363 2 2
200_0402_1% 4.7U 0805_10V4Z

A A
2

Y2
1 2 LAN_XTALO

1 25MHZ_20P 1
C415 C416
27P_0402_50V8J 27P_0402 50V8J
2 2 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A4221
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401552
Date Friday, May 16, 2008 Sheet 27 of 50
5 3 2 1
 5 4 3 2 1

3V_LAN

L_LAN_LINK# L_LAN_ACTIVITY#
U1

56
50
38
27
18
10
4
PI3L500-AZFEX_TQFN56_11X5

3
VDD6
VDD5
VDD4
VDD3
VDD2
VDD1
VDD0
48 D_LAN_MIDI0 @ @
0B1 D_LAN_MIDI0 38
47 D_LAN_MIDI0-
1B1 D_LAN_MIDI0- 38 PSOT24C-LF-T7_SOT23-3 PSOT24C-LF-T7_SOT23-3
27 LAN_MIDI0 LAN_MIDI0 2 A0 D_LAN_MIDI1 D20 D19
2B1 43 D_LAN_MIDI1 38
D 27 LAN_MIDI0- LAN_MIDI0- 3 42 D_LAN_MIDI1- D
D_LAN_MIDI1- 38

1
A1 3B1
37 D_LAN_MIDI2
4B1 D_LAN_MIDI2 38
27 LAN_MIDI1 LAN_MIDI1 7 36 D_LAN_MIDI2-
A2 5B1 D_LAN_MIDI2- 38

27 LAN_MIDI1- LAN_MIDI1- 8 32 D_LAN_MIDI3

A3 6B1 D_LAN_MIDI3 38
31 D_LAN_MIDI3-
7B1 D_LAN_MIDI3- 38
1 2
27 LAN_MIDI2 LAN_MIDI2 11 22 D_LAN_ACTIVITY#
A4 0LED1 D_LAN_ACTIVITY# 38
23 D_LAN_LINK# C374
1LED1 D_LAN_LINK# 38
27 LAN_MIDI2- LAN_MIDI2- 12 52 220P_0402_50V7K
A5 2LED1 JRJ45
46 L_LAN_MIDI0 2 1 12 Amber LED+
0B2 3V_LAN
27 LAN_MIDI3 LAN_MIDI3 14 45 L_LAN_MIDI0- R314 1K_0402_5%
A6 1B2 L_LAN_ACTIVITY# 11 Amber LED-
27 LAN_MIDI3- LAN_MIDI3- 15 41 L_LAN_MIDI1 16
A7 2B2 L_LAN_MIDI1- RJ45_MIDI3- SHLD2
3B2 40 8 PR4- Guide Pin
SHLD1 15
EC_DOCKIN# 17 35 L_LAN_MIDI2 RJ45_MIDI3 7
19,31,34,38 EC_DOCKIN# SEL 4B2 PR4+
34 L_LAN_MIDI2-
5B2 RJ45_MIDI1- 6 PR2-
LAN_ACTIVITY# 19 30 L_LAN_MIDI3
27 LAN_ACTIVITY# LAN_LINK# LED0 6B2 L_LAN_MIDI3- RJ45_MIDI2-
27 LAN_LINK# 20 LED1 7B2 29 5 PR3-
54 LED2
25 L_LAN_ACTIVITY# RJ45_MIDI2 4
0LED2 L_LAN_LINK# PR3+
5 NC 1LED2 26
NOTE: L : A-->B1 51 RJ45_MIDI1 3
2LED2 PR2+
57
H: A-->B2 PAD_GND RJ45_MIDI0- 2

GND10
GND11
GND12
GND13
PR1-

GND0
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
C 14 C
RJ45_MIDI0 SHLD2
1 PR1+
R586 0_0402_5% 13
LAN_MIDI0 L_LAN_MIDI0 L_LAN_LINK# SHLD1
1 1 2 10
6
9
13
16
21
24
28
33
39
44
49
53
55
VALUE@ Green LED-
R587 0_0402_5% 2 1 9
3V_LAN Green LED+
LAN_MIDI0- 1 2 L_LAN_MIDI0- R317 1K_0402_5%
VALUE@ FOX_JM36113-L2R8-7F
R588 0_0402_5% CONN@
LAN_MIDI1 1 2 L_LAN_MIDI1 1 2
MAIN@ VALUE@
R589 0_0402_5% C384
LAN_MIDI1- 1 2 L_LAN_MIDI1- 220P_0402_50V7K
VALUE@
R590 0_0402_5%
LAN_MIDI2 1 2 L_LAN_MIDI2
VALUE@ RJ45_GND 1 2 LANGND 40mil
R591 0_0402_5% 1 1
LAN_MIDI2- 1 2 L_LAN_MIDI2- C5
VALUE@ 1000P_1206_2KV7K C3 C4
R592 0_0402_5% 4.7U_0805_10V4Z
LAN_MIDI3 L_LAN_MIDI3 2 2
1 2
DVT VALUE@
R593 0_0402_5% 0.1U_0402_16V4Z
LAN_MIDI3- 1 2 L_LAN_MIDI3-
T1 VALUE@

L_LAN_MIDI0
1 TCT1 MCT1 24
RJ45_MIDI0 R594 0_0402_5%
ADD_DVT(JALA0)
2 TD1+ MX1+ 23
L_LAN_MIDI0- 3 22 RJ45_MIDI0- LAN_ACTIVITY# 1 2 L_LAN_ACTIVITY#
B TD1- MX1- VALUE@ L_LAN_ACTIVITY# B
4 TCT2 MCT2 21 1 2
L_LAN_MIDI1 5 20 RJ45_MIDI1 R595 0_0402_5% C375
L_LAN_MIDI1- TD2+ MX2+ RJ45_MIDI1- LAN_LINK# L_LAN_LINK# 68P_0402_50V8J
6 TD2- MX2- 19 1 2
7 18 VALUE@
L_LAN_MIDI2 TCT3 MCT3 RJ45_MIDI2
8 TD3+ MX3+ 17
L_LAN_MIDI2- 9 16 RJ45_MIDI2- L_LAN_LINK# 1 2
TD3- MX3- C383
10 TCT4 MCT4 15
L_LAN_MIDI3 11 14 RJ45_MIDI3 JALA0 68P_0402_50V8J
L_LAN_MIDI3- TD4+ MX4+ RJ45_MIDI3-
12 TD4- MX4- 13
350uH_GSL5009-1 LF
SP050003T10 For EMI
(S X'FORM GSL5009-1 LF ETHERNET)
1

R4 R5
75_0402_1% 75_0402_1%
0.1U_0402_16V4Z 0.1U_0402_16V4Z
2

1 1 1 1 R7 R8
C377 C378 C379 C382 75_0402_1% 75_0402_1%
2

2 2 2 2 RJ45_GND

0.1U_0402_16V4Z 0.1U_0402_16V4Z 40mil

A A

Place close to TCT pin

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/12/25 Deciphered Date 2007/12/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT AL
SCHEMATIC MB A4221
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401552
Date: Friday, May 16, 2008 Sheet 28 of 50
5 4 3 2 1
 A B C D E

R538 1 2 0_1206_5%
For Wireless LAN +3VS_WLAN
R542 1 @ 2 0_1206_5%
+3VS

+3V
LOWER SLOT(SAME AS JAL90)
+3VS_WLAN +1.5VS

Mini Card Power Rating

1 1 1 1 1 1
C557 C352 C315 C312 C344 C353 Power Primary Power (mA) Auxiliary Power (mA)
4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z Peak Normal Normal
2 2 2 2 2 2
1 1
+3VS 1000 750
PVT(JALA0) JMINI2
R278 1 @
PVT(JALA0) +3V 330 250 250 (wake enable)
23,27 ICH_PCIE_WAKE# 2 0_0402_5% 1 1 2 2 +3VS_WLAN
R665 1 2 0_0402_5% WLAN_BT_DATA R 3 4 +1.5VS 500 375 5 (Not wake enable)
30 WLAN_BT_DATA 3 4
R666 1 2 0_0402_5% WLAN_BT_CLK_R 5 6 +1.5VS
30 WLAN_BT_CLK 5 6
16 MINI1_CLKREQ# 7 7 8 8
9 9 10 10
16 CLK_PCIE_MINI1# 11 11 12 12
16 CLK_PCIE_MINI1 13 13 14 14
15 15 16 16
PVT(JALA0)
DVT 17
19
17 18 18
20 WL_OFF#_R R667 1 2 0_0402_5%
19 20 WL_OFF# 31
21 22 PLT_RST_BUF#
21 22 PLT_RST_BUF# 21
23 24 +3V_WLAN R275 1 2 0_0603_5% +3VS
23 PCIE_PTX_C_IRX_N2 23 24
25 26 R273 1 @ 2 0_0603_5% +3V
23 PCIE_PTX_C_IRX_P2 25 26
27 27 28 28
29 30 MINI1_SMBCLK R271 1 @ 2 0_0402_5% ICH_SMBCLK ICH_SMBCLK 16,23,27
29 30 MINI1_SMBDATA
23 PCIE_ITX_C_PRX_N2 31 31 32 32 R267 1 @ 2 0_0402_5% ICH_SMBDATA ICH_SMBDATA 16,23,27
23 PCIE_ITX_C_PRX_P2 33 33 34 34
35 35 36 36 USB20_N8 23
37 37 38 38 USB20_P8 23
+3VS_WLAN 39 39 40 40
41 42 (LED_WWAN#)
41 42
43 44 (LED_WLAN#) MINI1_LED# 32
43 44
DVT For MINICARD Port80 Debug 45 45 46 46

E51TXD_P80DATA R517 1 2 0_0402_5% CL_RST#1_R

47
49
47 48 48
50
(9~16mA)
31 E51TXD_P80DATA 49 50
E51RXD_P80CLK 51 52
31 E51RXD_P80CLK 51 52
2 2

G1
G2
G3
G3
FOX_AS0B226-S99N-7F

53
54
55
56
CONN@

For Robson2
UPPER SLOT(SAME AS JAL90)

+3VS +1.5VS

1 1 1 1 1
C345 C357 C348 C349 C313
MAIN@ MAIN@ MAIN@ MAIN@ MAIN@
2
4.7U_0805_10V4Z
2
0.1U_0402_16V4Z
2
4.7U_0805_10V4Z
2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z To USB/B Connector JALA0
PVT(JALA0)
3 JMINI1
80mil 0_0402_5% R205 3
JP11
1 (WAKE#) 2 +3VS 1 +5VALW 2 MAIN@
1
1 2 1 SYSON# 30,37,38
3 4 2 0_0402_5% R209
3 4 2 @
5 5 6 6 +1.5VS 3 3 2 1 USB_EN# 30,31
16 MINI2_CLKREQ# 7 7 8 8 9 GND 4 4
9 10 10 5 USB20_N4
9 10 GND 5 USB20_N4 23
11 12 6 USB20_P4
16 CLK_PCIE_MINI2# 11 12 6 USB20_P4 23
16 CLK_PCIE_MINI2 13 13 14 14 7 7
15 15 16 16 8 8 USB_OC#4 23
ACES_87212-08G0L
17 18 CONN@
DVT 19
17 18
20
19 20 PLT_RST_BUF#
21 21 22 22
23 PCIE_PTX_C_IRX_N4 23 23 24 24
23 PCIE_PTX_C_IRX_P4 25 25 26 26
27 27 28 28
29 30 MINI2_SMBCLK R272 1 @ 2 0_0402_5% ICH_SMBCLK
29 30 MINI2_SMBDATA R268 1 +5VALW
23 PCIE_ITX_C_PRX_N4 31 31 32 32 @ 2 0_0402_5% ICH_SMBDATA
23 PCIE_ITX_C_PRX_P4 33 33 34 34
35 35 36 36 USB20_N7 23
37 37 38 38 USB20_P7 23 1
+3VS 39 40 C376
39 40 MAIN@
41 42 (LED_WWAN#)
41 42 4.7U_0805_10V4Z
43 44 (LED_WLAN#)
43 44 2
For MINICARD Port80 Debug MAIN@
45 45 46 46
47 47 48 48
E51TXD_P80DATA R658 1 2 0_0402_5% CL_RST#2_R
DVT E51RXD_P80CLK
49
51
49 50 50
52
51 52
G1
G2
G3
G3

FOX_AS0B226-S99N-7F
53
54
55
56

CONN@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDEN IAL
SCHEMATIC MB A4221
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401552
Date Friday, May 16, 2008 Sheet 29 of 50
A B C D E
 A B C D E

+5VS +3VS +5VS

0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

1 1 1 1 1 1 1 1 1
C566 C564 C568 C559 C553 C551 C254 C250 C259

2 2 2 2 2 2 2 2 2

1000P_0402_50V7K 10U_0805_10V4Z 1000P_0402_50V7K 10U_0805_10V4Z 1000P_0402_50V7K 10U_0805_10V4Z

1 1

SATA HDD Conn. SATA ODD Conn.

JSATA2

1 JSATA1
SATA_ITX_C_DRX_P0 GND
22 SATA_ITX_C_DRX_P0 2 HTX+
SATA_ITX_C_DRX_N0 3 1
22 SATA_ITX_C_DRX_N0 HTX- SATA_ITX_C_DRX_P1 GND
4 GND 22 SATA_ITX_C_DRX_P1 2 A+
SATA_DTX_IRX_N0 5 SATA_ITX_C_DRX_N1 3
SATA_DTX_IRX_P0 HRX- 22 SATA_ITX_C_DRX_N1 A-
6 HRX+ 4 GND
7 SATA_DTX_IRX_N1 5
GND SATA_DTX_IRX_P1 B-
6 B+
7 GND

+3VS 8 VCC3.3
9 R190 1 @ 2 1K_0402_1% 8
VCC3.3 DP
10 VCC3.3 +5VS 9 +5V
11 GND 10 +5V
12 GND 11 MD
13 GND 12 GND GND 15
+5VS 14 VCC5 13 GND GND 14
15 VCC5
16 VCC5
17 SANTA_206401-1_13P
GND CONN@
18 RESERVED
19 GND
20 VCC12
21 VCC12 GND 24
22 VCC12 GND 23
22 SATA_DTX_C_IRX_N0 SATA_DTX_C_IRX_N0 1 2 SATA_DTX_IRX_N0 22 SATA_DTX_C_IRX_N1 SATA_DTX_C_IRX_N1 1 2 SATA_DTX_IRX_N1
2 C538 0.01U_0402_16V7K C281 0.01U_0402_16V7K 2
SUYIN_127043FB022GX78ZR_NR
22 SATA_DTX_C_IRX_P0 SATA_DTX_C_IRX_P0 1 2 SATA_DTX_IRX_P0 22 SATA_DTX_C_IRX_P1 SATA_DTX_C_IRX_P1 1 2 SATA_DTX_IRX_P1
C539 0.01U_0402_16V7K CONN@ JALA0 C279 0.01U_0402_16V7K

MP Bluetooth Conn.
+3VALW +3VS
MP Finger Print Conn.
+3VALW +3VS
USB CONN. (Stack-up Type)
1

R694 R695

1
0_0603_5% 0_0603_5%
@ R692 R693
0_0603_5% 0_0603_5% +USB_VCCA +USB_VCCA
2

@ W=80mils W=80mils
JALA0 +USB_VCCA JALA0 +USB_VCCA
2

2
+3VALW
1 1
1 1
JP8 C508 + C195 C478 + C235
C194 6
0.1U_0402_16V4Z G2 150U_D2_6.3VM 150U_D2_6.3VM
1 1 5 G1
C325 C327 2 2 2 2
2 1 4 4
USB20_N10 3 470P_0402_50V7K 470P_0402_50V7K
23 USB20_N10 3
0.1U_0402_16V4Z 1U_0603_10V4Z USB20_P10 2
23 USB20_P10 2
3

2 2
S
G 1 1
3 Q29 JUSB2 JUSB1 3
31 BT_ON# 1 2 2
R252 10K_0402_5% AO3413_SOT23-3 ACES_85201-04051 1 1
USB20_N0 VCC USB20_N2 VCC
D
CONN@ 23 USB20_N0 2 23 USB20_N2 2
1

USB20_P0 D- USB20_P2 D-
1 23 USB20_P0 3 D+ 23 USB20_P2 3 D+
C326 W=40mils ADD_DVT(JALA0) 4 4
GND GND
+BT_VCC Change SC300000O00 to SC300000B00
0.1U_0402_16V4Z 5 5
2 D32 GND1 GND1
1 1 6 GND2 6 GND2
1

C317 C318 USB20_P10 6 3 7 7

R245 CH3 CH2 GND3 GND3
8 GND4 8 GND4
4.7U_0805_10V4Z 300_0603_5%
2 2 SUYIN_020173MR004G565ZR SUYIN_020173MR004G565ZR
0.1U_0402_16V4Z +3VS 5 2 CONN@ CONN@
2

Vp Vn
1

D
2 Q27 4 1 USB20_N10
G 2N7002_SOT23 CH4 CH1 +3V
S PJUSB208_SOT23-6 80mil
3

+5VALW

1
D27 +USB_VCCA R483
+BT_VCC USB20_P0 6 3 USB20_P2 U31 0_0402_5%
CH3 CH2 R484
1 GND OUT 8 1 2 USB_OC#2 23
JP10 2 7 100K_0402_5%
IN OUT
1 9 3 6

2
1 GND IN OUT
2 2 +USB_VCCA 5 Vp Vn 2 1 4 EN# FLG 5 1 2 USB_OC#0 23
3 C513 R482
23 USB20_P5 3
4 TPS2061DRG4_SO8 10K_0402_5% 1
23 USB20_N5 4
5 4.7U_0805_10V4Z C509
5 USB20_N2 USB20_N0 2
29 WLAN_BT_DATA 6 6 4 CH4 CH1 1 JALA0
7 0.1U_0402_16V4Z
29 WLAN_BT_CLK 7 2
8 10 @ CM1293-04SO_SOT23-6 R204 0_0402_5%
8 GND
29,37,38 SYSON# 1 2
ACES_87213-0800G R208 0_0402_5%
CONN@ 1 @ 2
29,31 USB_EN#

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDEN IAL
SCHEMATIC MB A4221
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401552
Date Friday, May 16, 2008 Sheet 30 of 50
A B C D E
 5 4 3 2 1

3VALW For EC Tools

L34
0.1U 0402_16V4Z 0.1U_0402_16V4Z EC_VCCA 3VALW
1 1 C466 1 1 2
1 2
2 FBM-L11-160808-800LMT_0603 JP4 Place on RAM door
C465 1 KSI[0..7] 1
3VALW KSI[0..7] 32 1
C468 C469 C470 C471 2 E51RXD_P80CLK
KSO[0..17] 2 E51RXD_P80CLK 29
000P_0402_50V7K 1000P_0402_50V7K C467 3 E51TXD_P80DATA
2 2 2 2 1 1 KSO[0..17] 32 3 E51TXD_P80DATA 29
1 2 EC_PME# 4
R424 10K_0402_5% 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 4

ECAGND
@ ACES_85205-0400
@
D
3VALW Place on MiniCard D
JP5

111
125
22
33
96

67
1 1

9
U22 2 E51RXD_P80CLK
2 E51TXD_P80DATA
3

VCC
VCC
VCC
VCC
VCC
VCC

AVCC
3 R699 10K_0402_5% 3VS
4 4
1 2
ACES_85205-0400 @ JALA0
1 21 INVT_PWM @
22 EC_GA20 GA20/GPIO00 INVT_PWM/PWM1/GPIO0F INVT_PWM 18
2 23 BEEP#
22 EC_KBRST# KBRST#/GPIO01 BEEP#/PWM2/GPIO10 BEEP# 34
3 26 THERM_ALERT# THERM_ALERT# 2 1
23,25 SERIRQ SERIRQ# FANPWM1/GPIO12 VGA_THERM_ALERT# 17
4 27 ACOFF R698 0_0402_5%
22 LPC_FRAME# LFRAME# ACOFF/FANPWM2/GPIO13 ACOFF 42
C473 LPC_AD3 5 DVT(JALA0) 2 1 ECAGND @
22 LPC_AD3 LAD3
@ 22P_0402_50V8J LPC_AD2 7 PWM Output R700 0_0402_5% C472 0.01U_0402_16V7K
22 LPC_AD2 LAD2
2 1 R425 2 1 @ 33_0402_5% 22 LPC_AD1 8 63 BATT_TEMP_R2 1
LPC_AD1 LAD1 BATT_TEMP/AD0/GPIO38 BATT_TEMP 40
LPC_AD0 BATT_OVP
22 LPC_AD0 10 LAD0 LPC & MISC BATT_OVP/AD1/GPIO39 64 BATT_OVP 42
ADP_I/AD2/GPIO3A 65 ADP_I 42
12 AD Input 66 AD_BID0 PVT(JALA0)
16 CLK_PCI_LPC PCICLK AD3/GPIO3B
13 75 EC GPIOB PVT2(JALA0)
8,21,23,26,27 PLT_RST# PCIRST#/GPIO05 AD4/GPIO42
37 76 PGD_IN
ECRST# SELIO2#/AD5/GPIO43 PGD_IN 46
EC_SCI# 20 3S/4S# 1 2
23 EC_SCI# SCI#/GPIO0E
3VALW 2 1 38 R426 4.7K_0402_5%
R427 47K_0402_5% 23,25 PM_CLKRUN# CLKRUN#/GPIO1D DAC_BRIG
DAC_BRIG/DA0/GPIO3C 68 DAC_BRIG 18
2 1 70 EN_DFAN1
EN_DFAN1/DA1/GPIO3D EN_DFAN1 36
C474 0.1U_0402_16V4Z DA Output 71 IREF
IREF/DA2/GPIO3E IREF 42
KSI0 55 72 CALIBRATE#
KSI0/GPIO30 DA3/GPIO3F CALIBRATE# 42
KSI1 56
KSI2 KSI1/GPIO31
57 KSI2/GPIO32
KSI3 58 83 EC_MUTE
KSI3/GPIO33 PSCLK1/GPIO4A EC MUTE 35
C KSI4 59 84 LAN_LOWPWR LAN_LOWPWR 27 JALA0 C
5VS KSI5 KSI4/GPIO34 PSDAT1/GPIO4B DOCKIN#
60 KSI5/GPIO35 PSCLK2/GPIO4C 85 DOCKIN#
KSI6 3VALW
61 KSI6/GPIO36 PS2 Interface PSDAT2/GPIO4D 86 BT_LED# 32
KSI7 62 87 TP_CLK
KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E TP_CLK 32
1 2 TP_CLK KSO0 39 KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F 88 TP_DATA
TP_DATA 32
65W/90W# 2 1
R431 4.7K_0402_5% KSO1 40 R430 100K_0402_5%
KSO1/GPIO21
1 2 TP_DATA KSO2 41 KSO2/GPIO22
R432 4.7K_0402_5% KSO3 42 97 3S/4S#
KSO3/GPIO23 SDICS#/GPXOA00 3S/4S# 42
KSO4 43 98 65W/90W#
KSO4/GPIO24 SDICLK/GPXOA01 65W/90W# 42
KSO5 SBPWR EN
PVT2(JALA0) 2
R?
1 3VS
KSO6
44 KSO5/GPIO25 Int. K/B SDIDO/GPXOA02 99
EC_GPIOC
SBPWR_EN 37,44 Analog Board ID definition, SKU ID definition, JALA0
45 KSO6/GPIO26 Matrix SDIDI/GPXID0 109
2.2K_0402_5% KSO7 46 SPI Device Interface PVT2(JALA0) Please see page 3. Please see page 3.
KSO8 KSO7/GPIO27
GM@ 47 KSO8/GPIO28
KSO9 48 119 EC_SPIDI/FWR#
KSO9/GPIO29 SPIDI/RD# EC_SI_SPI_SO 32 3VALW
17,20 DVI_DET 1 GM@ 2 EC_GPIOC KSO10 49 120 EC_SPIDO/FRD# 3VALW
KSO10/GPIO2A SPIDO/WR# EC_SO_SPI_SI 32
R? 0_0402_5% KSO11 50 SPI Flash ROM 126 EC_SPICLK
KSO11/GPIO2B SPICLK/GPIO58 EC_SPICLK 32
1 GM@ 2 EC_GPIOB KSO12 51 128 EC_SPICS#/FSEL#
20 EC_DVI_DET KSO12/GPIO2C SPICS# EC_SPICS#/FSEL# 32

2
R? 0_0402_5% KSO13 52 R701
KSO14 KSO13/GPIO2D R433 100K_0402_5%
53 KSO14/GPIO2E JALA0 PVT(JALA0)
KSO15 54 73 SKU ID Ra 100K_0402_5% Rc @
KSO16 KSO15/GPIO2F CIR_RX/GPIO40
81 KSO16/GPIO48 CIR_RLC_TX/GPIO41 74 EC_ACIN 17
KSO17 82 89 FSTCHG
FS CHG 42

1
KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 BATT_GRN_LED# AD_BID0 SKU_ID
BATT_CHGI_LED#/GPIO52 90 BATT_GRN_LED# 32
91 CAPS_LED#
CAPS_LED#/GPIO53 CAPS_LED# 32

2
EC_SMB_CK1 77 GPIO 92 BATT_AMB_LED# 1 1
17,40 EC_SMB_CK1 SCL1/GPIO44 BATT_LOW_LED#/GPIO54 BATT_AMB_LED# 32
EC_SMB_DA1 78 93 PWR_LED R248 C475 R702 C701
17,40 EC_SMB_DA1 SDA1/GPIO45 SUSP_LED#/GPIO55 PWR_LED 32
JALA0 EC_SMB_CK2 79 SM Bus 95 SYSON Rb Rd 0_0402_5% 0.1U_0402_16V4Z
4,27 EC_SMB_CK2 SCL2/GPIO46 SYSON/GPIO56 SYSON 37,43,44
EC_SMB_DA2 80 121 VR_ON 33K_0402_5% @ @
4,27 EC_SMB_DA2 SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 VR_ON 33,46 2 2
127 ACIN
ACIN 23,39,42

1
B 3VALW AC_IN/GPIO59 0.1U_0402_16V4Z B

1 2 EC_SMB_CK1 23 PM_SLP_S3#
PM_SLP_S3# 6 PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 100 EC_RSMRST# 23
R234 2.2K_0402_5% PM_SLP_S5# 14 101 EC_LID_OUT# MP
23 PM_SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 EC_LID_OUT# 23
1 2 EC_SMB_DA1 23 EC_SMI#
EC_SMI# 15 EC_SMI#/GPIO08 EC_ON/GPXO05 102 EC_ON
EC_ON 33
R235 2.2K_0402_5% LID_SW# 16 103
32 LID_SW# LID_SW#/GPIO0A EC_SWI#/GPXO06 EC_SWI# 23
1 2 EC_SMB_CK2 2 WL_SW#
WL_SW# 17 SUSP#/GPIO0B ICH_PWROK/GPXO06 104 EC_PWROK
EC_PWROK 23,33
EC_CRY1 EC_CRY2
R229 2.2K_0402_5% JALA0 32 BT_SW# 18 GPO 105 BKOFF#
BT_SW# PBTN_OUT#/GPIO0C BKOFF#/GPXO08 BKOFF# 18
1 2 EC_SMB_DA2 27 EC_PME#
EC_PME# 19 EC_PME#/GPIO0D GPIO WL_OFF#/GPXO09 106 WL_OFF#
WL_OFF 2 1 1
R230 2.2K_0402_5% 25 107 USB_EN# JALA0 C289 C288
8 MCH_TSATN_EC# EC_THERM#/GPIO11 GPXO10 USB_EN# 29,30

4
1 2 LID_SW# 36 FAN_SPEED1
FAN_SPEED1 28 FAN_SPEED1/FANFB1/GPIO14 GPXO11 108 EC_DOCKIN#
EC_DOCKIN# 9,28,34,38
R457 100K_0402_5% BT_ON# 29 15P_0402_50V8J 15P_0402_50V8J

OUT
IN
30 BT_ON# FANFB2/GPIO15 2 2
E51TXD_P80DATA 30
E51RXD_P80CLK EC_TX/GPIO16
31 EC_RX/GPIO17 PM_SLP_S4#/GPXID1 110 PM_SLP_S4# 23
ON/OFF 32 112 ENBKL
33 ON/OFF ON_OFF/GPIO18 ENBKL/GPXID2 ENBKL 10,17
PWR_SUSP_LED EAPD

NC

NC
32 PWR_SUSP_LED 34 PWR_LED#/GPIO19 GPXID3 114 EAPD 34 PVT PVT
JALA0 NUM_LED# 36 GPI 115
32 NUM_LED# NUMLED#/GPIO1A GPXID4 EC_THERM# 23
116 SUSP#
SUSP# 33,37,45

3
GPXID5 PBTN_OUT#
GPXID6 117 PBTN_OUT# 23
5VALW 5VALW ENERGY_DET
GPXID7 118 ENERGY_DET 27 JALA0
C7020.1U_0402_16V4Z EC_CRY1 122 X2
XCLK1
1

1 2 EC_CRY2 123 124 32.768KHZ_12.5P_MC-306

R703 XCLK0 V18R
1 For KB926 C0 reversion
AGND

@ @ C286 JALA0
GND
GND
GND
GND
GND

100K_0402_5%
U43 4.7U_0805_10V4Z C479 100P_0402_50V8J
2

KB926QFB1_LQFP128_14X14 2 BATT_TEMP
8 1 2 1
11
24
35
94
113

69

VCC A0 5VALW C480 100P_0402_50V8J

EC_SMB_CK1
7 WP A1 2 20mil L35 BATT_OVP
A 6 SCL A2 3 2 1 A
EC_SMB_DA1 5 4 ECAGND 2 1 USB_EN# 2 1 C481 100P_0402_50V8J
SDA GND FBM-L11-160808-800LMT_0603 R704 @ 100K_0402_5% ACIN 2 1
AT24C16AN-10SI-2.7_SO8 DVT(JALA0)
@
1

R705 Security Classification Compal Secret Data Compal Electronics, Inc.

@ 2007/09/20 2008/09/20 Title
100K_0402_5%
Issued Date Deciphered Date
SCHEMATIC MB A4221
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT AL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401552
Date: Friday, May 16, 2008 Sheet 31 of 50
5 4 3 2 1
 2MB SA00001IT00 (MXIC , S IC FL 16MBIT MX25L1605AM2C-12G SO8 ROM , 85MHz)
2MB SA00001OZ00 (WINBOND , S IC FL 32MBIT W25X32VSSIG SOIC 8P 3.3V , 75MHz)
To TP/B Conn.
JP7
DVT(JALA0) SYS & EC & FP(PBA) & HDCP U17
EC_SPICS#/FSEL# 1 8 +SPI_VCC +5VS
C299 1 CS# VCC 1
+3VALW 1 2 2 0.1U_0402_16V4Z SPI_WP# 3 WP# SCLK 6 EC_SPICLK_R
31 TP_CLK
TP_CLK
2
R239 0_0603_5% SPI_HOLD# 7 5 EC_SO_SPI_SI TP_DATA
HOLD# SI 31 TP_DATA 3
4 2 EC_SI_SPI_SO LEFT_BTN#
+SPI_VCC GND SO RIGHT_BTN# 4
MX25L512AMC-12G_SO8 5
U15 @ 6
1 1
EC_SPICS#/FSEL# 1 8 R226 0_0402_5% Reserved for BIOS simulator. C199
31 EC_SPICS#/FSEL# CE# VDD ACES_85201-0605
R225 1 2 4.7K_0402_5% SPI WP# 3 6 EC_SPICLK_R 1 2 C198
R219 1 WP# SCK EC_SPICLK 31 Footprint SO8 CONN@
+3VALW 2 4.7K_0402_5% SPI HOLD# 7 HOLD# SI 5 R232 1 2 0_0402_5% EC_SO_SPI_SI 31
100P_0402_50V8J 100P_0402_50V8J
R218 1 2 2
4 VSS SO 2 2 0_0402_5% EC_SI_SPI_SO 31 SPI ROM Footprint 150mil
ENE suggestion SPI Frequency over 66MHz MX25L1605AM2C-12G_SOP8

SST: 50MHz 2MB Flash TP_CLK

MXIC: 70MHz
SPI ROM Footprint 200mil DVT(JALA0) TP_DATA
ST: 40MHz +5VS
To POWER/B(BTN/B)

3
KSI[0..7] C197 D10
INT_KBD Conn. KSO[0..17]
KSI[0..7] 31
JP6
0.1U_0402_16V4Z
@
PSOT24C_SOT23
KSO[0..17] 31 1
ON/OFFBTN# 33

1
2 PWR_LED#
JP3 3 PWR_SUSP_LED#
4 KSO0
(Left) KSO0 5 KSI4
LID_SW# 31
26 KSO0 G2 28 6
KSO1 25 27 KSI3 SW1 <BOM Structure> SW2
KSO2 KSO1 G1 KSO16 C58 7
24 KSO2 1 2 @ 100P_0402_50V8J 8
KSI2 KSI1 PRESENTATION SMT1-05-A_4P SMT1-05-A_4P
KSO3 23 KSO0 LEFT_BTN# 3 1 RIGHT_BTN#3 1
KSO4 KSO3 KSO17 C59 9
22 KSO4 1 2 @ 100P_0402_50V8J 10 KSI2 Program BTN#
KSO5 21 4 2 4 2
KSO6 KSO5 KSI2 C64 11
20 KSO6 1 2 @ 100P_0402_50V8J 12 KSI3 EMAIL BTN#
KSO7 19

5
6

5
6
KSO8 KSO7 KSO9 C45
18 KSO8 1 2 @ 100P_0402_50V8J ACES_85201-1205 KSI4 IE BTN#
KSO9 17 CONN@ +3VALW +5VS +5VALW
KSO10 KSO9 KSI3 C53
16 KSO10 1 2 @ 100P_0402_50V8J KSI5 E-KEY BTN#
KSO11 15
KSO12 KSO11 KSO8 C44
14 KSO12 1 2 @ 100P_0402_50V8J KSI6 SYNC
KSO13 13
KSO14
KSO15
12
11
KSO13
KSO14 To FUN/B(LED/B) KSI7 LOCK PWR_LED# PWR_SUSP_LED#
KSO16 KSO15 +5VS
10 KSO16

3
KSO17 9 KSO0 C36 1 2 @ 100P_0402_50V8J
KSI0 KSO17 JP5
8 KSI0
KSI1 7 KSI5 C55 1 2 @ 100P_0402_50V8J
KSI2 KSI1 1 KSO0 Q31A Q31B
6 KSI2 2 31 PWR_LED 2 31 PWR_SUSP_LED 5
KSI3 5 KSI6 C50 1 2 @ 100P_0402_50V8J KSI1
KSI3 3

1
KSI4 4 KSI5 2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6

4
KSI5 KSI4 KSI7 C51 4 KSI6
3 KSI5 1 2 @ 100P_0402_50V8J 5
R262 R258
KSI6 2 KSI7
KSI7 KSI6 6 10K_0402_5% 10K_0402_5%
1 KSI7 7 CAPS_LED# 31
(Right) NUM_LED# 31

2
8 MEDIA_LED#
ACES_88747-2601 9
CONN@ 10
ACES_85201-10051
CONN@

KSO15 C57 1 2 @ 100P_0402_50V8J KSO7 C43 1 2 @ 100P_0402_50V8J

KSO14 C56 1 2 @ 100P_0402_50V8J KSO6 C42 1 2 @ 100P_0402_50V8J

DVT(JALA0) +3VALW
KSO13 C49 1 2 @ 100P_0402_50V8J KSO5 C41 1 2 @ 100P_0402_50V8J

KSO12 C48 1 2 @ 100P_0402_50V8J KSO4 C40 1 2 @ 100P_0402_50V8J

3
+3VALW JALA0
KSI0 C60 1 2 @ 100P_0402_50V8J KSO3 C39 1 2 @ 100P_0402_50V8J D17

KSO11 C47
DAN217_SC59 PVT(JALA0)
1 2 @ 100P_0402_50V8J KSI4 C54 1 2 @ 100P_0402_50V8J @

1
@ +3VS
KSO10 C46 1 2 @ 100P_0402_50V8J KSO2 C38 1 2 @ 100P_0402_50V8J R288 U4

1
100K_0402_5% ICH_SPI_CS0# 1 8
23 ICH_SPI_CS0# CS# VCC
KSI1 C32 1 2 @ 100P_0402_50V8J KSO1 C37 1 2 @ 100P_0402_50V8J ICH_SPI_WP# 3 6 ICH_SPI_CLK
23 ICH_SPI_WP# WP# SCLK ICH_SPI_CLK 23
ICH_SPI_HOLD# 7 5 ICH_SPI_MOSI
23 ICH_SPI_HOLD# ICH_SPI_MOSI 23

2
HOLD# SI ICH_SPI_MISO
WL_SW# 31 4 GND SO 2 ICH_SPI_MISO 23
1

MX25L512AMC-12G_SO8
1

(AMB/GREEN) 5 6
PVT(JALA0) Check HT-297DQ-GQ_AMB-YG
5 6
Wireless SWITCH Reserved for BIOS simulator.
Compal Footprint SW3 SSS-12R-V-T/R_4P
Footprint SO8
+5VALW 1 2 4 A 3 PWR_SUSP_LED# SPI ROM Footprint 150mil
4 2 R290 453_0402_1% SN200001B00 (DIPTRONICS , S DIP SW SSS-12R-V-T/R 1P2T DIPTRO H2 4P)
3 1 +5VS 1 2 2 YG 1 PWR_LED# SN200001G00 (MISAKI , S DIP SW NSS607-212N-EEEG1T 1P2T MISAKI H2 4P)
R291 150_0402_5% +3VALW

LED1
MP(JALA0) (AMB/GREEN)
HT-297DQ-GQ_AMB-YG
2

+3VALW
+5VALW 1 2 4 A 3 BATT_AMB_LED# BATT_AMB_LED# 31 D16
R293 453_0402_1% DAN217_SC59
@
1

1 2 2 1 BATT_GRN_LED# +3VS
+5VALW YG
BATT_GRN_LED# 31
R294 150_0402_5% R287
1

100K_0402_5% Q11A

2
LED2 2N7002DW-T/R7_SOT363-6
MP(JALA0)
2

BT_SW# 31 26 5IN1_LED# 1 6
1

(AMB) SATA_LED# 4 3 MEDIA_LED#

1

R296 LED4 22 SATA_LED#

5 6
+3VS 2 1 2 1 MINI1_LED#
MINI1_LED# 29
5 6
BT SWITCH Q11B

5
SW4 SSS-12R-V-T/R_4P +3VS 2N7002DW-T/R7_SOT363-6
300_0402_5% HT-191UD_Amber_0603

R292 LED3 (BLUE)

+5VS 2 1 2 1 BT_LED#
BT_LED# 31
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title
300_0402_5% HT-191NBQA_BLUE_0603
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A4221
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401552
Date Friday May 16 2008 Sheet 32 of 50
 A B C D E

Power Button
ON/OFF switch HDA MDC Conn.
+3V

+3VALW
TOP Side JMDC1
20mil PM@ 1
C355
1 2 +3V
1 2 R279 0_0402_5%
1 R286 @ 10K_0603_5% +MDC_VCC 1U_0603_10V4Z 1
1 GND1 RES0 2 1 2 +1.5V

2
R277 0_0402_5% 2
22 HDA_SDOUT_MDC 3 IAC_SDATA_OUT RES1 4
1 2 R250 5 6 GM@
GND2 3.3V +3V
R573 @ 10K_0603_5% 22 HDA_SYNC_MDC 7 8
100K_0402_5% HDA_SDIN1_MDC IAC_SYNC GND3
22 HDA_SDIN1 1 2 9 IAC_SDATA_IN GND4 10
Bottom Side 22 HDA_RST_MDC#
R276 33_0402_5% 11 12 HDA_BITCLK_MDC 22

1
D13 IAC_RESET# IAC_BITCLK

1
2 ON/OFF 31
ON/OFFBTN# 1 R280

GND
GND
GND
GND
GND
GND
32 ON/OFFBTN#
3 51ON# 0_0402_5%
51ON# 39
DAN202UT106_SC70-3 ACES_88018-124G

13
14
15
16
17
18

2
CONN@ 1
C354
Connector for MDC Rev1.5
22P_0402_50V8J

1
2
2
C321 D15

1000P_0402_50V7K RLZ20A_LL34
1 For EMI

2
1
D
EC_ON 2 Q28
31 EC_ON
G
2

S 2N7002_SOT23
R249 3
10K_0402_5%
2 2
1

Power ON Circuit
+3VS

+3VALW +3VALW
1

U19A U19B
R257 SN74LVC14APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14
14

14

180K_0402_5%
D14 @
P

P
2

1 2 1 2 3 4 SYS_PWROK 1 2
31,46 VR_ON I O I O EC_PWROK 23,31
R260 @ 0_0402_5%
G

CH751H-40PT_SOD323-2 2
@
For South Bridge
7

C328
1U_0603_10V6K
@ 1

3 3

+3VS
PVT
+3VALW +3VALW
+RTCBATT
1

@ R263
U19C U19D
14

14

R668 10K_0402_1% SN74LVC14APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14

2
10K_0402_1%
P

P
2

1 2 5 6 9 8 R495
31,37,45 SUSP# I O I O VS_ON 43
2 1K_0402_5%
1

D C341
SUSP 2
For +VCCP/+1 05VS
37,45 SUSP
7

1 1
G 0.1U_0402_16V4Z
Q32 S 1 D29
3

2N7002_SOT23

+RTCVCC

2
+3VS
+3VALW +3VALW
C324 BAS40-04_SOT23-3
For ATI +CHGRTC
1

1 2 0.1U_0402_16V4Z 1
R261 C518
31.6K_0402_1% U19E U19F
14

14

PM@ SN74LVC14APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14 1U_0402_6.3V4Z

2
P

P
2

11 I O 10 13 I O 12 VGA_ON 17
For NV
1

D
2
SUSP 2 C334
7

G PM@
Q33 S 1U_0402_6.3V6K JALA0
3

2N7002_SOT23 1
PM@

DVT Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDEN IAL
SCHEMATIC MB A4221
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401552
Date Friday, May 16, 2008 Sheet 33 of 50
A B C D E
 A B C D E F G H

+VDDA

+5VAMP
60mil U38 (output = 300 mA)

1
R547 L50 1 2 1
10K_0402_5%
+5VS
KC FBM-L11-201209-221LMAT_0805 IN
OUT 5 40mil +VDDA
1 1 2 GND
L49 1 2 C586 C585 1 4.75V

2
KC FBM-L11-201209-221LMAT_0805 3 4 C588
10U_0805_10V4Z SHDN BYP
1 2
C584 1U_0402_6.3V4Z 2 2
0.1U_0402_16V4Z G9191-475T1U_SOT23-5 4.7U_0805_10V4Z
1

1
C587 2
R554
Cardbus usage for JALA0 10K_0402_5%
1 2 1
C573 1 R550
25 PCM_SPK# 2 1 2

2
1U_0402_6.3V4Z C574 0.01U_0402_16V7K
560_0402_5% 1 2 MONO_IN BOM Option
1U_0402_6.3V4Z
ALC268 268@

1
C
C571 1 2 1
R548
2 2 Q43
1
R551
2
2.4K_0402_1% ALC888S-VB 888VB@
31 BEEP# B
1U_0402_6.3V4Z
560_0402_5% E 2SC2411K_SOT23 ALC888S-VC 888VC@

3
C572 1 R549 L46
23 SB_SPKR 2 1 2
1U_0402_6.3V4Z MBK1608121YZF_0603
10mil

1
560_0402_5% +3VS DVDD 1 2

R544
D30
CH751H-40PT_SOD323-2
HD Audio Codec 1 1
+3VS

1
10K_0402_5% C549 C544
R518

2
0.1U_0402_16V4Z 0_0603_5%
2 2
PM@
10U_0805_10V4Z

2
L47
+AVDD_HDA MBK1608121YZF_0603
10mil +1.5VS_DVDD 1 2 +1.5VS
GM@
L48 1 2 0.1U_0402_16V4Z 40mil 1 1
+VDDA
FBM-L11-160808-800LMT_0603 1 1 C563 C567
C550
C565 0.1U_0402_16V4Z 10U_0805_10V4Z
2 10U_0805_10V4Z 2 2 2

25

38

9
2 2 U36

DVDD
AVDD1

AVDD2

DVDD_IO
14 35 AMP_LEFT
NC LINE_OUT_L AMP_LEFT 35
ESD(JALA0) AMP_RIGHT
15 NC LINE_OUT_R 36 AMP_RIGHT 35
R558 1K_0402_1% INT_MIC1 2 MIC2_C_L 16 39 HP_LEFT
MIC2_L HP_OUT_L HP_LEFT 35
INT_MIC_R 2 1 C578 4.7U_0805_6.3V6K
1 2 MIC2_C_R 17 41 HP_RIGHT
MIC2_R HP_OUT_R HP_RIGHT 35
C579 4.7U_0805_6.3V6K
LINE_L 1 2 LINE_C_L 23 45
35 LINE_L LINE1_L NC
C582 4.7U_0805_6.3V6K
LINE_R 1 2 LINE_C_R 24 46
35 LINE_R LINE1_R DMIC_CLK
C583 4.7U_0805_6.3V6K For EMI
18 CD_L NC 43 DVT(JALA0)
20 44 1 2 1 2 C561 MIC2_VREFO
CD_R NC R541 0_0402_5% 22P_0402_50V8J
19 CD_GND
6
INT(Analog) MIC
BIT_CLK HDA_BITCLK_AUDIO 22

1
MIC1_L 1 2 MIC1_C_L 21
35 MIC1_L MIC1_L
C580 4.7U_0805_6.3V6K R576
MIC1_R 1 2 MIC1_C_R 22 8 HDA_SDIN0_AUDIO 1 2 HDA_SDIN0 22 2.2K_0402_5%
35 MIC1_R MIC1_R SDATA_IN
C581 4.7U_0805_6.3V6K R543 33_0402_5% 15mil JP4
MONO_IN 12 37 1

2
PCBEEP MONO_OUT INT_MIC_R 1
1 2 MIC_R 2 2
29 L59 MBC1608121YZF_0603 3 5
LINE1_VREFO GND_R 3 G1
22 HDA_RST_AUDIO# 11 RESET# 1 1 2 4 4 G2 6
3 C596 R575 0_0603_5% 3
GPIO1 31
22 HDA_SYNC_AUDIO 10 10mil 15mil ACES_88266-04001
SYNC 220P_0402_50V7K CONN@
MIC1_VREFO_L 28 MIC1_VREFO_L 2
2 MIC_GND_R C608
22 HDA_SDOUT_AUDIO 5 SDATA_OUT
Place close to Codec 32 MIC1_VREFO_R 330P_0402_50V7K
MIC1_VREFO_R
DVT(JALA0) HDA_GPIO3
2 GPIO0 1
3 GPIO3 MIC2_VREFO 30 MIC2_VREFO
R556 2 1 39.2K_0402_1% SENSE_A 13 10mil MP(JALA0)
35,38 HP_PLUG# SENSE A
34 27 CODEC_VREF
R557 1 SENSE B VREF
35,38 LINEIN_PLUG# 2 10K_0402_1% 1 1
R555 2 1 20K_0402_1% 47 40 C562
35,38 MIC_PLUG# 31 EAPD EAPD JDREF C560

1
SPDIF 1 2SPDIF_R 48 SPDIFO NC 33 0.1U_0402_16V4Z 10U_0805_10V4Z
R521 0_0402_5% R522 2 2
1 2 4 26 20K_0402_1%
R540 0_0402_5% DVSS1 AVSS1
7 DVSS2 AVSS2 42

2
DGND PVT ALC268-GR_LQFP48_9X9 AGND
Sense Pin Impedance Codec Signals 1
R519
2
0_0805_5%
1
R577
2
0_0805_5%
SA00001GD10 (S IC ALC268-VB1-GR LQFP 48P)
39.2K PORT-A (PIN 39, 41) D34 +3VS
PVT2(JALA0) 1
R520
2
0_0805_5%
1
R578
2
0_0805_5%
1 2
20K PORT-B (PIN 21, 22)
SENSE A CH751H-40PT_SOD323-2
1
1 2 1 2
10K PORT-C (PIN 23, 24) R678 R563 0_0805_5% R568 0_0805_5%
HP_PLUG# 1 2 10K_0402_5%
R659 @ 0_0402_5%
5.1K PORT-D (PIN 35, 36) PVT(JALA0)
2

EC_DOCKIN# 1 2 HDA_GPIO3 GND GNDA GND GNDA

19,28 31,38 EC_DOCKIN#
39.2K PORT-E (PIN 14, 15) R660 @ 0_0402_5%

Use GPIO3 to detect Docking plug or not

20K PORT-F (PIN 16, 17) (The driver behavior is that when driver
SENSE B
DVT(JALA0) detect low,driver will enable SPDIF out)
10K PORT-G (PIN 43, 44)
Security Classification Compal Secret Data Compal Electronics, Inc.
5.1K PORT-H (PIN 45, 46) Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDEN IAL
SCHEMATIC MB A4221
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401552
Date Friday, May 16, 2008 Sheet 34 of 50
A B C D E F G H
 A B C D E

+5VAMP
W=40mil
+3VS
1 1
1
C554 C575
C569 0.1U_0402_16V4Z
C548 0.1U_0402_16V4Z 2 2
0.47U_0603_16V4Z 2 4.7U_0805_10V4Z +5VAMP
1 2 AMP_RIGHT_C-1 1 2 AMP_RIGHT_C
34 AMP_RIGHT C556 1U_0402_6.3V4Z +5VAMP

11

19

20
10

1
1 2 AMP_LEFT_C-1 1 2 AMP_LEFT_C U37 HP_PLUG#
34 AMP_LEFT HP_PLUG# 34,38

2
C547 C555 1U_0402_6.3V4Z

CVDD

HVDD

PVDD
PVDD

VDD
1

3
0.47U_0603_16V4Z R565

2
1 R531 R533 1
100K_0402_5%
R564 Q46B
560_0402_5% 560_0402_5% 3 22 SPKR+ 100K_0402_5% 5 2N7002DW-T/R7_SOT363-6

6 1
INR_A ROUT+ SPKR-
5 21

2
INL_A ROUT-
HPF Fc = 604Hz

4
JALA0 R545 1 2 100K_0402_5% 27 8 SPKL+
/AMP EN LOUT+ SPKL- Q46A
JALA0 R546 1 LOUT- 9
PLUG#
+5VAMP 2 100K_0402_5% 24 HP EN 2 2N7002DW-T/R7_SOT363-6
17 HPOUT_R
+5VAMP HP_RIGHT HP_RIGHT_C 1 HP_RIGHT_R HP_R HPOUT_L
1 2 2 4 18

1
34 HP_RIGHT C546 4.7U_0805_6.3V6K R532 39K_0402_5% HP_LEFT_R INR_H HP_L
6 INL_H
HP_LEFT 1 2 HP_LEFT_C 1 2
34 HP_LEFT
1

C545 4.7U_0805_6.3V6K R530 39K_0402_5% VOL_AMP 26

R553 /SD
CVSS 15
30K_0402_5% 28 BEEP PLUG# 2 HP_PLUG#
VSS 16 1
1 12 1 R661 0_0402_5%
2

CP+ C570 @
14 CP- GND 2
VOL_AMP C558 23 1U_0603_10V4Z
PGND
1U_0603_10V4Z 25 BIAS PGND 7
1

D 2 2
CGND 13
1

1 2 EC_MUTE EC_MUTE 31 1 GND 29

R552 G C576 DVT(JALA0)
100K_0402_1% C577 S Q45 APA2057A_TSSOP28 LINE Out/HP Out JACK
3

2N7002_SOT23 2.2U_0805_10V6K
2
0.01U_0402_16V7K 2
2

JHP1
8
Gain= 14dB 20mil 7
2 2
2 C589 C591 2
FSOV MP(JALA0) PLUG# 5
Int. Speaker Conn. Change 75 to 54.9 ohm 330P_0402_50V7K 330P_0402_50V7K
1 1
4
R559 54.9_0603_1%
HPOUT_R 1 2 HPOU _R_1 1 2 HPOUT_R_2 3
L51 FBM-11-160808-700T_0603 6
HPOUT_L 1 2 HPOU _L_1 1 2 HPOUT_L_2 2
JP1 R560 54.9_0603_1% L52 FBM-11-160808-700T_0603 1
SPKL+ R30 1 2 0_0603_5% SPK_L+ 1
SPKL- R29 1 2 0_0603_5% SPK_L- 2
1 For Docking SINGA_2SJ-E351-S03
2 CONN@
Left D_HPOUT_L R304 1 MAIN@ 2 0_0603_5% HPOUT_L
DVT
38 D_HPOUT_L
3 D_HPOUT_R R305 1 MAIN@ 2 0_0603_5% HPOUT_R
G1 38 D_HPOUT_R
4
20mil DVT
G2
ACES_88266-02001
Change part
MP(JALA0) CONN@
For Docking
JP2
SPKR+ R192 1 2 0_0603_5% SPK_R+ 1 1 D_LINE_L R299 1 MAIN@ 2 0_0603_5% LINE_L
38 D_LINE_L
SPKR- R191 1 2 0_0603_5% SPK_R- 2 2 D_LINE_R R300 1 MAIN@ 2 0_0603_5% LINE_R
38 D_LINE_R
2 C610
C609
2
330P_0402_50V7K Right LINE-IN JACK
330P_0402_50V7K 3 G1
4 G2 JLINE1
1 1 For Docking 8
ACES_88266-02001 7
CONN@ D_MIC_L R306 1 MAIN@ 2 0_0603_5% MIC1_L
38 D_MIC_L
D_MIC_R R308 1 MAIN@ 2 0_0603_5% MIC1_R
38 D_MIC_R
LINEIN_PLUG# 5
34,38 LINEIN_PLUG#
3 3
4
R571 1K_0402_1%
LINE_R 2 1 LINE_R_1 1 2 LINE_R_R 3
34 LINE_R
L55 FBM-11-160808-700T_0603 6
R2 1 2 0_0603_5% LINE_L 2 1 LINE_L_1 1 2 LINE_L_R 2
38 AUDIO_GNDA 34 LINE_L
L56 FBM-11-160808-700T_0603 1
R566 1K_0402_1% 1 1
SINGA_2SJ-E351-S03
ESD DVT(JALA0) C595 C594 CONN@
220P_0402_50V7K 220P_0402_50V7K
Change 75 to 1K ohm 2 2 (HDA Jack)

MIC JACK
JMIC1
MIC1_VREFO_L MIC1_VREFO_R 8
7

1
MIC_PLUG# 5
34,38 MIC_PLUG#
R570 R569
2.2K_0402_5% 2.2K_0402_5% 4
R561 1K_0402_1%

2
2 1 MIC1_R_R 1 2 MIC1_R_1 3
34 MIC1_R
L53 FBM-11-160808-700T_0603 6
2 1 MIC1_L_L 1 2 MIC1_L_1 2
34 MIC1_L
L54 FBM-11-160808-700T_0603 1
R562 1K_0402_1% 1 1
SINGA_2SJ-E351-S01
ESD DVT(JALA0) C593 C592 CONN@
220P_0402_50V7K 220P_0402_50V7K
Change 75 to 1K ohm 2 2
(HDA Jack)

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDEN IAL
SCHEMATIC MB A4221
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401552
Date Friday, May 16, 2008 Sheet 35 of 50
A B C D E
 H8 H2 H14 H19
FAN1 Conn H_3P0 H_3P0 H_3P0 H_3P0

+5VS @ @ @ @

1
C8 10U_0805_10V4Z +5VS
1 2 PVT2(JALA0)

1
U2 D1 H20 H17 H21 H11 H23 H3 H10 H12
1 8 1SS355_SOD323-2 H_3P0 H_3P0 H_3P0 H_3P0 H_3P3 H_3P3 H_3P3 H_3P3
VEN GND
2 VIN GND 7
+VCC_FAN1 3 6

2
EN_DFAN1 VO GND D3 @ @ @ @ @ @ @ @
31 EN_DFAN1 4 5

1
VSET GND
1 2
G993P1UF_SOP8 PVT2(JALA0)
BAS16_SOT23-3
C10
10U_0805_10V4Z H5 H18 H16 H13 H15 H6 H7 H33 H34
1 2 H_3P3 H_3P3 H_3P3 H_3P3 H_4P2 H_4P2 H_4P2 H_3P0 H_3P0
+3VS C16
1000P_0402_50V7K @ @ @ @ @ @ @ @ @

1
1 2

1
R34
10K_0402_5%
40mil JP12 H9 H22 DVT(JALA0)
2

+VCC_FAN1 H_4P1N H_4P6X4P1N

1
31 FAN_SPEED1 2
3 @ @
1

1
C26 ACES_85205-03001
1000P_0402_50V7K CONN@
2

EMI FD1 FD2 FD3 FD4 FD5 FD6

@ @ @ @ @ @

1
+5VALW +5VALW +5VALW
FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80

2 2 2
C601 C602 C603

330P_0402_50V7K 330P_0402_50V7K 330P_0402_50V7K

1 1 1

ADD DVT(JALA0)

EMI

+5VS +5VS
1

C604 C605
820P_0402_50V7K 820P_0402_50V7K
2

ADD PVT(JALA0)

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A4221
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401552
Date Friday May 16 2008 Sheet 36 of 50
 A B C D E

+5VALW TO +5VS +3VALW TO +3V(ICH9M AUX Power) +5VALW

+5VALW +5VS +3VALW +3V

2
U21 U11 R284
8 1 8 1 100K_0402_5%
D S D S
7 D S 2 7 D S 2

2
6 3 1 1 6 3 1 1

1
D S C360 C359 R289 D S C277 C275 R189
1 1 5 D G 4 1 5 D G 4
C361 C362 470_0603_5% C276 470_0603_5% SYSON#
29,30,38 SYSON#
AO4466_SO8 10U_0805_10V4Z AO4466_SO8 10U_0805_10V4Z

6
10U_0805_10V4Z 2 2
1U_0603_10V4Z 2 2
1U_0603_10V4Z

3 1
1 2 2
10U_0805_10V4Z 2
10U_0805_10V4Z 1
Q35A

3
SYSON 2
31,43,44 SYSON
Q16B 2N7002DW-T/R7_SOT363-6

1
Q36B 2N7002DW-T/R7_SOT363-6 5 SBPWR_EN#

1
+VSB 2 1 5VS_GATE 2N7002DW-T/R7_SOT363-6 5 SUSP +VSB 2 1 3V_GATE R281
R285 R188 100K_0402_5%

4
6
200K_0402_5% 1 200K_0402_5% 1

4
6
C358 C249

2
Q16A
Q36A 0.1U_0603_25V7K SBPWR_EN# 2 0.1U_0603_25V7K
SUSP 2
2N7002DW-T/R7_SOT363-6 2 +5VALW
2
2N7002DW-T/R7_SOT363-6

1
1

2
R282
100K_0402_5%

1
SUSP
+3VALW TO +3VS 33,45 SUSP

3
+3VALW +3VS

U20 Q35B
8 D S 1 31,33,45 SUSP# 5
7 2 2N7002DW-T/R7_SOT363-6
D S

2
6 3 1 1

4
D S

1
1 1 5 4 C351 C350 R274
C347 C346 D G 470_0603_5% R283
AO4466_SO8 10U_0805_10V4Z 10K_0402_5%
10U_0805_10V4Z 2 2
1U_0603_10V4Z
1 1
2 2 2
10U_0805_10V4Z 2
AO4468

2
D
2 SUSP
G DVT
S Q34
3

5VS_GATE 2N7002_SOT23

+5VALW

2
+1.8V to +1.8VS +1.5V to +1.5VS R201
100K_0402_5%
+1.8V +1.8VS +1.5V +1.5VS

1
U12 U13
8 D S 1 8 D S 1
7 2 1 1 7 2 1 1 24 SBPWR_EN# SBPWR_EN#
D S D S
2

2
6 3 C283 C284 6 3 C296 C293
D S R195 D S R236
1 1 5 D G 4 1 1 5 D G 4
C265 C264 10U_0805_10V4Z 470_0603_5% C292 C294 10U_0805_10V4Z 470_0603_5%

1
SI4856ADY_SO8 PM@ 2 2
1U_0603_10V4Z PM@ AO4466_SO8 2 2
1U_0603_10V4Z D
10U_0805_10V4Z PM@ PM@ 10U_0805_10V4Z 31,44 SBPWR_EN 2
1

1
PM@ 2 2
10U_0805_10V4Z 2 2
10U_0805_10V4Z G
PM@ SI4856/AO4430 SI4856/AO4430 Q19 S

3
3

1
2N7002_SOT23
R202
Q17B Q23B 100K_0402_5%
+VSB 2 1 1.8VS_GATE 2N7002DW-T/R7_SOT363-6 5 SUSP +VSB 2 1 1.5VS_GATE 2N7002DW-T/R7_SOT363-6 5 SUSP
R203 R222

2
510K_0402_5% 1 PM@ 510K_0402_5% 1
4

4
3 PM@ C285 C297 3
6

6
0.1U_0603_25V7K 0.1U_0603_25V7K
Q17A 2 PM@ Q23A 2
SUSP 2 2N7002DW-T/R7_SOT363-6 SUSP 2 2N7002DW-T/R7_SOT363-6
PM@
1

+1.5VS +2.5VS +1.05VS +0.9VS +1.8V DVT +1.5V

2

R240 R6 R178 R177 R206 R212

470_0603_5% 470_0603_5% 470_0603_5% 470_0603_5% 470_0603_5% 470_0603_5%
PM@ @ @
1

1
1

D D D D D D
2 SUSP 2 SUSP 2 SUSP 2 SUSP 2 SYSON# 2 SYSON#
G G G G G G
S Q26 S Q1 S Q15 S Q12 S Q20 S Q21
3

2N7002_SOT23 2N7002_SOT23 2N7002_SOT23 2N7002_SOT23 2N7002_SOT23 2N7002_SOT23

PM@ @ @

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDEN IAL
SCHEMATIC MB A4221
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401552
Date Friday, May 16, 2008 Sheet 37 of 50
A B C D E
 5 4 3 2 1

3VS 5VS

1
3VS R662 R663
5VS 10K_0402_5% 10K_0402_5%
3VALW
MAIN@ @

1
D R664 D

2
1
R102 10K_0402_5%
EC_DOCKIN#_S0 20

1
10K_0402_5% @

3
R97 MAIN@
Q9B

2
10K_0402_5% 2N7002DW-T/R7_SOT363-6

2
5 MAIN@

6
MAIN@
Q9A

4
2N7002DW-T/R7_SOT363-6
19,28,31,34 EC_DOCKIN# 2 MAIN@

EC_DOCKIN 20

1
1
C600
@
0.1U_0402_16V4Z
2

DVT

10/15 Acer DVR 1028 Rev0.3

JDOCK1
C C
DOCK_B+ 67 ACER DOCK 65
19V_5A GND
5VALW 68 5V_USB_3A GND 66
3VALW
Normal
34,35 LINEIN_PLUG# 33 LIN_IN_DT# GND 1
35 D_LINE_L 34 LIN_IN_L DVI_CLK 2 D_DVI_TXC 20
1

46 P3 P1 1
35 D_LINE_R 35 LIN_IN_R DVI_CLK# 3 D_DVI_TXC- 20
R223 47 (67) (65) 2
34,35 MIC_PLUG# 36 MIC_DT# GND 4
48 3
10K_0402_5% 35 D_MIC_L 37 MIC_L DVI_TX0 5 D_DVI_TXD0 20
49 33 20 4
MAIN@ 35 D_MIC_R 38 MIC_R DVI_TX0# 6 D_DVI_TXD0- 20
AUDIO_GNDA 50 34 21 5
35 AUDIO_GNDA 39 7
2

DOCKIN# GNDA 51 35 22 6 GND

31 DOCKIN# 40 DOCK_DT1# DVI_TX1 8 D_DVI_TXD1 20
52 36 23 7
1 34 SPDIF 41 SPDIF 24 DVI_TX1# 9 D_DVI_TXD1- 20
C306 53 37 8
42 GND GND 10
0.1U_0402_16V4Z D_LAN_MIDI2 54 38 25 9
28 D_LAN_MIDI2 43 LAN_2 DVI_TX2 11 D_DVI_TXD2 20
D_LAN_MIDI2- 55 39 26 10
44 12
2 MAIN@
28 D_LAN_MIDI2-
45
LAN_2#
GND
56 40
57 41
27 11
28 12
DVI_TX2#
GND 13
D_DVI_TXD2- 20
PVT
14 D_CRT_R_R R669 1 MAIN@ 2 0_0603_5%
58 42 29 13 VGA_R D_CRT_R 19
59 43 30 14 GND 15
46 16 D_CRT_R_G R670 1 MAIN@ 2 0_0603_5%
GND 60 44 31 15 VGA_G D_CRT_G 19
USB20_P3 47 17
23 USB20_P3 USB 61 45 32 16 GND
USB20_N3 48 18 D_CRT_R_B R671 1 MAIN@ 2 0_0603_5%
23 USB20_N3 USB# 62 17 VGA_B D_CRT_B 19
29,30,37 SYSON# 49 USB_EN# GND 19
63 P4 P2 18
50 RESERVED 64 (68) 66) 19
51 MAIN@
VGA_DT# DOCK_DT2# R1
52 LAN_PWR DOCK_DT2# 20 1 2 1K_0402_5%
28 D_LAN_ACTIVITY# 53 LAN_ACT HP_L 21 D_HPOUT_L 35
28 D_LAN_LINK# 54 LAN_LINK HP_R 22 D_HPOUT_R 35
B B
55 GND HP_DT# 23 HP_PLUG# 34,35
28 D_LAN_MIDI0 D_LAN_MIDI0 56 24 AUDIO_GNDA
D_LAN_MIDI0- LAN_0 GNDA
28 D_LAN_MIDI0- 57 LAN_0# DVI_DT 25 D_DVI_DET 20
58 GND DVI_DCDT 26 D_DVI_SDATA 20
28 D_LAN_MIDI1 D_LAN_MIDI1 59 27 D_DVI_SCLK 20
D_LAN_MIDI1- LAN_1 DVI_DDCCK
28 D_LAN_MIDI1- 60 LAN_1# VGA_VS 28 D_CRT_VSYNC 19
61 GND VGA_HS 29 D_CRT_HSYNC 19
28 D_LAN_MIDI3 D_LAN_MIDI3 62 30
LAN_3 VGA_DDCCK D_DDC_CLK 19
28 D_LAN_MIDI3- D_LAN_MIDI3- 63 31
LAN_3# VGA_DDCDT D_DDC_DATA 19
64 GND 5V_S0 32 5VS

72 GND GND 69
73 GND ACER DVR1027 Rev: 0.5 GND 70
74 GND GND 71
JAE_SP07-10207-22
CONN@

PVT2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT AL
SCHEMATIC MB A4221
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401552
Date: Friday, May 16, 2008 Sheet 38 of 50
5 4 3 2 1
 A B C D

Place at HW side

PD11
VIN
PDS1040-13_POWERDI5-3
2
1
3
DOCK_B+

SP02000EF00
PJP1
PR1
6 1M_0402_1%
G2
1 2
5 PL1 VIN VIN
G1 SMB3025500YA_2P PJ1 VS
DC_IN_S1 1 2DC_IN_S2 2 1
2 1

1
4 4
JUMP_43X79 PR2 PR3
10K_0402_5% 84.5K_0402_1%
3 PR5
3

8
PC2 PR4 PD2 22K_0402_5%

2
PC3 PC4 100P_0402_50V8J PC1 10K_0402_5% 1SS355_SOD323-2 3 1 2

P
1000P_0402_50V7K 100P_0402_50V8J 1000P_0402_50V7K +
2 1 2 2 1 1

2
2 23,31,42 ACIN 0

20K_0402_1%
- 2

1
G

PR6
PU1A

1
PC6
0.1U_0603_25V7K
1 LM358DT_SO8 PC5

4
1 PR7 PD3 1000P_0402_50V7K

2
10K_0402_5% GLZ4.3B_LL34-2

2
E&T_4510-E04C-01R

2
<BOM Structure>
PR8
10K_0402_5%
1 2
RTCVREF

2 2

Vin Dectector
Min. Typ Max.
- PBJ1 + H-->L 16.976V 17.525V 17.728V
2 1 +RTCBATT L-->H 17.430V 17.901V 18.384V
+RTCBATT

ML1220T13RE
45@

VIN 2
PJ2
1 2
PJ3
1
+3VALWP 2 1 +3VALW +1.5VP 2 1 +1.5V
JUMP_43X118 JUMP_43X118
2

PD4
LL4148_LL34-2

PD5 PJ4 PJ5

1

LL4148_LL34-2 2 1 2 1
+5VALWP 2 1 +5VALW +0.9VSP 2 1 +0.9VS
BATT+ 2 1
1

3 3

JUMP_43X118 JUMP_43X79
PR9 PR10
PQ1 68_1206_5% 68_1206_5%
TP0610K-T1-E3_SOT23-3
PR11
PJ6
2

200_0603_5% PJ7
CHGRTCP 1 2 N1 3 1 2 1 +1.8VP 2 1 +1.8V
VS +VSBP 2 1 +VSB 2 1
JUMP_43X39 JUMP_43X118
1

PR12 PC8
100K_0402_1% PC7 0.1U_0603_25V7K
0.22U_1206_25V7K
2

PR13 PJ8 PJ9

2

22K_0402_1% 2 1 2 1
+1.05VSP 2 1 +1.05VS +2.5VSP 2 1 +2.5VS
1 2
33 51ON# JUMP_43X118 JUMP_43X118

RTCVREF PJ16 PJ17

1

+1.05VSP 2 2 1 1 +1.05VS +1.8VP 2 2 1 1 +1.8V

PR14
PU2 200_0603_5% JUMP_43X118 JUMP_43X118
PR15 PR16 G920AT24U_SOT89-3
560_0603_5% 560_0603_5% 3.3V
2

1 2 1 2 3 2 N2
OUT IN
+CHGRTC
1

GND PC10
4
PC9 1U_0805_25V4Z 4

10U_0805_10V4Z 1
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A4221
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401552
Date Friday, May 16, 2008 Sheet 39 of 50
A B C D
 A B C D

PH1 under CPU botten side :

CPU thermal protection at 96 degree C
Recovery at 60 degree C
VL
VL
VL
VMB

2
PL2
SMB3025500YA_2P PR17

1
BATT_S1 1 2 BATT+ 47K_0402_1%
PH1 PC11
MAINPWON 22,41
100K_0603_1%_TH11-4H104FT 0.1U_0603_25V7K PR18

1
1

1
47K_0402_1%

1
PC12 PC13 1 2

2
1000P_0402_50V7K 0.01U_0402_25V7K PR19 PQ2

8
13.3K_0402_1% DTC115EUA_SC70-3
1 2 3 PD6

P
+
O 1 2 1 2
EC_SMCA TM_REF1 2 -

G
PU3A LL4148_LL34-2
LM393DG_SO8

3
0.22U_0603_16V7K

13.3K_0402_1%
1

1
PC14
PR23

1000P_0402_50V7K
PR22
PJP2 100K_0402_1%
PR24 2 1 VL

1
1 2 6.49K_0402_1%
1 2

PC15
2 1 +3VALWP

2
3 4

2
3 4

1
5 5 6 6

1
7 8 PR26 PR25
7 8 1K_0402_1% 100K_0402_1%
9 10

2
9 10

2
11 11 12 12
2
BATT_TEMP 31 2
13 13 14 14

15 15 16 16 PR21
17 17 18 18 2 1 EC_SMB_CK1 17,31
19 20
PH2 near main Battery CONN :
19 20 100_0402_1%
SUYIN_200109MS020G209ZR
BAT. thermal protection at 79 degree C
Recovery at 47 degree C
VL
PR20

2
EC_SMDA 2 1 EC_SMB_DA1 17,31
@ PR27
@PR27
VL 47K_0402_1%
100_0402_1% @PR28
@ PR28
47K_0402_1%

1
1 2

1
PQ3
TP0610K-T1-E3_SOT23-3
@PH2
@ PH2
100K_0603_1%_TH11-4H104FT VL

B++ 3 1 +VSBP

2
0.22U_1206_25V7K

0.1U_0603_25V7K

PR30
1

8
@ 9.09K_0402_1% @PD7
@ PD7
1

1
PC16

PC17

PR29 1 2 5 LL4148_LL34-2

P
100K_0402_1% +
O 7 2 1
@ @ TM_REF1 6
2

G
3 3

PR31 PU3B
2

1
VL 22K_0402_1% LM393DG_SO8

4
1 2 @ PC18
@PC18 @ PR32
@PR32
0.22U_0603_16V7K 22.1K_0402_1%

2
2

PR33
100K_0402_1%

PR34
1

0_0402_5% D
1 2 2 PQ4
41 SPOK G 2N7002W-T/R7_SOT323-3
0.1U_0402_16V7K

S
3
1

PC19

@
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A4221
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401552
Date Friday, May 16, 2008 Sheet 40 of 50
A B C D
 5 4 3 2 1

ISL6237_B+
ISL6237_B+
PL12 B++ PL13 PR35
FBMA-L11-322513-151LMA50T_1210 FBMA-L11-322513-151LMA50T_1210 0_0805_5%
1 2 1 2 1 2
D
B+ D
470P_0402_50V7K

470P_0402_50V7K

470P_0402_50V7K

470P_0402_50V7K

2200P_0402_50V7K

2200P_0402_50V7K
4.7U_1206_25V6K

4.7U_1206_25V6K
1

1
PC160

PC161

PC162

1
PC20
PC159

4.7U_1206_25V6K

4.7U_1206_25V6K
1

5
6
7
8
PC21

PC22
2

8
7
6
5

1
PC25
VL

PC23

PC24
1U_0603_10V6K
2

2
PQ6

2
2
PQ5 PC26 AO4466_SO8

2
AO4466_SO8 0.1U_0603_25V7K

4.7U_0805_6.3V6K
4

1
PC27
4

PC28
1
+5VALWP

3
2
1
PL4

1
2
3
PL3 8.2UH_PCMB063T-8R2MS_4.5A_20%

7
8.2UH_PCMB063T-8R2MS_4.5A_20% PC29 2 1
1 2 1U_0603_10V6K

LDO
VIN

VCC
+3VALWP 33 19 1 2
TP PVCC

5
6
7
8

1
4.7_1206_5%
1

8
7
6
5

PR39
DH3 26 15 DH5
PR36 PR37 UGATE2 UGATE1 PR40 2.2_0603_5% PQ8
4.7_1206_5% PQ7 2 1 BST3A 24 17 BST5A 2 1 AO4712_SO8
BOOT2 BOOT1
2

1 AO4712_SO8 2.2_0603_5%

2
2

61.9K_0402_1%
PR38 PC32 4

2
PC30 + 0_0402_5% 4 PC31 0.1U_0603_25V7K

2
330U_D3L_6.3VM_R25M 0.1U_0603_25V7K

1
1

PR41
LX3 25 16 LX5 PC34 1
1

2 PC33 PHASE2 PHASE1 680P_0402_50V7K

3
2
1

2
C 680P_0402_50V7K + PC35 C

1
2
3
DL3 23 18 DL5 150U_D2E_6.3VM_R18

1
LGATE2 LGATE1
2
2

10K_0402_1%
PGND 22

2
FB3 30 OUT2

PR43
@ PR42
10K_0402_1% 10
OUT1
VL 32
1

REFIN2

1
11 FB5
2VREF ISL6237 FB1

1 2 1 REF
PC36 0.22U_0603_10V7K
BYP 9
8 LDOREFIN @ PR44 0_0402_5%
+3.3VALWP Ipeak=8.444A ; Imax=5.91A SKIP 29 2 1 VL
Choke DCRmax=60m ohm, DCRtyp=54m ohm PR45 0_0402_5%
Rds(on)=18m ohm(max) ; Rds(on)=15m ohm(typical) 1 2
20 28
Vlimit=(5E-06 * 330K)/10=165mV PD8 PR46 NC POK2
Ilimit=165mV/18m ~ 165mV/15m GLZ5.1B_LL34-2 100K_0402_1%
1 2 1 2 4 13 SPOK 40
=9.167A ~ 11A VS EN_LDO POK1 PR48
2
200K_0402_5%

Iocp=Ilimit+Delta I/2 330K_0402_1%

2

B B
PR47

PC37 14 12 ILM1 2 1
=10.134A ~ 11.967A 0.22U_0603_25V7K EN1 ILIM1
1

Delta I=1.934A (Freq=300KHz)

1

PD12 27 31 ILIM2 2 1

GND
TON
1

1SS355_SOD323-2 EN2 ILIM2

NC
VL
2

0_0402_5%
2 PR49
@ PR50 PU4 330K_0402_1%
2

21
PR51

0_0402_5% ISL6237IRZ-T_QFN32_5X5
2

PR52
1

1
1U_0603_10V6K
806K_0603_1%
2VREF_ISL6237 1

PR54 @ PR55 PR53

+5VALWP Ipeak=8.444A ; Imax=5.91A
1

2
0_0402_5% 47K_0402_5% 0_0402_5%
PC143

22,40 MAINPWON
2 1 1 2
2VREF_ISL6237 2
Choke DCRmax=60m ohm, DCRtyp=54m ohm
1

Rds(on)=18m ohm(max) ; Rds(on)=15m ohm(typical)

0.047U_0603_16V7K

Vlimit=(5E-06 * 330K)/10=165mV
1

PC38

Ilimit=165mV/18m ~ 165mV/15m
2

=9.167A ~ 11A
3

@ PC39
0.047U_0402_16V7K
Iocp=Ilimit+Delta I/2
2

=10.147A ~ 11.980A
2 PQ35
TP0610K-T1-E3_SOT23-3 Delta I=1.96A (Freq=400KHz)
A A
1

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT AL
SCHEMATIC MB A4221
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401552
Date: Friday, May 16, 2008 Sheet 41 of 50
5 4 3 2 1
 A B C D

B+
PQ9 PQ10
SI4835BDY-T1-E3_SO8 SI4835BDY-T1-E3_SO8 PR56
VIN 8 3 3 8 0.015_2512_1%
7 2 2 7 PJ11
6 1 1 6 1 4 2 1 CHG_B+
2 1

1
5 5

2
2200P_0402_25V7K
4.7U_1206_25V6K

4.7U_1206_25V6K
2 3 JUMP_43X118 PR57
PR58 CHGEN# PC40 100K_0402_1%

2
0.01U_0402_25V7K
3.3_1210_5% 0.01U_0402_25V7K

1
100K_0402_1%

PC42

PC43

PC44

2
1
PC46 PC48

1
2

5
6
7
8

1
2
3
PC45

PR59
0.1U_0402_16V7K PU5 0.1U_0805_25V7K
1 2 1 28 PVCC 1 2 PQ12
CHGEN PVCC

1
SI4835BDY-T1-E3_SO8

1
PR174 PR61 /BATDRV 4

2
3.3_1210_5% PC47 @PC49
@PC49 2.2_0603_5% PQ11
0.1U_0603_25V7K 0.1U_0603_25V7K 27 BTST 1 2 4 AO4466_SO8

2
BTST

2
1 2
PR60
340K_0402_1% ACN 2 26 DH_CHG
ACN HIDRV
@PD9
@ PD9 1 ACP 3

3
2
1

5
6
7
8
RLZ24B_LL34 PC50 ACP PR62

1
2.2U_0805_25V6K ACDRV 4 25 LX_CHG PL5 0.02_2512_1%
2

ACDET ACDRV PH PD10 10UH_PCMB104T-100MS_6A_20%

5
BATT+
2

ACDET
2 1 1 2 1 2 1 4

10U_1206_25V6M
Place close to back to back MOS

10U_1206_25V6M
LL4148_LL34-2 PC51

REGN
2 3

2
0.1U_0603_25V7K

5
6
7
8

PC53
24751_VREF PR63 PR64

PC52
CELLS GND 3 Cell 54.9K_0402_1% ACSET 6 4.7_1206_5%
ACSET
24

2
REGN
VREF 4 Cell
1
2

1
PC54 PQ13
@ PR65
@PR65 1U_0603_10V6K 4 AO4466_SO8

1
100K_0402_1% PR66 PC56 PC55

2
2

0_0402_5% 0.47U_0603_16V7K 680P_0402_50V7K

1 2 1 2 7
1

2
PR67 ACOP DL_CHG
23

3
2
1
340K_0402_1% LODRV
CELLS
1

PGND 22
@ PQ14 OVPSET 8 PC57
OVPSET
1

2 D 2N7002W-T/R7_SOT323-3 0.1U_0402_16V7K 2

2 3S/4S# 31 1 2
G 9 21 ACOFF 31
AGND LEARN
2

S
3

1
PR68
54.9K_0402_1% PC58 @PC59
@PC59
24751_VREF CELLS 0.1U_0603_25V7K 0.1U_0603_25V7K
Cells selector 20

2
CELLS
1

24751_VREF 10
PQ15 VREF
3

1
SI2301BDS-T1-E3_SOT23-3 PC60
1U_0603_10V6K
PR69 RTCVREF 19 SE_CHG+

2
100K_0402_1% SRP
CP Point Setting 1 2PQ15_GATE
2 11 VDAC SRN 18 SE_CHG-

CP point=Iadapter*85% BAT 17
1

1
90W adapter PC62 PR70 VADJ 12
0.1U_0603_25V7K 100K_0402_1% VADJ PC61
Vacset=3.3*(100K/(64.9K+100K))=2.001V
2

ACSET 0.1U_0603_25V7K

2
CP Point=(Vacset/Vvdac)*(0.1/PR56)=4.04A 29 Icharge Setting
2

ACGOOD# TP
13 ACGOOD ICHG setting PR71 For 2200mA, Icharge=0.8C=0.8*2*2.2=3.52A
65W adapter R=(100K*100K)/(100K+100K)=50K 17.4K_0402_1% For 2400mA, Icharge=0.8C=0.8*2.4*2=3.84A
VMB 16 SRSET 2 1 Icharge=(Vsrset/Vdac)*(0.1/PR62)
Vacset=3.3*(50K/(50K+64.9K))=1.436V /BATDRV 14
SRSET IREF 31 IREF*(100k/(100K+17.4K)/3.3)*(0.1/0.02)=Icharge
BATDRV

1
PR72
IREF=0.77448*Icharge

1
CP POINT=(1.436V/3.3V)*(0.1/0.015)=2.901A 10_0603_5% PR73
1

15 1 2 100K_0402_1% @PC63
@PC63
IADAPT 0.01U_0402_25V7K

2
VS PR74 BQ24751ARHDR_QFN28_5X5 24751_VREF
Input OVP : 22.3V

2
3 3

LI-4S :18.0V----BATT-OVP=2.001V 340K_0402_1%

1
Input UVP : 17.26V
2

2
0.01U_0402_25V7K

BATT-OVP=0.1112*VMB PC64
Fsw : 300KHz 100P_0402_50V8J @ PR75
@PR75

2
LI-3S :13.5V----BATT-OVP=1.5012V 100K_0402_1%
1

PC65

24751_VREF 24751_VREF ADP_I 31 @PR176

@ PR176
1

BATT-OVP=0.1112*VMB 0_0402_5% 24751_VREF

1
200K_0402_1%
PR76 1 2
2

1
100K_0402_1%

Per cell=3.5V 499K_0402_1% ACIN 23,31,39

1

1
PR180

PQ15_GATE

1
D
PR179

PR78
2
8

PR77 PU1B 887K_0402_1% ACGOOD# 2 @ PQ16

1
10K_0402_1% LM358DT_SO8 D PQ17 G 2N7002W-T/R7_SOT323-3
5
P

+ PQ36 SI2301BDS-T1-E3_SOT23-3 PR80

1 2 7 0 2 S
2

3
31 BATT OVP 6 PC163 G SSM3K7002F_SC59-3 0_0402_5%
-
1
G

S
0.1U_0402_16V7K REGN VADJ

D
S 3 1 1 2
3
1

24751_VREF
0.01U_0402_25V7K

ACOFF 1 2 2
4

PR79 G

1
PC66

105K_0402_1%

G
S
3

2
1

2
340K_0402_1%

221K_0402_1%

100P_0402_50V8J
PQ37 PR82
2

1
PR181

SSM3K7002F_SC59-3 100K_0402_1% PR81

2

PR84

PC144
@PR177
@ PR177 100K_0402_1%
PR83 4.3K_0402_5%

2
64.9K_0402_1%
2

1
24751_VREF 1 2 ACSET CHGEN#

2
1
D
1

1
PQ19 D
2
31 CALIBRATE# G 2N7002W-T/R7_SOT323-3 2 PQ18
PR85
31 FSTCHG 2N7002W-T/R7_SOT323-3
S G

3
100K_0402_1% S

3
1

4 4
2

PR86
100K_0402_1%
1

D
31 65W/90W# 2 Charger ADJ Calibrate# PR78 PR84
2

G
PQ20 S
3

2N7002W-T/R7_SOT323-3 4.0V L @ @ Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title
4.1V L 887K 221K SCHEMATIC MB A4221
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
CP setting 4.2V H @ @
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401552
Date Friday, May 16, 2008 Sheet 42 of 50
A B C D
 A B C D

PC68

1
PC67 1U_0402_6.3V6K
1U_0402_6.3V6K

2
PR87 PR88
2.2_0603_1% 2.2_0603_1%
+5VALW 2 1 1 2 +5VALW

1
PC70 PC69
0.1U_0603_25V7K 0.1U_0603_25V7K

2
PJ12
JUMP_43X118 PR89 PR90
2 2 10_0603_1% 10_0603_1%
1 1
B+ ISL6228_B+ ISL6228 B+ 2 1 2 1 ISL6228 B+

22K_0402_1%

2
1000P_0402_50V7K
2
PR92

PR91
18.2K_0402_1%

1
PC72 PR93 PC71

PC73
1000P_0402_50V7K 3.3K_0402_5% PR94 1000P_0402_50V7K

1
2 1 1 2 60.4K_0402_1%

2
1
PR95

1
45.3K_0402_1%
FB_1.05V 2 1 FB_1.05V-1 29

PGOOD1

FSET1

VIN1

VCC1

VCC2

VIN2

FSET2
GND_T
PR98 PC74

2
PR96 3.3K_0402_5% 1000P_0402_50V7K
11.8K_0402_1% 8 28 PR97 2 1 1 2
2
6228_1.05VO1 FB1 PGOOD2 22.6K_0402_1% 2
1 2

PR99

1
45.3K_0402_1%
ISL6228 B+ 9 27 FB_1.8V-1 1 2 FB_1.8V
VO1 FB2
4.7U_1206_25V6K

4.7U_1206_25V6K

PR100
1

1
PC76

PC77

10K_0402_1%
8
7
6
5

PC75 OCSET_1.05V 10 26 6228_1.8VO2 1 2

0.015U_0402_16V7K OCSET1 VO2
2

1 2 PQ21
AO4466_SO8
Vref=0.6V
2

PR101 4 1.05V_EN 11 25 OCSET_1.8V

11.8K_0402_1% EN1 PU6 OCSET2
PR103
PL6 ISL6228HRTZ-T_QFN28_4X4 0_0402_5% SYSON 31,37,44 ISL6228 B+
+1.05VSP 1UH_MSCDRI-104R-1R0N-F_11A_30% 1 2
1

1
2
3

2 LX_1.05V 12 24
PHASE1 EN2 @ PC78
@PC78
1

4.7U_1206_25V6K

4.7U_1206_25V6K
0.01U_0402_25V7K PC82

5
6
7
8

1
PC81

PC79
1 2 0.022U_0402_16V7K
8
7
6
5

1 PR104 1 2
4.7_1206_5% PQ22 UG_1.05V 13 23
D
D
D
D

2
PC80 + FDS6670AS_NL_SO8 UGATE1 PHASE2
2

2
330U_D2E_2.5VM PR105
PR106 4 PQ23 10K_0402_1%
2 2.2_0603_5% AO4466_SO8
G 4
1

PC83 2 1 2 1BST_1.05V
14 BOOT1 UGATE2 22 UG_1.8V
680P_0402_50V7K PL7

1
S
S
S

LGATE1

LGATE2
PC84 1UH_MSCDRI-104R-1R0N-F_11A_30%
PGND1

PGND2

BOOT2
PVCC1

PVCC2
2

3
2
1
3 3

0.1U_0402_16V7K LX_1.8V 1 2
1
2
3

+1.8VP

5
6
7
8
PR108
DCR 6m ohm(max) Cout ESR=15m ohm PQ24 4.7_1206_5% 1

D
D
D
D
15

16

17

18

19

20

21
FDS6670AS_NL_SO8
+ PC88
+1.05VSP OCP Seting is same as ICL50

2
PR109 PC87 330U_D2E_2.5VM
Vo=Vref*((PR80+PR82)/PR80) 2.2_0603_5% 0.1U_0402_16V7K 4 G

1
BST_1.8V 1 PC89 2
Ipeak=14.02A, Imax=9.81A +5VALW 2 1 2
680P_0402_50V7K
Iocp=14.02*1.2=16.824A +5VALW
2

S
S
S

2
Csen=L/(Rocset*DCR) PC85 PC86

3
2
1
1U_0402_6.3V6K 1U_0402_6.3V6K
0.015U=1U/(Rocset*6m) Rocset=11.111K~11.8K
1

Iocp=(Rocset*10uA)/DCR
Iocp=(11K*10uA)/(6m ohm*1.3) =15.1A DCR 6m ohm(max) Cout ESR=15m ohm
LG_1.05V LG_1.8V
Vo=0.6*((PR87+PR83)/PR83)=1.8V
1.8VP Ipeak=11.93A, Imax=8.351A
Csen=L/(Rocset*DCR)=1uF/(Rocset*6m ohm)=0.022uF
=>Rocset=7.575K, Choose 10K because of thermal factor
PR110 Iocp=(Rocset*10uA)/DCR=(10K*10uA)/(0.006*1.3)=12.82A
0_0402_5%
2 1 1.05V_EN
33 VS ON
1

@ PC90
@PC90
0.01U_0402_25V7K
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A4221
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401552
Date Friday, May 16, 2008 Sheet 43 of 50
A B C D
 5 3 2 1

D
@PR178
@ PR178 D
0_0402_5%
1 2
31,37 SBPWR_EN
PJ13

4.7U_1206_25V6K
JUMP_43X118

PR111 8
PQ26
1
51117_B+ 2 2 1 1 B+
G2 D2

PC91
143K_0402_1% 7 2
PR112 S2/D1 D2
1 2 6 S2/D1 G1 3
0_0402_5% 5 4

2
S2/D1 S1
1 2
31,37,43 SYSON AO4932_SO8
<BOM Structure>
PR113 PC93 PL8
0_0603_1% 0.1U_0603_25V7K 2.2UH_MSCDRI-74A-2R2M-E_6.5A_20%

15

14
1

1
@PC94
@PC94
PU7 BST_1..5V 1 2BST_1..5V-1 1 2 1 2 +1.5VP

EN_PSV

TP

VBST
0.1U_0402_16V7K

2
2 13 DH_1..5V
TON DRVH
3 12 LX_1..5V 1
VOUT LL
VFB=0.75V + PC95
4 V5FILT TRIP 11 +5VALW 330U_D2E_2.5VM
5 VFB V5DRV 10
2
6 9 DL_1.5V DL_1.5V
PGOOD DRVL

PGND
PR114

GND

1
17.8K_0402_1%
0_0603_1%

PR115
1 2 @ PC96
@PC96 PC97
C +5VALW 47P_0402_50V8J TPS51117RGYR_QFN14_3.5x3.5 4.7U_0805_10V6K C

2
1 2
1

2
PC98
1U_0603_10V6K
2

PR116
10K_0402_1%
1 2
1

PR117
10K_0402_1%
2

VFB=0.75V
Vo=VFB*(1+PR87/PR88)=0.75*(1+10K/10K)=1.5V
Ton=19*e-12*143000(((2/3)*Vo+100mV)/19)+50ns
=2.645e-7 us
=>Vo/Vin=D=Ton/Ts =>Ts=3.35us
Fsw=298KHz

B Cout ESR=15m ohm B

Ipeak=4.71A, Imax=3.297A, Iocp=5.652A

Delta I=((19-1.5)*(1.5/19))/(L*Fsw)=2.107A
=>1/2DeltaI=1.053A
Vtrip=Rtrip*10uA=17.8K*10uA=0.178V
Iocpmin=Vtrip/Rdsonmax*1.2+1.053A
=0.178/(0.027*1.2)+1.053=5.493A+1.053A=6.546A
Iocpmax=(0.178/(0.021*1.1))+1.053A=7.705A+1.053A
=8.758A
Iocp=6.546A~8.758A

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A4221
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401552
Date Friday May 16 2008 Sheet 44 of 50
5 3 2 1
 5 3 2 1

D D

+1.8V

+3VALW

1
PJ14

1
JUMP_43X79
+5VALW
2

1
2 PU8
1 6 +3VALW

1
VIN VCNTL PJ15
C JUMP_43X79 C
2 GND NC 5
2

2
PM@PC105

1
PC99 3 7 PC100 1U_0603_6.3V6M

2
4.7U_0805_6.3V6K PR118 REFEN NC 1U_0603_6.3V6M
1

2
1K_0402_1% 4 8
VOUT NC

6
2 GND 9

1
5 PM@PC102

VCNTL
VIN 4.7U_0805_6.3V6K
RT9173DPSP_SO8 7 POK
4

2
VOUT

0.1U_0402_16V7K
PR119 PQ27
+0.9VSP
1

1
0_0402_5% 2N7002W-T/R7_SOT323-3 D PM@PR124 3
VOUT
+2.5VSP
PC101
33,37 SUSP 1 2 2 PR120 0_0402_5%

1
G 1K_0402_1% 2 31,33,37 SUSP# 1 2 8 EN FB 2
1

1
S PC104

GND
3

PC103 10U_0805_6.3V6M 9 PM@PR122 PM@PC107

2

2
VIN

1
0.1U_0402_16V7K 2.15K_0402_1% 0.01U_0402_25V7K
2

1
PM@PC116 PM@PC106

2
0.1U_0402_16V7K PM@PU11 22U_0805_6.3V6M

2
APL5915KAI-TRL_SO8

2
1
PM@PR123
1K_0402_1%

2
B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A4221
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401552
Date Friday May 16 2008 Sheet 45 of 50
5 3 2 1
 5 3 2 1

+5VS

B+
CPU_VID6 5 CPU_B+

2
CPU_VID5 5 PR125 PL9
1_0603_5% FBMA-L18-453215-900LMA90T_1812
CPU_VID4 5 2 1
31,33 VR_ON

2200P_0402_50V7K
10U_1206_25V6M

10U_1206_25V6M
CPU_VID3 5
PR126 1

1
PC112

PC113
D
499_0402_1% CPU_VID2 5 D

PC114
8,23 PM_DPRSLPVR 1 2 PC110 + PC115
PC109 2.2U_0603_6.3V6K 220U_25V_M
CPU_VID1 5

2
5
PR127 0_0402_5% 0.022U_0402_16V7K

2
2
5,8,22 H_DPRSTP# 1 2 CPU_VID0 5
PR128 0_0402_5%
1 2 PQ29

1
PR130 0_0402_5%

PR131 0_0402_5%

PR132 0_0402_5%

PR133 0_0402_5%
16 CLK_ENABLE#

PR129 0_0402_5%

PR135 0_0402_5%

PR136 0_0402_5%

PR137 0_0402_5%
4 SI7686DP-T1-E3_SO8
PR134 0_0402_5%
+3VS 1 2
+3VS

3
2
1
1
1U_0603_6.3V6M
1.91K_0402_1%
PR138 PC119 PL10

PC118
2.2_0603_5% 0.22U_0603_10V7K 0.36UH_FDU1040D-R36M_26A_20%
+CPU_CORE
1
BOOT_CPU1 1 2 1 2 2 1

2
2

PR140
PR139

5
6
7
8

1
10K_0402_1%
6.8_1206_5%

3.65K_0805_1%
5
6
7
8

1
PR142

PR143

PR144
499_0402_1%

49

48

47

46

45

44

43

42

41

40

39

38

37
UGATE_CPU1 PR145
2

1_0402_5%

3V3

CLK_EN#

DPRSTP#

VID6

VID5

VID4

VID3

VID2

VID1

VID0
GND

DPRSLPVR

VR_ON
1

@ PR146
@PR146

1 2

2
680P_0402_50V7K
1 36 4 PQ31 0_0603_5%

2
8,16,23 VGATE PGOOD BOOT1 AO4456_SO8
4 1 2

PC120
5 PSI# 1 2 2 35 VSUM PC121
PR147 0_0402_5% PSI# UGATE1 PQ30 1 2

2
31 PGD_IN 1 PR148 2 3 34 PHASE_CPU1 AO4456_SO8 VCC_PRM

3
2
1
PR149 PMON PHASE1 ISEN1

3
2
1
@ 0_0402_5% 1 2 147K_0402_1% 4 33 0.22U_0603_10V7K
RBIAS PGND1
VR_TT# 5 32 LGATE_CPU1 CPU_B+
VR_TT# LGATE1

2200P_0402_50V7K
5
C C
6 NTC PVCC 31

10U_1206_25V6M

10U_1206_25V6M
1

1
7 PU10 30 LGATE_CPU2
SOFT LGATE2

PC122

PC123

PC124
ISL6262ACRZ-T_QFN48_7X7 PQ32
PC125 8 29 SI7686DP-T1-E3_SO8

2
0.022U_0603_25V7K OCSET PGND2
4
1 2 9 28 PHASE_CPU2
VW PHASE2
PR151 13K_0402_1% 10 27 UGATE_CPU2-1 PL11
COMP UGATE2 0.36UH_FDU1040D-R36M_26A_20%
1 2

3
2
1
11 26 BOOT_CPU2
1 2 1 2 2 1
FB BOOT2 PR152
1 2

1
6.8_1206_5%
PC126 1000P_0402_50V7K 2.2_0603_5% PC127
DROOP

12 FB2 NC 25

1
VDIFF

ISEN2

ISEN1
VSUM

10K_0402_1%
PR154
VSEN

3.65K_0805_1%
PR153 6.81K_0402_1% 0.22U_0603_10V7K
GND

VDD
RTN

DFB

5
6
7
8

5
6
7
8

1
VIN

PR155
VO

1 2

PR157
PQ33 PQ34
1 2 AO4456_SO8 AO4456_SO8 PR156
13

14

15

16

17

18

19

20

21

22

23

24

1 2
1_0402_5%

2
PC128 1000P_0402_50V7K @ PR159
@PR159

2
680P_0402_50V7K
PC129
ISEN1 4 4 0_0603_5%
ISEN2 1 2

2
PR161 2

@ 0_0402_5%

PR160 97.6K_0402_1% PC130 1 2 +5VS

2 PR162 1
1K_0402_1%

1 2 2 1 PR158 1_0603_5% VSUM

1

1 2

3
2
1

3
2
1
470P_0402_50V7K PC131
1 2 1U_0402_6.3V4Z PC132
1

0.22U_0603_10V7K
PC133 220P_0402_50V7K VCC_PRM
PR163 PR164 ISEN2
255_0402_1% PC134 1000P_0402_50V7K 10_0603_5%
1 2 1 2 1 2 CPU_B+
B B
1

1 2 PC135
PR165 1K_0402_1% 0.1U_0603_25V7K
PR166
2

0_0402_5% PC136 820P_0402_50V7K

5 VCCSENSE 1 2 1 2
VSUM
1

PR167
1

20_0402_5% PC137 PC138

+CPU_CORE 1 2 @0.022U_0603_50V7K 0.01U_0603_50V7K PR168
2

PR169 2.61K_0402_1%
2

0_0402_5%
5 VSSSENSE 1 2
2
1
11K_0402_1%

PC139 180P_0402_50V8J
2

PR171

1 2
2

PR170
20_0402_5% 1 2 1 2 PH3
10KB_0603_5%_ERTJ1VR103J
2

PR172 1K_0402_1% PR173 4.42K_0402_1%

1

VCC_PRM
PC140
0.1U_0402_16V7K
1 2

2 1
2

PC141 0.22U_0402_6.3V6K
PC142
A 0.22U_0603_10V7K A
1

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A4221
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401552
Date Friday May 16 2008 Sheet 46 of 50
5 3 2 1
 5 4 3 2 1

Version change list (P.I.R. List) Page 1 of 2

for PWR
Item Fixed Issue Reason for change Rev. PG# Modify List Date Phase

D D

1 Delete PD1. Because we can cost down and DOCK_B+ has another one. 0.1 39 1 Delete PD1 SCSB540C080 (S SCH DIO B540C-13-F SMC) 20071108 EVT

2 3/5V exit on battery mode shutdown. To prevent 3/5V exit on battery mode shutdown. 0.2 41 Add SC100001K00 (S DIO 1SS355 SOD323 T/R-5K 20071221 DVT

3 PD11 has over temp. issue. Because PD11 has over temperature issue in JAQ60,
we change it to a 10A diode.
0.2 39 Change PD11 from SCSB540C080 to SCS00002F00 . 20071221 DVT

4 Add snubber in 3/5V by

EMI request.
Add snubber in 3/5V by EMI request. 0.2 41 Add PR36 and PR39 to SD001470B80 20071221 DVT

5 Down size. Down size. by sourcer request. 0.2 46 Change PC136 from SE025821K80 to SE000003W00 20071221 DVT

6 Down size. Down size. by sourcer request. 0.2 46 Change PC120 and PC129 from SE024681J80 to SE074681K80 20071221 DVT

7 Down size. Down size. by sourcer request. 0.2 43 Change PC72 and PC74 from SE068102J80 to SE074102K80 20071221 DVT

C 8 2nd source trial run TI controller. 2nd source trial run TI controller. 0.2 41 Add PC143 SE080105K80 20071221 DVT C

Add snubber in 3/5V by

9 EMI request. Add snubber in 3/5V by EMI request. 0.2 41 Add PC33 and PC34 SE074681K80 20071221 DVT

10 To meet Jeta SPEC. To meet Jeta SPEC. 0.2 42 Add PC144 SE074102K80 20071221 DVT

12 Add EMI solution. Add 3/5V boost resistor. 0.3 41 Add PR37, PR40 SD013220B80 (S RES 1/10W 2.2 +-5% 0603) 20080102 DVT

13 Add EMI solution. Add charger boost resistor. 0.3 42 Add PR61 SD013220B80 (S RES 1/10W 2.2 +-5% 0603) 20080102 DVT

Add PR64 SD001470B80(S RES 1/4W 4.7 +-5% 1206)

14 Add EMI solution. Add charger snubber. 0.3 42 Add PC55 SE074681K80(S CER CAP 680P 50V K X7R 0402 ) 20080102 DVT

15 Add EMI solution. Add 1.05V/1.8V boost resistor. 0.3 43 Add PR106, PR109 SD013220B80 (S RES 1/10W 2.2 +-5% 0603) 20080102 DVT
B B
Add PR104 SD001470B80(S RES 1/4W 4.7 +-5% 1206)
16 Add EMI solution. Add 1.05V snubber. 0.3 43 Add PC83 SE074681K80(S CER CAP 680P 50V K X7R 0402 ) 20080102 DVT

Add PR108 SD001470B80(S RES 1/4W 4.7 +-5% 1206)

17 Add EMI solution. Add 1.8V snubber. 0.3 43 Add PC89 SE074681K80(S CER CAP 680P 50V K X7R 0402 ) 20080102 DVT

18 Add EMI solution. Add CPU boost resistor. 0.3 46 Add PR138, PR152 SD013220B80 (S RES 1/10W 2.2 +-5% 0603) 20080102 DVT

Add PC159, PC160, PC161, PC162 SE074471K80(S CER CAP

19 Add EMI solution. Add 3/5V input capacitor filter.. 0.3 41 470P 50V K X7R 0402) 20080102 DVT

Add PL12, PL13 SM010016410(S SUPPRE_ KC FBMA-L11-

20 Add EMI solution. Add 3/5V input beat 0.3 41 322513-151LMA50T) 20080102 DVT

21

22
A A

23

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A4221
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, NC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401552
Date Friday, May 16, 2008 Sheet 47 of 50
5 4 3 2 1
 5 4 3 2 1

PHASE PAGE MODIFICATION LIST PURPOSE

-----------------------------------------------------------------------------------------------------------------------------------------------
DVT P.4 Change R25 , R18 , R11 , R19 from 56 to 54.9 ohm Reference standard circuit
P.4 Delete R10 Foe ESD
P.4 Change CPU temp sensor U9 , R55 / R56 from 100 to0 ohm , delete R64 / R652 ADI had issue , for SMSC / Fintek temp sensor , no used for OD output
P.8 Change R525 , R527 connected from +1.05Vs to GND Reference standard circuit
Change Cantiga GM U30 as SA00001P930 (Ver:B0) Revision upgrade
D
Change Cantiga PM U30 as SA00001ZO30 (Ver:B0) D

P.12 Change L42 , L18 , C499 , C229 , C280 , C232 as GM@ Reference standard circuit
Change R596 , R597 as PM@ For UMA CRT
P.12 Add C597 (220U)
Reserved
P.12 Add C597 (220U)
Reference standard circuit
P.12 Change R110 , C187 , C196 as stuff , R117 un-stuff
DFX
P.12 C461 down size as 10U_0603
NA
P.16 Change Q30 (dual N-MOS) as Q48 , Q49 (2 single N-MOS) NA
P.17 C500 down size as 680P_0402 For BOM
P.17 Add L57 , L58 , C598 , C599 for +1V8RUN +1V8RUN ripple (+1V8RUN is for MXM +PEX1V2)

P.17 Add R599 as 0ohm Reserve R598 , D31

P.17 Update JMXM1 footprint NA
P.17 Change Q41 (dual N-MOS) as Q50 , Q51 (2 single N-MOS) NA
P.18 C364 down size as 680P_0402 For BOM
C P.18 C365 , C366 , C367 change from 220P to 820P For EMI C

P.19 D5 change as RB411DT146_SOT23-3 Common part

P.19 Change Q40 (dual N-MOS) as Q52 , Q53 (2 single N-MOS) NA
P.19 Change C401 , C409 , C419 as 15P For DISCRETE CRT
P.19 Change C402 , C410 , C420 as 12P For DISCRETE CRT
P.19 C408 , C418 , C423 (22P) stuff for UMA only For UMA CRT only
P.19 Change L1 , L2 from FCM1608C-121T_0603 as 10ohm_0603 For CRT
P.20 Change Q7 from 2N7002_SOT23(Dual N-MOS) as Q7 & Q47(Single BSH111 N-MOS) For DVI SMBUS level shifter
P.20 Add R600 & R602 (4.7K ohm) pull high +3Vs For DVI SMBUS
P.20 Reserve R601 & R603 (2.7K ohm) pull high +5Vs For DVI SMBUS
P.20 Reserve U39 & U40 (SN74CBTD3306CPWR_TSSOP8) For DVI & HDMI SMBUS
P.20 Change D21 from RB751V_SOD323 as CH751H-40PT_SOD323-2 NA
P.22 Change R478 from 33 ohm as 1K ohm Customer request
P.22 LAN_RST# connect to GND No used Integrated LAN
B
P.22 R169 un-stuff For mobile B

P.22 Add CR_CPPE#(GPIO7) & CR_WAKE#(GPIO22) For JMB385 power management

P.22 Swap PCIE(x1) port 2 & port 4 NA
P.22 R385 un-stuff , U28 stuff For sequence
P.25 U34.127 is used as externel IDSEL NA
P.25 R489 un-stuff For PCMCIA Lan card not support PM_CLKRUN# function
P.25 Update JPCM1 footprint For DFX
P.26 Reserve R655 , R656 , D33 for CR_CPPE# & CR_WAKE# For JMB385 power management
P.26 Cantiga JMB385 U32 as SA00001W910 (Ver:B) Revision upgrade
P.27 Delete BCM5787M co-lay schematic NA
P.27 Update U25 footprint For DFX
P.28 Change T1 from GSL5009 as GSL5009-1(SP050003T10) NA
P.28 Add C375 , C383 (68P) For EMI
P.29 Add R658 Add 80 port function on JMINI2
P.30 D32(SC300000B00) stuff For ESD
A A
P.31 Add R604 NA
P.31 R248 change from 0 ohm as 8.2K ohm Foe Board ID as 1 define

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT AL
SCHEMATIC MB A4221
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401552
Date: Friday, May 16, 2008 Sheet 48 of 50
5 4 3 2 1
 5 4 3 2 1

PHASE PAGE MODIFICATION LIST PURPOSE

-----------------------------------------------------------------------------------------------------------------------------------------------
DVT P.31 C286 change from 3.3U as 4.7U Stable KB926 internal +1.8V regulator , ENE suggestion value
P.32 JP6 pin define reverse NA
P.32 Change SW3 & SW4 type NA
P.32 U15 change from 1MB as 2MB capacity SPI ROM Add Finger print code
P.33 R261 change from 10K as 31.6K Fix ATI MXM sku can't power on for battery mode issue
D P.33 C334 change from 0.1U as 1U Fix nVIDIA MXM sku power on issue D

P.34 Delete Internal(Digital) MIC reserved circuit NA

P.34 Change R574 (0 ohm) as L59 (MBC1608121YZF) For EMI
P.34 Add R660 to connect HDA_GPIO3 with DOCKIN# For docking spdif feature enable
P.34 Change R574 (0 ohm) as L59 (MBC1608121YZF) For EMI
P.35 R559 / R560 change from 47 ohm as 75 ohm For Audio precision FSOV
P.35 R561 / R562 / R566 / R571 change from 75 ohm as 1K ohm For ESD , Realtek suggestion value
P.36 Add C601 , C602 , C603 (330P) on +5VALW For EMI
P.37 R283 change from 100K to 10K NA
P.37 R206 , Q20 stuff For +1.8V discharge
P.38 Add switch to enable/disable EC_DOCKIN#_S0 for HDMI SMBUS NA
P.38 Update JDOCK1 footprint NA
PVT1
P.16 Change C308 / C311 (33P) as 27P For RTC accuracy
P.23 Use 4MB SPI ROM For Kinabalu_High & Kinabalu_Low
C C
P.23 Add test point T32 / T33 / T34 / T35 Reserved for PCIE(X1) port 1
P.25 Change U35 as SA000026P10(OZ2210GN-B1) For B1 version
P.27 Change U23 as SA000025P20(BCM5764MKMLG P20) For B0 version
P.27 Reserved R673 , R674 (0 ohm) For Lan SMBUS
P.27 Reserved Lan GPIO0(LAN_ALERT#) / LAN_ALERT#_EC / R675 , R676 , R677 to EC For Lan ASF workaround
P.27 U23 Pin17 / Pin5 / Pin55 connect to U23 Pin18 for power +Lan_VDDIO_1.2 U23 Pin18 is power source +Lan_VDDIO_1.2 for U23 Pin17 / Pin5 / Pin55
P.27 U23 Pin38 / Pin52 NC NA
P.29 Change JMINI1 for Robson2 , chnage JMINI2 for Wireless NA
P.31 Add LAN_ALERT#_EC & EC_ACIN for EC Reserved for ASF workrund & Nvidia MXM power saving
P.33 Add R668(10K) & reserved R263(10K) Fine tune +1.05VS timing for UMA boot display flash
P.34 Change U36 as ALC268-VB1-GR(SA00001GD10) Version upgrade
P.34 Stuff R659 & un-stuff R660 For SPDIF feature on docking
P.36 Add C604 , C605 (820P_0402) For EMI
P.50 Chipset change as GM(SA00002JT10) / PM(SA00002JJ00) /ICH9M(SA00002JH00) Version upgrade
B B
PVT2 P.27 Update U23 CIS symbol U23 Pin38 , 52 can't be changed as NC
P.34 Add D34 , R678 For ACER docking SPDIF feature (No SPDIF on board)
P.38 Update JDOCK1 CIS symbol Docking connector modify (add boss x 2) for DFX
P.35 Delete D2 , D4 (Int SPK ESD diode) NA
P.34 Delete D9 (Int MIC ESD diode) NA
P.35 Add C609 , C610 (330P_0603) on Right SPK For EMI
P.34 Add C608 (330P_0603) on Int MIC For EMI
P.08 Add Test point (T39 , T40 , T41 , T42) Add Management Engine JTAG pins
P.27 Add C612 , C614 (0.1u_0402) for +LAN_AVDD For lower 1000Base-T Comm-Mode O/P Voltage < 50mV
P.27 Add C615 , C616 , C617 (0.1u_0402) for +LAN_AVDDL For lower 1000Base-T Comm-Mode O/P Voltage < 50mV
P.08 Add U41, R679 , R680 , R681 , R682 , R683 , R684 , R685 , T43 Reserved for Management Engine JTAG debug
P.07 Chipset change as GM(SA00002JT50) / PM(SA00002JJ50) Version upgrade
P.20 , P.31 Add EC_DVI_DET , EC_GPIOB , EC_GPIOC , R687 , R688 , R691 Reserved for DVI detect delay control (by EC)
MP P.24 R73 , R148 change from 10_0402 to 100_0402 For USB issue on ICH9M A3 stepping
C128 , C204 change from 0.1U_0402 to 1U_0402
A A
P.34 , P.35 C608 , C609 , C610 change from 330P_0603 to 330P_0402 For 330P_0402 is standard part
P.31 Change R248 as 33K Board ID upgrade
P.30 Add R692 / R693 (0_0603) Reserved S3 power rail for check finger print sensor S3 resume too slow
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT AL
SCHEMATIC MB A4221
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401552
Date: Friday, May 16, 2008 Sheet 49 of 50
5 4 3 2 1
 5 4 3 2 1

PHASE PAGE MODIFICATION LIST PURPOSE

-----------------------------------------------------------------------------------------------------------------------------------------------
P.20 Add D35 Reserved for HDMI_HPD
P.30 Add R694 / R695 (0_0603) Reserved for check
P.27 Delete C612 , C614 , C615 , C616 , C617 (0.1u_0402) No need
P.16 Stuff R689 / R690 Reserved for LAN power saving
D D
P.35 R559 , R560 change from 75 to 54.9 ohm For FSOV between 420mv~480mv
Chipset change as GM(SA00002JTB0) / PM(SA00002JJA0) /ICH9M(SA00002JH70) Version upgrade
P.32 R291 , R294 change from 300_0402_5% to 150_0402_5% For ACER Hank's request to fine tune brighter
P.20 R84 , R85 , R86 , R91 change from 2K_0402_5% to 4.7K_0402_5% For UMA DVI/HDMI monitor P193WA (x) detect issue (On JAL90)

PCB IC For Discrete

ZZZ LA4221MB Rev0: DA600007R00 U30
C C
LA4221MB Rev1: DA600007R10
CRT
PM@ MCH
LA4221MB with Sub/B Rev1: DAZ04800100 C419 C409 C401 2 1
1 1 1 R128 PM@ 0_0402_5%
PCB 047 LA-4221P REV1 M/B CANTIGA ES_FCBGA1329
DVT CANTIGA PM: SA00001ZO30 (S IC EB88CTPM QR34 B0 FCBGA 1329 ES) PM@ 2 PM@ 2 PM@ 2 2 1
15P_0402_50V8J R129 PM@ 0_0402_5%
PVT CANTIGA PM: SA00002JJ00 (S IC AC88CTPM QT78 B2 FCBGA 1329 PM) 15P_0402_50V8J 15P_0402_50V8J
2 1
PVT2 CANTIGA PM: SA00002JJ50 (S IC AC88CTPM QU38 B3 FCBGA 1329 PM) R119 PM@ 0_0402_5%

Pre-MP CANTIGA PM: SA00002JJA0 (S IC AC82PM45 SLB97 B3 FCBGA1329 PM ABO!) 15P_0402_50V8J: SE071150J80 2 1
R138 PM@ 0_0402_5%
U30 12P_0402_50V8J: SE071120J80
2 1
R139 PM@ 0_0402_5%
UMAGL@
C420 C410 C402 2 1
1 1 1 R140 PM@ 0_0402_5%
CANTIGA ES_FCBGA1329
DC Cable DVT(Check_TBD) CANTIGA GL: SA000023Z00 (S IC CANTIGA ES FCBGA 1329 MCH GL) PM@ 2 PM@ 2 PM@ 2 2 1
12P_0402_50V8J R143 PM@ 0_0402_5%
ZZZ 12P_0402_50V8J 12P_0402_50V8J
0_0402_5%: SD028000080

B DC Cable (65W) U10 B

@ PVT(54 Rank)

ICH9ME@
DVT(Check)
DC301003R00(CONN SET 048 DCJACK-MB 2DW-G756-I50 65W)

ICH9-M ES_FCBGA676
ZZZ
ICH9-M: SA00002G120
(S IC AF82801IEM QT10 A3 PBGA 676P ICH9M)

DC Cable (90W)
@ PVT(54 Rank)

DC301003S00(CONN SET 048 DCJACK-MB 2DW-G756-I49 90W) U6

SPI2MB@

W25X16-VSSIG_SO8

MP Winbond: SA00001KN00
A
(S IC FL 16MBIT W25X16-VSSIG SOIC 8P) A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT AL
SCHEMATIC MB A4221
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401552
Date: Friday, May 16, 2008 Sheet 50 of 50
5 4 3 2 1