Computer Organization Study Material Q & A

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1. ExplaintheRegisterTransferLanguage.
Definition:Thesymbolicnotationusedtodescribethemicrooperationtransfersamongregistersiscal
ledaregistertransferlanguage.
 Theterm"registertransfer"impliestheavailabilityofhardwarelogiccircuitsthatcanperform
astatedmicrooperationandtransfertheresultoftheoperationtothesameoranotherregister
.
 Theword"language"isborrowedfromprogrammers,whoapplythistermtoprogramminglan
guages.
 Aregistertransferlanguageisasystemforexpressinginsymbolicformthemicrooperation
sequences amongtheregistersof adigitalmodule.
 Itisaconvenienttoolfordescribingtheinternalorganizationofdigitalcomputersinconciseand
precisemanner.
 Itcanalsobeusedtofacilitatethedesignprocessofdigitalsystems.
 Informationtransferfromoneregistertoanotherisdesignatedinsymbolicformbymeansofar
eplacementoperator.
 Thestatementbelowdenotesa transferofthe contentofregisterR1intoregisterR2.
R2 ← R1
 Astatementthat
specifiesaregistertransferimpliesthatcircuitsareavailablefromtheoutputsofthedestinatio
n registerhasaparallel load capability.
 Everystatementwrittenin aregister transfernotationimplies a
hardwareconstructionforimplementingthetransfer.
2. ExplaintheRegisterTransferindetailwithblockdiagramandtimi
ngdiagram.
Definition:Informationtransferfromoneregistertoanotherisdesignatedinsymbolicformbymeansof
areplacementoperatorisknownasRegisterTransfer.
R2 ← R1
Denotesatransferofthecontentof registerR1into registerR2.
 Computer registers aredesignatedbycapital letters(sometimesfollowed by
numerals)todenotethefunctionof theregister.
Forexample:
MAR Holdsaddressofmemoryunit
PC ProgramCounter
IR InstructionRegister
R1 ProcessorRegister
 Belowfigure1.1showstherepresentationofregistersin blockdiagramform.
1
Figure1.1: Blockdiagramofregister
 The most commonwaytorepresent aregister isbyarectangularbox

withthenameoftheregister inside,asshown infigure.
 Bits0through7are assignedthesymbol L(forlowbyte)andbits8through15areassignedthe
symbolH(for highbyte).Thenameofthe16-bitregisterisPC.The symbolPC(0-
7)orPC(L)referstothe low-orderbyte andPC(8-15)orPC(H)tothehigh-orderbyte.
 Thestatementthatspecifiesaregistertransferimpliesthatcircuitsareavailablefromtheout
putsofthe
sourceregistertotheinputsofthedestinationregisterandthatthedestinationregisterhasap
arallel load capability.
RegisterTransferwithcontrolfunction:
 Ifwewantthetransferto occuronlyunder apredeterminedcontrol condition.Thiscan
beshownbymeansofanif-thenstatement.
If(P = 1)then(R2 R1)
where Pisacontrolsignal.
 Itissometimesconvenienttoseparatethecontrolvariablesfromtheregistertransferopera
tioncontrolfunction byspecifyinga controlfunction.
 Acontrol functionisaBooleanvariablethat is equalto1or 0.The control
functionisincluded inthestatementasfollows:
P:R2R1
 Thecontrolconditionisterminatedwithacolon.It
symbolizestherequirementthatthetransferoperationbeexecutedbythehardwareonlyi
fP=1.
 Everystatementwritteninaregistertransfernotationimpliesahardwareconstructionforimp
lementingthetransfer.BelowfigureshowstheblockdiagramthatdepictsthetransferfromR1
toR2.
Figure1.2:TransferfromR1to R2when P=1

Figure1.3: Timingdiagram
 Then outputsof registerR1areconnectedtothen inputsof registerR2.The
letternwillbeusedtoindicate anynumberofbitsfortheregister.
 Inthetimingdiagram,Pisactivated inthecontrolsectionbythe risingedge ofa
clockpulseattimet.
 Thenextpositivetransition oftheclockattimet+1findstheloadinput active
andthedatainputsofR2 arethen loadedintotheregister inparallel.
 Pmaygobackto0attimet+1; otherwise,thetransferwilloccur
witheveryclockpulsetransitionwhilePremainsactive.
 Thebasicsymbolsoftheregistertransfernotation arelistedin Tablebelow:
Symbol Description Examples

Letters
Denotesaregister MAR,R2
(andnumerals)
Parentheses() Denotesapartofa register R2(0-7),R2(L)
Arrow Denotestransferofinformation R2R1
Comma, Separatestwomicrooperations R2R1,R1R2
Table1.1:BasicSymbolsforRegisterTransfers
 Registersaredenotedbycapitalletters,andnumeralsmayfollowtheletters.
 Parenthesesareusedtodenoteapartofaregisterbyspecifyingtherangeofbitsorbygivinga
symbol nametoa portion of aregister.
 Thearrowdenotes atransferofinformationandthedirectionoftransfer.
 Acommaisusedtoseparatetwoormoreoperationsthatareexecutedatthesametime.
 Thestatementbelow,denotesanoperationthatexchangesthecontentsoftworegiste
rsduringonecommon clockpulseprovidedthat T=1.
T:R2R1, R1R2
 Thissimultaneousoperationis possiblewithregistersthathaveedge-triggeredflip-flops.
3. Designandexplainacommonbussystemforfourregister.
 Atypicaldigitalcomputerhasmanyregisters,andpathsmustbeprovidedtotransferinformati
onfromoneregistertoanother.
 Thenumberofwireswillbeexcessiveifseparatelinesareusedbetweeneachregisterandallot
herregistersinthesystem.
 Amoreefficientschemefortransferringinformationbetweenregistersinamultiple-
registerconfigurationisa commonbussystem.
 Abusstructureconsistsofasetofcommonlines,oneforeachbitofaregister,throughwhichbin
aryinformationistransferredone at atime.
SwatiSharma,CEDepartment |2140707–ComputerOrganization 3
 Controlsignalsdeterminewhichregisterisselectedbythebusduringeachparticularregistertr
ansfer.
 Onewayofconstructinga commonbussystemiswithmultiplexers.
 Themultiplexersselectthesourceregisterwhosebinaryinformationisthenplacedonthebus.
 The construction of abus systemforfourregistersisshowninfigurebelow.
 Each registerhasfourbits, numbered0 through3.
 Thebusconsistsoffour4x1multiplexerseachhavingfourdatainputs,0through3,andtwo
selection inputs,S1and S0.
 Thediagramshowsthatthebitsinthesamesignificantpositionineachregisterareconnectedt
othedatainputsofone multiplexertoform one lineofthebus.
4-line
commonbus
S1
S0
4x1 4x1 4x 1 4x1
MUX 3 MUX 2 MUX 1 MUX 0
D2C2 B2 A2 D1C1 B1 A1 D0C0 B0 A0
D2D1D0 C2 C1 C0 B2 B1 B0 A2A1A0
3 21 0 3 21 0 3 21 0 3 21 0
RegisterD RegisterC RegisterB RegisterA
Figure1.4:Bussystemforfourregisters
 Thetwo selectionlines S1and S0areconnected to the selection inputsofall

fourmultiplexers.
 Theselection lineschoose thefourbitsofoneregister andtransferthemintothefour-
linecommonbus.
S1 S0 Register
selected
0 0 A
0 1 B
1 0 C
1 1 D
Table1.2:FunctionTableforBus
 WhenS1S0= 00,the0datainputsof all fourmultiplexersare

selectedandappliedtotheoutputsthatform the bus.
 Thiscausesthebuslinesto receive thecontent
ofregisterAsincetheoutputsofthisregisterareconnectedtothe0datainputsofthemultipl
exers.
 Similarly,registerBisselectedif S1S0= 01, and so on.
 Table showstheregisterthat isselected
bythebusforeachofthefourpossiblebinaryvaluesoftheselectionlines.
 Ingeneral, abussystemwill multiplexkregistersof n bitseachtoproduceann-
linecommonbus.
 Thenumberofmultiplexersneededto constructthebusisequalton,thenumberofbitsin
each register.
 The sizeof eachmultiplexer mustbeKx1 sinceitmultiplexesK datalines.
Forexample,acommonbusforeightregistersof16
bitseachrequires16multiplexers,oneforeachlineinthebus.Each multiplexermust have
eightdata input lines andthreeselectionlinestomultiplexonesignificantbit
intheeightregisters.
4. Adigitalcomputerhasacommonbussystemfor16registersof32bi
tseach.(i)Howmanyselectioninputarethereineachmultiplexer?
(ii)Whatsizeofmultiplexersisneeded?
(iii)Howmanymultiplexersarethereinabus?
(i) Howmanyselectioninputarethere ineachmultiplexer?
2n=No.ofRegisters;
n=selectioninputofmultiplexer2n=16;heren=4
Therefore4selectioninputlinesshouldbethereineachmultiplexer.
(ii) What sizeofmultiplexersisneeded?

sizeofmultiplexers=TotalnumberofregisterX1
=16X1
Multiplexerof16 x1 size isneededtodesigntheabovedefined commonbus.
(iii) Howmanymultiplexersarethereinabus?
No.ofmultiplexers=bitsof register
=32
32multiplexersareneededinabus.
5. Explainthree-statebusbuffer.OR
Explaintheoperationofthreestatebusbuffersandshowitsuseind
esignofcommonbus.
 Abussystem canbeconstructedwiththree-stategatesinsteadofmultiplexers.
 Athree-
stategateisadigitalcircuitthatexhibitsthreestates.State1:Signal
equivalentto Logic1
State2:Signalequivalentto Logic0
State3:HighImpedanceState(behavesasopencircuit)
 Thehigh-
impedancestatebehaveslikeanopencircuit,whichmeansthattheoutputisdisconnected
anddoes nothave logicsignificance.
 Themost commonlyused designof abussystemisthe buffergate.
 Thegraphicsymbolofathree-statebuffergateisshown infigure1.5below:
OutputY=AifC=1HighI
NormalInputA
mpedanceifC=0
ControlInputC
Figure1.5:Graphicsymbolsforthree-statebuffer
 Itisdistinguishedfromanormalbufferbyhavingbothanormalinputandacontrolinput.
 Thecontrolinputdeterminestheoutputstate.WhenthecontrolinputCisequalto1,theoutput
isenabledandthegatebehaveslikeanyconventionalbuffer,withtheoutput
equaltothenormal input.
 WhenthecontrolinputCis0,theoutputisdisabledandthegategoestoahigh-
impedancestate,regardlessofthevalue inthenormalinput.
 Thehigh-impedancestateofathree-
stategateprovidesaspecialfeaturenotavailableinothergates.
 Becauseofthisfeature,alargenumberofthree-
stategateoutputscanbeconnectedwithwirestoformacommonbuslinewithoutendangerin
gloadingeffects.
 Theconstructionofabussystemwiththree-statebuffersis demonstratedinfigure1.6below:
Buslineforbit0
A0
B0
C0
D0
S1
0
SelectE
1
S0 2x4 2
nable 3
Decoder
Figure1.6:Buslinewiththreestate-buffers
 Theoutputsoffourbuffersareconnected togetherto form asinglebusline.

 The
controlinputstothebuffersdeterminewhichofthefournormalinputswillcommunicatewith
thebusline.
 Nomorethanonebuffermaybeinthe activestateatanygiventime.
 Theconnectedbuffersmustbecontrolledsothatonlyonethree-
statebufferhasaccesstothebusline while allotherbuffersaremaintained
inahighimpedancestate.
 Oneway toensure that nomorethanonecontrolinputisactiveatany giventimeis
touseadecoder,asshowninthefigure:Buslinewith threestate-buffers.
 When the enable input of the decoder is0,all ofitsfour outputsare0, and the
buslineisinahigh-impedancestatebecauseallfourbuffersaredisabled.
 When the enableinputis active, oneofthe three-state bufferswillbe
active,dependingonthe binaryvaluein theselectinputsofthedecoder.
 Toconstructacommonbusforfourregistersofnbitseachusingthree-
statebuffers,weneedncircuitswithfourbuffersineachasshowninfigure:Buslinewiththreest
ate-buffers,
 Each groupoffourbuffersreceivesone significantbitfromthefourregisters.
 Eachcommonoutputproducesoneofthelinesforthecommonbusforatotalofnlines.
 Onlyonedecoderisnecessarytoselectbetweenthefourregisters.
6. ExplainMemoryTransfer
 ReadOperation:Thetransferofinformationfromamemorywordtotheoutsideenvironmen
tiscalledareadoperation.
 WriteOperation:Thetransferofnewinformationtobestoredintothememoryiscalledawrite
operation.
 AmemorywordwillbesymbolizedbytheletterM.
 ItisnecessarytospecifytheaddressofMwhenwritingmemorytransferoperations.
 Thiswillbedonebyenclosingtheaddressin squarebracketsfollowingtheletterM.
 Consideramemoryunitthatreceivestheaddressfromaregister,calledtheaddressregister,sy
mbolizedbyAR.
 Thedataaretransferredtoanotherregister,calledthedataregister,symbolizedbyDR.Therea
d operation canbe stated asfollows:
Read:DRM[AR]
 This causes atransferofinformationintoDRfromthe memory wordM selected by
theaddressin AR.
 ThewriteoperationtransfersthecontentofadataregistertoamemorywordMselectedbythe
address.AssumethattheinputdataareinregisterR1andtheaddressisinAR.
 Writeoperationcanbestatedsymbolicallyasfollows:
Write:M[AR]R1
 ThiscausesatransferofinformationfromR1intomemorywordMselectedbyaddressAR.
7. ExplainArithmeticMicro-operation.
 Thebasicarithmeticmicro-operationsare:
1. Addition
2. Subtraction
3. Increment
4. Decrement
5. Shift
 Theadditionalarithmeticmicrooperationsare:
1. Addwithcarry
2. Subtractwithborrow
3. Transfer/Load,etc.
 SummaryofTypicalArithmeticMicro-Operations:
R3 R1+R2 ContentsofR1plusR2transferredtoR3

R3 R1-R2 ContentsofR1minusR2transferredtoR3
R2 R2’ ComplementthecontentsofR2

R2  R2’+1 2's
complementthecontentsofR2(negate)
R3R1+R2’+ subtraction
1
R1 R1 +1 Increment
R1 R1 –1 Decrement
8. ExplainBinaryAdderindetail
 Toimplementtheaddmicrooperationwithhardware,weneed:
1. Registers:thatholdthedata
2. Digitalcomponent:thatperformsthearithmeticaddition.
 Full-adder
Thedigitalcircuitthatformsthearithmeticsumoftwobitsandapreviouscarryiscalledafull-
adder.
 Binaryadder
Thedigitalcircuitthatgeneratesthearithmeticsumoftwobinarynumbersofanylengthsiscall
ed abinaryadder.
 Thebinaryadderisconstructedwithfull-
addercircuitsconnectedincascade,withtheoutputcarryfromonefull-
adderconnectedtothe inputcarryofthenextfull-adder.
B3 A3 B2 A2 B1 A1 B0 A0
FA C3 C2 C1 C0
FA
FA
FA
C4 S3 S1 S0
S2
Figure1.7:4-bitbinaryadder
 Abovefigure1.7showstheinterconnectionsoffourfull-adders(FA)toprovidea4-
bitbinaryadder.
 TheaugendsbitsofAandtheaddendbitsofBaredesignatedbysubscriptnumbersfromrightto
left,withsubscript0denotingthelow-orderbit.
 Thecarriesareconnectedinachainthroughthefull-adders.
 The inputcarry tothebinaryadderisC0 andtheoutput carry isC4.
 TheSoutputsofthefull-addersgeneratetherequiredsumbits.
 An n-bitbinaryadder requiresnfull-adders.
 Theoutputcarryfromeachfull-adderisconnectedtotheinputcarryofthenext-high-
orderfull-adder.
 Then databitsfortheAinputscomefrom oneregister (suchasR1),andthe
ndatabitsfortheBinputscomefromanotherregister(suchasR2).Thesumcanbetransferredto
athirdregisterortooneofthesourceregisters(R1orR2),replacingitspreviouscontent.
9. ExplainBinaryAdder-Subtractorindetail.
 The subtractionofbinarynumberscanbe donemostconvenientlyby
meansofcomplements.
 RememberthatthesubtractionA-Bcanbedonebytakingthe2'scomplementofBand adding
it to A.
 The2'scomplementcanbeobtainedbytakingthel'scomplementandaddingonetothe
leastsignificantpairofbits. Thel's complementcan be implemented withinvertersandaone
can be addedtothesumthroughtheinput carry.
 Theadditionandsubtractionoperationscanbecombinedintoonecommoncircuitbyincludin
ganexclusive-ORgatewitheachfull-adder.
 ThemodeinputM controls theoperation.
WhenM=0the circuit isanAdder
WhenM=1thecircuitbecomesa Subtractor
 Each exclusive-ORgatereceivesinputMand oneoftheinputsof
B.WhenM=0,
Wehave C0=0
B⊕ 0=B
Thefull-addersreceivethevalueofB,theinputcarryis0,andthecircuitperformsA
plusB.When
M=1,
Wehave C0=1
B⊕ 1= B` ;B complement
TheBinputsareallcomplementedand1isaddedthroughtheinputcarry.Thecircuit
performstheoperationAplusthe2'scomplementofB.
A + 2’s compliment of B
 A4-bitadder-subtractorcircuitisshownasfollows:
B3 A3 B2 B1 B0 A0
A2 A1
FA C3 FA C2 FA C1 FA C0
C4 S3 S1 S0
S2
Figure1.8:4-bitAdder-Subtractor
 Forunsignednumbers,
IfA>=B,thenA-
BIfA<B,thenB-A
Forsignednumbers,
ResultisA-B, providedthatthere isnooverflow.
10. ExplainBinaryIncrementer
 Theincrementmicrooperationaddsonetoanumber inaregister.
 Forexample,ifa4-bitregisterhasabinaryvalue0110,itwillgoto0111afteritisincremented.
0110
+ 1
--------
0111
 Thediagramofa4-
bitcombinationalcircuitincrementerisshownabove.Oneoftheinputstotheleastsignificanth
alf-adder(HA)isconnectedtologic-
1andtheotherinputisconnectedtotheleastsignificantbitofthe numberto be incremented.
 Theoutputcarryfromonehalf-adderisconnectedtooneoftheinputsofthenext-higher-
orderhalf-adder.
 ThecircuitreceivesthefourbitsfromA0throughA3,addsonetoit,andgeneratestheincrement
edoutput in S0throughS3.
 TheoutputcarryC4 willbe1onlyafterincrementingbinary1111.Thisalsocauses
outputs S0through S3togo to0.
A3 A2 A1 A0 1
xy xy xy
x y
HA HA HA HA
C4 S3 S2 S1 S0
Figure1.9:4-bitbinaryincrementer
11. Drawblockdiagramof4-
bitarithmeticcircuitandexplainitindetail.
 Thearithmeticmicrooperationscanbeimplementedinonecompositearithmeticcircuit.
 Thebasic componentofan arithmeticcircuitisthe parallel adder.
 Bycontrollingthedatainputstotheadder,itispossibletoobtaindifferenttypesofarithmetic
operations.
 Hardwareimplementationconsistsof:
1. 4full-addercircuitsthatconstitutethe4-
bitadderandfourmultiplexersforchoosingdifferentoperations.
2. Therearetwo4-bit inputs A andB
The fourinputsfromAgo directlyto the X inputsofthe binary
adder.EachofthefourinputsfromBisconnectedtothedatainputsofthemultiplexers.T
hemultiplexer’sdatainputsalsoreceivethecomplement of B.
3. Theothertwodatainputsareconnectedtologic-0andlogic-1.Logic-
0isafixedvoltagevalue(0voltsforTTLintegratedcircuits)andthelogic-
1signalcanbegeneratedthrough an inverterwhose inputis0.
4. Thefour multiplexersare controlledbytwo selectioninputs,S1and S0.
5. TheinputcarryCin
goestothecarryinputoftheFAintheleastsignificantposition.Theothercarriesareconn
ectedfromonestagetothenext.
6. 4-bitoutputD0…D3
 Thediagramofa4-bitarithmeticcircuitisshownbelowfigure1.10:
Figure1.10:4-bitarithmeticcircuit
 Theoutputofbinaryadderiscalculatedfrom arithmeticsum.
D=A+Y+Cin
Select In Output Microoperation

S1 S0 p D=A+Y+ Cin
Cin ut
0 0 0 B D =A +B Add
0 0 1 B D =A +B+ 1 AddwithCarry
0 1 0 B’ D=A +B’ SubtractwithBorrow
0 1 1 B’ D=A +B’ +1 Subtract
1 0 0 0 D =A TransferA
1 0 1 0 D =A +1 IncrementA
1 1 0 1 D =A–1 DecrementA
1 1 1 1 D =A TransferA
TABLE1.3:4-4ArithmeticCircuitFunctionTable
 When S1S0= 00
IfCin=0,D=A+B;Add
 When IfCin=1,D=A+B+1;Addwithcarry
S1S0= 01
If Cin=0, D=A+B̅; Subtract with borrow
If Cin=1, D=A+B̅+1;A+2’s compliment of B i.e. A-B

 When S1S0= 10
Input B is neglected and Y=> logic ‘0’
D=A+0+Cin
IfCin=0,D=A;Transfer
AIfCin=1,D=A+1;Increment A
 When S1S0= 11
Input B is neglected and Y=> logic ‘1’
D=A-1+Cin
IfCin=0,D=A-1; 2’s
complimentIfCin=1,D=A;Transfer A
 Notethatthemicro-operationD=Aisgeneratedtwice,sothereareonlysevendistinctmicro-
operationsinthearithmeticcircuit.
12. DrawandexplainLogicMicro-operationsindetail.
 Logicmicrooperationsspecifybinaryoperationsforstringsofbitsstoredin registers.
 Theseoperationsconsidereachbitoftheregisterseparatelyandtreatthemasbinaryvariable
s.Forexample,theexclusive-ORmicro-
operationwiththecontentsoftworegistersR1andR2issymbolizedbythestatement:
P:R1R1⊕R2
1010 ContentofR1
⊕ 1100 ContentofR2
-----------------------------------
0110 ContentofR1after P=1
 Thelogicmicro-operationsareseldomused
inscientificcomputations,buttheyareveryusefulforbitmanipulationofbinarydata and
 for makinglogicaldecisions.
Notation:
The symbol∨will be used to denotean
ORmicrooperationandthesymbol∧todenoteanANDmicrooperation.Thecomplementmic
rooperationisthesameasthe1's
complementanduses abarontopofthesymbolthatdenotesthe registername.
 Althoughthe +symbolhastwomeanings,itwillbepossibleto
distinguishbetweenthembynotingwherethe symboloccurs.Whenthe symbol
+occursinamicrooperation, it willdenote an arithmeticplus.When it
occursinacontrol (orBoolean)function,itwilldenotean ORoperation.
P+ Q:R1R2 + R3,R4R5 V R6
 The+ betweenPandQis an ORoperation betweentwo binaryvariablesof
acontrolfunction.The+betweenR2andR3
specifiesanaddmicrooperation.TheORmicrooperationisdesignatedbythesymbolVbet
weenregistersR5andR6.
ListofLogicMicrooperations
 Thereare16differentlogicoperationsthatcanbeperformedwithtwobinaryvariabl
es.
 Theycanbedeterminedfromallpossibletruthtables
obtainedwithtwobinaryvariablesasshownintablebelow.
x Y F F F F F F F F F F F F F F F F
0 1 2 3 4 5 6 7 8 9 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
TABLE1.4:TruthTablesfor16FunctionsofTwoVariables
Boole Microoperation Name

anfun
F0= 0
ction F0 Clear
F1= xy FA∧ B AND
F2= xy'
FA∧B̅
F3=x FA TransferA
F4= x'y
FA̅∧B
F5= y FB TransferB
F6= x⊕y FA⊕B Exclusive-OR
F7= x+y FA∨B OR
F8= (x+y)' F̅A̅V̅B̅ NOR
f9=(X⊕Y)' ̅ ̅ Exclusive-NOR
FA̅⊕̅B̅
F10= y' FB̅ ComplementB
F1 1=x + y'
FA VB̅
F12= x' FA̅ ComplementA
F13= x' +y
FA̅V B
F14= (xy)' ̅ NAND
FA̅∧̅B̅
F15= 1 Fall1's Setto all l's
TABLE1.5:SixteenLogicMicrooperation
HardwareImplementation
 Thehardwareimplementationoflogicmicrooperationrequiresthatlogicgatesbeinsert
edforeachbit orpairofbitsin theregisterstoperformtherequiredlogicfunction.
 Althoughthereare16logicmicrooperation, mostcomputersuseonlyfour—
AND,OR,XOR(exclusive-OR),andcomplementfromwhichallotherscanbederived.
 Belowfigureshowsonestageof
acircuitthatgeneratesthefourbasiclogicmicrooperations.
Figure1.11:Onestageoflogiccircuit
S1 S0 Output Operation
0 0 E=A∧B AND
0 1 E = AV B OR
1 0 E = A ⊕B XOR
1 1 Compliment
E =𝐴̅
Table1.6:Functiontable
 Hardwareimplementation consistsoffourgatesandamultiplexer.
 Each
ofthefourlogicoperationsisgeneratedthroughagatethatperformstherequiredlogi
c.
 Theoutputsofthe gatesare appliedtothedatainputsofthemultiplexer.
 Thetwo selection inputsS1and S0chooseoneofthedata inputsof the
multiplexeranddirectitsvalueto theoutput.
 Thediagramshowsonetypical stagewith subscripti.For alogiccircuit
withnbits,thediagrammustberepeatedn timesfor i=0,1, 2,... n- 1.Theselectionvariables
are
appliedto allstages.
13. Explainselectiveset,selectivecomplementandselectiveclear.
Selective-Setoperation:
 Theselective-
setoperationsetsto1thebitsinregisterAwheretherearecorresponding1'sinregisterB.Itdoes
notaffectbitpositionsthathave0'sinB.Thefollowingnumericalexampleclarifiesthisoperatio
n:
1010 Abefore
1100 B(logical
operand)1110 Aafter
 Thetwo leftmostbitsofBare1's,so thecorrespondingbitsof Aaresetto1.
 Oneofthesetwobitswasalreadysetandtheother hasbeen changedfrom 0to1.
 ThetwobitsofAwithcorresponding0'sinBremainunchanged.Theexampleaboveservesasat
ruthtablesinceithasallfourpossiblecombinationsoftwobinaryvariables.
 TheORmicrooperation canbeusedtoselectivelyset bitsofaregister.
Selective-Complementoperation:
 The selective-complementoperationcomplementsbits in A
wheretherearecorresponding1's in B.Itdoesnotaffectbitpositionsthat have
O'sinB.Forexample:
1010 Abefore
1100 B(logical
operand)0110 Aafter
 Again thetwoleftmostbits ofB are 1's, sothe correspondingbitsofA arecomplemented.

 Theexclusive-ORmicrooperationcanbeusedtoselectivelycomplementbitsofaregister.
Selective-Clearoperation:
 The selective-clearoperationclearsto 0 thebits in A only
wheretherearecorresponding1'sinB.Forexample:
1010 Abefore
1100 B(logical
operand)0010 Aafter
 Againthetwo leftmostbitsofBare1's, so thecorrespondingbitsofAareclearedto0.

OnecandeducethattheBooleanoperationperformedontheindividualbitsisAB'.
 The correspondinglogicmicrooperationisA←A∧B’.
14. Explainshiftmicrooperationsanddraw4-
bitcombinationalcircuitshifter.
Thereare3typesofshiftmicro-operations:
1. Logical Shift:
 Alogicalshift isonethattransfers0throughthe serialinput.Wewill adoptthesymbols
shland shrfor logical shift-left and shift-rightmicro-operations.
 Forexample:
R1←shlR1R2
←shrR2
aretwomicro-operationsthatspecifya1-bitshifttotheleftofthecontentofregisterR1anda1-
bit shifttothe right ofthecontentofregisterR2.
 Theregistersymbolmustbethesameonboth sidesofthearrow.
 Thebittransferredtotheendpositionthroughtheserialinputisassumedtobe0during a
logicalshift.
2. CircularShift:
 Thecircularshift(alsoknownasarotateoperation)circulatesthebitsoftheregisteraroundthet
woendswithoutlossofinformation.
 Thisisaccomplishedbyconnectingtheserialoutputoftheshiftregistertoitsserialinput.Wewil
lusethesymbolscilandcirforthecircularshiftleftandright,respectively.
R1←Cil
R1R2←Cir R2
3. ArithmeticShift:
 Anarithmeticshiftisamicro-
operationthatshiftsasignedbinarynumbertotheleftorright.
 An arithmeticshift-leftmultipliesasignedbinarynumberby2.
 An arithmeticshift-rightdividesthenumberby2.
 Arithmeticshiftsmustleave the signbit
unchangedbecausethesignofthenumberremainsthe same
whenitismultipliedordividedby2.
 Theleftmostbitinaregisterholdsthesignbit,andtheremainingbitsholdthenumber.The
signbitis0forpositive and1fornegative.
 Negativenumbersarein2'scomplementform.
 Figureshowsatypicalregisterofnbits.BitRn-1intheleftmostpositionholdsthesign bit.
 Rn-2isthe mostsignificantbitofthenumberandR0istheleastsignificantbit.
 Thearithmeticshift-
rightleavesthesignbitunchangedandshiftsthenumber(includingthe sign bit)tothe
right.
 ThusRn-1remainsthesame;Rn-2receivesthebitfromRn-
1,andsoonfortheotherbitsintheregister.
 ThebitinR0is lost.
 Thearithmeticshift-left insertsa0intoR0,and shiftsall otherbitstothe left.
 Theinitialbitof Rn-1islost and replaced bythebit from Rn-2.
 Asignreversaloccursif thebitinRn-1 changesin
valueaftertheshift.Thishappensifthemultiplicationby2causesanoverflow.
4-bitcombinationalcircuitshifter
 AcombinationalcircuitshiftercanbeconstructedwithmultiplexersasshowninFigurebelow.
Figure1.12:4-bitcombinationalcircuitshifter
 The4-bit shifterhasfourdata inputs,A0 through A3 and fourdata outputs,H0 throughH3.
 Therearetwo serial inputs, onefor shift left(IL)andthe otherfor shift right (IL).
 Whenthe selection input S=0,the inputdata are shifted right(down inthediagram).
 WhenS=1,the inputdata areshifted left (up inthediagram).
 ThefunctiontableinFigure showswhichinput goesto eachoutputaftertheshift.
 Ashifterwithndatainputsandoutputsrequiresn multiplexers.
 Thetwoserialinputscanbecontrolledbyanothermultiplexertoprovidethethreepossibletyp
es of shifts.
15. Drawandexplainonestageofarithmeticlogicshiftunit.
 Insteadofhavingindividualregistersperformingthemicrooperationsdirectly,computersyst
emsemployanumberofstorageregistersconnectedtoacommonoperationalunitcalledanari
thmeticlogicunit,abbreviatedALU.
 Toperformamicrooperation,thecontentsofspecifiedregistersareplacedintheinputsofthec
ommonALU.
 TheALUperformsanoperationandtheresultoftheoperationisthentransferredtoadestinati
onregister.
 TheALUisacombinationalcircuitsothattheentireregistertransferoperationfromthesourcer
egistersthroughtheALUandintothedestinationregistercanbeperformedduringonedockpu
lseperiod.
 The arithmetic,logic,and shiftcircuitsintroduced in
previoussectionscanbecombinedintooneALUwithcommon selectionvariables.
 One stage ofan arithmeticlogic shiftunit is showninfigurebelow:
Figure1.13:Onestageofarithmeticlogicshiftunit
 The subscript idesignatesa typical stage.InputsAiandBiare
appliedtoboththearithmeticandlogicunits.
 Aparticularmicrooperation isselected with inputs S1and S0.
 A4x1 multiplexer attheoutput choosesbetween anarithmeticoutput inDiand alogic
 outputinEi.
 Thedata in themultiplexer areselectedwith inputs S3and S2.
 Theothertwo datainputstothemultiplexerreceiveinputsAi-1for theshift-
rightoperationandAi+1forthe shift-leftoperation.
 Notethatthediagramshowsjustonetypicalstage.Thecircuitshowninfigure
mustberepeatedntimesfor ann-bitALU.
 Theoutputscarry Ci+1ofa given arithmeticstagemustbeconnectedtotheinput

carryCinofthenextstageinsequence.
 Theinputcarrytothefirst stageistheinput carryOn, whichprovides aselection
variablefor
 thearithmeticoperations.
 Thecircuit whose onestageisspecifiedinfigureprovides
 8arithmeticoperation
 4logicoperations
 2shiftoperations
 Each operationis selected withthefive variablesS3, S2,Si, S0, and Cin. The input
carryCinisusedfor selectingan arithmeticoperation only.
 Tablebelowliststhe14operationsof theALU.
OperationSelect
Operation Function
S S S S C
3 2 1 0 in
0 0 0 0 0 F=A TransferA
0 0 0 0 1 F = A+ 1 IncrementA
0 0 0 1 0 F = A+ B Addition
0 0 0 1 1 F = A+B+1 Addwithcarry
0 0 1 0 0 Subtractwithborro
F = A+B̅
w
0 0 1 0 1 Subtraction
F = A+B̅+1
0 0 1 1 0 F = A-1 DecrementA
0 0 1 1 1 F=A TransferA
0 1 0 0 X F= A∧B AND
0 1 0 1 X F= A∨B OR
0 1 1 0 X F = A⊕B XOR
0 1 1 1 X ComplementA
F =A̅
1 0 X X X F = shrA Shift right A intoF
1 1 X X X F = shlA Shift left A intoF
Table1.7:FunctionTableforArithmeticLogicShiftUnit
 Thefirsteightare arithmeticoperationsandareselectedwithS3S2=00.
 Thenextfour are logicoperationsare selected withS3S2=01.The input
carryhasnoeffectduringthelogicoperationsandismarkedwithdon't-careX's.
 Thelasttwooperationsareshiftoperationsandare selectedwithS3S2=10 and11.
 Theotherthreeselection inputshaveno effecton the shift.
Unit1–ComputerDataRepresentation
1. Explainbasiccomputerdatatypesindetail.
 Thedatatypesfoundintheregistersofdigitalcomputersmaybeclassifiedasbeingoneofthefol
lowingcategories:
(1) numbersusedinarithmeticcomputations
(2) lettersofthealphabet used indataprocessing
(3) Otherdiscretesymbolsusedforspecific purposes.
 Alltypesofdata,exceptbinarynumbers,arerepresentedincomputerregistersinbinary-
codedform.
 Thisisbecauseregistersaremadeupofflip-flopsandflip-flopsaretwo-
statedevicesthatcanstore only1'sand 0's.
NumberSystem:
Radix
 UsesRdistinctsymbolsforeachdigit.Exa
mpleAR =an-1an-2...a1a0 .a-1…a-m.
 Radixpoint(.)separatestheintegerportionandthefractionalportion.
 Example:
R=10 Decimalnumbersystem, R= 2 Binary
R= 8 Octal, R=16 Hexadecimal
1. Decimal
 Thedecimalnumbersystemineverydayuseemploystheradix10system.
 The10 symbols are 0,1,2,3,4,5,6,7,8, and9.
Example
Thestringofdigits724.5isinterpretedtorepresentthequantity
7x 102 +2x 101+4x 10° +5x 10-1
that is,7 hundreds,plus2 tens,plus4units,plus5 tenths.
 Everydecimal numbercan be similarlyinterpretedto findthe
quantityitrepresents.
2. Binary
 Thebinarynumbersystem usestheradix2.
 The twodigitsymbolsusedare 0 and1. The string ofdigits
101101isinterpretedtorepresentthequantity
1x25+0x 24+1x23+1x 22+0x21+1x 2° = 45
 Todistinguishbetweendifferentradixnumbers,thedigitswillbeenclosedinparenthe
sesandthe radixofthenumberinsertedasasubscript.
Forexample,
toshowtheequalitybetweendecimalandbinaryforty-
fivewewillwrite(101101)2=(45)10.
3. Octal
 Octalnumbersystemuses the(radix8).
 Theeight symbolsoftheoctal systemare0,1,2,3,4,5,6,
and7.Forexample,octal736.4isconvertedtodecimalasfollows:
(736.4)8 =7x82+3x 81+6x 8° +4x 8-1
=7x 64 +3x8+6x1+ 4/8 = (478.5)10
4. Hexadecimal
 Hexadecimalnumbersystemusesthe(radix16).
 The16symbolsofthehexadecimalsystemare0,1,2,3,4,5,6,7,8,9,A,B,C,D, E,andF.
 Hexadecimaldigits,thesymbolsA,B,C,D,E,andFcorrespondtothedecimalnumbers1
0,11,12,13,14, and15,respectively.
 The equivalentdecimalnumberofhexadecimalF3is
obtainedfromthefollowingcalculation:
(F3)16=Fx 16 +3= 15 x 16 +3= (243)10
2. Explain Complement number system in detail

withappropriateexample.
 Complementsareusedindigitalcomputersforsimplifyingthesubtractionoperationandforl
ogical manipulation.
 Therearetwotypesofcomplementsforeachbasersystem:ther'scomplementandthe(r-
1)'scomplement.
 Whenthevalueofthebaserissubstitutedinthename,thetwotypesarereferredtoas the
2'sand1'scomplement forbinarynumbersand the 10's and 9's
complementfordecimalnumbers.
(r—1)'sComplement
 9'scomplement
 GivenanumberNinbaserhavingndigits,the(r-1)'scomplementofNisdefinedas(rn-1)-
N.Fordecimalnumbersr=10andr-1=9,sothe9'scomplementofNis(10" - 1)- N.
 Now,10nrepresentsanumberthatconsistsof asingle 1followedbyn0's.
 10n-1isanumberrepresentedbyn9's.
Forexample,withn=4we have104=10000 and104-1=9999.
 It followsthatthe 9's complementofa decimalnumberis
obtainedbysubtractingeachdigitfrom 9.
 Forexample,the9'scomplementof546700is999999-
546700=453299andthe9'scomplementof12389is99999-12389=87610.
 1'scomplement
 For binarynumbers,r=2 andr-1=1, sothe 1'scomplementof Nis(2"-1)-N.
 Again,2nisrepresentedbyabinarynumberthatconsistsofa1followedbyn
0's.
 2n-1isa binarynumberrepresentedbyn1's.
Forexample,with n=4,wehave 24=(10000)2and24-1= (1111)2.
 Thusthe1'scomplementofabinarynumberisobtainedbysubtractingeachdigitfrom
1.
 However,thesubtractionofabinarydigitfrom1causesthebittochangefrom0to1or
from1to0.
 Therefore,the1'scomplementofabinarynumberisformedbychanging1'sinto0'san
d0's into1's.
Forexample, the1's complementof1011001is 0100110 and
the1'scomplementof0001111is1110000.
(r's)Complement
 Ther'scomplementofann-digitnumberNinbaserisdefinedasr"-NforN≠0and0forN =0.
 Comparingwiththe(r-
1)'scomplement,wenotethatther'scomplementisobtainedbyadding1tothe (r-
1)'scomplement since r"-N=[(r"-1)-N]+1.
 10'scomplement
 Thusthe10'scomplementofthedecimal
2389is7610+1=7611andisobtainedbyadding1tothe 9'scomplementvalue.
 2'scomplement
 The2'scomplementofbinary101100is010011+1=010100andisobtainedbyadding1
tothe1'scomplementvalue.
 2's
complementnotationsolvestheproblemoftherelationshipbetweenpositiveandneg
ativenumbers,andachievesaccurateresultsinsubtractions.
3. Explain Subtraction of Unsigned Numbers in

Complementnumbersystemwithappropriateexample.
 The subtractionoftwo n-digitunsignednumbersM-N(N4-0) inbasercanbe done asfollows:
Add theminuendM to ther's complementofthesubtrahendN.ThisperformsM+
rn–N=M—N+r".
1. IfM≥N,thesumwillproduceanendcarryr"whichisdiscarded,andwhatis leftisthe
resultM -N.
2. IfM<N,thesumdoesnotproduceanendcarryandisequaltor"-(N-
M),whichisther'scomplementof(N-
M).Toobtaintheanswerinafamiliarform,takether'scomplementofthesumandplace
anegativesigninfront.
 Forexample,thesubtraction72532-13250=59282.The10'scomplementof13250is86750.
M = 72532
10'scomplementof N = +
Sum = 159282
Discardendcarry105 = -
Answer = 59282
 Nowconsider an examplewithM<N.Thesubtraction13250–
72532producesnegative59282.Usingtheprocedurewithcomplements,wehave
M = 132
10'scomplementof N = + 50 2746
Sum = 159282 8
Thereisnoendcarry.Answerisnegative59282=10'scomplementof40718.
 Subtractionwithcomplementsisdonewithbinarynumbersin
asimilarmannerusingthesameprocedureoutlinedabove.
 UsingthetwobinarynumbersX=1010100andY=1000011,weperformthesubtrac
tion X–Yand Y-X using2's complement's:
X = 1010100
2'scomplementof Y + 0111101
=
Sum = 10010001
Discardendcarry 27 - 10000000
=
Answer: X –Y= 0010001
Y = 1000011
2'scomplementof X +
= 0101100
Sum =
1101111
Thereisno endcarry.
Answerisnegative0010001=2'scomplementof1101111
4. ExplainFixedPointRepresentationindetail.
 Thismethodassumesthatbinarypoint isfixed inoneposition.
 BinaryFixed-PointRepresentationisshownbelow:
X =xnxn-1xn-2...x1x0. x-1x-2... x-m
SignBit(xn): 0forpositive -
1fornegativeRemainingBits(xn-1xn-2...x1x0.x-1x-
2...x-m)
 Positiveintegers,includingzero,canberepresentedasunsignednumbers.
 However,torepresentnegativeintegers,weneedanotationfornegativevalues.
 Inordinaryarithmetic,anegativenumberisindicatedbyaminussignandapositivenumberbya
plussign.
 Becauseofhardwarelimitations,computersmustrepresenteverythingwith1'sand0's,inclu
dingthe signofanumber.
 Asa consequence, it iscustomarytorepresentthesign withabitplacedin the
leftmostpositionofthenumber.
 Theconvention istomake thesign bitequalto0for positiveandto 1fornegative.
 In additiontothesign,anumber mayhaveabinary (or decimal)point.
 Thepositionofthebinarypointisneededtorepresentfractions,integers,ormixedinteger-
fractionnumbers.
 Therepresentationofthebinarypointinaregisteriscomplicatedbythefactthatitischaracteri
zedbyaposition inthe register.
 Therearetwowaysof specifyingthepositionofthebinarypointinaregister:
1. Bygivingitafixedposition
2. Byemployingafloating-pointrepresentation.
 Thefixed-pointmethodassumesthat thebinarypointisalwaysfixedinoneposition.
 Thetwo positions mostwidelyusedare
(1) Abinarypointintheextremeleftoftheregistertomakethestorednumberafraction,and
(2) Abinarypointintheextremerightoftheregistertomakethestorednumberaninteger.
 Ineithercase,thebinarypoint
isnotactuallypresent,butitspresenceisassumedfromthefactthatthenumberstored
intheregister istreatedasafraction orasan integer.
IntegerRepresentationofSignedNumbers
 Whenan integerbinarynumber ispositive,thesignisrepresentedby0
andthemagnitudebyapositivebinarynumber.
 Whenthenumberisnegative,thesignisrepresentedby1buttherestofthenumbermayberep
resentedinoneofthreepossibleways:
1. Signed-magnituderepresentation
2. Signed1'scomplementrepresentation
3. Signed2'scomplementrepresentation
 Thesigned-
magnituderepresentationofanegativenumberconsistsofthemagnitudeandanegativesign.
 Intheothertworepresentations,thenegativenumberisrepresentedineitherthe1'sor2'sco
mplementof itspositivevalue.
 Asanexample,considerthesignednumber14 storedin an8-bitregister.
1 Insigned-magnituderepresentation 1 00011
. Insigned-1'scomplementrepresentation
2 10
1 11100
.3 Insigned-2'scomplementrepresentation 1 0111100
 . 10
Thesigned-magnituderepresentationof-14isobtainedfrom+14bycomplementingonlythe
signbit.
 Thesigned-1's complementrepresentationof-14 is obtained by complementing all
thebitsof+14,includingthesignbit.
 Thesigned-
2'scomplementrepresentationisobtainedbytakingthe2'scomplementofthepositivenumb
er,includingitssignbit.
ArithmeticAddition
1. Comparetheirsigns
2. Iftwosignsarethe same, ADDthetwomagnitudes- Lookoutforanoverflow
3. Ifnotthesame,comparethe relativemagnitudesofthe
numbersandthenSUBTRACTthesmallerfrom thelarger-->needa subtractortoadd
4. Determinethesignoftheresult
+6 000001 -6 1111101
1
0 0
+13 000011 +1 0000110
0
1 3 1
+19 000100 +7 0000011
1
+6 000001 -6 1111101
1
0 0
-13 111100 - 1111001
1 13 1
-7 111110 - 1110110
1
 Ineachofthefourcases,theoperationperformedisalwaysaddition,includingthesign
bits.
 Anycarryoutofthe signbitpositionis discarded,andnegative
resultsareautomaticallyin2'scomplementform.
ArithmeticSubtraction
 ArithmeticSubtractionin2’scomplement.
 Takethe2'scomplementofthesubtrahend(includingthesignbit)andaddittotheminuend(in
cludingthesign bit).
 A carry outofthe signbit position is discarded.
 Thisprocedurestemsfromthefactthatasubtractionoperationcanbechangedtoanaddition
operationifthesign ofthe subtrahend ischanged.
 Thisisdemonstratedbythefollowingrelationship:
(±A) -(+B) =(±A) +(-B)
(±A) -(-B)=(±A) +(+B)
 Butchanginga positivenumberto anegativenumberiseasilydone
bytakingits2'scomplement.
 Thereverseisalsotruebecausethecomplementof
anegativenumberincomplementformproducestheequivalentpositivenumber.
 Considerthe subtractionof (- 6)- (-13) =+7.
 Inbinarywitheightbitsthisiswritten as11111010-11110011.
 Thesubtractionischangedtoadditionbytakingthe2'scomplementofthesubtrahend(- 13)to
give (+13).
 Inbinarythisis11111010+00001101=100000111.
 Removingtheendcarry,weobtainthecorrectanswer00000111(+7).
Overflow
 Whentwonumbersofndigitseach are addedand the
sumoccupiesn+1digits,wesaythatanoverflowoccurred.
 An overflow isaproblemindigitalcomputersbecausethewidthofregistersisfinite.
 Aresultthatcontainsn+1bitscannotbeaccommodatedina register with a standardlength
ofnbits.
 Forthisreason,manycomputersdetecttheoccurrenceofanoverflow,andwhen
itoccurs,acorrespondingflip-flopis set which canthenbecheckedbytheuser.
 An overflowcannotoccur after anaddition if onenumber ispositive andtheother
isnegative,sinceaddingapositivenumber
toanegativenumberproducesaresultthatissmallerthanthe largerofthetwo
originalnumbers.
 An overflowmayoccur ifthetwonumbersaddedareeitherpositiveorbothnegative.
 Considerthefollowingexample.
 Twosignedbinarynumbers,+70and+80,arestored intwo8-bitregisters.
 Therangeofnumbersthat eachregister
canaccommodateisfrombinary+127tobinary-128.
 Sincethesumofthetwonumbersis+150, itexceedsthecapacityofthe8-bitregister.
 Thisistrue ifthenumbersareeitherpositiveor bothnegative.
 Thetwo additionsinbinaryareshownbelowtogether withthelasttwocarries.
carries: 0 1 carries: 1 0
+70 0 1000110 -70 1 0111010
+80 0 1010000 -80 1 0110000
+150 1 0010110 -150 1 0110000
 Notethatthe8-bitresultthat shouldhave beenpositivehasanegativesign bit andthe8-

bitresultthatshouldhavebeennegativehasapositivesignbit.
 If,however,the carryoutofthesignbitposition istakenasthe signbitoftheresult,the9-
bitanswerso obtainedwillbecorrect.
 Sincetheanswercannotbeaccommodated within 8bits,wesaythatan
overflowoccurred.
 An overflowconditioncan
bedetectedbyobservingthecarryintothesignbitpositionandthe carryoutof thesign
bitposition.
 Ifthesetwocarriesarenot equal,anoverflowconditionisproduced.
 This is indicated in the examples where thetwocarries’ are explicitlyshown.
 If thetwo carries’areappliedtoanexclusive-ORgate, an overflow
willbedetectedwhentheoutputofthe gate isequalto1.
5. ExplainFloating-PointRepresentationindetail.
 Thefloating-pointrepresentationofanumberhastwoparts.
 Thefirstpartrepresentsasigned,fixed-pointnumbercalledthemantissa.
 Thesecondpartdesignatesthepositionofthedecimal(orbinary)pointandiscalledtheexpon
ent.
 Thefixed-pointmantissamaybeafractionor an integer.
Forexample,thedecimalnumber+6132.789isrepresentedinfloating-
pointwithafractionandanexponentasfollows:
Fraction Exponent
+0.6132789 +04
 Floating-pointisalwaysinterpretedtorepresentanumberinthefollowingform:
mx re
 Onlythemantissamandtheexponentearephysicallyrepresentedintheregister(includingth
eir signs).
 Theradixrandtheradix-pointpositionofthemantissaare alwaysassumed.
 Afloating-
pointbinarynumberisrepresentedinasimilarmannerexceptthatitusesbase2fortheexpone
nt.
 Forexample,thebinarynumber+1001.11isrepresentedwithan8-bitfractionand6-
bitexponent asfollows:
Fraction
Exponent01001110
000100
 Thefractionhasa0intheleftmostpositiontodenotepositive.
 Thebinarypoint ofthefractionfollows the signbit butisnot shownintheregister.
 Theexponenthastheequivalentbinarynumber+4(i.e.0001002=410).
 Thefloating-pointnumberisequivalentto:
mx 2e = +(.1001110)2x 2+4
Normalization
 Afloating-
pointnumberissaidtobenormalizedifthemostsignificantdigitofthemantissaisnonzero.
Forexample,thedecimalnumber350isnormalizedbut00035arenot.
 Regardlessofwherethepositionoftheradixpointisassumedtobeinthemantissa,thenumberi
snormalized only ifitsleftmost digitis nonzero.
For example,the 8-bitbinary number00011010isnotnormalizedbecause of
thethreeleading0's.
 Thenumbercanbenormalizedbyshiftingitthreepositionstotheleftanddiscardingtheleading
0'stoobtain11010000.
 Thethree shiftsmultiplythenumberby23=8.
 Tokeepthesamevalueforthefloating-
pointnumber,theexponentmustbesubtractedbynormalizednumbersprovidethemaximu
mpossibleprecisionforthefloating-pointnumber.
 Azerocannot benormalizedbecause it doesnothaveanonzerodigit.
 Itisusuallyrepresented in floating-pointbyall0'sinthemantissaandexponent.
 Arithmeticoperationswithfloating-
pointnumbersaremorecomplicatedthanarithmeticoperationswithfixed-
pointnumbersandtheirexecutiontakeslongerandrequiresmorecomplexhardware.
 However,floating-
pointrepresentationisamustforscientificcomputationsbecauseofthescalingproblemsinvol
vedwithfixed-pointcomputations.
 Manycomputersand allelectroniccalculatorshavethebuilt-incapability
ofperformingfloating-pointarithmeticoperations.
Unit2– BasicComputerOrganizationandDesign
1. Definethefollowing:
InstructionCode
An instructioncodeisagroupofbitsthatinstructthecomputertoperforma specificoperation.
OperationCode
Theoperationcodeofaninstructionisagroupofbitsthatdefinesuchoperationsasadd,subtract,multipl
y, shift,and
complement.Thenumberofbitsrequiredfortheoperationcodeofaninstructiondependsonthetotalnu
mberofoperationsavailableinthecomputer.Theoperationcodemustconsist ofatleastnbitsfor
n
agiven2 (or less)distinctoperations.
Accumulator(AC)
Computersthathaveasingle-
processorregisterusuallyassigntoitthenameaccumulator(AC)accumulatorandlabelitAC.Theoperati
onisperformedwiththememoryoperandandthecontentof AC.
2. ExplainStoredProgramOrganizationindetail.
 Thesimplestwaytoorganizeacomputeristohaveoneprocessorregisterandaninstructioncode
formatwithtwoparts.
 Thefirst part specifiestheoperationtobeperformed and thesecondspecifiesanaddress.
 Thememoryaddresstellsthecontrolwheretofind anoperandinmemory.
 Thisoperand isread from memoryandused asthe datato beoperated ontogether
withthedatastored in theprocessor register.
 Thefollowingfigure 2.1 showsthistype oforganization.
Figure2.1:StoredProgramOrganization
 Instructionsarestored inonesectionof memoryanddata inanother.
 Foramemoryunitwith4096words,weneed12bitstospecifyanaddresssince212=4096.
 Ifwestoreeachinstructioncodeinone 16-bitmemory word,wehave
availablefourbitsforoperationcode(abbreviatedopcode)tospecifyoneoutof16possibleoper
ations,and12bitstospecifytheaddressof anoperand.
 Thecontrolreadsa16-bitinstructionfromtheprogramportionofmemory.
 Itusesthe12-bitaddresspartoftheinstructiontoreada16-
bitoperandfromthedataportionofmemory.
 Itthenexecutestheoperationspecifiedbytheoperationcode.
 Computersthathaveasingle-processorregisterusuallyassigntoitthenameaccumulator and
labelitAC.
 Ifanoperationinaninstructioncodedoesnotneedanoperandfrommemory,therestofthebits
intheinstructioncanbe usedforotherpurposes.
 For example,operationssuch as clearAC,complementAC,andincrement AC operate
ondatastoredintheACregister.Theydonotneedanoperandfrommemory.Forthesetypesofop
erations,thesecondpartoftheinstructioncode(bits0through11)isnotneededforspecifyingam
emoryaddressandcanbe usedtospecifyotheroperationsforthecomputer.
3. ExplainDirectandIndirectaddressingofbasiccomputer.
 Thesecondpartofaninstructionformatspecifiestheaddressofanoperand,theinstructionissai
dtohave adirectaddress.
 InIndirectaddress,thebitsinthesecondpartoftheinstructiondesignateanaddressofamemory
word in whichtheaddressoftheoperandisfound.
 Onebitoftheinstructioncodecanbeusedtodistinguishbetweenadirectandanindirectaddress.
 Itconsistsofa3-bitoperationcode,a12-
bitaddress,andanindirectaddressmodebitdesignatedbyI.
 The modebit is0fora direct addressand 1for anindirect address.
 Adirect addressinstruction isshown in Figure2.2.Itisplacedinaddress22 inmemory.
 TheIbit is0, sotheinstructionis recognizedasadirectaddressinstruction.
 The opcode specifiesanADDinstruction,andthe addresspartisthe binary equivalentof457.
 Thecontrolfindstheoperandinmemoryataddress457andaddsittothecontentofAC.
 Theinstructioninaddress35showninFigure2.3hasamodebitI=1,recognizedasanindirectaddr
essinstruction.
 Theaddresspartisthebinaryequivalentof300.
 Thecontrolgoestoaddress300tofindtheaddressoftheoperand.Theaddressoftheoperandint
hiscaseis1350.Theoperandfoundinaddress1350isthenaddedtothecontentof AC.
 Theindirectaddressinstructionneedstworeferencestomemorytofetchanoperand.
1. Thefirstreferenceisneededtoreadtheaddressoftheoperand
2. Secondreferenceisfortheoperanditself.
 The memorywordthatholdstheaddressofthe operandin
anindirectaddressinstructionisusedasapointerto anarrayofdata.
15 14 12 11 0
I Opcode Address
Memory Memory
22 0 AD 457 35 1 AD 300
D D
1350
300
457 Operand
Operand
1350
+ +
AC AC
Figure2.2:DirectAddress Figure2.3:IndirectAddress
DirectAddress IndirectAddress
Whenthesecondpartofaninstructio Whenthesecondpartofaninstructioncodes
ncodespecifiestheaddressofanoper pecifiestheaddressofamemorywordinwhic
and,theinstructionissaidtohaveadir htheaddressoftheoperand,theinstructioni
ect address. ssaidtohaveadirectaddress.
ForinstancetheinstructionMOVR00 ForinstancetheinstructionMOV@R000H,w
0H.R0,whenconvertedtomachinela henconverted
nguageisthephysicaladdressofregist tomachinelanguage,@R0becomeswhatev
erR0.Theinstructionmoves0toR0. erisstoredinR0,andthatistheaddressusedt
omove0to.Itcanbewhateverisstoredin R0.
3. ExplainRegistersofbasiccomputer.
 Itisnecessarytoprovidearegisterinthecontrolunitforstoringtheinstructioncodeafteritisreadf
rommemory.
 Thecomputerneedsprocessorregistersformanipulatingdataandaregisterforholdingamemo
ryaddress.
 TheserequirementsdictatetheregisterconfigurationshowninFigure2.4.
Figure2.4:BasicComputerRegisterandMemory
 Thedataregister(DR)holdstheoperandreadfrommemory.
 Theaccumulator(AC)registerisageneralpurposeprocessingregister.
 Theinstructionreadfrommemoryisplacedintheinstructionregister(IR).
 Thetemporaryregister (TR)isusedforholdingtemporarydataduringtheprocessing.
 Thememoryaddressregister(AR)has12bits.
 The program counter (PC) also has12bitsand it holdstheaddressof thenext
instructiontobereadfrommemoryafterthecurrentinstructionisexecuted.
 Instructionwordsarereadandexecutedinsequenceunlessabranchinstructionisencountered.
Abranchinstructioncallsforatransfertoanonconsecutiveinstructionintheprogram.
 Tworegistersareusedforinputandoutput.Theinputregister(INPR)receivesan8-
bitcharacterfromaninputdevice.Theoutputregister(OUTR)holdsan8-
bitcharacterforanoutputdevice.
Regist Bits RegisterName Function
erSy
DR 16 Dataregister Holdsmemoryoperand
AR 12 Addressregister Holdsaddressformemory
AC 16 Accumulator Processorregister
IR 16 Instructionregister Holdsinstructioncode
PC 12 Programcounter Holdsaddressofinstruction
TR 16 Temporaryregister Holdstemporarydata
INPR 8 Inputregister Holdsinputcharacter
OUTR 8 Outputregister Holdsoutputcharacter
Table2.1:ListofRegistersforBasicComputer
4. Draw and explainCommonBus

Systemforbasiccomputerregister.
Whatistherequirementofcommon busSystem?
 Thebasiccomputerhaseightregisters,amemoryunit and acontrolunit.
 Pathsmustbeprovidedtotransferinformationfromoneregistertoanotherandbetweenmemo
ryandregister.
 Thenumberofwireswillbeexcessiveifconnectionsarebetweentheoutputsofeachregisterand
theinputsoftheotherregisters.Anefficientschemefortransferringinformation
inasystemwith manyregister istouse acommonbus.
 Theconnectionoftheregistersandmemoryofthebasiccomputertoacommonbussystem
isshown in figure 2.5.
 Theoutputsofsevenregistersandmemoryareconnectedtothecommonbus.Thespecific
output thatis selectedfor thebuslines at anygiventimeis determined
fromthebinaryvalueoftheselectionvariables S2,S1, andS0.
 Thenumberalongeachoutputshowsthedecimalequivalentoftherequiredbinaryselection.
 TheparticularregisterwhoseLD(load)inputisenabledreceivesthedatafromthebusduringthen
extclockpulsetransition.Thememoryreceivesthecontentsofthebuswhen itswrite
inputisactivated.Thememoryplacesits16-bit outputontothebuswhentheread input
isactivatedand S2S1S0=111.
 Fourregisters,DR,AC,IR,andTRhave16bitseach.
 Tworegisters,ARandPC,have12bitseachsincetheyholdamemoryaddress.
 WhenthecontentsofARorPCareappliedtothe16-bitcommonbus,thefourmostsignificantbits
aresetto0’s. WhenAR andPC receiveinformationfrom thebus, only
the12leastsignificantbitsaretransferredintotheregister.
 The inputregisterINPRandtheoutputregisterOUTR have 8bits each
andcommunicatewiththeeightleastsignificantbitsinthebus.INPRisconnectedtoprovideinfor
mationtothebusbutOUTRcanonlyreceiveinformationfromthe bus.
Figure2.5:Basiccomputerregistersconnectedtoacommonbus
 Fiveregistershavethreecontrolinputs:LD(load),INR(increment),andCLR(clear).Tworegisters
haveonlyaLDinput.
 ARmustalwaysbeusedtospecifyamemoryaddress;thereforememoryaddressisconnectedto
AR.
 The16inputsofACcomefromanadderandlogiccircuit.Thiscircuithasthreesetsofinputs.
1. Set of16-bitinputscomefromtheoutputsofAC.
2. Setof16-bitscomefrom thedataregisterDR.
3. Setof8-bit inputscomefromthe inputregisterINPR.
 TheresultofanadditionistransferredtoACandtheendcarry-
outoftheadditionistransferredtoflip-flopE(extendedACbit).
 Theclocktransitionattheendofthecycletransfersthecontentofthebusintothedesignateddes
tination register andtheoutputofthe adderand logiccircuitintoAC.
5. ExplainInstructionFormatwithitstypes.
 Thebasiccomputerhasthreeinstruction codeformats,asshown infigure2.6.
Figure2.6:Basiccomputerinstructionformat
 Each formathas16bits.
 Theoperationcode(opcode)partoftheinstructioncontainsthreebitsandthemeaningofthere
maining13bitsdependsontheoperation codeencountered.
 A memory-referenceinstructionuses12 bitstospecify an addressandonebitto
specifytheaddressingmode I.Iisequal to 0fordirectaddressandto1forindirect address.
 Theregisterreferenceinstructionsarerecognizedbytheoperationcode
111witha0intheleftmostbit(bit15)oftheinstruction.Aregister-
referenceinstructionspecifiesanoperationonoratestoftheACregister.Anoperandfrommem
oryisnotneeded;therefore,theother12bitsareusedtospecifytheoperationortesttobeexecut
ed.
 Aninput-
outputinstructiondoesnotneedareferencetomemoryandisrecognizedbytheoperationcode
111witha1intheleftmostbitoftheinstruction.Theremaining12bitsareusedtospecifythetypeo
finput-outputoperationortestperformed.
6. ExplainthebasicworkingprincipleoftheControlUnitwithtimingdi
agram.
 Theblockdiagram ofthecontrolunit isshowninfigure2.7.
 ComponentsofControlunitare
1. Twodecoders
2. Asequencecounter
3. Controllogicgates
 Aninstructionreadfrommemoryisplacedintheinstructionregister(IR).IncontrolunittheIRisdi
videdintothreeparts:Ibit,theoperationcode(12-14)bit,andbits0through11.
 Theoperation code inbits12through14 aredecodedwitha3X8decoder.
Figure2.7:Controlunitofbasiccomputer
 Bit-15oftheinstruction istransferredtoaflip-flopdesignatedbythesymbol I.
 TheeightoutputsofthedecoderaredesignatedbythesymbolsD0throughD7.Bits0through11a
reappliedtothecontrollogicgates.The4‐bitsequencecountercancountin binaryfrom
0through15.Theoutputsofcounter aredecodedinto16timingsignalsT0 throughT 15.
 ThesequencecounterSCcanbeincrementedorclearedsynchronously.Mostofthetime,thecou
nterisincrementedtoprovidethesequenceoftimingsignalsoutof4X16decoder.Onceinawhile,
thecounterisclearedto0,causingthenexttimingsignaltobeT0.
 Asanexample,considerthecasewhereSCisincrementedtoprovidetimingsignalsT0,T1,T2,T3an
dT4insequence.AttimeT4,SCisclearedto0ifdecoderoutputD3isactive.Thisisexpressedsymbol
icallybythestatement
D3T4:SC←0
TimingDiagram:
 Thetimingdiagramfigure2.8showsthe timerelationshipofthe controlsignals.
 ThesequencecounterSCrespondstothepositivetransitionoftheclock.
 Initially,the CLRinput ofSC isactive.
 ThefirstpositivetransitionoftheclockclearsSCto0,whichinturnactivatesthetimingT0
outofthedecoder.T0 isactiveduringoneclockcycle.Thepositiveclocktransition
labeledT0inthediagramwilltriggeronlythoseregisterswhosecontrolinputsareconnectedtoti
mingsignalT0.
 SCisincrementedwitheverypositiveclocktransition,unlessitsCLRinputisactive.
 Thisproceduresthesequenceoftimingsignals
T0,T1,T2,T3andT4,andsoon.IfSCisnotcleared,the timingsignalswill continuewithT5,T6, upto
T15andbacktoT0.
T0 T1 T2 T3 T4 T0
Clock
T0
T1
T2
T3
T4
D3CL
R SC
Figure2.8:Exampleofcontroltimingsignals
 ThelastthreewaveformsshowshowSCisclearedwhenD3T4=1.OutputD3fromtheoperationd
ecoderbecomesactiveattheendoftimingsignalT2.WhentimingsignalT4becomesactive,theou
tputoftheANDgatethatimplementsthecontrolfunctionD3T4becomesactive.
 ThissignalisappliedtotheCLRinputofSC.Onthenextpositiveclocktransitionthecounterisclear
edto0.ThiscausesthetimingsignalT0tobecomeactiveinsteadofT5thatwouldhavebeenactiveif
SCwereincremented insteadofcleared.
7. Drawandexplaintheflowchartforinstructioncycle.
 Aprogramresidinginthememoryunitofthecomputerconsistsofasequenceofinstructions.Int
hebasiccomputereachinstructioncycleconsistsofthefollowingphases:
1. Fetchaninstructionfrommemory.
2. Decodetheinstruction.
3. Readtheeffectiveaddressfrommemoryiftheinstructionhasanindirectaddress.
4. Executetheinstruction.
 Afterstep4,thecontrolgoesbacktostep1tofetch,decodeandexecutethenexinstruction.
 Thisprocesscontinuesunlessa HALTinstructionisencountered.
Figure2.9:Flowchartforinstructioncycle(initialconfiguration)
 Theflowchartpresentsaninitialconfigurationfortheinstructioncycleandshowshowthecontro
ldeterminestheinstructiontypeafterthedecoding.
 IfD7=1,theinstructionmustberegister-referenceorinput-
outputtype.IfD7=0,theoperationcodemustbeoneoftheothersevenvalues110,specifyingam
emory-
referenceinstruction.Controltheninspectsthevalueofthefirstbitoftheinstruction,which now
availableinflip-flopI.
 IfD7=0andI=1,wehaveamemory-referenceinstructionwith an
indirectaddress.Itisthennecessarytoreadtheeffectiveaddressfrommemory.
 The threeinstructiontypesare subdividedintofourseparatepaths.The selected
operationisactivatedwiththeclocktransitionassociatedwithtimingsignalT3.Thiscanbe
symbolized asfollows:
D’7IT3:ARM[AR]
D’7I’T3:Nothing
D7I’T3:Executearegister-reference
instructionD7IT3: Executeaninput-output
instruction
 Whenamemory-referenceinstruction withI =0isencountered,itis not
necessarytodoanythingsincetheeffectiveaddressisalreadyinAR.
 However,thesequencecounterSCmustbeincrementedwhenD’7IT3=1,sothattheexecutiono
fthememory-referenceinstructioncan becontinuedwithtimingvariableT4.
 Aregister-referenceorinput-
outputinstructioncanbeexecutedwiththeclickassociatedwithtimingsignalT3.Aftertheinstru
ctionisexecuted,SCisclearedto0andcontrolreturnstothefetchphasewithT0=1.SCiseitherincr
ementedorclearedto0witheverypositiveclocktransition.
8. Listandexplainregisterreferenceinstruction.
 Whentheregister-referenceinstructionis decoded,D7bitissetto1.
 Each controlfunctionneedstheBoolean relationD7I'T3
15 12 11 0
0111 RegisterOperation
 Thereare12register-referenceinstructionslistedbelow:
r: SC0 ClearSC
CLA rB 11 : AC0 ClearAC
CLE rB10: E 0 ClearE
CMA rB 9 : ACAC’ ComplementAC
CME rB 8 : E E’ ComplementE
CIR rB7: ACshrAC,AC(15) E, EAC(0) CircularRight
CIL rB6: ACshlAC, AC(0) E,E AC(15) CircularLeft
INC rB5: ACAC+1 IncrementAC
SPA rB4: if (AC(15) =0) then(PC PC+1) Skip ifpositive
SNA rB3: if (AC(15) =1) then(PC PC+1 Skipifnegative
SZA rB2: if (AC=0) then(PCPC+1) Skip ifACis zero
SZE rB1: if (E =0)then(PC PC+1) Skip ifE iszero
HLT rB0: S 0(S isa start-stopflip-flop) Haltcomputer
 These12bitsareavailableinIR(0-11).TheywerealsotransferredtoARduringtimeT2.
 Theseinstructionsareexecutedat timingcycleT3.
 Thefirstsevenregister-
referenceinstructionsperformclear,complement,circularshift,andincrementmicrooperatio
nsontheACorEregisters.
 The nextfourinstructionscausea skipofthenext instructionin sequencewhen
conditionis satisfied.Theskippingof theinstruction isachievedbyincrementing PC.
 Theconditioncontrolstatementsmustberecognizedaspartofthecontrolconditions.TheACisp
ositivewhenthesignbitinAC(15)=0;itisnegativewhenAC(15)=1.ThecontentofACiszero(AC=0)
if alltheflip-flopsofthe registerarezero.
 TheHLTinstructionclearsastart-stopflip-
flopSandstopsthesequencecounterfromcounting.Torestoretheoperationofthecomputer,t
hestart-stopflip-flopmustbesetmanually.
9. Listandexplainmemoryreferenceinstructions.
 Whenthememory-referenceinstructionisdecoded,D7bitissetto0.
15 14 12 11 0
I 000~110 Address
 Thefollowingtablelistssevenmemory-referenceinstructions.
Symb Operati SymbolicDescription
ol onDeco
AND D0 AC ACM[AR]
ADD D 1 AC AC+M[AR],ECout
LDA D2 AC M[AR]
STA D3 M[AR] AC
BUN D4 PC AR
BSA D5 M[AR] PC,PCAR+1
ISZ D6 M[AR] M[AR]+1,ifM[AR]+1=0then PCPC+1
 TheeffectiveaddressoftheinstructionisintheaddressregisterARandwasplacedthere
duringtiming signalT2whenI=0,orduringtimingsignalT3when I=1.
 Theexecutionofthememory-referenceinstructionsstartswithtimingsignalT4.
ANDtoAC
Thisisan instructionthat performsthe AND logicoperationonpairsofbitsinACand
thememorywordspecifiedbytheeffectiveaddress.TheresultoftheoperationistransferredtoA
C.
D0T4: DRM[AR]
D0T5: ACACDR, SC 0
ADDtoAC
Thisinstructionaddsthecontentofthememorywordspecifiedbytheeffectiveaddresstotheval
ueofAC.ThesumistransferredintoACand
theoutputcarryCoutistransferredtotheE(extendedaccumulator)flip-flop.
D1T4: DRM[AR]
D1T5: ACAC+DR,ECout,SC0
LDA:LoadtoAC
ThisinstructiontransfersthememorywordspecifiedbytheeffectiveaddresstoAC.D2T4:
DRM[AR]
D2T5: ACDR,SC 0
STA:StoreAC
ThisinstructionstoresthecontentofACintothememorywordspecifiedbytheeffectiveaddress.
D3T4: M[AR]AC,SC0
BUN:BranchUnconditionally
Thisinstructiontransferstheprogramtoinstructionspecifiedbytheeffectiveaddress.TheBUNi
nstructionallowstheprogrammertospecifyaninstructionoutofsequenceandtheprogrambra
nches(orjumps)unconditionally.
D4T4: PCAR,SC0
BSA:BranchandSaveReturnAddress
This
instructionisusefulforbranchingtoaportionoftheprogramcalledasubroutineorprocedure.W
henexecuted,theBSAinstructionstorestheaddressofthenextinstructioninsequence(whichis
availableinPC) intoamemorylocationspecifiedbytheeffectiveaddress.
M[AR]PC,PCAR+1M[135]
21,PC135+1=136
Figure2.10:ExampleofBSAinstructionexecution
ItisnotpossibletoperformtheoperationoftheBSAinstructioninoneclockcyclewhenweusethe
bussystemofthebasiccomputer.Tousethememoryandthebusproperly,theBSAinstructionm
ustbeexecuted withasequenceoftwomicrooperations:
D5T4:
M[AR]PC,ARAR+1D5T5:
PCAR,SC0
ISZ:IncrementandSkipifZero
Theseinstructionincrementsthewordspecifiedbytheeffectiveaddress,andiftheincremented
valueisequalto0,PCisincrementedby1.Sinceitisnotpossibleto
incrementawordinsidethememory,itisnecessarytoreadtheword
intoDR,incrementDR,andstorethewordbackintomemory.
D6T4:
DRM[AR]D6T5:
DRDR+1
D6T4: M[AR]DR,if(DR =0)then(PCPC+1),SC0
ControlFlowchart
Figure2.11:Flowchartformemory-referenceinstructions
10. Drawandexplaininput-outputconfigurationofbasiccomputer.
 A computercanservenousefulpurposeunlessitcommunicateswiththeexternalenvironment.
 Toexhibitthemostbasicrequirementsforinputandoutputcommunication,wewilluseatermin
alunitwith akeyboardand printer.
Figure2.12:Input-outputconfiguration
 Theterminalsendsandreceivesserialinformationandeachquantityofinformationhaseightbit
sof an alphanumeric code.
 Theserialinformationfrom thekeyboardisshifted intotheinputregisterINPR.
 Theserialinformationfortheprinterisstoredinthe outputregisterOUTR.
 ThesetworegisterscommunicatewithacommunicationinterfaceseriallyandwiththeACinpar
allel.
 ThetransmitterinterfacereceivesserialinformationfromthekeyboardandtransmitsittoINPR.
ThereceiverinterfacereceivesinformationfromOUTRandsendsittotheprinterserially.
 The1-bitinputflagFGIisacontrolflip-
flop.Itissetto1whennewinformationisavailableintheinputdeviceandisclearedto0whenthei
nformationisacceptedbythecomputer.
 Theflagisneededtosynchronizethetimingratedifferencebetweentheinputdeviceandthe
computer.
 Theprocessofinformationtransferisasfollows:
The process ofinputinformation transfer:

 Initially,theinputflagFGIisclearedto0.Whenakeyisstruckinthekeyboard,an8-
bitalphanumericcodeisshifted into INPRandtheinputflag FGI is setto1.
 Aslongastheflagisset,theinformationinINPRcannotbechangedbystrikinganotherkey.Theco
mputercheckstheflagbit;ifitis1,theinformationfromINPRistransferredin parallelinto AC
andFGIis clearedto 0.
 Oncetheflagiscleared,newinformationcanbeshiftedintoINPRbystrikinganotherkey.
The process ofoutputtinginformation:

 TheoutputregisterOUTRworkssimilarlybutthedirectionofinformationflowisreversed.
 Initially,theoutputflagFGOissetto1.Thecomputercheckstheflagbit;ifitis1,theinformationfro
mACistransferredinparalleltoOUTRandFGOisclearedto0.Theoutputdeviceacceptsthecode
dinformation,printsthecorrespondingcharacter,andwhentheoperationiscompleted,itsets
FGOto1.
 ThecomputerdoesnotloadanewcharacterintoOUTRwhenFGOis0becausethisconditionindic
atesthattheoutputdeviceisintheprocessofprintingthecharacter.
11. ExplainInput-Outputinstructions.
 InputandoutputinstructionsareneededfortransferringinformationtoandfromACregister,for
checkingtheflagbits,andforcontrollingtheinterruptfacility.
 Input-
outputinstructionshaveanoperationcode1111andarerecognizedbythecontrolwhenD7 =1
andI=1.
 Theremainingbitsoftheinstructionspecifytheparticularoperation.
 Thecontrolfunctionsandmicrooperationsfortheinput-outputinstructionsarelistedbelow.
INP AC(0-7) INPR,FGI0 Inputchar.toAC
OUT OUTR AC(0-7),FGO0 Outputchar.fromAC
SKI if(FGI= 1)then(PC PC+ 1) Skip on inputflag
SKO if(FGO= 1)then(PC PC +1) Skip onoutputflag
ION IEN1 Interruptenableon
IOF IEN0 Interruptenableoff
Table2.2:InputOutputInstructions
 TheINPinstructiontransferstheinputinformationfromINPRintotheeightlow-
orderbitsofACandalsoclearstheinputflagto0.
 The OUTinstructiontransfersthe eightleastsignificantbitsofAC intothe
outputregisterOUTRandclearstheoutput flagto0.
 ThenexttwoinstructionsinTable2.2checkthestatusoftheflagsandcauseaskipofthenextinstr
uctionif theflagis1.
 Theinstructionthatisskippedwillnormallybeabranchinstructiontoreturnandchecktheflagag
ain.
 The branch instruction isnotskipped if the flagis0.Iftheflagis1, the branch
instructionisskippedand an inputor outputinstruction isexecuted.
 Thelasttwoinstructionssetandclearaninterruptenableflip-
flopIEN.ThepurposeofIENisexplained in conjunctionwiththeinterruptoperation.
12. WhatisanInterruptCycle?Drawandexplainflowchartofit.
 The waythattheinterruptishandledby thecomputercanbeexplainedby means
oftheflowchart showninfigure 2.13.
 An interruptflip-flopRisincludedin the computer.
 WhenR=0, thecomputergoesthrough an instructioncycle.
 DuringtheexecutephaseoftheinstructioncycleIENischeckedbythecontrol.
 Ifitis0,itindicatesthattheprogrammerdoesnotwanttousetheinterrupt,socontrolcontinuesw
iththenextinstructioncycle.
 IfIENis1,control checks the flagbits.
 Ifbothflagsare0,itindicatesthatneithertheinputnortheoutputregistersarereadyfortransfero
finformation.
 Inthiscase,controlcontinueswiththenextinstructioncycle.Ifeitherflagissetto1while
IEN=1,flip-flopR is setto1.
 Attheendoftheexecutephase,controlchecksthevalueofR,andifitisequalto1,itgoestoaninter
ruptcycleinsteadofaninstructioncycle.
InterruptCycle Figure2.13:Flowchartforinterruptcycle
 Theinterruptcycleisahardwareimplementationofabranchandsavereturnaddressoperation.
 ThereturnaddressavailableinPCisstoredinaspecificlocationwhereitcanbefoundlaterwhent
heprogramreturnstotheinstructionatwhichitwasinterrupted.Thislocationmaybeaprocesso
rregister,amemorystack,oraspecificmemorylocation.
 Herewechoosethememorylocationataddress0astheplaceforstoringthereturn
address.
 Controlthen insertsaddress1intoPCand clearsIEN andRso that no
moreinterruptionscanoccuruntiltheinterruptrequestfromtheflaghasbeenserviced.
 An examplethatshowswhat happensduringtheinterruptcycle isshownin Figure2.14:
Figure2.14:Demonstrationoftheinterruptcycle
 SupposethataninterruptoccursandR=1,while thecontrolisexecutingtheinstructionat
address255.Atthistime, thereturnaddress256isinPC.
 Theprogrammerhaspreviouslyplacedaninput-
outputserviceprograminmemorystartingfromaddress1120
andaBUN1120instructionataddress1.
 ThecontentofPC(256)isstoredinmemorylocation0,PCissetto1,andRisclearedto0.
 Atthebeginningofthenextinstructioncycle,theinstructionthatisreadfrommemoryisinaddres
s1sincethisisthecontentofPC.Thebranchinstructionataddress1causestheprogramtotransfe
rtotheinput-outputserviceprogramataddress1120.
 Thisprogramcheckstheflags,determineswhichflagisset,andthentransferstherequiredinputo
routputinformation.Oncethisisdone,theinstructionIONisexecutedtosetIENto1(toenablefur
therinterrupts),andtheprogramreturnstothelocationwhereitwasinterrupted.
 Theinstructionthatreturnsthecomputertotheoriginalplaceinthemainprogramisabranchindi
rectinstructionwithanaddresspart of0.Thisinstructionisplacedat the
endoftheI/Oserviceprogram.
 TheexecutionoftheindirectBUNinstructionresultsinplacingintoPCthe
returnaddressfromlocation0.
Registertransferstatements forthe interruptcycle
 Theflip-
flopissetto1ifIEN=1andeitherFGIorFGOareequalto1.Thiscanhappenwithanyclocktransition
exceptwhentimingsignalsT0,T1orT2areactive.
 Theconditionforsettingflip-
flopR=1canbeexpressedwiththefollowingregistertransferstatement:
T0T1T2 (IEN) (FGI+FGO): R 1
 Thesymbol+betweenFGIandFGOinthecontrolfunctiondesignatesalogicORoperation.Thisis
AND withIENand T0T1T2.
 ThefetchanddecodephasesoftheinstructioncyclemustbemodifiedandReplaceT0,T1,T2
withR'T0, R'T1,R'T2
 Thereforetheinterruptcyclestatementsare:RT0
: AR0,TRPC
RT1: M[AR]TR,PC0
RT2: PCPC+ 1,IEN0,R0,SC0
 DuringthefirsttimingsignalARisclearedto0,andthecontentofPCistransferredtothetemporar
yregisterTR.
 Withthesecondtimingsignal,thereturnaddressisstoredinmemoryatlocation0andPCiscleare
dto0.
 ThethirdtimingsignalincrementsPCto1,clearsIENandR,andcontrolgoesbacktoT0byclearingS
Cto0.
 The beginningofthe nextinstructioncyclehas thecondition RT0andthe
contentofPCisequalto1.Thecontrolthengoesthroughaninstructioncyclethatfetchesandexe
cutestheBUNinstructioninlocation1.
13. Drawandexplainflowchartforcomputeroperation.
 Thefinalflowchartoftheinstructioncycle,includingtheinterruptcycleforthebasiccomputer,is
showninFigure2.15.
 Theinterruptflip-flopRmaybe setatanytimeduringtheindirectorexecutephases.
 The control returnstotiming signal T0afterSC isclearedto0.
 IfR=1,thecomputergoesthroughaninterruptcycle.IfR=0,thecomputergoesthroughaninstruc
tion cycle.
 Iftheinstructionisoneofthememory-
referenceinstructions,thecomputerfirstchecksifthereisanindirectaddressandthencontinue
stoexecutethedecodedinstructionaccordingtotheflowchart.
 Iftheinstructionisoneoftheregister-
referenceinstructions,itisexecutedwithoneofthemicrooperationsregisterreference.
 Ifitisaninput-outputinstruction,itisexecutedwithoneofthemicrooperation’sinput-
outputreference.
Figure2.15:Flowchartforcomputeroperation
14. DrawandexplaindesignofAccumulatorLogic
 ThecircuitsassociatedwiththeACregisterareshowninfigure2.16.
Figure2.16:CircuitsassociatedwithAC
 Theadder andlogiccircuit hasthreesetsofinputs.
 Onesetof 16 inputscomes from theoutputsofAC.
 Anothersetof16inputscomesfromthedataregisterDR.
 Athirdsetofeight inputscomes fromtheinput registerINPR.
 Theoutputsofthe adderandlogiccircuitprovidethedata inputsforthe register.
 Inaddition,itisnecessarytoincludelogicgatesforcontrollingtheLD,INR,andCLRintheregistera
ndforcontrollingthe operationoftheadderand logiccircuit.
 In orderto designthelogicassociated withAC,it is necessary to extract all
thestatementsthatchangethecontentofAC.
D0 T ANDwithDR
AC←AC ∧ DR
5: AC ←AC +DR AddwithDRTrans
D1 AC←DR ferfromDRTransf
T5: AC(0-7) ← erfromINPRCom
D2 INPRAC plement
T5: ←AC’ Shift right
rB6: ←shr AC,AC(0)
AC ←shlAC, AC(15)←E
←E Shiftleft
rB AC ←0 ClearInc
11: AC ←AC +1 rement
 The gatestructure thatcontrols theLD, INR,andCLRinputsof ACisshown infigure2.17.
Figure2.17:GatestructureforcontrollingtheLD,INR,andCLRofAC
 Thegateconfigurationisderivedfromthecontrolfunctionsin thelist above.
 ThecontrolfunctionfortheclearmicrooperationisrB11,wherer=D7I’T3andB11 =IR(11).
 TheoutputoftheANDgatethatgeneratesthiscontrolfunctionisconnectedtotheCLRinputofth
eregister.
 Similarly,theoutputofthegatethatimplementstheincrementmicrooperationisconnectedtot
heINRinputoftheregister.
 Theothersevenmicrooperationsaregeneratedintheadderandlogiccircuitandareloadedinto
ACatthepropertime.
 The outputsofthe gates foreachcontrolfunctionaremarkedwitha symbolicnameandusedin
thedesignof theadderandlogic circuit.
15. DrawandexplainOnestageofadderandlogiccircuit.
Figure2.18:Onestageofadderandlogiccircuit
 Theadderandlogiccircuitcanbesubdividedinto16stages,witheachstagecorrespondingtoone
bitofAC.TheinternalconstructionoftheregisterisasshowninFigure2.18.
 WenotethateachstagehasaJKflip-
flop,twoORgates,andtwoANDgates.Theload(LD)inputisconnectedto the inputsofthe
ANDgates.
 The inputis labeled Ii, andtheoutputAC(i).
 WhentheLDinputisenabled,the16inputsIi,fori=0,1,2,...,15aretransferredtoAC(0-15).
 OnestageoftheadderandlogiccircuitconsistsofsevenANDgates,oneORgateandafull-
adder(FA).
 TheANDoperationisachievedbyANDingAC(i)withthecorrespondingbitinthedataregisterDR(i
).TheADD operationis obtainedusing abinaryadder.
 Onestageoftheadderusesa full-adderwiththecorrespondinginputandoutputcarries.
 ThetransferfromINPR to ACis onlyforbits0through7.
 Thecomplementmicrooperationisobtainedbyinvertingthebitvalue inAC.
 Theshift-rightoperationtransfersthebitfromAC(i+1),andtheshift-
leftoperationtransfersthebitfromAC(i-1).
 Thecompleteadderandlogiccircuit consistsof16stagesconnectedtogether.
Unit3– ProgrammingTheBasicComputer
1. DefineProgramandCategoriesofprograms.
Program
Aprogramisalistofinstructionsorstatementsfordirectingthecomputertoperformarequireddata
-processingtask.
Categories ofprograms
1. Binarycode:
This isa
sequenceofinstructionsandoperandsinbinarythatlisttheexactrepresentationofinstructions
astheyappearin computermemory.
2. Octalorhexadecimalcode:
Thisisanequivalenttranslationofthebinarycodetooctalorhexadecimalrepresentation.
3. Symboliccode:
Theuseremployssymbols(letters,numerals,orspecialcharacters)fortheoperationpart,thead
dresspart,andotherpartsoftheinstructioncode.Eachsymbolicinstructioncanbetranslatedint
oonebinarycodedinstruction.Thistranslationisdonebyaspecialprogramcalledanassembler.
Becauseanassemblertranslatesthesymbols,thistypeofsymbolicprogramisreferredtoasan
assemblylanguageprogram.
4. High-levelprogramminglanguages:
Thesearespeciallanguagesdeveloped toreflectthe proceduresusedinthe solution
ofaproblemratherthanbeconcerned
withthecomputerhardwarebehavior.Anexampleofahigh-
levelprogramminglanguageisFortran.Itemploysproblem-
orientedsymbolsandformats.Theprogramiswritteninasequenceofstatementsinaform that
peopleprefertothinkinwhensolvingaproblem.However,eachstatementmustbetranslatedin
toasequenceofbinaryinstructionsbeforetheprogramcanbeexecutedinacomputer.Theprogr
amthattranslatesahighlevellanguageprogramtobinaryiscalledacompiler.
2. ExplainAssemblylanguageandalsostatetherulesoflanguage.
 Thesymbolicprogram(containsletters,numerals,orspecialcharacters)isreferredtoasanasse
mblylanguage program.
 Thebasicunitof anassemblylanguageprogramis a lineof code.
 Thespecificlanguageisdefinedbyasetof
rulesthatspecifythesymbolsthatcanbeusedandtheymaybecombinedtoforma
lineofcode.
Rules ofthe Language
Eachlineofanassemblylanguageprogramisarrangedinthreecolumnscalledfields.Thefieldsspecifythe
followinginformation.
1. Thelabelfieldmaybe emptyor itmayspecifyasymbolic address.
A symbolicaddressconsistsof one, two,orthree,but not more than
threealphanumericcharacters.Thefirstcharacter mustbe aletter; the next twomaybe
lettersornumerals.The symbolcan be chosenarbitrarilyby theprogrammer.A
symbolicaddressinthe labelfieldis terminatedbyacomma so thatit willberecognized asa
labelbythe assembler.
2. Theinstruction field specifies a machineinstructionorapseudoinstruction.
Theinstructionfieldinanassemblylanguageprogrammayspecifyoneofthefollowingitems:
i. Amemory-referenceinstruction(MRI)
ii. Aregister-referenceorinput-outputinstruction(non-MRI)
iii. Apseudo instructionwithorwithoutanoperand
3. Thecommentfieldmaybe emptyor it mayinclude acomment.
Alineofcodemayormaynothaveacomment,butifithas,itmustbeprecededbyaslashfortheass
emblertorecognizethebeginningofacommentfield.Commentsareusefulforexplainingthepr
ogramandarehelpfulinunderstandingthestep-by-
stepproceduretakenbytheprogram.Commentsareinsertedforexplanationpurposeonlyand
areneglectedduringthebinarytranslationprocess.
3. Explainpseudoinstruction.
Apseudoinstructionisnotamachineinstructionbutratheraninstructiontotheassemblergivinginform
ationaboutsomephaseofthetranslation.Fourpseudoinstructionsthatarerecognizedbytheassembler
arelistedinTable3.1.
Symbol Information forthe Assembler

ORG N Hexadecimalnumber Nisthe memorylocation fortheinstruction
oroperand listed inthe followingline
END Denotes theendof symbolicprogram
DEC N Signed decimalnumber Ntobeconvertedtobinary
HEX N Hexadecimalnumber Ntobeconverted tobinary
Table3.1:DefinitionofPseudoinstructions
 TheORG(origin)pseudoinstructioninformstheassemblerthattheinstructionoroperandinthef
ollowinglineistobeplacedinamemorylocationspecifiedbythenumbernexttoORG.Itispossibl
etouseORGmorethanonceinaprogramtospecifymorethanonesegmentofmemory.
 TheENDsymbolisplacedattheendoftheprogramtoinformtheassemblerthattheprogramister
minated.
 Theothertwopseudoinstructions(DECandHEX)specifytheradixoftheoperandandtelltheasse
mblerhowtoconvertthelistednumbertoabinarynumber.
4. DefineAssemblerandexplainFirstPassofanassemblerwithflowch
art.
Assembler
 Anassemblerisaprogramthatacceptsasymboliclanguageprogramandproducesitsbinary
machinelanguageequivalent.
 Theinputsymbolicprogramiscalledthesourceprogramandtheresultingbinaryprogra
miscalledtheobjectprogram.
 Theassemblerisaprogramthatoperatesoncharacterstringsandproducesanequival
entbinaryinterpretation.
First Pass ofan assembler

 Duringthefirstpass,itgeneratesatablethatcorrelatesalluser-
definedaddresssymbolswiththeirbinaryequivalentvalue.
 Thebinarytranslationisdoneduringthesecondpass.
 To
keeptrackofthelocationofinstructions,theassemblerusesamemorywordcalledalocationco
unter(abbreviatedLC).
 ThecontentofLCstoresthevalueofthememorylocation
assignedtotheinstructionoroperandpresentlybeingprocessed.
 The ORGpseudoinstruction initializesthe location countertothevalueofthe
firstlocation.
 Sinceinstructionsarestored in
sequentiallocations,thecontentofLCisincrementedby1afterprocessingeachline ofcode.
 To avoid ambiguityincaseORGismissing,the assemblersetsthe
locationcounterto0initially.
 Thetasksperformedbytheassemblerduringthefirstpassaredescribedin
theflowchartoffigure 3.1.
 LCis initiallysetto 0.
 Alineofsymbolic codeisanalyzedtodetermine if ithasalabel (bythepresence of
acomma).
 Ifthe lineofcodehasnolabel,the assembler checks the symbol in theinstructionfield.
 Ifitcontainsan ORGpseudoinstruction,theassembler
setsLCtothenumberthatfollowsORGand goesbacktoprocessthenextline.
 Ifthe linehas an
ENDpseudoinstruction,theassemblerterminatesthefirstpassandgoestothe
secondpass.
 If the lineofcodecontains a label,itisstoredinthe
addresssymboltabletogetherwithitsbinaryequivalentnumber
specifiedbythecontentofLCNothingisstoredinthe tableifno labelisencountered.
 LCisthen incrementedby1 andanewlineofcode isprocessed.
FirstPass
LC ←0
Scannextline ofcode
Set LC
Yes
No
Label ORG
No
Yes
Yes
Storesymbolinaddresssymboltabletogetherwith valueof LC END
Go toSecondPass
no
IncrementLC
Figure3.1:Flowchartforfirstpassofassembler
5. Explain the working of Second Pass Assembler with

itsflowchart.
 Machineinstructionsaretranslatedduringthesecondpassbymeansoftable-
lookupprocedures.
 Atable-
lookupprocedureisasearchoftableentriestodeterminewhetheraspecificitemmatchesoneof
theitemsstored in thetable.
 Theassemblerusesfourtables.Anysymbolthatisencounteredintheprogrammustbeavailable
asanentryinoneofthesetables;otherwise,thesymbolcannotbeinterpreted.
1. Pseudoinstructiontable
2. MRItable
3. Non-MRItable
4. Addresssymboltable
 TheentriesofthepseudoinstructiontablearethefoursymbolsORG,END,DEC,andHEX.
 Eachentryreferstheassemblertoasubroutinethatprocessesthepseudoinstructionwhenenco
unteredintheprogram.
 TheMRItablecontainsthesevensymbolsofthememory-referenceinstructionsandtheir3-
bitoperationcodeequivalent.
 Thenon-MRItablecontainsthesymbolsforthe18register-referenceandinput-output
instructionsandtheir16-bitbinarycodeequivalent.
 Theaddresssymboltable isgeneratedduringthefirstpassoftheassemblyprocess.
 Theassemblersearchesthesetablestofindthesymbolthatitiscurrentlyprocessinginordertode
termineitsbinaryvalue.
 ThetasksperformedbytheassemblerduringthesecondpassaredescribedintheflowchartofFi
gure 3.2.
 LCis initiallysetto 0.
 Linesofcodearethenanalyzedoneatatime.
 Labelsareneglectedduringthesecondpass,sotheassemblergoesimmediatelytotheinstructi
onfieldandproceedstocheckthefirst symbolencountered.
 Itfirstchecksthepseudo instructiontable.
 AmatchwithORGsendsthe assemblertoasubroutinethat setsLCtoaninitialvalue.
 AmatchwithENDterminatesthetranslationprocess.Anoperandpseudoinstructioncausesaco
nversionof the operandintobinary.
 Thisoperandisplaced inthememorylocationspecifiedbythecontentofLC.
 Thelocationcounteristhenincrementedby1andtheassemblercontinuestoanalyzethenextlin
e of code.
 Ifthesymbolencounteredisnotapseudoinstruction,theassemblerreferstotheMRItable.
 Ifthe symbol isnotfound inthistable,the assemblerrefersto thenon-MRItable.
 A symbolfound in thenon-MRItablecorresponds toaregisterreferenceorinput-
outputinstruction.
 Theassemblerstoresthe16-bitinstructioncodeintothememorywordspecifiedbyLC.
 Thelocationcounterisincrementedandanewline analyzed.
 WhenasymbolisfoundintheMRItable,theassemblerextractsitsequivalent3-bitcode
andinserts itmbits2through4ofa word.
 Amemoryreferenceinstructionisspecifiedbytwoorthreesymbols.
 Thesecondsymbolisasymbolicaddressandthethird,whichmayormaynotbepresent,isthelett
erI.
 Thesymbolicaddressisconvertedtobinarybysearchingtheaddresssymboltable.
 Thefirstbit of the instructionis setto0or1, dependingonwhether the letter I
isabsentorpresent.
 Thethreepartsofthebinaryinstructioncodeareassembledandthenstoredinthememoryloca
tionspecifiedbythecontentofLC.
 Thelocationcounterisincrementedandtheassemblercontinuestoprocessthenextline.
 Oneimportanttaskofan assembleristocheckforpossibleerrorsinthe
symbolicprogram.Thisiscallederrordiagnostics.
 Onesucherrormaybeaninvalidmachinecodesymbolwhichisdetectedbyitsbeingabsent in
theMRI andnon-MRItables.
 Theassemblercannottranslatesuchasymbolbecauseit
doesnotknowitsbinaryequivalentvalue.
 In sucha case,the assembler prints anerror message toinformtheprogrammer
thathissymbolicprogramhasanerrorataspecificlineofcode.
Second Pass
LC←0
Done
Scannext lineofcode
Set LC
yes
yes yes
Pseudo-
instruction ORG END
no
no
no
DEC orHEX
yes no
Convertoperandtobinary andstore inlocationgive
MRI
byLC
Get OperationCode
andset bits 2-4 Valid non-
MRI
instruction
Searchaddress-
symboltableforbinaryequivalentofsymbolicaddressand
no
setbits5-16 yes
Storebinary Error in
I equivalentofinstructioninlocationgivenby
lineofcode
LC
Set first Set first

bit to 1 bit to 0
Assembleallparts ofbinary
instructionandstore inlocationgivenbyLC IncrementLC
Figure3.2:Flowchartforsecondpassofassembler
6. Writeshortnoteonsubroutine.
The samepiece ofcodemustbe writtenover againinmanydifferent partsofaprogram.
Insteadofrepeatingthecodeeverytimeitisneeded,thereisanadvantageifthecommoninstruc
tionsarewrittenonlyonce.
 Asetofcommoninstructionsthatcanbeusedinaprogrammanytimesiscalleda
subroutine.
 Each time thatasubroutine isusedinthemainpart of theprogram, abranch
isexecutedtothebeginningofthesubroutine.
 Afterthesubroutinehasbeenexecuted,abranchisreturnedtothemainprogram.
 A subroutine consistsof a self-contained sequence ofinstructionsthat carriesout a
giventask.
 Abranchcanbemadetothe subroutinefromanypart ofthemainprogram.
 Thisposestheproblemofhowthesubroutineknowswhichlocationtoreturnto,sincemanydiffe
rentlocationsinthemainprogrammaymakebranchestothesamesubroutine.
 Itisthereforenecessarytostorethereturnaddresssomewhereinthecomputerforthesubroutin
etoknowwheretoreturn.
 Becausebranchingtoasubroutineandreturningtothemainprogramissuchacommonoperatio
n,allcomputersprovidespecialinstructionstofacilitatesubroutineentryandreturn.
 Inthebasiccomputer,thelinkbetweenthemainprogramandasubroutineistheBSAinstruction(
branchandsavereturnaddress).
ExampleofSubroutine: ORG100 /Mainprogram
100 LDA X /Load X
101 BSA SH4 /Branchtosubroutine
102 STA X /Storeshiftednumber
103 LDA Y /Load Y
104 BSA SH4 /Branchto subroutineagain
105 STA Y /Storeshiftednumber
106 HLT
107 x, HEX1234
108 Y, HEX4321
/Subroutinetoshiftleft4 times
109 SH4, HEX 0
/Storereturnaddresshere10A CIL
/Circulateleftonce
10B CIL
10C CIL
10D CIL
/Circulateleftfourthtime10E
ANDMSK /SetAC(13-16)tozero
10F BUNSH4I /Returntomainprogram
110 MSK, HEX FFF0 /Maskoperand
END
7. Drawandexplainflowchartformultiplicationprogram.
Figure3.3:Flowchartformultiplicationprogram
 Theprogramformultiplyingtwonumbersisbasedontheprocedureweusetomultiplynumbers
withpaperandpencil.
 Asshowninthenumericalexampleoffigure3.3,themultiplicationprocessconsistsofcheckingt
hebitsofthemultiplierYandaddingthemultiplicandXasmanytimesasthereare1's
inY,providedthatthevalueofXisshiftedleftfromone linetothenext.
 Sincethecomputercanaddonlytwonumbersatatime,wereserveamemorylocation,denotedb
yP,tostoreintermediatesums.
 Theintermediatesumsarecalledpartialproductssincetheyholdapartialproductuntilallnumbe
rsareadded.
 Asshown inthenumericalexampleunderP,thepartialproduct startswithzero.
 The multiplicand Xisadded tothecontentof Pforeachbitof themultiplier Ythat is1.
 ThevalueofXisshiftedleftafter checkingeachbitofthemultiplier.
 Thefinalvalue inPforms theproduct.
 Theprogramhasaloopthatistraversedeighttimes,onceforeachsignificantbitofthemultiplier.
 Initially,location XholdsthemultiplicandandlocationYholdsthemultiplier.
 A counterCTR issetto-8 and locationPiscleared tozero.
 Themultiplierbit can bechecked ifitistransferredtotheEregister.
 ThisisdonebyclearingE,loadingthevalueofYintotheAC,circulatingrightEandACandstoringth
eshiftednumberbackintolocationY.
 Thisbit stored inEisthelow-orderbit of the multiplier.
 WenowcheckthevalueofE.Ifitis1,themultiplicandXisaddedtothepartialproduct
P.Ifit is0,thepartialproductdoes not change.
 WethenshiftthevalueofXoncetotheleftbyloadingitintotheACandcirculatingleftE andAC.
 TheloopisrepeatedeighttimesbyincrementinglocationCTRandcheckingwhenitreacheszero.
 Whenthecounterreacheszero,theprogramexitsfromtheloop withtheproductstoredin
location P.
8. Write an assembly language program to Add two

doubleprecisionnumbers.(Sum14)
1 LDA AL /LoadA Low
2 ADDBL /AddB low , CarryinE
3 STA CL /Store inC low
4 CLA /ClearAC
5 CIL /Circulatetobring carryintoAC(16)
6 ADDAH /AddAhighand carry
7 ADDBH /AddB high
8 STA CH /Store inChigh
9 HLT /IncrementCounter0
10 AL ------------ /Locationsofoperand
11 ,
A ------------
12 H,
BL ------------
13 ,
BH ------------
14 ,
CL ------------
15 ,
CH ------------
16 , END /Endofsymbolicprogram
9. Writeanassemblylanguageprogramtomultiplytwopositivenumb
ers.(Sum14,Win11)
1 ORG100
2 LO CLE /ClearE
3 P, LDA Y /Loadmultiplier
4 CIR /Transfermultiplier bitto E
5 STA Y /Storeshiftedmultiplier
6 SZE /Checkifbitiszero
7 BUNONE /Bit isone,goto ONE
8 BUNZRO /Bit iszerogotoZERO
9 ON LDA X /LoadMultiplicand
10 E, ADDP /Addto partialproduct
11 STAP /Storepartialproduct
12 CLE /ClearE
13 ZR LDA X /LoadMultiplicand
14 O, CIL /Shiftleft
15 STA X /Storeshiftedmultiplicand
16 ISZ CTR /IncrementCounter
17 BUNLOP /Counternotzero;repeatloop
18 HLT /Counteriszerohalt
19 CT DEC -8 /Thislocation serversasacounter
20 R,
X, Hex000F /Multiplicandstoredhere
21 Y, HEX000B /Multiplierstoredhere
22 P, HEX 0 /Productformedhere
23 END /Endofsymbolicprogram
10 Writetheprogramto multiply twopositivenumbersbya
. repeatedaddition method. ex., to multiply 5 x 4,the
programevaluates theproduct byadding5 fourtimes,or
5+5+5+5.(Win10)
1 ORG100 /OriginofprogramisHEX 100
2 LDA X /Loadfirst addressofoperands
3 STAPTR /Storeinpointer
4 LDANBR /Loadminus second operand
5 STA Y /Storeincounter
6 CLA /Clearaccumulator
7 LOP ADDPTRI /AddanoperandtoAC
8 , ISZ Y /Incrementcounter
9 BUNLOP /Repeatloopagain
10 STAMUL /Storesum
11 HLT /Halt
12 X, DEC5 /Firstoperand
13 PTR HEX 0 /Thislocationreservedforapointer
14 ,NB DEC -4 /Secondoperand
16 R,
CTR HEX 0 /Thislocationreservedforacounter
17 ,
MU HEX 0 /Sumisstoredhere
18 L, END /Endofsymbolicprogram
11. Writeanassembly languageprogram to takea character

asinputandoutputsit.(Sum13)
Input aCharacter
1 CIF SKI /Checkinputflag
2 , BUNCIF /Flag=0,branchtocheckagain
3 INP /Flag=1,inputcharacter
4 OUT /PrintCharacter
5 STACHR /StoreCharacter
6 HLT
7 CH --
R
Outputa Character
1 LDACHR /LoadcharacterintoAC
2 CO SKO /Checkoutputflag
3 F, BUNCOF /Flag=0,branchtocheckagain
4 OUT /Flag=1,outputcharacter
5 HLT
6 CH HEX0057 /Character is “W”
R,
12. WriteaSubroutinetoInputandPackTwoCharacters.
1 IN2 /Subroutineentry
2 ,
FST SKI
3 , BUNFST
4 INP /Inputfirstcharacter
5 OUT
6 BSA SH4 /Shiftleftfourtimes
7 BSA SH4 /Shiftleftfourmoretimes
8 SC SKI
9 D, BUNSCD
10 INP /Inputsecondcharacter
11 OUT
12 BUNIN2I /Return
13. WriteanALPtotransferablockof10bytesfromonelocationtoother.
(Win14)
/Mainprogram
1 BSAMVE /Branchtosubroutine
2 HEX100 /First addressofsourcedata
3 HEX200 /Firstaddressofdestinationdata
4 DEC -10 /Numberofitemstomove
5 HLT
6 MV HEX 0 /SubroutineMVE
7 E, LDAMVE I /Bringaddressofsource
8 STAPT1 /Storeinfirstpointer
9 ISZMVE /Incrementreturnaddress
10 LDAMVE I /Bringaddressofdestination
11 STAPT2 /Storeinsecondpointer
13 LDAMVE I /Bringnumberofitems
14 STA CTR /Storeincounter
16 LOP LDA PT1 I /Loadsourceitem
17 , STAPT2I /Storeindestination
18 ISZPT1 /Incrementsourcepointer
19 ISZPT2 /Incrementdestinationpointer
21 BUNLOP /Repeat10times
22 BUNMVEI /Returntomainprogram
23 PT1 ---
24 ,
PT2 ---
25 ,
CTR ---
,
14. Writeanassemblylevelprogramforthefollowingpseudo code.
(Sum-10)
SUM=0
SUM=SUM+A+BDIF=
DIF–C
SUM=SUM+DIF
1 ORG100
2 LDAA /Loadvaluetoaccumulator
3 ADDB /additionAC=AC+B
4 STA SUM /Storeresultindestination
5 LDA C /Loadvaluetoaccumulator
6 CMA /
7 STA C Complementaccumulator
/Storeresultindestination
8 ISZ C /Incrementandskip ifzero
9 LDA DIF /Loadvaluetoaccumulator
10 ADDC /addition
11 STA DIF /Loadvaluetoaccumulator
12 HLT /halt
13 A, DEC5
14 B, DEC4
15 C, DEC10
16 SU HEX 0
17 M,
DIF, DEC100
15. WritetheprogramtologicallyORthetwonumbers.(Win-10)
2 LDAA /Loadfirstoperand
3 CMA /ComplementA
4 STAAD /Store at AD
5 LDAB /Loadsecondoperand
6 CMA /ComplementB
7 ANDAD /AndA andB
8 CMA /Complementtheresult
9 STA RES /Storetheresult
10 HLT /Halt
11 A, DEC5 /Firstoperand
12 AD, HEX 0 /ThislocationreservedAcomplement
13 B, DEC4 /Secondoperand
14 RE HEX 0 /ThislocationreservedforResult
S,
16. Writeaprogramloopusingapointerandacountertoclearthe
content of hex locations 500 to 5FF with 0
s .
(Win-
2 0
LDAAD /Loadfirst addressHEX500
3 S
STAPTR /Storeinpointer
4 LDANB /Loadminus second operand
5 R
STA /Storeincounter
6 CTR
CLA /Clearaccumulator
7 LOP, STAPTR /Clearmemorylocation
8 I
ISZPTR /IncrementPointer
10 BUNLO /Repeatloopagain
11 P
HLT /Halt
12 ADS, DEC50 /Startingmemorylocation
13 PTR, 0
HEX 0 /Startingpointer
14 NBR DEC- /Secondoperand
15 ,
CTR, 256 0
HEX /Thislocationreservedforacounter
17. WriteaSymbolicProgramtoAdd100Numbers.
2 LDAADS /Loadfirst addressofoperands
3 STAPTR /Storeinpointer
4 LDANBR /Loadminus100
5 STA CTR /Storeincounter
6 CLA /Clearaccumulator
7 LOP ADDPTRI /AddanoperandtoAC
8 , ISZPTR /Incrementpointer
9 ISZ CTR /Incrementcounter
10 BUNLOP /Repeatloopagain
11 STA SUM /Storesum
12 HLT /Halt
13 ADS HEX150 /First addressofoperands
14 ,
PTR HEX 0 /Thislocationreservedforapointer
15 ,NB DEC-100 /Constanttoinitializedcounter
16 R,
CTR HEX 0 /Thislocationreservedforacounter
17 ,
SU HEX 0 /Sumisstoredhere
18 M, ORG150 /Origin ofoperandsisHEX 150
19 DEC75 /Firstoperand
.
.
.
118 DEC23 /Last operand
18. Writeanassemblylanguageprogramforarithmeticrightshiftoper
ation.
1 CLE /ClearEto0
2 SPA /SkipifACispositive; Eremains0
3 CME /ACisnegative;setEto1
4 CIR /CirculateEandAC
19. WriteaProgramtoStoreInputCharactersinaBuffer.
1 LDAADS /Loadfirst addressofbuffer
2 STAPTR /Initializepointer
3 LO BSAIN2 /Goto subroutineIN2(seeprogramno.12)
4 P, STAPTRI /Storedoublecharacterwordinbuffer
5 ISZPTR /Incrementpointer
6 BUNLOP /Branchtoinputmorecharacters
7 HLT
8 AD HEX500 /First addressofbuffer
9 S,
PTR HEX 0 /Locationforpointer
,
20. WriteaProgramtoCompareTwoWords.
1 LDAWD1 /Loadfirstword
2 CMA
3 INC /Form2'scomplement
4 ADDWD2 /Addsecond word
5 SZA /Skip ifACiszero
6 BUNUEQ /Branchto"unequal"routine
7 BUNEQL /Branchto"equal"routine
8 WD1,—
9 WD2,—
21. Writeanassemblylanguageprogramtosubtracttwodoubleprecisi
onnumbers.(Sum13)
1 CLE
2 LDABL /LoadLowSubtrahend B
3 CMA /Takeone’scomplement
4 INC /Increment to form
5 ADDAL 2’scomplement
/Addthe Low Minuend
6 STACL /Storelowbit
7 CLA /Clear
8 CIL /leftshift
9 STATMP /SaveCarry
10 LDABH /LoadHigh B
11 CMA /ComplementBH
12 ADDAH
13 ADDTMP /Addcarry
14 STA CH /Store inC
15 HLT
16 TM HEX 0
17 P,
C, Hex0
22. Writeaprogramforthearithmeticshift-
leftoperation.BranchtoOVFifanoverflowoccurs.
1 LDA X
2 CLE
/zero toloworderbit;sign
3 bitinE
CIL
4 SZE
5 BUNON
6 E
SPA
7 BUNOV
8 FBUNEX
9 ON T
SNA
10 E, BUNOV
11 EXT FHLT
,
23. Writeaprogramthatevaluatesthelogicexclusive-
ORoftwologicoperands.
z=x⊕y=xy'+x'y=[(xy')'.(x'y)']'
1 LDAY
2 CMA
3 ANDX
4 CMA
5 STATM
5 P
LDAX
6 CMA
7 ANDY
8 CMA
9 AND
10 TMP
CMA
11 STAZ
12 HLT
13 X, ---
14 Y, ---
15 Z, ---
16 TM ---
P,
Unit4– MicroprogrammedControl
1. Definethefollowing.
HardwiredControlUnit:
Whenthecontrolsignalsaregeneratedbyhardwareusingconventionallogicdesigntechniques,thecon
trolunit issaidtobehardwired.
Micro programmedcontrolunit:
A controlunitwhosebinary controlvariablesare storedin memoryis calleda
microprogrammedcontrolunit.
Dynamic microprogramming:
Amoreadvanceddevelopmentknownasdynamicmicroprogrammingpermitsamicroprogramtobelo
adedinitiallyfromanauxiliarymemorysuchasamagneticdisk.Controlunitsthatusedynamicmicroprog
rammingemployawritablecontrolmemory.Thistypeofmemorycanbeusedforwriting.
ControlMemory:
ControlMemoryisthestorageinthemicroprogrammedcontrolunittostorethemicroprogram.
WriteableControlMemory:
ControlStoragewhosecontentscanbe modified,allow thechangein
microprogramandInstructionsetcanbechangedormodifiedisreferredas WriteableControlMemory.
ControlWord:
Thecontrolvariablesatanygiventimecanberepresentedbyacontrolwordstringof1'sand0'scalledaco
ntrolword.
2. Describethefollowingterms:Microoperation,Microinstruction,Mi
croprogram,Microcode.
Microoperations:
 Incomputercentralprocessingunits,micro-operations(alsoknownas amicro-ops
orμops)aredetailedlow-
levelinstructionsusedinsomedesignstoimplementcomplexmachineinstructions(sometimes
termed macro-instructionsinthiscontext).
Microinstruction:
 Asymbolicmicroprogramcanbetranslatedintoitsbinaryequivalentbymeansofanassembler.
 Eachlineoftheassemblylanguagemicroprogramdefinesasymbolicmicroinstruction.
 Eachsymbolicmicroinstructionisdividedintofivefields:label,microoperations,CD,BR,andAD.
Microprogram:
 Asequenceofmicroinstructionsconstitutesamicroprogram.
 Sincealterationsofthemicroprogramarenotneededoncethecontrolunitisinoperation,theco
ntrolmemorycanbearead-onlymemory(ROM).
 ROMwordsaremadepermanentduringthehardwareproductionoftheunit.
 Theuse of a microprogram involvesplacingall controlvariables in wordsofROMfor
usebythecontrolunitthroughsuccessivereadoperations.
 ThecontentofthewordinROM at agivenaddressspecifiesamicroinstruction.
Microcode:
 Microinstructionscanbesavedbyemployingsubroutinesthatusecommonsectionsofmicroco
de.
 Forexample,thesequenceofmicrooperationsneededtogeneratetheeffectiveaddressoftheo
perandforaninstructioniscommontoallmemoryreferenceinstructions.
 Thissequencecouldbeasubroutinethatiscalledfromwithinmanyotherroutinestoexecutethe
effectiveaddresscomputation.
3. Draw and explain the organization of micro

programmedcontrolunit.
 Thegeneralconfigurationofamicro-
programmedcontrolunitisdemonstratedintheblockdiagramofFigure4.1.
 ThecontrolmemoryisassumedtobeaROM,withinwhichallcontrolinformationispermanently
stored.
figure4.1:Micro-programmedcontrolorganization
 Thecontrolmemoryaddressregisterspecifiestheaddressofthemicroinstruction,andthecontr
oldataregisterholdsthemicroinstructionreadfrommemory.
 Themicroinstructioncontainsacontrolwordthatspecifiesoneormoremicrooperationsforthe
dataprocessor.Oncetheseoperations are
executed,thecontrolmustdeterminethenextaddress.
 Thelocationofthenextmicroinstructionmaybetheonenextinsequence,oritmaybelocatedso
mewhereelsein thecontrolmemory.
 While themicrooperationsarebeing executed,the next address is
computedinthenextaddressgeneratorcircuitandthentransferredintothecontroladdressregi
stertoreadthenextmicroinstruction.
 Thusamicroinstructioncontainsbitsforinitiatingmicrooperationsinthedataprocessorpartan
d bitsthatdeterminetheaddresssequenceforthecontrolmemory.
 Thenextaddressgeneratorissometimescalledamicro-
programsequencer,asitdeterminestheaddresssequencethatisreadfromcontrolmemory.
 Typicalfunctionsofamicro-
programsequencerareincrementingthecontroladdressregisterbyone,loadingintothecontro
laddressregisteranaddressfromcontrolmemory,transferringanexternaladdress,orloadinga
ninitialaddresstostartthecontroloperations.
 Thecontroldataregisterholdsthepresentmicroinstructionwhilethenextaddressiscomputed
andreadfrommemory.
 Thedataregisterissometimescalledapipelineregister.
 Itallowstheexecutionofthemicrooperationsspecifiedbythecontrolwordsimultaneouslywith
thegenerationofthenext microinstruction.
 Thisconfigurationrequiresatwo-
phaseclock,withoneclockappliedtotheaddressregisterandtheothertothedataregister.
 Themainadvantageofthemicroprogrammedcontrolisthefactthatoncethehardwareconfigur
ationisestablished;thereshouldbenoneedforfurtherhardwareorwiringchanges.
 Ifwewanttoestablishadifferentcontrolsequenceforthesystem,allweneedtodoisspecifyadiff
erentsetofmicroinstructionsforcontrolmemory.
4. ExplainthestepsofAddressSequencingindetail.
 Microinstructionsarestoredincontrolmemoryingroups,witheachgroupspecifyinga
routine.
 Toappreciatetheaddresssequencinginamicro-
programcontrolunit,letusspecifythestepsthatthecontrolmustundergoduringtheexecutiono
fasinglecomputerinstruction.
Step-1:
 Aninitialaddressisloadedintothecontroladdressregisterwhenpoweristurnedoninthecompu
ter.
 Thisaddressisusuallytheaddressofthefirstmicroinstructionthatactivatestheinstructionfetch
routine.
 Thefetchroutinemaybesequencedbyincrementingthecontroladdressregisterthroughthere
stofitsmicroinstructions.
 Attheendofthefetchroutine,theinstructionisintheinstructionregisterofthecomputer.
Step-2:
 Thecontrolmemorynextmustgothroughtheroutinethatdeterminestheeffectiveaddressofth
e operand.
 Amachineinstructionmayhavebitsthatspecifyvariousaddressingmodes,suchasindirectaddr
essandindexregisters.
 Theeffectiveaddresscomputationroutineincontrolmemorycanbereachedthroughabranch
microinstruction,whichisconditionedonthestatusofthemodebitsoftheinstruction.
 Whentheeffectiveaddresscomputationroutineiscompleted,theaddressoftheoperandisavai
lable inthememoryaddressregister.
Step-3:
 Thenextstepistogeneratethemicrooperationsthatexecutetheinstructionfetchedfrommem
ory.
 Themicrooperationstepstobegeneratedinprocessorregistersdependontheoperationcodep
artofthe instruction.
 Eachinstructionhasitsownmicro-programroutinestoredinagivenlocationofcontrolmemory.
 Thetransformationfromtheinstructioncodebitstoanaddressincontrolmemorywheretherou
tineislocatedisreferredtoasamapping process.
 Amappingprocedureisarulethattransformstheinstructioncodeintoacontrolmemoryaddress
.
Step-4:
 Oncetherequiredroutineisreached,themicroinstructionsthatexecutetheinstructionmaybe
sequencedbyincrementingthecontroladdressregister.
 Micro-
programsthatemploysubroutineswillrequireanexternalregisterforstoringthereturnaddress
.
 Returnaddressescannotbe stored in ROMbecausetheunithasnowritingcapability.
 Whentheexecutionoftheinstructioniscompleted,controlmustreturntothefetchroutine.
 Thisisaccomplishedbyexecutinganunconditionalbranchmicroinstructiontothefirstaddress
ofthefetch routine.
Insummary,theaddresssequencingcapabilitiesrequiredinacontrolmemoryare:
1. Incrementingofthecontroladdressregister.
2. Unconditionalbranchorconditionalbranch,dependingonstatusbitconditions.
3. Amappingprocessfromthebitsoftheinstructionto an addressforcontrolmemory.
4. Afacilityforsubroutinecall andreturn.
5. Drawandexplainselectionofaddressforcontrolmemory.
Figure4.2:Selectionofaddressforcontrolmemory
 Abovefigure4.2showsablockdiagramofacontrolmemoryandtheassociatedhardwareneede
dforselectingthenextmicroinstructionaddress.
 Themicroinstructionincontrolmemorycontainsasetofbits
toinitiatemicrooperationsincomputerregistersandotherbitstospecifythemethodbywhichth
enextaddressisobtained.
 Thediagramshowsfourdifferentpathsfromwhichthecontroladdressregister(CAR)receivesth
eaddress.
 Theincrementerincrementsthecontentofthecontroladdress registerbyone,
toselectthenextmicroinstructioninsequence.
 Branchingisachievedbyspecifyingthebranchaddressinoneofthefieldsofthemicroinstruction.
 Conditionalbranchingisobtainedbyusingpartofthemicroinstructiontoselectaspecificstatusb
it inorder todetermineitscondition.
 Anexternaladdressistransferredintocontrolmemoryviaamappinglogiccircuit.
 Thereturnaddressforasubroutineisstoredinaspecialregisterwhosevalueisthenusedwhenth
emicro-program wishestoreturnfromthesubroutine.
 Thebranchlogicof figure4.2providesdecision-makingcapabilitiesinthe controlunit.

 Thestatusconditionsarespecialbitsinthesystemthatprovideparameterinformationsuchasth
ecarry-outofanadder,thesignbitofanumber,themodebitsofaninstruction,and
inputoroutput statusconditions.
 Thestatusbits,togetherwiththefieldinthemicroinstructionthatspecifiesabranchaddress,con
troltheconditionalbranchdecisionsgenerated in thebranchlogic.
 A1outputinthemultiplexergeneratesacontrolsignaltotransferthebranchaddressfromthemi
croinstructionintothecontroladdressregister.
 A0outputinthemultiplexercausestheaddressregistertobeincremented.
6. ExplainMappingofanInstruction
 Aspecialtypeofbranchexistswhenamicroinstructionspecifiesabranchtothefirstwordincontr
olmemorywhereamicroprogramroutineforaninstructionislocated.
 Thestatusbitsforthistypeofbrancharethebitsintheoperationcodepartoftheinstruction.
Forexample,acomputerwithasimpleinstructionformatasshowninfigure4.3hasanoperation
codeoffourbitswhich can specifyupto 16distinctinstructions.
 Assumefurtherthatthecontrolmemoryhas128words,requiringanaddressofsevenbits.
 Onesimple mappingprocessthat convertsthe4-bit operation codetoa7-bit
addressforcontrolmemoryisshownin figure4.3.
 Thismappingconsistsofplacinga0inthemostsignificantbitoftheaddress,transferringthe four
operationcode bits,and clearingthe two least significantbitsofthecontroladdressregister.
 Thisprovidesforeachcomputerinstructionamicroprogramroutinewithacapacityoffourmicro
instructions.
 Iftheroutineneedsmorethanfourmicroinstructions,itcanuseaddresses1000000through111
1111.Ifituses fewerthanfourmicroinstructions,theunusedmemorylocationswould
beavailableforotherroutines.
Figure4.3:Mappingfrominstructioncodetomicroinstructionaddress
 Onecanextendthisconcepttoamore
generalmappingrulebyusingaROMtospecifythemappingfunction.
 ThecontentsofthemappingROMgivethebitsforthe controladdressregister.
SwatiSharma,CEDepartment|2140707–ComputerOrganization 6
 Inthiswaythemicroprogramroutinethatexecutestheinstructioncanbeplaced
inanydesiredlocationincontrolmemory.
 Themappingconceptprovidesflexibilityforaddinginstructionsforcontrolmemoryasthene
edarises.
7. DrawandexplainComputerHardwareConfigurationindetail.
Figure4.4:Computerhardwareconfiguration
Theblockdiagramof thecomputerisshown inFigure4.4. It consistsof
1. Twomemoryunits:
Mainmemory-
>forstoringinstructionsanddata,andControlmemory-
>forstoringthemicroprogram.
2. SixRegisters:
Processorunitregister:AC(accumulator),PC(ProgramCounter),AR(AddressRegister),DR(Dat
aRegister)
Controlunitregister:CAR(ControlAddressRegister),SBR(SubroutineRegister)
3. Multiplexers:
The transferofinformationamong theregistersin the processoris
donethroughmultiplexersratherthanacommonbus.
4. ALU:
Thearithmetic,logic,andshiftunitperformsmicrooperationswithdatafromACandDRandplac
estheresultin AC.
SwatiSharma,CEDepartment|2140707–ComputerOrganization 7
 DRcanreceiveinformationfromAC,PC,ormemory.
 ARcanreceiveinformationfromPCorDR.
 PCcanreceiveinformationonlyfromAR.
 Inputdatawrittentomemorycomefrom DR,anddata readfrommemorycan goonlytoDR.
8. ExplainMicroinstructionFormatindetail.
Themicroinstructionformatforthecontrolmemoryisshowninfigure4.5.The20bitsofthemicroinstruc
tionare dividedintofourfunctionalpartsasfollows:
1. ThethreefieldsF1,F2,and F3 specifymicrooperationsforthecomputer.
Themicrooperationsaresubdividedintothreefieldsofthreebitseach.Thethreebitsineachfield
areencodedtospecifysevendistinctmicrooperations.Thisgivesatotalof21microoperations.
2. TheCD fieldselectsstatusbitconditions.
3. TheBRfieldspecifiesthetypeofbranchtobeused.
4. TheADfieldcontainsabranchaddress.Theaddressfieldissevenbitswide,sincethecontrolmem
oryhas128=27words.
Figure4.5:MicroinstructionFormat
 Asanexample,a microinstructioncanspecifytwosimultaneousmicrooperationsfromF2
andF3andnone fromF1.
DRM[AR]with F2
=100PCPC+
1withF3=101
 Thenine bitsofthe microoperationfieldswillthen be 000100101.
 TheCD (condition)fieldconsistsoftwobitswhichare encodedto specifyfour
statusbitconditionsaslistedinTable4.1.
Table4.1:ConditionField
 TheBR(branch)fieldconsistsoftwobits.Itisused,inconjunctionwiththeaddressfieldAD,tocho
osethe addressofthe next microinstructionshown in Table 4.2.
Table4.2:BranchField
9. ExplainSymbolicMicroinstruction.
 Each lineoftheassemblylanguagemicroprogramdefinesasymbolicmicroinstruction.
 Eachsymbolicmicroinstructionisdividedintofivefields:label,microoperations,CD,BR,andAD.
ThefieldsspecifythefollowingTable4.3.
1 Label Thelabelfieldmaybeemptyoritmayspecifyasymbolicaddres
. s.Alabelisterminatedwithacolon (:).
2 Microoperation Itconsistsofone,two,orthreesymbols,separatedbycommas
. s ,fromthosedefinedinTable5.3.Theremaybenomorethanon
esymbolfromeachFfield.TheNOPsymbolisusedwhenthemi
croinstructionhasnomicrooperations.Thiswillbetranslated
bytheassemblertoninezeros.
3 CD TheCD field hasoneofthe letters U,I,S,orZ.
4 BR TheBRfieldcontainsoneofthefoursymbolsdefinedinTable5.
. 2.
5 AD TheADfieldspecifiesavaluefortheaddressfieldofthemicroin
. structionin oneof threepossibleways:
i. Withasymbolicaddress,thismustalsoappearasalab
el.
ii. WiththesymbolNEXTtodesignatethenextaddressin
sequence.
iii. WhentheBRfieldcontainsaRETorMAPsymbol,theA
Dfieldisleftemptyandisconvertedtosevenzerosbyth
eassembler.
Table4.3:SymbolicMicroinstruction
10. Draw the diagram of Micro programmed sequencer for
acontrolmemoryandexplainit.
Microprogram sequencer:
 Thebasiccomponentsofamicroprogrammedcontrolunitarethecontrolmemoryandthecircui
tsthatselectthenextaddress.
 Theaddressselectionpartiscalleda microprogramsequencer.
 Amicroprogramsequencercanbeconstructedwithdigitalfunctionstosuitaparticularapplicati
on.
 Toguarantee a widerangeof acceptability, an integratedcircuit sequencermustprovidean
internalorganizationthat canbeadaptedtoawide rangeof applications.
 Thepurposeofa microprogramsequencer isto present anaddressto the
controlmemorysothatamicroinstructionmaybereadandexecuted.
 Commercialsequencersincludewithintheunitaninternalregisterstackusedfortemporarystor
ageofaddressesduringmicroprogramloopingandsubroutinecalls.
 Somesequencersprovideanoutputregisterwhichcanfunctionastheaddressregisterfortheco
ntrolmemory.
 Theblockdiagramofthemicroprogramsequencerisshowninfigure4.6.
 Therearetwomultiplexersinthecircuit.
 Thefirstmultiplexerselectsanaddressfromoneoffoursourcesandroutesitintoacontroladdre
ssregisterCAR.
 Thesecondmultiplexerteststhevalueofaselectedstatusbitandtheresultofthetestisappliedt
oaninput logiccircuit.
 TheoutputfromCARprovidestheaddressforthecontrolmemory.
 ThecontentofCARisincrementedandappliedtooneofthemultiplexerinputsandtothesubrou
tineregistersSBR.
 Theotherthreeinputstomultiplexer1comefromtheaddressfieldofthepresentmicroinstructi
on,fromtheoutputofSBR,andfromanexternalsourcethatmapstheinstruction.
 Althoughthefigure4.6showsasinglesubroutineregister,atypicalsequencerwillhavea
registerstack aboutfour toeight levels deep.Inthisway,a numberof
subroutinescanbeactiveat thesametime.
 TheCD(condition)fieldofthemicroinstructionselectsoneofthestatusbitsinthesecondmultipl
exer.
 Ifthe bit selected isequalto 1, theT (test)variableisequalto1;otherwise,it isequal to0.
 TheTvaluetogetherwiththetwobitsfromtheBR(branch)fieldgoestoaninputlogiccircuit.
 Theinputlogicinaparticularsequencerwilldeterminethetypeofoperationsthatareavailablei
nthe unit.
l0Input 321 0
l1LogicT S1MUX 1S0 Load
S BR
Test Increment
1 MUX2
Clock CAR
L Select
ControlMemory
MicroopsCDBRAD
Figure4.6:MicroprogramSequencerforacontrolmemory
InputLogic:Truth Table
BR Input MUX1 LoadSBR
I1 I0 T S1 S0 L
00 0 0 0 0 0 0
00 0 0 1 0 1 0
01 0 1 0 0 0 0
01 0 1 1 0 1 1
10 1 0 X 1 0 0
11 1 1 X 1 1 0
Table4.4:InputLogicTruthTableforMicroprogramSequencer
Boolean
Function: S0=I0
S1= I0I1+ I0’TL
= I0’I1T
 Typicalsequenceroperationsare:increment,branchorjump,callandreturnfromsubroutine,l
oadanexternaladdress,pushorpopthestack,andotheraddresssequencingoperations.
 Withthreeinputs,thesequencercanprovideuptoeightaddresssequencingoperations.
 SomecommercialsequencershavethreeorfourinputsinadditiontotheTinputandthusprovid
eawiderrange ofoperations.
Unit5– CentralProcessingUnit
1. Whatisstack?
Givetheorganizationofregisterstackwithallnecessaryelementsa
ndexplaintheworkingofpushandpopoperations.
(Win’13,Win’14,Win’15,Sum’15)Stack organization:
 Astackisastoragedevicethatstoresinformationinsuchamannerthattheitemstoredlastisthefi
rstitemretrieved.
 Thestackindigitalcomputersisessentiallyamemoryunitwithanaddressregisterthatcancount
only.Theregisterthatholdstheaddressforthestackiscalledastackpointer(SP)becauseitsvalue
alwayspointsatthetopiteminthestack.
 Thephysicalregistersofastackarealwaysavailableforreadingorwriting.Itisthecontentofthe
word thatisinsertedordeleted.
Register stack:
Figure5.1:Blockdiagramofa64-wordstack
 Astackcanbeplacedinaportionofalargememoryoritcanbeorganizedasacollectionofafiniten
umberofmemorywordsorregisters.Figureshowstheorganizationofa64-wordregisterstack.
 ThestackpointerregisterSPcontainsabinarynumberwhosevalueisequaltotheaddressofthew
ordthatiscurrentlyontopofthestack.Threeitemsareplacedinthestack:A,B,andC,inthatorder.I
temCisontopofthestacksothatthecontentofSPisnow3.
 Toremovethetopitem,thestackispoppedbyreadingthememorywordataddress3anddecrem
entingthecontentofSP.ItemBisnowontopofthestacksinceSPholdsaddress2.
 Toinsertanewitem,thestackispushedbyincrementingSPandwritingawordinthenext-
higherlocationinthestack.
 Ina64-wordstack,thestackpointercontains6bitsbecause26=64.
 SinceSPhasonlysixbits,itcannotexceedanumbergreaterthan63(111111inbinary).When63ar
eincrementedby1,theresultis0since111111+1=1000000inbinary,butSPcanaccommodateo
nlythesixleastsignificantbits.
 Similarly,when000000isdecrementedby1,theresultis111111.Theone-
bitregisterFULLissetto1whenthestackisfull,andtheone-
bitregisterEMTYissetto1whenthestackisemptyof items.
 DRisthedataregisterthatholdsthebinarydatatobewrittenintoorreadoutofthestack.
PUSH:
 Ifthestackisnotfull(FULL=0),anewitemisinsertedwithapushoperation.Thepushoperationco
nsistsofthefollowingsequencesofmicrooperations:
SP←SP+1 Incrementstackpointer
M [SP] ← DR WRITE ITEMON TOPOFTHESTACK
IF (SP =0) then(FULL ←1) Checkisstackisfull
EMTY←0 Markthestacknotempty
 Thestackpointerisincrementedsothatitpointstotheaddressofnext-
higherword.AmemorywriteoperationinsertsthewordfromDRintothetopofthestack.
 SPholdstheaddressofthetopofthestackandthatM[SP]denotesthememorywordspecifiedbyt
headdresspresentlyavailable in SP.
 Thefirstitemstoredinthestack isataddress1. Thelastitemisstoredat address0.IfSPreaches0,
the stackisfull ofitems,soFULLis setto 1.Thiscondition is reached
ifthetopitempriortothelastpushwasinlocation63and,afterincrementingSP,thelastitemissto
redinlocation0.
 Once anitemisstoredin location 0,therearenomoreempty registersinthestack.
Ifanitemiswritteninthestack,obviouslythestackcannotbeempty,soEMTYisclearedto0.
POP:
 Anewitemisdeletedfromthestackifthestackisnotempty(ifEMTY=0).Thepopoperationconsis
tsofthefollowingsequencesofmicrooperations:
DR ←M[SP] Readitem on top of thestack

SP ←SP -1 DecrementstackpointerIF
(SP=0) then(EMTY ←1) Check ifstackis emptyFULL←0
Mark thestack not full
 The
topitemisreadfromthestackintoDR.Thestackpointeristhendecremented.Ifitsvaluereachesz
ero,thestackisempty,soEMTY issetto1.
 Thisconditionisreachedifthe item readwasin location1.
 Oncethisitemisread out,SP isdecremented andreachesthe value 0,whichisthe
initialvalueofSP.Ifapopoperationreadstheitemfromlocation0andthenSPisdecremented,SPi
schangesto111111,whichisequivalenttodecimal63.
 Inthisconfiguration,thewordinaddress0receivesthelastiteminthestack.Notealsothatanerro
neousoperationwillresultifthestackispushedwhenFULL=1orpoppedwhen EMTY=1.
2. ExplainMemoryStack. ( Win’14,Win’15)
Figure5.2:Computermemorywithprogram,data,andstacksegments
 TheimplementationofastackintheCPUisdonebyassigningaportionofmemorytoastackopera
tion andusinga processor registerasa stackpointer.
 Figure5.2showsaportionofcomputermemorypartitionedintothreesegments:program,data,
andstack.
 TheprogramcounterPCpointsattheaddressofthenextinstructionintheprogramwhichisused
duringthefetchphasetoreadaninstruction.
 TheaddressregistersARpointsatanarrayofdatawhichisusedduringtheexecutephasetoread
an operand.
 ThestackpointerSPpointsatthetopofthestackwhichisusedtopushorpopitemsintoorfromthe
stack.
 Thethreeregistersareconnectedtoacommonaddressbus,andeither
onecanprovideanaddressformemory.
 Asshown in Figure5.2, the initial valueof SP is4001andthe stackgrowswith
decreasingaddresses.Thusthefirstitemstoredinthestackisataddress4000,theseconditemiss
toredataddress3999,andthe lastaddressthatcanbeusedforthe stackis3000.
 WeassumethattheitemsinthestackcommunicatewithadataregisterDR.
PUSH
 Anewitemisinsertedwiththepushoperationasfollows:
SP ←SP -1
M[SP]←DR
 Thestackpointer isdecrementedsothat itpointsattheaddressofthenextword.
 Amemorywriteoperation insertsthe word fromDRintothetopofthestack.
POP
 Anewitem isdeleted withapopoperation asfollows:
DR ←
M[SP]SP←SP+
1
 Thetop item isreadfrom the stackintoDR.
 Thestackpointeristhenincrementedtopoint atthenextitem inthestack.
 The twomicrooperationsneededforeitherthepushorpopare(1)
anaccesstomemorythroughSP,and(2)updating SP.
 Whichofthe twomicrooperationsis donefirst
andwhetherSPisupdatedbyincrementingordecrementingdependsontheorganizationofthe
stack.
 Infigure.5.2thestackgrowsbydecreasingthememoryaddress.Thestackmaybeconstructedto
growbyincreasingthememoryalso.
 Theadvantage of amemorystackisthatthe CPUcanrefertoit withouthavingto
specifyanaddress,sincetheaddressisalwaysavailableandautomaticallyupdatedinthestackpo
inter.
3. Explainfourtypesofinstructionformats. (Sum’11,Win’13)
Three AddressInstructions:
 Computerswiththree-
addressinstructionformatscanuseeachaddressfieldtospecifyeitheraprocessorregisteroram
emoryoperand.Theprograminassemblylanguagethat evaluatesX=(A +B) * (C+D)is
shownbelow.
ADDR1,A,B R1M[A]+M[B]
ADDR2, C,D R2M[C]+M[D]
MULX,R1,R2 M[X]R1*R2
 The advantageofthree-addressformatis thatit resultsinshortprograms
whenevaluatingarithmeticexpressions.
 Thedisadvantageisthatthebinary-
codedinstructionsrequiretoomanybitstospecifythreeaddresses.
 Anexampleofacommercialcomputerthatusesthree-addressinstructionistheCyber170.
Two AddressInstructions:
 Twoaddressinstructionsarethemostcommonincommercialcomputers.Hereagaineachaddr
essfieldcanspecifyeitheraprocessorregisteroramemoryword.TheprogramtoevaluateX=(A+
B)* (C+D)isasfollows:
MOVR1,A R1M[A]
ADDR1,B R1R1+M[B]
MOVR2,C R2M[C]
ADDR2,D R2R2+M[D]
MULR1,R2 R1R1*R2
MOVX,R1 M[X] R1
 TheMOVinstructionmovesortransferstheoperandstoandfrommemoryandprocessorregiste
rs.Thefirstsymbollistedinaninstructionisassumedtobebothasourceandthedestinationwher
etheresultoftheoperationistransferred.
One AddressInstructions:
 Oneaddressinstructionsuseanimpliedaccumulator(AC)registerforalldatamanipulation.For
multiplicationanddivisiontheseisaneedfora secondregister.
 However,herewewillneglectthesecondregisterandassumethattheACcontainstheresultofall
operations.TheprogramtoevaluateX= (A+B)* (C+D)is
LOAD A ACM[A]
ADD B ACAC+M[
STORE T M[T] AC
B]
LOAD C ACM[C]
ADD D ACAC+M[
MUL T D]
ACAC*M[
STORE X T] AC
M[X]
 AlltheoperationsaredonebetweentheACregisterandamemoryoperand.Tistheaddressofthe
temporarymemorylocationrequiredforstoringtheintermediateresult.
Zero Address Instructions:
 Astack-
organizedcomputerdoesnotuseanaddressfieldfortheinstructionsADDandMUL.ThePUSHan
dPOPinstructions,however,needanaddressfieldtospecifytheoperandthatcommunicateswit
hthestack.
 TheprogramtoevaluateX=(A+B)*(C+D)willbewrittenforastack-organized
computer PUSH A TOSA
. PUSH B TOSB
ADD TOS (A+B)
PUSH C TOSB
PUSH D TOSD
ADD TOS(C +D)
MUL TOS(C +D)*(A+
POP X B) [X]TOS
M
 Toevaluatearithmeticexpressionsinastackcomputer,itisnecessarytoconverttheexpressioni
ntoreversepolishnotation.
RISCInstructions:
 AllotherinstructionsareexecutedwithintheregistersoftheCPUwithoutreferringtomemory.A
programforaRISCtypeCPUconsistsofLOADandSTOREinstructionsthathaveonememoryando
neregisteraddress,andcomputational-
typeinstructionsthathavethreeaddresseswithallthreespecifyingprocessorregisters.
 Thefollowingisaprogram toevaluateX=(A+ B)* (C+ D).
LOAD R1,A R1M[A
LOAD R1,B ]R1M[B
LOAD R1,C ]R1M[C
LOAD R1,D ]
R1M[D
ADD R1,R1,R2 ]
R1R1+
ADD R3,R3,R2 R2
R3R3+
MUL R1,R1,R3 R4
R1R1*
STORE X,R1 R3
M[X]R
 1
TheloadinstructionstransfertheoperandsfrommemorytoCPUregister.
 Addandmultiplyoperationsareexecutedwithdataintheregisterswithoutaccessingmemory.
 Theresultofthecomputationsisthenstoredinmemorywithastoreinstruction.
4. WriteanoteondifferentAddressingModes.
(Win’15, Sum’15,Win’14,Win’13)
Thegeneraladdressingmodessupportedbythecomputerprocessorareasfollows:
1) Impliedmode:
 Inthismodetheoperandsare specifiedimplicitlyin thedefinitionofthedefinitionof
theinstruction.Forexample,theinstruction“complementaccumulator”isanimplied-
modeinstructionbecausetheoperand in
theaccumulatorisanimpliedmodeinstructionbecausetheoperandintheaccumulatorregisteri
simpliedinthedefinitionoftheinstruction.
 Infactallregisterlaterregisterisimpliedinthedefinitionoftheinstruction.Infact,allregisterrefe
renceinstructionsthatuseanaccumulatorareimpliedmodeinstructions.
2) ImmediateMode:
 In this mode theoperandis specifiedin the instructionitself. In other words,animmediate-
modeinstructionhasanoperand fieldratherthan an addressfield.
 The operandfieldcontainstheactual operandto beusedin
conjunctionwiththeoperationspecifiedinthe instruction.
 Immediatemodeofinstructionsis useful forinitializingregistertoconstant value.
3) RegisterMode:
 InthismodetheoperandsareinregistersthatwithintheCPU.Theparticularregisterisselectedfr
om aregisterfieldintheinstruction.
 A k-bitfieldcanspecifyanyone of 2kregisters.
4) RegisterIndirectMode:
 InthismodetheinstructionspecifiesaregisterintheCPUwhosecontentsgivetheaddressoftheo
perandin memory.
 Beforeusingaregisterindirectmodeinstruction,theprogrammermustensurethatthememory
addressoftheoperandisplacedintheprocessorregisterwithapreviousinstruction.
 Theadvantageofthismodeisthataddressfieldoftheinstructionusesfewerbitstoselectaregiste
rthanwouldhavebeenrequiredtospecifyamemoryaddressdirectly.
5) AutoincrementorAutodecrementMode:
 Thisissimilartotheregisterindirectmodeexpectthattheregisterisincrementedordecremente
dafter(orbefore)itsvalueisusedtoaccessmemory.
 Whentheaddressstoredintheregisterreferstoa tableofdatainmemory,it
isnecessarytoincrementordecrementtheregisteraftereveryaccesstothetable.Thiscanbeach
ievedbyusingtheincrementordecrementinstruction.
6) DirectAddressMode:
 Inthismodetheeffectiveaddressisequaltotheaddresspartoftheinstruction.Theoperandresid
esinmemoryanditsaddressisgivendirectlybytheaddressfieldoftheinstruction.
7) IndirectAddressMode:
 Inthismodetheaddressfieldoftheinstructiongivestheaddresswheretheeffectiveaddressisst
oredinmemory.
 Controlfetchestheinstructionfrommemoryandusesitsaddressparttoaccessmemoryagainto
readtheeffectiveaddress.Theeffectiveaddressinthismodeisobtainedfromthefollowingcom
putational:
Effectiveaddress=addresspartofinstruction+contentofCPUregister
8) RelativeAddressMode:
 Inthismodethecontentoftheprogramcounterisaddedtotheaddressoftheinstructioninorder
toobtaintheeffectiveaddress.Theaddress
partoftheinstructionisusuallyasignednumberwhichcanbeeitherpositiveornegative.
 Whenthisnumberisaddedtothecontentoftheprogramcounter,theresultproducesaneffectiv
eaddresswhosepositioninmemoryisrelativetotheaddressofthenextinstruction.
 Relativeaddressingisoftenusedwithbranch-
typeinstructionwhenthebranchaddressisintheareasurroundingtheinstructionworditself.
9) IndexedAddressingMode:
 Inthismodethecontentofanindexregister isaddedto
theaddresspartoftheinstructiontoobtaintheeffectiveaddress.
 TheindexedregisterisaspecialCPUregisterthatcontainanindexvalue.Theaddressfieldofthein
structiondefinesthebeginningaddressofadataarrayinmemory.Eachoperandinthearrayissto
redinmemoryrelativetothebeggingaddress.
 The distancebetweenthebeginningaddressandtheaddressoftheoperandisthe
indexvaluestoredintheindexregister.
10) BaseRegisterAddressingMode:
 Inthismode thecontentof abase register isadded tothe addresspartofthe
instructiontoobtaintheeffectiveaddress.
 Abase registerisassumed to hold
abaseaddressandtheaddressfieldoftheinstructiongivesadisplacementrelativetothisbasead
dress.
 Thebaseregisteraddressingmodeisusedincomputerstofacilitatetherelocationofprogramsin
memory.
 Withabaseregister,thedisplacementvaluesofinstructiondonothavetochange.Onlythevalue
of thebaseregisterrequiresupdatingtoreflectthebeginningofanewmemorysegment.
5. ExplainDataTransferInstructions.
 Datatransferinstructions movedatafrom oneplace inthecomputer
toanotherwithoutchangingthedatacontent.
 Themostcommontransfersarebetweenmemoryandprocessorregisters,betweenprocessorr
egistersandinputoroutput,andbetweentheprocessorregistersthemselves.
 Theloadinstructionhasbeenusedmostlytodesignateatransferfrommemorytoaprocessorreg
ister,usuallyanaccumulator.
 Thestoreinstructiondesignatesatransferfromaprocessorregisterintomemory.
 ThemoveinstructionhasbeenusedincomputerswithmultipleCPUregisterstodesignateatrans
ferfromoneregistertoanother.IthasalsobeenusedfordatatransfersbetweenCPUregistersan
dmemoryorbetweentwomemorywords.
 Theexchangeinstructionswapsinformationbetweentworegistersoraregisterandamemoryw
ord.
 Theinputandoutputinstructionstransferdataamongprocessorregistersandinputoroutputte
rminals.
 Thepushandpopinstructionstransferdatabetweenprocessorregistersandamemorystack.
6. ExplainArithmeticinstructions.
Name Mnemonic
Increment INC
Decrement DEC
Add ADD
Subtract SUB
Multiply MUL
Divide DIV
Addwith carry ADDC
Subtractwith borrow SUBB
Negate(2'scomplement) NEG
7. ExplainLogicalinstructions.
Name Mnemonic
Clear CLR
Complement COM
AND AND
OR OR
Exclusive-OR XOR
Clearcarry CLRC
Setcarry SETC
Complementcarry COMC
Enable interrupt EI
Disableinterrupt DI
8. Explainshiftinstructions.
Name Mnemonic
Logicalshiftright SHR
Logicalshiftleft SHL
Arithmeticshiftright SHR A
Arithmeticshiftleft SHLA
Rotate right ROR
Rotate left ROL
Rotate rightthrough carry RORC
Rotate leftthrough carry ROLC
9. Whatarestatus registerbits? Draw and explaintheblock
diagramshowingallstatusregisters.(Win’13)
 ItissometimesconvenienttosupplementtheALUcircuitintheCPUwithastatusregisterwherest
atusbitconditionsbestoredforfurtheranalysis.Statusbitsarealsocalledcondition-
codebitsorflagbits.
 Figure5.3showstheblockdiagramofan8-bitALUwitha4-
bitstatusregister.ThefourstatusbitsaresymbolizedbyC,S,Z,andV.Thebitsaresetorclearedasa
resultofanoperationperformedintheALU.
Figure5.3:StatusRegisterBits
1. Bit C(carry)issetto1ifthe endcarryC8is1.Itisclearedto0ifthecarry is0.

2. BitS(sign)issetto1ifthehighest-orderbitF7is1.Itissetto0ifsetto0ifthebit is0.
3. BitZ(zero)issetto1iftheoutputoftheALUcontainsall0’s.itisclearedto0otherwise.Inot
herwords,Z=1iftheoutputiszeroandZ=0iftheoutputisnotzero.
4. BitV(overflow) issetto1if theexclusives-OR ofthelast
twocarriesisequalto1,andclearedto0otherwise.Thisistheconditionforanoverfloww
hennegativenumbersarein2’scomplement.Forthe8-
bitALU,V=1iftheoutputisgreaterthan+127orlessthan-128.
 Thestatus bits canbe
checkedafteranALUoperationtodeterminecertainrelationshipsthatexistbetweenthe
valesofA andB.
 Ifbit Vis set aftertheaddition oftwo signednumbers,it indicates anoverflowcondition.
 IfZissetafteranexclusive-ORoperation, it indicatesthat A=B.
 AsinglebitinAcanbecheckedtodetermineifitis0or1bymaskingallbitsexceptthebit inquestion
andthencheckingthe Zstatusbit.
10. Whatisprograminterrupt?Whathappenswhenitcomes?
Whatarethetaskstobeperformedbyserviceroutine?
OR
ExplainProgramInterrupts.Explainclearly,discussingtheroleofst
ack,PSWandreturnfrominterruptinstruction,howinterruptsarei
mplementedoncomputers.
 Theconceptofprograminterruptisusedtohandleavarietyofproblemsthatariseoutofnormalprogr
amsequence.
 Programinterruptreferstothetransferofprogramcontrolfromacurrentlyrunningprogram
toanother service program asa resultof anexternal
orinternalgeneratedrequest.Controlreturnstotheoriginalprogramaftertheserviceprogramisexe
cuted.
 Afteraprogramhasbeeninterruptedandtheserviceroutinebeenexecuted,theCPUmustreturntoe
xactlythe same statethat it waswhentheinterruptoccurred.
 Only ifthishappenswilltheinterrupted programbeable toresumeexactly asifnothing
hadhappened.
 ThestateoftheCPUattheendoftheexecutecycle(whentheinterruptisrecognized)isdeterminedfr
om:
1. Thecontentoftheprogramcounter
2. Thecontentofallprocessorregisters
3. Thecontentofcertainstatusconditions
 Theinterruptfacilityallowstherunningprogramtoproceeduntil
theinputoroutputdevicesetsitsreadyflag.Wheneveraflagissetto1,thecomputercompletestheex
ecutionoftheinstructioninprogressandthenacknowledgestheinterrupt.
 Theresultofthisactionisthattheretuneaddressisstaredinlocation0.Theinstructioninlocation1ist
henperformed;thisinitiatesaserviceroutinefortheinputoroutputtransfer.Theserviceroutine can
bestoredinlocation 1.
 Theserviceroutinemusthaveinstructionstoperformthefollowingtasks:
1. Savecontentsofprocessorregisters.
2. Checkwhichflagisset.
3. Servicethedevicewhoseflagisset.
4. Restorecontentsofprocessorregisters.
5. Turnthe interruptfacilityon.
6. Returntotherunningprogram.
11. Explainvarioustypesofinterrupts.
Therearethreemajortypesofinterruptsthatcauseabreakinthenormalexecutionofaprogram.Theyca
nbeclassifiedas:
1. Externalinterrupts
2. Internalinterrupts
3. Softwareinterrupts
1) Externalinterrupts:
 Externalinterruptscomefrominput-
output(I/0)devices,fromatimingdevice,fromacircuitmonitoringthepowersupply,orfromanyoth
erexternalsource.
 Examplesthatcauseexternalinterrupts areI/0devicerequesting
transferofdata,I/odevicefinishedtransferofdata,elapsedtimeofanevent,orpowerfailure.Timeou
tinterruptmayresultfromaprogramthat isinan endlessloopandthusexceededitstimeallocation.
 Powerfailureinterruptmayhaveasitsserviceroutineaprogramthattransfersthecompletestateoft
heCPUintoanondestructivememoryinthefewmillisecondsbeforepowerceases.
 Externalinterruptsareasynchronous.
Externalinterruptsdependonexternalconditionsthatareindependentoftheprogrambeingexecut
edatthetime.
2) Internalinterrupts:
 Internalinterruptsarisefromillegalorerroneoususeofaninstructionordata.Internalinterruptsare
alsocalledtraps.
 Examplesofinterruptscausedbyinternalerrorconditionsareregisteroverflow,attempttodivideby
zero,aninvalidoperationcode,stackoverflow,andprotectionviolation.Theseerrorconditionsusua
llyoccurasaresultofaprematureterminationoftheinstructionexecution.Theserviceprogramthat
processestheinternalinterruptdeterminesthecorrectivemeasuretobetaken.
 Internalinterruptsaresynchronouswiththeprogram..Iftheprogramisrerun,theinternalinterrupts
willoccurinthe sameplaceeachtime.
3) Softwareinterrupts:
 Asoftwareinterruptisaspecialcallinstructionthatbehaveslikeaninterruptratherthanasubroutine
call.Itcanbeusedbytheprogrammertoinitiateaninterruptprocedureatanydesiredpointinthepro
gram.
 Themostcommonuseofsoftwareinterruptisassociatedwithasupervisorcallinstruction.Thisinstru
ctionprovidesmeansforswitching fromaCPU usermodeto the supervisor
mode.Certainoperationsinthecomputermaybeassignedtothesupervisormodeonly,asforexamp
le,acomplexinputoroutputtransferprocedure.Aprogramwrittenbyausermustrunin
theusermode.
 Whenaninputoroutputtransferisrequired,thesupervisormodeisrequestedbymeansofasupervis
orcallinstruction.ThisinstructioncausesasoftwareinterruptthatstorestheoldCPUstateandbrings
inanewPSWthatbelongsto the supervisor mode.
 Thecallingprogrammustpassinformationtotheoperatingsysteminordertospecifytheparticulart
askrequested.
12. What do you understand by Reduced Instruction

SetComputers?WhatareComplexInstructionSetComputers?
ListimportantcharacteristicsofCISCandRISCcomputers.Alsoinata
bular form compare their relative advantages
/disadvantages.
(Win’15,Sum’15,Win’14,Win’13)CharacteristicsofRISC:
1. Relativelyfewinstructions
2. Relativelyfewaddressingmodes
3. Memoryaccesslimitedtoloadandstoreinstructions
4. Alloperationsdone within theregistersoftheCPU
5. Fixed-length,easilydecodedinstructionformat
6. Single-cycleinstructionexecution
7. Hardwiredratherthanmicroprogrammedcontrol
8. Arelativelylargenumberofregistersin theprocessorunit
9. Useofoverlappedregisterwindowstospeed-upprocedurecallandreturn
10. Efficientinstructionpipeline
11. Compilersupportforefficienttranslationofhigh-
levellanguageprogramsintomachinelanguageprograms
CharacteristicsofCISC:
1. Alargernumberofinstructions –typicallyfrom100to250instructions
2. Someinstructionsthatperformspecializedtasksandareusedinfrequently
3. Alargevarietyofaddressingmodes–typicallyfrom5to20differentmodes
4. Variable-lengthinstructionformats
5. Instructionsthatmanipulateoperandsinmemory
13. Whatisoverlappedregisterwindow?
Howthewindowsizeandregisterfilesizeiscalculated? (Win’13)
 AcharacteristicofsomeRISCprocessorsistheiruseofoverlappedregisterwindowstoprovideth
epassingofparametersandavoidtheneedforsavingandrestoringregistervalues.Eachprocedu
recallresultsintheallocationofanewwindowconsistingofasetofregistersfromtheregisterfilef
orusebythenewprocedure.
Figure5.4:OverlappedRegisterWindows
 Eachprocedurecallactivatesanewregisterwindowbyincrementingapointer,whilethereturn
statementdecrementsthepointerandcausestheactivationofthepreviouswindow.Windows
foradjacentprocedureshaveoverlappingregistersthataresharedtoprovidethepassingofpar
ametersandresults.
 Theconcept of overladeregisterwindowsisshown infigure.Thesystemhad atotal
of74registers.RegisterR0throughR9areglobalregistersthatholdparameterssharedbyallpr
ocedures
 Theother64
registersaredividedintofourwindowstoaccommodateprocedureA,B,CandD.Eachregister
windowconsistsof10local registersandtwo
setsofsixregisterscommontoadjacentwindows.
 Onlyoneregisterwindowisactivated at
anygiventimewithapointerindicatingtheactivewindow.
 Thehighregisterofthecallingprocedureoverlapthelowregistersofthecalledprocedure,an
dthereforetheparametersautomaticallytransferfromcallingtocalledprocedure.
 Theorganizationofregisterwindowswillhavethe
followingrelationships:Numberof globalregisters=G
Number of localregistersin eachwindow=LNumberof
registercommontotwo windows=CNumberof
windows=W
 Thenumberofregistersavailable foreachwindowiscalculatedas follows:
Window size =L+2C + G
 Thetotalnumberofregisterneededintheprocessoris
Registerfile =(L+ C)W+G
14. Explain Reverse Polish Notation (RPN) with

appropriateexample.
 The postfixRPNnotation,referredto as ReversePolishNotation(RPN),places
theoperatoraftertheoperands.
 Thefollowingexamplesdemonstratethethreerepresentations:
A+B Infix notation
+AB PrefixorPolishnotation
AB+ PostfixorreversePolishnotation
 ThereversePolishnotationisinaformsuitableforstackmanipulation.Theex
pression
A * B+C*D iswritteninreversePolishnotationasA
B* CD *+
 TheconversionfrominfixnotationtoreversePolishnotationmusttakeintoconsiderationtheop
erationalhierarchyadoptedforinfixnotation.
 This hierarchy dictates thatwefirstperformallarithmeticinsideinnerparentheses,
theninsideouterparentheses,anddomultiplicationanddivisionoperationsbeforeadditionan
dsubtractionoperations.
EvaluationofArithmeticExpressions
 Anyarithmeticexpressioncanbeexpressedinparenthesis-
freePolishnotation,includingreversePolishnotation
(3 *4)+(5 *6)  34 *5 6* +
Unit6–PipelineandVectorProcessing
1. ExplainFlynn’sclassificationforcomputers. (Win’15)
Flynn'sclassification
 Itisbasedonthemultiplicityof InstructionStreamsandData Streams
InstructionStream
Sequenceof Instructionsreadfrommemory
DataStream
Operationsperformedonthedataintheprocessor
Figure6.1:Flynn’sClassification
SISD:
 Singleinstructionstream,singledatastream.
 SISDrepresentstheorganizationofa singlecomputercontaininga
controlunit,aprocessorunit, anda memoryunit.
 Instructionsareexecutedsequentiallyandthesystemmayormaynothaveinternalparallelproc
essing capabilities.
SIMD Figure6.2:SISDOrganization
:
 SIMDrepresentsan organizationthatincludesmany processingunitsunderthesupervision of
acommoncontrolunit.
 All processorsreceivethe
sameinstructionfromthecontrolunitbutoperateondifferentitemsof data.

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 The most commonwaytorepresent aregister isbyarectangularbox

Figure1.2:TransferfromR1to R2when P=1

Symbol Description Examples

4x1 4x1 4x 1 4x1

MUX 3 MUX 2 MUX 1 MUX 0

D2C2 B2 A2 D1C1 B1 A1 D0C0 B0 A0

RegisterD RegisterC RegisterB RegisterA

 Thetwo selectionlines S1and S0areconnected to the selection inputsofall

 WhenS1S0= 00,the0datainputsof all fourmultiplexersare

(ii) What sizeofmultiplexersisneeded?

 Theoutputsoffourbuffersareconnected togetherto form asinglebusline.

R3 R1+R2 ContentsofR1plusR2transferredtoR3

R2 R2’ ComplementthecontentsofR2

Select In Output Microoperation

If Cin=1, D=A+B̅+1;A+2’s compliment of B i.e. A-B

Boole Microoperation Name

 Again thetwoleftmostbits ofB are 1's, sothe correspondingbitsofA arecomplemented.

 Againthetwo leftmostbitsofBare1's, so thecorrespondingbitsofAareclearedto0.

 Theoutputscarry Ci+1ofa given arithmeticstagemustbeconnectedtotheinput

2. Explain Complement number system in detail

3. Explain Subtraction of Unsigned Numbers in

Answer: X –Y= 0010001

 Notethatthe8-bitresultthat shouldhave beenpositivehasanegativesign bit andthe8-

4. Draw and explainCommonBus

The process ofinputinformation transfer:

The process ofoutputtinginformation:

Symbol Information forthe Assembler

First Pass ofan assembler

5. Explain the working of Second Pass Assembler with

Set first Set first

8. Write an assembly language program to Add two

11. Writeanassembly languageprogram to takea character

3. Draw and explain the organization of micro

 Thebranchlogicof figure4.2providesdecision-makingcapabilitiesinthe controlunit.

DR ←M[SP] Readitem on top of thestack

1. Bit C(carry)issetto1ifthe endcarryC8is1.Itisclearedto0ifthecarry is0.

12. What do you understand by Reduced Instruction

14. Explain Reverse Polish Notation (RPN) with

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