J Sign Process Syst (2016) 85:341–353

DOI 10.1007/s11265-015-1054-9

HARP2: An X-Scale Reconfigurable Accelerator-Rich

Platform for Massively-Parallel Signal Processing
Algorithms
Waqar Hussain1 · Roberto Airoldi1 · Henry Hoffmann2 · Tapani Ahonen1 ·
Jari Nurmi1

Received: 12 December 2014 / Revised: 23 June 2015 / Accepted: 21 September 2015 / Published online: 17 October 2015
© Springer Science+Business Media New York 2015

Abstract This paper presents design, development and
evaluation of an eXtra-large Scale, Homogeneous and a Het-
erogeneous Accelerator-Rich Platform (HARP2 ) for mas-
sively parallel signal processing algorithms. HARP is an
integrated platform of multiple Coarse-Grained Reconfig-
urable Arrays (CGRAs) over a Network-on-Chip (NoC)
where each CGRA is scaled and tailored for a specific
application. The architecture of the NoC consists of nine
nodes in a topology of 3-rows×3-columns and acts as back-
bone of communication between different CGRAs. In this
experimental work, the HARP template is used to instan-
tiate a homogeneous (HARP-hom) and a heterogeneous
(HARP-het) platform. The HARP-het is generated for a
proof-of-concept test to verify the design and functional-
ity of HARP. It also provides insight to many features of
the design and evaluation in terms of different performance
metrics. The other version (HARP-hom) is instantiated for
a relatively realistic design problem, i.e., satisfying the
execution-time constraints imposed on Fast Fourier Trans-
form processing in IEEE-802.11n demodulators. Both of the
versions of HARP are treated for comparative analysis using
different performance metrics against some of the existing
state-of-the-art platforms. The HARP versions are designed
to illustrate large-scale homogeneous/heterogeneous multi-
core architectures while presenting the advantages of max-
imizing the number of reconfigurable processing resources
on a single chip.
Keywords Reconfigurable · CGRA · Network-on-Chip ·
Heterogeneous · Homogeneous · Accelerator-Rich ·
Multicore

1 Introduction
 Waqar Hussain
waqar.hussain@tut.fi Today’s challenges for computing are of much larger scale
than in the past and, on the other hand, the demand in per-
Roberto Airoldi
roberto.airoldi@tut.fi
formance is constrained by many factors. In single core
platforms, the performance increase was achieved using
Henry Hoffmann
hankhoffmann@cs.uchicago.edu technology scaling over several years. This trend eventu-
ally ended due to increasing power density; a solution was
Tapani Ahonen
tapani.ahonen@tut.fi
found in multicore systems and multicore scaling proved
to yield reasonable performance advantages. The scaling
Jari Nurmi
in multicore systems could not sustain longer and suffered
jari.nurmi@tut.fi
limitations by some constraints. In reference [1], one of
1 Department of Electronics and Communications Engineering, the constraints is mentioned as ’utilization-wall’. It states
Tampere University of Technology, P.O. Box 527, FI-33101 that under a fixed power budget of a homogeneous multi-
Tampere, Finland core platform, all the cores on a chip cannot be operated
2
at their maximum frequency due to the limiting factor of
Department of Computer Science, The University
of Chicago, Ryerson Hall 250, 1100 E. 58th Street,
power density. This limiting factor imposing the utilization-
Chicago, IL 60637, USA wall gave rise to Dark Silicon, i.e., the silicon on the chip
342
that is dark (switched off) or dim (operated at very low fre-
quency). One way of dealing with the issue of Dark Silicon
is to replace the dark and dim part of the chip with special-
purpose accelerators that can operate at very low frequency
but can yield very high performance levels. In this context,
critical-priority applications can be selected for the design
of application-specific accelerators and then replacing the
under-utilized part of the chip.
In this paper, the focus is on the design of Hetero-
geneous Accelerator-Rich Platforms (HARP) to deal with
the issue of dark silicon. A VHDL template of HARP
is designed and two instances HARP-hom and HARP-het
are generated from the template that are the homogeneous
and heterogeneous versions of the platform, respectively.
The version HARP-het is a 408 reconfigurable Processing
Elements (rPEs) instance generated for a proof-of-concept
test-case. The test-case is only to verify the functionality
of the design and evaluate it for different performance met-
rics. The other instance HARP-hom is a relatively realistic
design made to satisfy the execution-time constraints of
IEEE-802.11n standard for Fast Fourier Transform (FFT)
[16] processing. The HARP-hom version is designed by
instantiating a total of 256 rPEs. The communication infras-
tructure used in the design of HARP2 is a Network-on-Chip
(NoC) of nine nodes arranged in the geometrical order of
three rows and three columns. The central node of the NoC
is the master node which contains a Reduced Instruction-
Set Computing (RISC) processor while the rest of the
nodes are the slave nodes containing an application-specific
Coarse-Grained Reconfigurable Array (CGRA) and a Direct
Memory Access (DMA) device. The CGRAs used for inte-
gration with NoC are of application-specific dimensions and
act as an accelerating engine on the slave node.
CGRAs are a powerful solution both in industrial and
academic research. They have a proven track-record of pro-
cessing massively parallel signal processing applications.
Some of the example of general-purpose CGRAs are BUT-
TER [2], MorphoSys [3], ADRES [4] and PACT-XPP [5].
On the other side, CREMA [6], AVATAR [7] and SCREMA
[8] are template-based CGRAs which can be crafted to
application specifications. HARP is made by integrating
template-based CGRAs over its nodes. In the recent past,
the accelerator architectures were made tightly coupled typ-
ically with a general-purpose RISC processor, therefore the
resources of the accelerator were dedicated only to the cou-
pled processor. In loose coupling, the resources among the
multiple cores can be shared for the purpose of computa-
tion and communication. The tight coupling was achieved
using a Direct Memory Access (DMA) device or by directly
integrating the CGRA in the datapath of the RISC proces-
sor. Examples of tightly coupled CGRA architectures are
well presented in [9, 10] and [11]. The advantage of tight
coupling is a faster communication channel between the
J Sign Process Syst (2016) 85:341–353
CGRAs and the RISC processor. The disadvantage can be in
case of multicore systems, where multiples CGRAs cannot
access each other’s resources. The loose coupling eventu-
ally results in a lower bandwidth for communication but
allows multiple CGRAs to access each other computational
and memory resources. An example of such communica-
tion infrastructure is an NoC. The drawback of bandwidth
can be overcome if the data is transfered to all the nodes
simultaneously.
This paper presents the advantages of using the loosely
coupled architecture of HARP and motivates to maximize
the number of rPEs on a system-on-chip. The HARP-het
is designed by placing seven heterogeneous accelerators
around a RISC core which is connected to the central node
while the HARP-hom is made by using four homogeneous
accelerators integrated around the same RISC core. The key
benefits of using HARP are as follows.
1. The number of rPEs are maximized to enhance the
digital signal processing capacity of the platform. Fur-
thermore, the scalable CGRAs composed of rPEs are
integrated over an NoC such that they are loosely
coupled and capable to share each other’s resources.
2. The RISC can establish centralized and allow dis-
tributed supervisory control between all the processing
cores for independent and simultaneous execution of
multiple kernels over the platform. The control mech-
anism is based on a message passing scheme over the
NoC.
This paper is organized as follows. Section 2 presents
state-of-the-art platforms related to HARP2 . Section 3
explains the architecture of CGRAs used for integration in
HARP2 , i.e., CREMA, AVATAR and SCREMA. The next
section presents the architecture of HARP2 that includes
the internal structure of master/slave nodes of the NoC
and synchronization between nodes as well as the overall
functionality. Section 5 presents measurements and estima-
tions of different performance metrics related to HARP2
when prototyped for a Field Programmable Gate Array
(FPGA) device. Evaluation and Comparisons are presented
in Section 6 based on the measured and estimated perfor-
mance metrics. Finally, in the last section, conclusions are
presented.
2 Related Work
One of the motivations of HARP2 is to provide a platform
which can be finely tailored in hardware to the computa-
tional needs of the application. Similar features can also be
found in many other state-of-the-art platforms. For exam-
ple, a system presented in [15] is a heterogeneous platform
designed to match hardware granularity with application’s
granularity.
J Sign Process Syst (2016) 85:341–353
NineSilica is a homogeneous Multi-Processor System-
on-Chip (MPSoC) platform built over an NoC of nine nodes
arranged in a geometrical grid of three rows and three
columns. Each node of NoC is integrated with a RISC
processor that acts a computational engine. Many signal
processing related algorithms have been mapped on Nine-
Silica, e.g., FFT and Correlations. In one of the cases,
NineSilica is reported to process a 64-point of FFT within
10.3 μs [22] on a 40 nm FPGA device.
In reference [24], several general-purpose microproces-
sors are integrated in a Multiple-Instruction Multiple-Data
(MIMD) fashion. Based on user specification, additional
accelerators can also be integrated with the microproces-
sor. The exchange of data between the microprocessors
and the accelerators is supported by two separate networks.
The overall system shows a performance of 19.2 Giga
Operations per Second (GOPS) on a 90 nm FPGA device.
The platform P2012 is a homogeneous MPSoC made up
of four clusters where each cluster contains sixteen general-
purpose microprocessors. The overall platform communi-
cates over an NoC. The processors within the cluster are
locally synchronous but globally asynchronous with proces-
sors in other clusters. The platform successfully performs
image processing related algorithms and delivers a perfor-
mance of 80 GOPS on a 28 nm technology [26].
The DREAM is an example of a mid-grain (granular-
ity ≤ 8 bits) DSP processor which contains a dynamically
reconfigurable datapath unit. It is capable to deliver a
performance of 0.2 GOPS/mW using a 90 nm CMOS tech-
nology. It was later integrated into MORPHEUS platform
[27] as it is suitable to be integrated in a heterogeneous
platform. Besides DREAM, MORPHEUS has a fine-grain
platform named FlexEOS and a CGRA called XPP-III. The
overall MORPHEUS chip has an average dynamic power
dissipation of 700 mW while yielding a performance of
0.02 GOPS/mW.
The platforms presented in [22, 24] and [26] are exam-
ples of loosely-coupled architectures. The design of HARP2
contains more number of processing resources in compar-
ison to the above mentioned platforms, therefore yielding
high performance levels. In Section 6, both of the versions
of HARP are treated for a detailed comparative analy-
sis against these state-of-the-art platforms using different
performance metrics.
3 Coarse-Grained Reconfigurable Arrays
As discussed earlier in Section 1, the CGRA templates used
to instantiate accelerators to be placed around the supervi-
sor node of NoC are CREMA, AVATAR and SCREMA. All
of these three CGRAs belong to the same family and there-
fore contain similar architectural characteristics. The unit of
343
OPERAND 1 OPERAND 2
REGISTER REGISTER
OPERAND 2
DECODER
MUX
OUT 2
To FEs
LUT + X SHIFTER
FP LOGIC
IMMEDIATE
REGISTER
OUTPUT MUX
Figure 1 The internal architecture of a rPE.
computation in all of the three CGRAs is a rPE, depicted in
Fig. 1. It contains a 32-bit Arithmetic and Logic Unit (ALU)
capable of performing both integer and floating-point oper-
ations in IEEE-754 format. Each rPE has two inputs (a,
b) and two outputs (A, B). The operands to be processed
by the ALU inside are received at the two inputs of rPE
and stored in the internal operand registers. The output A
receives the result of the operation performed by the ALU
while the output B receives the operand from the operand
register of input b. In this way, the operand at input b can
be supplied to the neighboring rPEs for any required opera-
tion of the target application. Each rPE constituting a CGRA
has local and global interconnections. The local intercon-
nections are for exchanging data with the neighboring PEs
while the global interconnections are used for exchanging
data with the rPEs that are relatively distant in space. The
CGRA is equipped with two local data memories and data
to be processed can be stored in any of them. The number
of banks in the local memory are fixed and has to be equal
to the total number of rPE inputs available in any row of
the CGRA. In between the local memories and the CGRA,
there are I/O buffers available to provide maximum inter-
leaving to the data for exchange between the CGRA and the
local memories. During the system start-up time, the con-
figuration stream and data to be processed are loaded in the
CGRA. The data to be processed is loaded by the DMA [19]
device in the local data memory of the CGRA. Each rPE has
its own configuration memory so the configuration stream is
injected by the DMA device using the pipelined infrastruc-
ture [20]. Once the loading of the data and the distribution of
configuration stream is complete, the CGRA can start pro-
cessing by enabling different contexts. During the process
344
First
Local Memory
Banks
I/O Buffer
Local
Interconnections
rPE rPE rPE
rPE rPE rPE
rPE rPE rPE
I/O Buffer
Second
Local Memory
Banks
Figure 2 A combined view of CREMA, AVATAR and SCREMA. The figure shows Local and Global Interconnections, I/O Buffers and the
Local Data Memories. The rPEs in black color are the reference rPEs to depict the Interconnections.
of context enabling, the RISC core also sends cycle-accurate
information to the CGRA control unit i.e., read cycles, write
cycles, stall cycles and local memory offsets. A context can
be defined as a pattern of interconnections between dif-
ferent processing elements and the set of operations to be
performed by the processing elements in a CGRA. The con-
texts are made using a custom graphical user-interface tool
at the system design time. The design of contexts are based
on the execution-time requirements of a certain application
and performance capabilities of the CGRA. The CGRA are
run-time reconfigurable as a new configuration stream can
be loaded during the processing of an application using the
DMA device.
CREMA is a 4-rows×8-columns rPE template-based
CGRA. The number of rows can be increased to fit the
requirements of a certain application. For example, in [21],
CREMA template was used to generate a 9×8 rPE radix-4
FFT accelerator. AVATAR is a 4×16 rPE CGRA template
(twice the size of CREMA) and was used to generate a
mixed-radix(2, 4) FFT accelerator to process 64 and 128-
point of FFT algorithms. SCREMA is a scalable version of
CREMA and it could flex to sizes of 4×4, 4×8, 4×16 and
4×32 rPEs as presented in [8]. Figure 2 shows the combined
view of all of these CGRA templates.
J Sign Process Syst (2016) 85:341–353
Global
Interconnections
rPE rPE rPE
rPE rPE rPE
rPE rPE rPE
4 Homogeneous/Heterogeneous Accelerator-Rich
Platform
As described earlier, HARP2 is a template of nine nodes
arranged in a geometrical order of three rows and three
columns. The central node acts as a supervisor node and rest
of the nodes act as slaves. Since it is a template-based archi-
tecture, it depends on the user to integrate a CGRA with a
particular node or leave it only as a data routing resource.
The user can instantiate HARP2 as heterogeneous platform
by integrating application-specific CGRA generated accel-
erators for different applications or can also instantiate it
as a homogeneous platform using accelerators designed for
similar applications. In this paper, HARP2 is instantiated
both as a homogeneous and heterogeneous architecture for a
detailed analysis. As a heterogeneous architecture, HARP2
was instantiated with seven different CGRAs for a proof-
of-concept test to verify the functionality and present the
design features in detail. This instance presents 408 rPEs in
total. HARP2 is also instantiated as homogeneous platform
with four CGRA of the same type and size with a maxi-
mum of 256 rPEs. The homogeneous platform is motivated
by satisfying the demanding FFT execution-time require-
ments of IEEE-802.11x standard. Figure 3 shows HARP2
J Sign Process Syst (2016) 85:341–353 345

4x8 PE

DMA
9x8 PE DMA DMA 4x16 PE
N0 N1 N2

4x4 PE DMA N3 N4 N5 DMA 4x8 PE

RISC
4x16 PE 4x32 PE
N6 N7 N8
DMA DMA

(a) HARP-het: 408-rPE Heterogeneous Accelerator-Rich Platform.

4x16 PE 4x16 PE

DMA DMA
N0 N1 N2

N3 N4 N5
RISC
4x16 PE 4x16 PE
N6 N7 N8
DMA DMA

(b) HARP-hom: 256-rPE Homogeneous Accelerator-Rich Platform.

Figure 3 Homogeneous/Heterogeneous Accelerator-Rich Platform Template. In the figure, the black colored N4 is the supervisor node, while
rest of the nodes are slave.

architecture for both homogeneous and heterogeneous
instances. In both of the figures, it can be observed that
the nodes which are not integrated with any CGRA are
not eliminated from the design in order to provide max-
imum available routing paths for data and configuration
transfer.
4.1 Processing Nodes and Synchronization
The central node of the HARP2 establishes the supervisory
control over the slave nodes. Each slave node contains a
data memory, a DMA device and a CGRA (optional). The
data transfer between the supervisor node’s data memory
and slave node’s data memory are inherently synchronized
as they are operated by the same clock as well as the NoC.
In this case, the data transfer between two nodes is one
word per clock cycle after a fixed latency of one clock cycle
per node encountered on the routing path. During the sys-
tem startup time, the supervisor node of the NoC containing
the RISC processor can send the configuration stream and
the data to be processed to the slave node’s data memory.
The data and configuration are transfered in form of pack-
ets, where the most significant part of the packet contains
the routing information while the rest of the packet contains
the data/configuration word. The packet passes through a
switch before being loaded onto the network where the
transport route is selected in east, west, north or south direc-
tion. The switch provides the supervisor node N4 and rest
of the slave nodes with variable routing possibilities. After
this process, the DMA device in the slave nodes can load the
346
RISC
-------------------- From NoC
DMA Master
Master Interface Initiator
Request Switch Arbiter Response Switch
Slave Interface -1 Slave Interface -2 Target
Instruction Memory Data
------------------------- Memory To NoC
DMA Slave
Figure 4 An overview of the Supervisor and Slave nodes of NoC.
In this figure, the RISC and Instruction Memory are shown for the
Supervisor node and the DMA for the Slave nodes.
configuration stream and the data in the respective local
memories of the CGRA. In this context, the DMA is acti-
vated by a control word sent by the RISC core in the
supervisor node. The loading and distribution of config-
uration stream and the data by the DMA needs several
cycles and during this time period, the RISC should not
send another control word to the DMA unless the previ-
ous data transfer task has been completed. Furthermore,
the RISC can utilize this time to carry out operations in
other nodes as well. To ensure this, synchronization needs
to be established between the supervisor and slave nodes.
The supervisor node establishes synchronization by allocat-
ing a shared memory space in its local data memory. The
size of the shared memory space is of eight words as there
are eight slave nodes. Before activating the DMA transfer
of a particular node, the RISC processor writes ’1’ in the
corresponding shared memory location. As the DMA com-
pletes the internal data transfer, it writes a ’0’ over the NoC
destined towards its corresponding shared memory location
in the data memory of supervisor node. This process syn-
chronizes the data transfers as the RISC waits and keeps a
check on this particular memory location and does not send
another activation control word to the same node’s DMA in
order to keep the sequence of data transfers.
When the configuration stream and the data to be pro-
cessed are received by the slave nodes and the slave node’s
internal data transfer is also completed by the DMA device,
the RISC can start sending the control words to the CGRAs
in all the slave nodes for cycle accurate processing. The user
can program the instance of HARP2 in different schemes.
The CGRAs can work simultaneously and independent of
J Sign Process Syst (2016) 85:341–353
each other unless the user implements specific data depen-
dencies in the program flow. In this way, the CGRA nodes
(slave) can exchange data with each other as well as with
the central supervisor node. The computational resources
of the CGRA are then allocated by the supervisor node to
process on the transferred data. Section 4.2 further explains
the mechanism of sharing computational resources. The
user can apply different execution and data transfer pro-
gramming schemes based on processing requirements of the
application.
The node of NoC has one master and two slave inter-
faces. The master interface can write to the network and
can also perform data transfer within the node. In case of
the supervisor node (N4), the two slave devices are the data
memory and instruction memory. The RISC is integrated to
the master interface of the node. In the rest of the nodes,
the slave interfaces of the nodes are integrated to the local
data memory and the slave part of the DMA device. The
master interface of the slave node is connected to the mas-
ter side of the DMA device. A node is contacted through
its initiator module and then the node’s arbiter sequences
between the request and response switch to establish con-
nection between different modules. The data is written
to the network through the target module. The combined
view of the NoC’s master and the slave node is shown in
Fig. 4.
4.2 Application Mapping
As mentioned earlier, the instantiation and application
mapping on HARP-het version is only for the proof-of-
concept and to demonstrate the technical capabilities of
the HARP2 template. The HARP-hom version is designed
for the processing of multiple FFT streams while consid-
ering execution time constraints of IEEE-802.11x standard.
Table 1 shows the type of the CGRA used to generate an
application-specific accelerator and the kernels mapped on
them for both of the versions of HARP.
One of the motivations behind the design of HARP2 is
to allow all the cores to share each other’s computational
and memory resources. It allows for multiple algorithms to
run concurrently and the cores can exchange the results with
each other. Furthermore if a core lacks computational and
memory resources to process an application, it can send part
of the data to other cores and then can receive back the
results as the processing completes. This is demonstrated
in the HARP-het version as the 9×8 rPE CGRA integrated
with node N0 computes a 64-point of FFT in a radix-4
scheme on the vector received from node N4. As the com-
putation completes, the DMA device of N0 transfers the
results to the data memory of node N1. The node N1 then
performs a 64-point complex Matrix-Vector Multiplication
(MVM) on the vector received from node N0. As soon as
J Sign Process Syst (2016) 85:341–353 347

Table 1 Sizes in terms of the number of rPEs in order of rows×columns for different CGRAs connected to nodes of HARP-het and -hom
instances, and the kernels accelerated on them, respectively.

Node rPEs CGRA Type Kernel

HARP-het-N0 8×9 CREMA radix-4

64-point FFT
HARP-het-N1 4×8 CREMA complex MVM
64th -order
HARP-het-N2 4×16 AVATAR radix-(2, 4)
128-point FFT
HARP-het-N3 4×4
HARP-het-N5 4×8 SCREMA real MVM
HARP-het-N6 4×16 32nd -order
HARP-het-N8 4×32
HARP-hom- 4×16 AVATAR 128-point FFT
(N0,N2,N6,N8)

All the kernels are processed in 12-bit integer format.

the node N1’s CGRA completes the processing, the results
are transferred to the data memory of node N4.
Another feature of HARP2 is that, it allows all the cores
to process data simultaneously and independent of each
other. It is demonstrated as the node N2 of HARP-het ver-
sion processes a 128-point of FFT using a radix-(2, 4)
accelerator generated from AVATAR CGRA template with-
out interacting with other cores. The node N3, N5, N6 and
N8 are integrated with a 4×4, 4×8, 4×16 and 4×32 rPE
CGRAs, respectively. These nodes process 32nd -order inte-
ger MVM simultaneously and independent of each other.
The node N7 is not instantiated with any CGRA to show
the template nature of HARP, allowing the user to tailor
the HARP template as required in the overall application
scenario. The homogeneous version HARP-hom has a 4×16
rPE radix-(2, 4) FFT accelerator attached to its nodes N0,
N2, N5 and N7 to process several streams for FFT process-
ing. As a test case, only four 128-point streams have been
processed with a workload distribution of only one stream
per accelerator. The design and implementation details
of these CGRA based accelerators are comprehensively
described in [7, 21], and [23].
The overall system is driven by a single clock source. The
number of clock cycles required for data transfer is shown
in Table 2. The table presents clock cycles required for three
types of data transfers for both of the versions of HARP. 1-
Between data memories of different nodes. 2- Data transfer
within a slave node using the DMA device i.e., transfer from
node’s data memory to CGRA’s local memory. 3- The data
transfer from a CGRA’s local memory to the NoC.

Table 2 Clock cycles required for data transfer and execution at different stages.

Node-to D. Mem to D. Mem Trans. Exe.

-Node D. Mem to CGRA Total Total

het(N4-N0) 1017 659 1676 420

het(N0-N1) 1036 446* 1482 457
het(N1-N4) - 448* - -
het(N4-N2) 2042 1033 3075 571

het(N4-N3) 728
het(N4-N5) 609
het(N4-N6) 75622 - 75622 340
het(N4-N8) 211

hom(N4- 4× 4× 4×
(N0,N2,N6,N8)) 2042 1033 3075 587

D. Mem, Trans. and Exe. stand for Data Memory, Transfer and Execution, respectively. * sign shows data transfer from CGRA to Node’s data
memory.
348 J Sign Process Syst (2016) 85:341–353

Table 3 Resource Utilization Summary for Stratix-V FPGA Device (5SGXEA4H1F35C1).

HARP ALMs 78,845 / 158,500 50%

het Registers 64,436 / 634,000 10%
Memory Bits 21,000,928 / 38,912,000 54%
DSP 236 / 256 92%

HARP ALMs 120,823 / 158,500 76%

hom Registers 67,475 / 634,000 10.6%
Memory Bits 13,679,616 / 38,912,000 35%
DSP 236 / 256 92%

5 Measurements and Estimations
The homogeneous and heterogeneous versions of HARP,
hom and het are synthesized on a Stratix-V FPGA device
for prototyping purposes. The resource utilization summary
of both of the versions is shown in Table 3 in terms of
the number of ALMs, Registers, Memory Bits and Digital
Signal Processing (DSP) elements. ALMs are the Adaptive
Logic Modules of the FPGA device, mostly used to imple-
ment the combinational part of the logic. The consumption
of ALMs in HARP-het version are less than the ALM’s
consumed by HARP-hom version although there are more
rPEs instantiated in the heterogeneous version than in the
homogeneous. A comparison based on this aspect can not
be established as the resource utilization is based on the
number of computational resources generated inside a rPE.
A CGRA in HARP-hom version is performing FFT algo-
rithm with a mixed-radix(2, 4) scheme. The complexity of
this algorithm is relatively much higher than any other algo-
rithm considered in this experimental work and therefore,
the rPEs in HARP-hom are more densely generated than the
HARP-het version. It is for this reason, the ALM consump-
tion in HARP-hom version is 76 % in comparison to the
54 % ALMs consumed by HARP-het version on the FPGA
device. The ever increasing density of FPGA devices offers
a large number of resources. Stratix-V FPGA device offers
a very high number of registers. Since the HARP design is
aggressively registered, it efficiently utilizes the FPGA reg-
isters using the automatic placement and routing utility of
the synthesis tool.
The HARP-het and hom versions are consuming the
same number of DSP resources as the total number of mul-
tipliers instantiated in both of the versions are the same.
Each multiplier instantiated is of 32 bits, so it needs two
18-bit DSP resources on the FPGA. The breakdown of
the multipliers instantiated for each node’s CGRA and the

Table 4 Node-by-node breakdown of DSP resources for both of the versions of HARP.

Accelerator 32-bit
Node Type Multipliers DSPs

HARP Node-0 Radix-4 FFT 12 24

het Node-1 Complex MVM 12 24
Node-2 Radix-(2, 4) FFT 28 56
Node-3 Real MVM 4 8
Node-4 RISC Core 6 12
Node-5 Real MVM 8 16
Node-6 Real MVM 16 32
Node-7 - - -
Node-8 Real MVM 32 64
Total - 118 236
HARP Node-0 Radix-(2, 4) FFT 28 56
hom Node-2 Radix-(2, 4) FFT 28 56
Node-4 RISC Core 6 12
Node-6 Radix-(2, 4) FFT 28 56
Node-8 Radix-(2, 4) FFT 28 56
Total - 118 236
J Sign Process Syst (2016) 85:341–353 349

corresponding DSP resource consumption in both of the
HARP versions is shown in Table 4. The number of multi-
pliers instantiated in a particular CGRA template is based
on the requirements of an application. The design of CGRA
based accelerators containing a specific number of multipli-
ers are explained in [7, 12, 21] and [23].
The overall design of HARP2 works on a single clock
source. The slow timing model (900 mV) of HARP-het
version shows the clock frequency of 214.64 MHz at 0 ◦ C
and 186.22 MHz at 85 ◦ C. The fast time model (900 mV)
shows 274.65 MHz at 0 ◦ C and 251.0 MHz at 85 ◦ C. The
HARP-hom version shows 208.42 MHz at 0 ◦ C and 196.89
MHz at 85 ◦ C for slow timing model also at 900 mV. The
operating frequency for fast timing model are found to be
299.31 MHz at 0 ◦ C and 272.63 MHz at 85 ◦ C.
Considering frequency of 186.22 MHz and the Clock
Cycles (CC) presented in Table 2, the HARP-hom processes
four streams of 128-point FFT within 587 CC × 1/186.22

Table 5 Dynamic Power/Energy Estimation of each CGRA Node in both of the versions of HARP.

Node Algorithm Dynamic Active Dynamic

CGRA Size (Type) Power Time Energy
Other HW (mW) (μs) (μJ)

HARP-het N0 Radix-4 FFT

8×9 rPE (64-point) 129.68 4.20 0.54
N1 Complex MVM
4×8 rPE (64-Order) 116.75 4.57 0.53
N2 Radix-(2, 4) FFT
4×16 rPE (128-point) 213.12 5.71 1.21
N3 Real MVM
4×4 rPE (32nd Order) 61.55 7.28 0.44
N4 General Flow
RISC Control 59.73 - -
N5 Real MVM
4×8 rPE (32nd Order) 98.97 6.09 0.60
N6 Real MVM
4×16 rPE (32nd Order) 175.80 3.40 0.59
N7 - 0.37 - -
N8 Real MVM
4×32 rPE (32nd Order) 327.36 2.11 0.69
NoC - 7.12 - -
Integration
Logic - 302.07 - -
Total - 1492.52 - 4.6

HARP-hom N0 Radix-(2, 4) FFT

4×16 rPE (128-point) 214.68
N2 Radix-(2, 4) FFT
4×16 rPE (128-point) 214.35
N4 General Flow
RISC Control 59.75
N6 Radix-(2, 4) FFT
4×16 rPE (128-point) 212.97 5.87 7.11
N8 Radix-(2, 4) FFT
4×16 rPE (128-point) 213.89
NoC - 0.67
Integration
Logic - 295.64
Total - 1211.95
350
MHz = 3.15 μs. It shows the capability of HARP-het to
satisfy FFT execution time constraints of IEEE-802.11n
standard.
The power dissipation is estimated for both of the
versions of HARP at an ambient temperature of 25 ◦ C
and at an operating frequency of 100.0 MHz. The esti-
mates are achieved by simulating the gate-level netlist of
both of the HARP versions and then generating the Value
Change Dump (VCD) data for the applications mentioned
in Section 4.2. The VCD data was then provided to the esti-
mation tool Quartus II PowerPlay Power Analyzer which
indicated a high confidence metric in the supplied data.
The tool estimated 1146.64 mW and 1492.54 mW as static
and dynamic power dissipation, respectively for the HARP-
het version. For HARP-hom version, the tool estimated the
static and dynamic component of power dissipation equal
to 1097.99 mW and 1211.95 mW, respectively. The I/O
power dissipation for both of the versions is the same, i.e.,
22.66 mW.
Table 5 shows the breakdown of dynamic power and
energy consumption of the CGRAs integrated in both of the
versions of HARP. It can be observed that as the scale of the
CGRA increases, the dynamic power dissipation increases.
The size of the CGRA is application-specific. Furthermore,
the table shows that a CGRA offering more parallelism
(number of rPE columns) dissipates more dynamic power
but offers lower execution time. As the energy consumption
is the product of power dissipation and execution time, in
the specific case of node N3, N5, N6 and N8, the energy
consumption does not appear to deviate with a considerable
amount while executing the same kernel, i.e., 32nd -order
integer MVM.
Table 6 Comparisons based on different performance metrics with HARP implementation at 100.0 MHz on 28 nm FPGA.
Platform / Performance Platform’s
Technology Metric Value (PV)
NineSilica [22] / FFT Execution
FPGA 40 nm Time (μs) 10.3
[24] /
FPGA 90 nm GOPS 19.2
P2012 / [26]
CMOS 28 nm GOPS/mW 0.04
MORPHEUS / [27]
CMOS 90 nm GOPS/mW 0.02
In the table, SU fTfs, SD aTfs and Ps stand for Speed-Up for FPGA to FPGA scaling, Speed-Down for ASIC to FPGA scaling and Power scaling,
respectively.
J Sign Process Syst (2016) 85:341–353
6 Evaluation and Comparisons
The HARP homogeneous and heterogeneous instances are
synthesized for a 28 nm FPGA device. The process size
scaling in Stratix FPGA devices leads to an average operat-
ing frequency increase of 20 % [28]. Xilinx claims to pro-
vide 50 % performance increase while scaling the process
size from 40nm to 28nm, however the performance comes
at the cost of increasing the device density by 2X, therefore
expecting the user to exploit the additional 2X density for a
highly pipelined and parallel design [29]. In this context, an
average increase of 20 % in operating frequency can also be
estimated for Xilinx FPGA devices, considering in general
the effects of scaling the process size on operating frequency
provided in Altera FPGA devices. In particular, the pro-
cess size scaling from 40 nm to 28 nm and from 90 nm to
28 nm will lead to 20 % and 40 % performance increase,
respectively [28]. An important case study shows that a 90
nm ASIC implementation is 3.4X to 4.6X (average 4.0X)
faster and requires 14 times less dynamic power on average
than an equivalent 90 nm FPGA implementation [30]. Based
on this discussion, Table 6 shows a comparative analysis
between HARP’s heterogeneous implementation on 28 nm
FPGA and the scaled performance metrics of the platforms
mentioned in Section 2.
The HARP-het version is performing 64-point FFT on
the node N0 in 420 CC × 1/100.0 MHz = 4.2 μs. NineSilica
is doing the same task using all of its computational nodes in
10.3 μs on a 40 nm FPGA device. After applying a scaling
factor to estimate the processing time on a 28 nm FPGA,
NineSilica appears to compute 64-point FFT in 8.24μs, thus
HARP-het has a 1.96X gain in comparison.
Scaled PV HARP-het
Value Gain
Exe. Time - Exe. Time×20% SU fTfs
= 10.3-10.3×0.2=8.24 4.2 1.96X
PV×40% SU fTfs
= 19.2×1.4=26.88 40.8 1.51X
PV×SD atfs×Ps
= 0.04×1/4×1/2= 0.005 0.0153 3.0X
(PV×SD aTfs×Ps)×60% SU fTfs
= (0.02×1/4×1/2)×1.6=0.004 0.0153 3.8X
J Sign Process Syst (2016) 85:341–353
A homogeneous MPSoC designed in a MIMD approach
is synthesized on a 90 nm FPGA which yields a perfor-
mance of 19.2 GOPS [24]. The multiplication by a scaling
factor of 40 % to estimate the performance from 90 nm
FPGA to 28 nm FPGA shows a scaled performance increase
to 26.88 GOPS. In comparison, HARP-het version performs
at 40.8 GOPS, therefore achieving a gain of 1.51X.
The platform P2012 [26] is synthesized using 28 nm
CMOS technology. As discussed previously, an analysis for
the performance gap between a 90 nm ASIC and a 90 nm
FPGA implementation is presented [30]. Similar gap ratios
are expected between a 28 nm ASIC and a 28 nm FPGA
implementation. The gap shows a performance degradation
by a factor of 4 and dynamic power dissipation increase by
a factor of 14 for an FPGA implementation in comparison
to the same ASIC implementation. Considering a worst case
scenario, where static power is equal to dynamic power, the
factor of 14 reduces to almost 2 for the overall power dissi-
pation. The scaled performance of P2012 on a 28 nm FPGA
is calculated to be 0.005 GOPS/mW as shown in Table 6. In
comparison HARP shows a performance gain of 3.0X.
Similarly, MORPHEUS’s [27] performance of 0.02
GOPS/mW at 90 nm CMOS can be scaled to a 90 nm FPGA
as shown in Table 6, and then a multiplication with a 60
% speed-up to estimate performance for a 28 nm FPGA
device. The HARP’s performance on 28 nm FPGA shows
a gain of 3.8X in comparison to the scaled performance of
MORPHEUS platform.
7 Conclusion
In this paper, a template-based Homogeneous, Heteroge-
neous Accelerator-Rich Platform (HARP2 ) is presented.
The HARP2 template is used to generate both homogeneous
(HARP-hom) and heterogeneous (HARP-het) versions to
compute massively-parallel signal processing related algo-
rithms. HARP-het version is generated for a proof-of-
concept test-case to verify the functionality and design
features of the template. HARP-hom version is execut-
ing four streams of 128-points for Fast Fourier Transform
(FFT) processing within 3.15 μs under the execution-time
constraint of 4.0 μs of 802.11n standard.
The HARP-het version has been compared against other
state-of-the-art platforms. It performs a 64-point FFT within
4.2 μs while achieving a gain of 1.96X in comparison
to the estimated performance of NineSilica which is a
homogeneous Multi-Processor System-on-Chip (MPSoC).
HARP-het also performs at 40.8 GOPS and showing a
gain of 1.51X in comparison to the scaled performance of
351
an MPSoC designed with a Multiple-Instruction Multiple-
Data approach. The comparisons extends to another homo-
geneous platform P2012 which is an integration of four
clusters where each cluster contains four general purpose
processors, and finally with a heterogeneous platform called
MORPHEUS which is made up of three different reconfig-
urable fabrics. The HARP2 ’s heterogeneous version when
compared against the scaled performance levels of P2012
and MORPHEUS in terms of GOPS/mW, shows a perfor-
mance gain of 3.0X and 3.8X, respectively.
Acknowledgment This research work is jointly conducted by the
Department of Electronics and Communications Engineering, Tam-
pere University of Technology, Finland and the Department of Com-
puter Science, University of Chicago, Illinois, USA. It was partially
funded by the Academy of Finland under contract # 258506 (DEFT:
Design of a Highly-parallel Heterogeneous MP-SoC Architecture for
Future Wireless Technologies) and Tampere Doctoral Programme in
Information Science and Engineering, Finland. The Department of
Computer Science, University of Chicago, Illinois, USA also provided
the financial and on-site resources for its implementation.
The authors sincerely acknowledge Bob Bartlett, Director of the
Technical Staff at the Department of Computer Science, University
of Chicago, IL, USA for his consistent training, support and making
available the required computing infrastructure in a short time for the
implementation of this research work.
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Waqar Hussain is currently a
Postdoctoral Researcher and lec-
turing at the Department of Elec-
tronics and Communications
Engineering, Tampere University
of Technology (TUT), Finland.
He has been a Visiting Scientist
at the Department of Computer
Science, University of Chicago,
IL, USA and also at the
Institute for Communication
Technologies and Embedded Sys-
tems, Rheinisch-Westfaelische
Technische Hochschule
(RWTH), Aachen, Germany.
He has an M.Sc and a D.Sc.
(Technology) degree from TUT, Finland. Dr. Hussain’s research
interests include design and development of homogeneous and het-
erogeneous multicore and manycore systems that are specialized for
application specific, reconfigurable and general purpose processing.
He is working on accelerator-rich architectures and issues related to
communication infrastructures e.g., Network-on-Chip in an effort to
exploit the under-utilized part of the chip known as Dark Silicon. Dr.
Hussain has been serving as technical program committee member,
organizer and reviewer of several high-level conferences and journals.
J Sign Process Syst (2016) 85:341–353
Roberto Airoldi received
the M.Sc. and the D.Sc.
(Tech) degrees respectively
from University of Bologna
(Italy) in 2009 and Tampere
University of Technology
(Finland) in 2013. Currently,
Dr. Airoldi works as senior
research scientist in the
Department of Electronics
and Communications Engi-
neering at Tampere University
of Technology, where he
has the technical lead of an
Academy of Finland project
focused on the design of
flexible architectures for the implementation of cognitive radio
systems. His main research interests are: development of physical
layer algorithms and flexible architectures for wireless communica-
tions, low power design, multi-processor architectures and parallel
programming.
Henry Hoffmann has been
an Assistant Professor in the
Department of Computer Sci-
ence at the University of
Chicago since January 2013
where he leads the Self-
aware computing group (or
SEEC project) and conducts
research on adaptive tech-
niques for power, energy, and
performance management in
computing systems. He has
spent the last 13 years work-
ing on multicore architectures
and system software in both
academia and industry. He
completed a PhD in Electrical Engineering and Computer Science at
MIT where his research on self-aware computing was named one of
the ten ”World Changing Ideas” by Scientific American in December
2011. He received his SM degree in Electrical Engineering and Com-
puter Science from MIT in 2003. As a Masters student he worked on
MIT’s Raw processor, one of the first multicores. Along with other
members of the Raw team, he spent several years at Tilera Corporation,
a startup which commercialized the Raw architecture and created one
of the first manycores. His implementation of the BDTI Communica-
tions Benchmark (OFDM) on Tilera’s 64-core TILE64 processor still
has the highest certified performance of any programmable processor.
Prior to his graduate studies, he served as an Associate Staff member
of MIT Lincoln Laboratory where his research produced the Parallel
Vector Library (PVL), which forms the foundation of the VSIPL++
standard, an interface for parallel signal and image processing. Henry
was appointed as a Lincoln Masters Scholar in 2001 and a Lincoln
Doctoral Scholar in 2004. In 1999, he received his BS in Mathemat-
ical Sciences with highest honors and highest distinction from UNC
Chapel Hill.
353
Tapani Ahonen is a Research
Fellow at Tampere Univer-
sity of Technology (TUT) in
Tampere, Finland, where he
has held various positions
since 2000. He is a Scien-
tific Collaborator at Univer-
sit Libre de Bruxelles (ULB)
in Bruxelles, Belgium, where
he was a Visiting Researcher
between 2009 and 2010. His
current activities include sci-
entific coordination of a pan-
European project involving 26
participant organizations from
ten different countries. His work is focused on proof-of-concept driven
computer systems design with emphasis on many-core processing
environments. Ahonen has an MSc (2001) in Electrical Engineering
and a PhD (2006) in Information Technology from TUT.
Jari Nurmi works as a Pro-
fessor at Tampere University
of Technology, Finland since
1999, currently at the Depart-
ment of Electronics and
Communications Engineering.
He is working on embed-
ded computing systems,
wireless localization, posi-
tioning receiver prototyping,
and software-defined radio.
He held various research,
education and management
positions at TUT since 1987
(e.g. Acting Associate Pro-
fessor 1991-1994) and was
the Vice President of the SME VLSI Solution Oy 1995-1998. Since
2013 he is also a partner and cofounder of Ekin Labs Oy, a research
spin-off company. He has supervised 19 PhD and about 130 MSc
theses at TUT, and been the opponent or reviewer of 25 PhD theses for
other universities worldwide. He is a senior member in IEEE Circuits
and Systems Society, Communications Society, Computer Society,
Signal Processing Society, and Solid-State Circuits Society. He is also
a member of the technical committee on VLSI Systems and Appli-
cations at IEEE CAS, and board member of Tampere Convention
Bureau. In 2004, he was one of the recipients of Nokia Educational
Award, and the recipient of Tampere Congress Award 2005. He was
awarded one of the Academy of Finland Research Fellow grants for
2007-2008. In 2011 he received IIDA Innovation Award, and in 2013
the Scientific Congress Award and HiPEAC Technology Transfer
Award. He is a steering committee member of four international con-
ferences, and participates actively in organizing conferences, tutorials,
workshops, and special sessions, and in editing special issues in inter-
national journals. He has edited 3 Springer books, and has published
about 300 international conference and journal articles and book chap-
ters. He was the head of the national graduate school TELESOC for
5 years, and board member of the national GETA graduate school for
7 years. He is leading the national DELTA doctoral training network
2014- 2017, and he is the coordinator of Marie Curie ITN MULTI-
POS (Multi-technology positioning professionals) in 2012-2016. He
is responsible for the Electrical Engineering MSc program at TUT
since 2014. He is also reviewing projects for EU and project proposals
for national funding agencies in Belgium, Canada, The Netherlands,
Saudi-Arabia, Slovenia, Sweden, and Switzerland.