Boot timing; we assume no electrical equipment in the power supply (no battery and

power); at the time the user presses the Power button, EC detects a level; PMPWROK
will serve as an enable signal is sent to the CPU peripherals; using VR_PWRGD_ICH
This signals the Southbridge CO; when the user needs to enter standby mode (S3), the
system's AC; When the machine from S0 to enter S5, namely the shutdown, there will be
one; on HP6525 Inventec electric timing design; We know that when the standby section

12

Boot timing

We assume no electrical equipment in the power supply (no battery and power), this
time, only the RTC circuit inside the machine in operation, Southbridge will pick a 3V
button battery for RTC power supply to keep the operation of the internal time and
CMOS information. Plug in the battery or power supply, the machine internal
microcontroller EC on Reset and start working, waiting for the user presses the Power
button. Timing in this period are: electricity after ALWAYS open, EC Reset and
start running , and then distributed to Southbridge called 'RSMRST #' signal. Some
features of this time Southbridge start initialization and wait for the boot signal. Here we
must note that this does not turn on when all power Southbridge, only a small part of the
features available, such as power-supply PWRBTN # signal detection signal.

In time the user presses the Power button, EC detected a level change (general
timing are: high - low - high), and then send a boot signal (PWRBTN #) to the South
Bridge, South Bridge after receiving a signal sequence PWRBTN # pulled SLP_S5 #,
SLP_S4 #, SLP_S3 # signal (see their role in the chart on page) to open all of the external
voltage is mainly +3 V, +5 V and DDR2.5V, etc., and send PM PWROK signal, this
signal showed peripheral power normally open.
 PM PWROK as an enable signal to the CPU peripheral voltage VCCP Generator,
and open VCCP. After this, VCCP Generator will issue CORE_VR_ON to open CORE
VR (ie, CPU core voltage). At this point, the whole voltage have all opened.

After notification of this signal with VR_PWRGD_ICH Southbridge CORE VR

successfully opened, Southbridge PCI RST # signal will be issued to the PCI bus, so the
device on the bus are initialized (including Northbridge), and also issued H_PWRGD to
notify its CPU core voltage has been successfully opened. Then Northbridge hair
H_CPURST # signal to the CPU, CPU is RESET, and started to work.

When the user needs to enter standby mode (S3) of, ACPI and windows system
operate simultaneously, pulled SLP_S3 #, and keep SLP_S4 # and SLP_S5 # is pulled to
close the MAIN power, the system enters standby mode and in need when you go to
sleep or off mode, while low SLP_S3 #, SLP_S4 # and SLP_S5 #, closed except for RTC
power.Of course, in the course of this series, the need to work together to BIOS and
operating system, and hardware engineers, in particular the need to ensure that only the
state can guarantee a specific voltage supply.

When the machine from S0 to enter S5, namely the shutdown, there will be a certain
timing, timing is essentially the reverse of the previous run, I would not spend more ink
the

HP6525 Inventec power on timing design

We know the timing part of the standby part manufacturers are similar no matter
what, let's take a look at the British industry's cleverly designed and unique.

1. Standby section

Let's look at some parts of British industry standby voltage and part of the main
signal.

1. DC JACK, + VADP. + VBATR, + VBDC, + BATP

 2. ACDRV #, PWM #, ALARM, ADP-PRES, AC-AND-CHG, 0CP-OC #.

3. SDA-MAIN, SCL-MAIN)

4. ADP-PRES.KBC-PW-ON

5. +3 A, +5 A +3 AL, +5 AL

6. RTC-BAT, + V-RTC,

Plug in the power adapter will have a DC JACK, too L505 conversion + VADP,
over Q2, Q6 are turned into + VBATR, + VBDC TPS51120 protection resistor to turn +
BATP. This is a conversion process isolation circuit. So Q2.Q6 were generated ACDRV
# BQ24703 control and PWM # conduction. The isolation circuit were each converted
into a voltage control circuit ministries, such as + VBDC, + VADP each by R3.R6 100K
resistor divider to U1, again produced by subsequent + V5AL OUT connected in
BQ24703 PIN26, which this + VADP another After all the way through R12 partial
pressure of playing for the LM393 do supply conditions, the LM393 circuit protection
make the R504. Thus interception to ADP-PRES. Another + VBATR through the
rectifier diode and capacitor circuit C522 D502 to BQ's 20PIN. Plus + VADP1, +
VADP2 to + VBATR middle sampling resistor R8, R40 0.003 ohms to BQ8.9PIN, ACN,
ACP do current detection. The protective circuit-based design, thus the perfect realization
of conduction Q2.Q6. Otherwise after conducting a sampling resistor is R506, resistance
to 0.015. To SRP.SRN. This presented a problem. R8.R40 with 0.003, 0.015 Why use as
a follow-up sampling? The same power is 1W.

We look at AC-AND-CHG, is how to get the. The same is + VADP through the

resistor voltage divider after the LM393 plus R502 1M resistor protection circuit OUT
AC-AND-CHG, the other is the ADP-PRES ALARM associated circuitry by subsequent
+3 VAL pull-down resistor R41 to get. 0CP-OC # the + VADP1, + VBATR power in
LM324, U504, U503. There is a subsequent increase supply + V5S combination
Q13.14.17.18 get H-STPCLK, OCP-OC #, this combination is a gate, an inverter is used
in principle acquisition. From the above it seems the British industry protection circuit
design really simple. This is the domestic production plants and differences
abroad. Domestic circuit design on a large number of industrial circuit protection, and
relatively little foreign circuit comparing a good quality on a single IC device, the
domestic components in general, due to savings in procurement costs. These signals use
looking ACDRV #, PWM #, ALARM, ADP-PRES, AC-AND-CHG, 0CP-OC #,

ACDRV #, PWM # already know are used in conducting Q2.Q6, ALARM, ADP-
PRES main purpose is to ADP-PRES, CHGCTRL-3 (from the back of the SMSC KBC
output) the output through Q511, U502 over R70, R70 to do the drop-down and
comparing AC-AND-CHG Q11 input do very, ADP-PRES do G-pole + V3AL do drop
down after over R71. Combination Q7 and Q509 get CFET. In the battery part SDA-
MAIN.SCL-MAIN is used to detect the battery charge. THM-MAIN is used to detect
battery temperature, battery temperature over time to protect important. Then insert the
battery output voltage Q500, Q507, CON501 1PIN battery voltage output with +
VBATA connected then connected in Q500 input pole, then G is also extremely +
VBATA resistor divider through a capacitor C34 is connected to the output later in +
VBDC, to Q507, The output is then in turn connected to + VADP2, blood pressure  
control with + VADP Q507 conducting, rectifying diodes connected in + VADP2. At this
step, I believe we can easily see + VADP. + VBATR, + VBDC, + BATP, turn into the
importance of voltage isolation circuit protection have every piece of feedback. So the
British industry, we believe that difficult to repair, the challenge here. When all the way
to failure, when all has an associated liability. So the British industry is a relatively large
system, there is no way comparable to other manufacturers. Like a parent and subsidiary
companies plus numerous numerous outside companies, which have internal related party
transactions, external normal and non-normal trading. We have a snack, which sort
associated load, I believe are not difficult repair.

ADP-PRES continues to output, he and KBC-PW-ON U19 had to TPS51120

provides role EN signal. Between supply and in SMSC KBC1070, and SLP-S3 #-3R
through NC7S02M5X, let Q2013 completed + V3A to + V3-LAN shift down tube is
Q2014. Here MOS role is to amplify the current card to the class load. WAC-AND-CHG
output by BQ, the role of this signal with the front of the ADP-PRES has said this last
0CP-OC # for direct output to Southbridge Southbridge GPIO. After received + VBATR
TPS output directly +3 VAL. +5 VAL. +3 VAL place where more power, the main role
is: to EC power, a power supply to the EC; prior to boot, EC need for + V3AL, so you
can ensure that part of the module is hit live state, to achieve some functionality, such as.
Read the battery charge and temperature information (see below), to charge the battery,
such as SB RTC module supply; RTC battery is a small life, so under normal
circumstances are powered by a + V3AL ensure crystal start-up, to ensure that SB inside
CMOS settings will not be lost! Give some small IC provides operating voltage (+ V5AL
also the main role). +3 AVL generated power to the EC makes

KBC-PW-ON then here there is a process. SMSC KBC1070 received THM-MAIN

#, ADP-PRES, SCL-MAIN, SDA-MAIN, its crystal after normal work conditions,
(where there are follow-up + V-RT output LOW-BAT # -3, LED-3NUM #, BAT-
AMBER-LED #, STBY-LED #, LED-3-CAPS #, output KBC-PW-ON. makes
TPS51120 produce +3 V +5 V. in Battery mode (not pre-boot), and + no + V3A V5A,
which is mainly based on power-saving mode designed to consider is the British
industry's main design. U19 is or door. supply is +5 VAL, under Battery Mode (not pre-
boot) ADP_PRES and KBC_PW_ON are low, So no + V3A and + V5A, just press the
power button KBC_PW_ON pulled, before opening + V3A and + V5A, while AC mode
(not pre-boot) ADP_PRES and KBC_PW_ON are high in + V3AL issued later, after a
RC delay circuit (specific delay according to the formula T = R * C can be calculated),
and then through the whole wave U1 (RC delay after wave rise time becomes longer, so
you need to use the wave type U1 rise time shorter, ie let the voltage up a little faster),
issued VCC1_POR # this delay circuit there are several, such as in the EC have after the
above conditions will be issued in accordance with the above RSMRST # SPEC know if
RSMRST # not normal, it will affect all subsequent electricity, because if SB received
RSMRST # is not normal, it will affect the SB issued SLP_S5 # (+ V1.8) and SLP_S3 #
(+ V1.5/1.8/2.5/3/5S) . S5 and S3 are provided to enable the subsequent turn-on voltage
of the signal is 1.8,1.5,2.5, and so on. RSMRST # only output to Southbridge, Inventec
also made a joint design simultaneously output to the TPS51120 \ 30PIN, This is a
problem we leave again, why should be designed??? this is we often encounter TPS51120
hot, overcurrent. regulated power supply current is about 0.12A, change TPS51120 bad,
not good to change SMSC . backward for South Bridge. yeah no good and some change
and this is not in itself make the TPS51120 hot really bad one of the reasons. Continued
below the power .. .. .. .. .. .. .... badly written, forgive me. welcome correction
supplement..

CPU addressing process.

E signal identifying the meanings DS #: C PU address strobe signal, when active

low, the address strobe signal is the same as if we travel, there are a couple of choices to
choose from, how can a specific choice to go in the CPU and Northbridge address lines is
unidirectional transmission.

BSY #: FSB bus busy signal, high indicates the general line is not busy, the low
level indicates that the bus is busy, busy, said address bus signals being transmitted
online.

FRAMWE #: PCI frame cycle signal, low indicates the PCI bus start working, high
indicates the PCI bus did not work.

IBDY #: master ready signal, active low, the master device ready signal and the
signal from the device is ready, when the data is transferred from the Northbridge to the
Southbridge to Northbridge mainly from Southbridge, Northbridge if Southbridge to
transfer data when Southbridge mainly from Northbridge.

CS #: chip select signals. Low level selected, not selected high.

 CPU addressing process that is the main CPU to begin the soft start and run the
POST BIOS self-test procedure; from the CPU to the Northbridge; Northbridge to the
Southbridge; Southbridge to the BIOS, then the entire process bus returned.

Laptop Motherboard various signals described in a lot of people watching the

notebook drawings for a variety of code inside, not sure! In fact, these are the
acronym! First, let me ALW, its English name is Alway, meaning always like +5 VALW,
it is used when the power plug after this voltage should have, so we plugged in after only
a ALW, regardless is 3VALW, or 5VALW, as long as the ALW, should have its
corresponding voltage, which is used to power the circuit, such as the EC and the like.

Followed by SUS, its English name is Suspend, mean delay, suspend meaning, such
as +3 VSUS (SLP_S5 # CTRLD POWER These will explain the timing of the power)
voltage generator behind it really ALW voltage when receiving SUS_on the control
voltage will produce this series of voltage, this voltage is not the main supply voltage,
just provide groundwork for the next step to generate a voltage, but this does not mean
that the voltage is not important, no SUS voltage, the voltage will not produce
behind. Once again, the voltage RUN, RUN voltage is not an abbreviation, it means run,
run mean, this is the main north and south bridge voltage work, of course, also need SUS
north and south bridge voltage. The system is running, then you really need to RUN
voltage is normal, if RUN voltage instability will cause instability in the motherboard.

PLTRST #

Total reset signal: PLTRST # is the Intel ® ICH9 total reset of the entire platform
(eg: I / O, BIOS chip, card, Northbridge, etc.). During power-up and when the S / W
signal (M by reset control register (I / O registers CF9h) to initialize a hard reset sequence
determines PLTRST # ICH9 state in PWROK and VRMPWRGD is high after a
minimum ICH9 driver PLTRST # 1 millisecond is invalid when initialized by a reset
control register (I / O registers CF9h) ICH9 driver PLTRST # is valid for at least 1
millisecond Notes: Only VccSus3_3 normal PLTRST # this signal to work.
 VTHRM # thermal alarm signal: activate THRM # is low signal to external
hardware to generate an SMI # or SCI signal)

THRMTRIP #

Thermal circuit signal: When THRMTRIP # signal is low model, the issue of the
heat from the processor circuit model, ICH9 immediately converted to S5 state. ICH9
will not be allowed to wait for a signal from the processor to stop the return will enter the
S5 state. SLP_S3 #

S3 sleep control signal: SLP_S3 # is the power level control. When entering the S3
(suspend to RAM), S4 (suspend to disk), S5 (soft-off) state of this signal to switch off all
non-critical system power. SLP_S4 #

S4 sleep control signal: SLP_S4 # i is the power level control signal when entering
S4 (suspend to disk), when S5 (soft-off) state of this signal to switch off all non-critical
system power. Note: The previously used to control foot Pin ICH9 of DRAM power
cycling capabilities.

Note: In a system on the support of Intel AMT, this signal used to control power
DRAM, comments: In the M1 state (when the host is in S3, S4, S5 status and operational
subsystems running ) This signal is forced HIGH together SLP_M # to provide
sufficient power for DIMM operational subsystems. SLP_S5 #

S5 sleep control signal: SLP_S5 # is a power level control signal when the system
enters S5 (soft-off) state SLP_S5 # for all non-critical system power is turned off.

SLP_M #

Operational sleep state control signals: Power-layer control for Intel AMT
subsystem. If there is no operational engine firmware, SLP_M # will be synchronized
with SLP_S3 #.
 S4_STATE #

S4 state pointer signal: when the machine is in S4 or S5 state of the signal is active
low. When the machine is in state S3

Operability of the current state of the engine, together with the mandatory SLP_S4 #
SLP_S4 # is high, this signal can be used for other devices to understand the machine.

PWROK

Power Good Signal: all power distribution bus PCICLK stable steady 99ms and 1ms
time, PWROK to Southbridge a valid flag. . PWROK asynchronously driven. PWROK
low level, Southbridge will think PLTRST # valid. Notes: (1) In the normal three RTC
clock cycle Southbridge completely reset the power supply and generates a complete
PLTRST # signal output, PWROK must be a minimum inactive.

2. PWROK must be no false signals, even RSMRST # is low.

WCLPWROK

Power Good signal control LINK: When CLPWROK have xxxxxx, said from the
power to control LINK subsystem (Northbridge, Southbridge, etc.) are stable and
notification Southbridge make CL_RST # invalid until the Northbridge receives this
signal

Notes: Before RSMRST # invalid CLPWROK allowed to be effective.

Notes: After PWROK effective CLPWROK allowed effective.

PWRBTN #

Power button: Power button will cause SMI # or SCI to indicate a system sleep
state. If the system is already a sleep state, this signal will trigger a wake-up event, if
there is room PWRBTN # xxxxxx than 4s, regardless of the system in S0, S1, S3, S4
state, then the state will unconditionally transition to S5. This signal has an internal pull-
up resistor

And inputs have a built-in 16ms debounce design.

Ringtones Tip: This signal is an input signal from the Modem. It allows a wake-up
event, power failure protection at the time.

SYS_RESET #

System reset: After DEBOUNCE This forced an internal reset signal. If the SMBus
idle, Southbridge will immediately reset, Also, before forcing a system reset,
SYS_RESET # 25ms ± 2ms will wait until the SMBus idle. RSMRST #

Restore normal reset signal: This signal is used to reset the power is restored logic,
all the power of this signal is valid for at least 10ms will work, when the lift is valid, this
signal is to hang a sign of stability bus.

LAN_RST #

LAN Reset: When this signal is active when the internal LAN controller is reset, in
ccLAN3_3 and VccLAN1_05 and VccCL3_3 power of the normal state of LAN signal to
be effective. After the lifting of an effective, this signal is a sign of stability LAN bus
Notes: (1) Before RSMRST # lifted effective LAN_RST # must be valid.

2 After PWROK effective, LAN_RST # must be valid.

3 In VccLAN3_3 and VccLAN1_05 and VccCL3_3 power are normal

circumstances LAN_RST # must be valid 1ms.

4 If the card is not integrated LAN_RST # can connect it to Vss.

WAKE #
 PCI Express * Wake Event: Sideband wake-up signal on the PCI Express slot and
has issued a wake-up request signal components.

MCH_SYNC #

Northbridge sync signal: The input signal is phase PWROK inside, the signal is
connected to the output of ICH_SYNC # Northbridge.