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Development Team
Prof. Vinay Gupta ,Department of Physics and Astrophysics,
Principal Investigator University of Delhi, Delhi
Dr. Monika Tomar, Department of Physics, Miranda House University of Delhi, Delhi
Content Writer
Dr. Ayushi Paliwal, Department of Physics, Deshbandhu College, University of Delhi, Delhi
Learning Objectives:
From this module students may get to know about the following:
IV characteristics of JFET
The modern era of semiconductor electronics was ushered in by the invention of the bipolar transistor in
1948 by Bardeen, Brattain, and Shockley at the Bell Telephone Laboratories. This device, along with its
field-effect counterpart, has had an enormous impact on virtually every area of modern life. In this
module, we will learn about the operation, applications, and fabrication of the field-effect transistor
(FET). The field-effect transistor comes in several forms. In a junction FET (called a JFET) the control
(gate) voltage varies the depletion width of a reverse biased p-n junction. A similar device results if the
junction is replaced by a Schottky barrier (metal-semiconductor FET, called a MESFET). Alternatively,
the metal gate electrode may be separated from the semiconductor by an insulator (metal-insulator-
semiconductorFET, called a MISFET). A common special case of this type uses an oxide layer as the
insulator (MOSFET). We have found that two dominant features of p-n junctions are the injection of
minority carriers with forward bias and a variation of the depletion width W with reverse bias. These
two p-n junction properties are used in two important types of transistors. The bipolar junction transistor
(BJT) uses the injection of minority carriers across a forward-biased junction, and the junction field-
effect transistor discussed in this chapter depends on control of a junction depletion width under reverse
bias. The FET is a majority carrier device, and is therefore often called a unipolar transistor. The BJT,
on the other hand, operates by the injection and collection of minority carriers. Since the action of both
electrons and holes is important in this device, it is called a bipolar transistor. Like its bipolar counterpart,
the FET is a three-terminal device in which the current through two terminals is controlled at the third.
Unlike the BJT, however, field-effect devices are controlled by a voltage at the third terminal rather than
by a current. The history of BJTs and FETs is rather interesting. It was the FET that was proposed first
in 1930 by Lilienfeld, but he never got it to work because he did not fully appreciate the role of surface
defects or surface states. In the process of trying to demonstrate experimentally such a field-effect
transistor, Bardeen and Brattain somewhat serendipitously invented the first bipolar transistor, the Ge
point contact transistor. This major breakthrough was rapidly followed by Shockley's extension of the
concept to the BJT. It was only much later, after the problem of surface states was resolved by growing
an oxide insulator on Si, that the first MOSFET was demonstrated in 1960 by Kahng and Atalla.
Although the BJT reigned supreme in the early days of semiconductor integrated electronics, it has been
gradually supplanted in most applications by the Si MOSFET. The main reason is, unlike BJTs, the
various types of FET are characterized by a high input impedance, since the control voltage is applied to
a reverse-biased junction or Schottky barrier, or across an insulator. These devices are particularly well
suited for controlled switching between a conducting state and a nonconducting state, and are therefore
useful in digital circuits. They are also suitable for integration of many devices on a single chip.
2. Junction field effect transistors (JFET)
Depletion
region
FIGURE 1 : A junction FET consisting of an n-type bar with p-regions formed on opposite sides.
However, the most practical form, substrate is directly connected to the source, which ensures zero bias.
The following diagram gives practical form of construction in silicon as shown in figure 3.
One expects that the gate transition regions would extend right through the channel as the drain voltage
is increased further, thus, cutting off the current completely, as also predicted by Shockley, the inventor
of JFET. The channel is pinched rather than cut off. Because of the steady voltage drop along the channel,
it tapers from one end to the other, because there is a steady voltage drop along it. The drain current
flowing through the channel multiplied by the channel resistance between the source and any point along
the channel, relative to the source, gives voltage at that point. So, there is no voltage drop along the
channel, if the current were cut off and all points along it would remain at the source voltage, and there
would be no decrease in the channel width from its value at the source end, so the current would not be
cutoff. The solution to this paradox is that the channel is almost cut off at the drain end of the channel.
The channel width keeps on becoming narrower, as the drain voltage VD is increased, to a point until
which, it is ‘pinched off’, which means that the current rises asymptotically to a final value, which
increases only slowly as the drain voltage increases further. The drain-gate voltage at which it occurs, is
the pinch-off voltage VP, the voltage across the gate p-n junction which causes it to widen right across
the channel. Then it reaches a state of steadiness, in which just sufficient channel is left to pass the current
needed to produce a voltage drop along the channel equal to this pinch-off voltage. So, it turns out to be
a self-adjusting process.
Pinch Off Condition:
The JFET under pinch off condition is shown in figure 5.
As VD increases, the gate to channel pn junction is reverse biased so that the depletion width increases
When VD>VDsat, ID ≈ IDsat and is independent of VD. Practically, all additional voltage appears across
depletion region.
1. Linear region: VGS = 0, with increase in small VDS (small depletion region), the current ID increase
linearly and JFET act as the voltage controlled resistor.
2. Non linear region: for moderate VDS < VDsat, depletion width increases, average channel area
decreases, channel resistance increases. Thus, ID increases at slower rate with VDS for given VGS.
3. Pinch off region: VGS is made sufficiently negative of VDS = VDsat such that drain and source are
isolated by depletion width and constant ID flows due to injected charge carriers.
4. Saturation region: VDS>VDsat and |VGS| >|VP|. The drain current ID is constant with VDS for a given
value of VGS.
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The cross section of a JFET is shown in figure 9, with clearly identified variables. The approximate d.c.
characteristics of a device can be calculated as follows:
If the p-type gates of the n-channel JFET are relatively doped, the p-n junctions between gates and
channel must be abrupt. This is required for the proportionality of transition region width Wx, at a
distance x from the source, with the square root of the applied voltage at that point.
Thus,
2𝜀𝑉𝑥
𝑊𝑥 2 = (2)
𝑞𝑁𝑑
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Thus, the drain current ID through a section of the channel, distance x from the source, is ID= conductivity
x electric field x cross sectional area of the channel at x
Let b be breadth of channel. We know, Ex=-dVx/dx
𝑑𝑉𝑥
ID = - σb (2a - 2wx) (4)
𝑑𝑥
So
2aσb 2 𝑉𝑥 3/2 VDS −VGS
ID = − [1 − ] −𝑉 (7)
𝐿 3 𝑉𝑃 1/2 𝐺𝑆
After integration and finally applying the limits on integration and simplifying,
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2aσb 2 (VDS −VGS )2 2 (−VGS )3/2
ID = − [VDS − 3 1 + ] (8)
𝐿 3 𝑉𝑃 1/2
𝑉𝑃 2
At pinch-off, VDS - VGs = Vp, and the characteristic enters the ‘saturation region of operation’.
Substituting for VDS in eq. (8)
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2aσb 𝑉𝑃
IDSS = (10)
𝐿 3
So, IDSS is a parameter which depends only on the structure of device and is determined by the design of
JFET. An approximation to equation (9) is often used, since it is too complex to be carefully analysed.
𝑉𝐺𝑆 2
ID (at pinch-off)= IDSS(1 + ) (11)
𝑉𝑃
Or,
2 1/2
gm (at pinch-off) = (ID(at pinch−off) 𝐼𝐷𝑆𝑆 ) (13)
𝑉𝑃
ID (at pinch-off) thus refers to current at pinch-off at the specified VGS. Thus, gm increases in proportion to
1/2
(ID(at pinch−off) ) .
As VDS is increased beyond pinch-off, ID does not remain constant because the channel shortens as VDS
increases. The rate of increase is proportional to ID, so straight portions of characteristic curves can be
extrapolated back to a voltage of -1/λ. From the geometry of figure 4, for output conductances, go at any
operating point are given by the slopes of the characteristics.
𝐼𝐷
go = (14)
𝑉𝐷𝑆 +1/λ
The transconductance increases as the separation between adjacent lines in figure 4 and 6 increases with
VDS , although it is generally enough to assume that gm in saturation is the same as in pinch-off. Using
geometry of figure 4 to drive an expression for the increase of gm with VDS, for a particular VGS,
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4. Summary
Structure of n-channel and p-channel JFET
Operation of n-channel JFET
IV characteristics of JFET
Theoretical description of IV relationship for JFET
Low frequency small signal model of JFET
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