Cache Related Preemption Delay Computation For Set-Associative Caches

Cache Related Preemption Delay Computation for
Set-Associative Caches
Pitfalls and Solutions
Claire Burguière, Jan Reineke, Sebastian Altmeyer
Workshop on WCET Analysis, Dublin 2009
saarland
university
computer science
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Context computer science
Preemptive scheduling
Cache related preemption delay (CRPD):
I Impact of preemption on the cache content
I Overall cost of additional reloads due to preemption
T1
T2
= CRPD
= Task Activation
Burguière, Reineke, Altmeyer CRPD for set-associative caches WCET, Dublin 2009 2 / 13
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CRPD computation for set-associative caches computer science
CRPD computation:
I Useful Cache Blocks (UCB)
I Evicting Cache Blocks (ECB)
CRPD for set-associative caches:
⇒ Pitfalls:
I LRU: CRPD not bounded by the number of ECBs
I FIFO and PLRU: CRPD not bounded
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Useful Cache Block - [Lee et al., 1996] computer science
Definition (Useful Cache Block)

A memory block m at program point P is called a useful cache block, if
a) m may be cached at P
b) m may be reused at program point P 0 that may be reached from P
with no eviction of m on this path.
= hit
= miss
P
A B D C B A C
Cache Content:
[A, B, C, D]
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= hit
= miss
P
A B D C B A C
Cache Content:
[A, B, C, D]
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= hit
= miss
P
A B D C B A C
Cache Content:
[A, B, C, D]
c
X
CRPDLRU = CRPDLRU (s)
s=1
LRU n = associativity
CRPDUCB (s) = BRT · min(|UCB(s)|, n) BRT = Block Reload Time
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Evicting Cache Blocks computer science
[Tomiyama and Dutt, 2000]

Definition (Evicting Cache Blocks (ECB))
A memory block of the preempting task is called an evicting cache
block, if it may be accessed during the execution of the preempting
task.
Cache Content: X Y Z Cache Content:

[A, B, C, D] [X , Y , Z , D]
A B C B A C
= additional miss due to preemption (CRPD)
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Evicting Cache Blocks computer science
[Tomiyama and Dutt, 2000]

Definition (Evicting Cache Blocks (ECB))
A memory block of the preempting task is called an evicting cache
block, if it may be accessed during the execution of the preempting
task.
Cache Content: X Y Z Cache Content:

[A, B, C, D] [X , Y , Z , D]
A B C B A C
= additional miss due to preemption (CRPD)
LRU ?
CRPDECB (s) = BRT · min(|ECB(s)|, n)
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CRPD computation for LRU using ECB: Pitfall computer science
0x08
0x09
0x0a
0x0b
8 9 a b
[b, a, 9, 8] [8, b, a, 9] [9, 8, b, a] [a, 9, 8, b] [b, a, 9, 8] 0 misses
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CRPD computation for LRU using ECB: Pitfall computer science
0x08
0x09
0x0a
0x0b
8 9 a b
[b, a, 9, 8] [8, b, a, 9] [9, 8, b, a] [a, 9, 8, b] [b, a, 9, 8] 0 misses
ECBs
= {e}
8∗ 9∗ a∗ b∗
[e, b, a, 9] [8, e, b, a] [9, 8, e, b] [a, 9, 8, e] [b, a, 9, 8] 4 misses
|UCB(s)| = 4
|ECB(s)| = 1
n=4
number of additional misses= 4
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LRU: new computation of CRPD using ECB computer science
ECB derivation used only to know if the set is used by the

preempting task:

LRU 0 if ECB(s) = ∅
CRPDECB (s) =
BRT · n otherwise
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CRPD for FIFO: Pitfalls computer science
a e∗ b c∗ e
[b, a] [b, a] [e, b] [e, b] [c, e] [c, e] 2 misses
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CRPD for FIFO: Pitfalls computer science
a e∗ b c∗ e
[b, a] [b, a] [e, b] [e, b] [c, e] [c, e] 2 misses
ECBs
= {x} a∗ e∗ b∗ c∗ e∗
[x, b] [a, x] [e, a] [b, e] [c, b] [e, c] 5 misses
|UCB(s)| = 2
|ECB(s)| = 1
n=2
But: number of additional misses= 3
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Definition – Relative Miss-Competitiveness computer science
Notation
mP (p, s) = number of misses that policy P incurs on
access sequence s ∈ M ∗ starting in state p
Definition (Relative miss competitiveness)

Policy P is (k , c)-miss-competitive relative to policy Q, if
mP (p, s) ≤ k · mQ (q, s) + c
for all access sequences s ∈ M ∗ and compatible cache-set states p, q.
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Definition – Relative Miss-Competitiveness computer science
Notation
mP (p, s) = number of misses that policy P incurs on
access sequence s ∈ M ∗ starting in state p
Definition (Relative miss competitiveness)

Policy P is (k , c)-miss-competitive relative to policy Q, if
mP (p, s) ≤ k · mQ (q, s) + c
for all access sequences s ∈ M ∗ and compatible cache-set states p, q.
PLRU(n) is (1, 0)-miss-competitive relative to LRU(1 + log2 n).

FIFO(n) is ( n−rn+1 , r )-miss-competitive relative to LRU(r ).
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A sequence of memory accesses computer science
Notation:
I m = number of misses
I m = number of misses in the case of preemption
mpre = 4 mpost = 2
mpre = mpre = 4 mpost = mpost + mCRPD = 5
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Notation:
mpre = 4 mpost = 2
Relative miss competitiveness:

(t)
m(t) = (t)
mpre + mpost
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Notation:
mpre = 4 mpost = 2

(t)
m(t) = (t)
mpre + mpost
LRU(s) LRU(s) LRU(s)
≤ [k · mpre + c] + [k · (mpost + mCRPD ) + c]
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Notation:
mpre = 4 mpost = 2

(t)
m(t) = (t)
mpre + mpost
= [k · (mpre + mpost ) + c] + [k · mCRPD + c]
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Notation:
mpre = 4 mpost = 2

(t)
m(t) = (t)
mpre + mpost
= [k · (mpre + mpost ) + c] + [k · mCRPD + c]
LRU(s)
= [k · m LRU(s) + c] + [k · mCRPD + c]
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Relative Competitiveness – Application computer science
PLRU(8) using LRU(4):

LRU(4)
m PLRU(8) ≤ m LRU(4) + mCRPD
FIFO(8) using LRU(5):

LRU(5)
m FIFO(8) ≤ (2 · m LRU(5) + 5) + (2 · mCRPD + 5)
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Conclusions computer science
Pitfalls Solutions
LRU: LRU:
|ECBs| is not an |ECBs| = 0
upper-bound ⇒ the set is not used
FIFO and PLRU: FIFO and PLRU:
|UCBs|, |ECBs| and n using relative
do not bound the number competitiveness
of additional misses and LRU bounds
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Further reading computer science
Altmeyer, S. and Burguière, C. (2009).
A New Notion of Useful Cache Block to Improve the Bounds of Cache-Related Preemption
Delay.
In ECRTS ’09 pp. 109–118, IEEE Computer Society.
Lee, C.-G., Hahn, J., Min, S. L., Ha, R., Hong, S., Park, C. Y., Lee, M. and Kim, C. S.
(1996).
Analysis of cache-related preemption delay in fixed-priority preemptive scheduling.
In RTSS’96 p. 264, IEEE Computer Society.
Negi, H. S., Mitra, T. and Roychoudhury, A. (2003).
Accurate estimation of cache-related preemption delay.
In CODES+ISSS’03 ACM.
Reineke, J. (2008).
Caches in WCET Analysis.
PhD thesis, Universität des Saarlandes, Saarbrücken.
Staschulat, J. and Ernst, R. (2007).
Scalable precision cache analysis for real-time software.
ACM TECS 6, 25.
Tan, Y. and Mooney, V. (2004).
Integrated intra- and inter-task cache analysis for preemptive multi-tasking real-time
systems.
In SCOPES’04 pp. 182–199,.
Tomiyama, H. and Dutt, N. D. (2000).
Program
Burgui pathAltmeyer
ère, Reineke, analysis
to bound cache-related
CRPD preemption
for set-associative caches delay in preemptive
WCET, Dublinreal-time
2009 13 / 13
saarland
university
Upper-bound on the CRPD - direct-mapped caches computer science
using UCB [Lee et al., 1996]:
CRPDUCB = BRT · |{si | ∃m ∈ UCB : m mod c = si }|
using ECB [Tomiyama and Dutt, 2000]:
CRPDECB = BRT · |{si | ∃m ∈ ECB : m mod c = si }|
using UCB and ECB [Negi et al., 2003, Tan and Mooney, 2004]:
CRPDUCB&ECB = BRT · |{si | ∃m ∈ UCB : m mod c = si

∧∃m0 ∈ ECB : m0 mod c = si }|
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Relative Competitiveness – Example computer science
mpre = 4 mpost = 2
LRU(s) (t) LRU(s)

m(t)
pre ≤ k · mpre +c mpost ≤ k · mpost + c
= k · mpre +c = k · (mpost + mCRPD ) + c
(t)
m(t) = m(t)
pre + mpost
≤ k · mpre + c + k · (mpost + mCRPD ) + c
= (k · (mpre + mpost ) + c) + (k · mCRPD + c)
LRU(s)
= (k · m LRU(s) + c) + (k · mCRPD + c).
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Relative Competitiveness – Application computer science
PLRU(n) using LRU(1 + log2 n):

I k = 1, c = 0
LRU(1+log2 n)
m PLRU(n) ≤ m LRU(1+log2 n) + mCRPD
I Example (n=8):
LRU(4)
m PLRU(8) ≤ m LRU(4) + mCRPD
FIFO(n) using LRU(r ):

n
I k= n−r +1 , c =r
n n LRU(r )
m FIFO(n) ≤ ( · m LRU(r ) + r ) + ( · mCRPD + r )
n−r +1 n−r +1
I Example (n=8,r=5):
LRU(5)
m FIFO(8) ≤ (2 · m LRU(5) + 5) + (2 · mCRPD + 5)
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CRPD for PLRU: Pitfalls computer science
1 d 0 b 1 c 0 b 1 a 1 d 0
1 1 1 0 0 0 0 1 0 1 1 1 1 0 0 misses
a b c d a b c d a b c d a b c d a b c d a b c d a b c d
ECBs
= {x, y} 1 d* 0 b* 1 c* 0 b 1 a* 0 d* 1
0 0 0 1 1 1 1 0 1 0 1 1 0 1 5 misses
a y c x a y d x b y d x b y d c b y d c b y a c b d a c
|UCB(s)| = 4
|ECB(s)| = 2
n=4
But: number of additional misses= 5

Cache Related Preemption Delay Computation For Set-Associative Caches

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Cache Related Preemption Delay Computation For Set-Associative Caches

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Cache Related Preemption Delay Computation for

Claire Burguière, Jan Reineke, Sebastian Altmeyer

Workshop on WCET Analysis, Dublin 2009

Definition (Useful Cache Block)

Definition (Useful Cache Block)

Definition (Useful Cache Block)

[Tomiyama and Dutt, 2000]

Cache Content: X Y Z Cache Content:

= additional miss due to preemption (CRPD)

[Tomiyama and Dutt, 2000]

Cache Content: X Y Z Cache Content:

= additional miss due to preemption (CRPD)

ECB derivation used only to know if the set is used by the

Definition (Relative miss competitiveness)

for all access sequences s ∈ M ∗ and compatible cache-set states p, q.

Definition (Relative miss competitiveness)

for all access sequences s ∈ M ∗ and compatible cache-set states p, q.

PLRU(n) is (1, 0)-miss-competitive relative to LRU(1 + log2 n).

mpre = mpre = 4 mpost = mpost + mCRPD = 5

mpre = mpre = 4 mpost = mpost + mCRPD = 5

Relative miss competitiveness:

mpre = mpre = 4 mpost = mpost + mCRPD = 5

Relative miss competitiveness:

mpre = mpre = 4 mpost = mpost + mCRPD = 5

Relative miss competitiveness:

mpre = mpre = 4 mpost = mpost + mCRPD = 5

Relative miss competitiveness:

PLRU(8) using LRU(4):

FIFO(8) using LRU(5):

using UCB [Lee et al., 1996]:

CRPDUCB = BRT · |{si | ∃m ∈ UCB : m mod c = si }|

using ECB [Tomiyama and Dutt, 2000]:

CRPDECB = BRT · |{si | ∃m ∈ ECB : m mod c = si }|

CRPDUCB&ECB = BRT · |{si | ∃m ∈ UCB : m mod c = si

mpre = mpre = 4 mpost = mpost + mCRPD = 5

LRU(s) (t) LRU(s)

PLRU(n) using LRU(1 + log2 n):

FIFO(n) using LRU(r ):

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