Quiz N.2 FSM

Johnny Gómez Marín Quiz N.
2 FSM
ENTIDAD
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity FSM_examen is
Port (RST:in std_logic;
X: in std_logic;
Clock:in std_logic;
Z: out std_logic_vector(1 downto 0));
end FSM_examen;
architecture Behavioral of FSM_examen is
type state is (S0, S1, S2, S3, S4);
signal Current_state, Next_state: state;
begin
sincronizar_reloj: process(RST,Clock)
begin
if RST= '1' then
Current_state <= S0;
elsif (rising_edge(Clock)) then
Current_state <= Next_state;
end if;
end process;
transiciones: process(Current_state, X)
begin
case Current_state is
when S0 =>
if (X = '0') then
Next_state <= S1;
elsif (X = '1') then
Next_state <= S3;
else
Next_state <= Next_state;
end if;
when S1 =>
if (X = '0') then
Next_state <= S0;
Next_state <= S2;
else
end if;
when S2 =>
if (X = '0') then
Next_state <= S3;
Next_state <= S4;
else

end if;
when S3 =>
if (X = '0') then
Next_state <= S3;
Next_state <= S4;
else
end if;
when S4 =>
if (X = '0') then
Next_state <= S1;
Next_state <= S4;
else
end if;
end case;
end process;
Salidas: process (Current_state)
begin
when S0 => Z <= "01";
when S1 => Z <= "00";
when S2 => Z <= "11";
when S3 => Z <= "11";
when S4 => Z <= "01";

when others => Z <= "00";
end case;
end process;
end Behavioral;
transiciones: process(RST, Current_state, X)
begin
if RST= '1' then
Next_state <= S0;
end if;
when S0 =>
if (X = '0') then
Next_state <= S1;
Next_state <= S3;
else
end if;
when S1 =>
if (X = '0') then
Next_state <= S0;
Next_state <= S2;
else

end if;
when S2 =>
if (X = '0') then
Next_state <= S3;
Next_state <= S4;
else
end if;
when S3 =>
if (X = '0') then
Next_state <= S3;
Next_state <= S4;
else
end if;
when S4 =>
if (X = '0') then
Next_state <= S1;
Next_state <= S4;
else
end if;
end case;
end process;
Salidas: process (Current_state)

begin
when S0 => Z <= "01";
when S1 => Z <= "00";
when S2 => Z <= "11";
when S3 => Z <= "11";
when S4 => Z <= "01";
when others => Z <= "00";
end case;
end process;
end Behavioral;
TEST BENCH
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Test_bench_FSM_examen is
-- Port ( );
end Test_bench_FSM_examen;
architecture Behavioral of Test_bench_FSM_examen is
component FSM_examen is
Port ( RST: in STD_LOGIC;

X: in STD_LOGIC;
Clock: in STD_LOGIC;
Z: out STD_LOGIC_VECTOR (1 downto 0));
end component FSM_examen;
signal RST : STD_LOGIC:='0';
signal X : STD_LOGIC:='0';
signal Clock : STD_LOGIC:='0';
signal Z: std_logic_vector (1 downto 0);
begin
fsm: FSM_examen port map (RST, X, Clock, Z);
instancia_1: process
begin
wait for 5 ns;
Clock <= not Clock;
end process;
instancia_2: process
begin
RST <= '1';
wait for 7 ns;
RST <= '0';
wait for 1 ms;
end process;

Quiz N.2 FSM

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Quiz N.2 FSM

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Johnny Gómez Marín Quiz N.

Port (RST:in std_logic;

Z: out std_logic_vector(1 downto 0));

architecture Behavioral of FSM_examen is

type state is (S0, S1, S2, S3, S4);

signal Current_state, Next_state: state;

if RST= '1' then

Current_state <= S0;

elsif (rising_edge(Clock)) then

Current_state <= Next_state;

Next_state <= S1;

elsif (X = '1') then

Next_state <= S3;

Next_state <= Next_state;

Next_state <= S0;

elsif (X = '1') then

Next_state <= S2;

Next_state <= Next_state;

Next_state <= S3;

elsif (X = '1') then

Next_state <= S4;

Next_state <= Next_state;

Next_state <= S3;

elsif (X = '1') then

Next_state <= S4;

Next_state <= Next_state;

Next_state <= S1;

elsif (X = '1') then

Next_state <= S4;

Next_state <= Next_state;

Salidas: process (Current_state)

when S0 => Z <= "01";

when S1 => Z <= "00";

when S2 => Z <= "11";

when S3 => Z <= "11";

when S4 => Z <= "01";

transiciones: process(RST, Current_state, X)

if RST= '1' then

Next_state <= S0;

Next_state <= S1;

elsif (X = '1') then

Next_state <= S3;

Next_state <= Next_state;

Next_state <= S0;

elsif (X = '1') then

Next_state <= S2;

Next_state <= Next_state;

Next_state <= S3;

elsif (X = '1') then

Next_state <= S4;

Next_state <= Next_state;

Next_state <= S3;

elsif (X = '1') then

Next_state <= S4;

Next_state <= Next_state;

Next_state <= S1;

elsif (X = '1') then

Next_state <= S4;

Next_state <= Next_state;

Salidas: process (Current_state)

when S0 => Z <= "01";

when S1 => Z <= "00";

when S2 => Z <= "11";