CTC5118 DS Draft11 20200817 en PDF

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Centec CTC5118 nt
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Draft Datasheet ia
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Issue
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Draft 11
Date
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2020-08-17
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Copyright © Centec Networks (Suzhou) Co., Ltd. All rights reserved.
No part of this document may be reproduced in any form or by any means without prior written permission
of Centec Networks (Suzhou) Co., Ltd.
The Centec trademarks, service marks ("Marks") and other Centec trademarks are the property of Centec
Networks. Centec Switch Series and Chips Series products of marks are trademarks or registered
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prior written consent of Centec.
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trademarks of Centec Networks (Suzhou) Co., Ltd. You are not permitted to use these Marks without the
holders.
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All other trademarks and trade names mentioned in this document are the property of their respective
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Notice
The purchased products, services and features are stipulated by the contract made between Centec and
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the customer. All or part of the products, services and features described in this document may not be
within the purchase scope or the usage scope. Unless otherwise specified in the contract, all statements,
or representations of any kind, either express or implied.

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information, and recommendations in this document are provided "AS IS" without warranties, guarantees
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The information in this document is subject to change without notice. Every effort has been made in the
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preparation of this document to ensure accuracy of the contents, but all statements, information, and
recommendations in this document do not constitute the warranty of any kind, express or implied.
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Centec Networks (Suzhou) Co., Ltd.
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Address
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#Suite 4F - 13/16, Building B, No.5 Xing Han Street,
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Suzhou Industrial Park, Suzhou, China
Telephone
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CTC5118 Draft Datasheet
About This Document
Table of Contents
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1 About This Document ............................................................................. 10
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1.1 Purpose and Audience ..................................................................... 10
1.2 Acronyms and Abbreviations .............................................................. 10
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1.3 Reference.................................................................................... 11
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1.4 Revision History ............................................................................. 12
1.5 Support ...................................................................................... 13
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2 General Description ............................................................................... 14
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3 Device Introduction ............................................................................... 15
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3.1 Core and I/O Bandwidth ................................................................... 16
3.1.1 180G Core Bandwidth................................................................................... 16
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3.2 Feature List ................................................................................. 17
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3.3 Target Application .......................................................................... 26
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3.3.1 Enterprise network access switch .................................................................... 26
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3.3.2 Chassis Management .................................................................................... 27
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3.3.3 Access CPE of network operator ...................................................................... 28
4 SmartPort™ Overview ............................................................................. 29
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4.1 Architecture Overview ..................................................................... 29
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4.2 SerDes Macro ................................................................................ 30
4.3 SmartPort™ Group .......................................................................... 30
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4.4 Typical Configuration ...................................................................... 31
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5 Memory Profile ..................................................................................... 32
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6 System Interface ................................................................................... 33
6.1 Overview .................................................................................... 33
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6.2 Network Interface .......................................................................... 33
C6.2.1 Interface Signals ......................................................................................... 34

6.2.2 USXGMII-M Interface .................................................................................... 35
6.2.3 1GbE/2.5GbE Port ....................................................................................... 35
6.2.4 5GbE ....................................................................................................... 36
6.2.5 10GbE port................................................................................................ 36
6.2.6 40GbE Port ................................................................................................ 37
6.3 CPU Interface ............................................................................... 37
6.4 PCIe Interface ............................................................................... 38
6.5 I2C Master Interface ....................................................................... 38
Draft 11 (2020-08-17) 3 Copyright © Centec Networks (Suzhou) Co., Ltd.

About This Document
6.6 I2C Slave Interface ......................................................................... 38

6.7 PTP and Sync Ethernet Interface ......................................................... 39
6.7.1 Sync Ethernet Interface ................................................................................ 39
6.7.2 PTP Interface Signals ................................................................................... 40
6.8 SMI Interface ................................................................................ 40
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6.8.1 SMI Interface Signals .................................................................................... 40
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6.8.2 Operation ................................................................................................. 41
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6.9 MAC LED Interface .......................................................................... 41
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6.9.2 LED Interface Signals ................................................................................... 42
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6.9.3 LED Bit Stream Encode Modes......................................................................... 42
7 Pin-Map and Pin-Out table ....................................................................... 44
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7.1 Pin Map ...................................................................................... 44
7.2 Pin-Out Table ................................................................................ 50
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8 Pin Information ..................................................................................... 70
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8.1 Pin information –Grouped by function ................................................... 70
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9 Electrical Specifications .......................................................................... 81
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9.1 Absolute Maximum Rating ................................................................. 81
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9.2 Recommended Operating Conditions .................................................... 82
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9.3 Power-Up and Power-Down Specifications .............................................. 83
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9.4 Boot Up/Reset Sequence .................................................................. 84
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9.5 Power Supply and Power Consumption .................................................. 84
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9.6 Interface I/O DC Specifications........................................................... 85
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9.6.1 3.3V General I/O Specifications ...................................................................... 85
9.6.2 1.8V General I/O Specifications ...................................................................... 85
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9.6.3 3.3V I2C I/O Specifications ............................................................................ 86
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9.6.4 1.2V/3.3V MDIO I/O Specifications................................................................... 86
9.6.5 1.8V/3.3V eMMC I/O Specifications .................................................................. 87
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9.6.6 LVDS I/O Specifications ................................................................................. 87
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9.6.7 DDR3/4 I/O Specifications ............................................................................. 88
9.6.8 HSS SerDes Electrical Specifications ................................................................. 88
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10 AC Timing........................................................................................... 89
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10.1 Clock Source Supply ...................................................................... 89
10.2 Recovery Clock Output ................................................................... 91
10.3 I2C Interface Timing Parameter ......................................................... 91
10.4 MDC/MDIO Interface Timing ............................................................. 92
10.5 OOBFC Interface Timing Parameter .................................................... 93
10.6 LED Interface Timing Parameter ........................................................ 94
10.7 HSS SerDes Signals Specifications ....................................................... 94
10.8 QSPI Interface Timing Parameter ....................................................... 95

About This Document
10.9 SPI Interface Timing Parameter ......................................................... 95

10.10 eMMC Interface Timing Parameter .................................................... 96
10.11 DDR3/DDR4 Timing Parameter ......................................................... 97
10.12 Trace Signals Timing Parameter........................................................ 99
11 Thermal Specifications ........................................................................ 100
11.1 Thermal Specification ................................................................... 100
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11.2 Reflow Profile ............................................................................ 101
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12 Package Mechanical Dimensions ............................................................ 102
12.1 Package Description ..................................................................... 102
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12.2 Marking .................................................................................... 102
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12.3 Package Dimension....................................................................... 103
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About This Document
List of Figure
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Figure 3-1 : IPE (Ingress Packet Engine) pipeline .......................................... 15
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Figure 3-2 : EPE (Egress Packet Engine) pipeline .......................................... 16
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Figure 3-3 : Chip performance for 180Gbps bandwidth ................................... 16
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Figure 3-4 : Enterprise network access switch application diagram..................... 27
Figure 3-5 : Chassis management application diagram.................................... 28
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Figure 3-6 : Access CPE of network application diagram ................................. 28
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Figure 4-1 : Data-path Architecture ......................................................... 29
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Figure 6-1 : Sync Ethernet Clock Scheme ................................................... 39
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Figure 6-2 : LED Interface Timing and Encoding Explanation............................. 41
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Figure 10-1 : Definition of timing of I2C..................................................... 92
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Figure 10-2 : MDC/MDIO Input Timing Diagram ............................................ 92
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Figure 10-3 : MDC/MDIO Output Timing Diagram .......................................... 93
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Figure 10-4 : FCIN_* Signals Input Timing Diagram ........................................ 93
Figure 10-5 : FCOUT_* Signals Output Timing Diagram.................................... 93
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Figure 10-6 : LEDCLK/MACLED Output Timing Diagram ................................... 94
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Figure 10-7 : QSPI_* Timing Diagram ........................................................ 95
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Figure 10-8 : SPI Interface Timing Diagram（For mode 3） .............................. 96
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Figure 10-9 : eMMC Interface Timing diagram.............................................. 97
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Figure 11-1 Device Reflow Profile........................................................... 101
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Figure 12-1 : Device Marking ................................................................ 102
Figure 12-2 : Top view ........................................................................ 103
Figure 12-3 : Bottom View ................................................................... 104
Figure 12-4 Side View ........................................................................ 105

About This Document
List of Tables
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Table 1-1 : Acronyms and Abbreviations ..................................................... 10
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Table 1-2 : Reference Documentation ....................................................... 11
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Table 3-1 : Features List ....................................................................... 17
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Table 4-1 : SmartPort™ Group Configuration in Octal SerDes Macro ..................... 31
Table 4-2 : SmartPort™ Group Configuration in 2-lane SerDes Macro .................... 31
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Table 4-3 : Typical Configuration ............................................................. 31
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Table 5-1 : Typical FTM™ Profiles ............................................................. 32
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Table 6-1 : Interface Signals .................................................................. 34
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Table 6-2 : Sync Ethernet Signals ............................................................. 40
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Table 6-3 : Recovery Clock Frequency of Different port speed........................... 40
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Table 6-4 : PTP signals ......................................................................... 40
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Table 6-5 : SMI Interface Signals.............................................................. 41
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Table 6-6 : LED Interface Signals ............................................................. 42
Table 6-7 : LED Bit Stream Encode Modes ................................................... 42
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Table 7-1 : Pin Map Top View Column 1-6 ................................................... 44
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Table 7-2 : Pin Map Top View Column 7-12 .................................................. 45
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Table 7-3 : Pin Map Top View Column 13-18 ................................................ 46
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Table 7-7 : Pin-Out Table (by Ball) ........................................................... 50
Table 7-8 : Pin-Out Table (by Pin name) ..................................................... 60
Table 8-1 : Pin information –Function Signals ............................................... 70
Table 8-2 : Pin information –Power and Ground ............................................ 78
Table 9-1 : Maximum Ratings ................................................................. 81
Table 9-2 : Recommended Operating Conditions ........................................... 82

About This Document
Table 9-3 : Recommended Power Supply .................................................... 82

Table 9-4 : Power Up and Power Off Timing Parameters .................................. 83
Table 9-5 : Maximum Power Consumption Estimation ..................................... 84
Table 9-6 : Typical Power Consumption Estimation ........................................ 84
Table 9-7 : Power Requirement for Different Voltage Jc=110 °C (Estimation) ......... 84
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Table 9-8 : 3.3V LVCMOS driver/receiver dc specification ................................ 85 i
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Table 9-9 : 1.8V LVCMOS driver/receiver dc specification ................................ 85
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Table 9-10 : 3.3V I2C I/O dc specification ................................................... 86
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Table 9-11 : 1.2V/3.3V MDIO DC specification (VDDIO = 1.2V) ........................... 86
Table 9-12 : 1.8V/3.3V eMMC specification (VDDIO = 1.8V) .............................. 87
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Table 9-13 : LVDS I/O receiver dc specification ............................................ 87
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Table 9-14 : DDR3/4 I/O dc specification ................................................... 88
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Table 9-15 : HSS SerDes Absolute Maximum Ratings ....................................... 88
Table 10-1 Characteristics of the SerDes interfaces reference clock.................... 89
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Table 10-2 : HSS SerDes External Reference Clock Requirements ....................... 90
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Table 10-3 : PCIe Reference Clock Jitter and Swing Requirement ....................... 90
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Table 10-4 : SerDes Recovery Clock Output Frequency ................................... 91
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Table 10-5 : Characteristics of the SDA and SCL for S-mode, from THE I 2C-BUS
SPECIFICATION ................................................................................... 91
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Table 10-6 : MDC/MDIO Interface Timing Parameters ..................................... 92
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Table 10-7 : OOBFC Interface Timing Parameters .......................................... 93
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Table 10-8 : LED Interface Timing Parameters ............................................. 94
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Table 10-9 : HSS SerDes TX Signals Characteristics ........................................ 94
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Table 10-10 : HSS SerDes RX Signals Characteristics....................................... 94
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Table 10-11 : QSPI Interface Timing Parameters ........................................... 95
Table 10-12 : SPI Interface Timing Parameters ............................................. 95
Table 10-13 : eMMC Interface Input Timing Parameters .................................. 96
Table 10-14 : eMMC Interface Output Timing Parameters ................................ 97
Table 10-15 : DDR4 Interface Timing Parameters .......................................... 97
Table 10-16 : DDR3 Interface Timing Parameters .......................................... 98
Table 10-17 : Trace Interface Timing Parameters .......................................... 99

About This Document
Table 12-1 : Package Mechanical Size ...................................................... 102

Table 12-2 Descriptions of marking ......................................................... 103
Table 12-3 : Package Size Parameters ...................................................... 105
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About This Document
1 About This Document

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1.1 Purpose and Audience n t
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This document describes the functionality, interfaces, signals, physical requirements, and the
operating environment of CTC5118. And it is intended for hardware, software, and application
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developers who need to understand CTC5118.
1.2 Acronyms and Abbreviations C

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Table 1-1 : Acronyms and Abbreviations
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Acronym
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ACL
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Access Control List
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AFT Accept Frame Type
APS
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Automatic Protection Switching
CFlex LAG
n Centec Flexible Link Aggregation
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DDR Double Data Rate
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DRR Deficit Round Robin
DVMRP
ECMP
o n Distance Vector Multicast Routing Protocol
Equal-Cost Multi-Path
GE
C Gigabit Ethernet
GRE
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IGMP
ISATAP
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Intra-Site Automatic Tunnel Addressing Protocol
IVI
e IPv4-derived IPv6
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IVL
LPM
Independent VLAN Learning
Longest Prefix Matching
LSP Label Switch Path
MAC Media Access Control
MDC Management Data Clock
MDIO Management Data Input/output
MSTP Multiple STP
NAPT Network Address Port Translation

About This Document
Acronym Definition
NAT Network Address Translation
NAT-PT Network Address Translation-Protocol Translation
NVGRE Network Virtualization using Generic Routing Encapsulation
OAM Operation Administration Management
PBR Policy Based Route
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PBT Provider Backbone Transport
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PHP
RPF
Penultimate Hop Popping
Reverse Path Forwarding
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RSPAN Remote Switched Port Analyzer
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RSTP Rapid STP
SIIT Stateless IP/ICMP Translation
SP Strict Priority
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STP Spanning Tree Protocol
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SVL Shared VLAN Learning
TCAM
VC Virtual Connection
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Ternary Content-addressable Memory
VFI
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Virtual Forwarding Instance
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VPLS Virtual Private LAN Service
VPWS
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Virtual Private Wire Service
VRF
nVirtual Route Forwarding
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VXLAN Overlaying Virtualized Layer 2 Networks over Layer 3 Networks
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WRR Weighted Round Robin
XAUI
DXAUI
o n 10 Gbps Attachment Unit Interface
20 Gbps Attachment Unit Interface
XLAUI
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QSPI
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SPI
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1.3 Reference e
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Table 1-2 : Reference Documentation
Documents Name Description
Advanced Hardware design guide Advanced hardware design info with CTC5118

About This Document
1.4 Revision History

Date Version Description Page
2020-03-06 Draft 01 First release N/A
2020-03-10 Draft02 Update the description about pin BOOT_RESV in 71

table 8-1
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2020-03-16 Draft03 Update the description about pin AVDD18_RSV, 79, 80
VDD_RSV in table 8-1
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2020-03-24 Draft04  Upate HSS12.5G SerDes to HSS SerDes with the 13, 16, 19, 26, 30,
speed 1.25Gbps~10.3125Gbps 32, 33, 69, 70, 80,
 Update the Buffer size to 3MB
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89~91, 95, 96
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 Delete MACsec and CapWap
2020-04-08 Draft05 Update the diagram of Sync Ethernet Clock 39
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Scheme
2020-04-20 Draft06 Add thermal specification 100
2020-06-02 Draft07
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Add note[7] for table 8-1, and delete the
“PD/PU” indication of output only pin.
69, 75, 76, 77
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Update ESD reference standard in table 9-1 80
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Add Reflow Profile 100
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2020-06-09 Draft08 Update the BOOT_RESV1 default connect to GND 71
2020-07-03 Draft09 t
in table 8-1
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Update table 9-7 84
2020-07-14 Draft10
f ide Add note “NOTE： All interfaces need to be

configured for normal operation. ” for section
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Delete “NOTE：For DDR Interface, it only
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supports single-die PCB with 8-bit width DDR.”
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Add working condition for Endpoint mode that 38
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the device needs to release reset(RST_SUP_B)
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Add “It is recommended that the device and 38
e external CPU use the same origin clock.” for
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PCIe interface
Update Boot_usb_vreg_byp description in table 76
8-1 to:
0： MSH internal logic uses clock generated from
MSH_CLK
1: MSH internal logic uses internal clock.
It is recommended to implement compatible
design, and the default is pull-down.
Delete Note3 for table 9-2 82

About This Document
Date Version Description Page

Modify some typos and misspellings
Update the QSPI_CLK rate to 25MHz in table 8-1 90
Update the USB_VBUS0 description in table8-1 75
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to “OTG function not supported. Leave this pin
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floating”.
2020-08-17 Draft11 Update IPv6 LPM to 3K in table5-1 32
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Add Ta range in table 9-2 82
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1.5 Support on
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More information such as register specification, white paper, application nodes can be found on
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Centec website. For VIP user, please login the website www.centecnetworks.com with your user
name and password. The materials can be found under support/Products Document. The user
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could also visit feedback.centecnetworks.com for bug/new requirements report.
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For anything not clear, please send mail to support@centecnetworks.com for further help.
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General Description
2 General Description
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The Centec® TsingMa.CX CTC5118 device is a purpose built device to address the challenge in
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the recent network evolution such as Cloud computing. To offer enhanced system function
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integration with lower system BoM cost, the TsingMa.CX family combines a feature-rich switch
core and an embedded ARM A53 CPU Core running at 800MHz/1.2GHz. TsingMa.CX provides
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180G I/O bandwidth and 180Gcore bandwidth. It equips 18 of 12.5G SerDes Lanes. As a highly
integrated chip, TsingMa.CX is an ideal choice for edge switch design in Enterprise Network
switch with form factors like 24x 1GbE+8x10GbE or 48x1GbE + 6x10GbE.
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As the 6th generation of Centec TransWarp™ family, TsingMa.CX is built on the field proven
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Centec switch architecture to provide Layer2, Layer3, MPLS, and VXLAN features. In addition,
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leveraging the internal IPFIX Engine, TsingMa.CX supports the statistics of session-based service,
packet-drop, and the watermark of latency and jitter. The device offers the advanced features
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such as Segment Routing up to 10 level MPLS Labels, IEEE1588v2, etc. TsingMa.CX also supports
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flexible programmability for tunneling process which identifies the unknown Layer2, Layer3 and
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Layer4 tunnel.
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The key features as supported by CTC5118 are listed below:
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 3MB embedded packet/table shared buffer with self-tuning threshold for more evenly and
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efficient buffer usage
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On-chip Flow Tracing Engine for advanced NetFlow sampling (IPFIX)
CoPP (Control Plane Policing) for CPU traffic protection
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On-chip OAM engine supporting Ethernet OAM/ BFD/ MPLS-TP OAM
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Embedded traffic manager providing 12 basic queues per port and 3K extra service queues
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which can be assigned to each port flexibly to meet the application requirement
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Support NVGRE and VXLAN
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Support Data Center Features including PFC, ETC, VEPA, TRILL, FCoE, etc.
Cut-Through forwarding for lower and fixed latency
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Rich monitoring and diagnostic features for troubleshooting
Large flow table for SDN/ OpenFlow
 IPv4/IPv6 dual-stack forwarding with translation technologies
 Support Jumbo Frame up to 9600 Bytes

Device Introduction
3 Device Introductionl
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CTC5118 follows the same truly distributed and service-aware architecture of Centec
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TransWarp™ Family to provide:
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 Truly distributed ingress/egress packet processing for both unicast and multicast
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 Scalable for both pizza-box and central forwarding system with dynamic port configuration
IPE Destination Processing

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Storm Control
Learning
Policing
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CoPP
ACL/ TCAM Processing
Forwaring
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OAM
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L2 Bridging
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Per-hop Behavior
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L3 Routing
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Packet Flow
Lookup Manager
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Decapsulation
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Interface Mapper
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SCL
1st Parsing
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Figure 3-1 : IPE (Ingress Packet Engine) pipeline
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Device Introduction
EPE
Epe Header Adjust
Egress Parsing
NextHopMapper
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Egress Feature Operation
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Routing | MPLS | Bridging | FCoE | TRILL
Packet Flow
Layer 3 Packet Editing

MPLS | NAT | Tunnel | TRILL
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Layer 2 Packet Editing
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Ethernet | PBB/PBT | Loopback
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Egress ACL/ TCAM Processing
Egress Per-hop Behavior
Egress Policing
Egress OAM C
ec Egress Header Editing
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Figure 3-2 : EPE (Egress Packet Engine) pipeline
3.1 Core and I/O Bandwidth a l C

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3.1.1 180G Core Bandwidth n
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CTC5118 delivers 180Gbps line rate performance for all packet-length, all ports can meet the
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requirement of the RFC2544 test.
o 120.00%
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Chip Performance
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t 60.00%
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Packet Rate %
40.00%
20.00% Datapath %
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64
77
90
103
116
129
142
155
168
181
194
207
220
233
246
259
Packet Length (Bytes)
Figure 3-3 : Chip performance for 180Gbps bandwidth

Device Introduction
3.2 Feature List

Table 3-1 : Features List
Feature Description
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Octal SerDes Macro Two HSS Macros provide up to 16 SerDes Lanes speed at 1.25G~10.3125G. Flexible
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SerDes configuration to operate in any of the following port mode (For more
details, please refer to CTC5118_ Port_Application_Note):
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 40GbE (4-lane) KR4/ CR4/ SR4/ ER4/ LR4/ with Base-R FEC (FC (2112,2080))
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 10GbE (1 lane) XFI/ SFI/ KR/ CR/ SR/ ER/ LR/ with Base-R FEC (FC (2112,2080))
10GbE (4-lane) XAUI
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
 5GbE (1-lane) QSGMII (Only 12 of QSGMII PCS interfaces are supported)
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 2.5GbE 2500 BASE-X (1-lane)
 1GbE (1 lane) SGMII with 10M/100M/ 1000M SGMII AN, IEEE802.3 clause 37 AN
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1000 BASE-X (1-lane) with 1000M IEEE802.3 clause 37 AN
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 10G USXGMII-M Multiple Mode: 2 of 10M/100M/1G/2.5G/5G ports or 4 of 10M/
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100M/ 1G/2.5G/ mode(Only support 12 of USXGMII PCS interfaces)
2-Lane SerDes Macro
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2 high speed SerDes lanes to provide 1.25G~10.3125G lane speed with the following
standards:

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10GbE (1 lane) XFI/ SFI/ KR/ CR/ SR/ ER/ LR/ with Base-R FEC (FC (2112,2080))
 2.5GbE 2500 BASE-X (1-lane)
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1GbE (1 lane) SGMII with 10M/100M/ 1000M SGMII AN, IEEE802.3 clause 37 AN
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
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1000 BASE-X (1-lane) with 1000M IEEE802.3 clause 37 AN
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Interface 100M/1G/2.5G/5G/10Gbps speed, configured or auto-negotiated
Standard MAC MIB
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Optional network port act as dedicated CPU traffic port
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x1 PCIe 2.0 for External CPU configuration and traffic interface
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OoBFC
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CPU burst I/O access mode
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MDIO 1G/10G read/write/scan
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I2C Master Interface
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I2C Slave Interface
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CPU Interface  2 of SGMII interfaces
 GPIO Interface
 DDR3/4 Interface
 QSPI interface
 SPI Interface
 MDIO Interface
 USB2.0 Interface
 PCIe Gen1/Gen2
 3 of UART Interfaces
 eMMC Interface

Device Introduction
Feature Description
2
 2 of I C Soc Interface
L2 Bridging SVL and IVL
Hardware-based MAC learning and aging
Station movement control
Fast MAC flush per port/VLAN/port + VLAN
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Per VLAN / destination port controlled unknown discard for unicast /multicast /
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broadcast
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Unknown unicast/multicast/broadcast to CPU
Static MAC
Per port L2 protocol packet processing
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Port random log
Access/trunk/hybrid port support
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Flexible AFT (per port accept/deny packets according to any combination of C-TAG
and S-TAG)
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SW MAC learning and aging
Black Hole MAC
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White List
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Dump MAC by port/ vlan / port+ vlan /MAC/MAC-fid
a
Dump MAC by dynamic /static/all
t i
Dump MAC sort by trie tree
n
Logic port learning for L2VPN
e
d
VLAN Support C-VLAN and S-VLAN
n fi
Global C-VLAN TPID and S-VLAN TPID setting and per port S-VLAN TPID selection
Ingress and egress VLAN filtering
o
Single or double tags VLAN translation on both ingress and egress
C
Any combination of adding/replacing/removing operation for CVID /C-TAG CoS /
c
C-TAG CFI / SVID / S-TAG CoS / S-TAG CFI on both ingress and egress
t e VLAN classification based on MAC SA/MAC DA/IP SA/IP DA/any L2 fields

combination/protocol/port
e n Single or double tag VLAN switching
C
Private VLAN
VLAN RX / TX statistics
Spanning Tree，MSTP, RSTP

L2 Multicast Per VLAN IGMP packet processing
L2 multicast to physical port or tunnel
PIM snooping
Discard or send to CPU for unknown multicast packets
IPDA, MACDA two level lookup
IP base l2 multicast

Device Introduction
Feature Description
Storm Control Per port / VLAN storm control
Both bits per second and packets per second rate limit
Support unknown unicast /unknown multicast/ broadcast/ known unicast /known
multicast /all unicast /all multicast rate limit
Per MAC address rate limit
a l
Per port per packet type configurable threshold
t i
n
Port LAG Route Selection：
e
 Static load balance for LAG
d
Regular and Random round-robin for LAG
fi

 Flowlet-based dynamic load balance for LAG
on
 Resilient hashing for LAG
 Forwarding mode for local members with higher priority
Fault Tolerance：
C
c
 Hardware-based LAG failover mechanism
Channel or CFlex Route Selection：
t e
n
LAG  Static load balance for LAG
e
 Regular and Random round-robin for LAG
C
 Flowlet-based dynamic load balance for LAG
l
 Resilient hashing for LAG
Fault Tolerance：

t i a
Hardware-based LAG failover mechanism
ECMP Route Selection：
e n
d
 Static load balance for ECMP
fi
 Regular and Random round-robin for ECMP
n
 Dynamic load balance for ECMP
o
 Resilient hashing for ECMP
C
Fault Tolerance：
c
 Hardware-based ECMP failover mechanism
e
 Self-Healing for ECMP
n t
HASH mechanism Fields for HASH:
L2: MAC SA / MAC DA / SVID / CVID / S-TAG CoS / C-TAG CoS/ EtherType
e

 L3: IP DA/IP SA/IP header protocol/MPLS label
C 

L4: TCP src/dest port, UDP src/dest port
Tunnel: Inner header's fields/outer header's fields/Inner+outer
Based on entropy information, for example: VXLAN, NVGRE, MPLS with entropy
label
Symmetric hashing
L3 Routing 4K Layer 3 interface, including VLAN interface and routed port
Per L3 interface L3 protocol packet processing
Per VLAN DHCP/ARP handling
IPv4 and IPv6 host route

Device Introduction
Feature Description
Algorithm based IPv4 and IPv6 LPM (TCAM-based lookup is also supported)
Public and Private route
ECMP
Loose and strict RPF check
VRRP
a l
ICMP redirect check
t i
IP Tunneling
Virtual Route Forwarding, up to 8K instances
Static V4inV4, V6inV4, V4inV6, V6inV6 tunnel
e n
6to4 tunnel
fi d
on
ISATAP tunnel
GRE tunnel with Ethernet/IPv4/IPv6/MPLS/UserDefinedType as payload
UDP tunnel
C
c
uRPF
IP Overlay
e
VXLAN / NVGRE / VXLAN-GPE / GENEVE technology
IP Multicast Routing (S, G), (*, G), (*, *) support
n t
e
Multicast RPF check
C
Physical replication (to port) and logical replication (to VLAN)
l
Fallback bridge on IPMC lookup failure
a
i
Discard or send to CPU for unknown multicast packets
t
n
PIM Sparse and Dense mode
Bidirectional PIM
d e
fi
Can be replicated to any port, VLAN, tunnel
n
Programmable Encap/ Decap and flexible editing behavior on tunnel such as PPPoE and G.INT
o
Tunnel
XGPON Pipeline Flexible process pipeline for XGPON application
Network Security
C
Port/MAC based 802.1X
e c Port Isolation
n t 

Per port isolation
Unidirectional and bidirectional
e  Isolation on flooded packets only or all packets
C Binding with any combination of IP/ MAC/ Port/ VLAN

DDoS Attack Prevention for:
 Illegal MAC SA
 Illegal IP SA
 Land Attack (MAC SA==MAC DA or IP SA==IP DA)
 Null scan (TCP sequence number=0, control bits=0)
 SYN/SYN-ACK flooding
 Smurf attack
Port/VLAN/System based MAC Limit

Device Introduction
Feature Description
Port Security
CPU Traffic Per protocol type rate limit
Protection Per group rate limit (multiple protocols can be grouped)
8 priority classes with SP/WFQ scheduling
Total CPU traffic rate limit
a l
CoPP policing based on flow rules, with bps or pps
t i
ACL Both ingress and egress
e n
Rate limit can be based on bps (bits per second) or pps (packet per second) unit
Applied on port, VLAN, L3Interface, and LogicPort
fi d
on
8 parallel-lookup for ingress & 3 parallel lookup for egress ACL
Deep packet parsing up to 144 bytes
Match all L2-L4 fields
C
c
UDF
e
Actions supported:
 Permit/deny
n t
Redirect to port/L3 Nexthop/multicast group/tunnel
e

 Redirect to CPU with timestamp attached


Priority and color remark

l C
Mirror (port, L3 Nexthop, multicast group, tunnel, CPU)
a

 Flow policing
t i
n
 Statistics
e
 Add/remove/replace any fields in STAG and/or CTAG
d
 Deny bridge
fi
Deny learning

n
Deny routing

o
Random log to CPU
C
 Select to on-chip flow tracing
c
N-Flow™ technology
t e Specify CPU Queue Id for traffic to CPU
n
SGT
e
 Classify based on Port, VLAN, L3Interface and LogicPort
C
 Flexible classify based on L2-L4 fields, and FIB
 Support SGT encapsulation
 Support SXP (identify and redirect to CPU)
Class group based ACL
 Classify based on Port, VLAN, L3Interface and LogicPort
 Flexible classify class group based on L2-L4 fields
Policy based routing
Forwarding Information as ACL key field
Flexible ACL TCAM Allocation
Policing and QoS SrTCM (RFC 2697), TrTCM (RFC 2698) and modified TrTCM (RFC 4115)

Device Introduction
Feature Description
Support both color-aware and color-blind mode
Fine granularity down to 8K bps
Up to 16M Bytes burst size
256 metering/policing profiles
MEF 10.3 BWP
a l
Both ingress and egress policing
t i
Port/ Flow/ VLAN based policing
PPS based policing
e n
Aggregated policing
fi d
on
WRED congestion avoidance on per-queue basis, support arking for TCP traffic
Tunnel ECN, flow-based ECN，stacking-based ECN
C
CIR/PIR shaper with minimum guaranteed bandwidth and maximum regulated
c
traffic for each queue.
e
8 basic queues per port
n t
Each of 64 Ports has 4 NetCtl queue (2 high priorities for CPU, 2 low priorities for
flooding and log/span)
e
384 flexible queue groups which can be bound to ports without limitation
l C
8 scheduling priorities in a base queue group, SP for different priorities, WFQ for
a
queues with the same priority.
t i
8 scheduling priorities in a extend queue group, SP for different priorities, WFQ for
e n
queues with the same priority.
Configurable CIR/PIR weight, CIR is SP, PIR is SP/WFQ
fi d
Priority propagation is from group to channel, 8 scheduling priorities in a group
could be mapped to 4 scheduling priorities in a physical port
o n
Configurable WFQ weight between different groups
C
Traffic rate regulation for all destinations by FPS (frame per second) unit
Support packet aging and queue flush (only extend queue support)
e c Ingress/Egress Resource Manage
n t Flexible PHB Mapping
e
MPLS Per system/per interface label space
C
Full label space
Penultimate Hop Pop
L-LSP and E-LSP support
Pipe/Short Pipe/Uniform Model LSP
Parse/push/pop/lookup label number: 8/10/3/3
Optimized Multi-Path MPLS, MPLS IP based ECMP
Entropy label and flow label
Martini Encapsulation
Raw mode and tagged mode PW

Device Introduction
Feature Description
VPWS (port AC, VLAN AC)
VPLS (port AC, VLAN AC)/H-VPLS
L3VPN
Multicast MPLS
Upstream MPLS
a l
MPLS over GRE Tunnel
t i
l2/l3 Gateway
Using TCAM resolve hash conflict
e n
Ethernet OAM 802.1ag Connectivity Fault Management
fi d
on
Support both UP MEP and Down MEP
MIP
CCM (interval 3.3ms/10ms/100ms/1s/60s/600s)
C
c
Link Trace (LTM/LTR)
Loopback (LBM/LBR)
t e
n
CSF
RDI
e
APS/RAPS
AIS
l C
Link OAM
t i a
n
802.3ah EFM
e
Y.1731 Performance Measurement
d
fi
One-way/Two-way DM
n
Single-end/Dual-end LM
o
QinQ OAM
C
VPLS/VPWS OAM
c
BFD IP BFD
t e LSP BFD
n
VCCV/PW BFD
e VXLAN BFD
C
NVGRE BFD
S-BFD
Micro-BFD
TRILL BFD
MPLS-TP OAM Y.1731 based
BFD based
Network Performance RFC2544 for L2/L3
Management Y.1564 for L2/L3
TWAMP/OWAMP

Device Introduction
Feature Description
MEF SAT Testing (MEF46/MEF48/MEF49)
SLM/SLR
Automatic Protection Protocol/topology independent mechanism
Switch One-bit flap quick switch. No need to flush forwarding table
2-level protection switch
a l
Support both unicast and multicast
t i
Support both source and sink end
Can be comprehensively applied to G.8031/G.8032/G.8131/G.8132/IETF
e n
fi
EAPS/Smart Link and all other possible protection switch protocols
Hardware based APS switch d
on
Mirror Both ingress and egress mirror
C
Port/VLAN/Flow based mirror
32 mirror sessions
e c
Mirror destination: port/VLAN/tunnel/multicast group/CPU
With extended information
n t
e
 Arrival timestamp
 Forwarding latency
 Application aware
l C
a
TCP session-sensed load balance
t i
Packet length truncation for log or to CPU
Discard packet mirror

e n
normal + discard mirror

fi d
only discard mirror
n
Network Time IEEE 1588-2008 with up to 4 management domains
o
Synchronization OC/BC/TC support for both 1-step and 2-step mode
C
PTP over Ethernet/IPv4/IPv6/MPLS/PWE
c
PTP timestamp granularity is 4ns with 250MHz reference clock
t e G.8261 compliant Synchronize Ethernet with all SerDes capability
n
SyncE reference selection
e Up to 3 SyncE clock output
C
China Mobile ToD
Monitor SyncE references
Data Center Bridging Cut-Through forwarding for low latency
PFC (Priority Flow Control)
 PFC reception and stop responding traffic
 PFC reception timer
 Transmit PFC frame
 8 classes flow control per port
ETS (Enhanced Transmission Selection)
 8 user configured TCs

Device Introduction
Feature Description
 3 user configured TCGs
 SP and DRR scheduling
 BW configuration with at least 1% granularity
Virtualization
l
 802.1Qbg VEPA (Virtual Ethernet Port Aggregation)
a
 802.1br Port Extender
 Reflective relay
t i
Port virtualization by S-VLAN on both ingress and egress
n

 Multicast to all virtual ports
d e
fi
 M-Tag insertion in case of multicast to port extender
TRILL
on
 VLAN Mapping
 Multi nickname per system
 Multi distribution trees
C
Distribution tree selection based on HASH
c

t
Multi-destination frame tree adjacency check
e
n
 Multi-destination frame RPF check
e
 Multi-destination frame parallel links check
 Multi-destination frame port group check

l C
Pruning distribution tree per-VLAN
a
 Pruning distribution tree by IGMP MLD snooping
 FCoE over TRILL
t i
FCoE
 VSAN
e n

fi d
FCoE traffic isolated from other
FCoE access switch in switch mode


o n
FCoE access switch in NPV mode
FPMA
C
 SPMA
c
 FCoE virtual link check
e
 FCoE switching by monitoring FC header
n t MLAG
e
 MLAG Isolation
C
Address Translation NAT
NAPT
NAT-PT
NAT64
IVI
CloudStacking™ Flexible topology: Ring/Tree/Line/Full mesh
Flexible, expansible and compatible stacking Header
Spine-leaf
Horizontal stacking: stacking cross L2/L3 network

Device Introduction
Feature Description
Source node based load balance and loop break
Stacking on any network port interface
TCP Sensed Flow Elephant flow detection based
Performance Tuning  Priority changing
 Dynamic load balancing
a l
i
Fast packet aging for retransmitted packet
High bandwidth ultra-low latency (HULL) policy with DCTCP
n t
e
On-chip flow tracing to support enhanced IPFIX
Hardware IP FIX(Flow Tracing）

 Hardware Overlay Tunnel Learning
fi d
on
 NetFlow Random Sampling and interval sampling
 Hardware based aging
 New Flow Export
C
c
 First N packet for new flow log
e
Export based packet counter overflow or packet byte overflow or time expired or
t

TCP session closed
Diagnosis
 Support IPFIX only when RPF Check Fail
Active Buffer Monitoring
e n
Active Latency Monitoring
l C
Watermark
Software defined counters
t ia


Off-chip statistics
e n
On-chip timer trigger DMA operation (DMA @) with Statistic chaining
fi d
On-chip Packet flow path Debug Information collection
VM-Aware

o n
Deep insight for overlay traffic to apply:
TCP sensed flow performance tuning
DMA
C
Packet RX/TX
c
 User Mode and Kernel Mode
e
 SDK in User Mode, Packet TX/RX in Kernel
n t DMA Info for IPFIX/Learning/Aging/SDC/Monitor
e
DMA read/write table
C
DMA Sync MAC stats
HASH Dump
3.3 Target Application

3.3.1 Enterprise network access switch
CTC5118 provides two typical form factors for different enterprise applications:

Device Introduction
 24 x 1GbE + 8x10GbE
 48x1GbE + 6x10GbE
Highlights:
 Low power consumption and low latency
 Enhanced NetFlow
a l
i
FAN FAN FAN DDR NoR Flash
t
Conector Conector Conector
e n
d
FAN Conector CPU
fi
subsystem
on
CTC5118
C
Clock HSS0 HSS1 HSS2
PSU Generator ......
12 x QSGMII
e c
t
4*QSGMII
PHY
4*QSGMII 2*QSGMII
2*QSGMII
4*QSGMII
n
PHY
PHY PHY
PHY
PHY
e
6 x XFI
l C
t i a
n
48 x 1GbE 6 x 10GbE
d e
Figure 3-4 : Enterprise network access switch application diagram
3.3.2 Chassis Managementf i

o n
CTC5118 is well defined for chassis Management applications with integrated 18 of 10.3125G
C
SerDes. The typical form factor in master board is 12x1G or 12x10G
e c
t
en
C

Device Introduction
DDR NoR Flash

FAN FAN
Conector Conector
CPU
FAN Conector subsystem
CTC5118
a l
Clock
t i
PSU
Generator
HSS0 HSS1 HSS2
e n
12 x XFI
fi d
on
C
12 x 10GbE
e c
Figure 3-5 : Chassis management application diagram
n t
3.3.3 Access CPE of network operator e
Typical Form factor:
l C
 8x1GbE + 2x10GbE
t i a
n
de
DDR NoR Flash
f i
Clock
Generator
o n
CPU
subsystem
C CTC5118
e c
PSU
n t HSS0 HSS1 HSS2
e 4 x SGMII
C 4 x SGMII
4*SGMII
4*SGMII
4*SGMII
4*SGMII
PHY
PHY
PHY
PHY
2 x XFI
8 x 1GbE 2 x 10GbE
Figure 3-6 : Access CPE of network application diagram

SmartPort™ Overview
4 SmartPort™ Overview
i a l
4.1 Architecture Overview n t
d e
fi
Figure 4-1 shows the data-path architecture of CTC5118. CTC5118 features 18 SerDes Lanes
which there are grouped into 3 HSS Macros. There are two HSS Macros with 8 SerDes Lanes
on
called Octal SerDes Macro. The other one is called 2-lane HSS Macro with 2 SerDes Lanes. Each
SerDes lane provides up to 10.3125Gbps lane speed.
 Octal HSS Macro
C
− 2 Groups
e c
− Speed: 1.25Gbps ~ 10.3125Gbps
n t
e
− Each Macro: 8 Lanes
C
 2-lane HSS Macro
− 1 Groups
a l
− Speed: 1.25Gbps ~ 10.3125Gbps
t i
− Each Macro: 2 Lanes
e n
fi dCTC5118
ARM A53 Core
o n OAM Engine
C Integrated Packets Buffer
e c Traffic Management
t
Iloop
Eloop
n
Shared
e
IPE Resource EPE
(Parser, FTM)
C Flow Tracing
SerDes Security SerDes

Macros Engine Macros
Figure 4-1 : Data-path Architecture

4.2 SerDes Macro

Each lane in Octal SerDes Macro support PN Swap function to correct system wiring issues,
which can control the polarity of both TX data and RX data. But the PN swap must be
enabled/disabled simultaneously on TX and RX side.
l
The Octal SerDes Macro in CTC5118 is compatible with multiple industry standards including:


10 Gbps Ethernet application that include IEEE 802.3ak CX4 10Gb/s Ethernet
t
10 Gbps Ethernet application that include IEEE 802.3ap KX KX4, and 10G-KR Ethernet overi a
backplane
e n
d
 10 Gbps Small Form Factor Module, XFP and XFI

fi
Enhanced 8.5 and 10 Gigabit Small Form Factor Pluggable Module “SFP+”, SFF-8431
on
 1Gbps Ethernet applications that include SGMII (AC-coupled only)
 1Gbps Ethernet applications that include IEEE 802.3z 1000BASE-SX/LX

C
40 Gbps Ethernet applications that include IEEE802.3ba XLPPI, XLAUI, CR4, KR4.

e c
OIF-CEI-02.0 6G+ Short Reach and Long Reach and 11G+ Short Reach, Medium Reach, and
t
Long Reach
e n
Each lane in 2-lane SerDes Macro supports PN swap function to correct system wiring issues,
which can control the polarity of both TX data and RX data. But the PN swap must be
C
enabled/disabled simultaneously on TX and RX side.The 2-Lane SerDes Macro in CTC5118 is
l
compatible with multiple industry standards including:
a

t i
10 Gbps Ethernet application that include IEEE 802.3ak CX4 10Gb/s Ethernet
n
 10 Gbps Ethernet application that include IEEE 802.3ap KX KX4, and 10G-KR Ethernet over
e
backplane


fi d
10 Gbps Small Form Factor Module, XFP and XFI
Enhanced 8.5 and 10 Gigabit Small Form Factor Pluggable Module “SFP+”, SFF-8431


n
1Gbps Ethernet applications that include SGMII (AC-coupled only)
o
1Gbps Ethernet applications that include IEEE 802.3z 1000BASE-SX/LX

C
OIF-CEI-02.0 6G+ Short Reach and Long Reach and 11G+ Short Reach, Medium Reach, and
Long Reach
e c
n t
4.3 SmartPort™ Group
e
C
Centec’s SmartPort™ architecture is designed to support dynamic port speed configuration,
which enables customer to use the same silicon for different application scenarios.
In CTC5118, there are two kinds of HSS Macros, Qctal SerDes Macro and 2-lane SerDes Macro. A
Octal SerDes Macro integrates 3 PLLs which can support 3 kinds of lane rate with different PLL
oscillation rate, and the 2-lane SerDes Macro integrates 2 PLLs which can support 2 kinds of lane
rate(For more details, please refer to CTC5118 DMPS Application Note)
The SmartPort™ group supported configuration modes are shown in the following table.

Table 4-1 : SmartPort™ Group Configuration in Octal SerDes Macro

Mode SGMII XFI QSGMII USXGMII XLAUI XAUI
SerDes Lane 0 SGMII_0 XFI_0 QSGMII_0 USXGMII_0 XLAUI_0 XAUI_0
a l
t i
e n
d
SerDes Lane 5 SGMII_5 XFI 5 QSGMII_5 USXGMII_5 XLAUI_1 XAUI_1
SerDes Lane 6 SGMII_6 XFI 6 QSGMII_6 USXGMII_6 XLAUI_1

fi XAUI_1
SerDes Lane 7 SGMII_7 XFI 7 QSGMII_7 USXGMII_7

on
XLAUI_1 XAUI_1
C
e c
t
：
n
 1. QSGMII/USXGMII can only be connected to the SerDes Lane 0~11.
e
 2. Typically, for dynamic switch application scenario, it is recommended to use 4 Lanes in a
HSS SerDes total group, the speed of 4 lanes can be dynamic configured.
l C
Table 4-2 : SmartPort™ Group Configuration in 2-lane SerDes Macro
Mode SGMII
ti a XFI
SerDes Lane 0
SerDes Lane 1
SGMII
SGMII
e n XFI
XFI
f id
4.4 Typical Configuration o n
C
e c
Table 4-3 : Typical Configuration
n t 24 x 1GbE + 4 x
e
HSS Macro 48x1G + 6x10G 8*1G +16 x 10G
10GbE
C
Octal SerDes Macro #0
QSGMII0…
QSGMII5
QSGMII0… QSGMII7
XFI0~XFI1
QSGMII2~QSGMII3
XFI4 … XFI7
QSGMII8… QSGMII11
Octal SerDes Macro #1 XFI0 … XFI3 XFI6 … XFI13
XFI0 … XFI3
2-Lane SerDes Macro#0 XFI4~ XFI5 XFI14 ~XFI15

Memory Profile
5 Memory Profile
i a l
CTC5118 incorporates eTCAM and eSRAM as table memory. FTM technology enables flexible
n t
e
table memory partition per customer requirement. Each table size combination is called as a
d
fi
“memory profile”. On chip memory resources such as TCAM and embedded SRAM are considered
as a sharing pool. With different memory profiles, the chip is able to support different cases
on
such as more MAC address or more IP address. Table 5-1 shows example of memory profiles
supported by CTC5118.
C
Shared Buffer technology: to address the extra-large table size requirement in several special
c
application scenarios, CTC5118 integrates the shared buffer technology which allows the
e
t
embedded packet buffer to be configured to work in packet store mode or Dynamic Tables
n
mode. Shared buffer can be configured for the Dynamic Tables such as
MacKey/MacAd/DsNexthop, etc.
e
Table 5-1 : Typical FTM™ Profiles
l C
Symbol
t ia MAX
n
MAC 32K
IP Host (v4/ v6)
d e 12K
fi
IP LPM v4/v6 12K/3K
SCL (QinQ, VXLAN)
MPLS
o n 4K
2K
Policer
C 1K
ACL
e c 4K +1.5K
Buffer
n t 3MB
Queue
e 1K
C
Counter 32K

System Interface
6 System Interface
i a l
6.1 Overview n t
d e
fi
CTC5118 integrates the following major external interfaces:
on
 Multiple Speed SerDes links, Network interface
 I2C interface to access the external Optical Modules
C
 PTP and Sync-E Interface for time synchronization and IEEE1588 protocol
c
 SMI, IEEE 802.3-compliant Serial Management Interface for communication with external
e
PHY devices

n t
LED interface: to control the operation of the LEDs on the front panel
e
 PCIE 2.0
CPU Subsystem Interface
C

a l
DDR3/DDR4 SDRAM Interface, 16-bit + 8-bit ECC
−
nonvolatile storage
t i
Quad Serial Peripheral Interface (QSPI) used by the CPU subsystem for boot and
e n
Serial Peripheral Interface (SPI) for CPU subsystem for low-speed access
− USB Interface
fi d
n
− SGMII Interface: two ports connected to external PHYs up to 1GE for management
o
functionality.
C
− GPIO 34 pins
c
− SMI for external PHY management
−
t e
EMMC interface for the communication with the external eMMC storage devices
en
C
All interfaces need to be configured for normal operation.
6.2 Network Interface

3 HSS Macros are integrated in CTC5118 to work as the network interfaces. Among these 3 HSS
Macros, there are two Octal SerDes for 1.25G to 10.3125G lane rate and one 2-Lane SerDes for
1.25G to 10.3125G lane rate. These SerDes links support multiple speeds for multiple port
standards, including the following industry standards interface (the baud rate also listed):
 SGMII, 1.25Gbps
 SGMII2.5G, 3.125G

System Interface
 XAUI/10GBASE-KX4, 3.125Gbps
 QSGMII, 5Gbps*1
 USXGMII-Multiport, 5.15625Gbps*1
 XFI/SFI/10GBASE-KR/USXGMII-Multiport, 10.3125Gbps*1
 DXAUI, 6.25Gbps
 XLAUI/40GBASE-KR4/40GBASE-CR4, 10.3125Gbps
a l
i
*1: QSGMII and USXGMII are only supported by the 0~11 of 12.5G SerDes Lanes
6.2.1 Interface Signals

n t
d e
fi
Table 6-1 : Interface Signals
on
Pin Name Type Rate Pin # Description
HSS Macro0/1 Group Interface
HS_S[0:1]_REFCLK_P I LVDS 156.25MHz 4
C
HSS input differential clock,
HS_S[0:1]_REFCLK_N
e c impedance 100±10% Ohm.
HS_S[0:1]_RX_N[0:7]
HS_S[0:1]_RX_P[0:7]
I CML IN 1.25G~10.3125Gbps
n t
32 1.25G~10.3125Gbps SerDes
links input.
e Typical configurations are:
lC
 SGMII/1000BASE-X, 1.25Gbps
 XAUI/10GBASE-KX4,
tia
3.125Gbps
 QSGMII, 5Gbps
e n  Usxgmii-Multiport,5.15625G
bps
id
 XFI/SFI/10GBASE-KR/USXGMI
n f 
I-Multiport, 10.3125Gbps
DXAUI, 6.25Gbps
o  XLAUI/40GBASE-KR4/CR4,
C
10.3125Gbps
c
HS_S[0:1]_TX_N[0:7] O CML OUT 1.25G~10.3125Gbps 32 1.25G~10.3125Gbps SerDes
links output.
e
HS_S[0:1]_TX_P[0:7]
t
HSS Macro2 Group Interface
n
e
HS_S[2]_REFCLK_P I LVDS 156.25MHz 2 HSS input differential clock,
HS_S[2]_REFCLK_N impedance 100±10% Ohm.
C
HS_S[2]_RX_N[0:1]
HS_S[2]_RX_P[0:1]
I CML IN 1.25G~10.3125Gbps 4 1.25G~10.3125Gbps SerDes
links input.
Typical configurations are:
 SGMII/1000BASE-X, 1.25Gbps
 XFI/SFI/10GBASE-KR,
10.3125Gbps
HS_S[2]_TX_N[0:1] O CML OUT 1.25G~10.3125Gbps 4 1.25G~10.3125Gbps SerDes
HS_S[2]_TX_P[0:1] links output.
PCIe (HSS5G) Interface

System Interface

PCIE_REFCLK_P I HCSL 100MHz 2 PCIE input deferential
PCIE_REFCLK_N reference clock 100M.
PCIE_REXT I LVCMOS Static 1 External resistor for
termination calibration:
Connect 50 ohm external
resistor (1% precision) between
a l
i
PCIE_REXT to AVDD18_PCIE (no
t
need to be close to BGA BALL)
n
e
PCIE_RX_P I CML IN 2.5/5.0Gbps 2 PCIE lane input data.
d
PCIE_RX_N
PCIE_TX_P O CML OUT 2.5/5.0Gbps 2
fi
PCIE lane output data.
on
PCIE_TX_N
PCIE_TPOUT O LVCMOS Static 1 Analog output test pin which is
C
reserved for factory debug. It
should be connected to a via.
e c
6.2.2 USXGMII-M Interface
n t
e
The Universal Serial Media Independent Interface for carrying multiple network ports over a
C
single SerDes (USXGMII-M) is integrated in CTC5118:

a l
Convey Multiple network ports over an USXGMII MAC-PHY interface, e.g.: 100M, 1000M, 1G,
i
2.5G, 5G

n t
Utilize a 64/66 PCS to minimize power and serial bandwidth
e
 Use modified IEEE802.3 to add Alignment Markers to support multiple ports over single
d
SerDes

n fi
System Interface operates in full duplex mode only
6.2.3 1GbE/2.5GbE Port

o
C
CTC5118 can provide up to 54x1GbE ports. The embedded 1GE ports have the following
features:
e c


n t
IEEE 802.3z compliance
Support auto-negotiation with speed

e
Supports full duplex only operations


C
Supports full duplex flow control (IEEE 802.3x)
FCS generation for transmitting, checking for receiving packets
 Includes PCS block (8b/10b @ QSGMII or SGMII) or (64b/66b @ USXGMII) for SerDes interface
to external Gigabit PHY
Basic Operation
The device implements a MAC unit with PCS layer integrated. It can be programmed to filter out
frames that are longer or shorter than specific sizes. It also filters packets out with bad CRCs or
reception error.

System Interface
 Enable/Disable Port
 MAC Speed
 IEEE 802.3x Flow Control
 Link State
 Enable/Disable CRC Checking
 Maximum Receive Unit (MRU)
a l
The SerDes link runs at 3.125Gbps for 2500Mbps.
t i
SerDes link to receive and transmit data by the multiplexing function
e n
While SerDes link runs at 10.3125G for USXGMII-M interface，4 MACS will be connected to one
fi d
While SerDes link runs at 5.0Gbps for QSGMII interface, 4 MACs will be connected to one SerDes
on
link to receive and transmit data by the multiplexing function.
6.2.4 5GbE
C
c
CTC5118 also supports 5GbE port by USXGMII protocol. While data rate is 10.3125Gbps for
e
t
USXGMII interface, 2 of 5G ports can receive and transmit data by the multiplexing function.
6.2.5 10GbE port

e n
10 Gigabit MAC Standard Features
l C

t i a
Compliant to IEEE Std 802.3-2015 Clause 46,47,48,49,72,73,74
10 Gigabit MAC Extended Features

e n

fi d
MAC/ RS/ PCS implementations compliant to IEEE 802.3 specifications


o n
Comprehensive statistics gathering with statistic vector outputs
Supports flow-control in both directions

C
Per frame and default programmable padding and FCS insertion

e c
Supports Deficit Idle Count for maximum data throughput
t
 Maintains minimum IPG under all conditions and provides line rate performance


e n
XGMII link fault detection and generation
Supports loopback for diagnose

 C
Supports backplane auto-negotiation and link training
Supports Base-R FEC (FC (2112,2080))
Basic Operation
The SGMAC module performs the packet transmission and reception protocol as described in
IEEE standard 802.3-2015 including a MAC Control Sub-layer and PCS layer.
In transmitting direction, the SGMAC module receives data from internal data bus and performs
idle conversion, code group generation 64b/66b encoding for XFI/SFI/10G-KR. Next, the SGMAC
prepares the data for transmission over one link for XFI/SFI/10G-KR/ XAUI/DXAUI.

System Interface
In receiving direction, the SGMAC module accepts 4-lane wide data for XAUI/DXAUI or 1-lane
data for XFI/SFI/10G-KR from a SerDes lane.
6.2.6 40GbE Port
40 Gigabit MAC Standard Features
a l
 Compliant to IEEE Std802.3-2015 Clause 80~83
t i
40 Gigabit MAC Extended Features
e n
 MAC/RS/PCS implementations compliant to IEEE 802.3 specifications
fi d
on
 Supports flow-control in both directions
 Per frame and default programmable padding and FCS insertion
XLGMII link fault detection and generation
C

c
 Supports Deficit Idle Count for maximum data throughput
e
Maintains minimum IPG under all conditions and provides line rate performance
t

n
 Supports backplane auto-negotiation and link training
e
 Supports Base-R FEC (FC (2112,2080))
Basic Operation
l C
t i a
The XLGMAC module performs the packet transmission and reception protocol as described in
n
IEEE standard 802.3ba.
e
In transmitting direction, the XLGMAC module receives data from internal data bus and
d
fi
performs idle conversion, code group generation, and 64b/66b encoding for XLAUI. After that,
the XLGMAC prepares the data for transmission over 4 links for XLAUI.
o n
In receiving direction, the XLGMAC module accepts 4-lane wide data for XLAUI from four lines
of SerDes. XLGMAC pass data to 64b/66b decoding, then go to the XLGMII data bus.
C
During operation, the XLGMAC collects statistics about the success and failure of various
c
operations. The statistic information is processed by network management entities in the
e
system.
n t
e
6.3 CPU Interface
C
The feature sets of CTC5118 CPU Subsystem within the switch device are listed as below.
 One dual-core ARM A53 CPU running at 1.2GHz or 800MHz, which can be configured by the
chip pin, with the following caches:
− 32KB L1 Instruction cache and 32KB L1 data cache
− Internal 256 KB L2 Cache
 Neon + FPU for float point computing
 96KB RAM on system AXI bus
 64KB Boot ROM on system AXI bus

System Interface
 16-bit + 8bit (ECC) wide configuration DDR3/DDR4 interface

 USB2.0 Interface
 34 GPIOs
 2 SGMII Interfaces for out-of-band management
 SMI Interface
 EMMC interface support 4.51
a l
QSPI with two CS signals, support 1-bit, 2-bit, and 4-bit work mode
i

 SPI interface with four CS signals

n t
e
 Security boot up technology

fi d
2 I2C SoC Interface to connect the I2C device between internal CPU and external I2C devices
6.4 PCIe Interface

on
C
The single SerDes lane is dedicated for CPU interface connection. The PCIE could be used for
c
register configuration, DMA for internal table access, and packet I/O.
e
Rootport mode.
n t
Also, if internal CPU is enabled, PCIe interface can be configured to work at Endpoint mode or

e
Rootport mode: PCIe interface can be controlled by the internal CPU for the connection
with the external PCIe devices;
l C
Endpoint mode: Another external CPU can be connected to the PCIe interface for switch
a

t i
control. When the device works in Endpoint mode, it needs to release reset(RST_SUP_B) 5ms
n
earlier than external CPU.
e
CTC5118 PCIE supports Gen1 and Gen2 protocol, it provides maximum data rate of 5Gbps. The
d
fi
data rate is auto-negotiated during PCIE training. It is recommended that the device and
external CPU use the same origin clock.
o n
6.5 I2C Master Interface
C
c
CTC5118 I2C Master Interface supports serial bus interface which is compatible with Philips I2C
e
n t
standards. But it can only run at master mode and no more than 400Kbps.
The switch core I2C master interfaces do not support clock synchronizing function and can only
e
be used to access the external optical modules such as SFP, XFP, SFP +. The state of external
C
optical modules could be collected by I2C master interface periodically and save to internal 384
Bytes memory.
6.6 I2C Slave Interface

CTC5118 I2C slave interface supports serial bus interface which is compatible with Philips I2C
standards. But it can only run at slave mode and no more than 400Kbps.
The I2C slave interface is used for slow speed configuration for internal register or table. In
most cases, the I2C slave interface is used to configure and debug the PCIE interface.

System Interface
The address LSB 2 bits of CTC5118 I2C slave interface is configurable by tie 2 external pins to
VDD or GND. So the I2C slave address is 7’b011_11??. For 7bits address mode and for 10 bits
address mode, the address is 10’b00_0011_11??.
6.7 PTP and Sync Ethernet Interface

CTC5118 supports packet-based Time Synchronization (IEEE1588 and IEEE802.1AS) and
a l
t
Synchronous Ethernet Layer-one Clock Recovery (ITU G.8261). The synchronous communication
i
e n
over Ethernet is a control protocol that negotiates resource and timing on the network. The
protocol synchronizes the real-time clocks in a system and enables network measurement and
control based on real time.
fi d
on
6.7.1 Sync Ethernet Interface
C
The sync Ethernet interface provides the scheme to recover the clock from upstream devices
and pass the clock to downstream devices through physical layer. CTC5118 generates three
c
output clocks to feed in an external DPLL to produce transmitting reference clock.
e
transfer to transmitting reference clock.
n t
Figure 6-1 shows the detail of one instance of recovery clock and how the recovery clock
e
In typical application cases, the output selected recovery clock should be guarded by the
l C
corresponding link state of MAC and SerDes. CTC5118 also has the valid output to provide the
a
capability for customer to shut off the selected recovery clock off chip while the corresponding
link state of MAC or SerDes is failure.
t i
e n
fi d
o n
C
e c
n t
e
C
Figure 6-1 : Sync Ethernet Clock Scheme

System Interface
Table 6-2 : Sync Ethernet Signals

Name IO Description
RECV_CLK[0:2] O, CMOS SyncE recovery Clock
l
CTC5118 supports clock recovering via SerDes. The recovered clock can be divided by divider,
ia
which has a range of 1 to 1024. Each output can be controlled by link status of the recovery
path. The detailed recovery clock frequency of different port speed is as bellow table.
nt
Table 6-3 : Recovery Clock Frequency of Different port speed
de
Port Mode Data Rate Recovery clock Divider
fi
Output Clock
on
(Gbps) Frequency (MHz) Frequency (MHz)
SGMII 1 125 64 1.953125
C
SGMII 2.5 312.5 160 1.953125
c
XFI/XLG 10 322.265625 165 1.953125
te
6.7.2 PTP Interface Signals
en
l C
The PTP signals provide three types of signals. The first one is the differential reference clock
fed into the internal TsEngine. The second one is the sync interface which is used for receiving
ia
time code (Slave Mode) or transmitting time code and synthesized output low speed TDM clock
t
n
(Master Mode). The last one is the ToD signal to receive or transmit time code which obeys the
e
China Mobile’s standards.
fid
Table 6-4 : PTP signals
Pin Name
PTP_REFCLK_P
o n Type
I LVDS
Description
TsEngine Differential clock input, typical frequency is 125MHz
PTP_REFCLK_N
C
SYNC_CLK
e c I/O LVCMOS TsEngine sync clock, up to 25MHz.
t
SYNC_PULSE I/O LVCMOS TsEngine sync pulse.
en
SYNC_CODE I/O LVCMOS TsEngine sync code.
TOD_CODE I/O LVCMOS ToD (Time of Date) output code, typical rate is 9600 baud rate.
C
TOD_PULSE
TOD_REFCLK
I/O LVCMOS
I LVCMOS1.8V
ToD output pulse, typical 1pps pulse
ToD Reference Clock, typical 96MHz
6.8 SMI Interface

6.8.1 SMI Interface Signals
CTC5118 supports the IEEE 802.3 MII Management Interface via the MDIO and MDC pins. MDIO is
a serial input and output data signal which is clocked by the periodic clock MDC. This interface

System Interface
allows CTC5118 accesses to the PHY internal registers, by which CTC5118 can monitor and
control the real-time status of the external PHY devices connected to CTC5118.
Besides, SMI interface could scan the state of PHY devices continuously without CPU involved to
collect the link status. It will trigger the APS operation while there are failures of links.
l
Table 6-5 : SMI Interface Signals
Name IO Description
t i a
n
MDC_A[1:0] External PHI MDIO clock, compatible with 1GE PHY
O LVCMOS
e
MDC_B[1:0] and 10GE PHY.
MDIO_A[1:0]
MDIO_B[1:0]
I/O LVCMOS
fi d
External PHY MDIO data, compatible with 1GE PHY
and 10GE PHY.
on
6.8.2 Operation
C
e c
Though each SMI interface can support up to 32 PHY devices, CTC5118 provides 2 groups (SMI
n t
A/B) to mitigate the load to reduce the system design difficulty. Each group, includes 2
interfaces, can be configured as either 10G or 1G MDIO mode. For example, the MDIO_A_0 and
e
MDIO_A_1 need to be configured to 10G or to 1G simultaneously.
l C
There are two operation types for SMI interface operation, the one is read/write operation, the
other is auto-scan. The read/write operation can only access one register one time, but the
t i a
auto-scan can access multiple status registers of many PHY.
6.9 MAC LED Interface e n

fi d
The serial LED interface consists of encoded bit stream. The timing and encoding diagram are
o n
shown in the following figure. An EPLD or simple shift register logic is needed to convert this bit
stream to drive individual LED.
C
The port sequence is programmable through internal register. Every port supports 2 modes:
c
On/Off mode and Blink mode. Every port can be configured to support 1 mode (only one LED for
e
n t
one MAC) or 2 modes (there are 2 LEDs for one MAC) independently. If mode 1 is configured,
then this port only output 1 bit on LED interface; If mode 2 is configured, then this port output
e
2 continual bits on LED interface.
Figure 6-2 : LED Interface Timing and Encoding Explanation

System Interface
6.9.2 LED Interface Signals

CTC5118 provides a pair of LED interfaces according to SmartPortTM Group. The LED interface
signals are given as bellow:
Table 6-6 : LED Interface Signals

Name IO Description
a l
LED_CLK O, LVCMOS LED Clock
t i
LED_DATA O, LVCMOS Encoded bit stream to drive LED
e n
6.9.3 LED Bit Stream Encode Modes
fi d
on
In order to maximize the facility of driving LED under different application scenario, total ten
LED bit stream encode modes are supported in CTC5118 this could save the external glue logic
and only the shift logic is needed.
C
Table 6-7 : LED Bit Stream Encode Modes
e c
Mode # Mode Description
n t
On/Off Blink
0 RX Link
e
RX Link = 1/0 0
lC
1 TX Link (10GE only) TX Link = 1/0 0
tia
2 RX Link and activity RX Link = 1/0 RX activity
3 TX Link and Activity (10GE only) TX Link = 1/0 TX activity
4 RX Link and RX/TX activity
e n RX Link = 1/0 RX or TX activity
fid
5 TX activity 0 TX activity
6 RX activity 0 RX activity
7
8
RX/TX activity
LED Force On
o n 0
1
RX or TX activity
0
9
C
LED Force Off 0 0
c
So, there are one pair of 2bits (total 4 bits) stand for the LED mode. For example, if user wants
e
n t
LED to be configured to work at mode #2 (Rx Link and activity), LED On/Off mode encode
should be 2’b01, LED blink mode encode should be 2’b01.
e
The LED control are 2 bits, which are deduced from the LED On/Off mode and LED blink mode
C
encoding, LED_PortStatus[1:0] MSB bit is blink bit, 1’b1 is blinking, 1’b0 is Non-blinking; on the
other hand, LED_PortStatus[1:0] LSB bit is On/Off bit, 1’b1 is On, 1’b0 is Off. Besides, the MSB
bit (i.e. the LED blinking bit) has the higher priority than LSB bit.
Take LED mode #2 as an example:
(1) Cfg LED On/Off mode encode = 2’b01, LED blink mode encode= 2’b01;
(2) If sample the Rx Link status = 1, then set LED_PortStatus[0]= 1’b1; If sample the Rx activity
status = 1, then set LED_PortStatus[1]= 1’b1.
(3) Since LED_PortStatus[1:0]= 2’b11, and blink status has the higher priority, the LED refresh
bit stream will be 0 => 1 => 0 => 1 toggling according to the interval of LED refresh.

System Interface
The LED blink behavior is implemented through the “and” operation of BLINK square-wave and
the BLINK bit of LED_PortStatus.
If need secondary LED for one port, such as 10GE port, the primary LED displays “Rx Link and
activity” (LED mode #2), and the secondary LED displays “TX Link and activity” (LED mode #3),
then an extra LED port status bits are required.
Note that if the customer needs all of the MACs’ raw link and activity status to be output for
a l
i
further processing (LedRawStatusCfg.rawStatusEn), all of the MACs’ mode configuration are not
effective.
n t
d e
fi
on
C
e c
n t
e
l C
t i a
e n
fi d
o n
C
e c
n t
e
C

Pin-Map and Pin-Out table
7 Pin-Map and Pin-Out table

i a l
This section provides the pin map and pin-out table with pin assignment for CTC5118.
n t
d e
7.1 Pin Map
fi
Table 7-1 : Pin Map Top View Column 1-6
on
C
ec
1 2 3 4 5 6
A VSS VSS DDR_DQ0 DDR_DQ1 DDR_DQ6
nt
B VSS DDR_DQ10 DDR_DQ7 DDR_DQ4 DDR_DQS_P0 DDR_DQ2
e
C DDR_DQS_N1 DDR_DQS_P1 DDR_DQ14 DDR_DM0 VSS DDR_DQS_N0
D DDR_DQ13 VSS DDR_DQ11 DDR_DQ3 DDR_DQ5
lC
E DDR_DM1 DDR_DQ9 DDR_DQ12 DDR_DQ15 VDDIO_DDR VDDIO_DDR
tia
F DDR_DQ8 VSS VSS VDDIO_DDR VSS
G DDR_DQ18 DDR_DQ20 DDR_DQ22 VDDIO_DDR VDDIO_DDR VSS
H
J
DDR_DQS_P2 DDR_DQS_N2
DDR_DQ16
VSS
VSS
e n DDR_DQ23
VSS
VDDIO_DDR
VDDIO_DDR
VSS
VSS
fid
K DDR_DQ19 DDR_DM2 DDR_DQ21 VDDIO_DDR VDDIO_DDR VSS
n
L DDR_CLK_N0 DDR_CLK_P0 VSS DDR_DQ17 VDDIO_DDR VSS
o
M DDR_CLK_N1 DDR_CLK_P1 VSS VDDIO_DDR VSS
C
N DDR_CS_B0 DDR_ODT1 VSS VDDIO_DDR VDDIO_DDR VSS
c
P DDR_TEN DDR_CKE1 DDR_ODT0 DDR_CS_B2 VDDIO_DDR VSS
e
R DDR_CKE0 VSS VSS VDDIO_DDR VSS
T DDR_CAS_B
n t DDR_CS_B1 DDR_CS_B3 VDDIO_DDR VDDIO_DDR VSS
e
U DDR_RAS_B DDR_WE_B DDR_ADDR14 DDR_ODT3 VDDIO_DDR VSS
V DDR_BA2 VSS VSS VDDIO_DDR VSS
Y
C
DDR_ADDR12
DDR_ADDR1
DDR_ADDR15
DDR_ADDR10
DDR_ODT2
DDR_ADDR2
VDDIO_DDR
DDR_ADDR4
VDDIO_DDR
VDDIO_DDR
VSS
VSS
AA DDR_BA1 VSS VSS VDDIO_DDR VSS
AB DDR_ADDR6 DDR_ADDR0 DDR_CKE2 VDDIO_DDR VDDIO_DDR VSS
AC DDR_ADDR9 DDR_ADDR8 DDR_ADDR7 DDR_ADDR3 VDDIO_DDR VSS
AD DDR_PAR VSS VSS VDDIO_DDR VSS
AE DDR_ADDR13 DDR_ADDR11 DDR_CKE3 VDDIO_DDR VDDIO_DDR VSS
AF DDR_RST_B DDR_ADDR5 DDR_ALERT_B DDR_BA0 VDDIO_DDR VSS

AG VSS VSS DDR_ZQ VSS VSS

1 2 3 4 5 6
AH USB_D_P USB_D_N VSS VSS VSS VSS

AJ VSS VSS VSS USB_VBUS0 USB_TXR_TUNE USB_ID0
AK HS_S0_TX_P0 HS_S0_TX_N0 VSS VSS VSS VSS
AL VSS VSS HS_S0_TX_N1 HS_S0_TX_P1 VSS VSS

AM HS_S0_TX_N2 HS_S0_TX_P2 VSS VSS VSS VSS
a l
i
AN VSS VSS VSS VSS VSS VSS
AP VSS VSS HS_S0_RX_N0 HS_S0_RX_P0 VSS
t
HS_S0_TX_P4
n
e
AR HS_S0_RX_P1 HS_S0_RX_N1 VSS VSS VSS HS_S0_TX_N4
d
AT VSS VSS HS_S0_RX_P2 VSS HS_S0_TX_N3 VSS
AU VSS VSS HS_S0_RX_N2 VSS HS_S0_TX_P3
fi VSS
on
C
ec
7 8 9 10 11 12
A HS_RX_N0 VSS HS_TX_N0
n t VSS HS_CMU_REFCLK_
N
B VSS HS_RX_P0 VSS

e
HS_TX_P0 VSS HS_CMU_REFCLK_
lC
P
C VSS VSS VSS VSS VSS VSS
ia
D VSS HS_RX_P1 VSS HS_TX_P1 VSS VSS
E
F
VSS
VSS
HS_RX_N1
VSS
VSS
VSS
n t HS_TX_N1
VSS
VSS
VSS
VSS
VSS
d e
fi
H
J
K
o n VSS AVDD09_VCO_HS3
C VSS VSS
c
M AVDD18_HS3 AVDD18_HS3
te VSS AVDD09_HS3
n
P AVDD18_DATA_L1 AVSS18_DATA_L1
6_DDR 6_DDR
R
e DDR_VREF1 DDR_VREF0
U
C AVDD18_DATA_H8
_DDR
VSS
AVSS18_DATA_H8
_DDR
VSS
V AVSS18_ADD_DDR ADD_AVDD_PLL
W VSS VSS
Y AVDD33_USB VDD
AA VDD_USB VSS
AB AVDD33_USB VDD
AC VSS VSS

7 8 9 10 11 12
AD VDD VDD
AE VSS VSS
AF AVDD09_HS0 AVDD09_HS0
AG VSS VSS
AH VSS AVDD18_HS0
a l
i
AJ
AK
n t
e
AL
d
AM VSS VSS VSS VSS VSS VSS
AN VSS VSS VSS VSS VSS

fi VSS
on
AP VSS VSS VSS HS_S0_RX_N4 VSS VSS
AR VSS VSS VSS HS_S0_RX_P4 VSS VSS
AT HS_S0_TX_P5 VSS HS_S0_RX_P3 VSS

C
HS_S0_RX_N5 VSS
AU HS_S0_TX_N5 VSS HS_S0_RX_N3 VSS
e c
HS_S0_RX_P5 VSS
n t
e
A
13
AVSS_PCIE
14
PCIE_TX_P
15
l C 16
AVSS_PCIE
17
PCIE_REFCLK_N
18
B AVSS_PCIE PCIE_TX_N
t
PCIE_RX_P
i a AVSS_PCIE PCIE_REFCLK_P CORE_REFCLK_P
n
C AVSS_PCIE AVSS_PCIE PCIE_RX_N AVSS_PCIE AVSS_PCIE CORE_REFCLK_N
de
D AVSS_PCIE AVSS_PCIE AVSS_PCIE AVSS_PCIE PCIE_TPOUT VSS
i
E AVSS_PCIE AVSS_PCIE AVSS_PCIE AVSS_PCIE PCIE_REXT VSS
F AVSS_PCIE AVSS_PCIE
n f AVSS_PCIE AVSS_PCIE VSS THM_VREFP
o
G
J
C
K AVSS_PCIE
e cAVSS_PCIE AVSS_PCIE AVDD18_THM VDD VDD

L
M
AVSS_PCIE
AVDD18_HS3
n t AVDD09_VCO_PCIE
AVDD09_HS3
AVDD18_PCIE
AVSS_PCIE
VSS
VDD
VDD
VDD
VDD
VDD
N
e
AVDD09_HS3 VSS AVDD09_PCIE VSS VDD VSS
P
T
C
VDDIO_DDR
VDDIO_DDR
VDDIO_DDR
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
U VDDIO_DDR_CK VSS VDD VSS VDD VSS
V VDDIO_DDR VDD VSS VDD VSS VDD
W VDD VSS VDD VSS VDD VSS

Y VSS VDD VSS VDD VSS VDD
AA VDD VSS VDD VSS VDD VSS
AB VSS VDD VSS VDD VSS VDD

13 14 15 16 17 18
AC VDD VSS VDD VSS VDD VSS
AD VSS VDD VSS VDD VSS VDD
AE VDD VSS AVDD09_VCO_HS VSS VDD VSS

0
l
AF AVDD09_HS0 AVDD09_HS0 VSS VSS AVDD09_HS1 AVDD09_HS1
i a
AG VSS VSS VSS VSS VSS VSS
AH
AJ
AVDD18_HS0 AVDD18_HS0 AVDD18_HS0 VSS VSS AVDD18_HS1
n t
AK
d e
fi
AL
on
AN VSS VSS VSS VSS VSS VSS
C
AP VSS HS_S0_TX_P7 VSS VSS VSS HS_S0_RX_N7
ec
AR VSS HS_S0_TX_N7 VSS VSS VSS HS_S0_RX_P7
AT HS_S0_TX_N6 VSS HS_S1_TX_P8 VSS HS_S0_RX_P6 VSS
nt
AU HS_S0_TX_P6 VSS HS_S1_TX_N8 VSS HS_S0_RX_N6 VSS
e
l C
19 20
t i
21
a 22 23 24
n
A PTP_REFCLK_P MSH_DATA6 MSH_DATA4 SD_DET_B
de
B PTP_REFCLK_N MSH_DATA2 MSH_DATA0 MSH_DATA3 MSH_CMD MSH_CLK
i
C VSS MSH_DATA1 VSS MSH_DATA5 MSH_RST_B VSS
D VSS MSH_DATA7
n f VSS SD_WP VSS VSS
o
E VSS VSS GPIOHS2 GPIOHS3 GPIOHS4 GPIOHS5
F THM_VINS0 VSS VDDIO18_EFUSE_ME VDDIO18_EFUSE GPIOHS9 GPIOHS10
C M _INFO
c
G
H
t e
n
J
e
K AVDD18_DDRPLL VDD09_DDRPLL AVDD18_PLL AVDD18_LVDS VSS VSS
C
L AVSS_DDRPLL VSS_DDRPLL AVSS_PLL VSS VDDOUT_MSH VDDOUT_G5
M VSS VDD VSS VDD VSS VDD
N VDD VSS VDD VSS VDD VSS

P VSS VDD VSS VDD VSS VDD
R VDD VSS VDD VSS VDD VSS
T VSS VDD VSS VDD VSS VDD

U VDD VSS VDD VSS VDD VSS
V VSS VDD VSS VDD VSS VDD
W VDD VSS VDD VSS VDD VSS
Y VSS VDD VSS VDD VSS VDD

19 20 21 22 23 24
AA VDD VSS VDD VSS VDD VSS
AB VSS VDD VSS AVDD18_RSV AVDD18_RSV AVDD18_RSV
AC VDD VSS VDD VSS VSS VSS

AD VSS VDD VSS VDD_RSV VDD_RSV VDD_RSV
AE AVDD09_VCO_HS1 VSS VDD VSS AVDD09_VCO_HS2 VSS
a l
i
AF VSS AVDD09_HS1 AVDD09_HS1 VSS VSS AVDD09_HS2
AG AVDD18_HS1 VSS VSS VSS VSS VSS
n t
e
AH AVDD18_HS1 AVDD18_HS1 VSS VSS AVDD18_HS2 AVDD18_HS2
d
AJ
AK
fi
on
AL
AN VSS VSS VSS VSS

C
VSS VSS
ec
AP VSS VSS VSS HS_S1_TX_P10 VSS VSS
nt
AR VSS VSS VSS HS_S1_TX_N10 VSS VSS
AT HS_S1_RX_N8 VSS HS_S1_TX_N9 VSS HS_S1_TX_P11 VSS
AU HS_S1_RX_P8 VSS HS_S1_TX_P9
e
VSS HS_S1_TX_N11 VSS
l C
t i a
A
25
QSPI_CLK
26
QSPI_DATA2
27
e n TRST_B
28
TDI
29 30
SCL_SOC0
31
B QSPI_DATA0 QSPI_DATA1
fi d
QSPI_CS1 TCK SDA_SOC1 MSCL1 SDA_SOC0
n
C SD_SW_VOLT_ QSPI_CS0 VSS TMS SCL_SOC1 VSS MSDA1
o
EN
D QSPI_DATA3 VSS VSS TDO VSS VSS MSCL0
E GPIOHS6 GPIOHS7
C GPIOHS8 MDIO_B1 MDC_B1 MDIO_B0 MDC_B0
F GPIOHS11
e cGPIOHS12 GPIOHS13 GPIOHS14 GPIOHS15 GPIOHS16 GPIOHS17
t
G
H
J
e n
K
L
H
C
VDDIO3318_MS
VDDIO18
VDDIO3318_MS
H
VDDIO18
VDDIO33
VDDIO33
M VSS VDDOUT_MDIO VDDIO3312_MD
_A IO_A
N VDD VDDOUT_MDIO VDDIO3312_MD

_B IO_B
P VSS VDDIO18 VDDIO3318_GP

IO_7_0
R VDD VDDIO18 VDDOUT_GPIO

_7_0

25 26 27 28 29 30 31
T VSS VDDIO18 VDDIO33
U VDD VDDOUT_G1 VDDIO33
V VSS VDDOUT_G2 VDDIO33

W VDD VDDOUT_G3 VDDIO33
Y VSS VDDOUT_G4 VDDIO33
a l
i
AA VDD VDDOUT_RECV VDDIO3318_RE
AB AVDD18_RSV AVDD18_RSV
CV
AVDD18_RSV
n t
AC VSS VSS VSS
d e
fi
AD VDD_RSV VDD_RSV VDD_RSV
on
AE VDD VSS VSS
AF AVDD09_HS2 AVDD09_HS2 AVDD09_HS2
C
AG VSS VSS VSS
c
AH AVDD18_HS2 AVDD18_HS2 VSS
e
AJ
AK
n t
e
AL
lC
AM VSS VSS VSS VSS VSS VSS VSS
AN VSS VSS VSS VSS VSS VSS VSS
tia
AP VSS HS_S1_RX_N10 VSS VSS VSS HS_S1_TX_P13 VSS
AR VSS HS_S1_RX_P10 VSS VSS VSS HS_S1_TX_N13 VSS
AT HS_S1_RX_P9 VSS HS_S1_RX_N11
e n VSS HS_S1_TX_N12 VSS HS_S1_TX_P14
id
AU HS_S1_RX_N9 VSS HS_S1_RX_P11 VSS HS_S1_TX_P12 VSS HS_S1_TX_N14
n f
o
32
C 33 34 35 36 37
A MSDA0
e c MDIO_A1 GPIOHS0 VSS VSS
t
B MDC_A0 MDC_SOC MDC_A1 GPIOHS1 GPIO0 VSS
C
D
MDIO_A0
VSS
e n VSS
DEBUG_MODE0
MDIO_SOC
USB_OVC_B
GPIO1
GPIO4
GPIO2
GPIO5
GPIO3
GPIO6
G
C
DEBUG_MODE1
DEBUG0
DEBUG1
DEBUG_MODE2
DEBUG4
TOD_REFCLK
GPIO7
WDT1_RST_B
UART_TXD2
VSS
BOOT_STRAP1
UART_TXD1
WDT0_RST_B
BOOT_STRAP0
UART_TXD0
BOOT_STRAP2
UART_RXD0
H DEBUG2 DEBUG5 UART_RXD2 VSS UART_RXD1
J CFG_GPIO_SEL VSS GPIO8 BOOT_USB_VRE GPIO9 GPIO10

G_BYP
K BOOT_LPBK_TES DEBUG7 RST_SUP_B GPIO11 GPIO12 GPIO13

T_MODE
L CFG_PLL_CORE_ DEBUG3 BOOT_PCIE_AUTO_ VSS GPIO14

BYP MODE

32 33 34 35 36 37
M CFG_PLL_SUP_B DEBUG6 INTR_B1 GPIO15 INTR_B0 INTR_B2
YP
N BOOT_PCIE_FOR FUSE_DONE VSS LED_CLK LED_DATA INTR_B3

CE_MODE
P BOOT_I2C_SA1 FUSE_FAIL BOOT_CPU_SPEED VSS TOD_PULSE

R BOOT_I2C_SA0 BOOT_RESV0 SYNC_CLK SYNC_PULSE SYNC_CODE TOD_CODE
a l
T BOOT_CPU_DIS BOOT_RESV1 VSS VSS RECV_CLK1
t
RECV_CLK0
i
U BOOT_TEST_MO
DE
RECV_CLK2 VSS HSS_REFCLK_N HSS_REFCLK_P
e n
fi d
V BOOT_RESV2 BOOT_PCIE_RP_MO VSS VSS HS_S2_REFCLK_N HS_S2_REFCLK_
DE P
on
W VSS VSS VSS HS_S1_REFCLK_ HS_S1_REFCLK_P
N
C
Y VSS VSS VSS VSS HS_S0_REFCLK_N HS_S0_REFCLK_
P
AA VSS VSS VSS VSS
e c VSS VSS
t
AB VSS VSS VSS VSS NC NC
AC
AD
VSS
VSS
VSS
VSS
NC
VSS
NC
VSS
e n VSS
HS_S2_RX_P17
VSS
HS_S2_RX_N17
AE
AF
VSS
VSS
VSS
VSS
VSS
VSS
l CVSS
VSS
VSS
NC
VSS
NC
AG VSS VSS NC
t i a NC VSS VSS
n
AH VSS VSS VSS VSS HS_S2_TX_N17 HS_S2_TX_P17
de
AJ VSS VSS VSS VSS VSS VSS
i
AK VSS VSS VSS VSS HS_S2_RX_N16 HS_S2_RX_P16
AL VSS VSS
n f HS_S1_RX_N15 HS_S1_RX_P15 VSS VSS
o
AM VSS VSS VSS VSS VSS HS_S2_TX_P16
AN VSS VSS VSS VSS VSS HS_S2_TX_N16
AP VSS VSS
C HS_S1_RX_N13 VSS VSS HS_S1_TX_P15
AR VSS
e c
VSS HS_S1_RX_P13 VSS VSS HS_S1_TX_N15
t
AT VSS HS_S1_RX_P12 VSS HS_S1_RX_N14 VSS VSS
AU VSS
e n HS_S1_RX_N12 VSS HS_S1_RX_P14 VSS VSS
C
7.2 Pin-Out Table
Table 7-7 : Pin-Out Table (by Ball)
Ball Ball Name Ball Ball Name Ball Ball Name
Location Location Location
A1 VSS AN26 VSS F9 VSS
A10 HS_TX_N0 AN27 VSS G1 DDR_DQ18


A11 VSS AN28 VSS G2 DDR_DQ20
A12 HS_CMU_REFCLK_ AN29 VSS G3 DDR_DQ22
N
l
A13 AVSS_PCIE AN3 VSS G32 DEBUG1
A14
A16
PCIE_TX_P
AVSS_PCIE
AN30
AN31
VSS
VSS
G33
G34
TOD_REFCLK
UART_TXD2
t i a
A17 PCIE_REFCLK_N AN32 VSS G35 UART_TXD1
e n
A19
A2
PTP_REFCLK_P
VSS
AN33
AN34
VSS
VSS
G36
G37
fi
UART_TXD0
UART_RXD0 d
on
A20 MSH_DATA6 AN35 VSS G4 VDDIO_DDR
C
A22 MSH_DATA4 AN36 VSS G5 VDDIO_DDR
A23 SD_DET_B AN37 HS_S2_TX_N16 G6 VSS
ec
A25 QSPI_CLK AN4 VSS H1 DDR_DQS_P2
nt
A26 QSPI_DATA2 AN5 VSS H2 DDR_DQS_N2
e
A28 TRST_B AN6 VSS H3 VSS
lC
A29 TDI AN7 VSS H32 DEBUG2
A3 DDR_DQ0 AN8 VSS H33 DEBUG5
ia
A31 SCL_SOC0 AN9 VSS H34 UART_RXD2
A32 MSDA0 AP1
n t
VSS H35 VSS
de
A34 MDIO_A1 AP10 HS_S0_RX_N4 H36 UART_RXD1
i
A35 GPIOHS0 AP11 VSS H4 DDR_DQ23
A36 VSS
n f
AP12 VSS H5 VDDIO_DDR
o
A37 VSS AP13 VSS H6 VSS
C
A4 DDR_DQ1 AP14 HS_S0_TX_P7 J2 DDR_DQ16
c
A6 DDR_DQ6 AP15 VSS J3 VSS
e
A8 HS_RX_N0 AP16 VSS J32 CFG_GPIO_SEL
A9 VSS
n t AP17 VSS J33 VSS
e
AA11 VDD_USB AP18 HS_S0_RX_N7 J34 GPIO8
C
AA12 VSS AP19 VSS J35 BOOT_USB_VREG_BYP
AA13 VDD AP2 VSS J36 GPIO9
AA14 VSS AP20 VSS J37 GPIO10
AA15 VDD AP21 VSS J4 VSS
AA16 VSS AP22 HS_S1_TX_P10 J5 VDDIO_DDR
AA17 VDD AP23 VSS J6 VSS
AA18 VSS AP24 VSS K1 DDR_DQ19
AA19 VDD AP25 VSS K11 VSS
AA2 DDR_BA1 AP26 HS_S1_RX_N10 K12 AVDD09_VCO_HS3


AA20 VSS AP27 VSS K13 AVSS_PCIE
AA21 VDD AP28 VSS K14 AVSS_PCIE
AA22 VSS AP29 VSS K15 AVSS_PCIE
AA23 VDD AP3 HS_S0_RX_N0 K16 AVDD18_THM
a l
AA24 VSS AP30 HS_S1_TX_P13 K17 VDD
t i
n
AA25 VDD AP31 VSS K18 VDD
AA26 VDDOUT_RECV AP32 VSS K19
e
AVDD18_DDRPLL
d
fi
AA27 VDDIO3318_RECV AP33 VSS K2 DDR_DM2
on
AA3 VSS AP34 HS_S1_RX_N13 K20 VDD09_DDRPLL
AA32 VSS AP35 VSS K21 AVDD18_PLL
C
AA33 VSS AP36 VSS K22 AVDD18_LVDS
ec
AA34 VSS AP37 HS_S1_TX_P15 K23 VSS
nt
AA35 VSS AP4 HS_S0_RX_P0 K24 VSS
AA36 VSS AP5 VSS K25 VDDIO3318_MSH
AA37 VSS AP6 HS_S0_TX_P4
e K26 VDDIO3318_MSH
AA4
AA5
VSS
VDDIO_DDR
AP7
AP8
VSS
VSS
l C K27
K3
VDDIO33
DDR_DQ21
AA6 VSS AP9
ti
VSS
a K32 BOOT_LPBK_TEST_MODE
AB1
AB11
DDR_ADDR6
AVDD33_USB
AR1
AR10
e n
HS_S0_RX_P1
HS_S0_RX_P4
K33
K34
DEBUG7
RST_SUP_B
fid
AB12 VDD AR11 VSS K35 GPIO11
n
AB13 VSS AR12 VSS K36 GPIO12
AB14 VDD
o AR13 VSS K37 GPIO13
AB15 VSS
C AR14 HS_S0_TX_N7 K4 VDDIO_DDR
c
AB16 VDD AR15 VSS K5 VDDIO_DDR
AB17 VSS
t e AR16 VSS K6 VSS

AB18
AB19
VDD
e
VSSn AR17
AR18
VSS
HS_S0_RX_P7
L1
L11
DDR_CLK_N0
VSS
AB2
AB20 C DDR_ADDR0
VDD
AR19
AR2
VSS
HS_S0_RX_N1
L12
L13
VSS
AVSS_PCIE
AB21 VSS AR20 VSS L14 AVDD09_VCO_PCIE
AB22 AVDD18_RSV AR21 VSS L15 AVDD18_PCIE
AB23 AVDD18_RSV AR22 HS_S1_TX_N10 L16 VSS
AB24 AVDD18_RSV AR23 VSS L17 VDD
AB25 AVDD18_RSV AR24 VSS L18 VDD
AB26 AVDD18_RSV AR25 VSS L19 AVSS_DDRPLL
AB27 AVDD18_RSV AR26 HS_S1_RX_P10 L2 DDR_CLK_P0


AB3 DDR_CKE2 AR27 VSS L20 VSS_DDRPLL
AB32 VSS AR28 VSS L21 AVSS_PLL
AB33 VSS AR29 VSS L22 VSS
AB34 VSS AR3 VSS L23 VDDOUT_MSH
a l
AB35 VSS AR30 HS_S1_TX_N13 L24 VDDOUT_G5
t i
n
AB36 NC AR31 VSS L25 VDDIO18
AB37 NC AR32 VSS L26 VDDIO18
d e
fi
AB4 VDDIO_DDR AR33 VSS L27 VDDIO33
on
AB5 VDDIO_DDR AR34 HS_S1_RX_P13 L3 VSS
AB6 VSS AR35 VSS L32 CFG_PLL_CORE_BYP
C
AC1 DDR_ADDR9 AR36 VSS L33 DEBUG3
ec
AC11 VSS AR37 HS_S1_TX_N15 L34 BOOT_PCIE_AUTO_MODE
nt
AC12 VSS AR4 VSS L35 VSS
AC13 VDD AR5 VSS L36 GPIO14
AC14 VSS AR6 HS_S0_TX_N4
e L4 DDR_DQ17
AC15
AC16
VDD
VSS
AR7
AR8
VSS
VSS
l C L5
L6
VDDIO_DDR
VSS
AC17 VDD AR9
ti
VSS
a M11 AVDD18_HS3
AC18
AC19
VSS
VDD
AT1
AT10
e n
VSS
VSS
M12
M13
AVDD18_HS3
AVDD18_HS3
fid
AC2 DDR_ADDR8 AT11 HS_S0_RX_N5 M14 AVDD09_HS3
n
AC20 VSS AT12 VSS M15 AVSS_PCIE
AC21 VDD
o AT13 HS_S0_TX_N6 M16 VDD
AC22 VSS
C AT14 VSS M17 VDD
c
AC23 VSS AT15 HS_S1_TX_P8 M18 VDD
AC24 VSS
t e AT16 VSS M19 VSS

AC25
AC26
VSS
e
VSSn AT17
AT18
HS_S0_RX_P6
VSS
M2
M20
DDR_CLK_N1
VDD
AC27
AC3 C VSS
DDR_ADDR7
AT19
AT2
HS_S1_RX_N8
VSS
M21
M22
VSS
VDD
AC32 VSS AT20 VSS M23 VSS
AC33 VSS AT21 HS_S1_TX_N9 M24 VDD
AC34 NC AT22 VSS M25 VSS
AC35 NC AT23 HS_S1_TX_P11 M26 VDDOUT_MDIO_A
AC36 VSS AT24 VSS M27 VDDIO3312_MDIO_A
AC37 VSS AT25 HS_S1_RX_P9 M3 DDR_CLK_P1
AC4 DDR_ADDR3 AT26 VSS M32 CFG_PLL_SUP_BYP


AC5 VDDIO_DDR AT27 HS_S1_RX_N11 M33 DEBUG6
AC6 VSS AT28 VSS M34 INTR_B1
AD11 VDD AT29 HS_S1_TX_N12 M35 GPIO15
AD12 VDD AT3 HS_S0_RX_P2 M36 INTR_B0
a l
AD13 VSS AT30 VSS M37 INTR_B2
t i
n
AD14 VDD AT31 HS_S1_TX_P14 M4 VSS
AD15 VSS AT32 VSS M5 VDDIO_DDR
d e
fi
AD16 VDD AT33 HS_S1_RX_P12 M6 VSS
on
AD17 VSS AT34 VSS N1 DDR_CS_B0
AD18 VDD AT35 HS_S1_RX_N14 N11 VSS
C
AD19 VSS AT36 VSS N12 AVDD09_HS3
ec
AD2 DDR_PAR AT37 VSS N13 AVDD09_HS3
nt
AD20 VDD AT4 VSS N14 VSS
AD21 VSS AT5 HS_S0_TX_N3 N15 AVDD09_PCIE
AD22 VDD_RSV AT6 VSS
e N16 VSS
AD23
AD24
VDD_RSV
VDD_RSV
AT7
AT8 VSS
l C
HS_S0_TX_P5 N17
N18
VDD
VSS
AD25 VDD_RSV AT9
ti a
HS_S0_RX_P3 N19 VDD
AD26
AD27
VDD_RSV
VDD_RSV
AU1
AU10
e n
VSS
VSS
N2
N20
DDR_ODT1
VSS
fid
AD3 VSS AU11 HS_S0_RX_P5 N21 VDD
n
AD32 VSS AU12 VSS N22 VSS
AD33 VSS
o AU13 HS_S0_TX_P6 N23 VDD
AD34 VSS
C AU14 VSS N24 VSS
c
AD35 VSS AU15 HS_S1_TX_N8 N25 VDD
AD36
t e
HS_S2_RX_P17 AU16 VSS N26 VDDOUT_MDIO_B
AD37
AD4
e
VSSn
HS_S2_RX_N17 AU17
AU18
HS_S0_RX_N6
VSS
N27
N3
VDDIO3312_MDIO_B
VSS
AD5
AD6
C VDDIO_DDR
VSS
AU19
AU2
HS_S1_RX_P8
VSS
N32
N33
BOOT_PCIE_FORCE_MOD
E
FUSE_DONE
AE1 DDR_ADDR13 AU20 VSS N34 VSS
AE11 VSS AU21 HS_S1_TX_P9 N35 LED_CLK
AE12 VSS AU22 VSS N36 LED_DATA
AE13 VDD AU23 HS_S1_TX_N11 N37 INTR_B3
AE14 VSS AU24 VSS N4 VDDIO_DDR
AE15 AVDD09_VCO_HS0 AU25 HS_S1_RX_N9 N5 VDDIO_DDR


AE16 VSS AU26 VSS N6 VSS
AE17 VDD AU27 HS_S1_RX_P11 P1 DDR_TEN
AE18 VSS AU28 VSS P11 AVDD18_DATA_L16_DDR
AE19 AVDD09_VCO_HS1 AU29 HS_S1_TX_P12 P12 AVSS18_DATA_L16_DDR
a l
AE2 DDR_ADDR11 AU3 HS_S0_RX_N2 P13 VDDIO_DDR
t i
n
AE20 VSS AU30 VSS P14 VDD
AE21 VDD AU31 HS_S1_TX_N14 P15 VSS
d e
fi
on
AE23 AVDD09_VCO_HS2 AU33 HS_S1_RX_N12 P17 VSS
C
AE25 VDD AU35 HS_S1_RX_P14 P19 VSS
ec
AE26 VSS AU36 VSS P2 DDR_CKE1
nt
AE3 DDR_CKE3 AU4 VSS P21 VSS
AE32 VSS AU5 HS_S0_TX_P3
e P22 VDD
AE33
AE34
VSS
VSS
AU6
AU7
VSS
l C
HS_S0_TX_N5
P23
P24
VSS
VDD
AE35 VSS AU8
ti
VSS
a P25 VSS
AE36
AE37
VSS
VSS
AU9
B1
e n
HS_S0_RX_N3
VSS
P26
P27
VDDIO18
VDDIO3318_GPIO_7_0
fid
AE4 VDDIO_DDR B10 HS_TX_P0 P3 DDR_ODT0
n
AE5 VDDIO_DDR B11 VSS P32 BOOT_I2C_SA1
AE6 VSS
o B12 HS_CMU_REFCLK_P P33 FUSE_FAIL
AF1 DDR_RST_B
C B13 AVSS_PCIE P34 BOOT_CPU_SPEED
c
AF11 AVDD09_HS0 B14 PCIE_TX_N P35 VSS
AF12
t e
AVDD09_HS0 B15 PCIE_RX_P P36 TOD_PULSE
AF13
AF14
e n
AVDD09_HS0
AVDD09_HS0
B16
B17
AVSS_PCIE
PCIE_REFCLK_P
P4
P5
DDR_CS_B2
VDDIO_DDR
AF15
AF16 C VSS
VSS
B18
B19
CORE_REFCLK_P
PTP_REFCLK_N
P6
R11
VSS
DDR_VREF1
AF17 AVDD09_HS1 B2 DDR_DQ10 R12 DDR_VREF0
AF18 AVDD09_HS1 B20 MSH_DATA2 R13 VDDIO_DDR
AF19 VSS B21 MSH_DATA0 R14 VSS
AF2 DDR_ADDR5 B22 MSH_DATA3 R15 VDD
AF20 AVDD09_HS1 B23 MSH_CMD R16 VSS
AF21 AVDD09_HS1 B24 MSH_CLK R17 VDD
AF22 VSS B25 QSPI_DATA0 R18 VSS


AF23 VSS B26 QSPI_DATA1 R19 VDD
AF24 AVDD09_HS2 B27 QSPI_CS1 R2 DDR_CKE0
AF25 AVDD09_HS2 B28 TCK R20 VSS
AF26 AVDD09_HS2 B29 SDA_SOC1 R21 VDD
a l
AF27 AVDD09_HS2 B3 DDR_DQ7 R22 VSS
t i
n
AF3 DDR_ALERT_B B30 MSCL1 R23 VDD
AF32 VSS B31 SDA_SOC0 R24 VSS
d e
fi
AF33 VSS B32 MDC_A0 R25 VDD
on
AF34 VSS B33 MDC_SOC R26 VDDIO18
AF35 VSS B34 MDC_A1 R27 VDDOUT_GPIO_7_0
C
AF36 NC B35 GPIOHS1 R3 VSS
ec
AF37 NC B36 GPIO0 R32 BOOT_I2C_SA0
nt
AF4 DDR_BA0 B37 VSS R33 BOOT_RESV0
AF5 VDDIO_DDR B4 DDR_DQ4 R34 SYNC_CLK
AF6 VSS B5 DDR_DQS_P0
e R35 SYNC_PULSE
AG11
AG12
VSS
VSS
B6
B7
DDR_DQ2
VSS
l C R36
R37
SYNC_CODE
TOD_CODE
AG13 VSS B8
ti a
HS_RX_P0 R4 VSS
AG14
AG15
VSS
VSS
B9
C1
e n
VSS
DDR_DQS_N1
R5
R6
VDDIO_DDR
VSS
fid
AG16 VSS C10 VSS T1 DDR_CAS_B
n
AG17 VSS C11 VSS T11 AVDD18_DATA_H8_DDR
AG18 VSS
o C12 VSS T12 AVSS18_DATA_H8_DDR
AG19 AVDD18_HS1
C C13 AVSS_PCIE T13 VDDIO_DDR
c
AG2 VSS C14 AVSS_PCIE T14 VDD
AG20 VSS
t e C15 PCIE_RX_N T15 VSS

AG21
AG22
VSS
e
VSSn C16
C17
AVSS_PCIE
AVSS_PCIE
T16
T17
VDD
VSS
AG23
AG24 C VSS
VSS
C18
C19
CORE_REFCLK_N
VSS
T18
T19
VDD
VSS
AG25 VSS C2 DDR_DQS_P1 T2 DDR_CS_B1
AG26 VSS C20 MSH_DATA1 T20 VDD
AG27 VSS C21 VSS T21 VSS
AG3 VSS C22 MSH_DATA5 T22 VDD
AG32 VSS C23 MSH_RST_B T23 VSS
AG33 VSS C24 VSS T24 VDD
AG34 NC C25 SD_SW_VOLT_EN T25 VSS


AG35 NC C26 QSPI_CS0 T26 VDDIO18
AG36 VSS C27 VSS T27 VDDIO33
AG37 VSS C28 TMS T3 DDR_CS_B3
AG4 DDR_ZQ C29 SCL_SOC1 T32 BOOT_CPU_DIS
a l
AG5 VSS C3 DDR_DQ14 T33 BOOT_RESV1
t i
n
AG6 VSS C30 VSS T34 VSS
AH1 USB_D_P C31 MSDA1 T35 VSS
d e
fi
AH11 VSS C32 MDIO_A0 T36 RECV_CLK1
on
AH12 AVDD18_HS0 C33 VSS T37 RECV_CLK0
AH13 AVDD18_HS0 C34 MDIO_SOC T4 VDDIO_DDR
C
AH14 AVDD18_HS0 C35 GPIO1 T5 VDDIO_DDR
ec
AH15 AVDD18_HS0 C36 GPIO2 T6 VSS
nt
AH16 VSS C37 GPIO3 U1 DDR_RAS_B
AH17 VSS C4 DDR_DM0 U11 VSS
AH18 AVDD18_HS1 C5 VSS
e U12 VSS
AH19
AH2
AVDD18_HS1
USB_D_N
C6
C7
DDR_DQS_N0
VSS
l C U13
U14
VDDIO_DDR_CK
VSS
AH20 AVDD18_HS1 C8
ti
VSS
a U15 VDD
AH21
AH22
VSS
VSS
C9
D10
e n
VSS
HS_TX_P1
U16
U17
VSS
VDD
fid
AH23 AVDD18_HS2 D11 VSS U18 VSS
n
AH24 AVDD18_HS2 D12 VSS U19 VDD
AH25 AVDD18_HS2
o D13 AVSS_PCIE U2 DDR_WE_B
AH26 AVDD18_HS2
C D14 AVSS_PCIE U20 VSS
c
AH27 VSS D15 AVSS_PCIE U21 VDD
AH3 VSS
t e D16 AVSS_PCIE U22 VSS

AH32
AH33
VSS
e
VSSn D17
D18
PCIE_TPOUT
VSS
U23
U24
VDD
VSS
AH34
AH35 C VSS
VSS
D19
D2
VSS
DDR_DQ13
U25
U26
VDD
VDDOUT_G1
AH36 HS_S2_TX_N17 D20 MSH_DATA7 U27 VDDIO33
AH37 HS_S2_TX_P17 D21 VSS U3 DDR_ADDR14
AH4 VSS D22 SD_WP U32 BOOT_TEST_MODE
AH5 VSS D23 VSS U33 RECV_CLK2
AH6 VSS D24 VSS U34 VSS
AJ1 VSS D25 QSPI_DATA3 U35 HSS_REFCLK_N
AJ2 VSS D26 VSS U36 HSS_REFCLK_P


AJ3 VSS D27 VSS U4 DDR_ODT3
AJ32 VSS D28 TDO U5 VDDIO_DDR
AJ33 VSS D29 VSS U6 VSS
AJ34 VSS D3 VSS V11 AVSS18_ADD_DDR
a l
AJ35 VSS D30 VSS V12 AVDD18_ADD_DDR
t i
n
AJ36 VSS D31 MSCL0 V13 VDDIO_DDR
AJ37 VSS D32 VSS V14 VDD
d e
fi
AJ4 USB_VBUS0 D33 DEBUG_MODE0 V15 VSS
on
AJ5 USB_TXR_TUNE D34 USB_OVC_B V16 VDD
AJ6 USB_ID0 D35 GPIO4 V17 VSS
C
AK1 HS_S0_TX_P0 D36 GPIO5 V18 VDD
ec
AK2 HS_S0_TX_N0 D37 GPIO6 V19 VSS
nt
AK3 VSS D4 DDR_DQ11 V2 DDR_BA2
AK32 VSS D5 DDR_DQ3 V20 VDD
AK33 VSS D6 DDR_DQ5
e V21 VSS
AK34
AK35
VSS
VSS
D7
D8
VSS
HS_RX_P1
l C V22
V23
VDD
VSS
AK36 HS_S2_RX_N16 D9
ti
VSS
a V24 VDD
AK37
AK4
HS_S2_RX_P16
VSS
E1
E10
e n
DDR_DM1
HS_TX_N1
V25
V26
VSS
VDDOUT_G2
fid
AK5 VSS E11 VSS V27 VDDIO33
n
AK6 VSS E12 VSS V3 VSS
AL1 VSS
o E13 AVSS_PCIE V32 BOOT_RESV2
AL2 VSS
C E14 AVSS_PCIE V33 BOOT_PCIE_RP_MODE
c
AL3 HS_S0_TX_N1 E15 AVSS_PCIE V34 VSS
AL32 VSS
t e E16 AVSS_PCIE V35 VSS

AL33
AL34
VSS
e n
HS_S1_RX_N15
E17
E18
PCIE_REXT
VSS
V36
V37
HS_S2_REFCLK_N
HS_S2_REFCLK_P
AL35
AL36 C HS_S1_RX_P15
VSS
E19
E2
VSS
DDR_DQ9
V4
V5
VSS
VDDIO_DDR
AL37 VSS E20 VSS V6 VSS
AL4 HS_S0_TX_P1 E21 GPIOHS2 W1 DDR_ADDR12
AL5 VSS E22 GPIOHS3 W11 VSS
AL6 VSS E23 GPIOHS4 W12 VSS
AM1 HS_S0_TX_N2 E24 GPIOHS5 W13 VDD
AM10 VSS E25 GPIOHS6 W14 VSS
AM11 VSS E26 GPIOHS7 W15 VDD


AM12 VSS E27 GPIOHS8 W16 VSS
AM13 VSS E28 MDIO_B1 W17 VDD
AM14 VSS E29 MDC_B1 W18 VSS
AM15 VSS E3 DDR_DQ12 W19 VDD
a l
AM16 VSS E30 MDIO_B0 W2 DDR_ADDR15
t i
n
AM17 VSS E31 MDC_B0 W20 VSS
AM18 VSS E32 DEBUG_MODE1 W21 VDD
d e
fi
AM19 VSS E33 DEBUG_MODE2 W22 VSS
on
AM2 HS_S0_TX_P2 E34 GPIO7 W23 VDD
AM20 VSS E35 VSS W24 VSS
C
AM21 VSS E36 WDT0_RST_B W25 VDD
ec
AM22 VSS E4 DDR_DQ15 W26 VDDOUT_G3
nt
AM23 VSS E5 VDDIO_DDR W27 VDDIO33
AM24 VSS E6 VDDIO_DDR W3 DDR_ODT2
AM25 VSS E7 VSS
e W32 VSS
AM26
AM27
VSS
VSS
E8
E9
HS_RX_N1
VSS
l C W33
W34
VSS
VSS
AM28 VSS F10
ti
VSS
a W35 HS_S1_REFCLK_N
AM29
AM3
VSS
VSS
F11
F12
e n
VSS
VSS
W36
W4
HS_S1_REFCLK_P
VDDIO_DDR
fid
AM30 VSS F13 AVSS_PCIE W5 VDDIO_DDR
n
AM31 VSS F14 AVSS_PCIE W6 VSS
AM32 VSS
o F15 AVSS_PCIE Y1 DDR_ADDR1
AM33 VSS
C F16 AVSS_PCIE Y11 AVDD33_USB
c
AM34 VSS F17 VSS Y12 VDD
AM35 VSS
t e F18 THM_VREFP Y13 VSS

AM36
AM37
VSS
e n
HS_S2_TX_P16
F19
F2
THM_VINS0
DDR_DQ8
Y14
Y15
VDD
VSS
AM4
AM5 C VSS
VSS
F20
F21
VSS
VDDIO18_EFUSE_MEM
Y16
Y17
VDD
VSS
AM6 VSS F22 VDDIO18_EFUSE_INF Y18 VDD
O
AM7 VSS F23 GPIOHS9 Y19 VSS
AM8 VSS F24 GPIOHS10 Y2 DDR_ADDR10
AM9 VSS F25 GPIOHS11 Y20 VDD
AN1 VSS F26 GPIOHS12 Y21 VSS
AN10 VSS F27 GPIOHS13 Y22 VDD


AN11 VSS F28 GPIOHS14 Y23 VSS
AN12 VSS F29 GPIOHS15 Y24 VDD
AN13 VSS F3 VSS Y25 VSS
AN14 VSS F30 GPIOHS16 Y26 VDDOUT_G4
a l
AN15 VSS F31 GPIOHS17 Y27 VDDIO33
t i
n
AN16 VSS F32 DEBUG0 Y3 DDR_ADDR2
AN17 VSS F33 DEBUG4 Y32 VSS
d e
fi
AN18 VSS F34 WDT1_RST_B Y33 VSS
on
AN19 VSS F35 BOOT_STRAP1 Y34 VSS
AN2 VSS F36 BOOT_STRAP0 Y35 VSS
C
AN20 VSS F37 BOOT_STRAP2 Y36 HS_S0_REFCLK_N
ec
AN21 VSS F4 VSS Y37 HS_S0_REFCLK_P
nt
AN22 VSS F5 VDDIO_DDR Y4 DDR_ADDR4
AN23 VSS F6 VSS Y5 VDDIO_DDR
AN24 VSS F7 VSS
e Y6 VSS
AN25 VSS F8 VSS
l C
t i a
Table 7-8 : Pin-Out Table (by Pin name)
n
de
Ball Name Ball Location Ball Name Ball Location Ball Name Ball Location
fi
AVDD18_ADD_DDR V12 MDIO_A0 C32 VSS AJ2
AVSS18_ADD_DDR
AVDD18_PLL
V11
K21
o n MDIO_A1
MDIO_B0
A34
E30
VSS
VSS
AJ3
AJ32
AVDD18_DDRPLL K19
C MDIO_B1 E28 VSS AJ33
AVSS_PLL
e c L21 MDIO_SOC C34 VSS AJ34
t
AVSS_DDRPLL L19 MSCL0 D31 VSS AJ35
BOOT_CPU_DIS
BOOT_CPU_SPEED
e n T32
P34
MSCL1
MSDA0
B30
A32
VSS
VSS
AJ36
AJ37
C
BOOT_I2C_SA0
BOOT_I2C_SA1
R32
P32
MSDA1
MSH_CLK
C31
B24
VSS
VSS
AK3
AK32
BOOT_LPBK_TEST_MODE K32 MSH_CMD B23 VSS AK33
BOOT_PCIE_AUTO_MODE L34 MSH_DATA0 B21 VSS AK34
BOOT_PCIE_FORCE_MODE N32 MSH_DATA1 C20 VSS AK35
BOOT_PCIE_RP_MODE V33 MSH_DATA2 B20 VSS AK4
BOOT_RESV0 R33 MSH_DATA3 B22 VSS AK5
BOOT_RESV1 T33 MSH_DATA4 A22 VSS AK6
BOOT_RESV2 V32 MSH_DATA5 C22 VSS AL1

BOOT_STRAP0 F36 MSH_DATA6 A20 VSS AL2
BOOT_STRAP1 F35 MSH_DATA7 D20 VSS AL32
BOOT_STRAP2 F37 MSH_RST_B C23 VSS AL33
BOOT_TEST_MODE U32 AVDD09_PCIE N15 VSS AL36
BOOT_USB_VREG_BYP J35 AVDD09_VCO_PCIE L14 VSS AL37
a l
CFG_GPIO_SEL J32 AVDD18_PCIE L15 VSS AL5
t i
CFG_PLL_CORE_BYP
CFG_PLL_SUP_BYP
L32
M32
AVSS_PCIE
AVSS_PCIE
A13
A16
VSS
VSS
e
AL6
n
AM10
CORE_REFCLK_N C18 AVSS_PCIE B13 VSS
fi d AM11
on
CORE_REFCLK_P B18 AVSS_PCIE B16 VSS AM12
AVDD18_RSV AB22 AVSS_PCIE C13 VSS AM13
AVDD18_RSV AB23 AVSS_PCIE C14
C VSS AM14
ec
nt
AVDD18_RSV AB26 AVSS_PCIE D13 VSS AM17
AVDD18_RSV AB27 AVSS_PCIE
eD14 VSS AM18
VDD_RSV
VDD_RSV
AD22
AD23
AVSS_PCIE
AVSS_PCIE
l C D15
D16
VSS
VSS
AM19
AM20
VDD_RSV AD24
t
AVSS_PCIE
i a E13 VSS AM21
n
VDD_RSV AD25 AVSS_PCIE E14 VSS AM22
VDD_RSV AD26
d e
AVSS_PCIE E15 VSS AM23
fi
VDD_RSV AD27 AVSS_PCIE E16 VSS AM24
n
AVDD18_DATA_H8_DDR T11 AVSS_PCIE F13 VSS AM25
AVSS18_DATA_H8_DDR T12
o AVSS_PCIE F14 VSS AM26
C
VDDIO_DDR_CK U13 AVSS_PCIE F15 VSS AM27
c
DDR_ADDR0 AB2 AVSS_PCIE F16 VSS AM28
DDR_ADDR1
te Y1 AVSS_PCIE K13 VSS AM29
n
DDR_ADDR10 Y2 AVSS_PCIE K14 VSS AM3
DDR_ADDR11
e AE2 AVSS_PCIE K15 VSS AM30
C
DDR_ADDR12 W1 AVSS_PCIE L13 VSS AM31
DDR_ADDR13 AE1 AVSS_PCIE M15 VSS AM32
DDR_ADDR14 U3 PCIE_REFCLK_N A17 VSS AM33
DDR_ADDR15 W2 PCIE_REFCLK_P B17 VSS AM34
DDR_ADDR2 Y3 PCIE_REXT E17 VSS AM35
DDR_ADDR3 AC4 PCIE_RX_N C15 VSS AM36
DDR_ADDR4 Y4 PCIE_RX_P B15 VSS AM4
DDR_ADDR5 AF2 PCIE_TPOUT D17 VSS AM5
DDR_ADDR6 AB1 PCIE_TX_N B14 VSS AM6

DDR_ADDR7 AC3 PCIE_TX_P A14 VSS AM7
DDR_ADDR8 AC2 PTP_REFCLK_N B19 VSS AM8
DDR_ADDR9 AC1 PTP_REFCLK_P A19 VSS AM9
DDR_ALERT_B AF3 QSPI_CLK A25 VSS AN1
DDR_BA0 AF4 QSPI_CS0 C26 VSS AN10
a l
DDR_BA1 AA2 QSPI_CS1 B27 VSS AN11
t i
DDR_BA2
DDR_CAS_B
V2
T1
QSPI_DATA0
QSPI_DATA1
B25
B26
VSS
VSS
e n
AN12
AN13
DDR_CKE0 R2 QSPI_DATA2 A26 VSS
fi d AN14
on
DDR_CKE1 P2 QSPI_DATA3 D25 VSS AN15
DDR_CKE2 AB3 RECV_CLK0 T37 VSS AN16
DDR_CKE3 AE3 RECV_CLK1 T36
C VSS AN17
ec
DDR_CLK_N0 L1 RECV_CLK2 U33 VSS AN18
nt
DDR_CLK_N1 M2 RST_SUP_B K34 VSS AN19
DDR_CLK_P0 L2 SCL_SOC0 A31 VSS AN2
DDR_CLK_P1 M3 SCL_SOC1
eC29 VSS AN20
DDR_CS_B0
DDR_CS_B1
N1
T2
SD_DET_B
SD_SW_VOLT_EN
l C A23
C25
VSS
VSS
AN21
AN22
DDR_CS_B2 P4 SD_WP
t ia D22 VSS AN23
n
DDR_CS_B3 T3 SDA_SOC0 B31 VSS AN24
DDR_DM0 C4
d e
SDA_SOC1 B29 VSS AN25
fi
DDR_DM1 E1 AVDD18_DATA_L16_DDR P11 VSS AN26
n
DDR_DM2 K2 AVSS18_DATA_L16_DDR P12 VSS AN27
DDR_DQ0 A3
o SYNC_CLK R34 VSS AN28
C
DDR_DQ1 A4 SYNC_CODE R36 VSS AN29
c
DDR_DQ10 B2 SYNC_PULSE R35 VSS AN3
DDR_DQ11
te D4 TCK B28 VSS AN30
n
DDR_DQ12 E3 TDI A29 VSS AN31
DDR_DQ13
e D2 TDO D28 VSS AN32
C
DDR_DQ14 C3 AVDD18_THM K16 VSS AN33
DDR_DQ15 E4 THM_VINS0 F19 VSS AN34
DDR_DQ16 J2 THM_VREFP F18 VSS AN35
DDR_DQ17 L4 TMS C28 VSS AN36
DDR_DQ18 G1 TOD_CODE R37 VSS AN4
DDR_DQ19 K1 TOD_PULSE P36 VSS AN5
DDR_DQ2 B6 TOD_REFCLK G33 VSS AN6
DDR_DQ20 G2 TRST_B A28 VSS AN7
DDR_DQ21 K3 UART_RXD0 G37 VSS AN8

DDR_DQ22 G3 UART_RXD1 H36 VSS AN9
DDR_DQ23 H4 UART_RXD2 H34 VSS AP1
DDR_DQ3 D5 UART_TXD0 G36 VSS AP11
DDR_DQ4 B4 UART_TXD1 G35 VSS AP12
DDR_DQ5 D6 UART_TXD2 G34 VSS AP13
a l
DDR_DQ6 A6 USB_D_N AH2 VSS AP15
t i
DDR_DQ7
DDR_DQ8
B3
F2
USB_D_P
VDD_USB
AH1
AA11
VSS
VSS
e n
AP16
AP17
DDR_DQ9 E2 USB_ID0 AJ6 VSS
fi d AP19
on
DDR_DQS_N0 C6 USB_OVC_B D34 VSS AP2
DDR_DQS_N1 C1 USB_TXR_TUNE AJ5 VSS AP20
DDR_DQS_N2 H2 USB_VBUS0 AJ4
C VSS AP21
ec
DDR_DQS_P0 B5 AVDD33_USB Y11 VSS AP23
nt
DDR_DQS_P1 C2 AVDD33_USB AB11 VSS AP24
DDR_DQS_P2 H1 VDD AA13 VSS AP25
DDR_ODT0 P3 VDD
eAA15 VSS AP27
DDR_ODT1
DDR_ODT2
N2
W3
VDD
VDD
l C AA17
AA19
VSS
VSS
AP28
AP29
DDR_ODT3 U4 VDD
t i a AA21 VSS AP31
n
DDR_PAR AD2 VDD AA23 VSS AP32
DDR_RAS_B U1 VDD
d e AA25 VSS AP33
fi
DDR_RST_B AF1 VDD AB12 VSS AP35
n
DDR_TEN P1 VDD AB14 VSS AP36
VDDIO_DDR AA5
o VDD AB16 VSS AP5
C
VDDIO_DDR AB4 VDD AB18 VSS AP7
c
VDDIO_DDR AB5 VDD AB20 VSS AP8
VDDIO_DDR
te AC5 VDD AC13 VSS AP9
n
VDDIO_DDR AD5 VDD AC15 VSS AR11
VDDIO_DDR
e AE4 VDD AC17 VSS AR12
C
VDDIO_DDR AE5 VDD AC19 VSS AR13
VDDIO_DDR AF5 VDD AC21 VSS AR15
VDDIO_DDR E5 VDD AD11 VSS AR16
VDDIO_DDR E6 VDD AD12 VSS AR17
VDDIO_DDR F5 VDD AD14 VSS AR19
VDDIO_DDR G4 VDD AD16 VSS AR20
VDDIO_DDR G5 VDD AD18 VSS AR21
VDDIO_DDR H5 VDD AD20 VSS AR23
VDDIO_DDR J5 VDD AE13 VSS AR24

VDDIO_DDR K4 VDD AE17 VSS AR25
VDDIO_DDR K5 VDD AE21 VSS AR27
VDDIO_DDR L5 VDD AE25 VSS AR28
VDDIO_DDR M5 VDD K17 VSS AR29
VDDIO_DDR N4 VDD K18 VSS AR3
a l
VDDIO_DDR N5 VDD L17 VSS AR31
t i
VDDIO_DDR
VDDIO_DDR
P13
P5
VDD
VDD
L18
M16
VSS
VSS
e n
AR32
AR33
VDDIO_DDR R13 VDD M17 VSS
fi d AR35
on
VDDIO_DDR R5 VDD M18 VSS AR36
VDDIO_DDR T13 VDD M20 VSS AR4
VDDIO_DDR T4 VDD M22
C VSS AR5
ec
VDDIO_DDR T5 VDD M24 VSS AR7
nt
VDDIO_DDR U5 VDD N17 VSS AR8
VDDIO_DDR V13 VDD N19 VSS AR9
VDDIO_DDR V5 VDD
eN21 VSS AT1
VDDIO_DDR
VDDIO_DDR
W4
W5
VDD
VDD
l C N23
N25
VSS
VSS
AT10
AT12
VDDIO_DDR Y5 VDD
t ia P14 VSS AT14
n
DDR_VREF0 R12 VDD P16 VSS AT16
DDR_VREF1 R11 VDD
d e P18 VSS AT18
fi
DDR_WE_B U2 VDD P20 VSS AT2
n
DDR_ZQ AG4 VDD P22 VSS AT20
DEBUG_MODE0 D33
o VDD P24 VSS AT22
C
DEBUG_MODE1 E32 VDD R15 VSS AT24
c
DEBUG_MODE2 E33 VDD R17 VSS AT26
DEBUG0
te F32 VDD R19 VSS AT28
n
DEBUG1 G32 VDD R21 VSS AT30
DEBUG2
e H32 VDD R23 VSS AT32
C
DEBUG3 L33 VDD R25 VSS AT34
DEBUG4 F33 VDD T14 VSS AT36
DEBUG5 H33 VDD T16 VSS AT37
DEBUG6 M33 VDD T18 VSS AT4
DEBUG7 K33 VDD T20 VSS AT6
VDDIO18_EFUSE_INFO F22 VDD T22 VSS AT8
VDDIO18_EFUSE_MEM F21 VDD T24 VSS AU1
FUSE_DONE N33 VDD U15 VSS AU10
FUSE_FAIL P33 VDD U17 VSS AU12

GPIO0 B36 VDD U19 VSS AU14
GPIO1 C35 VDD U21 VSS AU16
GPIO10 J37 VDD U23 VSS AU18
GPIO11 K35 VDD U25 VSS AU2
GPIO12 K36 VDD V14 VSS AU20
a l
GPIO13 K37 VDD V16 VSS AU22
t i
GPIO14
GPIO15
L36
M35
VDD
VDD
V18
V20
VSS
VSS
e
AU24
AU26 n
GPIO2 C36 VDD V22 VSS
fi d AU28
on
GPIO3 C37 VDD V24 VSS AU30
GPIO4 D35 VDD W13 VSS AU32
GPIO5 D36 VDD W15
C VSS AU34
ec
GPIO6 D37 VDD W17 VSS AU36
nt
GPIO7 E34 VDD W19 VSS AU37
GPIO8 J34 VDD W21 VSS AU4
GPIO9 J36 VDD
eW23 VSS AU6
GPIOHS0
GPIOHS1
A35
B35
VDD
VDD
l C W25
Y12
VSS
VSS
AU8
B1
GPIOHS10 F24 VDD
t i a Y14 VSS B11
n
GPIOHS11 F25 VDD Y16 VSS B37
GPIOHS12 F26 VDD
d e Y18 VSS B7
fi
GPIOHS13 F27 VDD Y20 VSS B9
n
GPIOHS14 F28 VDD Y22 VSS C10
GPIOHS15 F29
o VDD Y24 VSS C11
C
GPIOHS16 F30 VDD09_DDRPLL K20 VSS C12
c
GPIOHS17 F31 AVDD18_LVDS K22 VSS C19
GPIOHS2
te E21 VDDIO18 T26 VSS C21
n
GPIOHS3 E22 VDDOUT_GPIO_7_0 R27 VSS C24
GPIOHS4
e E23 VDDIO18 P26 VSS C27
C
GPIOHS5 E24 VDDIO18 R26 VSS C30
GPIOHS6 E25 VDDOUT_MDIO_A M26 VSS C33
GPIOHS7 E26 VDDOUT_MDIO_B N26 VSS C5
GPIOHS8 E27 VDDOUT_MSH L23 VSS C7
GPIOHS9 F23 VDDOUT_RECV AA26 VSS C8
HS_CMU_REFCLK_N A12 VDDOUT_G1 U26 VSS C9
HS_CMU_REFCLK_P B12 VDDOUT_G2 V26 VSS D11
HS_RX_N0 A8 VDDOUT_G3 W26 VSS D12
HS_RX_N1 E8 VDDOUT_G4 Y26 VSS D18

HS_RX_P0 B8 VDDOUT_G5 L24 VSS D19
HS_RX_P1 D8 VDDIO33 K27 VSS D21
AVDD09_HS0 AF11 VDDIO33 L27 VSS D23
AVDD09_HS0 AF12 VDDIO33 T27 VSS D24
AVDD09_HS0 AF13 VDDIO33 U27 VSS D26
a l
AVDD09_HS0 AF14 VDDIO33 V27 VSS D27
t i
AVDD09_VCO_HS0
AVDD18_HS0
AE15
AH12
VDDIO33
VDDIO33
W27
Y27
VSS
VSS
e
D29
D3 n
AVDD18_HS0 AH13 VDDIO3318_GPIO_7_0 P27 VSS
fi d D30
on
AVDD18_HS0 AH14 VDDIO3312_MDIO_A M27 VSS D32
AVDD18_HS0 AH15 VDDIO3312_MDIO_B N27 VSS D7
HS_S0_REFCLK_N Y36 VDDIO3318_MSH K25
C VSS D9
ec
HS_S0_REFCLK_P Y37 VDDIO3318_MSH K26 VSS E11
nt
HS_S0_RX_N0 AP3 VDDIO3318_RECV AA27 VSS E12
HS_S0_RX_N1 AR2 VSS A1 VSS E18
HS_S0_RX_N2 AU3 VSS
eA11 VSS E19
HS_S0_RX_N3
HS_S0_RX_N4
AU9
AP10
VSS
VSS
l C A2
A36
VSS
VSS
E20
E35
HS_S0_RX_N5 AT11 VSS
t i a A37 VSS E7
n
HS_S0_RX_N6 AU17 VSS A9 VSS E9
HS_S0_RX_N7 AP18 VSS
d e AA12 VSS F10
fi
HS_S0_RX_P0 AP4 VSS AA14 VSS F11
n
HS_S0_RX_P1 AR1 VSS AA16 VSS F12
HS_S0_RX_P2 AT3
o VSS AA18 VSS F17
C
HS_S0_RX_P3 AT9 VSS AA20 VSS F20
c
HS_S0_RX_P4 AR10 VSS AA22 VSS F3
HS_S0_RX_P5
te AU11 VSS AA24 VSS F4
n
HS_S0_RX_P6 AT17 VSS AA3 VSS F6
HS_S0_RX_P7
e AR18 VSS AA32 VSS F7
C
HS_S0_TX_N0 AK2 VSS AA33 VSS F8
HS_S0_TX_N1 AL3 VSS AA34 VSS F9
HS_S0_TX_N2 AM1 VSS AA35 VSS G6
HS_S0_TX_N3 AT5 VSS AA36 VSS H3
HS_S0_TX_N4 AR6 VSS AA37 VSS H35
HS_S0_TX_N5 AU7 VSS AA4 VSS H6
HS_S0_TX_N6 AT13 VSS AA6 VSS J3
HS_S0_TX_N7 AR14 VSS AB13 VSS J33
HS_S0_TX_P0 AK1 VSS AB15 VSS J4

HS_S0_TX_P1 AL4 VSS AB17 VSS J6
HS_S0_TX_P2 AM2 VSS AB19 VSS K11
HS_S0_TX_P3 AU5 VSS AB21 VSS K23
HS_S0_TX_P4 AP6 VSS AB32 VSS K24
HS_S0_TX_P5 AT7 VSS AB33 VSS K6
a l
HS_S0_TX_P6 AU13 VSS AB34 VSS L11
t i
HS_S0_TX_P7
AVDD09_HS1
AP14
AF17
VSS
VSS
AB35
AB6
VSS
VSS
e
L12
L16 n
AVDD09_HS1 AF18 VSS AC11 VSS
fi d L22
on
AVDD09_HS1 AF20 VSS AC12 VSS L3
AVDD09_HS1 AF21 VSS AC14 VSS L35
AVDD09_VCO_HS1 AE19 VSS AC16
C VSS L6
ec
AVDD18_HS1 AG19 VSS AC18 VSS M19
nt
AVDD18_HS1 AH18 VSS AC20 VSS M21
AVDD18_HS1 AH19 VSS AC22 VSS M23
AVDD18_HS1 AH20 VSS
eAC23 VSS M25
HS_S1_REFCLK_N
HS_S1_REFCLK_P
W35
W36
VSS
VSS
l C AC24
AC25
VSS
VSS
M4
M6
HS_S1_RX_N10 AP26 VSS
t ia AC26 VSS N11
n
HS_S1_RX_N11 AT27 VSS AC27 VSS N14
HS_S1_RX_N12 AU33 VSS
d e AC32 VSS N16
fi
HS_S1_RX_N13 AP34 VSS AC33 VSS N18
n
HS_S1_RX_N15 AL34
o VSS AC37 VSS N22
C
c
HS_S1_RX_N9 AU25 VSS AD13 VSS N3
HS_S1_RX_P10
te AR26 VSS AD15 VSS N34
n
HS_S1_RX_P11 AU27 VSS AD17 VSS N6
HS_S1_RX_P12
e AT33 VSS AD19 VSS P15
C
HS_S1_RX_P13 AR34 VSS AD21 VSS P17
HS_S1_RX_P14 AU35 VSS AD3 VSS P19
HS_S1_RX_P15 AL35 VSS AD32 VSS P21
HS_S1_RX_P8 AU19 VSS AD33 VSS P23
HS_S1_RX_P9 AT25 VSS AD34 VSS P25
HS_S1_TX_N10 AR22 VSS AD35 VSS P35
HS_S1_TX_N11 AU23 VSS AD4 VSS P6
HS_S1_TX_N12 AT29 VSS AD6 VSS R14
HS_S1_TX_N13 AR30 VSS AE11 VSS R16

HS_S1_TX_N14 AU31 VSS AE12 VSS R18
HS_S1_TX_N15 AR37 VSS AE14 VSS R20
HS_S1_TX_N8 AU15 VSS AE16 VSS R22
HS_S1_TX_N9 AT21 VSS AE18 VSS R24
HS_S1_TX_P10 AP22 VSS AE20 VSS R3
a l
HS_S1_TX_P11 AT23 VSS AE22 VSS R4
t i
HS_S1_TX_P12
HS_S1_TX_P13
AU29
AP30
VSS
VSS
AE24
AE26
VSS
VSS
e
R6
T15 n
HS_S1_TX_P14 AT31 VSS AE27 VSS
fi d T17
on
HS_S1_TX_P15 AP37 VSS AE32 VSS T19
HS_S1_TX_P8 AT15 VSS AE33 VSS T21
HS_S1_TX_P9 AU21 VSS AE34
C VSS T23
ec
AVDD09_HS2 AF24 VSS AE35 VSS T25
nt
AVDD09_HS2 AF27 VSS
eAE6 VSS T6
AVDD09_VCO_HS2
AVDD18_HS2
AE23
AH23
VSS
VSS
l C AF15
AF16
VSS
VSS
U11
U12
AVDD18_HS2 AH24 VSS
t ia AF19 VSS U14
n
AVDD18_HS2 AH25 VSS AF22 VSS U16
AVDD18_HS2 AH26 VSS
d e AF23 VSS U18
fi
HS_S2_REFCLK_N V36 VSS AF32 VSS U20
n
HS_S2_REFCLK_P V37 VSS AF33 VSS U22
HS_S2_RX_N16 AK36
o VSS AF34 VSS U24
C
HS_S2_RX_N17 AD37 VSS AF35 VSS U34
c
NC AC34 VSS AF6 VSS U6
NC
te AB36 VSS AG11 VSS V15
n
HS_S2_RX_P16 AK37 VSS AG12 VSS V17
HS_S2_RX_P17
e AD36 VSS AG13 VSS V19
C
NC AC35 VSS AG14 VSS V21
NC AB37 VSS AG15 VSS V23
HS_S2_TX_N16 AN37 VSS AG16 VSS V25
HS_S2_TX_N17 AH36 VSS AG17 VSS V3
NC AG35 VSS AG18 VSS V34
NC AF37 VSS AG2 VSS V35
HS_S2_TX_P16 AM37 VSS AG20 VSS V4
HS_S2_TX_P17 AH37 VSS AG21 VSS V6
NC AG34 VSS AG22 VSS W11

NC AF36 VSS AG23 VSS W12
AVDD09_HS3 M14 VSS AG24 VSS W14
AVDD09_HS3 N12 VSS AG25 VSS W16
AVDD09_HS3 N13 VSS AG26 VSS W18
AVDD09_VCO_HS3 K12 VSS AG27 VSS W20
a l
AVDD18_HS3 M11 VSS AG3 VSS W22
t i
AVDD18_HS3
AVDD18_HS3
M12
M13
VSS
VSS
AG32
AG33
VSS
VSS
e
W24
W32 n
HS_TX_N0 A10 VSS AG36 VSS
fi d W33
on
HS_TX_N1 E10 VSS AG37 VSS W34
HS_TX_P0 B10 VSS AG5 VSS W6
HS_TX_P1 D10 VSS AG6
C VSS Y13
ec
HSS_REFCLK_N U35 VSS AH11 VSS Y15
nt
HSS_REFCLK_P U36 VSS AH16 VSS Y17
VDDIO18 L25 VSS AH17 VSS Y19
VDDIO18 L26 VSS
eAH21 VSS Y21
INTR_B0
INTR_B1
M36
M34
VSS
VSS
l C AH22
AH27
VSS
VSS
Y23
Y25
INTR_B2 M37 VSS
t ia AH3 VSS Y32
n
INTR_B3 N37 VSS AH32 VSS Y33
LED_CLK N35 VSS
d e AH33 VSS Y34
fi
LED_DATA N36 VSS AH34 VSS Y35
n
MDC_A0 B32 VSS AH35 VSS Y6
MDC_A1 B34
o VSS AH4 VSS_DDRPLL L20
C
MDC_B0 E31 VSS AH5 WDT0_RST_B E36
c
MDC_B1 E29 VSS AH6 WDT1_RST_B F34
MDC_SOC
te B33 VSS AJ1
e n
C

Pin Information
8 Pin Information
i a l
8.1 Pin information –Grouped by function n t
d e
fi
Note[1]: PU/PD is internal Pull Up or Pull Down of LVCMOS IO, the internal pull-up resistor
ranges from 33 kΩ to 88K kΩ (typical value is 58K kΩ) while the internal pull-down resistor
on
ranges from 34K kΩ to 93 kΩ (typical value is 60K kΩ)
Note[2]: If not indicate specifically, LVCMOS is 3.3V (typ) IO
C
Note[3]: “I”/”O”/”B” in Type column represent “Input”/”Output”/”Bi-Direction” respectively.
e
Note[4]: “OD” is open-drain IO, external pull-up resistor should be used. c
n t
Note[5]: DDR SSTL-15 voltage 1.35V(DDR3L) or 1.5V(DDR3), 1.2V(DDR4) SSTL and POD can be
e
selected via configuring on die termination.
C
Note[6]: Support 1.8V/3.3V I/O, if the frequency exceeds 50MHz, it is recommended to use 1.8
I/O, for 0~50Mhz frequency, 1.8 /3.3V can be used.
a l
while used as input.
t i
Note[7]: The pull up or pull down are only effective for those input PAD or bi-directional PAD
e n
d
Table 8-1 : Pin information –Function Signals
Pin Name Type
n fi Rate Pin
#
PU/
PD
Description
Octal SerDes Interface

o
HS_S[0:1]_REFCLK_P
C
I LVDS 156.25MHz 4 - HSS input differential clock, impedance
HS_S[0:1]_REFCLK_N
e c 100±10% Ohm.
n t
HS_S[0:1]_RX_P[7:0]
HS_S[0:1]_RX_N[7:0]
I CML IN 1.25G~10.3125Gbps 32 - 1.25G~10.3125Gbps SerDes links input.
Typical configurations are:
e  SGMII, 1.25Gbps
C
 XAUI/10GBASE-KX4, 3.125Gbps
 QSGMII, 5Gbps
 Usxgmii-Multiport,5.15625Gbps
 XFI/SFI/10GBASE-KR/USXGMII-Multipor
t, 10.3125Gbps
 DXAUI, 6.25Gbps
 XLAUI/40GBASE-KR4/CR4,
10.3125Gbps
HS_S[0:1]_TX_P[7:0] O CML 1.25G~10.3125Gbps 32 - 1.25G~10.3125Gbps SerDes links output.
HS_S[0:1]_TX_N[7:0] OUT

Pin Information
Pin Name Type Rate Pin PU/ Description

# PD
SerDes (HSS12.5G) Interface
HS_S[2]_REFCLK_P I LVDS 156.25MHz 2 - HSS input differential clock, impedance
HS_S[2]_REFCLK_N 100±10% Ohm.
HS_S[2]_RX_P[1:0] I CML IN 1.25G~10.3125Gbps 4 - 1.25G~10.3125Gbps SerDes links input.
a l
i
HS_S[2]_RX_N[1:0] Typical configurations are:
 SGMII, 1.25Gbps
n
XFI/SFI/10GBASE-KR, 10.3125Gbpst
e

d
HS_S[2]_TX_P[1:0] O CML 1.25G~10.3125Gbps 4 - 1.25G~10.3125Gbps SerDes links output.
fi
HS_S[2]_TX_N[1:0] OUT
on
PCIE SerDes (HSS5G) Interface
PCIE_REFCLK_P I HCSL 100MHz 2 - PCIE input deferential reference clock
PCIE_REFCLK_N 100M.
C
c
PCIE _RX_P I CML IN 2.5G/5Gbps 2 - PCIE input data.
PCIE _RX_N
t e
n
PCIE_TX_P O CML 2.5G/5Gbps 2 - PCIE output data.
e
PCIE_TX_N OUT
C
PCIE_REXT I LVCMOS Static 1 - External resistor for termination
l
calibration: Connect 50 ohm external
a
resistor (1% precision) between
t i PCIE_REXT to AVDD18_PCIE (no need to
n
be close to BGA BALL)
e
PCIE_TPOUT O LVCMOS static 1 - Analog output test pin, reserved for
d
factory debug. Should connect to a via.
RST_SUP_B I LVCMOS
n fi
Static
Configuration
1 PD Global reset for chip, Schmitt trigger.
o Active low.
CFG_GPIO_SEL
C
I LVCMOS Static 1 PU 1'b1: GPIOHS[17:0] set to GPIO mode
e c 1'b0: GPIOHS[17:0] set to TRACE debug

mode
CFG_PLL_CORE_BYP
n t I LVCMOS static 1 PD If set, the internal PLL CORE will be
e
bypassed, should tie to GND while bring
up
C
CFG_PLL_SUP_BYP I LVCMOS static 1 PD If set, the internal PLL SUP will be
bypassed, should tie to GND while bring
up
Configuration
BOOT_PCIE_AUTO_M I LVCMOS - 1 PU Define the Reset Mode of PCIE:
ODE 1’b1: De-assert the related reset signals
of PCIe automatically
1’b0: user needs to de-assert the related
reset signal manually by I2CSlave
Interface(Debug Only)

Pin Information

# PD
BOOT_PCIE_FORCE_M I LVCMOS - 1 PU Define the PCIE Mode:
ODE 1’b1: Force to operate at GEN1 Mode;
1’b0: Normal Mode
BOOT_PCIE_RP_MODE I LVCMOS - 1 PU Tie to 3.3v if PCIe interface runs on
Rootport mode. Otherwise, tie to GND
a l
BOOT_STRAP[2:0] I LVCMOS - 3 PD
t i
Define the internal CPU boot up mode:
3’b000: ROM + QSPI
3’b001: Reserved
e n
3’b011: ROM + UART
fi d
on
3’b100: QSPI
3’b101: JTAG
3’b11x: Reserved
BOOT_CPU_SPEED I LVCMOS - 1 PU
C
0: Internal CPU runs 1.2GHz
c
1: Internal CPU runs 800MHz
e
BOOT_CPU_DIS I LVCMOS - 1 PD
n t
0: Enable internal CPU
1: Disable internal CPU, PCIe interface
e must be brought up for this mode.
lC
BOOT_TEST_MODE I LVCMOS - 1 PD 0: Function mode
1: Internal DFT Test mode
ia
CPU coresight JTAG should be under
n t function mode.
Tie to GND
BOOT_I2C_SA[1:0] I LVCMOS -
d e 2 PD I2C Slave address LSB 2bits
fi
7’b11_11xx (xx = 00 to 11)
n
BOOT_RESV0 I LVCMOS - 1 PU Connect to GND
BOOT_RESV1 I LVCMOS
o- 1 PU Connect to GND
BOOT_RESV2
C
I LVCMOS - 1 PU Connect to GND
BOOT_LPBK_TEST_M
ODE
e c I LVCMOS - 1 PD 0: Function mode
t
1: Set to Interface IP loopback test mode
n
Tie to GND
e GPIO Interface
C
GPIO[7:0] B LVCMOS 0-150MHz/0-50MHz 8 - General purpose IO
1.8V/3.3V GPIO[1:0]: also used in TsEngine
SysGpioMultiCtl.cfgGpio[N]Sel[1:0]
N=0..7, each field control the selection
of each bit of GPIO[7:0] to be used as
GPIO or SPI or FAN.
2’b00: GPIO => GPIO[7:0]
2’b01: SPI =>
Bit0: SPI_CLK
Bit1: SPI_FSS (could don’t care)
Bit2: SPI_MISO

Pin Information

# PD
Bit3: SPI_MOSI
Bit[4:7]: SPI_CS_B[0:3]
2’b10: FAN =>
l
Bit[0:3]: TACH[0:3] FANs’ status
ia
Bit[4:7]: PWM[0:3] control the FANs
GPIO[15:8] B LVCMOS
3.3V
0-50MHz 8 - General purpose IO
nt
SysGpioMultiCtl.cfgGpio[N]Sel[1:0]
e
N=8..15, each field control the selection
d
i
of each bit of GPIO[15:8] to be used as
f
GPIO or UART or FAN.
on
2’b00: GPIO => GPIO[15:8]
2’b01: UART2 =>
C
Bit10: UART2_DTR_N
c
Bit11: UART2_RTS_N
e
Bit12: UART2_CTS_N
nt Bit13: UART2_DSR_N
Bit14: UART2_DCD_N
e Bit15: UART2_RI_N
l C 2’b10: FAN =>

Bit[0:3]: PWM[0:3] control the FANs
ia
Bit[4:7]: TACH[0:3] FANs’ status
GPIOHS[17:0] B LVCMOS
nt
0~150MHz 18 - CFG_GPIO_SEL:
e
1.8V 0: used as DS-5 trace interface
d
Bit[0:15]: TRACE_DATA[0:15]
fi Bit16: TRACE_CLK
on Bit17: TRACE_CTL
1: used as general purpose IO and OobFC
C
SysGpioHsMultiCtl.cfgGpioHs[N]Sel[1:0]
N = 0..17, each field control the selection
ec of each bit of GIPIOHS[17:0].
t 2’b00: used as GPIO
en
2’b01: used as OobFC:
Bit0: FCIN_CLK
C
Bit[1:2]: FCIN_DATA[0:1]
Bit3: FCIN_SYNC
Bit4: FCOUT_CLK
Bit[5:6]: FCOUT_DATA[0:1]
Bit7: FCOUT_SYNC
MSH
MSH_CMD B LVCMOS 0-150MHz/0-50MHz 1 - Bidirectional Command channel used for
1.8V/ 3.3V command and response transfers.
MSH_CLK O LVCMOS 0-150MHz/0-50MHz 1 - Output MSH CLK, always valid

1.8V/3.3V While the MSH IO power supply is 1.8V,

Pin Information

# PD
the CLK frequency could be 0-150MHz,
otherwise the CLK frequency is 0-50MHz.
MSH_DATA[7:0] B LVCMOS 0-150MHz/0-50MHz 8 - Bidirectional data signals.
l
1.8V/3.3V
i a
MSH_RST_B O LVCMOS 0-150MHz/0-50MHz 1 - Reset the device and make the device to
1.8V/3.3V
for eMMC device.
n t
the pre-idle state. Active low. Only used
SD_DET_B I LVCMOS 0-50MHz 1 - pull down with 1K ohm..
d e
fi
SD_WP I LVCMOS 0-50MHz 1 - pull down with 1K ohm.
on
SD_SW_VOLT_EN - - - - Reserved
QSPI
QSPI_CLK O LVCMOS 25MHz 1 -
C
QSPI output clock
c
QSPI_CS[1:0] O LVCMOS Static 2 - Chip Selection signal of QSPI interface
QSPI_DATA[3:0] B LVCMOS 50MHz 4 -
t e
QSPI bidirectional data
n
UART Interface
UART_TXD[2:0] O LVCMOS 5MHz 3
e
- Tx Data of UART interface
UART_RXD[2:0] I LVCMOS 5MHz
l C3
DDR SDRAM Interface
PD Rx Data of UART interface
DDR_CLK_P[1:0] O SSTL DDR3: 800MHz
tia 4
- Differential clock output
n
DDR_CLK_N[1:0] DDR4: 800MHz
DDR_CKE[3:0] O SSTL See above
e 4 - Clock enable, active high
fid
O SSTL See above - Chip select, Active low.
n
Ensure each group signals are connected
correctly. (For example,
o ODT0/CKE0/CS0)
C
DDR_CS_B[3:0] 4
If only use one chip select pin, it must
c
use DDR_CS_B0/ ODT0/ CKE0.
e
And use two chip select pin, it must use
DDR_ODT[3:0]
n t O SSTL See above 4 -
DDR_CS_B0/B1.
On-die termination
e O SSTL See above - Address output
C
DDR_ADDR[15:0] 16
DDR_ADDR[14] is used as DDR_ACT_B of
DDR4;
DDR_ADDR[15] is used as DDR_BG[1] of
DDR4.
O SSTL See above - Bank address output
DDR_BA[2:0] 3
DDR_BA[2] is used as DDR_BG[0] of DDR4.
O SSTL See above - RAS command, active low
DDR_RAS_B 1 Used as DDR4 DDR_ADDR[16] when
DDR_ACT_B is low
DDR_CAS_B O SSTL See above 1 - CAS command, active low

Pin Information

# PD
Used as DDR4 DDR_ADDR[15] when
DDR_ACT_B is low
O SSTL See above - WE command, active low
l
DDR_WE_B 1 Used as DDR4 DDR_ADDR[14] when
a
DDR_ACT_B is low
DDR_RST_B O SSTL See above 1 - Reset device, active low
t i
DDR_DQ[23:0]
B SSTL See above
24
- DQ[15:0] used for pure data
e n
DQ[23:16] used for ECC, can NOT be used
B SSTL See above - Data strobe

fi d
for data even ECC is disabled.
on
DDR_DQS_P[2:0] Bit2: used for DDR_DQ[23:16]
6
DDR_DQS_N[2:0] Bit1: used for DDR_DQ[15:8]
C
Bit0: used for DDR_DQ[7:0]
O SSTL See above -
c
Data mask
e
t
DDR_DM[2:0] 3
n
e Bit0: used for DDR_DQ[7:0]
lC
B SSTL See above - Calibration resistor for PVT compensation
DDR_ZQ 1 Should connect to external resistor 240
ia
ohm (+/-1%)
DDR_PAR O SSTL See above
n t 1 - DDR4 command and address parity check
e
O SSTL See above - DDR4 SDRAM connectivity test mode
DDR_TEN 1
enable
B SSTL
fi d
See above - DDR4 SDRAM used only:
n
Input pin: DDR4 used for CRC and
o
DDR_ALERT_B 1 command/ address parity check. Active
low.
C Ouput pin: connectivity test
DDR_VREF0
e c I PWR -
1
- Used for ATE IO DC test.
t
Keep floating when application.
DDR_VREF1
e n I PWR -
1
- Used for ATE IO DC test.
Keep floating when application.
USB_D_P C B Analog 480Mbps

USB
1 - USB D+ signal
In HS operation, this pin
receives/transmits a maximum of 800 mV
or 400 mV nominally. In FS or LS
operation, this pin receives/transmits
3.3V nominally.
USB_D_M B Analog 480Mbps 1 - USB D- signal
USB_VBUS0 B Analog - 1 - OTG function not supported. Leave this
pin floating.

Pin Information

# PD
USB_ID0 B Analog - 1 - Used to differentiate b/w a mini-A and
mini-B plug.
USB_ID0 also could be used for analog
test signal through internal configuration
USB_TXR_TUNE B Analog - 1 - Transmitter resistor tune pin
a l
t
Connect to 200 ohm (+/-1%) resistor
i
USB_OVC_B I LVCMOS Static 1 PU
n
USB interface over current indication.
Active low.
e
BOOT_USB_VREG_BY
P
I LVCMOS - 1 PD
fi d
0： MSH internal logic uses clock
on
generated from MSH_CLK
1: MSH internal logic uses internal clock.
It is recommended to implement
C
compatible design, and the default is
c
pull-down.
CPU_SGMII
t e
n
HS_CMU_REFCLK_P/N I LVDS 156.25MHz 2 - Reference clock input, typical 156.25MHz
HS_TX_P[1:0] O CML, 3.125Gbps 4
e
- Differential Tx Data
C
HS_TX_N[1:0] 1.0V 1.25Gbps ~ 3.125Gbps
HS_RX_P[1:0] I CML, 3.125Gbps
a l 4 - Differential Rx Data
i
HS_RX_N[1:0] 1.0V 1.25Gbps ~ 3.125Gbps
HS_CMU_REXT10K O LVCMOS static
n t 1 - Reserve Pin
de
Should connect to via or keep floating.
i
SOC I2C Interface
SCL_SOC[1:0] B OD
n f
0~400KHz 2 - SCL_SOC[1] is only for internal CPU.
SCL_SOC[0] is duplexed pin which can be
o used for Internal CPU or switch core for
C data transfer by I2C interface.
c
SDA_SOC[1:0] B OD 0~400KHz 2 - SDA_SOC[1] is only for internal CPU.
e
SDA_SOC[0] is duplexed pin which can be
n t used for Internal CPU or switch core for

data transfer by I2C interface.
e SOC SMI Interface

MDC_SOC
MDIO_SOC
C O LVCMOS
B LVCMOS
0~25MHz
0~25MHz
1
1
-
-
CPU Subsystem 1G PHY MDIO clock
CPU Subsystem 1G PHY MDIO data
Watchdog Interface
WDT0_RST_B O LVCMOS - 1 Reset Watchdog. Active low.
WDT1_RST_B O LVCMOS - 1 Reset Watchdog. Active low.
CORE reference clock
CORE_REFCLK_P I LVDS 50MHz 2 - Differential input reference clock for
CORE_REFCLK_N Core PLL, typical 50MHz

Pin Information

# PD
I2C Master Interface
MSCL[0:1] O OD 400KHz 2 I2C Master SCL out, up to 400KHz,
default is 100KHz
MSDA[0:1] B OD 400KHz 2
al
I2C Master SDA, related with MSCL0~1.
i
SMI Interface
MDC_A[1:0] O LVCMOS 0-25MHz 2 -
nt
External PHY MDIO clock, compatible
e
1.2V/3.3V with 1G/10G PHY
id
MDIO_A[1:0] B LVCMOS 0-25MHz 2 - External PHY MDIO data, compatible with
1.2V/3.3V 1G/10G PHY
f
on
MDC_B[1:0] O LVCMOS 0-25MHz 2 - External PHY MDIO clock, compatible
1.2V/3.3V with 1G/10G PHY
MDIO_B[1:0] B LVCMOS 0-25MHz 2 -

C
External PHY MDIO data, compatible with
1.2V/3.3V
ec 1G/10G PHY
t
Synchronous Ethernet Interface
RECV_CLK[0:2] O LVCMOS
1.8V/3.3V
0-150MHz
en 3 Synchronous Ethernet recovery clock, the

typical frequencies refer to chapter 10.2.
C
1.25G~10.3125Gbps: 1.953125MHz
l
ia
LED Interface
LED_CLK O LVCMOS
nt
25MHz 1 Led clock out.
e
LED_DATA O LVCMOS 25MHz 1 Led data out.
fid Thermal Interface
on
THM_VINS0 I analog - 1 Used for THM INL/DNL testing, floating in
function mode.
THM_VREFP I analog - 1 Used for trimming, floating in function
C mode.
ec MISC Interface
FUSE_DONE
t O LVCMOS - 1 If assert, indicate the fuse download
en
procedure is finished.
FUSE_FAIL O LVCMOS - 1 If assert, it indicates that the fuse
C
download procedure is failed.
DEBUG[7:0] O LVCMOS 0- 150MHz 8 Used for chip function debugging;
1.8V Connect to debug tap on board.
DEBUG_MODE[2:0] I LVCMOS - 3 PD Debug mode selection;
1.8V Connect to debug tap on board;
The internal pull-down resistor ranges
from 61K kΩ to 196 kΩ (typical value is
104K kΩ)
IEEE1588 Time Stamp Interface
PTP_REFCLK_P I LVDS 125M/250MHz 2 - IEEE1588 Time stamp Engine Differential

Pin Information

# PD
PTP_REFCLK_N clock input, maximum frequency is
250MHz.
TOD_REFCLK I LVCMOS 96MHz 1 - Time of Date interface reference clock
l
1.8V input, typical 96MHz
i a
TOD_CODE B LVCMOS 0-25MHz 1 PU Obey the CMCC High Precision Time Sync
Spec Ver1.0, typical baud rate is
n t
9600bps, indicate the Time of Date.
TOD_PULSE B LVCMOS 0-25MHz 1 PD Typical 1pps assertion.
d e
fi
SYNC_CLK B LVCMOS 0-25MHz 1 PD TsEngine sync clock, up to 25MHz.
on
SYNC_PULSE B LVCMOS 0-25MHz 1 PD TsEngine sync pulse.
SYNC_CODE B LVCMOS 0-25MHz 1 PD TsEngine sync code.
Interrupt Interface
C
c
INTR_B[3:0] O LVCMOS - 4 Interrupt output signals. Active low.
JTAG Interface
t e
n
TCK I LVCMOS 25MHz 1 PU JTAG Clock input.
TRST_B I LVCMOS 25MHz 1
e
PD JTAG Test Reset. This signal is active
lC
low.
TMS I LVCMOS 25MHz 1 PU JTAG Test Mode Select input.
tia
TDI I LVCMOS 25MHz 1 PU JTAG Data input.
n
TDO O LVCMOS 25MHz 1 - JTAG Data output.
e
f id
Table 8-2 : Pin information –Power and Ground
Pin Name
o
Type n Rate Pin # Description
C Power
c
VDD I 0.9V Core Power VDD core power supply (0.9V typ)
VDD_RSV
t e I 0.9V Core Power Reserved power PIN, recommend to refer to
n
demo board design
e
I 3.3V or MDIO_A IO MDIO_A IO power supply (3.3V or 1.2V typ)
VDDIO3312_MDIO_A
1.2V Power
C
VDDOUT_MDIO_A
O Power Filter MDIO_A Power Filter, connect to 1.0uF
capacitor
I 3.3V or MDIO_B IO MDIO_B IO power supply (3.3V or 1.2V typ)
VDDIO3312_MDIO_B
1.2V Power
O Power Filter MDIO_B Power Filter, connect to 1.0uF
VDDOUT_MDIO_B
capacitor
VDDIO33 I 3.3V 3.3V IO power 3.3V IO power supply (3.3V typ)
O Power Filter 3.3V IO power filter, connect to 1.0uF
VDDOUT_G{1..5}
capacitor

Pin Information

I 3.3V or GPIO{0..7} GPIO{0..7} 3.3V power supply (3.3V typ)
VDDIO3318_GPIO_7_0
1.8V Power
O Power Filter GPIO{0..7} power filter, connect to 1.0uF
VDDOUT_GPIO_7_0
capacitor
l
I 3.3V or RECV Power Recovery clocks IO 3.3V power supply (3.3V
VDDIO3318_RECV
a
1.8V typ)
O Power Filter
ti
Recovery clocks IO power filter, connect to
n
VDDOUT_RECV
1.0uF capacitor
I 3.3V or MSH Power
e
eMMC IO 3.3V power supply (3.3V typ)
id
VDDIO3318_MSH
1.8V
O Power Filter
f
eMMC IO power filter, connect to 1.0uF
on
VDDOUT_MSH
capacitor
AVDD18_THM I 1.8V Analog Power 1 Thermal analog power supply (1.8V typ)
I 1.8V Analog Power
C
Analog power 1.8V for the PLL for DDR PHY
c
AVDD18_DDRPLL 1
(1.8v typ), corresponding GND is AVSS_DDRPLL
VDD09_DDRPLL
I 0.9v
te
Analog Power
1
Digital power 0.9V for the PLL for DDR PHY
n
(0.9v typ), corresponding GND is VSS_DDRPLL
I 1.8v
e
Analog Power Analog power 1.8V for the PLLs of
C
AVDD18_PLL 1 Core/Sup/SoC (1.8v typ), corresponding GND
l
is AVSS_PLL
ia
VDDIO18 I 1.8v 1.8V IO Power Digital Power supply for 1.8V IO (1.8v typ)
AVDD18_PCIE
I 1.8v
nt Analog Power Analog Power 1.8V for PCIe PHY,

corresponding GND is AVSS_PCIE
I 0.9v
de Analog Power Analog Power 0.9V for PCIe PHY,
i
AVDD09_PCIE
f
on
I 0.9v Analog Power Analog Power 0.9V for PCIe PHY VCO,
AVDD09_VCO_PCIE
C
AVDD09_HS0 I 0.9v Analog Power Analog Power 0.9V for 8x Lanes HSS SerDes
AVDD09_HS1 hard macro (0.9v typ)
AVDD09_HS2
ec
t
AVDD09_VCO_HS0 I 0.9v Analog Power Analog Power 0.9V for 8x Lanes HSS SerDes
en
AVDD09_VCO_HS1 VCO (0.9v typ)
AVDD09_VCO_HS2
AVDD18_HS0
AVDD18_HS1
AVDD18_HS2
C I 1.8v Analog Power Analog Power 1.8V for 8x Lanes HSS SerDes
hard macro (1.8v typ)
I 0.9v Analog Power Analog Power 0.9V for SoC 2x Lanes HSS SerDes
AVDD09_HS3
AVDD09_VCO_HS3
VCO (0.9v typ)
AVDD18_HS3
AVDD18_RSV I 1.8v Analog Power Reserved power PIN, recommend to refer to

Pin Information

demo board design
I 1.8v Analog Power Analog Power 1.8V for DDR PHY address (1.8v
AVDD18_ADD_DDR
typ), corresponding GND is AVSS18_ADD_DDR
I 1.8v Analog Power Analog Power 1.8V for DDR PHY MSB 8bit Data
l
AVDD18_DATA_H8_DDR (1.8V typ), corresponding GND is
a
AVSS18_DATA_H8_DDR
I 1.8v Analog Power
t i
Analog Power 1.8V for DDR PHY LSB 16bit Data
n
AVDD18_DATA_L16_DDR (1.8V typ), corresponding GND is
e
AVSS18_DATA_L16_DDR
I 1.2v or
1.35v or
Power
fi d
Digital power supply for DDR IO
- 1.2V DDR4
on
VDDIO_DDR
1.5v - 1.35V DDR3L
- 1.5V DDR3
I 1.2v or Power
C
Digital power supply for DDR Clock IO
c
1.35v or - 1.2V DDR4
VDDIO_DDR_CK
1.5v
e
- 1.35V DDR3L
t
n
- 1.5V DDR3
e
VDD_USB I 0.9v Power Digital Power supply for USB PHY
lC
AVDD33_USB I 3.3v Analog Power Analog Power supply for USB PHY (3.3v typ)
AVDD18_LVDS I 1.8v Analog Power Analog Power supply for LVDS IO (1.8v typ)
tia
I 1.8v Power Digital power supply for 32x32b customized
eFUSE.
n
VDDIO18_EFUSE_INFO
MUST connect to GND through resistor(1kΩ ) in
e function mode.
fid
I 1.8v Power Digital power supply for 128x32b memory
n
eFUSE.
VDDIO18_EFUSE_MEM
o
MUST connect to GND through resistor(1kΩ ) in
function mode.
C GROUND
VSS
e c I GND Digital ground

AVSS_DDRPLL
VSS_DDRPLL
n t I
I
GND
GND
Analog ground for AVDD18_DDRPLL
Ground for VDD09_DDRPLL
AVSS_PLL
e I GND 3 Analog ground for AVDD18_PLL
AVSS_PCIE
C
AVSS18_ADD_DDR
I
I
GND
GND
Analog ground for PCIe PHY
Analog ground for AVDD18_ADD_DDR
AVSS18_DATA_H8_DDR I GND Analog ground for AVDD18_DATA_H8_DDR
AVSS18_ADD_L16_DDR I GND Analog ground for AVDD18_DATA_L16_DDR

Electrical Specifications
9 Electrical Specifications
i a l
9.1 Absolute Maximum Rating n t
d e
fi
on
Stress above the specification listed in Table 9-1 may cause permanent damage to the device.
C
Function operation is not guaranteed under or above these conditions. Exposure to absolute
maximum ratings for extended periods may affect device reliability.
e c
Table 9-1 : Maximum Ratings
n t
Symbol Parameter
e Min Max Unit
lC
VDD[1] Core digital 0.9V power Supply -0.18 1.08 V
ia
VDD09_DDRPLL Digital 0.9V power supply for the PLL for -0.18 1.08 V
AVDD09*
DDR PHY
n t
Analog 0.9V Power Supply -0.18 1.08 V
de
AVDD18* Analog 1.8V Power Supply -0.36 1.98 V
VDDIO18*
VDDIO33*
n fi
Digital 1.8V Power Supply
Digital Power Supply for 3.3V IO
-0.36
-0.5
1.98
3.80
V
V
VDDIO3312*
oDigital Power Supply for 3.3V/1.2V -0.5 3.80 V
C compatible IO 1.38
VDDIO3318*
e c Digital Power Supply for 3.3V/1.8V -0.5 3.80 V
t
compatible IO 1.98
VDDIO_DDR*
e n Digital IO Power Supply for DDR IO

- 1.2V (DDR4)
-0.5 1.38
1.5525
V
C
- 1.35V (DDR3L) 1.725
- 1.5V (DDR3)
VDV/DT[2] Supply Voltage Slew Rate - 18 V/ms
TST Storage Temperature -40 125 °C
HBM JS-001-2014 JEP-155 - 1000 V
CDM JS-002-2014 JEP-157 - 250 V
Note[1]: Limited by 12G LVDS RX Digital VDD absolute maximum ratings.

Note[2]: Limited by 1.8V GPIO

9.2 Recommended Operating Conditions

Recommended operating conditions are values that guarantee correct device operation. As long
as the device is used within the ranges, electrical characteristics (DC and AC characteristics)
are guaranteed.
Table 9-2 : Recommended Operating Conditions
a l
Symbol Parameter Min Typ Max Toleranc
t i
Unit
e (use
e
for Typ)n
fi d
(AC+DC
)
on
VDD[1] Core digital 0.9V power Supply 0.873 0.900 0.927 ±3% V
VDD09_DDRPLL Digital 0.9V power supply for 0.873 0.900 0.927 ±3% V
the PLL for DDR PHY
C
AVDD09* Analog 0.9V Power Supply 0.873
c
0.900
e
0.927 ±3% V
AVDD18*
VDDIO18*
Analog 1.8V Power Supply
Digital 1.8V Power Supply
1.710
1.710
n t 1.800
1.800
1.890
1.890
±5%
±5%
V
V
VDDIO33* Digital Power Supply for 3.3V 3.135
e 3.300 3.465 ±5% V
VDDIO3312*
IO
Digital Power Supply for
l C 3.135 3.300 3.465 ±5% V
3.3V/1.2V compatible IO
t i a 1.140 1.200 1.260
n
VDDIO3318* Digital Power Supply for 3.135 3.300 3.465 ±5% V
e
3.3V/1.8V compatible IO 1.62 1.80 1.98
VDDIO_DDR*
fi d
Digital IO Power Supply for DDR
IO
1.140
1.283
1.200
1.350
1.260
1.417
±5% V
o n
- 1.2V (DDR4)
- 1.35V (DDR3L)
1.425 1.500 1.575
C - 1.5V (DDR3)
c
[2]
Tj Junction Temperature 0 110 °C
Ta
t e Ambient operating
-10 70 °C
n
temperature range
e
C
Note*: All voltages are probed from package BGA BALL.
Note[1]: VDD tolerance ±3%, AC ripple MUST be less than 20mVpp from DC to 100MHz (Limited by PCIe
PHY).
Note[2]: Operation condition of Tj is limited by PCIe PHY
Consider the minimum number of voltage supply number and the minimum power consumption
of CTC5118, the recommended power supply as the following table: Table 9-3
Table 9-3 : Recommended Power Supply

Power Type/Power Module Voltage (Typical) Tolerance (Minimum) Unit
(AC+DC)

VDD 0.900 ±3% V

VDD09_DDRPLL 0.900 ±3% V
AVDD09*
AVDD18* 1.800 ±5% V
VDDIO18*
l
VDDIO3318* (1.8V mode)
VDDIO33*
3.300 ±5% V
t i a
n
de
VDDIO3312* (1.2V mode) 1.200 ±5% V
VDDIO_DDR* (DDR4 mode) [1]
f i
Note[1]: DDR IO could use 1.5V for DDR3 or 1.35V for DDR3L.
o n
C
9.3 Power-Up and Power-Down Specifications
e c
n t
e
Table 9-4 : Power Up and Power Off Timing Parameters
tDELAY1
Symbol
l C
Description
0.9V power up to 1.2V/1.35V/1.5V power up delay 200
Min
-
Max Units
us
t i a
1.2V/1.35V/1.5V power off to 0.9V power off
n
tDELAY2 1.2V/1.35V/1.5V power up to 1.8V power up delay 200 - us
de
1.8V power off to 1.2V/1.35V/1.5V power off
i
tDELAY3 1.8V power up to 3.3V power up delay 20 - us
f
3.3V power off to 1.8V power off
n
o
tSLEW Power Ramp Up Slew 200 10000 us
C
Zpwr Power supply Impedance (DC ~ 100MHz) - 40 mOhm
e c
n t tDELAY1
e 0.9V
C tDELAY1 tDELAY2
1.2/1.35/1.5V
tDELAY2 tDELAY3
1.8V
tDELAY3
3.3V
The detailed information about Boot Up/Reset Sequence, please refer to

CTC5118_Advanced_Hardware_Design_Guide.

9.4 Boot Up/Reset Sequence
The detailed information about Boot Up/Reset Sequence, please refer to

CTC5118_Advanced_Hardware_Design_Guide.
9.5 Power Supply and Power Consumption

a l
t i
The following power consumptions based on different bandwidth (i.e different core frequency
and configuration mode) are estimated.
e n
Table 9-5 : Maximum Power Consumption Estimation
fi d
Mode I/O Junction VDD *AVDD18
on
*AVDD09 Max
C
Bandwidth Temp (°C) (V) (V) (V) (Watts)
ec
18x10G 180Gbps 110 0.927 1.890 0.927 24
nt
48 x 1G + 6 x 10G 108Gbps 110 0.927 1.890 0.927 20
8 x 1G 8Gbps 110 0.927 1.890 0.927 14.5
e
l C
The maximum power consumption estimation includes the CPU’s.
t
Table 9-6 : Typical Power Consumption Estimation
i a
Mode I/O
n Junction VDD *AVDD1 *AVDD09 Typical
de
Bandwidth Temp (°C) (V) 8 (V) (V) (Watts)
fi
18x10G 180Gbps 60 0.900 1.800 0.900 19
48 x 1G + 6 x 10G
8 x 1G
o n
108Gbps
8Gbps
60
60
0.900
0.927
1.800
1.890
0.900
0.927
15
11
C
e c
The typical power consumption estimation includes the CPU’s.
n t
For PSU and thermal designing, the following power requirement for different voltage rails are
e
provided based on 18x10GE, total 180Gbps, other configuration mode could use different
C
number proportionally.
The power requirements of different voltage rails for 180Gbps are listed in the following table.
Table 9-7 : Power Requirement for Different Voltage Jc=110 °C (Estimation)

Power Type Voltage Tolerance Watts Current Percentage
(Min) (Max) (Max) (Subtotal/
(AC+DC) Unit: A Total Pwr)
VDD 0.900 ±3% 17.31 19.24 72.12%

Power Type Voltage Tolerance Watts Current Percentage

(Min) (Max) (Max) (Subtotal/
(AC+DC) Unit: A Total Pwr)
AVDD09* 0.900 ±3% 3.204 3.56 13.35%
AVDD18* 1.800 ±5% 2.34 1.3 9.75%
a l
AVDD33_USB/ 3.300 ±5% 0.584 0.18 2.43%
t i
n
VDDIO33*
VDDIO_DDR*[1] 1.500 or ±5% 0.675 or 0.45 or
d e
1.75%
fi
1.2 or 0.42 or 0.35 or
1.35 or 0.513 0.38
on
VDDIO3312* 1.200 ±5% 0.144 0.12 0.6%
C
Note1: VDDIO_DDR* use 1.20V (DDR4) or 1.35V (DDR3L) or 1.50V (DDR3)
e c
9.6 Interface I/O DC Specifications
n t
e
9.6.1 3.3V General I/O Specifications
l C
i
These specifications apply to 3.3V LVCMOS I/O signals.
t a
n
Table 9-8 : 3.3V LVCMOS driver/receiver dc specification
VIL
Symbol
DC Input Logic Low
f i
Parameter
de Min
-0.300 -
Typ.
0.825
Max
V
Units
VIH
o n
DC Input Logic High 2.063 - 3.6 V
VOL
C
DC Output Logic Low - - 0.413 V
VOH
e c
DC Output Logic High 2.475 - - V
t
IOZ Tristate Output Leakage Current ±10 uA
II
IOL
e nInput Leakage Current
Low Level Output Current @VOL (max) 6.8 13.2

±10
23.9
uA
mA
IOH
Freq.
C High Level Output Current @VOH (min)
IO frequency
10.9 18.9 33.5
50.0
mA
MHz
9.6.2 1.8V General I/O Specifications

These specifications apply to 1.8V LVCMOS I/O signals.
Table 9-9 : 1.8V LVCMOS driver/receiver dc specification

Symbol Parameter Min Typ Max Units

Symbol Parameter Min Typ Max Units

VIL DC Input Logic Low -0.30 - 0.63 V
VIH DC Input Logic High 1.17 - 1.98 V
VOL DC Output Logic Low - - 0.45 V
l
VOH DC Output Logic High 1.35 - - V
IOZ Tristate Output Leakage Current ±10 uA
t ia
n
II Input Leakage Current ±10 uA
IOL Low Level Output Current @VOL (max) 11.1 18.2 25.6
d e mA
fi
IOH High Level Output Current @VOH (min) 13.1 19.1 26.3 mA
on
Freq. IO frequency 150.0 MHz
CI Capacitance Pad to GND 1.18 pF
C
9.6.3 3.3V I2C I/O Specifications
e c
These specifications apply to 3.3V I2C I/O signals.
n t
Table 9-10 : 3.3V I2C I/O dc specification
e
lC
Symbol Parameter Min Typ. Max Unit Comments
tia
s
VIL DC Input Logic Low -0.500 0 0.800 V
VIH DC Input Logic High
e n 2.195 3.30
0
3.6 V
fid
VOL DC Output Logic Low 0 - 0.4 V @IOL =3mA
IOZ
@Vo=3.3V or 0V
o n
Tristate Output Leakage Current -10 10 uA @VO= 3.3V or 0V
II
C
Input Leakage Current -10 10 uA 0V < VI < 3.465V
c
0V < VI < 3.465V
e
Freq.
CI
n t
IO frequency
Capacitance of each I/O pin (Pad to

400K
10
Hz
pF
e GND)
C
9.6.4 1.2V/3.3V MDIO I/O Specifications
These specifications apply to 1.2V/3.3V MDIO I/O signals
Table 9-11 : 1.2V/3.3V MDIO DC specification (VDDIO = 1.2V)

Symbol Parameter Min Typ. Max Units Comments
VIL DC Input Logic Low - - 0.52 V


VIH DC Input Logic High 0.77 - - V
VOL DC Output Logic Low - - 0.20 V
IOL Low Level Output Current @VOL (max) 4.0 - 6.7 mA
a l
IOH High Level Output Current @VOH (min) 4.0 - 7.2 mA
t i
Freq. Operating Frequency 25 MHz
e n
fi d
on
Note: 1.2V/3.3V MDIO DC spec is the same as 3.3V only IO while VDDIO=3.3V
9.6.5 1.8V/3.3V eMMC I/O Specifications

These specifications apply to 1.8V/3.3V eMMC I/O signals C
e c
Table 9-12 : 1.8V/3.3V eMMC specification (VDDIO = 1.8V)
n t
e
C
VIL DC Input Logic Low -0.30 - 0.58 V
VIH DC Input Logic High
a l 1.27 - 1.98 V
VOL DC Output Logic Low
n ti - - 0.45 V
e
id
IOL Low Level Output Current @VOL (max) 6.7 11.4 16.7 mA
IOH
n f
High Level Output Current @VOH (min) 3.8 9.4 17.7 mA
Freq.
o
Operating Frequency (VDDIO = 1.8V) 150 MHz
C
e c
Note: 1.8V/3.3V MDIO DC spec is the same as 3.3V only IO while VDDIO=3.3V
n t
e
9.6.6 LVDS I/O Specifications
C
Table 9-13 : LVDS I/O receiver dc specification
Symbol Parameter Min Typ. Max Units
NVDD1 Analog Supply Voltage 1.62 1.80 1.98 V
Idda Analog Supply Current - 5 - mA
Iddd Digital Supply Current - 1 - mA
Rterm RX internal termination resistance 50 100 Ohm
VI RX input range 0 NVDD1 V


Vt RX input differential threshold -200 - +200 mV
Freq Data rate - - 500 Mbps
9.6.7 DDR3/4 I/O Specifications

a l
t i
Table 9-14 : DDR3/4 I/O dc specification
n
de
fi
VDDIO_DDR DDR3 IO post-driver power 1.425 1.5 1.575 V
on
VDDIO_DDR_CK DDR4 IO post-driver power 1.14 1.2 1.26 V
AVDD18_*_DDR 1.8V analog Power 1.71 1.80 1.89 V
C
9.6.8 HSS SerDes Electrical Specifications
e c
n t
Unless otherwise specified, the following characteristics are met while operating within the
e
Normal Range of Operating condition. These specifications apply at the module BGA ball.
Table 9-15 : HSS SerDes Absolute Maximum Ratings

l C
Parameter
ti a
Description Max Unit
VINPUT
e n
Digital Input signal Voltage Level 1.1 V
id
VOUTPUT Digital Output signal Voltage Level 1.1 V
n f
o
C
e c
n t
e
C

AC Timing
10 AC Timing
i a l
10.1 Clock Source Supply n t
d e
fi
The table lists the requirement of the reference clock.
on
Table 10-1 Characteristics of the SerDes interfaces reference clock
C
Seq# PIN Name TYPE Description Requirement
c
1 HS_S0/1/2_REFCLK_P/N I LVDS 10.3125G Serdes  Freq：156.25MHz±50ppm
e
macro#0/1/2 reference  Duty cycle：40~60%
clock
n t
 jitter: 1.0ps rms[2]
e
 Rise/Fall rate(20%~80%):
 1V/ns~4V/ns
lC
 Input voltage: 400~1600mV
tia
2 HSS_REFCLK_P/N[1] I LVDS External Reference  Freq：156.25MHz±50ppm
clock to generate sup  Duty cycle：45~55%
n
clock for super control
e
logic. HSS_REFCLK is
necessary for chip boot
 Rise/Fall time (20~80%): 0.1ns~0.75ns
fid
up.  Input voltage: 350~1200mV
n
3 HS_CMU_REFCLK_P/N I LVDS CPUMAC SGMII  Freq：156.25MHz±50ppm
o
reference clock  Duty cycle：40~60%
C
Rise/Fall rate(20~80%):
c

e
 1V/ns~4V/ns
4
n t
CORE_CLK_P/N I LVDS CORE reference clcok
Freq：50MHz±50ppm
e

 Duty cycle：40~60%
C 

jitter: 2.0ps rms[3]
Rise/Fall time (20~80%): 0.25ns~0.75ns
5 PCIe_REFCLK_P/N I HCSL PCIe reference clcok  Freq：100MHz±100ppm
 Refer to PCIe2.0 Standard
 Jitter: See Note[4]
6 PTP_CLK_P/N I LVDS PTP reference clock  Freq：125/250MHz±4.6ppm
 Duty cycle：40~60%
 Jitter: ±100ps(c2c) [5]

AC Timing
Seq# PIN Name TYPE Description Requirement

 Rise/Fall time (20~80%): 0.1ns~0.75ns
7 TOD_REFCLK I 1.8V TOD reference clock  Freq：96MHz±100ppm

CMOS  Duty cycle：40~60%
 Jitter: ±200ps(c2c)
a l
i
t

n
8 FCIN_CLK I 1.8V External FlowControl  Freq：125MHz±100ppm
e
CMOS reference clock  Duty cycle：40~60%


Jitter: ±200ps(c2c)
fi d
on
C
c
Note[1]: Random Jitter 50KHz ~10MHz
e
Note[2]: PLL external input reference clock jitter is long term RMS jitter from 10kHz to Fref/10 < 2ps, the
t
value of Fref=50MHz.
Note[4]: Frequency tolerance is ±4.6ppm.

e n
Note[3]: PCIe 100MHz reference clock requirements refer to the PCIe SIG spec.
l
Table 10-2 : HSS SerDes External Reference Clock Requirements
C
Symbol Parameter
t i a Conditions Min Typ. Max Units
n
TC-RISE Rising edge rate Differential 1.0 - 4.0 V/ns
de
TC-FALL Falling edge rate Differential 1.0 - 4.0 V/ns
i
VDIFF Differential Input Swing Differential 400 - 1600 mV
VRB
n f
Ring Back Voltage Margin Differential -50 - +50 mV
o
TSTABLE Time Before VRB is allowed Differential 500 ps
C
TPERIOD-AVG Average Clock Period Accuracy Differential -100 - +100 ppm
c
156.25 or
FREF Reference Clock Freq. MHz
e
61.13
DUTY
n t Duty Cycle Differential 40 60 ohm
e
ps
RJ Random Jitter 50KHz ~10MHz 1.0
rms
C
Table 10-3 : PCIe Reference Clock Jitter and Swing Requirement
Application Reference Clock Jitter and Swing Requirement
PCIe 2.5 Gbps For requirements, refer to the PCI Express 1.0 Card Electrometrical specification
PCIe 5.0 Gbps For requirements, refer to the PCI Express 2.0 base specification

AC Timing
10.2 Recovery Clock Output

Table 10-4 : SerDes Recovery Clock Output Frequency
Data Rate Baud Rate Enc/Dec Recovery clock Divider Output Clock
l
(Gbps) (Gbps) Frequency (MHz) Frequency (MHz)
a
1 1.25 8b/10b 125 64 1.953125
2.5 3.125 8b/10b 312.5 160 1.953125
t i
10 10.3125 64b/66b 322.265625 165 1.953125
e n
fi d
10.3 I2C Interface Timing Parameter
on
C
c
Table 10-5 : Characteristics of the SDA and SCL for S-mode, from THE I 2C-BUS SPECIFICATION
e
PARAMETER SYMBOL
MIN．
n t
STANDARD-MODE
MAX. MIN．
FAST-MODE
MAX.
Units
SCL Clock frequency fSCL 0

e 100 0 400 kHz
Hold time(repeated) START condition.
l C
a
After this period, the first clock pulse is tHD,STA 4.0 — 0.6 — µs
generated
t i
LOW period of SCL clock
HIGH period of the SCL clock
e
tLOW
tHIGHn 4.7
4.0
—
—
1.3
0.6
—
—
µs
µs
Set-up time for a repeated START
condition
fi d tSU,STA 4.7 — 0.6 — µs
Data hold time:

for CBUS compatible masters
o n tHD,DAT
5.0 — — —
µs
for I2C-bus devices
C 0 3.45 0 0.9
Data set-up time
e c tSU,DAT 250 — 100 — µs
n t
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
tr
tf
—
—
1000
300
20+0.1Cb
20+0.2Cb
300
300
ns
ns
e
Set-up time for STOP condition tSU,STO 4.0 — 0.6 — µs
C
Bus free time between a STOP and
START condition
tBUF 4.7 — 1.3 — µs
Capacitive load for each bus line Cb — 400 — 400 pF

Noise margin at the LOW level for each
VnL 0.1VDD — 0.1VDD — V
connected device (including hysteresis)
Noise margin at the High level for each
VnH 0.2VDD — 0.2VDD — V
connected device (including hysteresis)

AC Timing
a l
t i
e n
Figure 10-1 : Definition of timing of I2C
fi d
10.4 MDC/MDIO Interface Timing
on
C
c
Table 10-6 : MDC/MDIO Interface Timing Parameters
Symbol Signals Description
t e Min Max Units

FMDC
DCMDC
MDC_*
MDC_*
MDC clock frequency
MDC clock duty cycle
e n -
40
25
60
MHz
%
lC
TSU MDIO_* MDIO input Setup time 10 - nS
tia
THD MDIO_* MDIO input Hold time 0 - nS
TOSU MDIO_* MDIO output Setup time 10 - nS
TOH MDIO_*
e n
MDIO output Hold time 10 - nS
f id
n
MDC/MDIO INTERFACE TIMING WAVEFORM OF INPUT
o
FMDC
C
MDC
e c TSU THD
t
MDIO
e n
C
Figure 10-2 : MDC/MDIO Input Timing Diagram
MDC
Tosu Toh
MDIO

AC Timing
Figure 10-3 : MDC/MDIO Output Timing Diagram
10.5 OOBFC Interface Timing Parameter

Table 10-7 : OOBFC Interface Timing Parameters
a l
Symbol Signals Description Relative to Min Max
t i
Units
Clock
n
de
F FCIN_CLK Flow control clocks N/A - 125 MHz
FCOUT_CLK
f i
DC FCIN_CLK
FCOUT_CLK
Flow clock duty cycle N/A 40
o n 60 %
TSU FCIN_DATA Setup time FCIN_CLK

C 1 - nS
ec
FCIN_SYNC
THD FCIN_DATA Hold time FCIN_CLK 1 - nS
FCIN_SYNC
n t
e
TOSU FCOUT_DATA Flow control output setup FCOUT_CLK 1 - nS
time
lC
FCOUT_SYNC
TOH FCOUT_DATA Flow control output hold FCOUT_CLK 1 - nS
ia
FCOUT_SYNC time
n t
e
FCIN_CLK/FCIN_DATA,FCIN_SYNC INTERFACE TIMING WAVEFORM OF INPUT
d
n
F
fi
o
FCIN_CLK
C TSU THD
c
FCIN_DATA/
e
FCIN_SYNC
n t
e
Figure 10-4 : FCIN_* Signals Input Timing Diagram
C
FCOUT_CLK
FCOUT_DATA/
FCOUT_SYNC
Tosu Toh
Figure 10-5 : FCOUT_* Signals Output Timing Diagram

AC Timing
10.6 LED Interface Timing Parameter

Table 10-8 : LED Interface Timing Parameters
Symbol Signals Description Relative to Min Max Units
l
Clock
a
Freq LEDCLK LED clocks N/A - 25 MHz
DC LEDCLK LED clock duty cycle N/A 40 60
t
%
i
TOSU MACLED MACLED output setup time LEDCLK 10 -
n nS
de
TOH MACLED MACLED output hold time LEDCLK 10 - nS
f i
LEDCLK
o n
C
MACLED
e c
Tosu
n t
Toh
e
Figure 10-6 : LEDCLK/MACLED Output Timing Diagram
l C
t i a
10.7 HSS SerDes Signals Specifications
e n
fi d
Unless otherwise specified, the Table 9-16 characteristics are met while operating within the
Normal Range of Operating conditions. These specifications apply at CTC5118 BGA balls.
o n
Table 10-9 : HSS SerDes TX Signals Characteristics
Parameter
C Conditions Min Typ. Max Unit
c
Differential Output Peak to Peak
e
200 - 1200 mVp-p
t
Voltage
e n
20~80% rise/fall time
Differential return loss 1GHz ~ 6GHz
24
10
- 150 Ps
dB
C
Common mode return loss
DC output differential termination
0.1GHz ~ 6GHz 8
80 - 120
dB
ohm
Total Jitter 10.3125Gbps - - 20.15 ps
Random Jitter 10.3125Gbps - - 600 fs
Table 10-10 : HSS SerDes RX Signals Characteristics

Parameter Conditions Min Typ. Max Unit
Differential Input Peak to Peak
110 1000 mVp-p
Voltage

AC Timing
Parameter Conditions Min Typ. Max Unit

Input Transition time 0.15 - 0.4 UI
Differential return loss 1GHz~6GHz 12 dB
Common mode return loss 0.1GHz~6GHz 6 dB
DC input differential termination 80 120 Ohm
Freq. offset tolerance -100 0 100 ppm
a l
t i
10.8 QSPI Interface Timing Parameter e n
fi d
on
Table 10-11 : QSPI Interface Timing Parameters
Symbol Signals Description Min
C Typ Max Units
ec
fCK QSPI_CLK QSPI clock frequency 1 - 25 MHz
nt
tCK QSPI_CLK QSPI clock period 40 1/tCK 1000 ns
tWH QSPI_CLK QSPI clock high time 0.4 tCK - 0.6 tCK nS
tWL QSPI_CLK QSPI clock low time
e 0.4 tCK - 0.6 tCK nS
tDO
tSU
QSPI_DATA
QSPI_DATA QSPI data Setup time
l C
QSPI data output valid time -
5
- 12
-
nS
nS
tHD QSPI_DATA QSPI data Hold time
tia 5 - nS
tCSS
tCSH
QSPI_CS[1:0]
QSPI_CS[1:0]
e n
QSPI chip select output lead time
QSPI chip select output trail time
1 tCK
1 tCK
-
-
nS
nS
f id
n
QSPI_CS
o
tCSS tWH tWL tCSH
QSPI_CLK
C tDO
c
QSPI_DATA (Output) VALID OUTPUT
e
tSU tHD
n t
QSPI_DATA (Input) VALID INPUT
e
Figure 10-7 : QSPI_* Timing Diagram
C
10.9 SPI Interface Timing Parameter
Table 10-12 : SPI Interface Timing Parameters
Symbol Signals Description Min Typ Max Units
fCK SPI_CLK SPI clock frequency 2 - 25 MHz
tCK SPI_CLK SPI clock period 40 1/fCK 500 ns

AC Timing
Symbol Signals Description Min Typ Max Units

tWH SPI_CLK SPI clock high time 0.4 tCK - 0.6 tCK nS
tWL SPI_CLK SPI clock low time 0.4 tCK - 0.6 tCK nS
tDO SPI_MOSI SPI data output valid time - - 5 nS
relative to SPI_CLK falling edge
tSU SPI_MISO SPI data in setup time relative to 4.0 - nS
a l
i
SPI_CLK rising edge
tHD SPI_MISO SPI data in hold time relative to
SPI_CLK rising edge
5.0 - -
n t
nS
de
tCSS SPI_CS_B[3:0] SPI chip select active before 0.5 tCK - - nS
SPI_FSS SPI_CLK active edge
f i
tCSH SPI_CS_B[3:0]
SPI_FSS
SPI chip select not active after
SPI_CLK active edge
0.5 tCK -
o n - nS
C
e c
SPI_FSS/SPI_CS_B{0..3}
tCSS
n t
e
Mode3 tWH tWL
SPI_CLK
tDO
l C
a
SPI_MOSI VAILID OUTPUT
t i tSU tHD
SPI_MISO
e n VAILID INPUT
fi d
Figure 10-8 : SPI Interface Timing Diagram（For mode 3）
10.10 eMMC Interface Timing Parameter o n

C
c
MMC interface support the following speeds, frequencies, and voltages switching.
eMMC
t e

e n
Backwards Compatibility with legacy MMC card – up to 25MHz, 3.3V/1.8V

C High speed SDR – clock up to 50MHz, 3.3V/1.8V
Table 10-13 : eMMC Interface Input Timing Parameters

Signal Input Min Setup Time Input Min Hold Time
tISU tIH
CMD/DATA 0ns 2.0ns

AC Timing
Table 10-14 : eMMC Interface Output Timing Parameters

Speed Mode Max Freq. Min Period Output Min Output Max
fPP tODLY tODLY (ns)
l
Identification Mode 400KHz 2.5us - 50.0ns
MMC High Speed SDR 50MHz 20ns - 8.5ns
t i a
(DATA and CMD)
e n
fi d
on
tWH tWL
tPP
MSH_CLK
tIH
C
ec
tISU
Input (MSH_CMD/DATA) Data Data
Output (MSH_CMD/DATA)
tODLY
n t Data
e
MSH_CLK
l C tPP
tISUddr tIHddr
t i a tISUddr
tIHddr
n
Input (MSH_CMD/DATA) Data Data Data
d e tODLYddr(min)
tODLYddr(max)
tODLYddr(min)
tODLYddr(max)
fi
Output (MSH_CMD/DATA) Data Data Data
o n
Figure 10-9 : eMMC Interface Timing diagram
C
c
10.11 DDR3/DDR4 Timing Parameter
e
n t
Table 10-15 : DDR4 Interface Timing Parameters
e Parameter Symbol DDR4-1600
C Output clock timing spec

Min Typ Max
Average clock period tCK - 1.25 -

Average high-pulse width tCH 0.48 0.5 0.52
Average low-pulse width tCL 0.48 0.5 0.52
Clock-period jitter tJIT -0.063 - 0.063
Output signals timing spec
Address , command and Bank address setup time to clk tIS 0.215 - -

AC Timing
Parameter Symbol DDR4-1600

Min Typ Max
Address , command and Bank address hold time to clk tIH 0.215 - -
DQS_P differential high-pulse width tDQSH 0.46 - 0.54
DQS_P differential low-pulse width tDQSL 0.46 - 0.54
DQS_P/N falling to CLK_P/N rising tDSS 0.18 - -
a l
CLK_P/N rising to DQS_P/N falling tDSH 0.18 - -
t i
Input signals timing spec
n
de
DQS_P/N to DQ skew tDQSQ - - 0.16
fi
DQS_P/N differential input high pulse width tQSH 0.4 - -
on
DQS_P/N differential input low pulse width tQSL 0.4 - -
C
Table 10-16 : DDR3 Interface Timing Parameters
e c
Parameter Symbol Min
DDR3-800
Typ
n Max t Min
DDR3-1600
Typ Max Unit
Output clock timing spec
e
lC
Average clock period tCK - 2.5 - - 1.25 - ns
tia
Average high-pulse width tCH 0.47 0.50 0.53 0.47 0.50 0.53
tCK
Average low-pulse width tCL 0.47 0.50 0.53 0.47 0.50 0.53
Clock-period jitter tJIT
e n
-0.10 - 0.10 -0.07 - 0.07 ns
id
Output signals timing spec
Address , command and Bank
address setup time to clk
tIS
n f 0.200 - - 0.045 - -
o
ns
Address , command and Bank tIH 0.275 - - 0.120 - -
address setup time to clk
C
c
DQS_P differential high-pulse tDQSH 0.45 - 0.55 0.45 - 0.55
e
width
width
n t
DQS_P differential low-pulse tDQSL 0.45 - 0.55 0.45 - 0.55
e
DQS_P/N falling to CLK_P/N tDSS 0.2 - - 0.18 - -
tCK
rising
C
CLK_P/N rising to DQS_P/N tDSH 0.2 - - 0.18 - -
falling
Input signals timing spec
DQS_P/N to DQ skew tDQSQ - - 0.200 - - 0.100 ns
DQS_P/N differential input high tQSH 0.38 - - 0.4 - -
pulse width
tCK
DQS_P/N differential input low tQSL 0.38 - - 0.4 - -
pulse width

AC Timing
10.12 Trace Signals Timing Parameter
l
Table 10-17 : Trace Interface Timing Parameters
Symbol Signals Description Min Max
t i a
Units
n
FTRACE TRACE_CLK TRACE clock frequency - 150 MHz
de
DCTRACE TRACE_CLK TRACE clock duty cycle TBD TBD %
i
TOSU TRACE_DATA* TRACE output Setup time TBD - nS
TOH
TRACE_CTL
TRACE_DATA* TRACE output Hold time TBD
n f
- nS
TRACE_CTL
o
*1: If the HW design with 4-layer PCB, the trace function is not supported.
C
e c
n t
e
l C
t i a
e n
fi d
o n
C
e c
n t
e
C

Thermal Specifications
11 Thermal Specifications
i a l
11.1 Thermal Specification n t
d e
fi
Thermal specifications for this device are based on the JEDC JESD51 family of documents.
These documents are available on the JEDEC Web site at www.jedec.org. The thermal
on
specification are modeled using an four-layer test board with two signal layers, one power
plane and one ground planes (2s2p PCB).
Tj = Ta + θja x Power
C
Where θja =( θjc || θjb) + θca
e c
θja = Junction to Ambient thermal resistance (°C/W)
n t
e
θjc = Junction to Package Case thermal resistance (°C/W), Case temperature measured at the
top center of the outside surface of the component package
l C
θjb = Junction to Board thermal resistance (°C/W). Board temperature measured at the center
ia
ball or column location on the outer most ball or column row of the longest side of the
package.
t
n
θca = Package Case to Ambient thermal resistance (°C/W)
e
fi d
The typical θja is 0.5C/W with heat sink and environment as below:

o n
Heatsink Width in mm ------------------------------------->80
C
 Heatsink Length in mm ------------------------------------>80
Heatsink Height in mm ------------------------------------>25
c

e
 Air Flow in LFPM ------------------------------------------->400

n t
Heat sink Base Thickness in mm ------------------------->4
Heat sink Fins Pitch in mm -------------------------------->2.7
e

Heat sink Fin Thickness in mm --------------------------->1
C

 Number of Fins ---------------------------------------------->30

 Thermal Resistance of Heat sink in C/W --------------->0.37 @ 400 LFPM air flow
 Estimated Mass(weight) of Heat sink in grams -------->233g
 Heat sink Material ------------------------------------------->Extrusion Grade Aluminum
Air Flow in LFPM 0 100 200 300 400 600 700
θja (C/W) 4.74 1.85 1.31 1.10 0.98 0.86 0.82
θsa (C/W) 4.35 1.46 0.91 0.70 0.58 0.45 0.42
 Note: θsa is the thermal resistance of proposed heat sink.

Thermal Specifications
 For this package/Die combination:

 θjc = 0.39 Degree C/Watt
 θjb = 0.69 Degree C/Watt
 1. This proposed heat sink solution is a traditional extruded heat sink solution, which
meets thermal requirement for a listed application and environment conditions.
a l

t
2. Note that many more other thermal solutions can be possible for this package and
i
n
application environments.
e
 3. The heat sink attaches process uses phase change material with 3.8 W/m-K thermal
d
conductivity, 5mil thickness and at least 80% coverage.
fi
 4. If any of these application conditions or thermal parameters changes, the thermal
on
solution may not work.
11.2 Reflow Profile

C
e c
n t
e
l C
t i a
n
Figure 11-1 Device Reflow Profile
d e
n fi
o
C
e c
n t
e
C

Package Mechanical Dimensions
12 Package Mechanical Dimensions

i a l
12.1 Package Description n t
d e
fi
Table 12-1 is the package size description of CTC5118.
on
Table 12-1 : Package Mechanical Size
C
Package Package Package Lead frame Package thickness(mm) Pin pitch
Type Dimension Include BALL (mm)
ec
FC-PBGA 1043, 31.0mm*31.0mm OPL Forced Nom = 2.656 0.800
FC-PBGA Lead Free
t
Max = 2.816
n
12.2 Marking e
l C
t ia
The marking of CTC5118 is shown as Figure 12-1.
e n
fi d
TSINGMA.CX
o n
C
XX XXX X.XX ABC D
e c
YY WW
n t
CTCXXXX R001
e Made in China
C
Figure 12-1 : Device Marking
The descriptions of marking are listed as below:

Table 12-2 Descriptions of marking

Marking Description
TSINGMA.CX Chip Name
“XXXXXX.XXABCD” Lot Number
“YYWW” Date Code
a l
CTCXXXX Chip Part Number
t i
“R001” Revision Level and Number
e n
Made in China Made in China
fi d
on
A01 Corner Identifier
C
12.3 Package Dimension e c
n t
e
Figure 12-2, Figure 12-3, Figure 12-4 is the CTC5118 package mechanical diagram.
TOP VIEW
l C
t ia
e n
fi d
o n
C
e c
n t
e
C
Figure 12-2 : Top view

BOTTOM VIEW
a l
t i
e n
fi d
on
C
e c
n t
e
Figure 12-3 : Bottom View
l C
t ia
SIDE VIEW
e n
fi d
o n
C
e c
n t
e
C

a l
t i
en
fi d
on
C
Figure 12-4 Side View
e c
t
Table 12-3 lists the mechanical dimensions of CTC5118 package.
n
Table 12-3 : Package Size Parameters
e
lC
Dimension in mm Dimension in inch
Symbol
ia
Min. Nom. Max. Min. Nom. Max.
A 2.496 2.656
n t 2.816 0.098 0.105 0.111
de
A1 0.35 0.40 0.45 0.014 0.016 0.018
A2 2.106 2.256 2.406 0.083 0.089 0.095
c
D
0.756
30.80
n fi0.856
31.00
0.956
31.20
0.030
1.213
0.034
1.220
0.038
1.228
E 30.80
o 31.00 31.20 1.213 1.220 1.228
D1
C
--- 28.80 --- --- 1.134 ---
E1
e c --- 28.80 --- --- 1.134 ---

e
b
n t ---
0.46
0.80
0.51
---
0.56
---
0.018
0.031
0.020
---
0.022
e
aaa 0.20 0.008
C ccc
ddd
0.35
0.20
0.014
0.008
eee 0.20 0.008
fff 0.08 0.003
MD/ME 37/37

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C6.2.1 Interface Signals ......................................................................................... 34

Draft 11 (2020-08-17) 3 Copyright © Centec Networks (Suzhou) Co., Ltd.

6.6 I2C Slave Interface ......................................................................... 38

Draft 11 (2020-08-17) 4 Copyright © Centec Networks (Suzhou) Co., Ltd.

10.9 SPI Interface Timing Parameter ......................................................... 95

Draft 11 (2020-08-17) 5 Copyright © Centec Networks (Suzhou) Co., Ltd.

Draft 11 (2020-08-17) 6 Copyright © Centec Networks (Suzhou) Co., Ltd.

Draft 11 (2020-08-17) 7 Copyright © Centec Networks (Suzhou) Co., Ltd.

Table 9-3 : Recommended Power Supply .................................................... 82

Draft 11 (2020-08-17) 8 Copyright © Centec Networks (Suzhou) Co., Ltd.

Table 12-1 : Package Mechanical Size ...................................................... 102

Draft 11 (2020-08-17) 9 Copyright © Centec Networks (Suzhou) Co., Ltd.

1 About This Document

1.2 Acronyms and Abbreviations C

e c Generic Routing Encapsulation

Draft 11 (2020-08-17) 10 Copyright © Centec Networks (Suzhou) Co., Ltd.

e c Quad Serial Peripheral Interface

n t Serial Peripheral Interface

Draft 11 (2020-08-17) 11 Copyright © Centec Networks (Suzhou) Co., Ltd.

1.4 Revision History

2020-03-10 Draft02 Update the description about pin BOOT_RESV in 71

f ide Add note “NOTE： All interfaces need to be

n t 5ms earlier than external CPU.

e external CPU use the same origin clock.” for

Draft 11 (2020-08-17) 12 Copyright © Centec Networks (Suzhou) Co., Ltd.

Date Version Description Page

Update the QSPI_CLK rate to 25MHz in table 8-1 90

Update the USB_VBUS0 description in table8-1 75

Draft 11 (2020-08-17) 13 Copyright © Centec Networks (Suzhou) Co., Ltd.

Draft 11 (2020-08-17) 14 Copyright © Centec Networks (Suzhou) Co., Ltd.

IPE Destination Processing

Draft 11 (2020-08-17) 15 Copyright © Centec Networks (Suzhou) Co., Ltd.

Layer 3 Packet Editing

3.1 Core and I/O Bandwidth a l C

Packet Length (Bytes)

Figure 3-3 : Chip performance for 180Gbps bandwidth

Draft 11 (2020-08-17) 16 Copyright © Centec Networks (Suzhou) Co., Ltd.

3.2 Feature List

 5GbE (1-lane) QSGMII (Only 12 of QSGMII PCS interfaces are supported)

2-Lane SerDes Macro

Draft 11 (2020-08-17) 17 Copyright © Centec Networks (Suzhou) Co., Ltd.

t e VLAN classification based on MAC SA/MAC DA/IP SA/IP DA/any L2 fields

e n Single or double tag VLAN switching

Spanning Tree，MSTP, RSTP

Draft 11 (2020-08-17) 18 Copyright © Centec Networks (Suzhou) Co., Ltd.

 Flowlet-based dynamic load balance for LAG

 L3: IP DA/IP SA/IP header protocol/MPLS label

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e  Isolation on flooded packets only or all packets

C Binding with any combination of IP/ MAC/ Port/ VLAN

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Applied on port, VLAN, L3Interface, and LogicPort

 Redirect to CPU with timestamp attached

Priority and color remark

t e Specify CPU Queue Id for traffic to CPU

Draft 11 (2020-08-17) 21 Copyright © Centec Networks (Suzhou) Co., Ltd.

Tunnel ECN, flow-based ECN，stacking-based ECN

e c Ingress/Egress Resource Manage

n t Flexible PHB Mapping

Draft 11 (2020-08-17) 22 Copyright © Centec Networks (Suzhou) Co., Ltd.

Draft 11 (2020-08-17) 23 Copyright © Centec Networks (Suzhou) Co., Ltd.