Cortex-M3: The ARM Processor for Embedded Applications

The ARM® Cortex™-M3 32-bit processor has been specifically developed to provide
a high-performance, low-cost platform for a broad range of applications, including
microcontrollers, automotive body systems, industrial control systems and wireless
networking. With a balance between size and speed, Actel's free Cortex-M3
processor operates at up to 100 MHz and is included as a hard resource in
Actel's SmartFusionFPGA device family. The central core of the Cortex-M3
processor, based on a 3-stage pipeline Harvard bus architecture, incorporates
advanced features such as hardware single-cycle multiply and hardware divide. The
Cortex-M3 processor implementation of the Thumb®2 instruction set, plus features
such as unaligned data storage and atomic bit manipulation, deliver world class 32-
bit performance. The configurable Cortex-M3 processor connects to the Advanced
High-Performance Bus (AHB), enabling designers to build their subsystem and easily
add peripheral functionality. In addition to SmartDesign andSoftConsole from Actel
and RealView® tools from ARM, third-party vendors offer a vast range of supporting
tools in the well-established ARM ecosystem, from compilers and debuggers to real-
time operating system (RTOS) solutions.

Cortex-M3 Features

 ARMv7-M architecture, optimized for microcontroller and low-cost

applications
 Hardware single-cycle multiply and hardware divide instructions
o 32-bit multiplication in a single cycle
o Signed and unsigned divide operations between 2 and 12 cycles
 Thumb-2 instruction set
o Enhanced levels of performance, energy efficiency, and code density
o Mixed mode capability implies no need to interwork between modes
o ARM7 levels of performance with thumb-level code density
 Hierarchical structure with tightly integrated peripherals
o CM3Core
 Based on modified Harvard bus architecture with combined I-
code and D-code buses
 Highly efficient 3-stage pipeline with branch speculation
 Nested vectored interrupt controller (NVIC)
 Gate efficient stack-based register model
 Configurable from 1 to 150 physical interrupts; up to 256 levels
of priority
 Non-maskable interrupt (NMI) enables critical interrupt
capabilities
 Low latency through tail chaining, late arrival service and stack
pop pre-emption
 Nesting (stacking) of interrupts
 Dynamic interrupt reprioritization
 o Memory protection unit (MPU)
 Optional component for separation of processing tasks and data
protection
 Up to 8 regions of protection; each of which can be divided into
8 sub-regions
 Region sizes from 32 bytes to the entire 4 gigabytes of
addressable memory
o Data watchpoint and trace unit (DWT)
 Implements hardware breakpoints and provides instruction
execution statistics
 DWT configured to include data matching
o Flash patch and breakpoint unit (FPB) that implements 6 program
breakpoints and 2 literal data fetch breakpoints
o Debug port (SWJ-DP)
 Serial Wire JTAG debug port (SWJ-DP) enabling either JTAG or
SW protocol for debugging
 SWJ-DP defaults to JTAG mode at power-up
 Can be switched to SW by applying a specific sequence to the
debug pins
o Trace port interface unit (TPIU)
 Configured to support instrumentation trace macrocell (ITM)
debug trace only
 Serial Wire mode is used for the TPIU output data, overlaid on
the JTAG TDO port
 SW debugging and ITM can be used concurrently
o ROM table as described in the Cortex-M3 Technical Reference Manual
o I-Code and D-Code buses combined into a single shared code bus
within the AHB bus matrix, with the bus access internally arbitrated by
Cortex-M3
o 150 interrupts (151 including NMI)
o 32 levels of interrupt priority
 Preconfigured memory map
 Up to 4 gigabytes of addressable memory space
 Predefined addresses for code, memory, external devices, peripherals
 Dedicated space for vendor specific addressability
 Atomic bit manipulation with bit banding
o Direct access to single bits of data
o Two 1 MB bit banding regions for memory and peripherals mapping to
32 MB alias regions
o Atomic operation, cannot be interrupted by other bus activities
 Unaligned data storage and access
o Continuous storage of data requiring different byte lengths
o Data access in a single core access cycle
 Integrated sleep modes
o Sleep Now mode for immediate transfer to low-power state
o Sleep on Exit mode for entry into low-power state after the servicing
of an interrupt
o Ability to extend power savings to other system components
  Supported by a full range of development tools

Cortex-M3 Devices

Cortex-M3 is available for use in SmartFusion flash

devices as an on-chip processor. SmartFusion devices combine the Cortex-M3 and
supporting AHB infrastructure with Actel's proven low-power nonvolatile flash FPGA
fabric, on-chip embedded nonvolatile memory (eNVM), an extensive set of on-chip
communication interfaces, and a flexible analog subsystem to deliver the ideal
solution for embedded system designers.

SmartFusion Features

 ARM Cortex-M3 32-bit processor running at up to 100 MHz

 Internal memory
o eNVM, 64 Kbytes to 512 Kbytes
o Embedded high-speed SRAM (eSRAM), 16 Kbytes to 64 Kbytes,
implemented in 2 physical blocks to enable simultaneous access from 2
different masters
  Multi-layer AHB communications matrix provides up to 16 Gbps of on-chip
memory bandwidth (theoretical maximum)
 10/100 Ethernet MAC with RMII interface in SmartFusion A2F200 and larger
devices
 Programmable external memory controller in SmartFusion A2F200 and larger
devices, supporting:
o Asynchronous memories
o NOR flash, SRAM, PSRAM
o Synchronous SRAM
 Two I C peripherals
2

 Two 16550 compatible UARTs

 Two SPI peripherals
 Two 32-bit timers, combinable into a single 64-bit timer
 32-bit watchdog timer
 8-channel DMA controller
 Clock sources
o 1.5 MHz to 20 MHz main oscillator
o Battery-backed 32 KHz low-power oscillator with real-time counter
(RTC)
o 100 MHz embedded RC oscillator; 1% accurate
o Embedded PLL with 4 output phases
 Proven low-power, highly-reliable FPGA fabric
 On-chip mixed-signal analog compute engine (ACE)
 Embedded real-time debug and JTAG interface
 Available with no license fees or royalties

For more information, visit the SmartFusion web page.

Availability

Cortex-M3 Devices A2F060 A2F200 A2F500

SmartFusion
Intellectual Property

In addition to the on-chip AHB bus and communications

infrastructure supporting the Cortex-M3, Actel offers a broad portfolio of IP cores
for use in the FPGA fabric to implement custom design solutions. A wide range of IP
cores are available FREE in theLibero® Integrated Design Environment (IDE)
Catalog and SmartDesign IP design tool.
To see a complete list of IP cores available in Libero IDE, visit the Actel IP
cores web page. Actel provides software drivers that ease the use of the cores for
application developers, enabling development to focus on system capability instead
of basic infrastructure. Actel's Firmware Catalog includes all of the available
drivers and is installed with Libero IDE.

Software developers will find support for SmartDesign and the Cortex-M3 in Actel's
Eclipse-based SoftConsole, Keil™, IAR Systems® software development
environments.

Design Software

Libero Integrated Design Environment (IDE)

 Actel comprehensive FPGA design and development software

 Combines the latest design creation, physical implementation, and
verification tools from leading EDA vendors

For more information, visit the Libero IDE web page.

SmartDesign

 Graphical block system design creation tool

 Create complete FPGA and system-on-chip (SoC) designs, including
processors, Actel IP cores, standard library cores, user IP, and custom HDL
 Automatically creates synthesis-ready HDL
 Operates within Libero IDE

For more information, visit the SmartDesign web page.

SoftConsole

 Eclipse-based Actel processor software development environment

 Includes GNU C/C++ compiler and GDB debugger

For more information, visit the SoftConsole web page.