Lab Exercise9_ VLSI Design;

Aim: To simulate the C2MOS Latch and analyze its operation

Simulate the operation of the clocked CMOS latch shown in Fig.

To simulate apply the waveform as suggested below

clk PULSE 0 1 500p 0 0 1n 2n
clkb PULSE1 0 500p 0 0 1n 2n
D PULSE 0 1 250p 0 0 750 1.25n
VDD dc 1
The simulation output for figure

As we can see from the output waveform, the clock samples the input when it is low and
transfers the data to the output “q” when the clock goes high. This behavior is similar to the edge
triggered D-FF.