BITS Pilani

Pilani Campus

RKTiwary
Digital Design
Converting from Truth Table to Boolean
Function

In designing digital circuits, the designer often begins

with a truth table describing what the circuit should do.
 The design task is largely to determine what type of
circuit will perform the function described in the truth
table.
 While some people seem to have a natural ability to look
at a truth table and immediately envision the necessary
logic gate or relay logic circuitry for the task, there are
procedural techniques available for the rest of us.
 Here, Boolean algebra proves its utility in a most
dramatic way!

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Converting from Truth Table to Boolean
Function

This problem will be solved by showing that any

Boolean function can be represented by a Boolean
sum of Boolean products of the variables and their
complements or the product of sums.

• There are two ways to convert from truth tables

to Boolean functions:
1. Using Sum of Products /Minterms
2. Using Product of Sums /Maxterms

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Converting from Truth Table to Boolean
Function

• Minterm
– Product (AND function)
– Contains all variables
– Evaluates to ‘1’

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Converting from Truth Table to Boolean
Function

• Maxterm
– Sum (OR function)
– Contains all variables
– Evaluates to ‘0’ for a
specific combination

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Converting from Truth Table to Boolean
Function Using Minterms & Maxterms
Truth Table to Boolean Function

F= A’B’C+ AB’C’+ AB’C + ABC

F= (A+B+C) (A+B’+C) (A+B’+C’) (A’+B’+C)

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Gate-Level Minimization

 The Boolean functions also can be simplified by

map method as Karnaugh map or K-map.
 The map is made up of squares, with each square
representing one minterm or maxterm of the
function.
 This produces a circuit diagram with a minimum
number of gates and the minimum number of
inputs to the gate.
 It is sometimes possible to find two or more
expressions that satisfy the minimization criteria.

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Two-Variable map
Two-variable has four minterms, and consists of four
squares.

Example: m1 + m2 + m3 = x’y + xy’ + xy

=x(y+y’)+x’y
= x+x’y= (x+ x’)(x + y)= x+y
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Three-Variable map

Note that the minterms are not arranged in a binary sequence,

but similar to the Gray code.
For simplifying Boolean functions, we must recognize the basic
property possessed by adjacent squares.
m5+m7= xy’z + xyz = xz(y’ + y) = xz
discarded

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 3 variable :Simplification of the number of
adjacent squares

A larger number of adjacent squares are combined,

we obtain a product term with fewer literals.
1 square = 1 minterm = three literals.
2 adjacent squares = 1 term = two literals.
4 adjacent squares = 1 term = one literal.
8 adjacent squares encompass the entire map and
produce a function that is always equal to 1.

It is obviously to know the number of adjacent squares is

combined in a power of two such as 1,2,4, and 8.

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Example

 Ex.3-3 F(x, y, z) = ∑(0, 2, 4, 5, 6)

=+

F = z’ + xy’

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 Karnaugh Map simplification Algorithm
 Encircle and accept as prime implicants any box or boxes that cannot
be combined with any other
 Identify the boxes that can be combined with a single other box in only
one way. Encircle such two box combinations. A box which can be
combined into a two-grouping but can be combined in more than one
way is to be temporarily bypassed
 Identify the boxes that can be combined with three other box in only
one way. If not all of the four boxes so involved are already covered in
grouping of two, encircle these four boxes. Again, a box which can be
encompassed into a group of 4 in more than one way is to be
temporarily bypassed
 Repeat the preceding for groups of 8 etc.
 After the above procedure if at all there remain any uncovered boxes,
they are to be combined with each other or other already covered
boxes in arbitrary manner if possible, keeping in mind to make as few
grouping as possible.

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Four-variable map
1 square = 1 minterm = 4 literals
2 adjacent squares = 1 term = 3 literals
4 adjacent squares = 1 term = 2 literals
8 adjacent squares = 1 term = 1 literal
16 adjacent squares = 1

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Example

Ex. 3-6 F = A’B’C’ + B’CD’ + A’BCD’ + AB’C’

= B’D’ + B’C + A’CD
’ ’

14
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Essential prime implicants

F(A, B, C, D) = (0, 2, 3, 5, 7, 8, 9, 10, 11, 13, 15)

If a minterm in a square is
covered by only one prime
implicant, that the prime
implicant is said to be essential.

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Prime implicant
F(A, B, C, D) = (0, 2, 3, 5, 7, 8, 9, 10, 11, 13, 15)

A prime implicant is a product term

obtained by combining the maximum
possible number of adjacent squares
in the map.

This shows all possible ways that the

three minterms(m3,m9,m11) can be
covered with prime implicants.

F = BD+B’D’+CD+AD

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Prime implicant
F = BD+B’D’+CD+AD

= BD+B’D’+CD+AB’

= BD+B’D’+B’C+AD

= BD+B’D’+B’C+AB’

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Product of sums simplification

If we mark the empty squares by 0’s rather than 1’s

and combine them into valid adjacent squares, we
obtain the complement of the function, F’. Use the
DeMorgan’s theorem, we can get the product of
sums.
Ex.3-8 Simplify the Boolean function in
(a) sum of products
(b) product of sums
F(A, B, C, D) = ∑(0, 1, 2, 5, 8, 9, 10)

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Example F(A, B, C, D) = ∑(0, 1, 2, 5, 8, 9, 10)

(a) SOPs

F=
B’D’+ B’C’ + A’C’D
(b) POSs

F’=
AB + CD + BD’
By Demorgan’s Law
F= (A’+B’ .
).(B’+D) (C’+D’)

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Explanation

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Exchange minterm and maxterm

Consider the truth table that

defines the function F in Table
3-2.
Sum of minterms
F(x, y, z) = ∑(1, 3, 4, 6)
Product of maxterms
F(x, y, z) = ∏(0, 2, 5, 7)
In the other words, the 1’s of
the function represent the
minterms, and the 0’s
represent the maxterms.

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Example continued

F= x’z + xz’

F= (x’+z’) .(x+z)

F’= xz + x’z’
Aplying DeMorgan’s Law
F= (x’+z’).(x+z)

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Don’t care conditions

Ex.3-9 Simplify the F (w, x, y, z)= ∑(1, 3, 7, 11, 15) with

don’t-care conditions d(w, x, y, z) = ∑(0, 2, 5)
In part (a) with minterms 0 and 2 F = yz + w’x’
In part (b) with minterm 5  F = yz + w’z

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 Example
  F(A,B,C,D)=

AB CD 00 01 11 10
00 1 1 1
01 1 1
11 1 1 1
10 1 1

AB CD 00 01 11 10 F= A’BCD’

00 1 1 1 + A’B’C’+ ABC’
01 1 1
+ B’D + C’D
11 1 1 1
+AD
10 1 1

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NAND and NOR implementation

NAND gate is a universal gate because any digital system can

be implemented with it.
NAND gate can be used to express the basic gates, NOT,
AND, and OR.

(x.y)’ ((x.y)’)’= xy

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Two graphic symbols for NAND gate

In part (b), we can place a bubble (NOT) in each

input and apply the DeMorgan’s theorem, then get a
Boolean function in NAND type.

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Two-level implementation

Double
F = AB + CD complementation,
so can be removed
=

OR
gate,Fig.3-
18

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Multilevel NAND circuits

To convert a multilevel AND-OR diagram into an all-

NAND diagram using mixed notation is as follows:
1. Convert all AND gates to NAND gates with AND-invert
graphic symbols.
2. Convert all OR gates to NAND gates with invert-OR
graphic symbols.
3. Check all the bubbles in the diagram. For every bubble
that is not compensated by another small circle along the
same line, insert an inverter or complement the input
literal.

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Multilevel NAND circuits

(CD)
(CD+B)
A(CD+B)

A(CD+B)+BC
(BC)

(CD)’
(CD)
(CD+B) A(CD+B)
B
A
A(CD+B)+BC
(BC)’

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NOR implementation

The NOR operation is the dual of the NAND operation, all

procedures and rules for NOR logic are the dual of NAND
logic.
NOR gate is also a universal gate.

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Two graphic symbols for NOR gate

In part (b), we can place a bubble (NOT) in each

input and apply the DeMorgan’s theorem, then get a
Boolean function in NOR type.

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Implementing F with NOR gates

F = (AB’ + A’B)(C + D’)

To compensate for the bubbles in four inputs, it is
necessary to complement the corresponding input
literals.

AB’
(AB’ + A’B)’ (AB’ + A’B)(C+D’)

A’B

(C + D’)’

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Mapping when function not entered in Minterm

F(A,B,C,D)= A’B’C’D’+BC’D+A’C’+A

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 Example (practice)
  F(A,B,C,D)=

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 Quine McCluskey Method
F(a,b,c,d)= m(0,1,2,5,6,7,8,9,10,14)

Grp D Grp
0 0 0 0 0 0 0,1 000- 0,1,8,9 -00-
1 0 0 0 1 0,2 00-0 0,2,8,10 -0-0
1 0,8 -000 -00-
2 0 0 1 0 0,8,1,9
8 1 0 0 0 1,5 0-01 0,8,2,10 -0-0
5 0 1 0 1 1,9 -001 2,6,10,14 - -10
6 0 1 1 0 2,6 0-10 2,10,6,14 - -10
2 9 1 0 0 1 2,10 -010
10 1 0 1 0 8,9 100-
7 0 1 1 1 8,10 10-0
3 5,7 01-1
14 1 1 1 0
6,7 011-
6,14 -110
10,14 1-10

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Thanks

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956