Basic Analog and Digital Multiplexer Design Comparison

April 2002
Revised April 2002

Basic Analog and Digital Multiplexer Design Comparison

Switches and muliplexers are integral building blocks in the In order to have an analog switch (which can be used with
telecommunications industry, which is growing at an expo- a digital signal as well) a pass gate configuration is
nential rate. In this industry, it is important for designers to required. A pass gate configuration uses an NMOS and
understand the functional difference between analog and PMOS in parallel as shown in Figure 2.
digital devices. This document provides an overview of
how analog and digital devices differ in functionality based
on whether a standard NMOS or a pass gate configuration
is used. A designer can choose one or both of these config-
urations depending on design requirements. If a simple
HIGH (VOH) or LOW (VOL) signal is required, a designer
can use either of these configurations. If a sine wave is
required, then the designer should choose the analog con-
figuration.
The following subjects will be discussed in this document:
• The difference between analog and digital switches FIGURE 2. Analog/Digital Switch
• How NMOS switches will not provide analog rail-to-rail
outputs. The main difference here is that when the NMOS FET
• How an analog pass gate device will work with any volt- turns off (when VIN > VG - VT), the PMOS FET will then turn
age between VSS and VCC. on, transferring the complete input signal to the output.
Note: PMOS FETs require a low voltage to turn ON If a low RON specification is required, this circuit can be
(VGS < VT) (VT typically 1V) approximately three times the area as the circuit in Figure 1
Note: NMOS FETs require a high voltage to turn ON if a matched PMOS/NMOS device is required.
(VGS > VT) (VT typically 1V)

Analog Pass Gate Multiplexer

Differences Between Analog and An example of an analog pass gate design in the form of a
Digital Switches 2:1 analog/digital multiplexer switch is shown in Figure 3.
This device passes either an analog or digital signal. From
Figure 1 shows a digital switch using an NMOS FET as the
Figure 3, it is clear that if “S” is a logic “0” then P4 and N4
switch.
are ON, while P2 and N2 are OFF, thereby passing any
input signal connected to “B” to output “Z”. The signal on
input “B” can vary between VCC and ground due to the
operation of the NMOS and PMOS transistors.
Note: Select line “S” is a logic HIGH with 5 volts and a logic LOW with 0
volts.

FIGURE 1. Digital Switch

Depending on the gate voltage (VG), VOUT will be limited by

VG - VT, where VT is the threshold voltage. The threshold
voltage is the minimum voltage required to turn the NMOS
on.
VOUT in Figure 1 results in a range of 0 to (VG - VT). This
will work for a digital input because VG - VT is larger than
VOH(MIN). If an analog signal was input, the upper end of
the signal would be clipped.
Example:
VG = 5 volts
VIN = 0 to 5 volts
VT = 1 volt
VOUT = 0 to 4 volts or 0 to (VG - VT)
FIGURE 3. Analog Pass Gate 2:1 Multiplexer
(Analog/Digital Output)

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Basic Analog and Digital Multiplexer Design Comparison
Analog Pass Gate Multiplexer (Continued)
If the select line “S” is set to a logic “1” or “HIGH”, then the As long as the input signal stays less than VG-VT for the
exact same result will happen for input “A”. Table 1 com- NMOS and greater than VG-VT for the PMOS, full range
pares the results of the different combinations. will be accomplished.
Note: The P2, P4, N2, and N4 represent the same functionality of P2, P4,
N2, and N4 shown in Figure 1.

TABLE 1. Analog Pass Gate 2:1 Multiplexer

Truth Table
A B S P2 N2 P4 N4 Z
0-VIN 0-VIN GND OFF OFF ON ON B
0-VIN 0-VIN GND OFF OFF ON ON B
0-VIN 0-VIN GND OFF OFF ON ON B
0-VIN 0-VIN GND OFF OFF ON ON B
0-VIN 0-VIN VCC ON ON OFF OFF A
0-VIN 0-VIN VCC ON ON OFF OFF A
FIGURE 5. Analog Waveform Low Signal
0-VIN 0-VIN VCC ON ON OFF OFF A
0-VIN 0-VIN VCC ON ON OFF OFF A
Note: There are three voltage regions of operation in an analog pass gate. NMOS Multiplexer
(PMOS/NMOS) (See Table 2):
Figure 6 displays a 2:1 multiplexer design using two NMOS
• Region A: NMOS non-saturated (ON), PMOS OFF
FETs instead of the pass gate configuration. In order for the
• Region B: NMOS non-saturated (ON), PMOS non-saturated (ON)
NMOS to turn on, the gate-to-source voltage (VGS) must be
• Region C: NMOS OFF, PMOS non-saturated (ON)
greater than the threshold voltage (VT) (see Figure 7). Cur-
rent (ID) remains zero until VGS is greater than VT. The
TABLE 2. Pass Gate Truth Table
threshold voltage is controlled during the fabrication pro-
Region VDSn VGSn |VT| Result VDSp VGSp |VT| Result cess and is usually set between 1 and 3 volts. The right
hand side of Figure 7 indicates that the NMOS shuts off at
A 0 5 1 ON 0 0 1 OFF
4 volts.
B 1 5 1 ON 1 0 1 ON
2 5 1 ON 2 0 1 ON
3 5 1 ON 3 0 1 ON
4 5 1 ON 4 0 1 ON
C 5 5 1 OFF 5 0 1 ON
Note: In most case the Input signal.

The waveform in Figure 4 is an example of an analog sig-

nal being passed through an analog switch. This waveform
shows how the input signal is passed through to the output.

FIGURE 6. Digital NMOS 2:1 Multiplexer

The Truth Table (Table 3) shows that each gate will turn off
when the input signal is VGS - VT, meaning that full rail-to-
rail signal pass is not accomplished from input to output
using this configuration. This feature is the major reason
why pass gate devices are used.
FIGURE 4. Analog Waveform
TABLE 3. NMOS 2:1 Multiplexer Truth Table
The waveform in Figure 5 indicates why a pass gate is
used in analog and digital applications. A pass gate VDS VGS VT RESULT
achieves rail-to-rail outputs and allows lower voltage sig- 0 5 1 ON
nals to pass through without modifying the original signal.
1 5 1 ON
This feature is accomplished by having the source of the
PMOS and the drain of the NMOS connected directly to the 2 5 1 ON
input voltage (VIN) rather than VCC or VSS. 3 5 1 ON
4 5 1 ON

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 Basic Analog and Digital Multiplexer Design Comparison
NMOS Multiplexer (Continued)
VDS VGS VT RESULT
5 5 1 OFF
Note: Using VDS ≤ VGS −VT and the select line “S” set at 5 Volts.

FIGURE 7. NMOS Transfer Characteristic

The waveform in Figure 8 explains the operation of a Conclusion

NMOS switch, whereby the output clips 1 volt below VCC.
FIGURE 8. NMOS Waveform Output Clipped at 4V
This document provides an overview of how analog and
digital devices differ in functionality using either a standard
NMOS or pass gate configuration. One or both of these
configurations may suit any design depending on the
requirements.
If a simple HIGH or LOW signal is required, a designer can
use a standard NMOS or pass gate configuration. But if an
analog signal is required with signal integrity being an
important characteristic, then the designer may want to
choose the analog option (pass gate configuration).
Switches and multiplexers are an important building block
in circuit design especially in telecommunications. As the
telecommunication market grows, so does the need for
these devices. Therefore an understanding of the differ-
ences is important.
The information in this document is based on devices run-
ning at a signal speed of 300 MHz or lower. For high fre-
quency RF applications specifications such as transistor
matching, RON and off-isolation are a few areas that need
to be investigated (See Fairchild Semiconductor Miscella-
neous document, MS-556, “Effects of On Resistance RON
to an Analog Switch”.).

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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