Spurious in Phase Locked Loop (PLL)

University of California, San Diego – XXXXXX

PLL Synthesizers for Wireless Systems; By Professor XXXXX

Presented by; XXXXX, March 7th 2020

Content
1. Introduction
2. PLL synthesizers spurious
a. Reference & Non-reference spurious
i. Types
1. Definition
2. Mitigations
Introduction:

An unintended signal which gets generated as a result of Harmonics, Frequency Conversion or Electro-magnetic
interference is called a spurious signal. This signal is unwanted in the path of transmission or frequency
generation because of the reason that it contributes to the noise in the system. Spurious signals in contrast to
the harmonics are present at the non-integer multiple of the carrier frequency whereas harmonics are a
function of the carrier frequency.
PLL Synthesizers spurious:

The phase locked loop is negative feedback system which keeps the phase and the frequency of a Voltage
controlled oscillator constant and is build using the following building blocks. When there’s a need of using a
High frequency local oscillator a PLL is used.

The PLL consists of various power supplies throughout the different blocks such as V_OCXO, V_CP and V_VCO.
The spurs correlated to the noise or any unwanted signals present on these power supplies which gets
translated in to spurs at the signal of the local oscillator. The spurious present at the LO signal cannot be
completed eliminated but can be reduced up to a certain extent, which are also referred as reference spurs.

In PLL synthesizers, spurious tones are undesirable as they are in any other applications. The following are the
few ways in which spurs are transmitted and received as a part of the system;

1. In radio transmissions, spurs get transmitted as a part of the carrier frequency which eventually
interfere with the adjacent channels.
2. In receivers, spurs convert signals in the adjacent channels which causes interference and sensitivity
issues.
3. In clock and data recovery circuits, spurs are responsible for BER (Bit error rate) due to edge-transition
inaccuracies where 0 is interpreted as 1 and vice-versa.
4. In Fractional-N synthesizers, spurs at the output of the signal results in an increased noise floor for the
synthesizers.
To narrow the scope of the report the spurious could be categorized in to the followings sections;
1. Reference Spurs; The type of spurs appearing at the multiples of the comparison frequency is termed as
reference spurs. Spurs constitutes a variety of different spurs arousing from various parts, internal or
external to the PLL. Reference spurs are causes by the charge pump, where leakage dominates the lower
frequency and mismatch dominates the high frequencies internally causes by the AC modulation on the
tuning line of the VCO which is wrongly interpreted as FM modulation.

a. Spurs due to leakage effects; In a locked condition, the charge pump generates short alternating
pulses of current with longer OFF time versus shorter ON time. During the OFF time, charge
pump sees the infinite impedance, but in-fact there’s some leakage through the charge pump
along with some leakage from the VCO, Capacitors and the PCB. The leakage effects are more
dominant at the lower frequency is because of the fact that the charge pump has a longer
duration to leak at the OFF time.
i. The leakage due to the charge pump is a temperature dependent entity and can be
controlled up to a certain extent by controlling the temperature.
ii. Spurious would rise exponentially if the temperature of the PLL is increased

b. Spurs due to mismatches; The definition of the reference spurs quite clearly defines that the
charge pump is solely responsible for the reference spurs. Another type of spurs which charge
pump generates is spurs due to charge pump mismatch. This spurs are caused by when the
source current is not same as the sink current are caused by the following;
i. Mismatch over tuning voltage; The current sourced by the PMOS is sunked by the NMOS
devices. The effect of the tuning voltage at the source and sunk causes PMOS and NMOS
to draw more or less current and this combined effect causes mismatch.
ii. Unequal turn-on times; The PMOS and NMOS do not support an equal turn-on time
because of the difference in the majority charge carriers with respect to holes and
electrons. Holes appears to be slower in comparison to electrons which makes NMOS’s
turn-on time a bit faster than the PMOS. The PMOS is theoretically half the speed of
NMOS.

2. Non-reference Spurs; The non-reference spurs do not correlate to the reference spurs, or can be put
into the following words, any spurs that is not reference spurs is called Non-reference spurs. Non-
reference spurs are often seen in system using dual-PLL’s. The following section describes different
types of spurs, causes and remedies.

a. Auxiliary PLL Crosstalk Spurs

b. External Crosstalk Spurs
c. Fractional N Spurs
d. Greatest common multiple Spur
e. Phantom Reference Spur
f. Prescaler Miscounting spur
g. Reference spurs and their harmonics
h. VCO Harmonics spurs
Type(s) of Spurs Description Causes Remedies
Auxiliary PLL Crosstalk Often seen in dual PLLs Parasitic capacitances Diagnosis with respect to crosstalk on
Board or in the PLL
External Crosstalk Unrelated to the Auxiliary PLL output and appears Source is external to the PLL PLL should be isolated from the signal
from external sources source
Fractional N Spurs Appears only in fractional N PLL and appears at the Fractional N PLL employs averaging Imperfections in the compensation
multiples of the fractional Modulus M which gives rises to the fractional spurs circuitry.
Greatest Common Multiple Appears at the comparison frequency in a dual PLL Dual PLL system triggers both the Decoupling capacitors on the VCC and
system charge pumps at the same instance VPP lines
Phantom Reference Changes in reference frequency Various instruments measurement Reducing the number of leaky
techniques such as averaging capacitors
Pre-scaler Miscounting Appears at half the comparison frequency, and may Matching issues between the high Sensitivity is voltage dependent and
also occur at 1/3, 2/3 of the comparison frequency frequency input and violation of voltage tuning helps
sensitivity with respect to the PLL and
VCO harmonics
Reference/Harmonics Appears at the comparison frequency from the Mismatches and leakages in the charge Improvising loop filter design helps
carrier and their harmonics pump
VCO Harmonics Occurs at the multiple of output frequency VCO are the source of spurs Implementation of filters (LC/RC)
References:

1. University of California, San Diego

a. Extension course – PLL Synthesizers for wireless systems
i. Professor – Dr. Reza Moazzam
2. PLL Performance, Simulation, and Design
a. By Dean Banerjee
3. RF Microelectronics
a. Behzad Razavi
4. IEEE Explore
a. A Phase-Locked Loop reference spur modelling using Simulink
b. A Spur-reduction technique for a 5GHz frequency synthesizer
5. Texas Instruments
a. Integer/Fractional-N PLL Basics
6. Closed-loop spurious tone reduction for Self-healing frequency synthesizers
a. California Institute of Technology