Dell Latitude E7440 (Compal LA-9591P) PDF

A B C D E
COMPAL CONFIDENTIAL
MODEL NAME : VAUA0
1 1
PCB NO : LA-9591P (DAA00005W10)

BOM P/N : 4319LK31L01
GPIO MAP: 3.0
2
Goliad 14" 2
Haswell ULT
2013-05-17
REV : 1.0 (A00)
@ : Nopop Component
1@ : M/B SPI ROM
2@ : TAA/B SPI ROM
EMC@ : EMI, ESD and RF Component SPI on M/B TAA
3 3
XDP@ : XDP Component

Vpro 1@/3@/4@/EMC@ 2@/3@/5@/EMC@
CONN@ : Connector Component
3@ : M/B for non support WWAN non-Vpro 1@/EMC@ 2@/EMC@
4@ : M/B SPI 4M ROM Component
5@ : TAA/B SPI 4M ROM Component
7@ : M/B for Non-Vpro
4 4
MB PCB
Part Number Description
DELL CONFIDENTIAL/PROPRIETARY
DAA00005W10 PCB 0VN LA-9591P REV1 M/B
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Cover Sheet
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 0.4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
LA-9591P
Date: Friday, May 17, 2013 Sheet 1 of 58
A B C D E
A B C D E
Goliad 14 Block Diagram

Memory BUS (DDR3L) DDR3L-DIMM X2
eDP CONN eDP
1333/1600MHz
1 BANK 0, 1, 2, 3 1
PAGE 22
PAGE 18 19
DP
Mini-DP
PAGE 27 USB2.0[3] Camera
INTEL PAGE 22
Trough eDP Cable
DP
For MB/Dock Pericom DOCKED_LIO_EN
DDI2
DP Video Switch PI3VDP12412 SLGC55584A
IDT VMM2320
DP HASWELL ULT
VGA PAGE 27 NX3DV221 SW_USB2.0[0] USB POWER SHARE
PAGE 21 USB2.0[0]
USB20 Switch PAGE 33
PAGE 33
USB DOCKED DOCK _USB2.0[0] USB3.0/2.0+PS

USB3.0[2]
DOCKING HDMI Reduce Level DDI1 PAGE 33
HDMI CONN
PORT PAGE 23
ShifterPAGE 23 SW_USB2.0[5]
PAGE 34
USB2.0[5] PI3USB3102 SW_USB3.0[3] USB3.0/2.0
PAGE 33
USB3.0[3] USB3&2PAGE
Switch
2 2
32 DOCK _USB2.0[5]
DAI
DOCK_USB3.0[3]
DOCK_USB3.0[3] PAGE 6~17
SATA0 USB2.0[1]
DOCK_USB2.0[0] Card reader USB3.0/2.0
SD4.0 PCIE5_L0 USB3.0[1] PAGE 35
DOCK_USB2.0[5] O2 Micro OZ777FJ2LN
PAGE 30 PAGE 30 IO/B
HD Audio I/F
PCI Express BUS Free Fall sensor
SPI
SATA1
PCIE3 PCIE4 PCIE6_L0 USB2.0[7] PAGE 25
Intel Clarkville WLAN+BT/ Full Mini Card Near Field PAGE 20

Discrete TPM INT.Speaker
I218LM 60GHz WWAN+mSATA AT97SC3204 W25Q64CVSSIQ SATA Conn HDA Codec Communications con
PAGE 29 PAGE 26
PAGE 28 PAGE 31 PAGE 31 PAGE 25 ALC3226
3 64M 4K sector Vol bottom SW 3
USB2.0[2] USB2.0[6] PAGE 26
LAN SWITCH SATA3 W25Q32BVSSIQ Combo Jack PAGE 40
LPC
PI3L720 Touch Screen

PAGE 28
32M 4K sector PAGE 7 IO/B CPU XDP Port
Conn DAI PAGE 9
PAGE 22 To Docking side
Transformer Smart Card TDA8034HN USH Trough eDP Cable Automatic Power
PAGE 35 BCM5882 SMSC SIO
Switch (APS) PAGE 9
RFID ECE5048 Dig. MIC
Fingerprint PAGE 36 PAGE 22 WiFi ON/OFF
RJ45 FP_USB USB2.0[4]
PAGE 35
CONN PAGE 35
IO/B
Trough eDP Cable
PAGE 29 USH board DC/DC Interface
SMSC KBC
BC BUS PAGE 39
FAN CONN MEC5075
PAGE 37 PAGE 37
4
Power On/Off 4
KB and TP CONN SW & LED PAGE 40

PAGE 38
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Block diagram
LA-9591P
A B C D E
5 4 3 2 1
POWER STATES
Signal SLP SLP SLP SLP ALWAYS M SUS RUN CLOCKS PCIE USB3.0 SATA DESTINATION
State S3# S4# S5# A# PLANE PLANE PLANE PLANE
USB3.0 1 JUSB3-->IO-->Right
D S0 (Full ON) / M0 HIGH HIGH HIGH HIGH ON ON ON ON ON D
USB3.0 2 JUSB1-->Rear left
S3 (Suspend to RAM) / M3 LOW HIGH HIGH HIGH ON ON ON OFF OFF
PCIE 1 USB3.0 3 JUSB2-->Rear Right//DOCK
S4 (Suspend to DISK) / M3 LOW LOW HIGH HIGH ON ON OFF OFF OFF
PCIE 2
S5 (SOFT OFF) / M3 LOW LOW LOW HIGH ON ON OFF OFF OFF
PCIE 3 LOM
S3 (Suspend to RAM) / M-OFF LOW HIGH HIGH LOW ON OFF ON OFF OFF
PCIE 4 WLAN (WiGi)
S4 (Suspend to DISK) / M-OFF LOW LOW HIGH LOW ON OFF OFF OFF OFF
PCIE 5 MMI (CARD READER)
S5 (SOFT OFF) / M-OFF LOW LOW LOW LOW ON OFF OFF OFF OFF
PCIE 6 SATA 3 WWAN(PP/mSATA)
SATA 2 NA
C
PM TABLE C
+5V_ALW +3.3V_SUS +5V_RUN +3.3V_M +3.3V_M SATA 1 HDD

+3.3V_ALW +1.35V_MEM +3.3V_RUN +1.05V_M +1.05V_M
+3.3V_ALW_PCH +0.675V_DDR_VTT (M-OFF) SATA 0 DOCK
power
plane +3.3V_RTC_LDO +1.05V_RUN
+VCC_CORE
USB PORT# DESTINATION
State 0 JUSB1 // E-Dock 1
1 IO/ JUSB3
S0 ON ON ON ON ON
2 WLAN + BT
B S3 ON ON OFF ON OFF HSW B
3 CAMERA
ULT
S5 S4/AC ON OFF OFF ON OFF
4 USH->SMART CARD
S5 S4/AC don't exist OFF OFF OFF OFF OFF
5 JUSB2 // E-Dock 2
need to update Power Status and
PM Table 6 WWAN
7 TOUCH
0 BIO
USH
1 NA
A A
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Port assignment
LA-9591P
5 4 3 2 1
5 4 3 2 1
A_ON
+1.05V_RUN +3.3V_RUN PWRSHARE_EN# ESATA_USB_PWR_EN#
TPS51212
(PU300) G471 G471
(U35) (U35)
DOCKED
D D
EN_INVPWR FDC654P
ADAPTER +1.05V_M
(Q2) +5V_USB_
+USB_PWR
TPS22966 CHG_PWR
MPHYP_PWR_EN
(U31)
+BL_PWR_SRC
SI3456
BATTERY +PWR_SRC
+1.05V_RUN_VMM +3.3V_RUN_VMM (Q125) +1.05V_MOD_PHY
ALWON
C TPS51225 C
+5V_ALW
CHARGER (PU100)
USB_SIDE_EN#
G471
MCARD_WWAN_PWREN
PCH_ALW_ON
AUX_EN_WOWL +3.3V_ALW (IO/B)
SIO_SLP_LAN#
RUN_ON
3.3V_HDD_EN
EN_LCDPWR
RUN_ON
RUN_ON
RUN_ON
RUN_ON
TPS22966 +USB_IO_PWR
SUS_ON
(U43)
A_ON
TPS51622 RT8207
(PU500) (PU11)
TPS22966 TPS22966 TPS22966 APL3512 TPS22966 TPS22966
(U45) (U3) (U22) (U9) (U46) (U18)
H_VR_EN
B B
+3.3V_ALW_PCH
SUS_ON
0.675V_DDR_VTT_ON
+VCC_CORE +1.35V_MEM +5V_RUN +3.3V_RUN

+1.05V_RUN
_AUDIO _AUDIO
+3.3V_M +3.3V_WLAN +3.3V_LAN +LCDVDD

+3.3V_RUN
3.3V_CAM_EN#
+5V_RUN
3.3V_TS_EN
+3.3V_mSATA
+0.675V_DDR_VTT +3.3V_SUS +3.3V_HDD LP2301ALT1G
_WWAN +5V_TSP
(Q1)
LP2301ALT1G
A +3.3V_CAM A
(Q3)
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Power rails
LA-9591P
5 4 3 2 1
5 4 3 2 1
2.2K
SMBUS Address [0x9a]
2.2K
+3.3V_ALW_PCH
AP2 MEM_SMBCLK 202
MEM_SMBDATA
2N7002
AH1 200 DIMMA
2N7002
1K
202
D
PCH D
+3.3V_ALW_PCH 200 DIMMB
1K
SML0CLK 0ohm LAN_SMBCLK 28
AN1
SML0DATA 0ohm LAN_SMBDATA 31 LOM
AK1
AH3 AU3 53
51 XDP
2.2K
SML1_SMBDATA
SML1_SMBCLK
+3.3V_ALW_PCH 10K
2.2K
0ohm NFC_SMBCLK
A5 B6 2.2K 0ohm NFC_SMBDATA NFC +3.3V_RUN
10K
3A 3A
2.2K +3.3V_ALW 4
6 G Sensor
B4 DOCK_SMB_CLK 127
1A
129 DOCKING
1A A3 DOCK_SMB_DAT
30
2.2K 32 WWAN
C C
+3.3V_ALW
2.2K
B5 LCD_SMBCLK
1B
A4 LCD_SMDATA
1B
2.2K
KBC 2.2K
+3.3V_ALW
100 ohm 7
1C A56 PBAT_SMBCLK
100 ohm 6 BATTERY
1C B59 PBAT_SMBDAT CONN
2.2K
+3.3V_SUS
2.2K
A50 M9
1E USH_SMBCLK
B53 L9 USH
1E USH_SMBDAT
B B
2.2K
+3.3V_ALW
2.2K
MEC 5075
2B A49 CARD_SMBCLK
2B B52 CARD_SMBDAT
10K
+3.3V_ALW
10K
B50 9
1G CHARGER_SMBCLK
A47 8 Charger
1G CHARGER_SMBDAT
2.2K
+3.3V_ALW
2.2K
2D B7 BAY_SMBDAT
A A
2D A7 BAY_SMBCLK
2.2K
+3.3V_ALW DELL CONFIDENTIAL/PROPRIETARY
2.2K
2A B48 GPU_SMBDAT PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
GPU_SMBCLK
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT SMbus Block diagram
2A B49 BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
LA-9591P
5 4 3 2 1
5 4 3 2 1
+RTC_CELL
1
330K_0402_1%
RC1 +3.3V_ALW_PCH
2
D 1 2 PCH_AZ_SDOUT D
@ RC3 1K_0402_5%
PCH_INTVRMEN
FLASH DESCRIPTOR SECURITY OVERRIDE

1
330K_0402_1%
LOW = ENABLE (DEFAULT)

@ RC2
HIGH = DISABLE
2
+3.3V_RUN
CC1
1 2 PCH_RTCX1_R 1 2 PCH_RTCX1 HDD_DET# 1 2
INTVRMEN - INTEGRATED SUS 1.05V VRM @ RC4 0_0402_5% 100K_0402_5% RC11
ENABLE
10M_0402_5%
18P_0402_50V8J
1
mCARD_PCIE_SATA# 1 2
High - Enable Internal VRs
RC5
10K_0402_5% RC12
Low - Enable External VRs
YC1 UC1E HASWELL_MCP_E
2
32.768KHZ_12.5PF_Q13FC135000040
CC2
1 2 PCH_RTCX2 AW5
AY5 RTCX1
1 2 18P_0402_50V8J INTRUDER# AU6 RTCX2 J5
PCH_INTVRMEN AV7 INTRUDER RTC SATA_RN0/PERN6_L3 H5 SATA_PRX_DKTX_N0_C <34>
RC7 1M_0402_5%
1 2 AV6 INTVRMEN SATA_RP0/PERP6_L3 B15 SATA_PRX_DKTX_P0_C <34>
SRTCRST#
+RTC_CELL
RC8 1 2 20K_0402_5% PCH_RTCRST# AU7 SRTCRST SATA_TN0/PETN6_L3 A15 SATA_PTX_DKRX_N0_C <34> DOCK
RC6 20K_0402_5% RTCRST SATA_TP0/PETP6_L3 SATA_PTX_DKRX_P0_C <34>
J8
C <9> PCH_RTCRST# SATA_RN1/PERN6_L2 SATA_PRX_DTX_N1_C <25> C
H8
1 2 1 2 SATA_RP1/PERP6_L2 A17 SATA_PRX_DTX_P1_C <25>
1 2 1 2 SATA_TN1/PETN6_L2 B17 SATA_PTX_DRX_N1_C <25> SATA HDD
SATA_TP1/PETP6_L2 SATA_PTX_DRX_P1_C <25>
PCH_AZ_BITCLK AW8 J6
@ @ PCH_AZ_SYNC AV11 HDA_BCLK/I2S0_SCLK SATA_RN2/PERN6_L1 H6
ME1 SHORT PADS~D CMOS1 SHORT PADS~D PCH_AZ_RST# AU8 HDA_SYNC/I2S0_SFRM SATA_RP2/PERP6_L1 B14
1 2 1 2 PCH_AZ_CODEC_SDIN0 AY10 HDA_RST/I2S_MCLK SATA_TN2/PETN6_L1 C15
1U_0402_6.3V6K <26> PCH_AZ_CODEC_SDIN0 AU12 HDA_SDI0/I2S0_RXD AUDIO SATA SATA_TP2/PETP6_L1
CC3 1U_0402_6.3V6K CC4
1 2 PCH_AZ_SDOUT AU11 HDA_SDI1/I2S1_RXD F5
CMOS place near DIMM <36> ME_FWP
RC9 1K_0402_5% AW10 HDA_SDO/I2S0_TXD SATA_RN3/PERN6_L0 E5 SATA_PRX_MSATATX_N3 <31>
AV10 HDA_DOCK_EN/I2S1_TXD SATA_RP3/PERP6_L0 C17 SATA_PRX_MSATATX_P3 <31>
AY8 HDA_DOCK_RST/I2S1_SFRM SATA_TN3/PETN6_L0 D17 SATA_PTX_MSATARX_N3 <31> WWAN mSATA
I2S1_SCLK SATA_TP3/PETP6_L0 SATA_PTX_MSATARX_P3 <31>
V1 MPCIE_RST#
CMOS_CLR1 CMOS setting SATA0GP/GPIO34 U1 HDD_DET#
MPCIE_RST# <12,31>
SATA1GP/GPIO35 V6 HDD_DET# <25>
Shunt Clear CMOS SATA2GP/GPIO36 AC1 PCH_GPIO36 <12>
PCH_JTAG_TRST# AU62 SATA3GP/GPIO37 MCARD_PCIE_SATA# <36>
Open Keep CMOS <9> PCH_JTAG_TRST#
PCH_JTAG_TCK AE62 PCH_TRST A12 SATA_IREF 2 1
<9> PCH_JTAG_TCK PCH_TCK SATA_IREF +PCH_ASATA3PLL
PCH_JTAG_TDI AD61 L11 @ RC14 0_0402_5%
<9> PCH_JTAG_TDI PCH_TDI RSVD PAD~D T1 @
PCH_JTAG_TDO AE61 K10
ME_CLR1 TPM setting <9> PCH_JTAG_TDO
PCH_JTAG_TMS AD62 PCH_TDO JTAG RSVD C12 SATA_COMP PAD~D T2 @
<9> PCH_JTAG_TMS PCH_TMS SATA_RCOMP
AL11 U3 SATA_ACT#
Shunt Clear ME RTC Registers @ T3 PAD~D
AC4 RSVD SATALED SATA_ACT# <40>
@ T4 PAD~D RSVD
AE63
Open Keep ME RTC Registers <9> PCH_JTAG_JTAGX
AV2 JTAGX
@ T5 PAD~D RSVD
+1.05V_M
B 5 OF 19 Rev1p2 B
1
0_0603_5%
@RC16
@ RC16
2
+1.05V_M_JTAG 2 1 PCH_JTAG_TDI SATA Impedance Compensation

RC17 51_0402_1%
RC18
2
2
1
1
PCH_JTAG_TDO
51_0402_1%
PCH_JTAG_TMS
HDA for Codec SATA_COMP 1
+PCH_ASATA3PLL
2
RC20 51_0402_1% 3.01K_0402_1% RC19
2 1 PCH_JTAG_JTAGX 1
PCH_AZ_SDOUT2
<26> PCH_AZ_CODEC_SDOUT
@ RC10 1K_0402_1% RC23 33_0402_5%
1 2 PCH_AZ_SYNC CAD note:
2 1 PCH_JTAG_TCK <26> PCH_AZ_CODEC_SYNC
RC24 33_0402_5%
@ RC22 51_0402_1% 1 2 PCH_AZ_RST# Place the resistor within 500 mils of the PCH. Avoid
<26> PCH_AZ_CODEC_RST#
RC25 33_0402_5% routing next to clock pins.
1 EMC@ 2 PCH_AZ_BITCLK
<26> PCH_AZ_CODEC_BITCLK
RC26 33_0402_5%
27P_0402_50V8J
1
@ CC5
2
Reserve for EMI

A A
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT CPU (1/12)
LA-9591P
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN
UC1G HASWELL_MCP_E
LPC_LAD0 AU14 AN2 PCH_SMB_ALERT#

<29,36,37> LPC_LAD0 LAD0 SMBALERT/GPIO11
LPC_LAD1 AW12 AP2 MEM_SMBCLK
<29,36,37> LPC_LAD1 LAD1 SMBCLK
2
LPC_LAD2 AY12 LPC AH1 MEM_SMBDATA
<29,36,37> LPC_LAD2 LAD2 SMBDATA
LPC_LAD3 AW11 AL2
<29,36,37> LPC_LAD3 LAD3 SML0ALERT/GPIO60
LPC_LFRAME# AV12 SMBUS AN1 SML0CLK MEM_SMBCLK 6 1
<29,36,37> LPC_LFRAME# LFRAME SML0CLK DDR_XDP_WAN_SMBCLK <18,19,25,31,9>
AK1 SML0DATA
SML0DATA AU4 QC1A
SML1ALERT/PCHHOT/GPIO73 PCH_GPIO73 <12>
5
AU3 SML1_SMBCLK DMN66D0LDW-7_SOT363-6
SML1CLK/GPIO75 AH3 SML1_SMBDATA SML1_SMBCLK <37>
SML1DATA/GPIO74 SML1_SMBDATA <37>
PCH_SPI_CLK AA3 MEM_SMBDATA 3 4
SPI_CLK DDR_XDP_WAN_SMBDAT <18,19,25,31,9>
PCH_SPI_CS0# Y7 AF2 PCH_CL_CLK1
SPI_CS0 CL_CLK PCH_CL_CLK1 <31>
D PCH_SPI_CS1# Y4 AD2 PCH_CL_DATA1 QC1B D
SPI_CS1 CL_DATA PCH_CL_DATA1 <31>
AC2 SPI C-LINK AF4 PCH_CL_RST1# DMN66D0LDW-7_SOT363-6
PCH_SPI_DO AA2 SPI_CS2 CL_RST PCH_CL_RST1# <31>
PCH_SPI_DIN AA4 SPI_MOSI
PCH_SPI_DO2 Y6 SPI_MISO +3.3V_ALW_PCH
PCH_SPI_DO3 AF1 SPI_IO2
SPI_IO3 PCH_SMB_ALERT# 2 1
10K_0402_5% RC27
SML0CLK 2 1 MEM_SMBCLK 2 1
@ RC35 0_0402_5% LAN_SMBCLK <28> 2.2K_0402_5% RC28
+3.3V_M 7 OF 19 Rev1p2 SML0DATA 2 1 MEM_SMBDATA 2 1
@ RC33 0_0402_5% LAN_SMBDATA <28>
2.2K_0402_5% RC30
1 2 PCH_SPI_DO2 2 1 SML1_SMBCLK 1 2
R1 1K_0402_5% @ RC31 0_0402_5% NFC_SMBCLK <20> 2.2K_0402_5% RC36
1 2 PCH_SPI_DO3 2 1 SML1_SMBDATA 1 2
@ RC29 0_0402_5% NFC_SMBDATA <20>
R2 1K_0402_5% 2.2K_0402_5% RC37
SML0CLK 2 1
+3.3V_M 1K_0402_5% RC38
SML0DATA 2 1
1@ C5 1K_0402_5% RC39
1 2
64Mb Flash ROM 0.1U_0402_25V6
U1 1@
PCH_SPI_CS0# 1@ R3 1 2 0_0402_5% SPI_PCH_CS0#_R 1 8
PCH_SPI_DIN 1@ R4 1 2 33_0402_5% SPI_DIN64 2 /CS VCC 7 SPI_PCH_DO3_64 1@ R5 1 2 33_0402_5% PCH_SPI_DO3
PCH_SPI_DO2 1@ R6 1 2 33_0402_5% SPI_PCH_DO2_64 3 DO(IO1) /HOLD(IO3) 6 SPI_CLK64 1@ R7 1 2 33_0402_5% PCH_SPI_CLK
4 /WP(IO2) CLK 5 SPI_DO64 1@ R9 1 2 33_0402_5% PCH_SPI_DO
SPI_WP#_SEL 2 1 GND DI(IO0)
<36> SPI_WP#_SEL
@ R8 0_0402_5% W25Q64FVSSIQ_SO8
+3.3V_M
TAA Config JTAA1
+3.3V_M
PCH_SPI_DO 2@ R11 1 2 33_0402_5% TAA_DO64 1 2

4@ C6 PCH_SPI_DO 5@ R12 1 2 33_0402_5% TAA_DO32 3 1 2 4
1 2 5 3 4 6
C
PCH_SPI_CLK 2@ R13 1 2 33_0402_5% TAA_CLK64 7 5 6 8 TAA_DO3_64 2@ R43 1 2 33_0402_5% PCH_SPI_DO3 C
32Mb Flash ROM 0.1U_0402_25V6 PCH_SPI_CLK 5@ R18 1 2 33_0402_5% TAA_CLK32 9 7 8 10 TAA_DO3_32 5@ R48 1 2 33_0402_5% PCH_SPI_DO3
U2 4@ PCH_SPI_CS0# 2@ R10 1 2 0_0402_5% TAA_CS0#_R 11 9 10 12 TAA_DO2_64 2@ R58 1 2 33_0402_5% PCH_SPI_DO2
PCH_SPI_CS1# 4@ R14 1 2 0_0402_5% SPI_PCH_CS1#_R 1 8 PCH_SPI_CS1# 5@ R17 1 2 0_0402_5% TAA_CS1#_R 13 11 12 14 TAA_DO2_32 5@ R59 1 2 33_0402_5% PCH_SPI_DO2
PCH_SPI_DIN 4@ R15 1 2 33_0402_5% SPI_DIN32 2 /CS VCC 7 SPI_PCH_DO3_32 4@ R16 1 2 33_0402_5% PCH_SPI_DO3 15 13 14 16
PCH_SPI_DO2 4@ R19 1 2 33_0402_5% SPI_PCH_DO2_32 3 DO/IO1 /HOLD/IO3 6 SPI_CLK32 4@ R20 1 2 33_0402_5% PCH_SPI_CLK PCH_SPI_DIN 2@ R22 1 2 33_0402_5% TAA_DIN64 17 15 16 18
4 /WP/IO2 CLK 5 SPI_DO32 4@ R21 1 2 33_0402_5% PCH_SPI_DO PCH_SPI_DIN 5@ R41 1 2 33_0402_5% TAA_DIN32 19 17 18 20
SPI_WP#_SEL 2 1 GND DI/IO0 19 20
@ R23 0_0402_5% W25Q32FVSSIQ_SO8 21 22
23 G G 24
G G
ACES_50185-02041-001
CONN@
SPI_CLK32 SPI_CLK64 CC7

1 2 XTAL24_IN_R 2 1
@ RC40 0_0402_5%
2
2
33_0402_5%
33_0402_5%
18P_0402_50V8J
2
@ R45
@ R57
1M_0402_5%
3
4
HASWELL_MCP_E
RC44
UC1F
YC2
24MHZ_12PF_X3G024000DC1H
1
1
2
33P_0402_50V8J
33P_0402_50V8J
C43 A25 XTAL24_IN CC6

CLKOUT_PCIE_N0 XTAL24_IN
2
2
@ C85
@ C76
C42 B25 XTAL24_OUT 2 1

RC57 1 2 10K_0402_5% PCIECLK_REQ0# U2 CLKOUT_PCIE_P0 XTAL24_OUT
+3.3V_RUN PCIECLKRQ0/GPIO18 K21 PAD~D T6 @ 18P_0402_50V8J
1
B41 RSVD M21

CLKOUT_PCIE_N1 RSVD PAD~D T7 @
A41 C26 CLK_BIASREF
Y5 CLKOUT_PCIE_P1 DIFFCLK_BIASREF
<29> PCH_TPM_LPC_EN RC56 1 2 10K_0402_5% PCIECLKRQ1/GPIO19 C35 MCP_TESTLOW1
+3.3V_RUN TESTLOW_C35
B C41 CLOCK C34 MCP_TESTLOW2 B
<28> CLK_PCIE_LAN# B42 CLKOUT_PCIE_N2 TESTLOW_C34 AK8 MCP_TESTLOW3
10/100/1G LAN ---> <28> CLK_PCIE_LAN AD1 CLKOUT_PCIE_P2 SIGNALS TESTLOW_AK8 AL8 MCP_TESTLOW4
<12,28> LANCLK_REQ# PCIECLKRQ2/GPIO20 TESTLOW_AL8
B38 AN15 PCI_CLK_LPC_0 0_0402_5% 1 2 RC65 @ PCI_CLK_LPC
<31> CLK_PCIE_MINI2# CLKOUT_PCIE_N3 CLKOUT_LPC_0
PCI_CLK_LPC_0 2 1 C37 AP15 PCI_CLK_LPC_1 22_0402_5% 1 2 RC64 EMC_3@
12P_0402_50V8J @ CC15
WLAN (Mini Card 2)---> <31> CLK_PCIE_MINI2
N1 CLKOUT_PCIE_P3 CLKOUT_LPC_1 22_0402_5% 1 2 RC66 EMC@ CLK_PCI_DOCK <34>
<12,31> MINI2CLK_REQ# PCIECLKRQ3/GPIO21 CLK_PCI_LPDEBUG <37>
B35
A39 CLKOUT_ITPXDP_N A35
PCI_CLK_LPC_1 2 1 <30> CLK_PCIE_MMI# B39 CLKOUT_PCIE_N4 CLKOUT_ITPXDP_P
12P_0402_50V8J @ CC14
MMI ---> <30> CLK_PCIE_MMI U5 CLKOUT_PCIE_P4
<30> MMICLK_REQ# PCIECLKRQ4/GPIO22
+3.3V_RUN RC55 1 2 10K_0402_5%
B37
<31> CLK_PCIE_MINI1# A37 CLKOUT_PCIE_N5
Reserve for EMI WWAN (Mini Card 1)---> <31> CLK_PCIE_MINI1 T2 CLKOUT_PCIE_P5
<12,31> MINI1CLK_REQ# PCIECLKRQ5/GPIO23
6 OF 19 Rev1p2
+PCH_VCCACLKPLL
CLK_BIASREF 1 2
3.01K_0402_1% RC45
PCI_CLK_LPC RC58 1 EMC@ 2 22_0402_5%
CLK_PCI_TPM_TCM <29> MCP_TESTLOW1 1 2
RC61 1 EMC@ 2 22_0402_5% 10K_0402_5% RC46
CLK_PCI_5048 <36> MCP_TESTLOW2 1 2
RC63 1 EMC@ 2 22_0402_5% 10K_0402_5% RC47
CLK_PCI_MEC <37> MCP_TESTLOW3 1 2
10K_0402_5% RC50
MCP_TESTLOW4 1 2
10K_0402_5% RC52
A A
LA-9591P
5 4 3 2 1
5 4 3 2 1
D UC1C HASWELL_MCP_E UC1D HASWELL_MCP_E D

<19> DDR_B_D[0..63]
<18> DDR_A_D[0..63]
DDR_A_D0 AH63 AU37 M_CLK_DDR#0
SA_DQ0 SA_CLK#0 M_CLK_DDR#0 <18>
DDR_A_D1 AH62 AV37 M_CLK_DDR0 DDR_B_D0 AY31 AM38 M_CLK_DDR#2
SA_DQ1 SA_CLK0 M_CLK_DDR0 <18> SB_DQ0 SB_CK#0 M_CLK_DDR#2 <19>
DDR_A_D2 AK63 AW36 M_CLK_DDR#1 DDR_B_D1 AW31 AN38 M_CLK_DDR2
SA_DQ2 SA_CLK#1 M_CLK_DDR#1 <18> SB_DQ1 SB_CK0 M_CLK_DDR2 <19>
DDR_A_D3 AK62 AY36 M_CLK_DDR1 DDR_B_D2 AY29 AK38 M_CLK_DDR#3
SA_DQ3 SA_CLK1 M_CLK_DDR1 <18> SB_DQ2 SB_CK#1 M_CLK_DDR#3 <19>
DDR_A_D4 AH61 DDR_B_D3 AW29 AL38 M_CLK_DDR3
SA_DQ4 SB_DQ3 SB_CK1 M_CLK_DDR3 <19>
DDR_A_D5 AH60 AU43 DDR_CKE0_DIMMA DDR_B_D4 AV31
SA_DQ5 SA_CKE0 DDR_CKE0_DIMMA <18> SB_DQ4
DDR_A_D6 AK61 AW43 DDR_CKE1_DIMMA DDR_B_D5 AU31 AY49 DDR_CKE2_DIMMB
SA_DQ6 SA_CKE1 DDR_CKE1_DIMMA <18> SB_DQ5 SB_CKE0 DDR_CKE2_DIMMB <19>
DDR_A_D7 AK60 AY42 DDR_B_D6 AV29 AU50 DDR_CKE3_DIMMB
SA_DQ7 SA_CKE2 SB_DQ6 SB_CKE1 DDR_CKE3_DIMMB <19>
DDR_A_D8 AM63 AY43 DDR_B_D7 AU29 AW49
DDR_A_D9 AM62 SA_DQ8 SA_CKE3 DDR_B_D8 AY27 SB_DQ7 SB_CKE2 AV50
DDR_A_D10 AP63 SA_DQ9 AP33 DDR_CS0_DIMMA# DDR_B_D9 AW27 SB_DQ8 SB_CKE3
SA_DQ10 SA_CS#0 DDR_CS0_DIMMA# <18> SB_DQ9
DDR_A_D11 AP62 AR32 DDR_CS1_DIMMA# DDR_B_D10 AY25 AM32 DDR_CS2_DIMMB#
SA_DQ11 SA_CS#1 DDR_CS1_DIMMA# <18> SB_DQ10 SB_CS#0 DDR_CS2_DIMMB# <19>
DDR_A_D12 AM61 DDR_B_D11 AW25 AK32 DDR_CS3_DIMMB#
SA_DQ12 SB_DQ11 SB_CS#1 DDR_CS3_DIMMB# <19>
DDR_A_D13 AM60 AP32 DDR_B_D12 AV27
DDR_A_D14 AP61 SA_DQ13 SA_ODT0 DDR_B_D13 AU27 SB_DQ12 AL32
DDR_A_D15 AP60 SA_DQ14 AY34 DDR_A_RAS# DDR_B_D14 AV25 SB_DQ13 SB_ODT0
SA_DQ15 SA_RAS DDR_A_RAS# <18> SB_DQ14
DDR_A_D16 AP58 AW34 DDR_A_WE# DDR_B_D15 AU25 AM35 DDR_B_RAS#
SA_DQ16 SA_WE DDR_A_WE# <18> SB_DQ15 SB_RAS DDR_B_RAS# <19>
DDR_A_D17 AR58 AU34 DDR_A_CAS# DDR_B_D16 AM29 AK35 DDR_B_WE#
SA_DQ17 SA_CAS DDR_A_CAS# <18> SB_DQ16 SB_WE DDR_B_WE# <19>
DDR_A_D18 AM57 DDR_B_D17 AK29 AM33 DDR_B_CAS#
SA_DQ18 SB_DQ17 SB_CAS DDR_B_CAS# <19>
DDR_A_D19 AK57 AU35 DDR_A_BS0 DDR_B_D18 AL28
SA_DQ19 SA_BA0 DDR_A_BS0 <18> SB_DQ18
DDR_A_D20 AL58 AV35 DDR_A_BS1 DDR_B_D19 AK28 AL35 DDR_B_BS0
SA_DQ20 SA_BA1 DDR_A_BS1 <18> SB_DQ19 SB_BA0 DDR_B_BS0 <19>
DDR_A_D21 AK58 AY41 DDR_A_BS2 DDR_B_D20 AR29 AM36 DDR_B_BS1
SA_DQ21 SA_BA2 DDR_A_BS2 <18> SB_DQ20 SB_BA1 DDR_B_BS1 <19>
DDR_A_D22 AR57 DDR_B_D21 AN29 AU49 DDR_B_BS2
SA_DQ22 DDR_A_MA[0..15] <18> SB_DQ21 SB_BA2 DDR_B_BS2 <19>
DDR_A_D23 AN57 AU36 DDR_A_MA0 DDR_B_D22 AR28
SA_DQ23 SA_MA0 SB_DQ22 DDR_B_MA[0..15] <19>
DDR_A_D24 AP55 AY37 DDR_A_MA1 DDR_B_D23 AP28 AP40 DDR_B_MA0
DDR_A_D25 AR55 SA_DQ24 SA_MA1 AR38 DDR_A_MA2 DDR_B_D24 AN26 SB_DQ23 SB_MA0 AR40 DDR_B_MA1
DDR_A_D26 AM54 SA_DQ25 SA_MA2 AP36 DDR_A_MA3 DDR_B_D25 AR26 SB_DQ24 SB_MA1 AP42 DDR_B_MA2
DDR_A_D27 AK54 SA_DQ26 SA_MA3 AU39 DDR_A_MA4 DDR_B_D26 AR25 SB_DQ25 SB_MA2 AR42 DDR_B_MA3
DDR_A_D28 AL55 SA_DQ27 SA_MA4 AR36 DDR_A_MA5 DDR_B_D27 AP25 SB_DQ26 SB_MA3 AR45 DDR_B_MA4
C DDR_A_D29 AK55 SA_DQ28 SA_MA5 AV40 DDR_A_MA6 DDR_B_D28 AK26 SB_DQ27 SB_MA4 AP45 DDR_B_MA5 C
DDR_A_D30 AR54 SA_DQ29 SA_MA6 AW39 DDR_A_MA7 DDR_B_D29 AM26 SB_DQ28 SB_MA5 AW46 DDR_B_MA6
DDR_A_D31 AN54 SA_DQ30 SA_MA7 AY39 DDR_A_MA8 DDR_B_D30 AK25 SB_DQ29 SB_MA6 AY46 DDR_B_MA7
DDR_A_D32 AY58 SA_DQ31 SA_MA8 AU40 DDR_A_MA9 DDR_B_D31 AL25 SB_DQ30 SB_MA7 AY47 DDR_B_MA8
DDR_A_D33 AW58 SA_DQ32 SA_MA9 AP35 DDR_A_MA10 DDR_B_D32 AY23 SB_DQ31 SB_MA8 AU46 DDR_B_MA9
DDR_A_D34 AY56 SA_DQ33 SA_MA10 AW41 DDR_A_MA11 DDR_B_D33 AW23 SB_DQ32 SB_MA9 AK36 DDR_B_MA10
DDR_A_D35 AW56 SA_DQ34 DDR CHANNEL A SA_MA11 AU41 DDR_A_MA12 DDR_B_D34 AY21 SB_DQ33 DDR CHANNEL B SB_MA10 AV47 DDR_B_MA11
DDR_A_D36 AV58 SA_DQ35 SA_MA12 AR35 DDR_A_MA13 DDR_B_D35 AW21 SB_DQ34 SB_MA11 AU47 DDR_B_MA12
DDR_A_D37 AU58 SA_DQ36 SA_MA13 AV42 DDR_A_MA14 DDR_B_D36 AV23 SB_DQ35 SB_MA12 AK33 DDR_B_MA13
DDR_A_D38 AV56 SA_DQ37 SA_MA14 AU42 DDR_A_MA15 DDR_B_D37 AU23 SB_DQ36 SB_MA13 AR46 DDR_B_MA14
DDR_A_D39 AU56 SA_DQ38 SA_MA15 DDR_B_D38 AV21 SB_DQ37 SB_MA14 AP46 DDR_B_MA15
SA_DQ39 DDR_A_DQS#[0..7] <18> SB_DQ38 SB_MA15
DDR_A_D40 AY54 AJ61 DDR_A_DQS#0 DDR_B_D39 AU21
SA_DQ40 SA_DQSN0 SB_DQ39 DDR_B_DQS#[0..7] <19>
DDR_A_D41 AW54 AN62 DDR_A_DQS#1 DDR_B_D40 AY19 AW30 DDR_B_DQS#0
DDR_A_D42 AY52 SA_DQ41 SA_DQSN1 AM58 DDR_A_DQS#2 DDR_B_D41 AW19 SB_DQ40 SB_DQSN0 AV26 DDR_B_DQS#1
DDR_A_D43 AW52 SA_DQ42 SA_DQSN2 AM55 DDR_A_DQS#3 DDR_B_D42 AY17 SB_DQ41 SB_DQSN1 AN28 DDR_B_DQS#2
DDR_A_D44 AV54 SA_DQ43 SA_DQSN3 AV57 DDR_A_DQS#4 DDR_B_D43 AW17 SB_DQ42 SB_DQSN2 AN25 DDR_B_DQS#3
DDR_A_D45 AU54 SA_DQ44 SA_DQSN4 AV53 DDR_A_DQS#5 DDR_B_D44 AV19 SB_DQ43 SB_DQSN3 AW22 DDR_B_DQS#4
DDR_A_D46 AV52 SA_DQ45 SA_DQSN5 AL43 DDR_A_DQS#6 DDR_B_D45 AU19 SB_DQ44 SB_DQSN4 AV18 DDR_B_DQS#5
DDR_A_D47 AU52 SA_DQ46 SA_DQSN6 AL48 DDR_A_DQS#7 DDR_B_D46 AV17 SB_DQ45 SB_DQSN5 AN21 DDR_B_DQS#6
DDR_A_D48 AK40 SA_DQ47 SA_DQSN7 DDR_B_D47 AU17 SB_DQ46 SB_DQSN6 AN18 DDR_B_DQS#7
SA_DQ48 DDR_A_DQS[0..7] <18> SB_DQ47 SB_DQSN7
DDR_A_D49 AK42 AJ62 DDR_A_DQS0 DDR_B_D48 AR21
SA_DQ49 SA_DQSP0 SB_DQ48 DDR_B_DQS[0..7] <19>
DDR_A_D50 AM43 AN61 DDR_A_DQS1 DDR_B_D49 AR22 AV30 DDR_B_DQS0
DDR_A_D51 AM45 SA_DQ50 SA_DQSP1 AN58 DDR_A_DQS2 DDR_B_D50 AL21 SB_DQ49 SB_DQSP0 AW26 DDR_B_DQS1
DDR_A_D52 AK45 SA_DQ51 SA_DQSP2 AN55 DDR_A_DQS3 DDR_B_D51 AM22 SB_DQ50 SB_DQSP1 AM28 DDR_B_DQS2
DDR_A_D53 AK43 SA_DQ52 SA_DQSP3 AW57 DDR_A_DQS4 DDR_B_D52 AN22 SB_DQ51 SB_DQSP2 AM25 DDR_B_DQS3
DDR_A_D54 AM40 SA_DQ53 SA_DQSP4 AW53 DDR_A_DQS5 DDR_B_D53 AP21 SB_DQ52 SB_DQSP3 AV22 DDR_B_DQS4
DDR_A_D55 AM42 SA_DQ54 SA_DQSP5 AL42 DDR_A_DQS6 DDR_B_D54 AK21 SB_DQ53 SB_DQSP4 AW18 DDR_B_DQS5
DDR_A_D56 AM46 SA_DQ55 SA_DQSP6 AL49 DDR_A_DQS7 DDR_B_D55 AK22 SB_DQ54 SB_DQSP5 AM21 DDR_B_DQS6
DDR_A_D57 AK46 SA_DQ56 SA_DQSP7 DDR_B_D56 AN20 SB_DQ55 SB_DQSP6 AM18 DDR_B_DQS7
DDR_A_D58 AM49 SA_DQ57 AP49 DDR_B_D57 AR20 SB_DQ56 SB_DQSP7
SA_DQ58 SM_VREF_CA +SM_VREF_CA SB_DQ57
DDR_A_D59 AK49 AR51 +SM_VREF_DQ0 DDR_B_D58 AK18
DDR_A_D60 AM48 SA_DQ59 SM_VREF_DQ0 AP51 DDR_B_D59 AL18 SB_DQ58
B SA_DQ60 SM_VREF_DQ1 +SM_VREF_DQ1 SB_DQ59 B
DDR_A_D61 AK48 DDR_B_D60 AK20
DDR_A_D62 AM51 SA_DQ61 DDR_B_D61 AM20 SB_DQ60
DDR_A_D63 AK51 SA_DQ62 DDR_B_D62 AR18 SB_DQ61
SA_DQ63 DDR_B_D63 AP18 SB_DQ62
SB_DQ63
3 OF 19 Rev1p2 4 OF 19 Rev1p2
A A
LA-9591P
5 4 3 2 1
5 4 3 2 1
@ RC72 1 2 0_0402_5% +RTC_CELL

+3.3V_RUN
@ CC9
+3.3V_RUN
330K_0402_1%
1 2
2
@ CC8
RC73
1 2 0.1U_0402_25V6
5
+3.3V_ALW_PCH 0.1U_0402_25V6
5
XDP_DBRESET# 1
1
1 2 ME_SUS_PWR_ACK B 4 SYS_RESET# PCH_PLTRST# 1
P
RC70 10K_0402_5% 2 1 ME_RESET# 2 O B 4 PCH_PLTRST#_EC DSWODVREN
A O PCH_PLTRST#_EC <29,31,36,37>
G
1 2 SUSACK# @ RC76 8.2K_0402_5% @ UC2 2
A
G
RC98 10K_0402_5% 74AHC1G09GW_TSSOP5 UC3 +3.3V_ALW2
330K_0402_1%
1 2 SUS_STAT#/LPCPD# TC7SH08FU_SSOP5~D @ CC82
2
@ RC78
@ RC74 10K_0402_5% 1 2
0.1U_0402_25V6
+PCH_VCCDSW3_3
D D
1
5
RP12 PCH_DPWROK 1 2 PCH_RSMRST#_R
4 5 PCH_BATLOW# @ RC79 0_0402_5% SIO_SLP_A# 1
P
3 6 AC_PRESENT B 4 PM_APWROK_R
2 7 PCH_PCIE_WAKE# ME_SUS_PWR_ACK_R 1 2 SUSACK#_R PM_APWROK 2 O
<37> PM_APWROK A
G
1 8 @ RC82 0_0402_5% UC7
PCH_AUDIO_EN <12>
TC7SH08FU_SSOP5~D DSWODVREN - ON DIE DSW VR ENABLE
3
10K_8P4R_5% RESET_OUT# 1 2 SYS_PWROK_R
@ RC84 0_0402_5% HIGH = ENABLED (DEFAULT)
1 2
@ RC144 0_0402_5%
1 2 PCH_RSMRST#_R
LOW = DISABLED
RC136 10K_0402_5%
UC1H HASWELL_MCP_E
SYSTEM POWER MANAGEMENT

@ RC86 1 2 0_0402_5% SUSACK#_R AK2 AW7 DSWODVREN
<36> SUSACK# SUSACK DSWVRMEN
SYS_RESET# AC3 AV5 PCH_DPWROK JAPS1
SYS_RESET DPWROK PCH_DPWROK <36>
@ RC87 1 2 0_0402_5% SYS_PWROK_R AG2 AJ5 PCH_PCIE_WAKE# +3.3V_ALW_PCH 1
+3.3V_RUN <36> SYS_PWROK SYS_PWROK WAKE PCH_PCIE_WAKE# <37> 1
@ RC88 1 2 0_0402_5% PCH_PWROK AY7 SIO_SLP_S3# 2
<15,37> RESET_OUT# PCH_PWROK 2
@ RC139 1 2 0_0402_5% PM_APWROK_R AB5 +PCH_VCCDSW3_3
3
<20> PLTRST_NFC# APWROK 3
@ RC89 1 2 0_0402_5% PCH_PLTRST# AG7 V5 CLKRUN# SIO_SLP_S5# 4
<29> PLTRST_USH# PLTRST CLKRUN/GPIO32 CLKRUN# <12,29,36,37> 4
1 2 ME_RESET# @ RC90 1 2 0_0402_5% AG4 SUS_STAT#/LPCPD# SIO_SLP_S4# 5
<30> PLTRST_MMI# SUS_STAT/GPIO61 5
@ RC81 8.2K_0402_5% @ RC91 1 2 0_0402_5% AE6 SUSCLK SIO_SLP_A# 6
<28> PLTRST_LAN# SUSCLK/GPIO62 T10 PAD~D @ 6
@ RC92 1 2 0_0402_5% AP5 SIO_SLP_S5# +PCH_VCCDSW3_3
7
<21> PLTRST_VMM2320# SLP_S5/GPIO63 SIO_SLP_S5# <37> 7
@ RC93 1 2 0_0402_5% PCH_RSMRST#_R AW6 8
<38> PCH_RSMRST#_Q RSMRST T11 PAD~D @ 8
@ RC94 1 2 0_0402_5% ME_SUS_PWR_ACK_R AV4 PCH_RTCRST# 9
<37> ME_SUS_PWR_ACK SUSWARN/SUSPWRDNACK/GPIO30 T12 PAD~D @ <6> PCH_RTCRST# 9
SIO_PWRBTN# AL7 AJ6 SIO_SLP_S4# 10
<37,9> SIO_PWRBTN# PWRBTN SLP_S4 SIO_SLP_S4# <36,39,43> 10
AC_PRESENT AJ8 AT4 SIO_SLP_S3# 11
<37> AC_PRESENT ACPRESENT/GPIO31 SLP_S3 SIO_SLP_S3# <36,39,43> <37,40> POWER_SW#_MB 11
PCH_BATLOW# AN4 AL5 SIO_SLP_A# 12
SIO_SLP_S0# AF3 BATLOW/GPIO72 SLP_A AP4 SIO_SLP_SUS# SIO_SLP_A# <36,39,44> SYS_RESET# 13 12
<37> SIO_SLP_S0# SIO_SLP_WLAN# AM5 SLP_S0 SLP_SUS AJ7 SIO_SLP_LAN# SIO_SLP_SUS# <36> 14 13
<36> SIO_SLP_WLAN# SLP_WLAN/GPIO29 SLP_LAN SIO_SLP_LAN# <28,36> SIO_SLP_S0# 15 14
16 15
17 16
18 17
8 OF 19 Rev1p2 19 18
20 GND
+3.3V_RUN GND
CONN@
C CC41 XDP@ ACES_50506-01841-P01 C
2 1
UC6 XDP@
0.1U_0402_25V6 +1.05V_RUN
14 +1.05V_RUN +1.05V_RUN
VCC
0.1U_0402_25V6
0.1U_0402_25V6
1 2 TDO_XDP 2 3 CPU_XDP_TDO
<6> PCH_JTAG_TDO 1A 1B
RC95 0_0402_5% JXDP1
1
@ CC10
@ CC11
XDP@ 1 2
RUNPWROK 1 CPU_XDP_PREQ# 3 GND0 GND1 4 CFG17
1OE OBSFN_A0 OBSFN_C0 CFG17 <13>
CPU_XDP_PRDY# 5 6 CFG16 CFG16 <13>
2
1 2 TDI_XDP 1 2 TDI_XDP_R 5 6 CPU_XDP_TDI 7 OBSFN_A1 OBSFN_C1 8
<6> PCH_JTAG_TDI 2A 2B GND2 GND3
RC96 0_0402_5% RC103 0_0402_5% <13> CFG0 CFG0 9 10 CFG8 CFG8 <13>
XDP@ XDP@ CFG1 11 OBSDATA_A0 OBSDATA_C0 12 CFG9
<13> CFG1 OBSDATA_A1 OBSDATA_C1 CFG9 <13>
RUNPWROK 4 13 14
2OE CFG2 15 GND4 GND5 16 CFG10
<13> CFG2 OBSDATA_A2 OBSDATA_C2 CFG10 <13>
1 2 TMS_XDP 9 8 CPU_XDP_TMS <13> CFG3 CFG3 17 18 CFG11 CFG11 <13>
<6> PCH_JTAG_TMS 3A 3B OBSDATA_A3 OBSDATA_C3
RC101 0_0402_5% 19 20
XDP@
Place near JXDP1 XDP_OBS0_R 21 GND6 GND7 22 CFG19
OBSFN_B0 OBSFN_D0 CFG19 <13>
RUNPWROK 10 XDP_OBS1_R 23 24 CFG18 CFG18 <13>
3OE 25 OBSFN_B1 OBSFN_D1 26
TRST#_XDP 12 11 CPU_XDP_TRST# CFG4 27 GND8 GND9 28 CFG12
4A 4B <13> CFG4 OBSDATA_B0 OBSDATA_D0 CFG12 <13>
<13> CFG5 CFG5 29 30 CFG13 CFG13 <13>
31 OBSDATA_B1 OBSDATA_D1 32
RC5 need to close to JCPU1 GND10 GND11
RUNPWROK 13 7 <13> CFG6 CFG6 33 34 CFG14 CFG14 <13>
<36,37> RUNPWROK 4OE GND OBSDATA_B2 OBSDATA_D2
RC105 1 2 1K_0402_5% <13> CFG7 CFG7 35 36 CFG15 CFG15 <13>
<15> H_VCCST_PWRGD OBSDATA_B3 OBSDATA_D3
15 XDP@ 37 38
GND PAD H_CPUPWRGD @ RC106 1 2 1K_0402_5% H_VCCST_PWRGD_XDP 39 GND12 GND13 40
@ RC107 1 2 0_0402_5% CFD_PWRBTN#_XDP 41 PWRGOOD/HOOK0 ITPCLK/HOOK4 42
<37,9> SIO_PWRBTN# HOOK1 ITPCLK#/HOOK5
43 44
74CBTLV3126BQ_DHVQFN14_2P5X3 <15> CPU_PWR_DEBUG# VCC_OBS_AB VCC_OBS_CD
@ RC108 1 2 0_0402_5% CPU_PWR_DEBUG#_R 45 46 XDP_RST#_R 2 1 PCH_PLTRST#_EC
SYS_PWROK @ RC110 1 2 0_0402_5% SYS_PWROK_XDP 47 HOOK2 RESET#/HOOK6 48 XDP_DBRESET# RC109 1K_0402_5%
reference Shark Bay ULT Validation Customer Debug Port HOOK3 DBR#/HOOK7
49 50 XDP@
Implementation Requirement Rev 1.0 @ RC111 1 2 0_0402_5% DDR_XDP_SMBDAT_R1 51 GND14 GND15 52 TDO_XDP
<18,19,25,31,7> DDR_XDP_WAN_SMBDAT SDA TD0
2 1 CPU_XDP_TRST# @ RC112 1 2 0_0402_5% DDR_XDP_SMBCLK_R1 53 54 TRST#_XDP
<6> PCH_JTAG_TRST# <18,19,25,31,7> DDR_XDP_WAN_SMBCLK SCL TRST#
@ 0_0402_5% RC135 @ RC142 1 2 0_0402_5% PCH_JTAG_TCK_R 55 56 TDI_XDP
<6> PCH_JTAG_TCK TCK1 TDI
CPU_XDP_TCLK 57 58 TMS_XDP
+1.05V_VCCST 2 1 CPU_XDP_TCLK 59 TCK0 TMS 60 CFG3_R 1 2 CFG3
<6> PCH_JTAG_JTAGX GND16 GND17
@ 0_0402_5% RC97 RC99 1K_0402_5%
1 2 H_CATERR# SAMTE_BSH-030-01-L-D-A CONN@ XDP@ +1.05V_RUN
@ RC113 49.9_0402_1% 2 1 TDO_XDP
1 2 H_PROCHOT# 0_0402_5% RC123 @
B RC114 62_0402_5% TDO_XDP 2 1 B
PCH_JTAG_TDO 2 1 TDI_XDP_R +3.3V_ALW_PCH 51_0402_1% @ RC280
0_0402_5% RC104 @
2
1K_0402_5%
PCH_JTAG_TCK 2 1 CPU_XDP_TCLK
RC102
XDP@
0_0402_5% RC124 @
H_PROCHOT#
Place near JXDP1.48
0.1U_0402_25V6
XDP_DBRESET#
1
1
@
CC68 XDP@
CC149 SYS_PWROK_XDP
0.1U_0402_25V6
22P_0402_50V8J
2
2
1
@ CC48
UC1B HASWELL_MCP_E
2
EMI request add CPU_DETECT# D61
<36> CPU_DETECT# H_CATERR# K61 PROC_DETECT
MISC
PECI_EC N62 CATERR J62 CPU_XDP_PRDY#
<37> PECI_EC PECI PRDY K62 CPU_XDP_PREQ#
Place near JXDP1.47 +3.3V_RUN
PREQ E60 CPU_XDP_TCLK
JTAG
PROC_TCK E61 CPU_XDP_TMS
H_CPUPWRGD 1 2 H_PROCHOT#_R K63 PROC_TMS E59 CPU_XDP_TRST# XDP_DBRESET# 2 1 RC116
<37,46,47,48> H_PROCHOT# PROCHOT PROC_TRST
RC117 56_0402_5% THERMAL F63 CPU_XDP_TDI 1K_0402_5%
PROC_TDI
10K_0402_5%
F62 CPU_XDP_TDO
1
PROC_TDO +1.05V_RUN
RC115
H_CPUPWRGD C61
PROCPWRGD CPU_XDP_TMS 2 1 @ RC118
PWR
J60 XDP_OBS0_R 51_0402_1%
BPM#0 H60 XDP_OBS1_R CPU_XDP_TDI 2 1 @ RC119
2
BPM#1 H61 XDP_OBS2_R PAD~D T122 @ 51_0402_1%

BPM#2 H62 XDP_OBS3_R PAD~D T126 @ CPU_XDP_PREQ# 2 1 @ RC120
SM_RCOMP0 AU60 BPM#3 K59 XDP_OBS4_R PAD~D T129 @ 51_0402_1%
SM_RCOMP1 AV60 SM_RCOMP0 DDR3 BPM#4 H63 XDP_OBS5_R PAD~D T130 @ CPU_XDP_TDO 2 1 RC122
SM_RCOMP2 AU61 SM_RCOMP1 BPM#5 K60 XDP_OBS6_R PAD~D T131 @ 51_0402_1%
CAD Note: AV15 SM_RCOMP2 BPM#6 J61 XDP_OBS7_R PAD~D T132 @
<18> DDR3_DRAMRST#_CPU SM_DRAMRST BPM#7
Avoid stub in the PWRGD path <18> DDR_PG_CTRL AV61
SM_PG_CNTL1 CPU_XDP_TCLK 2 1 RC127
while placing resistors RC115 51_0402_1%
2 OF 19 Rev1p2 CPU_XDP_TRST# 2 1 @ RC131
A 51_0402_1% A
DDR3 COMPENSATION SIGNALS H_CPUPWRGD
200_0402_1% 2 1 RC125 SM_RCOMP0

1
@
121_0402_1% 2 1 RC129 SM_RCOMP1 CC90
100P_0402_50V8J
2
100_0402_1% 2 1 RC133 SM_RCOMP2

CAD Note: ESD request add Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
Trace width=12~15 mil, Spcing=20 mils
Max trace length= 500 mil
LA-9591P
5 4 3 2 1
5 4 3 2 1
D D
UC1A HASWELL_MCP_E
DDI1_LANE_N0 C54 C45 EDP_CPU_LANE_N0

<23> DDI1_LANE_N0 DDI1_LANE_P0 C55 DDI1_TXN0 EDP_TXN0 B46 EDP_CPU_LANE_P0 EDP_CPU_LANE_N0 <22> COMPENSATION PU FOR eDP
<23> DDI1_LANE_P0 DDI1_LANE_N1 B58 DDI1_TXP0 EDP_TXP0 A47 EDP_CPU_LANE_N1 EDP_CPU_LANE_P0 <22>
<23> DDI1_LANE_N1 DDI1_LANE_P1 C58 DDI1_TXN1 EDP_TXN1 B47 EDP_CPU_LANE_P1 EDP_CPU_LANE_N1 <22>
<23> DDI1_LANE_P1 DDI1_LANE_N2 B55 DDI1_TXP1 EDP_TXP1 EDP_CPU_LANE_P1 <22> +VCCIOA_OUT
<23> DDI1_LANE_N2 DDI1_LANE_P2 A55 DDI1_TXN2 C47
<23> DDI1_LANE_P2 DDI1_LANE_N3 A57 DDI1_TXP2 EDP_TXN2 C46 EDP_COMP 2 1
<23> DDI1_LANE_N3 DDI1_LANE_P3 B57 DDI1_TXN3 EDP_TXP2 A49 24.9_0402_1% RC134
<23> DDI1_LANE_P3 DDI1_TXP3 DDI EDP EDP_TXN3 B49
DDI2_LANE_N0 C51 EDP_TXP3
<27> DDI2_LANE_N0
DDI2_LANE_P0 C50 DDI2_TXN0 A45 EDP_CPU_AUX#
CAD Note:Trace width=20 mils ,Spacing=25mil,
<27> DDI2_LANE_P0 DDI2_TXP0 EDP_AUXN EDP_CPU_AUX# <22>
<27> DDI2_LANE_N1
DDI2_LANE_N1 C53
DDI2_TXN1 EDP_AUXP
B45 EDP_CPU_AUX
EDP_CPU_AUX <22>
Max length=100 mils.
DDI2_LANE_P1 B54
+3.3V_RUN <27> DDI2_LANE_P1 DDI2_LANE_N2 C49 DDI2_TXP1 D20 EDP_COMP
<27> DDI2_LANE_N2 DDI2_LANE_P2 B50 DDI2_TXN2 EDP_RCOMP A43
1 2 CONTACTLESS_DET# <27> DDI2_LANE_P2 DDI2_LANE_N3 A53 DDI2_TXP2 EDP_DISP_UTIL
RC137 10K_0402_5% <27> DDI2_LANE_N3 DDI2_LANE_P3 B53 DDI2_TXN3
1 2 DGPU_PWROK <27> DDI2_LANE_P3 DDI2_TXP3
C RC138 10K_0402_5% C
1 2 TOUCHPAD_INTR#
RC140 10K_0402_5%
1 2 PIRQC# 1 OF 19 Rev1p2
RC146 10K_0402_5%
1 2 PIRQD#
RC148 10K_0402_5%
+3.3V_RUN
1 2 ENVDD_PCH UC1I HASWELL_MCP_E RP3

@ RC152 100K_0402_5% CPU_DPB_CTRLCLK 1 8
2 1 CODEC_IRQ CPU_DPB_CTRLDAT 2 7
@ RC154 1K_0402_5% CPU_DPC_CTRLCLK 3 6
CPU_DPC_CTRLDAT 4 5
EDP_BIA_PWM B8 B9 CPU_DPB_CTRLCLK
<22> EDP_BIA_PWM A9 EDP_BKLCTL DDPB_CTRLCLK C9 CPU_DPB_CTRLCLK <23>
PANEL_BKLEN CPU_DPB_CTRLDAT 2.2K_0804_8P4R_5%
<22> PANEL_BKLEN C6 EDP_BKLEN DDPB_CTRLDATA D9 CPU_DPB_CTRLDAT <23>
ENVDD_PCH eDP SIDEBAND CPU_DPC_CTRLCLK
<22,36> ENVDD_PCH EDP_VDDEN DDPC_CTRLCLK D11 CPU_DPC_CTRLDAT CPU_DPC_CTRLCLK <27> CPU_DPB_AUX# 2 1
DDPC_CTRLDATA CPU_DPC_CTRLDAT <27>
100K_0402_5% RC147
CPU_DPC_AUX# 2 1
1 2 PIRQC# U6 100K_0402_5% RC149
<29> CONTACTLESS_DET# DGPU_PWROK P4 PIRQA/GPIO77 C5 CPU_DPB_AUX#
@ R495 0_0402_5%
PIRQC# N4 PIRQB/GPIO78 DISPLAY DDPB_AUXN B6 CPU_DPC_AUX#
<25> HDD_FALL_INT PIRQD# N2 PIRQC/GPIO79 DDPC_AUXN B5 CPU_DPB_AUX CPU_DPC_AUX# <27>
1 2 PIRQD# AD4 PIRQD/GPIO80 DDPB_AUXP A6 CPU_DPC_AUX
@ T13 PAD~D PME DDPC_AUXP CPU_DPC_AUX <27>
R494 0_0402_5% GPIO DPC_HPD 2 1
TOUCHPAD_INTR# U7 100K_0402_5% RC151
L1 GPIO55 CPU_DPB_AUX 2 1
<12> TOUCH_RST_N_GYRO_INT1 L3 GPIO52 C8 DPB_HPD 100K_0402_5% RC153
R5 GPIO54 DDPB_HPD A8 DPC_HPD DPB_HPD <23> CPU_DPC_AUX 2 1
CODEC_IRQ L4 GPIO51 DDPC_HPD D6 DPC_HPD <27> 100K_0402_5% RC155
B GPIO53 EDP_HPD EDP_CPU_HPD <22> B
100K_0402_5%
1
RC158
9 OF 19 Rev1p2
2
A A
LA-9591P
5 4 3 2 1
5 4 3 2 1
D D
UC1K HASWELL_MCP_E
PCIE_PRX_MMITX_N5 F10 AN8 USBP0-

<30> PCIE_PRX_MMITX_N5 PCIE_PRX_MMITX_P5 E10 PERN5_L0 USB2N0 AM8 USBP0+ USBP0- <33> -----> Ext Port 1 and DOCK2 (USB SW)
<30> PCIE_PRX_MMITX_P5 PERP5_L0 USB2P0 USBP0+ <33>
MMI --> PCIE_PTX_MMIRX_N5 C23 AR7 USBP1-
<30> PCIE_PTX_MMIRX_N5 PCIE_PTX_MMIRX_P5 C22 PETN5_L0 USB2N1 AT7 USBP1+ USBP1- <35>
<30> PCIE_PTX_MMIRX_P5 PETP5_L0 USB2P1 USBP1+ <35> ----->Ext Port 2 IO/B
F8 AR8 USBP2-
E8 PERN5_L1 USB2N2 AP8 USBP2+ USBP2- <31>
PERP5_L1 USB2P2 USBP2+ <31> ----->WLAN/BT
B23 AR10 USBP3-
A23 PETN5_L1 USB2N3 AT10 USBP3- <22>
USBP3+
PETP5_L1 USB2P3 USBP3+ <22> ----->Camera
H10 AM15 USBP4-
G10 PERN5_L2 USB2N4 AL15 USBP4- <29>
USBP4+
PERP5_L2 USB2P4 USBP4+ <29> ----->USH
B21 AM13 USBP5-
C21 PETN5_L2 USB2N5 AN13 USBP5+ USBP5- <32>
C PETP5_L2 USB2P5 USBP5+ <32> ----->Ext Port 3 and DOCK1(USB SW) C
E6 AP11 USBP6-
F6 PERN5_L3 USB2N6 AN11 USBP6+ USBP6- <31>
PERP5_L3 USB2P6 USBP6+ <31> ----->WWAN
B22 AR13 USBP7-
A21 PETN5_L3 USB2N7 AP13 USBP7+ USBP7- <22>
PETP5_L3 USB2P7 USBP7+ <22> ----->Touch
PCIE_PRX_GLANTX_N3 G11
<28> PCIE_PRX_GLANTX_N3 PCIE_PRX_GLANTX_P3 F11 PERN3 G20
<28> PCIE_PRX_GLANTX_P3 PERP3 USB3RN1 H20 USB3RN1 <35>
10/100/1G LAN ---> PCIE_PTX_GLANRX_N3 C29 USB3RP1 USB3RP1 <35>
<28> PCIE_PTX_GLANRX_N3 PCIE_PTX_GLANRX_P3 B30 PETN3 PCIe USB C33 ----->Ext USB3 Port 3 IO/B
<28> PCIE_PTX_GLANRX_P3 PETP3 USB3TN1 B34 USB3TN1 <35>
PCIE_PRX_WLANTX_N4 F13 USB3TP1 USB3TP1 <35>
<31> PCIE_PRX_WLANTX_N4 PCIE_PRX_WLANTX_P4 G13 PERN4 E18
<31> PCIE_PRX_WLANTX_P4 PERP4 USB3RN2 F18 USB3RN2 <33>
WLAN (Mini Card 2)---> PCIE_PTX_WLANRX_N4 B29 USB3RP2 USB3RP2 <33>
<31> PCIE_PTX_WLANRX_N4 PCIE_PTX_WLANRX_P4 A29 PETN4 B33 ----->Ext USB3 Port 1
<31> PCIE_PTX_WLANRX_P4 PETP4 USB3TN2 A33 USB3TN2 <33>
G17 USB3TP2 USB3TP2 <33>
<32> USB3RN3 F17 PERN1/USB3RN3
<32> USB3RP3 PERP1/USB3RP3
Ext USB Port 2 <---- C30
<32> USB3TN3 C31 PETN1/USB3TN3 AJ10 USBRBIAS
<32> USB3TP3 PETP1/USB3TP3 USBRBIAS AJ11
F15 USBRBIAS AN10 PAD~D T14@
G15 PERN2/USB3RN4 RSVD AM10 PAD~D T15@
PERP2/USB3RP4 RSVD
B31
A31 PETN2/USB3TN4
PETP2/USB3TP4 AL3 USB_OC0# USBRBIAS
OC0/GPIO40 AT1 USB_OC1# USB_OC0# <33>
OC1/GPIO41 USB_OC1# <35>
22.6_0402_1%
B AH2 USB_OC2# B
OC2/GPIO42 USB_OC2# <12,33>
1
@ T16 PAD~D E15 AV3 USB_OC3#
RSVD OC3/GPIO43
RC159
@ T17 PAD~D E13
RC161 1 2 3.01K_0402_1% PCH_PCIE_RCOMP A27 RSVD
+PCH_AUSB3PLL PCIE_RCOMP
@ RC163 1 2 0_0402_5% PCH_PCIE_IREF B27
PCIE_IREF
2
11 OF 19 Rev1p2
CAD NOTE:
Route single-end 50-ohms and max 500-mils length.
Avoid routing next to clock pins or under stitching capacitors.
Recommended minimum spacing to other signal traces is 15
mils.
+3.3V_ALW_PCH
USB_OC0# 1 2
10K_0402_5% RC160
USB_OC1# 1 2
10K_0402_5% RC165
USB_OC3# 1 2
10K_0402_5% RC166
A A
LA-9591P
5 4 3 2 1
5 4 3 2 1
+PCH_VCCDSW3_3
D H_THERMTRIP#_R +1.05V_VCCST D
2 1 EC_WAKE# 1 2 H_THERMTRIP# 2 1
LAN_WAKE# <28,37>
RC206 10K_0402_5% 0_0402_5% RC177 @ 1K_0402_5% R24
1
@
CC91
100P_0402_50V8J +3.3V_RUN
2
+3.3V_RUN
FFS_INT2 2 1
UC1J HASWELL_MCP_E 100K_0402_5% RC183
2 1 MPHYP_PWR_EN USH_DET# 2 1
RC170 100K_0402_5% ESD request add 10K_0402_5% RC282
2 1 SIO_EXT_SCI# CPPE# 2 1
RC199 100K_0402_5% 100K_0402_5% RC185
PCH_AUDIO_EN P1 D60 H_THERMTRIP#_R @ 0_0402_5%2 1 RC172 CAM_MIC_CBL_DET#2 1
<9> PCH_AUDIO_EN AU2 BMBUSY/GPIO76 THERMTRIP V4 H_THERMTRIP# <37>
SIO_EXT_WAKE# SIO_RCIN# 10K_0402_5% RC193
<36> SIO_EXT_WAKE# AM7 GPIO8 RCIN/GPIO82 T4 IRQ_SERIRQ SIO_RCIN# <37> TPM_ID0 2 1
+PCH_VCCDSW3_3
<28> PM_LANPHY_ENABLE PCH_GPIO15 AD6 LAN_PHY_PWR_CTRL/GPIO12 CPU/ SERIRQ AW15 PCH_OPI_COMP IRQ_SERIRQ <29,36,37>
10K_0402_5% RC284
Y1 GPIO15 MISC PCH_OPI_RCOMP AF20 @ T18 PAD~D TPM_ID1 2 1
2 1 PM_LANPHY_ENABLE <28> LAN_RST# PCH_GPIO17 T3 GPIO16 RSVD AB21 @ T19 PAD~D 20K_0402_5% RC285
RC197 10K_0402_5% @ T139 PAD~D AD5 GPIO17 RSVD SLP_ME_CSW_DEV#2 1
EC_WAKE# AN5 GPIO24 10K_0402_5% RC289
<37> EC_WAKE# AD7 GPIO27 PCH_GPIO83 2 1
<20> PCH_NFC_RST NFC_IRQ AN3 GPIO28 10K_0402_5% RC290
<20> NFC_IRQ GPIO26 R6 PCH_GPIO83 PCH_GPIO84 2 1
MEDIACARD_RST# AG6 GSPI0_CS/GPIO83 L6 PCH_GPIO84 10K_0402_5% RC291
+3.3V_ALW_PCH <30> MEDIACARD_RST# AP1 GPIO56 GSPI0_CLK/GPIO84 N6 PCH_GPIO85 3.3V_TS_EN 2 1
<30> MEDIACARD_PWREN SLATE_MODE_R AL4 GPIO57 GSPI0_MISO/GPIO85 L8 BBS_BIT 10K_0402_5% RC294
AT5 GPIO58 GSPI0_MOSI/GPIO86 R7 PCH_GPIO87
2 1 <20> NFC_DET# AK4 GPIO59 GSPI1_CS/GPIO87 L5
MEDIACARD_PWREN PCH_GPIO44 3.3V_TP_EN RP4
RC175 10K_0402_5% AB6 GPIO44 GPIO GSPI1_CLK/GPIO88 N7 PCH_GPIO85 5 4
2 1 PCH_GPIO44 <30> MEDIACARD_IRQ# PCH_GPIO48 U4 GPIO47 GSPI1_MISO/GPIO89 K2 3.3V_TS_EN <22> 3.3V_TP_EN 6 3
C @ T140 PAD~D PCH_GPIO49 Y3 GPIO48 GSPI_MOSI/GPIO90 J1 CPPE# 3.3V_HDD_EN <28> TOUCH_PANEL_INTR# 7 2 C
RC200 10K_0402_5%
2 1 MEDIACARD_RST# @ T141 PAD~D P3 GPIO49 UART0_RXD/GPIO91 K3 CPUSB# CPPE# <31> 8 1
<22> TOUCH_PANEL_INTR# MPHYP_PWR_EN Y2 GPIO50 UART0_TXD/GPIO92 J2 CPUSB# <31> <10> TOUCH_RST_N_GYRO_INT1
RC171 10K_0402_5%
1 2 <39> MPHYP_PWR_EN AT3 HSIOPC/GPIO71 UART0_RTS/GPIO93 G1
PCH_GPIO46 KB_DET# LPIO 10K_8P4R_5%
<38> KB_DET# PCH_GPIO14 AH4 GPIO13 UART0_CTS/GPIO94 K4
RC230 10K_0402_5%
@ T138 PAD~D 3.3V_CAM_EN# AM4 GPIO14 UART1_RXD/GPIO0 G2 FFS_INT2 RP5
<22> 3.3V_CAM_EN# AG5 GPIO25 UART1_TXD/GPIO1 J3 FFS_INT2 <25> 5 4
SIO_EXT_SMI# LCD_CBL_DET# 3.3V_HDD_EN
<37> SIO_EXT_SMI# AG3 GPIO45 UART1_RST/GPIO2 J4 LCD_CBL_DET# <22> 6 3
RP13 PCH_GPIO46 LCD_CBL_DET#
4 5 SIO_EXT_SMI# GPIO46 UART1_CTS/GPIO3 F2 I2C0_SDA CPUSB# 7 2
3 6 SLATE_MODE_R PCH_GPIO9 AM3 I2C0_SDA/GPIO4 F3 I2C0_SCL 8 1
2 7 MEDIACARD_IRQ# PCH_GPIO10 AM2 GPIO9 I2C0_SCL/GPIO5 G4 I2C1_SDA_TCH_PAD <28,7> LANCLK_REQ#
@ T137 PAD~D GPIO10 I2C1_SDA/GPIO6
1 8 P2 F1 I2C1_SCL_TCH_PAD 10K_8P4R_5%
USB_OC2# <11,33> <31> mSATA_DEVSLP C4 DEVSLP0/GPIO33 I2C1_SCL/GPIO7 E3 USH_DET#
L2 SDIO_POWER_EN/GPIO70 SDIO_CLK/GPIO64 F4 CAM_MIC_CBL_DET# USH_DET# <29>
10K_8P4R_5% RP6
<25> HDD_DEVSLP SIO_EXT_SCI# N5 DEVSLP1/GPIO38 SDIO_CMD/GPIO65 D3 PCH_GPIO66 CAM_MIC_CBL_DET# <22> SIO_RCIN# 5 4
<37> SIO_EXT_SCI# SPKR V2 DEVSLP2/GPIO39 SDIO_D0/GPIO66 E4 TPM_ID0 6 3
RP14
4 5 <26> SPKR SPKR/GPIO81 SDIO_D1/GPIO67 C3 <31,7> MINI1CLK_REQ# 7 2
PCH_GPIO9 TPM_ID1
3 6 SDIO_D2/GPIO68 E2 <31,7> MINI2CLK_REQ# 8 1
SIO_EXT_WAKE# SLP_ME_CSW_DEV#
2 7 SDIO_D3/GPIO69 SLP_ME_CSW_DEV# <36>
<31,6> MPCIE_RST#
KB_DET#
1 8 10 OF 19 Rev1p2 10K_8P4R_5%
PCH_GPIO73 <7>
10K_8P4R_5%
RP7
I2C0_SDA 1 8
2 1 3.3V_CAM_EN# I2C1_SDA_TCH_PAD @ RC174 2 1 0_0402_5% I2C0_SCL 2 7
I2C1_SDA_VMM <21> I2C1_SDA_TCH_PAD 3 6
RC211 100K_0402_5%
2 1 NFC_IRQ I2C1_SCL_TCH_PAD @ RC176 2 1 0_0402_5% I2C1_SCL_TCH_PAD 4 5
I2C1_SCL_VMM <21>
RC210 100K_0402_5%
2 1 MPHYP_PWR_EN 2.2K_0804_8P4R_5%
@ RC169 I2C1_SDA_TCH_PAD <38>
10K_0402_5%
+3.3V_RUN +3.3V_RUN I2C1_SCL_TCH_PAD <38>

RP11
B IRQ_SERIRQ 5 4 B
6 3
<29,36,37,9> CLKRUN#
1
1
1K_0402_5%
10K_0402_5%
7 2
<6> PCH_GPIO36
@
@ RC283
PCH_GPIO87 8 1
RC218
+3.3V_ALW_PCH +3.3V_RUN 10K_8P4R_5%

2
PCH_OPI_COMP 1 2
1
1
1K_0402_5%
1K_0402_5%
PCH_GPIO66 BBS_BIT 49.9_0402_1% RC168
RC190
@ RC222
PCH_GPIO83 1 2
1
1K_0402_5%
100_0402_5% 7@ RC292
1
@ RC288
1K_0402_5%
@ RC287
2
PCH_GPIO15 SPKR
2
TOP-BLOCK SWAP OVERRIDE BOOT BIOS STRAP BIT BBS TLS CONFIDENTIALITY NO REBOOT STRAP
HIGH depop RC288 HIGH LPC HIGH ENABLE HIGH ENABLE
LOW pop RC288 (DEFAULT) LOW(DEFAULT) SPI LOW(DEFAULT) DISABLE LOW(DEFAULT) DISABLE
A A
LA-9591P
5 4 3 2 1
5 4 3 2 1
D D
CFG STRAPS for CPU

UC1S HASWELL_MCP_E CFG0
1
1K_0402_1%
@ RC232
CFG0 AC60 AV63 PAD~D T20@
<9> CFG0 AC62 CFG0 RSVD_TP AU63 PAD~D T21@
CFG1
<9> CFG1
2
AC63 CFG1 RSVD_TP
<9> CFG2 AA63 CFG2
<9> CFG3 CFG4 AA60 CFG3 C63 PAD~D T22@
<9> CFG4 Y62 CFG4 RSVD_TP C62 PAD~D T23@
<9> CFG5 Y61 CFG5 RSVD_TP B43 PAD~D T24@
<9> CFG6 Y60 CFG6 RSVD
<9> CFG7
CFG8 V62 CFG7 A51 PAD~D T25@ EAR-STALL/NOT STALL RESET SEQUENCE AFTER PCU PLL IS LOCKE
<9> CFG8 CFG9 V61 CFG8 RSVD_TP B51 PAD~D T26@
<9> CFG9 CFG10 V60 CFG9 RSVD_TP
<9> CFG10 U60 CFG10 L60 PAD~D T27@ 1:(Default) Normal Operation; No stall
<9> CFG11 T63 CFG11 RESERVED RSVD_TP CFG0
<9> CFG12 T62 CFG12 N60 PAD~D T28@ 0:Lane Reversed
<9> CFG13 T61 CFG13 RSVD
C <9> CFG14 T60 CFG14 W23 PAD~D T29@ C
<9> CFG15 CFG15 RSVD Y22 PAD~D T30@
AA62 RSVD AY15 PROC_OPI_RCOMP
<9> CFG16 U63 CFG16 PROC_OPI_RCOMP CFG1
<9> CFG18 AA61 CFG18 AV62 PAD~D T31 @
<9> CFG17 U62 CFG17 RSVD D58 PAD~D T32 @
<9> CFG19 CFG19 RSVD
1
1K_0402_1%
@ RC233
CFG_RCOMP V63 P22
CFG_RCOMP VSS N21
@ T33 PAD~D A5 VSS
RSVD P20 PAD~D T34 @
2
@ T35 PAD~D E1 RSVD R20 PAD~D T36 @
@ T37 PAD~D D1 RSVD RSVD
@ T38 PAD~D J20 RSVD
@ T39 PAD~D H18 RSVD
TDI_IREF B12 RSVD
TD_IREF
19 OF 19 Rev1p2 PCH/PCH LESS MODE SELECTION
1:(Default) Normal Operation
CFG1
0:Lane Reversed
2 1 CFG_RCOMP
RC235 49.9_0402_1%
1 2 TDI_IREF PROC_OPI_RCOMP 1 2
RC236 8.2K_0402_1% 49.9_0402_1% RC237
B B
CFG10 CFG9 CFG8 CFG4
1
1
1
1K_0402_1%
1K_0402_1%
@ RC240
1K_0402_1%
1K_0402_1%
@ RC239
@ RC241
RC238
2
2
2
SAFE MODE BOOT NO SVID PROTOCOL CAPABLE VR CONNECTED ALLOW THE USE OF NOA ON LOCKED UNITS Display Port Presence Strap
1: POWER FEATURES ACTIVATED DURING 1: VRS support SVID protocol are present 1: Enable(Default): Noa will be disable in
1 : Disabled; No Physical Display Port
RESET 0:No VR support SVID is present locked units and enable in un-locked
CFG10 CFG9 CFG8 CFG4 attached to Embedded Display Port
0: POWER FEATURES (ESPECIALLY CLOCK The chip will not generate(OR Respond to) units
0: Enable Noa will be available pegardless of
0 : Enabled; An external Display Port device is
GATINE ARE NOT ACTIVATED SVID activity the locking of the unit
connected to the Embedded Display Port
A A
LA-9591P
5 4 3 2 1
5 4 3 2 1
D D
2
1 1
0_0402_5% RC254 @
UC1Q HASWELL_MCP_E
DC_TEST_AY2_AW2 AY2 A3 DC_TEST_A3_B3

DC_TEST_AY3_AW3 AY3 DAISY_CHAIN_NCTF_AY2 DAISY_CHAIN_NCTF_A3 A4 DC_TEST_A4
DC_TEST_AY60 AY60 DAISY_CHAIN_NCTF_AY3 DAISY_CHAIN_NCTF_A4
DC_TEST_AY61_AW61 AY61 DAISY_CHAIN_NCTF_AY60 A60 DC_TEST_A60
DC_TEST_AY62_AW62 AY62 DAISY_CHAIN_NCTF_AY61 DAISY_CHAIN_NCTF_A60 A61 DC_TEST_A61_B61
TP_DC_TEST_B2 B2 DAISY_CHAIN_NCTF_AY62 DAISY_CHAIN_NCTF_A61 A62 DC_TEST_A62 2
2 1
DC_TEST_A3_B3 B3 DAISY_CHAIN_NCTF_B2 DAISY_CHAIN_NCTF_A62 AV1 DC_TEST_AV1 0_0402_5% @ RC266
DC_TEST_A61_B61 B61 DAISY_CHAIN_NCTF_B3 DAISY_CHAIN_NCTF_AV1 AW1 DC_TEST_AW1 2 1
B62 DAISY_CHAIN_NCTF_B61 DAISY_CHAIN_NCTF_AW1 AW2 DC_TEST_AY2_AW2 0_0402_5% @ RC268
DC_TEST_B62_B63 B63 DAISY_CHAIN_NCTF_B62 DAISY_CHAIN_NCTF_AW2 AW3 DC_TEST_AY3_AW3
C1 DAISY_CHAIN_NCTF_B63 DAISY_CHAIN_NCTF_AW3 AW61 DC_TEST_AY61_AW61
4
DC_TEST_C1_C2 C2 DAISY_CHAIN_NCTF_C1 DAISY_CHAIN_NCTF_AW61 AW62 DC_TEST_AY62_AW62
DAISY_CHAIN_NCTF_C2 DAISY_CHAIN_NCTF_AW62 AW63 DC_TEST_AW63
17 OF 19 Rev1p2DAISY_CHAIN_NCTF_AW63
C C
3
2 1
0_0402_5% RC269 @
Package Daisy Chain:

1.B2-PKG-C1-PCB-C2-PKG-B3-PCB-A3-PKG-A4
2.A62-PKG-A61-PCB-B61-PKG-B62-PCB-B63-PKG-A60
3.AY60-PKG-AW61-PCB-AY61-PKG-AW62-PCB-AY62-PKG-AW63
4.AW1-PKG-AW3-PCB-AY3-PKG-AW2-PCB-AY2-PKG-AV1
UC1R HASWELL_MCP_E
N23 @
RSVD_N23 PAD~D T48
RSVD R23 RSVD_R23 @
PAD~D T49
RSVD_AT2 AT2 RSVD T23 RSVD_T23 @
@T50 PAD~D PAD~D T51
RSVD_AU44 AU44 RSVD RSVD U10 RSVD_U10 @
@T54 PAD~D RSVD_AV44 AV44 RSVD RSVD
B @T55 PAD~D RSVD_D15 D15 RSVD B
RSVD AL1 @
RSVD_AL1 PAD~D T56
RSVD AM11 RSVD_AM11 @
PAD~D T57
RSVD_F22 F22 RSVD AP7 RSVD_AP7 @
H22 RSVD RSVD AU10 @
@T60 PAD~D RSVD_H22 RSVD_AU10 PAD~D T61
RSVD_J21 J21 RSVD RSVD AU15 RSVD_AU15 @
RSVD RSVD AW14 @
RSVD_AW14 PAD~D T64
RSVD AY14 RSVD_AY14 @
PAD~D T65
RSVD
18 OF 19 Rev1p2
A A
LA-9591P
5 4 3 2 1
5 4 3 2 1
+VCC_CORE
ESD test request +1.35V_MEM
EMC@CC57
EMC@ CC57
1 2
+1.05V_RUN +1.05V_RUN +VCCIO_OUT +1.35V_MEM
VDDQ DECOUPLING
22U_0603_6.3V6M
2 1
1
150_0402_1%
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1 2 VCCST_PWRGD @RC242
@ RC242 0_0603_5%
RC253
D @ CC22 D
1
@ CC81
@ CC52
@ CC17
@ CC20
100P_0402_50V8J
CC12
CC13
CC16
CC18
CC19
CC21
RESISTOR STUFFING OPTIONS ARE
2
PROVIDED FOR TESTING PURPOSES
CPU_PWR_DEBUG#
1
10K_0402_5%
@ RC258
2
+1.05V_VCCST +3.3V_RUN
1
+VCC_CORE
10K_0402_5%
@ RC255
10K_0402_5%
HASWELL_MCP_E
@ RC259
UC1L
@ T66 PAD~D L59 C36

+1.35V_MEM @ T67 PAD~D J58 RSVD VCC C40
2
RSVD VCC C44
H_VR_EN 2 1 H_VR_READY AH26 VCC C48
10K_0402_5% RC256 AJ31 VDDQ VCC C52
AJ33 VDDQ VCC C56
AJ37 VDDQ VCC E23
+1.05V_VCCST AN33 VDDQ VCC E25
AP43 VDDQ VCC E27
AR48 VDDQ VCC E29
VDDQ VCC
2
+3.3V_ALW
1K_0402_5%
AY35 E31
VDDQ VCC
RC243
C AY40 E33 C
UC4 AY44 VDDQ VCC E35
1 5 1 2 AY50 VDDQ VCC E37
NC VCC @ CC24 0.1U_0402_25V6 VDDQ VCC E39
1
2 1 2 F59 VCC E41
<37,9> RESET_OUT# A +VCC_CORE VCC VCC
@ RC263 0_0402_5% 4 H_VCCST_PWRGD @ T68 N58 E43
3 Y PAD~D AC58 RSVD VCC E45
GND @ T69 PAD~D RSVD VCC E47
74AUP1G07GW_TSSOP5 VCCSENSE E63 VCC E49
AB23 VCC_SENSE VCC E51
@ T70 PAD~D RSVD VCC
A59 E53
+VCCIO_OUT VCCIO_OUT VCC
E20 E55
+VCCIOA_OUT VCCIOA_OUT VCC
@ T71 PAD~D AD23 E57
AA23 RSVD VCC F24
@ T72 PAD~D RSVD VCC
@ T73 PAD~D AE59 F28
RSVD VCC F32
+1.05V_VCCST H_CPU_SVIDALRT# L62 VCC F36
SVID ALERT <46> VIDSCLK
VIDSCLK
VIDSOUT
N63
L63
VIDALERT
VIDSCLK
VIDSOUT
VCC
VCC
VCC
F40
F44
@ RC245 1 2 0_0402_5% VCCST_PWRGD B59 HSW ULT POWER F48
<9> H_VCCST_PWRGD VCCST_PWRGD VCC
1
75_0402_1%
@ RC246 1 2 0_0402_5% VR_EN F60 F52

<46> H_VR_EN VR_EN VCC
RC244
@ RC247 1 2 0_0402_5% VR_READY C59 F56

CAD Note: Place the PU resistors close to CPU <46> H_VR_READY VR_READY VCC G23
RC224 close to CPU 300 - check D63 VCC G25
H59 VSS VCC G27
1500mils <9> CPU_PWR_DEBUG#
2
P62 PWR_DEBUG VCC G29

2 1 H_CPU_SVIDALRT# P60 VSS VCC G31
<46> VIDALERT_N @ T74 PAD~D RSVD_TP VCC
43_0402_5% RC248 @ T75 P61 G33
PAD~D N59 RSVD_TP VCC G35
@ T76 PAD~D RSVD_TP VCC
@ T77 N61 G37
PAD~D T59 RSVD_TP VCC G39
+1.05V_VCCST @ T78 PAD~D RSVD VCC
@ T79 AD60 G41
B
SVID DATA @ T80
PAD~D
PAD~D
AD59 RSVD
RSVD
VCC
VCC
G43 B
110_0402_1%
@ T81 AA59 G45

PAD~D RSVD VCC
1
AE60 G47
CAD Note: Place the PU resistors close to CPU @ T82 PAD~D RSVD VCC
RC249
@ T83 AC59 G49

PAD~D RSVD VCC
RC249close to CPU 300 - 1500mils @ T84 PAD~D
AG58
RSVD VCC
G51
@ T85 U59 G53
PAD~D V59 RSVD VCC G55
@ T86 PAD~D
2
RSVD VCC G57

VIDSOUT AC22 VCC H23
<46> VIDSOUT +1.05V_VCCST VCCST VCC
AE22 J23
AE23 VCCST VCC K23
VCCST VCC K57
AB57 VCC L22
+VCC_CORE VCC VCC
AD57 M23
AG57 VCC VCC M57
C24 VCC VCC P57
VCC_SENSE +VCC_CORE C28
C32
VCC
VCC
VCC
VCC
VCC
VCC
U57
W57
1
100_0402_1%
12 OF 19 Rev1p2
RC250
+1.05V_RUN +1.05V_VCCST
@ PJP11
2
1 2
22U_0603_6.3V6M
VCCSENSE PAD-OPEN1x1m
<46> VCCSENSE
1U_0402_6.3V6K
1
@
CC50
CC26
CAD Note: RC250 SHOULD BE PLACED CLOSE TO CPU

2
A A
LA-9591P
5 4 3 2 1
5 4 3 2 1
ESD test request

+1.05V_M +1.05V_RUN
+1.05V_RUN +VCC_CORE
+1.05V_MODPHY +1.05V_MODPHY_PCH
1 2 1 2
330U_D3_2.5VY_R6M
330U_D3_2.5VY_R6M
@
330U_D3_2.5VY_R6M
@
@ RC262 0_0805_5%
1
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
@ CC73
EMC@ CC83 22U_0603_6.3V6M
+ + +
1
@ CC74
CC71
CC72
1 2
CC27
CC29
2
+1.05V_RUN EMC@ CC84 22U_0603_6.3V6M +3.3V_RUN
2
CC29 place near K9;
1 2
D
CC27 place near L10 D
EMC@ CC85 22U_0603_6.3V6M
CC74 place near M9
+RTC_CELL
CC35,CC38, CC39 place near AG10

+1.05V_MODPHY
0.1U_0402_10V7K
0.1U_0402_10V7K
1U_0402_6.3V6K
+PCH_AUSB3PLL UC1M HASWELL_MCP_E
1
@
LC1
CC38
CC39
CC35
1 2 +1.05V_MODPHY_PCH
K9
2.2UH_LQM2MPN2R2NG0L_30% +1.05V_RUN L10 VCCHSIO
2
VCCHSIO
22U_0603_6.3V6M
22U_0603_6.3V6M M9
VCCHSIO
1
N8 mPHY AH11
VCC1_05 VCCSUS3_3 +PCH_RTC_VCCSUS3_3
CC76
CC42
1U_0402_6.3V6K
P9 RTC AG10
B18 VCC1_05 VCCRTC AE7 +DCPRRTC 1 2
+PCH_AUSB3PLL
2
VCCUSB3PLL DCPRTC
@ CC31
B11 CC36 0.1U_0402_10V7K
CC42 place near B18 +PCH_ASATA3PLL VCCSATA3PLL +3.3V_M
2
Y20 SPI Y8 CC40 place near Y8
RSVD VCCSPI
0.1U_0402_10V7K
AA21 OPI
W21 VCCAPLL
+V1.05S_APLLOPI VCCAPLL
@ CC40
AG14 +1.05V_M
VCCASW AG13
VCCASW +1.05V_RUN
CC34 and CC33 place near
2
+1.05V_MODPHY +PCH_ASATA3PLL +3.3V_ALW_PCH J13 USB3
+PCH_DCPSUS DCPSUS3 J11; CC37 place near AE8
LC2 J11 +PCH_VCCDSW 2 1
1 2 VCC1_05 H11 RC275 5.11_0402_1%
VCC1_05 +1.05V_M
10U_0603_6.3V6M
2.2UH_LQM2MPN2R2NG0L_30% AH14 AXALIA/HDA H15
+PCH_VCCDSW_R
CC44 place near AH14 VCCHDA VCC1_05
22U_0603_6.3V6M
22U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
AE8
VCC1_05
1
0.1U_0402_10V7K
CC33
AF22
CC49 place near B11 VCC1_05
1
22U_0805_6.3V6M
CC37
CC34
AH13 VRM/USB2/AZALIA AG19 +PCH_VCCDSW
DCPSUS2 DCPSUSBYP
1
+3.3V_ALW_PCH
CC77
CC49
1U_0402_6.3V6K
CORE AG20
2
DCPSUSBYP
1
CC44
AE9 CC46 CC47 place near AE9
2
VCCASW
CC46
@
AF9
2
VCCASW
CC47
CC28 place near AC9 AC9 AG8
CC65 place near AG19
2
AA9 VCCSUS3_3 VCCASW AD10
+3.3V_RUN
22U_0603_6.3V6M VCCSUS3_3 DCPSUS1 +PCH_DCPSUS1
1U_0402_6.3V6K
AH10 AD8
C +PCH_VCCDSW3_3 VCCDSW3_3 DCPSUS1 C
V8 GPIO/LCC
VCC3_3
1
CC28
CC43 place near V8 W9
VCC3_3
1
J15 +3.3V_RUN
VCCTS1_5 +1.5V_THERMAL
22U_0603_6.3V6M
CC65
THERMAL SENSOR K14
2
VCC3_3
1
0.1U_0402_10V7K
K16 CC59 place near K14
2
+1.05V_RUN +V1.05S_APLLOPI CC43 VCC3_3
1
LC5 +3.3V_RUN
2
+1.05V_RUN
CC59
1 2 J18
+PCH_VCC1P05 VCCCLK
2.2UH_LQM2MPN2R2NG0L_30% K19 SDIO/PLSS U8 CC45 place near U8
2
VCCCLK VCCSDIO
100U_1206_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
A20 T9
+PCH_VCCACLKPLL VCCACLKPLL VCCSDIO
J17
VCCCLK
1
1
+PCH_RTC_VCCSUS3_3 +3.3V_ALW_PCH
1U_0402_6.3V6K
1U_0402_6.3V6K
CC63 close to Pin J17 R21
VCCCLK
CC55
CC56
CC45
T21 LPT LP POWER
CC64 close to Pin R21 VCCCLK
1
1
K18 SUS OSCILLATOR AB8 2 1
CC56 place near AA21 +PCH_DCPSUS4
2
2
RSVD DCPSUS4
CC63
CC64
M20 0_0402_5% RC261 @
V21 RSVD +1.05V_RUN
2
AE20 RSVD AC20 +3.3V_ALW

+3.3V_ALW_PCH VCCSUS3_3 RSVD
AE21 AG16 CC60 place near AG16
VCCSUS3_3 USB2 VCC1_05
1U_0402_6.3V6K
AG17 2 1
VCC1_05
1U_0402_6.3V6K
0_0402_5% RC264 @
CC60
1
+1.05V_M +PCH_DCPSUS
CC30
13 OF 19 Rev1p2
CC30 place near AH11
2
1 2
@ RC276 0_0603_5%
+1.05V_RUN +PCH_VCC1P05
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
LC3
1
1
@ CC66
@ CC61
@ CC62
1 2
2.2UH_LQM2MPN2R2NG0L_30%
100U_1206_6.3V6M
1U_0402_6.3V6K
2
+PCH_DCPSUS1 +1.05V_M
1
CC66 place near AH13

CC79
CC51
2 1
0_0402_5% RC272 @
CC61 CC62 place near J13 CC51 place near J18
2
B B
1U_0402_6.3V6K
1
@ CC54
CC54 place near AD10
2
+3.3V_ALW_PCH +PCH_VCCDSW3_3
1 2
@ RC265 0_0402_5% +PCH_VCCACLKPLL
+1.05V_RUN
+3.3V_ALW LC6
1 2
@ RC267 1 2 0_0402_5% 2.2UH_LQM2MPN2R2NG0L_30% +PCH_DCPSUS4 +1.05V_M
100U_1206_6.3V6M
1U_0402_6.3V6K
@ LC4
1U_0402_6.3V6K
2 1
2.2UH_LQM2MPN2R2NG0L_30%
CC32 place near AH10 CC58 place near A20
1
1
CC78
CC58
1
@ CC32
1U_0402_6.3V6K
100U_1206_6.3V6M
2
1
@ CC53
@ CC75
2
2
CC53 place near AB8
A A
LA-9591P
5 4 3 2 1
5 4 3 2 1
D D
UC1N HASWELL_MCP_E UC1O HASWELL_MCP_E
A11 AJ35 AP22 AV59

A14 VSS VSS AJ39 AP23 VSS VSS AV8
A18 VSS VSS AJ41 AP26 VSS VSS AW16
A40 VSS VSS AJ52 AP39 VSS VSS AW4 UC1P
VSS VSS VSS VSS HASWELL_MCP_E
A44 AJ54 AP48 AW40 H17
A48 VSS VSS AJ56 AP52 VSS VSS AW42 D33 VSS H57
A52 VSS VSS AJ58 AP54 VSS VSS AW44 D34 VSS VSS J10
A56 VSS VSS AJ60 AP57 VSS VSS AW47 D35 VSS VSS J22
AA1 VSS VSS AJ63 AR11 VSS VSS AW50 D37 VSS VSS J59
AA58 VSS VSS AK23 AR15 VSS VSS AW51 D38 VSS VSS J63
AB10 VSS VSS AK3 AR17 VSS VSS AW59 D39 VSS VSS K1
AB20 VSS VSS AK52 AR23 VSS VSS AW60 D41 VSS VSS K12
AB22 VSS VSS AL10 AR31 VSS VSS AY11 D42 VSS VSS L13
AB7 VSS VSS AL13 AR33 VSS VSS AY16 D43 VSS VSS L15
AC61 VSS VSS AL17 AR39 VSS VSS AY18 D45 VSS VSS L17
AD21 VSS VSS AL20 AR43 VSS VSS AY22 D46 VSS VSS L18
AE10 VSS VSS AL26 AR52 VSS VSS AY30 D5 VSS VSS L61
AE5 VSS VSS AL29 AT13 VSS VSS AY33 D50 VSS VSS L7
AE58 VSS VSS AL31 AT35 VSS VSS AY4 D51 VSS VSS M22
C AF11 VSS VSS AL33 AT37 VSS VSS AY51 D53 VSS VSS N10 C
AF12 VSS VSS AL36 AT40 VSS VSS AY53 D54 VSS VSS N3
AF14 VSS VSS AL39 AT42 VSS VSS AY57 D55 VSS VSS P59
AF15 VSS VSS AL40 AT43 VSS VSS AY59 D57 VSS VSS P63
AF17 VSS VSS AL45 AT46 VSS VSS AY6 D59 VSS VSS R10
AF18 VSS VSS AL46 AT49 VSS VSS B20 D62 VSS VSS R22
AG1 VSS VSS AL51 AT61 VSS VSS B24 D8 VSS VSS R8
AG11 VSS VSS AL52 AT62 VSS VSS B26 E11 VSS VSS T1
AG21 VSS VSS AL54 AT63 VSS VSS B28 E17 VSS VSS T58
AG23 VSS VSS AL57 AU1 VSS VSS B32 F20 VSS VSS U20
AG62 VSS VSS AM1 AU20 VSS VSS B40 F34 VSS VSS U9
AG63 VSS VSS AM17 AU22 VSS VSS B44 F38 VSS VSS V10
AH17 VSS VSS AM23 AU24 VSS VSS B48 F42 VSS VSS V3
AH19 VSS VSS AM31 AU26 VSS VSS B52 F46 VSS VSS V7
AH20 VSS VSS AM52 AU28 VSS VSS B56 F50 VSS VSS W20
AH22 VSS VSS AN17 AU30 VSS VSS B60 F54 VSS VSS W22
AH24 VSS VSS AN23 AU33 VSS VSS C11 F58 VSS VSS Y10
AH28 VSS VSS AN31 AU51 VSS VSS C14 F61 VSS VSS Y59
AH30 VSS VSS AN32 AU53 VSS VSS C18 G18 VSS VSS Y63
AH32 VSS VSS AN35 AU55 VSS VSS C20 G22 VSS VSS
AH34 VSS VSS AN36 AU57 VSS VSS C25 G3 VSS
AH36 VSS VSS AN39 AU59 VSS VSS C27 G5 VSS V58
AH38 VSS VSS AN40 AV14 VSS VSS C38 G6 VSS VSS AH46
AH40 VSS VSS AN42 AV16 VSS VSS C39 G8 VSS VSS V23
AH42 VSS VSS AN43 AV20 VSS VSS C57 H13 VSS VSS E62
AH44 VSS VSS AN45 AV24 VSS VSS D12 VSS VSS_SENSE AH16 VSSSENSE <46>
AH49 VSS VSS AN46 AV28 VSS VSS D14 16 OF 19 Rev1p2 VSS
AH51 VSS VSS AN48 AV33 VSS VSS D18
B AH57 VSS VSS AN52 AV39 VSS VSS D23 B
AJ13 VSS VSS AN60 AV41 VSS VSS D25
AJ14 VSS VSS AN63 AV43 VSS VSS D26 VSSSENSE 1 2
AJ23 VSS VSS AN7 AV46 VSS VSS D27 RC260 100_0402_1%
AJ25 VSS VSS AP10 AV49 VSS VSS D29
VSS VSS VSS 15 OF 19 Rev1p2 VSS
14 OF 19 Rev1p2
CAD Note: RC260 SHOULD BE PLACED CLOSE TO CPU
A A
LA-9591P
5 4 3 2 1
5 4 3 2 1
<8> DDR_A_DQS#[0..7]
<8> DDR_A_D[0..63]
H=4mm
<8> DDR_A_DQS[0..7] +SM_VREF_DQ0_DIMM1 +DIMM1_VREF_DQ +1.35V_MEM
Reverse Type +1.35V_MEM
JDIMM1
<8> DDR_A_MA[0..15] 1 2 1 2
VREF_DQ VSS1
2.2U_0402_6.3V6M
@ RD1 0_0402_5% 3 4 DDR_A_D9
VSS2 DQ4
0.1U_0402_25V6
DDR_A_D13 5 6 DDR_A_D12
D DDR_A_D8 7 DQ0 DQ5 8 D
DQ1 VSS3
1
9 10 DDR_A_DQS#1
VSS4 DQS#0
CD1
CD2
11 12 DDR_A_DQS1
13 DM0 DQS0 14 +1.35V_MEM
Note:
2
DDR_A_D14 15 VSS5 VSS6 16 DDR_A_D15
Check voltage tolerance of DDR_A_D10 17 DQ2 DQ6 18 DDR_A_D11
VREF_DQ at the DIMM socket 19 DQ3 DQ7 20
Layout Note: VSS7 VSS8
1
470_0402_5%
DDR_A_D28 23 DQ8 DQ12 24 DDR_A_D24
Place near JDIMM1 DQ9 DQ13
RD3
25 26
DDR_A_DQS#3 27 VSS9 VSS10 28
DDR_A_DQS3 29 DQS#1 DM1 30 DDR3_DRAMRST#
2
31 DQS1 RESET# 32
DQ10 DQ14
0.1U_0402_25V6
DDR_A_D31 35 36 DDR_A_D26 1 2
+1.35V_MEM 37 DQ11 DQ15 38 <19> DDR3_DRAMRST# DDR3_DRAMRST#_CPU <9>
@ RC279 0_0402_5%
VSS13 VSS14
@ CD3
DQ16 DQ20
1
43 DQ17 DQ21 44
VSS15 VSS16
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
DDR_A_DQS#5 45 46
2
DDR_A_DQS5 47 DQS#2 DM2 48
DQS2 VSS17
1
1
49 50 DDR_A_D42
VSS18 DQ22
CD4
CD5
CD6
CD7
CD8
CD9
CD10
CD11
DDR_A_D47 53 DQ18 DQ23 54
2
2
55 DQ19 VSS19 56 DDR_A_D52
VSS20 DQ28 CAD NOTE
DDR_A_D50 59 DQ24 DQ29 60 PLACE THE CAP NEAR TO DIMM RESET PIN
61 DQ25 VSS21 62 DDR_A_DQS#6
63 VSS22 DQS#3 64 DDR_A_DQS6 +1.35V_MEM
65 DM3 DQS3 66
DQ26 DQ30
1
1.8K_0402_1%
DQ27 DQ31
RC217
71 72
+1.35V_MEM VSS25 VSS26
C +SM_VREF_DQ0_DIMM1 +SM_VREF_DQ0 C
2
DDR_CKE0_DIMMA 73 74 DDR_CKE1_DIMMA
<8> DDR_CKE0_DIMMA CKE0 CKE1 DDR_CKE1_DIMMA <8>
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
330U_D3_2.5VY_R6M
75 76
77 VDD1 VDD2 78 DDR_A_MA15 1 2
DDR_A_BS2 79 NC1 A15 80 DDR_A_MA14 RC173 2_0402_1%
<8> DDR_A_BS2 BA2 A14
1
@ CD15
@ CD18
0.022U_0402_16V7K
81 82
VDD3 VDD4
1
1
CD14
CD16
CD17
CD19
CD20
CD21
CD22
1.8K_0402_1%
+ DDR_A_MA12 83 84 DDR_A_MA11
A12/BC# A11
1
DDR_A_MA9 85 86 DDR_A_MA7
A9 A7
1
RC221
CC70
87 88
2
DDR_A_MA8 89 VDD5 VDD6 90 DDR_A_MA6

DDR_A_MA5 91 A8 A6 92 DDR_A_MA4
2
93 A5 A4 94
2
DDR_A_MA3 95 VDD7 VDD8 96 DDR_A_MA2
A3 A2
1
24.9_0402_1%
DDR_A_MA1 97 98 DDR_A_MA0
A1 A0
RC195
99 100
M_CLK_DDR0 101 VDD9 VDD10 102 M_CLK_DDR1
<8> M_CLK_DDR0 103 CK0 CK1 104 M_CLK_DDR1 <8>
M_CLK_DDR#0 M_CLK_DDR#1
<8> M_CLK_DDR#0 105 CK0# CK1# 106 M_CLK_DDR#1 <8>
2
DDR_A_MA10 107 VDD11 VDD12 108 DDR_A_BS1
A10/AP BA1 DDR_A_BS1 <8>
DDR_A_BS0 109 110 DDR_A_RAS#
<8> DDR_A_BS0 111 BA0 RAS# 112 DDR_A_RAS# <8>
DDR_A_WE# 113 VDD13 VDD14 114 DDR_CS0_DIMMA#
Layout Note: <8> DDR_A_WE#
DDR_A_CAS# 115 WE# S0# 116 M_ODT0
DDR_CS0_DIMMA# <8>
<8> DDR_A_CAS# 117 CAS# ODT0 118
Place near DDR_A_MA13 119 VDD15 VDD16 120 M_ODT1
DDR_CS1_DIMMA# 121 A13 ODT1 122 +SM_VREF_CA_DIMM1 +SM_VREF_CA_DIMM
JDIMM1.203,204 <8> DDR_CS1_DIMMA# 123 S1# NC2 124
125 VDD17 VDD18 126 1 2
127 NCTEST VREF_CA 128 0_0402_5% @ RD12
VSS27 VSS28
0.1U_0402_25V6
2.2U_0402_6.3V6M
DDR_A_D1 131 DQ32 DQ36 132 DDR_A_D4
DQ33 DQ37
1
CD13
CD12
133 134
DDR_A_DQS#0 135 VSS29 VSS30 136
DDR_A_DQS0 137 DQS#4 DM4 138
DDR3L SODIMM ODT GENERATION
2
+0.675V_DDR_VTT 139 DQS4 VSS31 140 DDR_A_D3
B B
DDR_A_D2 141 VSS32 DQ38 142 DDR_A_D7 +5V_ALW
DDR_A_D6 143 DQ34 DQ39 144
145 DQ35 VSS33 146 DDR_A_D18 +1.35V_MEM QD1
VSS34 DQ44
1
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
10U_0603_6.3V6M
10U_0603_6.3V6M
220K_0402_5%
DDR_A_D21 147 148 DDR_A_D19 BSS138-G_SOT23-3
DQ40 DQ45
R28
DDR_A_D20 149 150
DQ41 VSS35
1
151 152 DDR_A_DQS#2 1 3 1 2 M_ODT0
S
VSS36 DQS#5
CD26
CD27
CD28
CD29
CD30
CD31
153 154 DDR_A_DQS2 R29 66.5_0402_1%

155 DM5 DQS5 156 1 2 M_ODT1
2
2
DDR_A_D17 157 VSS37 VSS38 158 DDR_A_D22 R30 66.5_0402_1%
G
2
DDR_A_D16 159 DQ42 DQ46 160 DDR_A_D23 1 2
161 DQ43 DQ47 162 M_ODT2 <19>
0.675V_DDR_VTT_ON R31 66.5_0402_1%
DDR_A_D36 163 VSS39 VSS40 164 DDR_A_D37 1 2
165 DQ48 DQ52 166 M_ODT3 <19>
DDR_A_D33 DDR_A_D32 R33 66.5_0402_1%
167 DQ49 DQ53 168
VSS41 VSS42
2
2M_0402_5%
DDR_A_DQS#4 169 170
DQS#6 DM6
@ R32
DDR_A_DQS4 171 172
173 DQS6 VSS43 174 DDR_A_D35
DDR_A_D34 175 VSS44 DQ54 176 DDR_A_D39
DDR_A_D38 177 DQ50 DQ55 178
1
179 DQ51 VSS45 180 DDR_A_D63
DDR_A_D62 181 VSS46 DQ60 182 DDR_A_D59
DDR_A_D58 183 DQ56 DQ61 184
185 DQ57 VSS47 186 DDR_A_DQS#7 +1.35V_MEM
187 VSS48 DQS#7 188 DDR_A_DQS7
189 DM7 DQS7 190 U5
DDR_A_D60 191 VSS49 VSS50 192 DDR_A_D56 1 5 1 2
DDR_A_D61 193 DQ58 DQ62 194 DDR_A_D57 NC VCC @ CD23 0.1U_0402_25V6
195 DQ59 DQ63 196 2
1 2 197 VSS51 VSS52 198 <9> DDR_PG_CTRL A 4 0.675V_DDR_VTT_ON
199 SA0 EVENT# 200 3 Y 0.675V_DDR_VTT_ON <43>
@ RD5 0_0402_5% +3.3V_RUN
1 2 201 VDDSPD SDA 202 DDR_XDP_WAN_SMBDAT <19,25,31,7,9> GND
203 SA1 SCL 204 DDR_XDP_WAN_SMBCLK <19,25,31,7,9>
@ RD6 0_0402_5% +0.675V_DDR_VTT +0.675V_DDR_VTT 74AUP1G07GW_TSSOP5
VTT1 VTT2
2.2U_0402_6.3V6M
0.1U_0402_25V6
205 206
A G1 G2 A
1
1
@ CD25
FOX_AS0A621-U4R6-7H
CD24
CONN@
2
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT DDR3L
LA-9591P
5 4 3 2 1
5 4 3 2 1
H=4mm
+SM_VREF_DQ1_DIMM2 +DIMM2_VREF_DQ
Reverse Type
+1.35V_MEM +1.35V_MEM
<8> DDR_B_DQS#[0..7]
JDIMM2 CONN@
1 2 1 2
<8> DDR_B_D[0..63] VREF_DQ VSS1
@ RD7 0_0402_5% 3 4 DDR_B_D12
VSS2 DQ4
2.2U_0402_6.3V6M
DDR_B_D8 5 6 DDR_B_D9
<8> DDR_B_DQS[0..7] DQ0 DQ5
0.1U_0402_25V6
DDR_B_D14 7 8
9 DQ1 VSS3 10 DDR_B_DQS#1
<8> DDR_B_MA[0..15] Note: VSS4 DQS#0
1
D 11 12 DDR_B_DQS1 D
Check voltage tolerance of DM0 DQS0
CD32
CD33
13 14
VREF_DQ at the DIMM socket DDR_B_D10 15 VSS5 VSS6 16 DDR_B_D13
2
DDR_B_D11 17 DQ2 DQ6 18 DDR_B_D15 +1.35V_MEM
19 DQ3 DQ7 20
DDR_B_D28 21 VSS7 VSS8 22 DDR_B_D25
DQ8 DQ12
1.8K_0402_1%
1
25 DQ9 DQ13 26
VSS9 VSS10
RC67
DDR_B_DQS#3 27 28
DDR_B_DQS3 29 DQS#1 DM1 30 DDR3_DRAMRST#
DQS1 RESET# DDR3_DRAMRST# <18> +SM_VREF_CA_DIMM +SM_VREF_CA
31 32
Layout Note:
2
VSS11 VSS12
0.1U_0402_25V6
DDR_B_D27 35 DQ10 DQ14 36 DDR_B_D31
Place near JDIMM2 DQ11 DQ15
@ CD34
37 38 1 2
DDR_B_D40 39 VSS13 VSS14 40 DDR_B_D45 RC68 2_0402_1%
DQ16 DQ20
0.022U_0402_16V7K
2
DQ17 DQ21
1.8K_0402_1%
43 44
VSS15 VSS16
1
DDR_B_DQS#5 45 46
DQS#2 DM2
1
RC69
CC67
DDR_B_DQS5 47 48
49 DQS2 VSS17 50 DDR_B_D47
DDR_B_D46 51 VSS18 DQ22 52 DDR_B_D43
2
+1.35V_MEM DDR_B_D42 53 DQ18 DQ23 54 CAD NOTE
2
55 DQ19 VSS19 56 DDR_B_D61
VSS20 DQ28 PLACE THE CAP NEAR TO DIMM RESET PIN
1
24.9_0402_1%
DQ24 DQ29
RC83
DDR_B_D57 59 60
DQ25 VSS21
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
61 62 DDR_B_DQS#7
63 VSS22 DQS#3 64 DDR_B_DQS7
DM3 DQS3
1
1
65 66
2
VSS23 VSS24
CD35
CD36
CD37
CD38
CD39
CD40
CD41
CD42
2
71 DQ27 DQ31 72
VSS25 VSS26
DDR_CKE2_DIMMB 73 74 DDR_CKE3_DIMMB
C <8> DDR_CKE2_DIMMB CKE0 CKE1 DDR_CKE3_DIMMB <8> +1.35V_MEM C
75 76
77 VDD1 VDD2 78 DDR_B_MA15
NC1 A15
1
1.8K_0402_1%
DDR_B_BS2 79 80 DDR_B_MA14
+1.35V_MEM <8> DDR_B_BS2 BA2 A14
81 82
DDR_B_MA12 83 VDD3 VDD4 84 DDR_B_MA11
RC130
DDR_B_MA9 85 A12/BC# A11 86 DDR_B_MA7
87 A9 A7 88 +SM_VREF_DQ1_DIMM2 +SM_VREF_DQ1
2
VDD5 VDD6
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
330U_D3_2.5VY_R6M
DDR_B_MA8 89 90 DDR_B_MA6
DDR_B_MA5 91 A8 A6 92 DDR_B_MA4
93 A5 A4 94 1 2
VDD7 VDD8
1
@ CD46
@ CD47
DDR_B_MA3 95 96 DDR_B_MA2 RC126 2_0402_1%

A3 A2
1
1
CD45
CD48
CD49
CD50
CD51
CD52
CD53
0.022U_0402_16V7K
+ DDR_B_MA1 97 98 DDR_B_MA0
A1 A0
1.8K_0402_1%
99 100
VDD9 VDD10
1
M_CLK_DDR2 101 102 M_CLK_DDR3
<8> M_CLK_DDR2 M_CLK_DDR3 <8>
2
CK0 CK1
1
RC132
CC69
M_CLK_DDR#2 103 104 M_CLK_DDR#3
<8> M_CLK_DDR#2 CK0# CK1# M_CLK_DDR#3 <8>
105 106
DDR_B_MA10 107 VDD11 VDD12 108 DDR_B_BS1 DDR_B_BS1 <8>
2
DDR_B_BS0 109 A10/AP BA1 110 DDR_B_RAS#
<8> DDR_B_BS0
2
111 BA0 RAS# 112 DDR_B_RAS# <8>
VDD13 VDD14
24.9_0402_1%
DDR_B_WE# 113 114 DDR_CS2_DIMMB#
<8> DDR_B_WE# WE# S0# DDR_CS2_DIMMB# <8>
1
DDR_B_CAS# 115 116 M_ODT2
<8> DDR_B_CAS# CAS# ODT0 M_ODT2 <18>
RC128
117 118
DDR_B_MA13 119 VDD15 VDD16 120
A13 ODT1 M_ODT3 <18>
+SM_VREF_CA_DIMM2 +SM_VREF_CA_DIMM
DDR_CS3_DIMMB# 121 122
<8> DDR_CS3_DIMMB# S1# NC2
123 124
2
125 VDD17 VDD18 126 1 2
127 NCTEST VREF_CA 128 0_0402_5% @ RD13
VSS27 VSS28
0.1U_0402_25V6
2.2U_0402_6.3V6M
133 DQ33 DQ37 134
Layout Note: VSS29 VSS30
1
CD44
CD43
DDR_B_DQS#0 135 136
DDR_B_DQS0 137 DQS#4 DM4 138
Place near 139 DQS4 VSS31 140 DDR_B_D2
2
B
JDIMM2.203,204 DDR_B_D7 143 DQ34 DQ39 144 B
145 DQ35 VSS33 146 DDR_B_D16
DDR_B_D20 149 DQ40 DQ45 150
+0.675V_DDR_VTT 155 DM5 DQS5 156
DDR_B_D23 159 DQ42 DQ46 160 DDR_B_D18
161 DQ43 DQ47 162
DQ48 DQ52
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
10U_0603_6.3V6M
10U_0603_6.3V6M
DDR_B_D33 165 166 DDR_B_D32

167 DQ49 DQ53 168
VSS41 VSS42
1
1
CD54
CD55
CD56
CD57
CD58
CD59
DDR_B_DQS#4 169 170

DDR_B_DQS4 171 DQS#6 DM6 172
173 DQS6 VSS43 174 DDR_B_D34
2

DDR_B_D39 177 DQ50 DQ55 178
179 DQ51 VSS45 180 DDR_B_D51
DDR_B_D49 183 DQ56 DQ61 184
189 DM7 DQS7 190
DDR_B_D53 193 DQ58 DQ62 194 DDR_B_D50
195 DQ59 DQ63 196
+3.3V_RUN 197 VSS51 VSS52 198
199 SA0 EVENT# 200
+3.3V_RUN VDDSPD SDA DDR_XDP_WAN_SMBDAT <18,25,31,7,9>
2 1 201 202
SA1 SCL DDR_XDP_WAN_SMBCLK <18,25,31,7,9>
@ RD10 0_0402_5% +0.675V_DDR_VTT 203 204 +0.675V_DDR_VTT
VTT1 VTT2
1
0_0402_5%
@ RD11
205 206
G1 G2
2.2U_0402_6.3V6M
0.1U_0402_25V6
FOX_AS0A621-U4R6-7H
A
1
A
@ CD61
2
CD60
2
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT DDR3L
LA-9591P
5 4 3 2 1
5 4 3 2 1
D D
+3.3V_ALW_PCH
@ C388
2 1
5
0.1U_0402_25V6
1
P
<9> PLTRST_NFC# B 4 NFC_RST
2 O
<12> PCH_NFC_RST A
G
U29
NFC CONN
3
TC7SH08FU_SSOP5~D
C C
+3.3V_ALW_PCH JNFC1
17
GND 16
15 GND
14 15
13 14
@ T87 PAD~D TP_NFC_SWP_PWR_RSVD 12 13
@ T88 PAD~D TP_NFC_RSVD4 11 12
NFC_RST 10 11
9 10
NFC_SMBCLK 8 9
+3.3V_ALW_PCH <7> NFC_SMBCLK NFC_SMBDATA 7 8
<7> NFC_SMBDATA TP_NFC_RSVD3 6 7
5 6
1 2 <12> NFC_IRQ 4 5
NFC_DET#
R38 100K_0402_5% @ T89 PAD~D TP_NFC_RSVD1 3 4
NFC_DET# 2 3 +3.3V_ALW_PCH
1 2 TP_NFC_RSVD3 <12> NFC_DET# 1 2
1
0.1U_0402_16V4Z
@ R37 0_0402_5%
E-T_6705K-Y15N-00L
CONN@
@ C1
2
B
C1 close to JNFC1 B
A A
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT NFC
LA-9591P
5 4 3 2 1
2 1
+1.05V_RUN_VMM
+3.3V_RUN_VDDA +3.3V_RUN_VMM
1V Digital
L1 U6B L2
1 2 E6 3.3V Analog H5 1 2
BLM18AG102SN1D_2P E7 VDD VDDRX_33 C10 BLM18AG102SN1D_2P
+1.05V_VMM_VDD VDD VDDTX0_33
10U_0603_6.3V6M
0.01U_0402_16V7K
0.01U_0402_16V7K
0.01U_0402_16V7K
0.01U_0402_16V7K
E8 H12
VDD VDDTX1_33
1U_0603_10V6K
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
1U_0603_10V6K
E9 K6
VDD VGA_AVDD33
1
H6 K7
VDD VGA_AVDD33
C132
C8
C9
C11
C10
C12
C13
C14
C15
C16
H7 U6A
H8 VDD 0.1U_0402_10V7K 1 2 C155 DP12412_P0_C G1 B7
<27> DP12412_P0
2
H9 VDD C5 0.1U_0402_10V7K 1 2 C156 DP12412_N0_C G2 RxP0 Tx0P0 A7 DPC_LANE_P0 <34>
VDD VSS D5 <27> DP12412_N0 1 2 F1 RxN0 Tx0N0 B8 DPC_LANE_N0 <34>
0.1U_0402_10V7K C157 DP12412_P1_C
E3 VSS D6 <27> DP12412_P1 1 2 F2 RxP1 Tx0P1 A8 DPC_LANE_P1 <34>
0.1U_0402_10V7K C158 DP12412_N1_C
G3 VDDRX VSS D7 <27> DP12412_N1 1 2 E1 RxN1 Tx0N1 B9 DPC_LANE_N1 <34>
0.1U_0402_10V7K C159 DP12412_P2_C
VDDRX VSS D8 <27> DP12412_P2 1 2 DP12412_N2_C E2 RxP2 Tx0P2 A9 DPC_LANE_P2 <34>
0.1U_0402_10V7K C160
C8 VSS D9 <27> DP12412_N2 1 2 D1 RxN2 Tx0N2 B10 DPC_LANE_N2 <34>
0.1U_0402_10V7K C161 DP12412_P3_C
C9 VDDTX0 VSS D10 <27> DP12412_P3 1 2 D2 RxP3 Tx0P3 A10 DPC_LANE_P3 <34>
0.1U_0402_10V7K C162 DP12412_N3_C
VDDTX0 VSS <27> DP12412_N3 RxN3 Tx0N3 DPC_LANE_N3 <34>
0.01U_0402_16V7K
F12 D11 0.1U_0402_10V7K 1 2 C19 DP12412_AUX_C H1 A14
VDDTX1 VSS <27> DP12412_AUX RxAUXP CAD0 DPC_CA_DET <24,34>
1U_0603_10V6K
0.1U_0402_25V6
G12 E4 0.1U_0402_10V7K 1 2 C20 DP12412_AUX#_C H2 B11 SW_DPC_AUX
VDDTX1 VSS <27> DP12412_AUX# RXAUXN Tx0AUXP SW_DPC_AUX <24>
1
1
E11 SRCDET C2 A11 SW_DPC_AUX#
VSS RxSRCDET Tx0AUXN SW_DPC_AUX# <24>
C25
C17
C18
J3 F4 DP12412_HPD J1 B12 VMM_DPC_CTRLCLK
VDDXT1V VSS F5 <27> DP12412_HPD RxHPD Tx0DDCSCL A12 VMM_DPC_CTRLDAT VMM_DPC_CTRLCLK <24>
VMM_DPC_CTRLDAT <24>
2
2
E5 VSS F6 Tx0DDCSDA A6
+1.05V_RUN_VMM VDDLP VSS F7 Tx0HPD DPC_DOCK_HPD <34>
H3 VSS A13 E13
1 V Analog
F3 VDDRXA0 F8 <9> PLTRST_VMM2320# RSTN_IN Tx1P0 E14 DPB_LANE_P0 <34>
L4
1 2 +1.05V_VMM_VDDTX D3 VDDRXA1 VSS F9 VMM_MESCL B5 Tx1N0 F13 DPB_LANE_N0 <34>
BLM18AG102SN1D_2P VDDRXA2 VSS F10 VMM_MESDA B6 MESCL Tx1P1 F14 DPB_LANE_P1 <34>
VSS MESDA Tx1N1 DPB_LANE_N1 <34>
0.01U_0402_16V7K
0.01U_0402_16V7K
E10 F11 VMM_SPI_WP# B1 G13
VDDTX0A0 VSS ROMWP Tx1P2 DPB_LANE_P2 <34>
1U_0603_10V6K
0.1U_0402_25V6
C7 G4 G14
VDDTX0A1 VSS Tx1N2 DPB_LANE_N2 <34>
1
C6 G5 H13
VDDTX0A2 VSS Tx1P3 DPB_LANE_P3 <34>
C21
C22
C23
C24 2 1 VMM_GPIO9 VMM_SPI_CS# A4 H14

H11 G6 1M_0402_5% R63 VMM_SPI_CLK B3 SPICS Tx1N3 M14 DPB_LANE_N3 <34>
2
E12 VDDTX1A0 VSS G7 2 1 SW_DPC_AUX VMM_SPI_DIN B4 SPICLK CAD1 J13 SW_DPB_AUX DPB_CA_DET <24,34>
D12 VDDTX1A1 VSS G8 VMM_SPI_DO A3 SPIDI Tx1AUXP J14 SW_DPB_AUX# SW_DPB_AUX <24>
1M_0402_5% R92
VDDTX1A2 VSS G9 2 1 SPIDO Tx1AUXN K13 SW_DPB_AUX# <24>
B SW_DPB_AUX VMM_DPB_CTRLCLK B
J10 VSS G10 1M_0402_5% R47 Tx1DDCSCL L14 VMM_DPB_CTRLDAT VMM_DPB_CTRLCLK <24>
+3.3V_RUN_VMM K8 VGA_AVDD VSS G11 2 1 D14 Tx1DDCSDA K14 VMM_DPB_CTRLDAT <24>
RED_DOCK
L5 K9 VGA_AVDD VSS H4 150_0402_1% R311 D13 GPIO0 Tx1HPD DPB_DOCK_HPD <34>
1 2 +3.3V_RUN_VDDIO K10 VGA_AVDD VSS D4 2 1 GREEN_DOCK C14 GPIO1 L9 VMM2310_TX2P0
BLM18AG102SN1D_2P VGA_AVDD VSS 150_0402_1% R312 C13 GPIO2 VGA_VSYNC M9 VMM2310_TX2N0
GPIO3 VGA_HSYNC
0.01U_0402_16V7K
0.01U_0402_16V7K
J2 2 1 BLUE_DOCK B14 M6 VMM2310_TX2N3
3.3V IO
VDDSA GPIO4 VGA_RP
1U_0603_10V6K
0.1U_0402_25V6
J5 150_0402_1% R351 B13 L6

VSS GPIO5 VGA_RN
1
C3 J11 2 1 LP_CTL VMM_GPIO6 C1 M7 VMM2310_TX2N2

VDDIO VSS GPIO6/INT VGA_GP
C26
C27
C28
C29
C4 J12 100K_0402_5% R207 @ VMM_GPIO7 M12 L7

C11 VDDIO VSS K5 VMM_GPIO8 M13 GPIO7/MSCL VGA_GN M8 VMM2310_TX2N1
2
C12 VDDIO VSS H10 VMM_GPIO9 L3 GPIO8/MSDA VGA_BP L8

K3 VDDIO VGA_AVSS J6 LP_CTL B2 GPIO9 VGA_BN L4 VMM2310_SCL
K4 VDDIO VGA_AVSS J7 A5 LP_CTL VGA_SCL M4 VMM2310_SDA
K11 VDDIO VGA_AVSS J8 LP_EN VGA_SDA
K12 VDDIO VGA_AVSS J9
J4 VDDIO VGA_AVSS CLK_27M_IN_R 1 2 M3 VMM2310_HDP
+3.3V_RUN_VDDA VDDXT3V VGA_DET
@ R107 0_0402_5% K2 M5 VMM2310_AUXN
RX_STS VGA_IREF
1
1M_0402_5%
IDTVMM2320BKG8_BGA168 L2 L5 VMM2310_AUXP @ T40 PAD~D
M1 TX0_STS VGA_NC
TX1_STS
R66
M2 A1
TX2_STS SSDA A2 I2C1_SDA_VMM <12>
SSCL I2C1_SCL_VMM <12>
Y1
2
27MHZ_12PF_X1E000021042600 M11
+1.05V_RUN +1.05V_RUN_VMM 1 3 CLK_27M_IN K1 TRSTN M10
IN OUT XIN TCK L12
U31 2 4 TMS L13
GND GND TMS2
22P_0402_50V8J
22P_0402_50V8J
1 14 1 2 CLK_27M_OUT L1 L11
2 VIN1 VOUT1 13 C432 0.1U_0402_10V7K XOUT TDI L10 +3.3V_RUN_VMM
VIN1 VOUT1 TDO
1
C42
C43
DOCKED 3 12 1 2
<27,28,32,36> DOCKED ON1 CT1 1 2
C433 470P_0402_50V7K IDTVMM2320BKG8_BGA168 SW_DPB_AUX#
2
4 11 1M_0402_5% R44
+5V_ALW VBIAS GND VMM_GPIO6 1 2
DOCKED 5 10 1 2 2.2K_0402_5% R52
ON2 CT2 C394 470P_0402_50V7K SRCDET 1 2
6 9 1M_0402_5% R69
+3.3V_RUN VIN2 VOUT2 +3.3V_RUN_VMM
7 8
VIN2 VOUT2 RP9
0.1U_0402_10V7K
15 VMM_DPB_CTRLCLK 1 8
GPAD
2
VMM_DPB_CTRLDAT 2 7
EEPROM
C392
TPS22966DPUR_SON14_2X3 +3.3V_RUN_VMM VMM_GPIO7 3 6

VMM_GPIO8 4 5
1
C34
1 2 2.2K_0804_8P4R_5%
U7 0.1U_0402_25V6 VMM_MESCL 1 2
VMM_SPI_CS# 1 8 2.2K_0402_5% R40
VMM_SPI_DIN 2 CS# VCC 7 VMM_SPI_HOLD VMM_MESDA 1 2
VMM_SPI_WP# 3 DO(IO1) HOLD#(IO3) 6 VMM_SPI_CLK 2.2K_0402_5% R42
4 WP#(IO2) CLK 5 VMM_SPI_DO VMM_DPC_CTRLCLK 1 2
GND DI(IO0) 2.2K_0402_5% R49
W25X10CVSNIG_SO8 VMM_DPC_CTRLDAT 1 2
2.2K_0402_5% R46
SW_DPC_AUX# 1 2
1M_0402_5% R91
VMM_SPI_CS# 2 1
10K_0402_5% R64
VMM_SPI_HOLD 2 1
2.2K_0402_5% R65
+3.3V_RUN_VMM
VMM2310_TX2N3 1 2 RED_DOCK
@ R73 0_0402_5% RED_DOCK <34> VMM2310_HDP 2 1
10K_0402_5% 3@ R74
VMM2310_TX2N2 1 2 GREEN_DOCK
@ R75 0_0402_5% GREEN_DOCK <34>
A VMM2310_TX2N1 1 2 BLUE_DOCK A
@ R76 0_0402_5% BLUE_DOCK <34>
VMM2310_SCL 1 2 CLK_DDC2_DOCK
@ R77 0_0402_5% CLK_DDC2_DOCK <34>
VMM2310_SDA 1 2 DAT_DDC2_DOCK
DAT_DDC2_DOCK <34>
@ R81 0_0402_5%
VMM2310_TX2N0 1 2 HSYNC_DOCK
@ R84 0_0402_5% HSYNC_DOCK <34> VMM2310_AUXN 1 2
3.74K_0402_1% 3@ R85
VMM2310_TX2P0 1 2 VSYNC_DOCK
@ R88 0_0402_5% VSYNC_DOCK <34>
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT DP 1.2 MST HUB
LA-9591P
2 1
5 4 3 2 1
+5V_TSP
JEDP1
45
44 G5 40
40
39
LED CONN
43 G4 39 38 USBP7- <11>
42 G3 38 37 USBP7+ <11> JLED1
41 G2 37 36 1
G1 36 DMIC0 <26> +5V_ALW 1
35 2
35 <40> BATT_WHITE_LED# 2
3
L30ESDL5V0C3-2_SOT23-3
34 3
34 33 DMIC_CLK <26> <40> BATT_YELLOW_LED# 4 3
33 +3.3V_CAM <40> PANEL_HDD_LED# 4
100P_0402_50V8J
100P_0402_50V8J
32 USBP3_D- 5
32 31 USBP3_D+ <40> BREATH_WHITE_LED# 6 5
31 <12> TOUCH_PANEL_INTR# 6
@ D8
30 7
30 CAM_MIC_CBL_DET# <12> GND
@ CE1
@ CE2
D 29 LOOP_BACK 8 D
29 28 GND
2
28 27 E-T_4260K-Q06N-23L
27 +BL_PWR_SRC
26 CONN@
1
26 25
25 24
24 23
23 ESD depop location
22 LE1 1
EMC@LE1
EMC@ 2 BIA_PWM
22 21 DISP_ON BLM15BB221SN1D_2P~D
21 20 LOOP_BACK
20 19
19
1
1K_0402_5%
18
18 17 +5V_TSP
17
R108
16
16
15
15 EDP_CPU_HPD <10>
For Touchscreen
1
PAD-OPEN1x1m
14
2
14
@
13
13 LCD_TST <36> +5V_RUN +5V_RUN
PJP10
12
12 11 Q1
11 +LCDVDD
10 LP2301ALT1G_SOT23-3
10
1
47K_0402_5%
9 EDP_CPU_AUX#_C C54 2 1 0.1U_0402_10V7K
EDP_CPU_AUX# <10>
2
9 8 EDP_CPU_AUX_C C55 2 1 0.1U_0402_10V7K +5V_TSP_Q 1 3
S
8 EDP_CPU_AUX <10>
R94
0.1U_0402_25V6
7 EDP_CPU_LANE_P0_C C59 2 1 0.1U_0402_10V7K
7 6 EDP_CPU_LANE_P0 <10>
EDP_CPU_LANE_N0_C C56 2 1 0.1U_0402_10V7K
6 5 EDP_CPU_LANE_N0 <10>
EDP_CPU_LANE_P1_C C60 2 1 0.1U_0402_10V7K
G
EDP_CPU_LANE_P1 <10>
2
5
C61
4 EDP_CPU_LANE_N1_C C57 2 1 0.1U_0402_10V7K
4 3 EDP_CPU_LANE_N1 <10>
3 2
LCD_CBL_DET# <12>
2
2 1
1 +3.3V_RUN
DMN66D0LDW-7_SOT363-6
ACES_50398-04071-001
6
CONN@
3
C C
Q17A
+BL_PWR_SRC +LCDVDD +3.3V_CAM +5V_ALW +5V_TSP +3.3V_RUN 2 Q17B
<12> 3.3V_TS_EN 5 DMN66D0LDW-7_SOT363-6
0.1U_0603_50V7K
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_16V4Z
0.1U_0402_25V6
0.1U_0402_25V6
4
1
1
@
@
C52
C63
C68
C3
C62
C64
2
2
Close to JEDP1.24~27 Close to JEDP1.11,12 Close to JEDP1.33 Close to JLED1.1 Close to JLED1.40 Close to JLED1.2
D10 D21
LCDVDD POWER +LCDVDD
+3.3V_ALW
3 EDP_BIA_PWM 3 @ C431 U9
EDP_BIA_PWM <10> PANEL_BKLEN <10> 2 1 1
BIA_PWM 1 DISP_ON 1 VOUT 5
2 BIA_PWM_EC 2 10U_0603_6.3V6M VIN
BIA_PWM_EC <37> PANEL_BKEN_EC <36> 2
D2
GND
1
10K_0402_5%
100K_0402_5%
0.01U_0402_16V7K
4
SS
1
@
BAT54CW_SOT323-3 BAT54CW_SOT323-3 2
<36> LCD_VCC_TEST_EN
1
R95
R96
C430
1 EN_LCDPWR 3
EN
3 APL3512ABI-TRG_SOT23-5
<10,36> ENVDD_PCH
2
2
2
100K_0402_5%
2
R104
2nd source SA000028Y10
BAT54CW_SOT323-3
B B
1
WebCAM
+3.3V_CAM Backlight POWER +BL_PWR_SRC
Q2
1
PAD-OPEN1x1m
+PWR_SRC FDC654P-G_SSOT-6
@
+3.3V_RUN 6
D
PJP9
4 5
S
Q3 2
1000P_0402_50V7K
LP2301ALT1G_SOT23-3 1
2
100K_0402_5%
0.1U_0603_50V7K
1
0.1U_0402_25V6
+3.3V_CAM_Q 1 3
D
3
1
1
C66
R97
C65
1
C67
G
2
1 2
2
<36> CCD_OFF @ R102 0_0402_5%

2
1 2
<12> 3.3V_CAM_EN#
@ R106 0_0402_5% PWR_SRC_ON
Q4
L2N7002WT1G_SC-70-3
1 2 1 3
D
change back to CCD_OFF at Goliad project R99 47K_0402_5%

L8 EMC@
1 2 USBP3_D+
G
<11> USBP3+
2
1 2
A 4 3 USBP3_D- A
<11> USBP3- 4 3 <37> EN_INVPWR
DLW21HN900SQ2L_4P
1 2
@ R100 0_0402_5%
1 2
@ R101 0_0402_5%
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT eDP CONN & Touch screen
LA-9591P
5 4 3 2 1
5 4 3 2 1
L9 @
1 2
9NH_0402HS-9N0EJTS_5%
EMC@ L10
2 1 TMDS_CLK_C 4 3 TMDSB_CON_CLK
<10> DDI1_LANE_P3 4 3
C103 0.1U_0402_10V7K
2 1 TMDS_CLK#_C 1 2 TMDSB_CON_CLK#
<10> DDI1_LANE_N3 1 2
C191 0.1U_0402_10V7K
1.8P_0402_50V8
1.8P_0402_50V8
DLW21SN900HQ2L-0805_4P
1
@ C273
@ C274
D 1
L11 @
2 D
2
L12 @
1 2
L13 EMC@
2 1 TMDS_P0_C 4 3 TMDSB_CON_P0
<10> DDI1_LANE_P2 4 3
C199 0.1U_0402_10V7K
2 1 TMDS_N0_C 1 2 TMDSB_CON_N0
<10> DDI1_LANE_N2 1 2
C209 0.1U_0402_10V7K
1.8P_0402_50V8
1.8P_0402_50V8
1
@ C275
@ C276
L14 @
1 2
2
L15 @
1 2
9NH_0402HS-9N0EJTS_5% +5V_RUN
0.1U_0402_16V4Z
L16 EMC@
<10> DDI1_LANE_P1 4 3
C269 0.1U_0402_10V7K
1
@
+VHDMI_VCC
C333
2 1 TMDS_N1_C 1 2 TMDSB_CON_N1
<10> DDI1_LANE_N1 1 2
1
C270 0.1U_0402_10V7K
2
C C
1.8P_0402_50V8
1.8P_0402_50V8
IN
1
1
@ C277
@ C278
AP2330W-7_SC59-3
0.1U_0402_10V7K
10U_0603_6.3V6M
L17 @
1 2
1
U48
C88
@ C87
GND
OUT
2
L18 @
1 2
3
L19 EMC@
<10> DDI1_LANE_P0 4 3
C271 0.1U_0402_10V7K JHDMI1 CONN@
HDMI_HPD_SINK 19
2 1 TMDS_N2_C 1 2 TMDSB_CON_N2 18 HP_DET
<10> DDI1_LANE_N0 1 2 +5V
C272 0.1U_0402_10V7K 17
DDC/CEC_GND
1.8P_0402_50V8
1.8P_0402_50V8
DLW21SN900HQ2L-0805_4P CPU_DPB_CTRLDAT_R 16
SDA
1
@ C279
@ C382
CPU_DPB_CTRLCLK_R 15
L20 @ 14 SCL
1 2 HDMI_CEC 13 Reserved
2
9NH_0402HS-9N0EJTS_5% TMDSB_CON_CLK# 12 CEC 20
11 CK- GND 21
TMDSB_CON_CLK 10 CK_shield GND 22
TMDSB_CON_N0 9 CK+ GND 23
8 D0- GND
TMDSB_CON_P0 7 D0_shield
TMDSB_CON_N1 6 D0+
5 D1-
+5V_RUN TMDSB_CON_P1 4 D1_shield
TMDSB_CON_N2 3 D1+
2 D2-
+3.3V_RUN TMDSB_CON_P2 1 D2_shield
D2+
RB751VM-40TE-17_SOD323-2
B 2 B
1
0_0402_5%
LCN_AUF05-1922S10-0019
@ R472
D65
Q120A
1
2
2
1 6 CPU_DPB_CTRLCLK_R 1 2 +5V_HDMI_DDC +3.3V_RUN

<10> CPU_DPB_CTRLCLK
R471 2.2K_0402_5%
5
HDMI_CEC 2 1
10K_0402_5% @ R473
4 3 CPU_DPB_CTRLDAT_R 1 2
<10> CPU_DPB_CTRLDAT
R470 2.2K_0402_5%
Q120B
TMDS_P2_C R465 1 2 470_0402_1% HDMI_OB

TMDS_N2_C R468 1 2 470_0402_1%
TMDS_P1_C R467 1 2 470_0402_1%
+3.3V_RUN TMDS_N1_C R469 1 2 470_0402_1%
TMDS_P0_C R462 1 2 470_0402_1%
TMDS_N0_C R463 1 2 470_0402_1%
TMDS_CLK_C R464 1 2 470_0402_1%
1M_0402_5%
TMDS_CLK#_C R466 1 2 470_0402_1%

2
R475
1
D
+3.3V_RUN R460 1 2 10K_0402_5% 2 Q29

2
G
G L2N7002WT1G_SC-70-3
1
3
3 1 HDMI_HPD_SINK 1 2
<10> DPB_HPD R474 20K_0402_5%
S
Q121
A L2N7002WT1G_SC-70-3
A
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT HDMI CONN
LA-9591P
5 4 3 2 1
+3.3V_RUN_VMM
AUX/DDC SW for DPB to E-DOCK 1
C93
2
0.1U_0402_25V6
U11
1 14
2 1 SW_DPB_AUX_C 2 BE0 VCC 13
D <21> SW_DPB_AUX A0 BE3 D
C94 0.1U_0402_10V7K
DPB_DOCK_AUX 3 12
<34> DPB_DOCK_AUX B0 A3 VMM_DPB_CTRLCLK <21>
4 11
2 1 SW_DPB_AUX#_C 5 BE1 B3 10
<21> SW_DPB_AUX# A1 BE2
C95 0.1U_0402_10V7K
DPB_DOCK_AUX# 6 9
<34> DPB_DOCK_AUX# B1 A2 VMM_DPB_CTRLDAT <21>
7 8
GND B2
PI3C3125LEX_TSSOP14~D
+3.3V_RUN_VMM
100K_0402_5%
1
R60
2
DPB_CA_DET#
BSS138W-7-F_SOT323-3
1
D
DPB_CA_DET 2
<21,34> DPB_CA_DET
Q10
G
S
3
C C
+3.3V_RUN_VMM
AUX/DDC SW for DPC to E-DOCK 1
C97
2
0.1U_0402_25V6
U13
1 14
2 1 SW_DPC_AUX_C 2 BE0 VCC 13
<21> SW_DPC_AUX A0 BE3
C98 0.1U_0402_10V7K
DPC_DOCK_AUX 3 12
<34> DPC_DOCK_AUX B0 A3 VMM_DPC_CTRLCLK <21>
4 11
2 1 SW_DPC_AUX#_C 5 BE1 B3 10
<21> SW_DPC_AUX# A1 BE2
C99 0.1U_0402_10V7K
DPC_DOCK_AUX# 6 9
<34> DPC_DOCK_AUX# B1 A2 VMM_DPC_CTRLDAT <21>
7 8
GND B2
B B
+3.3V_RUN_VMM
100K_0402_5%
1
R56
2
DPC_CA_DET#
1
D
DPC_CA_DET 2
<21,34> DPC_CA_DET
G
S
3
Q6
1 2 DPB_CA_DET
A R120 1M_0402_5% A
1 2 DPC_CA_DET
R121 1M_0402_5%
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT DP SW
LA-9591P
5 4 3 2 1
5 4 3 2 1
D D
+3.3V_RUN
1
PAD-OPEN1x1m
@ PJP2
2
+3.3V_RUN +5V_HDD
+3.3V_RUN_FFS
10U_0603_6.3V6M
0.1U_0402_25V6
1
100K_0402_5%
1 2 DDR_XDP_WAN_SMBDAT
@ R125
R122 10K_0402_5%
Free Fall Sensor
1
1 2 DDR_XDP_WAN_SMBCLK +3.3V_RUN
C101
C102
R123 10K_0402_5%
2
1
100K_0402_5%
U15
LNG3DM FFS_INT2_Q
R126
10
RES
3
1 13
14 VDD_IO RES 15
2
VDD RES
Q19B
16
11 RES 5
<10> HDD_FALL_INT 9 INT 1 5
FFS_INT2
INT 2 GND
12
4
GND
6
7
C 6 SDO/SA0 C
<18,19,31,7,9> DDR_XDP_WAN_SMBDAT SDA / SDI / SDO
Q19A
4
<18,19,31,7,9> DDR_XDP_WAN_SMBCLK SCL/SPC 2 FFS_INT2 2
8 NC 3 <12> FFS_INT2
CS NC
1
LNG3DMTR_LGA16_3X3~D
+3.3V_HDD
1 2 HDD_DEVSLP
@ R188 10K_0402_5%
JSATA1
1
C105 2 1 0.01U_0402_16V7K SATA_PTX_DRX_P1 2 1
<6> SATA_PTX_DRX_P1_C 2
C106 2 1 0.01U_0402_16V7K SATA_PTX_DRX_N1 3
<6> SATA_PTX_DRX_N1_C 4 3
C109 2 1 0.01U_0402_16V7K SATA_PRX_DTX_N1 5 4
<6> SATA_PRX_DTX_N1_C C108 2 1 0.01U_0402_16V7K SATA_PRX_DTX_P1 6 5
<6> SATA_PRX_DTX_P1_C 7 6
8 7
9 8
+3.3V_HDD 9
10
11 10
<12> HDD_DEVSLP 12 11
B HDD_DET# 13 12 B
+5V_HDD +3.3V_HDD <6> HDD_DET# 14 13
@ PJP3 15 14
1 2 +5V_HDD 16 15
+5V_RUN 16
17
17
1000P_0402_50V7K
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
PAD-OPEN1x1m 18
FFS_INT2_Q 19 18
19
1
1
C111
C112
@ C113
C114
20
21 20
22 G1
2
23 G2
24 G3
G4
ACES_50406-02071-001
CONN@
Place near HDD CONN
A A
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT HDD CONN
LA-9591P
5 4 3 2 1
2 1
+3.3V_RUN_AUDIO
+5V_RUN_AUDIO +5V_RUN_AUDIO
1
place close to pin27
0_0603_5%
@ R140
L21
1
0_0805_5%
+VDDA_AVDD1 1 2
0.1U_0402_25V6
10U_0603_6.3V6M
@ R130
+3.3V_RUN_AUDIO +3.3V_RUN_AUDIO PBY160808T-600Y-N_2P
Internal Speakers Header place close to pin38
2
1
1
+DVDD_CORE
C115
C117
+VDDA_AVDD2
2
1U_0603_10V6K
0.1U_0402_25V6
1U_0603_10V6K
0.1U_0402_25V6
10U_0603_6.3V6M
0.1U_0402_25V6
10U_0603_6.3V6M
40 mils trace keep 10 mil spacing CONN@
2
@
JSPK1 place close to pin39 place close to pin45
1
C118
C119
C405
INT_SPK_L+ EMC@ L22 1 2 BLM18PG330SN1_2P INT_SPKR_L+ 1
1
C120
C121
C150
C116
0.1U_0402_25V6
10U_0603_6.3V6M
0.1U_0402_25V6
10U_0603_6.3V6M
INT_SPK_L- EMC@ L23 1 2 BLM18PG330SN1_2P INT_SPKR_L- 2
INT_SPK_R+ EMC@ L24 1 2 BLM18PG330SN1_2P INT_SPKR_R+ 3 2
2
3
1
INT_SPK_R- EMC@ L25 1 2 BLM18PG330SN1_2P INT_SPKR_R- 4 U17
4
C129
C128
C123
C122
5 1 27
6 GND1 DREG_OUT AVDD1 38
2
GND2 AVDD2/HVDD(3.3)
E-T_4280K-F04N-05L 3 45 +VDDA_PVDD
DVDD-IO PVDD2 39
PVDD1 +VREFOUT
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
9 13 AUD_SENSE_A
DVDD Sense A
1
14 AUD_SENSE_B RING2 1 2
Sense B
@ C124
@ C125
@ C126
@ C127
2.2K_0402_5% R187
28 RING2 SLEEVE 1 2
2
PCH_AZ_CODEC_BITCLK 6 LINE1-L/RING2 29 SLEEVE RING2 <35> SLEEVE/RING2 please keep 40 mils trace width 2.2K_0402_5% R197
<6> PCH_AZ_CODEC_BITCLK BIT-CLK LINE1-R/SLEEVE SLEEVE <35>
23
LINE1-VREFO +VREFOUT
PCH_AZ_CODEC_SDOUT 5 1 2
<6> PCH_AZ_CODEC_SDOUT SDATA-OUT 31 C385 10U_0603_6.3V6M AUD_HP_OUT_L/ AUD_HP_OUT_Rplease keep 15 mils trace width
10 HPOUT-L/MIC-CAP 33 AUD_OUT_L 1 2 AUD_HP_OUT_L
B <6> PCH_AZ_CODEC_SYNC SYNC AVSS2/HPOUT-L AUD_HP_OUT_L <35> B
Place R136 close to codec 32 AUD_OUT_R R162 1 2 18_0402_5% AUD_HP_OUT_R +VREFOUT
1 2 PCH_AZ_SDIN0_R 8 HP-OUT-R R166 18_0402_5% AUD_HP_OUT_R <35>
<6> PCH_AZ_CODEC_SDIN0 SDATA-IN
1U_0603_10V4Z
Close to U17 R136 33_0402_5% 40 INT_SPK_L+ 1 2
SPK-L+
@
PCH_AZ_CODEC_RST# 11 41 INT_SPK_L- @ R194 10K_0402_5%
<6> PCH_AZ_CODEC_RST# RESET# SPK-L-
C131
1 2
44 INT_SPK_R+ @ R153 10K_0402_5%
2
SPK-R+ 43 INT_SPK_R- 2 1 1 2
1 2 15 SPK-R- SPKR <12>
I2S_MCLK C145 0.1U_0402_25V6 R147 1K_0402_5%
<34> DAI_12MHZ# EMC_3@ R137 22_0402_5% I2S_MCLK 12 AUD_PC_BEEP 2 1 1 2
1 2 16 PCBEEP BEEP <37>
I2S_BCLK C146 0.1U_0402_25V6 R151 1K_0402_5%
<34> DAI_BCLK# EMC_3@ R139 22_0402_5% I2S_SCLK 2 DMIC_CLK_L 1 2 DMIC_CLK
1 2 I2S_DO 17 GPIO0/DMIC-CLK 4 EMC@ R170 33_0402_5% DMIC_CLK <22>
<34> DAI_DO# Place R142 close to codec I2S_DOUT GPIO1/DMIC-DATA DMIC0 <22>
3@ R142 33_0402_5% 46 1 2
1 2 I2S_LRCLK 18 DMIC1/GPIO2 48 @ R186 0_0402_5%
<34> DAI_LRCK# @ R143 0_0402_5% I2S_LRCK GPIO3
EN_I2S_NB_CODEC# <36>
1 2 I2S_DI# 24 37
<34> DAI_DI @ R144 0_0402_5% I2S_DIN MONO-OUT/CBP DMIC_CLK
Close to U17 pin5 Close to U17 pin6
22P_0402_50V8J
1
19 35 2 1
MIC1-L CBN Place C134 close to Codec
@
PCH_AZ_CODEC_SDOUT PCH_AZ_CODEC_BITCLK C134 2.2U_0603_6.3V6K
C130
20
2
MIC1-R
1
1
47_0402_5%
33_0402_5%
36
CBP/AVSS2
@ R148
@ R149
AUD_NB_MUTE# 47
<36> AUD_NB_MUTE# EAPD/PD Place close to Codec
1U_0603_10V6K
21 +ALC290_LDO_CAP
LDO-CAP 22
JDREF
1
1 2 7 34 +ALC3226_CPVEE place close to pin2
+3.3V_RUN_AUDIO
2
DVSS CPVEE
C410
R150 10K_0402_5% 25 +ALC3226_VREF
VREF
0.1U_0402_10V7K
10P_0402_50V8J
42
2
PVSS 30
MIC1-VREFO
1
1
@ C135
0.1U_0402_25V6
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
20K_0402_1%
10U_0603_6.3V6M
49 26
GND AVSS1
1
1
@ C136
C167
C169
C138
R39
C140
ALC3226-CG_QFN48_7X7
2
2
2
Notes:
2
Keep PVDD supply and speaker traces routed on the DGND plane.
Keep away from AGND and other analog signals
Place closely to Pin 13. AUD_SENSE_A

@ PJP4
39.2K_0402_1%
1 2
place at AGND and DGND plane
1
R152
1 2 PAD-OPEN1x1m
@ C141 0.1U_0402_25V6
3 2
1 2
@ C142 0.1U_0402_25V6
Q20B
6
5
AUD_HP_NB_SENSE <35,36> 1 2
0.1U_0402_25V6
10U_0603_6.3V6M
@ C144 0.1U_0402_25V6
4
2
C137
@ C408
Q20A +5V_RUN_AUDIO
DMN66D0LDW-7_SOT363-6 U18
1
1 14 1 2
+5V_ALW VIN1 VOUT1
2 13 @ C188 0.1U_0402_10V7K
VIN1 VOUT1
1 2 3 12 1 2
<36,37,39> RUN_ON ON1 CT1
@ R154 0_0402_5% C147 470P_0402_50V7K
4 11
VBIAS GND
5 10 1 2
SLEEVE ON2 CT2
Add for solve pop noise and detect issue C148 1000P_0402_50V7K
+3.3V_ALW 6 9
7 VIN2 VOUT2 8
A
+RTC_CELL VIN2 VOUT2 +3.3V_RUN_AUDIO A
0.1U_0402_10V7K
15
GPAD
Place closely to Pin 14
@ C139
TPS22966DPUR_SON14_2X3
1
100K_0402_5%
2
R202
AUD_SENSE_B
3
Q123B
2
1
1
39.2K_0402_1%
20K_0402_1%
5
+3.3V_RUN_AUDIO +3.3V_RUN_AUDIO
R156
R157
6
4
100K_0402_5%
1
1
100K_0402_5%
2
2
R158
2 1 2 PCH_AZ_CODEC_RST#
R159
@ R213 0_0402_5%
Q123A
1
6
1 2 AUD_NB_MUTE#
2
@ R220 0_0402_5%
Realtek feedback
2 5
<36> DOCK_HP_DET
Q21A Q21B
DOCK_MIC_DET <36> Prevent the Noise from Combo Jack
DMN66D0LDW-7_SOT363-6 DMN66D0LDW-7_SOT363-6 while system entry into S3 / S4 /S5
1
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Codec _ALC3226
LA-9591P
2 1
5 4 3 2 1
+3.3V_RUN
4.7U_0603_6.3V6K
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
D D
1
@ C153
C151
C152
C154
U19
12 42 mDP_LANE_N0 C163 1 2 0.1U_0402_10V7K mDP_LANE_N0_C
2
21 VDD D0-A 41 mDP_LANE_P0 C164 1 2 0.1U_0402_10V7K mDP_LANE_P0_C
34 VDD D0+A 40 mDP_LANE_N1 C165 1 2 0.1U_0402_10V7K mDP_LANE_N1_C +3.3V_RUN
VDD D1-A 39 mDP_LANE_P1 C166 1 2 0.1U_0402_10V7K mDP_LANE_P1_C
D1+A 38 mDP_LANE_N2 C168 1 2 0.1U_0402_10V7K mDP_LANE_N2_C
DOCKED 2 D2-A 37 mDP_LANE_P2 C170 1 2 0.1U_0402_10V7K mDP_LANE_P2_C
<21,28,32,36> DOCKED 3 GPU_SEL D2+A 36 mDP_LANE_N3 1 2 mDP_LANE_N3_C
C172 0.1U_0402_10V7K
<10> DDI2_LANE_N0 D0- D3-A
0.1U_0402_16V4Z
4 35 mDP_LANE_P3 C173 1 2 0.1U_0402_10V7K mDP_LANE_P3_C
<10> DDI2_LANE_P0 D0+ D3+A
1
+3.3V_RUN 6 24 mDP_AUX#
<10> DDI2_LANE_N1 D1- AUX-A
@ C383
7 23 mDP_AUX
<10> DDI2_LANE_P1 D1+ AUX+A
1
8 16 mDP_HPD
<10> DDI2_LANE_N2
2
1 2 mDP_AUX#_C 9 D2- HPD_A
IN
<10> DDI2_LANE_P2 D2+
AP2337SA-7 SOT-23
R163 100K_0402_5% 10 33
<10> DDI2_LANE_N3 11 D3- D0-B 32 DP12412_N0 <21>
<10> DDI2_LANE_P3 D3+ D0+B 31 DP12412_P0 <21>
D1-B DP12412_N1 <21>
U50
30
1 2 mDP_HPD 13 D1+B 29 DP12412_P1 <21>
<10> CPU_DPC_AUX# 14 AUX- D2-B 28 DP12412_N2 <21>
R164 100K_0402_5%
GND
OUT
1 2 mDP_AUX_C <10> CPU_DPC_AUX DOCKED 5 AUX+ D2+B 27 DP12412_P2 <21>
R165 100K_0402_5% 18 AUX_HPD_SEL D3-B 26 DP12412_N3 <21>
2 1 mDP_CA_DET <10> DPC_HPD HPD D3+B 19 DP12412_P3 <21>
DP12412_AUX# <21>
3
R167 1M_0402_5% 1 AUX-B 20 +VDISPLAY_VCC
1 2 DPB_MB_P14 17 GND AUX+B 15 DP12412_AUX <21>
R168 5.1M_0402_5% 22 GND HPD_B DP12412_HPD <21>
GND
0.01U_0402_16V7K
43 25 2 1
HGND OE +3.3V_RUN
R161 4.7K_0402_5%
PI3VDP12412ZHEX_TQFN42_9X3P5~D
C171
C C
2
DOCKED function
1 Dock
0 mini DP JmDP1 CONN@

20
19 DP_PWR
mDP_AUX#_C 18 GND 24
mDP_LANE_N2_C 17 AUX_CH_N GND4 23
mDP_AUX_C 16 LANE2_N GND3 22
mDP_LANE_P2_C 15 AUX_CH_P GND2 21
14 LANE2_P GND1
+3.3V_RUN 13 GND
AUX/DDC SW for DPC to Mini DP 1

C411
2
mDP_LANE_N3_C
mDP_LANE_N1_C
mDP_LANE_P3_C
12
11
10
GND
LANE3_N
LANE1_N
0.1U_0402_25V6 mDP_LANE_P1_C 9 LANE3_P
8 LANE1_P
7 GND
U49 DPB_MB_P14 6 GND
1 14 mDP_LANE_N0_C 5 CONFIG2
mDP_AUX 2 1 SW_mDP_AUX_C 2 BE0 VCC 13 mDP_CA_DET 4 LANE0_N
C174 0.1U_0402_10V7K A0 BE3 mDP_LANE_P0_C 3 CONFIG1
mDP_AUX_C 3 12 mDP_HPD 2 LANE0_P
B0 A3 CPU_DPC_CTRLCLK <10> 1 HOT_PLUG
4 11 GND
mDP_AUX# 2 1 SW_mDP_AUX#_C 5 BE1 B3 10 ACON_MAR2F-20K1800
C175 0.1U_0402_10V7K A1 BE2
mDP_AUX#_C 6 9
B1 A2 CPU_DPC_CTRLDAT <10>
B 7 8 B
GND B2
+3.3V_RUN
100K_0402_5%
1
R67
2
mDP_CA_DET#
1
D
mDP_CA_DET 2
Q31
G
S
3
A A
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Mini DP
LA-9591P
5 4 3 2 1
5 4 3 2 1
U21
@ R169 1 2 0_0402_5% LANCLK_REQ#_R 48 13 LAN_TX0+

<12,7> LANCLK_REQ# PLT_LAN_RST# 36 CLK_REQ_N MDI_PLUS0 14 LAN_TX0-
PE_RST_N MDI_MINUS0 +0.9V_LAN
44 17 LAN_TX1+
<7> CLK_PCIE_LAN 45 PE_CLKP MDI_PLUS1 18 LAN_TX1-
<7> CLK_PCIE_LAN# PE_CLKN MDI_MINUS1
PCIE
2 1 PCIE_PRX_GLANTX_P3_C REGCTL_PNP10 1 2
MDI
<11> PCIE_PRX_GLANTX_P3
C179 0.1U_0402_10V7K 38 20 LAN_TX2+ 4.7UH_CBC2012T4R7M_20% L26
PETp MDI_PLUS2
0.1U_0402_10V7K
10U_0603_6.3V6M
2 1 PCIE_PRX_GLANTX_N3_C 39 21 LAN_TX2-
+3.3V_LAN <11> PCIE_PRX_GLANTX_N3 PETn MDI_MINUS2
C176 0.1U_0402_10V7K
1
+3.3V_LAN
C177
C180
1 2 PCIE_PTX_GLANRX_P3_C 41 23 LAN_TX3+
<11> PCIE_PTX_GLANRX_P3 PERp MDI_PLUS3
1 2 TP_LAN_JTAG_TMS C178 0.1U_0402_10V7K 42 24 LAN_TX3-
D
@ R171 10K_0402_5% 1 2 PCIE_PTX_GLANRX_N3_C PERn MDI_MINUS3 D
<11> PCIE_PTX_GLANRX_N3
2
10K_0402_5%
1 2 TP_LAN_JTAG_TCK C181 0.1U_0402_10V7K
1
@ R173
@ R172 10K_0402_5% 1 2 LAN_SMBCLK_R 28 6 VCT_LAN_R1 2 1
<7> LAN_SMBCLK SMB_CLK SVR_EN_N
SMBUS
2 1 LAN_WAKE#_R @ R174 0_0402_5% 31 @ R175 0_0402_5%
@ R176 4.7K_0402_5% 1 2 LAN_SMBDATA_R SMB_DATA 1 +RSVD_VCC3P3_1 R178 2 1 4.7K_0402_5%
<7> LAN_SMBDATA RSVD_VCC3P3_1 +3.3V_LAN
@ R177 0_0402_5%
1 2 LAN_WAKE#_R 2 5
2
1 2 <12,37> LAN_WAKE# @ R179 0_0402_5% LAN_DISABLE#_R 3 LANWAKE_N VDD3P3_IN
<12> PM_LANPHY_ENABLE LAN_DISABLE_N Place C177, C180 and L26 close to U21
@ R180 0_0402_5% SMBus Device Address 0xC8 4 +3.3V_LAN_OUT 2 1
VDD3P3_4 +3.3V_LAN
@ R181 0_0603_5%
<36> LAN_DISABLE#_R
10K_0402_5%
1U_0603_10V6K
15 Pin 6 is SVR_EN in Clarkville
VDD3P3_15
1
@ R182
LOM_ACTLED_YEL# 26 19
LED0 VDD3P3_19 +0.9V_LAN
C182
LOM_SPD100LED_ORG# 27 29
LED1 VDD3P3_29 +0.9V_LAN
LED
LOM_SPD10LED_GRN# 25
2
LED2
47
2
VDD0P9_47 46
VDD0P9_46
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
22U_0805_6.3V6M
@ T92 PAD~D TP_LAN_JTAG_TDI 32 37
@ T93 PAD~D TP_LAN_JTAG_TDO 34 JTAG_TDI VDD0P9_37
JTAG_TDO
1
JTAG
TP_LAN_JTAG_TMS 33 43
JTAG_TMS VDD0P9_43
C183
C184
C185
C186
C187
TP_LAN_JTAG_TCK 35
JTAG_TCK 11
2
VDD0P9_11
XTALO_R 1 2 XTALO 9 40
@ R183 0_0402_5% XTALI 10 XTAL_OUT VDD0P9_40 22
XTAL_IN VDD0P9_22
1
16
VDD0P9_16 8
R206 LAN_TEST_EN 30 VDD0P9_8
TEST_EN Note:
1M_0402_5%
Y3 RES_BIAS 12 7 REGCTL_PNP10
+1.0V_LAN will work at 0.95V to 1.15V
2
3 1 RBIAS CTRL0P9
OUT IN
33P_0402_50V8J
49
VSS_EPAD
1
33P_0402_50V8J
1K_0402_5%
3.01K_0402_1%
4 2
GND GND WGI218LM-SLK3A-B1_QFN48_6X6~D
2
2
C189
R184
R185
25MHZ_18PF_7V25000034
C190
1
2
C C
+3.3V_RUN 2 1
@ 0_0402_5% R145
2 1 LAN_RST# +3.3V_RUN
R331 10K_0402_5% @ C406
2 1
+3.3V_ALW
0.1U_0402_10V7K
5
+3.3V_LAN
1 U22
P
<12> LAN_RST# B 4 PLT_LAN_RST# 1 14 1 2

2 O 2 VIN1 VOUT1 13 C426 0.1U_0402_10V7K
<9> PLTRST_LAN# A VIN1 VOUT1
G
1
100K_0402_5%
@ U20 2 1 3 12 1 2
<36,9> SIO_SLP_LAN#
3
ON1 CT1
@ R25
TC7SH08FU_SSOP5~D @ R196 0_0402_5% C407 470P_0402_50V7K

4 11
+5V_ALW VBIAS GND
1 2 5 10 1 2
<12> 3.3V_HDD_EN
2
@ R129 0_0402_5% ON2 CT2 C429 470P_0402_50V7K

6 9
7 VIN2 VOUT2 8
VIN2 VOUT2 +3.3V_HDD
15
GPAD
0.1U_0402_10V7K
1
@ C428
+3.3V_LAN LAN ANALOG SWITCH
2
+3.3V_LAN
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
@ C198
1
1 2
C192
C193
C194
B B
0.1U_0402_10V7K
2
5
Layout Notice : Place bead as LOM_SPD100LED_ORG# 1
P
B 4
39
30
21
14
close PI3L500 as possible O WLAN_LAN_DISB# <36>

8
4
1
U23 LOM_SPD10LED_GRN# 2
A
G
U24
VDD
VDD
VDD
VDD
VDD
VDD
VDD
38 SW_LAN_TX0+ NL17SZ08DFT2G_SSOP5~D
SW_LAN_TX0+ <35>
3
B0+ 37 SW_LAN_TX0-
B0- SW_LAN_TX0- <35>
LAN_TX0+ 1 2 LAN_TX0+R 2
EMC@ L27 12NH_0603CS-120EJTS_5% A0+ 34 SW_LAN_TX1+
B1+ SW_LAN_TX1+ <35>
LAN_TX0- 1 2 LAN_TX0-R 3 33 SW_LAN_TX1-
A0- B1- SW_LAN_TX1- <35>
EMC@ L28 12NH_0603CS-120EJTS_5%
29 SW_LAN_TX2+
LAN_TX1+ 1 2 LAN_TX1+R 6 B2+ 28 SW_LAN_TX2- SW_LAN_TX2+ <35>
EMC@ L29 12NH_0603CS-120EJTS_5% A1+ B2- SW_LAN_TX2- <35>
LAN_TX1- 1 2 LAN_TX1-R 7 25 SW_LAN_TX3+ Q32A Q33A
A1- B3+ 24 SW_LAN_TX3+ <35>
EMC@ L30 12NH_0603CS-120EJTS_5% SW_LAN_TX3- DMN66D0LDW-7_SOT363-6 DMN66D0LDW-7_SOT363-6
B3- SW_LAN_TX3- <35>
SW_ACTLED_YEL# 1 6 SW_10_GRN# 1 6
LAN_ACTLED_YEL# <35> LED_10_GRN# <35>
LAN_TX2+ 1 2 LAN_TX2+R 9 17 SW_ACTLED_YEL#
EMC@ L31 12NH_0603CS-120EJTS_5% A2+ LEDB0 18 SW_100_ORG#
LAN_TX2- 1 2 LAN_TX2-R 10 LEDB1 41 SW_10_GRN#
2
EMC@ L32 12NH_0603CS-120EJTS_5% A2- LEDB2
36 DOCK_LOM_TRD0+ MASK_BASE_LEDS# MASK_BASE_LEDS#
C0+ DOCK_LOM_TRD0+ <34> MASK_BASE_LEDS# <40>
LAN_TX3+ 1 2 LAN_TX3+R 11 35 DOCK_LOM_TRD0-
A3+ C0- DOCK_LOM_TRD0- <34>
EMC@ L33 12NH_0603CS-120EJTS_5%
LAN_TX3- 1 2 LAN_TX3-R 12 32 DOCK_LOM_TRD1+
A3- C1+ 31 DOCK_LOM_TRD1+ <34> Q33B
EMC@ L34 12NH_0603CS-120EJTS_5% DOCK_LOM_TRD1- Q32B
C1- DOCK_LOM_TRD1- <34>
DMN66D0LDW-7_SOT363-6 DMN66D0LDW-7_SOT363-6
DOCKED 13 27 DOCK_LOM_TRD2+ SW_100_ORG# 4 3 4 3
<21,27,32,36> DOCKED SEL C2+ DOCK_LOM_TRD2+ <34> LED_100_ORG# <35>
26 DOCK_LOM_TRD2-
C2- DOCK_LOM_TRD2- <34>
LOM_ACTLED_YEL# 15 23 DOCK_LOM_TRD3+
DOCK_LOM_TRD3+ <34>
5
5
LOM_SPD100LED_ORG# 16 LEDA0 C3+ 22 DOCK_LOM_TRD3-
42 LEDA1 C3- DOCK_LOM_TRD3- <34>
LOM_SPD10LED_GRN# MASK_BASE_LEDS#
LEDA2 19 DOCK_LOM_ACTLED_YEL#
LEDC0 DOCK_LOM_ACTLED_YEL# <34>
5 20 DOCK_LOM_SPD100LED_ORG#
PD LEDC1 40 DOCK_LOM_SPD100LED_ORG# <34>
DOCK_LOM_SPD10LED_GRN#
LEDC2 DOCK_LOM_SPD10LED_GRN# <34>
A 1: TO DOCK 43 A
PAD_GND
DOCKED
0: TO RJ45
PI3L720ZHEX_TQFN42_9X3P5~D
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT LAN
LA-9591P
5 4 3 2 1
5 4 3 2 1
D D
+3.3V_RUN +3.3V_RUN_TPM
@ PJP5
1 2
+3.3V_RUN_TPM
PAD-OPEN1x1m
ATMEL TPM for E4
0.1U_0402_25V6
4700P_0402_25V7K
1
1
@ C200
U25 +3.3V_RUN_TPM
C201
10
2
VCC_0
2200P_0402_50V7K
2200P_0402_50V7K
2200P_0402_50V7K
0.1U_0402_25V6
5 19
SB3V VCC_1 24
VCC_2
@ C384
1
1
C203
C202
C204
1 2
<7> PCH_TPM_LPC_EN
@ R198 10_0402_5%
2
1 2 SP_TPM_LPC_EN_R 28 12
<36> SP_TPM_LPC_EN LPCPD# V_BAT 13
@ R193 0_0402_5%
LPC_LAD0 26 NBO_13 14
<36,37,7> LPC_LAD0 LPC_LAD1 23 LAD0 NBO_14
<36,37,7> LPC_LAD1 20 LAD1
LPC_LAD2
<36,37,7> LPC_LAD2 LPC_LAD3 17 LAD2
<36,37,7> LPC_LAD3 LAD3 6
GPIO6
21 9
<7> CLK_PCI_TPM_TCM LPC_LFRAME# 22 LCLK TESTBI 8
<36,37,7> LPC_LFRAME# 16 LFRAME# TESTI
C <31,36,37,9> PCH_PLTRST#_EC IRQ_SERIRQ 27 LRESET# C
<12,36,37> IRQ_SERIRQ CLKRUN# 15 SERIRQ
<12,36,37,9> CLKRUN# CLKRUN# 7
NC_7
1 4
2 ATEST_1 GND_4 11
3 ATEST_2 GND_11 18
ATEST_3 GND_18 25
GND_25
AT97SC320412-ABF _TSSOP28
USH CONN
JUSH1
+3.3V_SUS 22
21 GND2
1 2 USH_SMBCLK 20 GND1
R190 2.2K_0402_5% 19 20
1 2 <11> USBP4- 18 19
USH_SMBDAT
<11> USBP4+ 17 18
R191 2.2K_0402_5%
16 17
1 2 USH_PWR_STATE# <37> USH_SMBCLK 15 16
<37> USH_SMBDAT 14 15
R195 1M_0402_5%
B <36> BCM5882_ALERT# 13 14 B
12 13
11 12
+3.3V_SUS 11
10
9 10
8 9
+3.3V_RUN 8
7
+5V_RUN 7
6
<9> PLTRST_USH# 5 6
<36> USH_PWR_STATE# 4 5
+5V_RUN +3.3V_RUN +3.3V_SUS <10> CONTACTLESS_DET# 3 4
2 3
2
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
1
<12> USH_DET# 1
@
CONN@
1
@
C208
C207
ACES_50506-02041-P01
C206
2
Close to JUSH1
A A
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT USH & TPM
LA-9591P
5 4 3 2 1
A B C D E
C215 close to U27.9

+3.3V_RUN
C213 C214 close to
U27.35
1 2 +3.3V_RUN_AIN
L35 BLM15AG601SN1D_2P
+3.3V_RUN
4.7U_0603_6.3V6K
0.1U_0402_25V6
0.1U_0402_25V6
1
1
C213
C214
C215
2
2
0.1U_0402_25V6
4.7U_0603_6.3V6K
0.1U_0402_25V6
1
1
1 1
C210
C211
C212
2
2
C210 close to U27.42
C211 C212 close to +3.3V_RUN
U27.23
U27
+1.2V_LDO
4.7U_0603_6.3V6K
0.1U_0402_25V6
4.7U_0603_6.3V6K
0.1U_0402_25V6
9 12 +AUX_LDO
27
PE_33VCCAIN
UHSII_33VCCAIN/NC
OZ777FJ2LN AUX_LDO_CAP
2
C224
C219
C225
C226
25 +SD_IO_LDO
SD_IO_LDO_CAP
4.7U_0603_6.3V6K
0.1U_0402_25V6
0.1U_0402_25V6
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
0.1U_0402_25V6
1U_0402_6.3V6K
42 2
1
SD_33VCCD
2
@ C221
C223
C217
C218
C220
C216
C222
23
SD_SKT_33VIN
1
1
13 22 1
AUX _33VIN SD_SKT_33VOUT +3.3V_RUN_CARD
11 24 +1.8V_RUN_CARD
MAIN_LDO_VIN SD_SKT_18VOUT
+1.2V_LDO 10
L36 MAIN_LDO_12VOUT
1 2 +1.2V_LDO_AIN
BLM15AG601SN1D_2P 41
CORE_12VCCD
4.7U_0603_6.3V6K
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
20 SDWP
36 SD_WPI 21 SD/MMCCD#
UHSII_12VCCAIN/NC SD_CD#
2
2
@ C232
31
UHSII_12VCCAIN/NC
C230
C231
C233
C234
28 43 SD/MMCCLK_R R230 1 EMC@ 2 10_0402_5% SD/MMCCLK
UHSII_12VCCAIN/NC SD_CLK 45 SD/MMCCMD
1
1
SD_CMD
5P_0402_50V8C
1
PE_12VCCAIN 39
MMC_D7
1
2 2
@ C255
40
MMC_D6 44
1 2 PE_REXT 4 MMC_D5 46
2
R205 191_0402_1% PE_REXT MMC_D4 47 SD/MMCDAT3 @ R410 1 2 0_0402_5% SD/MMCDAT3_R
C235 1 2 0.1U_0402_10V7K PCIE_PTX_MMIRX_P5_C 6 SD_D3 48 SD/MMCDAT2 @ R341 1 2 0_0402_5% SD/MMCDAT2_R
<11> PCIE_PTX_MMIRX_P5 PE_RXP SD_D2
C236 1 2 0.1U_0402_10V7K PCIE_PTX_MMIRX_N5_C 5 37 SD/MMCDAT1
<11> PCIE_PTX_MMIRX_N5 PE_RXM SD_D1 38 SD/MMCDAT0 EMI solution for SD card EMI depop location
C237 1 2 0.1U_0402_10V7K PCIE_PRX_MMITX_P5_C 7 SD_D0
<11> PCIE_PRX_MMITX_P5 C238 1 2 0.1U_0402_10V7K PCIE_PRX_MMITX_N5_C 8 PE_TXP 29
<11> PCIE_PRX_MMITX_N5 PE_TXM SD_RCLK_M/NC 30
2 SD_RCLK_P/NC 32 SD_UHS2_D1P
<7> CLK_PCIE_MMI# PE_REFCLKM SD_D1P/NC
3 33 SD_UHS2_D1N
<7> CLK_PCIE_MMI PE_REFCLKP SD_D1M/NC 34 SD_UHS2_D0N
PE_RST# 15 SD_D0M/NC 35 SD_UHS2_D0P
PE_RST#_GATE# SD_D0P/NC +3.3V_RUN_CARD +1.8V_RUN_CARD
14 26 R211 1 2 4.7K_0402_1%
<12> MEDIACARD_PWREN MAIN_LDO_EN SD_REXT/NC
0.1U_0402_25V6
0.1U_0402_25V6
4.7U_0603_6.3V6K
16
<12> MEDIACARD_IRQ# DEV_WAKE#
@ C228
17 19
<7> MMICLK_REQ# CLKREQ# LED#
@ C227
@ C229
IO_LDOSEL 18 49
2
IO0_LDOSEL GND
OZ777FJ2LN_QFN48_6X6
please routing daisy chain

1. from U27.38 (SD_D0) -> U27.32 (SD_RCLK_P) -> L46.4 C227 near U27.22 C228 C229 near U27.24
+3.3V_RUN
2. From U27.37 (SD_D1) -> U27.33 (SD_RCLK_N) -> L46.1
R231,R297,R306,R315,R333,R337 for EMI solution
1
100K_0402_5%
R231 1 2 @ 0_0402_5%
3 3
R212
L46 @
SD/MMCDAT0 4 3 SD/MMCDAT0_D
2
4 3
IO_LDOSEL SD/MMCDAT1 1 2 SD/MMCDAT1_D

1 2 JSD1 CONN@
100K_0402_5%
DLW21SN900SQ2L-0805_4P +3.3V_RUN_CARD 4
VDD/VDD1
1
+1.8V_RUN_CARD 14
VDD2
@ R214
SD/MMCCMD 2
R297 1 2 @ 0_0402_5% +3.3V_RUN_CARD +1.8V_RUN_CARD SD/MMCCLK 5 CMD
CLK
SD/MMCCD# 18
2
CARD DETECT
0.1U_0402_25V6
R306 1 2 @ 0_0402_5% SDWP 19
WRITE PROTEC
1
0.1U_0402_25V6
4.7U_0603_6.3V6K
0.1U_0402_25V6
4.7U_0603_6.3V6K
1M_0402_5%
1
R493
SD/MMCDAT0_D 7
DAT0/RCLK+
1
@ C240
C256
L47 @ SD/MMCDAT1_D 8
DAT1/RCLK-
C239
C246
C247
SD_UHS2_D0P 4 3 SD_UHS2_D0P_D SD/MMCDAT2_R 9
2
4 3 SD/MMCDAT3_R 1 DAT2
2
1 2 SD_UHS2_D0P_D 11 CD/DAT3
@ R443 0_0402_5% SD_UHS2_D0N 1 2 SD_UHS2_D0N_D SD_UHS2_D0N_D 12 D0+
1 2 SD_UHS2_D1P_D 16 DO-
+3.3V_RUN DLW21SN900SQ2L-0805_4P SD_UHS2_D1N_D 15 D1+ 20
D1- GND1 21
C341 @ 3 GND2 22
2 1 R315 1 2 @ 0_0402_5% 6 VSS1 GND3 23
10 VSS2 GND4 24
Near to JSD1 VSS3 GND5
5
0.1U_0402_25V6 13 25
1 17 VSS4 GND6 26
P
<9> PLTRST_MMI# B VSS5 GND7

4 PE_RST# R333 1 2 @ 0_0402_5%
2 O ALPS_SCDADA0101_NR
<12> MEDIACARD_RST# A
G
100K_0402_5%
@U26
@ U26 L48 @
3
TC7SH08FU_SSOP5~D SD_UHS2_D1P 1 2 SD_UHS2_D1P_D

4 1 2 4
@ R27
SD_UHS2_D1N 4 3 SD_UHS2_D1N_D
4 3
2
DLW21SN900SQ2L-0805_4P
R337 1 2 @ 0_0402_5%
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Card Reader
LA-9591P
A B C D E
5 4 3 2 1
Mini WWAN/GPS/LTE/mSATA/PP H=4 Mini WLAN/WIiGi/BT H=4

+3.3V_WLAN +3.3V_WLAN
+3.3V_mSATA_WWAN +3.3V_mSATA_WWAN JMINI1

JMINI2 PCIE_WAKE# 1 2
PCIE_WAKE# 1 2 3 1 2 4
<37> PCIE_WAKE# 3 1 2 4 5 3 4 6
5 3 4 6 7 5 6 8 C241
MINI1CLK_REQ# 7 5 6 8 <12,7> MINI2CLK_REQ# 9 7 8 10 1 2
<12,7> MINI1CLK_REQ# 7 8 +SIM_PWR 9 10
9 10 UIM_DATA 11 12
9 10 <7> CLK_PCIE_MINI2# 11 12
CLK_PCIE_MINI1# 11 12 UIM_CLK 13 14 MSDATA 4700P_0402_25V7K
<7> CLK_PCIE_MINI1# 11 12 <7> CLK_PCIE_MINI2 13 14
CLK_PCIE_MINI1 13 14 UIM_RESET 15 16
<7> CLK_PCIE_MINI1 13 14 15 16 HOST_DEBUG_TX <37>
15 16 UIM_VPP 17 18
17 15 16 18 <36,37> EC5048_TX 19 17 18 20 WLAN_RADIO_DIS#_R
D 19 17 18 20 <37> MSCLK 21 19 20 22 MINI_CARD_RST# D
19 20 WWAN_RADIO_DIS# <36> 21 22
21 22 MINI_CARD_RST# PCIE_PRX_WLANTX_N4 23 24
SATA_PRX_MSATATX_P3 23 21 22 24 <11> PCIE_PRX_WLANTX_N4 PCIE_PRX_WLANTX_P4 25 23 24 26
<6> SATA_PRX_MSATATX_P3 SATA_PRX_MSATATX_N3 25 23 24 26 <11> PCIE_PRX_WLANTX_P4 27 25 26 28
<6> SATA_PRX_MSATATX_N3 27 25 26 28 29 27 28 30
29 27 28 30 WWAN_SMBCLK C242 1 2 0.1U_0402_10V7K PCIE_PTX_WLANRX_N4_C 31 29 30 32 WIGIG60GHZ_DIS#_R
29 30 <11> PCIE_PTX_WLANRX_N4 31 32
C244 1 2 0.1U_0402_10V7K SATA_PTX_mSATARX_N3_C 31 32 WWAN_SMBDAT C243 1 2 0.1U_0402_10V7K PCIE_PTX_WLANRX_P4_C 33 34
<6> SATA_PTX_MSATARX_N3 31 32 <11> PCIE_PTX_WLANRX_P4 33 34
C245 1 2 0.1U_0402_10V7K SATA_PTX_mSATARX_P3_C 33 34 35 36
<6> SATA_PTX_MSATARX_P3 33 34 35 36 USBP2- <11>
35 36 37 38
35 36 USBP6- <11> <12> CPPE# 37 38 USBP2+ <11>
37 38 39 40
37 38 USBP6+ <11> 39 40 CPUSB# <12>
39 40 41 42 WIMAX_LED#
41 39 40 42 LED_WWAN_OUT# 43 41 42 44 WLAN_LED#
43 41 42 44 45 43 44 46 BT_LED#
43 44 mSATA_DEVSLP <12> <7> PCH_CL_CLK1 45 46
45 46 47 48 1 2
45 46 <7> PCH_CL_DATA1 47 48 MSDATA <37>
47 48 @ R223 1 2 0_0402_5% 49 50 @ R222 0_0402_5%
47 48 <7> PCH_CL_RST1# 49 50
49 50 BT_RADIO_DIS#_R 51 52
51 49 50 52 51 52
<36> HW_GPS_DISABLE2# 51 52 53 54
53 54 GND1 GND2
GND1 GND2
LCN_DAN08-52406-0500
LCN_DAN08-52406-0500 CONN@
CONN@
+3.3V_mSATA_WWAN +3.3V_WLAN
1 2
+3.3V_mSATA_WWAN @ R215 0_0402_5%
1 2 mSATA_DEVSLP +3.3V_mSATA_WWAN
0.1U_0402_25V6
0.047U_0402_16V4Z
0.047U_0402_16V4Z
0.1U_0402_25V6
0.1U_0402_25V6
4.7U_0603_6.3V6K
@ R160 10K_0402_5% 1 2 WLAN_RADIO_DIS#_R
<36> WLAN_RADIO_DIS#
0.047U_0402_16V4Z
0.047U_0402_16V4Z
33P_0402_50V8J
22U_0805_6.3V6M
33P_0402_50V8J
150U_B2_6.3VM_R35M
150U_B2_6.3VM_R35M
D12
1
2.2K_0402_5%
2.2K_0402_5%
@C257
RB751S40T1G_SOD523-2
1
1
@ R216
@ R217
3@ C253
C258
C259
C260
C261
C262
1
@ C254
+ + 1 2
2
C248
C249
C250
C251
C252
@ R224 0_0402_5%
2
1 2 WIGIG60GHZ_DIS#_R
<36> WIGIG60GHZ_DIS#
2
2 1 WWAN_SMBCLK D13
<18,19,25,7,9> DDR_XDP_WAN_SMBCLK
@ R218 0_0402_5% RB751S40T1G_SOD523-2
2 1 WWAN_SMBDAT
<18,19,25,7,9> DDR_XDP_WAN_SMBDAT
@ R219 0_0402_5% 1 2
C @ R225 0_0402_5% C
1 2 BT_RADIO_DIS#_R
<36> BT_RADIO_DIS#
D14
RB751S40T1G_SOD523-2 Primary Power Aux Power
PWR Voltage
Rail Tolerance
Peak Normal Normal
+3.3V +-9% 1000 750

250 (Wake enable)
+3.3Vaux +-9% 330 250 5 (Not wake enable)
SIM Card Push-Push

+SIM_PWR
1
JSIM1 CONN@
VCC
R50
1 2 MCARD_WWAN_PWREN
100K_0402_5%
LED control circuit
UIM_RESET 2 11 1 2 AUX_EN_WOWL
RST GND_2
1U_0402_6.3V6K
UIM_CLK 3 12 R51 100K_0402_5%

CLK GND_3
3@ C263
4 13
D+ GND_4
1
5 14 +3.3V_WLAN
B UIM_VPP 6 GND_1 GND_5 15 B
UIM_DATA 7 VPP GND_6 16 +3.3V_ALW +3.3V_mSATA_WWAN
2
8 I/O GND_7 17 U3
9 D- GND_8 18 1 14 1 2
DET GND_9 VIN1 VOUT1
100K_0402_5%
100K_0402_5%
100K_0402_5%
10 2 13 @ C425 0.1U_0402_10V7K
COM VIN1 VOUT1
2
R229
R227
R228
3 12 C427 1 2
<36> MCARD_WWAN_PWREN ON1 CT1
T-SOL_159-1000302602 470P_0402_50V7K
4 11
+5V_ALW VBIAS GND
5
1
1
5 10 1 2
<36> AUX_EN_WOWL ON2 CT2 C409 470P_0402_50V7K WIMAX_LED# 4 3
WIRELESS_LED# <36,40>
6 9
7 VIN2 VOUT2 8 Q22B
VIN2 VOUT2 +3.3V_WLAN
2
@ U28 DMN66D0LDW-7_SOT363-6
15 0.1U_0402_10V7K
GPAD
1
@ C422 WLAN_LED# 1 6
UIM_RESET 1 6 UIM_CLK TPS22966DPUR_SON14_2X3
Q22A
2
2
2 5
+SIM_PWR
BT_LED# 1 6
UIM_VPP 3 4 UIM_DATA Q30A

@ R232 1 2 0_0402_5% DMN66D0LDW-7_SOT363-6
33P_0402_50V8J
33P_0402_50V8J
33P_0402_50V8J
33P_0402_50V8J
+3.3V_mSATA_WWAN
1
+3.3V_RUN
@ C264
@ C265
@ C266
@ C267
SRV05-4.TCT_SOT23-6~D
@ C338
2
1 2
2
100K_0402_5%
0.1U_0402_25V6
5
R226
1
P
<29,36,37,9> PCH_PLTRST#_EC B
5
4 MINI_CARD_RST#
1
2 O
<12,6> MPCIE_RST# A
G
100K_0402_5%
LED_WWAN_OUT# 4 3
1
@ U30
3
@ R26
TC7SH08FU_SSOP5~D Q30B
A A
2
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Mini Card
LA-9591P
5 4 3 2 1
5 4 3 2 1
D D
+3.3V_SUS
4.7U_0603_6.3V6K
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
U33
3
VDD
1
@ C419
@ C418
@ C417
9 31
VDD TX+A SW_USB3TP3 <33>
C420
C415
C414
C416
12 30
C 16 VDD TX-A 27 SW_USB3TN3 <33> C
2 SW_USB3RP3 <33>
2
20 VDD RX+A 26
29 VDD RX-A 19 SW_USB3RN3 <33>
VDD D+A 18 SW_USBP5+ <33>
D-A 17 SW_USBP5- <33>
USB_IDA
25
1 TX+B 24 DOCK_USB3TP3 <34>
<11> USB3TP3 2 TX+ TX-B 23 DOCK_USB3TN3 <34>
<11> USB3TN3 4 TX- RX+B 22 DOCK_USB3RP3 <34>
<11> USB3RP3 5 RX+ RX-B 15 DOCK_USB3RN3 <34>
<11> USB3RN3 6 RX- D+B 14 DOCK_USBP5+ <34>
<11> USBP5+ 7 D+ D-B 13 DOCK_USBP5- <34>
<11> USBP5- 8 D- USB_IDB
USB_ID
11
OE#
10 21
<21,27,28,36> DOCKED 32 SS_SEL GND 28
HS_SEL GND 33
HGND
PI3USB3102ZLEX_TQFN32_6X3
check port mapping

DOCKED function
1 Dock
B B
0 M/B
A A
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT USB SW
LA-9591P
5 4 3 2 1
5 4 3 2 1
+USB_PWR
JUSB2 CONN@
L37 EMC@ D15 EMC@ 1
VBUS
150U_D2_6.3VY_R15M
4 3 USB3RN3_D- USB3RN3_D- 1 9 USB3RN3_D- USBP5_D- 2
<32> SW_USB3RN3 4 3 D-
USBP5_D+ 3
USB3RP3_D+ 2 8 USB3RP3_D+ 4 D+
GND
1
100U_1206_6.3V6M
0.1U_0402_25V6
1 2 USB3RP3_D+ USB3RN3_D- 5
<32> SW_USB3RP3 1 2 SSRX-
1
@ C280
USB3TN3_D- 4 7 USB3TN3_D- + USB3RP3_D+ 6 10
SSRX+ GND
C86
C281
DLW21SN900HQ2L-0805_4P 7 11
GND GND
2
USB3TP3_D+ 5 6 USB3TP3_D+ USB3TN3_D- 8 12
2
SSTX- GND
D16 EMC@
D 1 2 USB3TP3_D+ 9 13 D
@ R235 0_0402_5% SSTX+ GND
1 2 SANTA_373070-1
@ R236 0_0402_5% 3
TVWDF1004AD0_DFN9
1
L38 EMC@ L39 EMC@
<32> SW_USB3TN3 2 1 SW_USB3TN3_C 4 3 USB3TN3_D- 1 2 USBP5_D+
4 3 <32> SW_USBP5+ 1 2 +USB_PWR
C282 0.1U_0402_10V7K +5V_ALW
U32
<32> SW_USB3TP3 2 1 SW_USB3TP3_C 1 2 USB3TP3_D+ 4 3 USBP5_D- 1 8
1 2 <32> SW_USBP5- 4 3 GND VOUT
C283 0.1U_0402_10V7K 2 7
DLW21SN900HQ2L-0805_4P DLW21HN900SQ2L_4P 3 VIN VOUT 6
VIN VOUT
10U_0603_6.3V6M
0.1U_0402_25V6
4 5 USB_OC2# <11,12>
<36> ESATA_USB_PWR_EN# EN FLG
1 2 1 2
1
@ R237 0_0402_5% @ R238 0_0402_5% G547I2P81U_MSOP8
C284
C285
1 2 1 2
@ R239 0_0402_5% @ R240 0_0402_5%
2
C C
+5V_ALW
2
100K_0402_5%
R243
1
PWRSHARE_EN#
1 2
<36> USB_PWR_SHR_VBUS_EN
L2N7002WT1G_SC-70-3
@ R241 0_0402_5%
1
U39 D
1 2 SB# 8 1 PWRSHARE_EN 2
<36> USB_PWR_SHR_EN# CB CEN
Q7
@ R242 0_0402_5% SW_USBP0- 7 2 PS_USBP0_D- G
SW_USBP0+ 6 TDM DM 3 PS_USBP0_D+ S
3
5 TDP DP 4 SEL
+5V_ALW VDD SELCDP 9
+3.3V_ALW Thermal Pad
support APR/SPR/LIO Dock +5V_USB_CHG_PWR
SLGC55594AVTR_TDFN8_2X2
U36
0.1U_0402_25V6
10 1 SW_USBP0+ JUSB1 CONN@
VCC 1D+
1
9 2 SW_USBP0- 1
<36> DOCKED_LIO_EN S 1D- VBUS
0.1U_0402_25V6
C287
8 3 USBP0_D- 2
<11> USBP0+ D+ 2D+ DOCK_USBP0+ <34> D-
1
150U_D2_6.3VY_R15M
7 4 USBP0_D+ 3
<11> USBP0- DOCK_USBP0- <34>
D- 2D- 2 +5V_ALW D+
C322
100U_1206_6.3V6M
0.1U_0402_25V6
6 5 4
OE# GND GND
1
USB3RN2_D- 5
2
StdA-SSRX-
1
@ C290
NX3DV221GM_XQFN10U10_2X1P55 SEL 1 2 + USB3RP2_D+ 6 10
StdA-SSRX+ GND
C89
C291
10K_0402_5% R244 7 11
USB3TN2_D- 8 GND-DRAIN GND 12
2
StdA-SSTX- GND
3
USB3TP2_D+ 9 13
check port mapping StdA-SSTX+ GND
D18 EMC@
B TAITW_PUBAU4-09FLBS1NN4H0 B
DOCKED_LIO_EN function
1 Dock
0 M/B
1
D17 EMC@
L40 EMC@ USB3RN2_D- 1 9 USB3RN2_D-
4 3 USB3RN2_D-
<11> USB3RN2 4 3 USB3RP2_D+ 2 8 USB3RP2_D+
1 2 USB3RP2_D+ USB3TN2_D- 4 7 USB3TN2_D- +5V_ALW +5V_USB_CHG_PWR

<11> USB3RP2 1 2 U35
DLW21SN900HQ2L-0805_4P USB3TP2_D+ 5 6 USB3TP2_D+ 1 8
2 GND VOUT 7
1 2 3 VIN VOUT 6
VIN VOUT
10U_0603_6.3V6M
0.1U_0402_25V6
@ R246 0_0402_5% PWRSHARE_EN# 4 5 USB_OC0# <11>
1 2 3 EN FLG
1
C288
C289
@ R247 0_0402_5% G547I2P81U_MSOP8
TVWDF1004AD0_DFN9
2
L42 EMC@
L41 EMC@ PS_USBP0_D+ 1 2 USBP0_D+
2 1 USB3TN2_C 4 3 USB3TN2_D-
<11> USB3TN2 4 3
C292 0.1U_0402_10V7K
PS_USBP0_D- 4 3 USBP0_D-
2 1 USB3TP2_C 1 2 USB3TP2_D+
<11> USB3TP2 1 2
C293 0.1U_0402_10V7K CMM0805-120Y-N_4P
A A
1 2
1 2 @ R249 0_0402_5%
@ R248 0_0402_5% 1 2
1 2 @ R251 0_0402_5%
@ R250 0_0402_5%
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT USB3.0
LA-9591P
5 4 3 2 1
5 4 3 2 1
JDOCK1 CONN@
DOCK_DET_1 1 2 DOCK_AC_OFF
3 1 2 4 DOCK_AC_OFF <48>
<28> DOCK_LOM_SPD10LED_GRN# DPC_CA_DET 5 3 4 6 DPB_CA_DET DOCK_LOM_SPD100LED_ORG# <28>
<21,24> DPC_CA_DET 7 5 6 8 DPB_CA_DET <21,24>
C302 2 1 0.1U_0402_10V7K DPC_LANE_P0_C EMC@ R259 1 2 33_0402_5% DPC_DOCK_LANE_P0 9 7 8 10 DPB_DOCK_LANE_P0 EMC@ R260 1 2 33_0402_5% DPB_LANE_P0_C C294 2 1 0.1U_0402_10V7K
D <21> DPC_LANE_P0 9 10 DPB_LANE_P0 <21> D
C295 2 1 0.1U_0402_10V7K DPC_LANE_N0_C EMC@ R252 1 2 33_0402_5% DPC_DOCK_LANE_N0 11 12 DPB_DOCK_LANE_N0 EMC@ R261 1 2 33_0402_5% DPB_LANE_N0_C C296 2 1 0.1U_0402_10V7K
<21> DPC_LANE_N0 13 11 12 14 DPB_LANE_N0 <21>
<21> DPC_LANE_P1 15 16 DPB_LANE_P1 <21>
DPC_DOCK_AUX 33 31 32 34 DPB_DOCK_AUX
<24> DPC_DOCK_AUX DPC_DOCK_AUX# 35 33 34 36 DPB_DOCK_AUX# DPB_DOCK_AUX <24>
<24> DPC_DOCK_AUX# 37 35 36 38 DPB_DOCK_AUX# <24>
DPC_DOCK_HPD 39 37 38 40 DPB_DOCK_HPD
<21> DPC_DOCK_HPD 39 40 DPB_DOCK_HPD <21>
0.033U_0402_16V7K
41 42
+NBDOCK_DC_IN_SS 41 42 ACAV_DOCK_SRC# <48>
0.033U_0402_16V7K
43 44
43 44
@
BLUE_DOCK 45 46
<21> BLUE_DOCK 45 46 DAT_DDC2_DOCK <21>
C311
47 48
47 48 CLK_DDC2_DOCK <21>
@ C310
49 50
2
51 49 50 52
2
RED_DOCK 53 51 52 54 SATA_PRX_DKTX_P0 2 1
Close to DOCK <21> RED_DOCK 53 54 SATA_PRX_DKTX_P0_C <6> Close to DOCK
55 56 SATA_PRX_DKTX_N0 C312 2 1 0.01U_0402_16V7K
Its for Enhance ESD on 57 55 56 58 C313 0.01U_0402_16V7K
SATA_PRX_DKTX_N0_C <6> Its for Enhance ESD on dock
dock issue. GREEN_DOCK 59 57 58 60 SATA_PTX_DKRX_P0 1 2 issue.
<21> GREEN_DOCK 61 59 60 62 SATA_PTX_DKRX_P0_C <6>
SATA_PTX_DKRX_N0 C314 1 2 0.01U_0402_16V7K
63 61 62 64 C315 0.01U_0402_16V7K SATA_PTX_DKRX_N0_C <6>
65 63 64 66 DOCK_USBP0_D+ 2 1
<21> HSYNC_DOCK 67 65 66 68 2 1 DOCK_USBP0+ <33>
DOCK_USBP0_D-
<21> VSYNC_DOCK 69 67 68 70
DPC_DOCK_HPD
71 69 70 72 3 4
<37> CLK_MSE 73 71 72 74 DOCK_USBP5+ <32> 3 4 DOCK_USBP0- <33>
C <37> DAT_MSE 75 73 74 76 DOCK_USBP5- <32> C
DLW21SN900SQ2L-0805_4P
75 76
1
100K_0402_5%
77 78 @ L43
<26> DAI_BCLK# 79 77 78 80 CLK_KBD <37> 2 1
<26> DAI_LRCK# 81 79 80 82 DAT_KBD <37>
@ R269 0_0402_5%
83 81 82 84 2 1
<26> DAI_DI 83 84 DOCK_USB3RN3 <32>
R268
85 86 @ R270 0_0402_5%
<26> DAI_DO# DOCK_USB3RP3 <32>
2
87 85 86 88
87 88 EMI solution for E-Docking USB
89 90
<26> DAI_12MHZ# 91 89 90 92 DOCK_USB3TN3 <32>
93 91 92 94 DOCK_USB3TP3 <32> DPB_DOCK_HPD
95 93 94 96
97 95 96 98
<36> D_LAD0 97 98 BREATH_LED# <36,40>
100K_0402_5%
99 100
<36> D_LAD1 99 100 DOCK_LOM_ACTLED_YEL# <28>
1
101 102
103 101 102 104
<36> D_LAD2 105 103 104 106 DOCK_LOM_TRD0+ <28>
<36> D_LAD3 105 106 DOCK_LOM_TRD0- <28>
R271
107 108
109 107 108 110
<36> D_LFRAME#
2
111 109 110 112 DOCK_LOM_TRD1+ <28> +3.3V_ALW
<36> D_CLKRUN# 113 111 112 114 DOCK_LOM_TRD1- <28> +LOM_VCT
115 113 114 116
<36> D_SERIRQ 115 116
1U_0402_6.3V6K
117 118 DOCK_DET# 1 2
<36> D_DLDRQ1# 117 118 +LOM_VCT
119 120 10K_0402_5% R272
119 120
@ C316
121 122
<7> CLK_PCI_DOCK 123 121 122 124 DOCK_LOM_TRD2+ <28>
125 123 124 126 DOCK_LOM_TRD2- <28>
2
127 125 126 128
<37> DOCK_SMB_CLK 129 127 128 130 DOCK_LOM_TRD3+ <28>
<37> DOCK_SMB_DAT 131 129 130 132 DOCK_LOM_TRD3- <28>
133 131 132 134
<36,41,48> DOCK_SMB_ALERT# 135 133 134 136 DOCK_DCIN_IS+ <47>
<41> DOCK_PSID 137 135 136 138 DOCK_DCIN_IS- <47>
B 139 137 138 140 B
<37> DOCK_PWR_BTN# 141 139 140 142 DOCK_POR_RST# <37>
D19
SLICE_BAT_PRES# 143 141 142 144 DOCK_DET_R# 1 2
<36,41,48> SLICE_BAT_PRES# 143 144 DOCK_DET# <36,48>
145 148 RB751S40T1G_SOD523-2
146 GND1 GND2 149
+DOCK_PWR_BAR PWR1 PWR2 +DOCK_PWR_BAR
147 150
PWR1 PWR2
3
2
4.7U_0805_25V6-K
0.1U_0603_50V7K
L30ESD24VC3-2_SOT23-3
0.1U_0603_50V7K
151 157
Shield_G Shield_G
1
D20 @
152 158
Shield_G Shield_G
1
1
@ CE7
153 159
154 Shield_G Shield_G 160
2
Shield_G Shield_G
C317
C318
155 161
2
156 Shield_G Shield_G 162

Shield_G Shield_G
DAI_12MHZ# DAI_BCLK# CLK_PCI_DOCK
WD2F144WB7
1
10_0402_1%
10_0402_1%
33_0402_5%
JAE_WD2F144WB7-DT
@ RE4
@ RE5
@ R273 12P_0402_50V8J
2
2
4.7P_0402_50V8C
4.7P_0402_50V8C
1
1
@ CE8
@ CE9
@ C319
2
2
EMI depop location
A A
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT E-Dock
LA-9591P
5 4 3 2 1
5 4 3 2 1
T94
SW_LAN_TX1- 1 1:1 24 NB_LAN_TX1-

<28> SW_LAN_TX1- TD1+ TX1+
+3.3V_LAN
SW_LAN_TX1+ 2
D <28> SW_LAN_TX1+ TD1- 23 NB_LAN_TX1+ D
TX1-
3 22 Z2805
TDCT1 TXCT1
470P_0402_50V7K
0.1U_0402_10V7K
1
C321
4 21 Z2807
TDCT2 TXCT2
0.47U_0603_10V7K
0.47U_0603_10V7K
C320
SW_LAN_TX0- 5 1:1 20 NB_LAN_TX0-
<28> SW_LAN_TX0- TD2+ TX2+
RJ45 LOM circuit
2
1
1
C323
C324
+3.3V_LAN:20mils
2
SW_LAN_TX0+ 6 19 NB_LAN_TX0+
<28> SW_LAN_TX0+ TD2- TX2-
JLOM1 CONN@
1 2 LAN_ACTLED_YEL_R# 10
<28> LAN_ACTLED_YEL# Yellow LED-
R274 150_0402_5%
SW_LAN_TX3- 7 1:1 18 NB_LAN_TX3- 9
<28> SW_LAN_TX3- TD3+ TX3+ Yellow LED+
NB_LAN_TX3- 8
PR4-
SW_LAN_TX3+ 8 NB_LAN_TX3+ 7
<28> SW_LAN_TX3+ TD3- 17 NB_LAN_TX3+ PR4+
TX3- NB_LAN_TX1- 6
PR2-
9 16 Z2806 NB_LAN_TX2- 5
TDCT3 TXCT3 PR3-
NB_LAN_TX2+ 4
10 15 Z2808 PR3+
TDCT4 TXCT4
75_0402_1%
75_0402_1%
75_0402_1%
75_0402_1%
0.47U_0603_10V7K
0.47U_0603_10V7K
SW_LAN_TX2-11 1:1 14 NB_LAN_TX2- NB_LAN_TX1+ 3

<28> SW_LAN_TX2- TD4+ TX4+ PR2+
C NB_LAN_TX0- 2 C
PR1-
1
15
GND
C325
C326
NB_LAN_TX0+ 1
SW_LAN_TX2+12 13 NB_LAN_TX2+ PR1+ 14
<28> SW_LAN_TX2+
2
TD4- TX4- 1 2 LED_10_GRN_R# 11 GND

<28> LED_10_GRN# Green LED-
R275 150_0402_5%
1 2 LED_100_ORG_R# 13
<28> LED_100_ORG# Orange LED-
1
350uH_IH-115-F R276 150_0402_5%
12
Green-Orange LED+
rev1
SANTA_130456-341
R277 2
R278 2
R279 2
R280 2
GND 1 2 EMC@ +GND_CHASSIS
C327 150P_1808_2.5KV8J
CHASSIS use 40mil trace if necessary
USB3.0 repeater +3.3V_RUN +3.3V_RUN

I/O CONN +5V_ALW
JIO1
0.01U_0402_16V7K
0.1U_0402_10V7K
1
2 1
2
1
1
C395
B 3 B
3
C381
4
+3.3V_RUN 5 4
2
<36> WIRELESS_ON#/OFF 6 5
<11> USB_OC1# 7 6
U51
<36> USB_SIDE_EN# 7
R478 2 1 EQ0 6 16 8
4.7K_0402_5% VDD VDD 9 8
<11> USB3TP1 9
USB3RN1_IO 1 15 USB3RN1_RPC335 2 1 0.1U_0402_10V7K <11> USB3TN1 10
INn OUTn USB3RN1 <11> 10 +5V_ALW +3.3V_ALW +3.3V_RUN
R479 2 1 EQ1 USB3RP1_IO 2 14 USB3RP1_RPC286 2 1 0.1U_0402_10V7K 11
INp OUTp USB3RP1 <11> <11> USBP1+ 12 11
4.7K_0402_5%
<11> USBP1- 12
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
4 12 13
@ R480 2 1 DE NC NC USB3RP1_IO 14 13
4.7K_0402_5% EQ0 19 17 EQ1 USB3RN1_IO 15 14
EQ0 EQ1 15
1
@ C4
@ C50
@ C77
DE 18 11 1 2 @
@R477
R477 16
DE EQ_INC# 4.7K_0402_5% 17 16
2 1 10 20 <36,40> LID_CL# 18 17
+3.3V_ALW
2
R476 3.01K_0402_1% REXT PD# 5 19 18
3 I2C_EN 7 <26,36> AUD_HP_NB_SENSE 20 19
GND NC +3.3V_RUN 20
13 8 21
GND NC <26> AUD_HP_OUT_R 21
21 9 22
GND NC 23 22
<26> RING2 23
24
<26> SLEEVE 24
PS8711BTQFN20GTR-A0_TQFN20_3X3 25
26 25
<26> AUD_HP_OUT_L 26
27
28 GND
GND
ACES_50506-02641-P01
CONN@
A A
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT RJ45 & I/O
LA-9591P
5 4 3 2 1
5 4 3 2 1
+3.3V_ALW +3.3V_ALW_U37
PJP6
1 2
10U_0603_6.3V6M
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_10V7K
0.1U_0402_25V6
0.1U_0402_25V6
PAD-OPEN1x1m
1
C328
C329
C330
C334
C331
C332
2
2
+3.3V_ALW
D D
1 2 ALS_INT#
A17
B30
A43
A54
R281 10K_0402_5%
B5
1 2 HW_GPS_DISABLE2# U37
R282 100K_0402_5%
VCC1
VCC1
VCC1
VCC1
VCC1
1 2 PROCHOT_GATE A23
R283 100K_0402_5% B52 GPIOI0 B63 SIO_SLP_A#
<33> DOCKED_LIO_EN GPIOA0 GPIOI1 SIO_SLP_A# <39,44,9>
1 2 CPU_DETECT# A49 A60
R284 100K_0402_5% MCARD_MISC_PWREN B53 GPIOA1 GPIOI2/TACH0 A61
@ T97 PAD~D GPIOA2 GPIOI3 SIO_SLP_S4# <39,43,9>
1 2 SLICE_BAT_PRES# <47> PROCHOT_GATE PROCHOT_GATE A50 B65 +3.3V_RUN
GPIOA3 GPIOI4 SIO_SLP_S3# <39,43,9>
R285 100K_0402_5% LID_CL_SIO# B54 A62
GPIOA4 GPIOI5 IMVP_PWRGD <46>
1 2 WWAN_RADIO_DIS# DOCK_SMB_ALERT# A51 B66 RP8
<34,41,48> DOCK_SMB_ALERT# GPIOA5 GPIOI6 IMVP_VR_ON <46>
R286 100K_0402_5% @ T98 PAD~D TOUCH_SCREEN_PD# B55 A63 D_CLKRUN# 1 8
1 2 USB_PWR_SHR_EN# A52 GPIOA6 GPIOI7 DOCK_AC_OFF_EC <48> D_SERIRQ 2 7
R287 100K_0402_5% GPIOA7 B67 AUX_EN_WOWL D_DLDRQ1# 3 6
1 2 USB_SIDE_EN# USB_SIDE_EN# A33 GPIOJ0 A64 AUX_EN_WOWL <31> LPC_LDRQ1# 4 5
<35> USB_SIDE_EN# GPIOB0 GPIOJ1/TACH1 WLAN_LAN_DISB# <28>
R288 10K_0402_5% EN_I2S_NB_CODEC# B36 A5 SIO_SLP_LAN#
<26> EN_I2S_NB_CODEC# GPIOB1 GPIOJ2/TACH2 SIO_SLP_LAN# <28,9>
1 2 WIGIG60GHZ_DIS# USH_PWR_STATE# A34 B6 SIO_SLP_SUS# 100K_0804_8P4R_5%
<29> USH_PWR_STATE# GPOC2 GPIOJ3 SIO_SLP_SUS# <9>
R289 100K_0402_5% <48> EN_DOCK_PWR_BAR EN_DOCK_PWR_BAR B37 A6
1 2 USB_PWR_SHR_VBUS_EN PANEL_BKEN_EC A35 GPOC3 GPIOJ4 B7 MODC_EN GPIO_PSID_SELECT <41>
<22> PANEL_BKEN_EC GPOC4 GPIOJ5 PAD~D T101 @
R291 100K_0402_5% ENVDD_PCH B38 A7 DOCK_HP_DET
<10,22> ENVDD_PCH GPOC5 GPIOJ6 DOCK_HP_DET <26>
1 2 DOCK_SMB_ALERT# LCD_TST A36 B8 DOCK_MIC_DET
<22> LCD_TST GPOC6/TACH4 GPIOJ7 DOCK_MIC_DET <26>
R292 100K_0402_5% PSID_DISABLE# A37
1 2 WIRELESS_ON#/OFF <41> PSID_DISABLE# PBAT_PRES# B40 GPIOC7 A8 ME_FWP
<41,48> PBAT_PRES# GPIOD0 GPIOK0 ME_FWP <6>
R293 100K_0402_5% DOCKED A38 B9 MASK_SATA_LED#
<21,27,28,32> DOCKED GPIOC1 GPIOK1/TACH3 MASK_SATA_LED# <40>
1 2 ESATA_USB_PWR_EN# DOCK_DET# B41 B10 USB_PWR_SHR_EN#
<34,48> DOCK_DET# GPIOC0 GPIOK2 USB_PWR_SHR_EN# <33>
R295 100K_0402_5% AUD_NB_MUTE# A39 A10 LED_SATA_DIAG_OUT#
<26> AUD_NB_MUTE# GPIOB7 GPIOK3 LED_SATA_DIAG_OUT# <40>
1 2 BT_RADIO_DIS# MCARD_WWAN_PWREN B42 B11
R298 100K_0402_5% <31> MCARD_WWAN_PWREN LCD_VCC_TEST_EN A40 GPIOB6 GPIOK4 A11 RUN_ON
<22> LCD_VCC_TEST_EN GPIOB5 GPIOK5 RUN_ON <26,37,39>
1 2 XFR_ID_BIT# CCD_OFF B43 B12 RUN_ON 2 1
<22> CCD_OFF GPIOB4 GPIOK6 AC_DIS <41,48>
@R302
@ R302 100K_0402_5% AUD_HP_NB_SENSE A41 A12 R303 100K_0402_5%
<26,35> AUD_HP_NB_SENSE GPIOB3 GPIOK7 SPI_WP#_SEL <7>
ESATA_USB_PWR_EN# B44 CPU_VTT_ON 2 1
<33> ESATA_USB_PWR_EN# GPIOB2 B60 SUS_ON R305 100K_0402_5%
GPIOL0/PWM7 SUS_ON <39,43>
+3.3V_RUN A57 SLICE_BAT_ON 2 1
MODULE_ON B32 GPIOL1/PWM8 B64 BAT1_LED# R307 100K_0402_5%
C @ T106 PAD~D GPIOD1 GPIOL2/PWM0 BAT1_LED# <40> trace width 20 mils C
<48> SLICE_BAT_ON SLICE_BAT_ON A31 B68 SUS_ON 2 1
1 2 SP_TPM_LPC_EN SLICE_BAT_PRES# B33 GPIOD2 GPIOL3/PWM1 A9 BAT2_LED# R308 100K_0402_5%
<34,41,48> SLICE_BAT_PRES# GPIOD3 GPIOL4/PWM3 BAT2_LED# <40> trace width 20 mils
@ R304 10K_0402_5% @ T107 PAD~D MODULE_BATT_PRES# B15 B1
A15 GPIOD4 GPIOL5/PWM2 A18
GPIOD5 GPIOL6 USH_PWR_ON <39>
@ T110 PAD~D CHARGE_PBATT B16 A44 FP_POA_EN PAD~D T100 @
1 2 LCD_TST A16 GPIOD6 GPIOL7/PWM5
R309 100K_0402_5% GPIOD7 B34 HW_GPS_DISABLE2#
GPIOM1 HW_GPS_DISABLE2# <31>
1 2 SYS_LED_MASK# B39 BREATH_LED#
GPIOM3/PWM4 BREATH_LED# <34,40>
R310 10K_0402_5% WIGIG60GHZ_DIS# A1 B51
<31> WIGIG60GHZ_DIS# GPIOE0/RXD GPIOM4/PWM6 DIS_BAT_PROCHOT# <48>
1 2 CHARGE_EN EC5048_TX B2
<31,37> EC5048_TX GPIOE1/TXD
R313 100K_0402_5% A2
mCARD_PCIE_SATA# B3 GPIOE2/RTS# A27 LPC_LAD0
<6> MCARD_PCIE_SATA# GPIOE3/DSR# LAD0 LPC_LAD0 <29,37,7>
CPU_DETECT# A3 A26 LPC_LAD1
<9> CPU_DETECT# GPIOE4/CTS# LAD1 LPC_LAD1 <29,37,7>
XFR_ID_BIT# B45 B26 LPC_LAD2
GPIOE5/DTR# LAD2 LPC_LAD2 <29,37,7>
A42 B25 LPC_LAD3
GPIOE6/RI# LAD3 LPC_LAD3 <29,37,7>
@ T115 PAD~D DP_HDMI_HPD B4 A21 LPC_LFRAME#
GPIOE7/DCD# LFRAME# LPC_LFRAME# <29,37,7>
B22 PCH_PLTRST#_EC
LRESET# PCH_PLTRST#_EC <29,31,37,9>
A28 CLK_PCI_5048
PCICLK CLK_PCI_5048 <7>
A59 B20 CLKRUN#
GPIOF0 CLKRUN# CLKRUN# <12,29,37,9>
BCM5882_ALERT# B62
<29> BCM5882_ALERT# GPIOF1
A58 A22 LPC_LDRQ1#
<9> SUSACK# GPIOF2 LDRQ1#
@ T118 PAD~D EDID_SELECT# B61 B21 IRQ_SERIRQ
GPIOF3/TACH8 SER_IRQ IRQ_SERIRQ <12,29,37>
A56 A32
VGA_ID B59 GPIOF4/TACH7 14.318MHZ/GPIOM0 B35
GPIOF5 CLK32/GPIOM2 EC_32KHZ_ECE5048 <37>
A55
SLP_ME_CSW_DEV# B58 GPIOF6
<12> SLP_ME_CSW_DEV# GPIOF7 B29 D_LAD0
DLAD0 B28 D_LAD1 D_LAD0 <34>
LAN_DISABLE#_R B47 DLAD1 A25 D_LAD2 D_LAD1 <34>
<28> LAN_DISABLE#_R GPIOG0/TACH5 DLAD2 D_LAD2 <34>
CHARGE_EN A45 A24 D_LAD3
SYS_LED_MASK# B48 GPIOG1 DLAD3 B23 D_LFRAME# D_LAD3 <34>
<40> SYS_LED_MASK# GPIOG2 DLFRAME# D_LFRAME# <34>
ALS_INT# A46 A19 D_CLKRUN#
GPIOG3 DCLKRUN# D_CLKRUN# <34>
<12> SIO_EXT_WAKE# SIO_EXT_WAKE# B49 B24 D_DLDRQ1#
GPIOG4 DLDRQ1# D_DLDRQ1# <34>
WIRELESS_LED# A47 A20 D_SERIRQ
<31,40> WIRELESS_LED# GPIOG5 DSER_IRQ D_SERIRQ <34>
B B50 B
<33> USB_PWR_SHR_VBUS_EN WLAN_RADIO_DIS# A48 GPIOG6
<31> WLAN_RADIO_DIS# GPIOG7/TACH6 A29 BC_INT#_ECE5048
BC_INT# BC_INT#_ECE5048 <37>
B31 BC_DAT_ECE5048
BC_DAT BC_DAT_ECE5048 <37>
WIRELESS_ON#/OFF B13 A30 BC_CLK_ECE5048
<35> WIRELESS_ON#/OFF GPIOH0 BC_CLK BC_CLK_ECE5048 <37>
BT_RADIO_DIS# A13
<31> BT_RADIO_DIS# GPIOH1
WWAN_RADIO_DIS# A53 +3.3V_ALW
<31> WWAN_RADIO_DIS# SYSOPT1/GPIOH2
SYS_PWROK B57 A4 RUNPWROK
<9> SYS_PWROK SYSOPT0/GPIOH3 PWRGD RUNPWROK <37,9>
@ T121 PAD~D DGPU_SELECT# B14
A14 GPIOH4 B56 SP_TPM_LPC_EN
<9> SIO_SLP_WLAN# GPIOH5 OUT65 SP_TPM_LPC_EN <29>
1
100K_0402_5%
CPU_VTT_ON B17
@ R319 1 2 0_0402_5% B18 GPIOH6
<9> PCH_DPWROK GPIOH7
R322
B19 1 2
TEST_PIN R321 1K_0402_5% +CAP_LDO trace width 20 mils
B46 +CAP_LDO
2
CAP_LDO
4.7U_0603_6.3V6K
B27
VSS
1
C1 LID_CL_SIO# 2 1
EP LID_CL# <35,40>
C336
R325 10_0402_1%
DB Version 0.4 CLK_PCI_5048
0.047U_0402_16V4Z
ECE5048-LZY_DQFN132_11X11~D
1
33_0402_5%
@ R324
+3.3V_ALW
C337
2
2
100K_0402_5%
2
R317
33P_0402_50V8J
@ C339
ME_FWP PCH has internal 20K PD.
1
(suspend power rail)
1
ME_FWP
2
VGA_ID
1
1K_0402_5%
EMI depop location

2
A A
@ R326
100K_0402_5%
@ R320
VGA_ID0
Discrete 0
2
UMA 1
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT ECE5048
LA-9591P
5 4 3 2 1
5 4 3 2 1
+RTC_CELL +RTC_CELL
100K_0402_5%
1
1
100K_0402_5%
+RTC_CELL
R327
R328
@ C340 @ C342
1 2 +RTC_CELL_VBAT 1 2 1 2
@ R332 0_0402_5%
0.1U_0402_25V6
1U_0402_6.3V6K 1U_0402_6.3V6K
2
1
POWER_SW_IN# 1 2 DOCK_PWR_SW# 1 2
POWER_SW#_MB <40,9> DOCK_PWR_BTN# <34>
C345
R329 10K_0402_5% R330 10K_0402_5%
1U_0402_6.3V6K
1U_0402_6.3V6K
2
1
C343
C344
+3.3V_ALW_U38
2
1 2 +3.3V_VTR
@ R336 0_0402_5%
0.1U_0402_25V6
1U_0402_6.3V4Z
+3.3V_ALW
1
C346
C352
D 1 2 PCIE_WAKE# D
R340 10K_0402_5% U38
2
1 2 BC_DAT_ECE5048
R343 100K_0402_5% B64 A10 SYSTEM_ID
1 2 PBAT_SMBDAT +3.3V_ALW_U38 VBAT GPIO021/RC_ID1 B10 BOARD_ID
R345 2.2K_0402_5% GPIO020/RC_ID2 B8 R338 1 2 1K_0402_5%
1 2 1 2 A22 GPIO014/GPTP-IN7/RC_ID3 B27 VOL_UP <40>
PBAT_SMBCLK +3.3V_VTR_ADC LAN_WAKE#
H_VTR GPIO025/UART_CLK B44 LAN_WAKE# <12,28> +1.05V_RUN
R339 2.2K_0402_5% @ R354 0_0402_5% HOST_DEBUG_TX
GPIO120/UART_TX B46 HOST_DEBUG_TX <31> 1 2
HOST_DEBUG_RX
0.1U_0402_25V6
GPIO124/GPTP-OUT5/UART_RX
1U_0402_6.3V4Z
A58 B26 RUNPWROK @ R334 0_0402_5%
VTR_ADC VCC_PWRGD RUNPWROK <36,9>
1
10K_0402_5%
A25 EN_INVPWR
GPIO060/KBRST/BCM_B_INT# EN_INVPWR <22>
C353
C347
+5V_RUN B36 PCH_SATA_MOD_EN#
GPIO101/ECGP_SCLK/GANG_DATA5 PAD~D T123 @
@ R335
RP2 B3 B37
2
VTR GPIO103/ECGP_MISO/GANG_DATA7 SLICE_PERF_EN <48> H_PROCHOT# <46,47,48,9>
L2N7002WT1G_SC-70-3
1 8 CLK_KBD A11 B38 PCIE_WAKE#
2 7 +3.3V_ALW +3.3V_ALW_U38 A26 VTR GPIO105/ECGP_MOSI A34 PCIE_WAKE# <31>
DAT_KBD DDR_HVREF_RST_GATE
2
VTR GPIO102/BCM_C_INT#/GANG_DATA6 D
1
3 6 CLK_MSE B35 A35
4 5 DAT_MSE PJP7 A41 VTR GPIO104 A36 DYN_TUR_CURRNT_SET# <47> PROCHOT#_EC 2
VTR GPIO106 SIO_SLP_S0# <9>
@ Q9
1 2 A52 A40 MSDATA G
VTR GPIO116/MSDATA/V2P_COUT_LO/TAP_SEL_STRAP B43 MSDATA <31>
4.7K_8P4R_5% MSCLK S
MSCLK <31>
3
GPIO117/MSCLK/V2P_COUT_HI
10U_0603_6.3V6M
0.1U_0402_25V6
100K_0402_5%
PAD-OPEN1x1m A45
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
GPIO127/A20M
2
+3.3V_RUN B65 FWP#
NFWP
1
@C349
@ R342
SML1_SMBDATA A5
<7> SML1_SMBDATA GPIO007/I2C1D_DATA/PS2_CLK0B/I2C3A_DATA/GANG_BUSY
C348
C354
C350
C355
C356
C351
1 2 VOL_MUTE SML1_SMBCLK B6
<7> SML1_SMBCLK A37 GPIO010/I2C1D_CLK/PS2_DAT0B/I2C3A_CLK/GANG_ERROR B57
@ R358 100K_0402_5% CLK_TP_SIO R349 1 2 1K_0402_5%
<38> CLK_TP_SIO VOL_DOWN <40>
2
1 2 VOL_DOWN DAT_TP_SIO B40 GPIO110/PS2_CLK2/GPTP-IN6 GPIO156/LED0 B1 DEVICE_DET#
<38> DAT_TP_SIO
1
@ R360 100K_0402_5% CLK_KBD A38 GPIO111/PS2_DAT2/GPTP-OUT6 GPIO157/LED1 A55 PS_ID
1 2 <34> CLK_KBD B41 GPIO112/PS2_CLK1A GPIO153/LED2 A1 PS_ID <41>
VOL_UP DAT_KBD +3.3V_ALW
<34> DAT_KBD A39 GPIO113/PS2_DAT1A GPIO027/GPTP-OUT1 B28 ALW_PWRGD_3V_5V <42>
@ R362 100K_0402_5% CLK_MSE 1.05V_A_PWRGD
1 2 <34> CLK_MSE B42 GPIO114/PS2_CLK0A GPIO026/GPTP-IN1 B2 1 2 1.05V_A_PWRGD <44>
FAN1_PWM DAT_MSE
<34> DAT_MSE B59 GPIO115/PS2_DAT0A GPIO001/ECSPI_CS1 A8 VOL_MUTE <40> 2 1
R408 10K_0402_5% PBAT_SMBDAT R352 1K_0402_5% DYN_TUR_CURRNT_SET#
1 2 <41> PBAT_SMBDAT A56 GPIO154/I2C1C_DATA/PS2_CLK1B GPIO015/GPTP-OUT7/GANG_DATA3 B9 ME_SUS_PWR_ACK <9>
FAN1_TACH PBAT_SMBCLK 1.35V_SUS_PWRGD 100K_0402_5% R363
<41> PBAT_SMBCLK GPIO155/I2C1C_CLK/PS2_DAT1B GPIO016/GPTP-IN8/GANG_DATA4 A9 1.35V_SUS_PWRGD <43> 2 1
R376 10K_0402_5% PM_APWROK BAY_SMBDAT
A51 GPIO017/GPTP-OUT8 B39 PM_APWROK <9>
JTAG_TDI RESET_OUT# 2.2K_0402_5% R453
B55 GPIO145/I2C1K_DATA/JTAG_TDI GPIO107/NRESET_OUT A44 RESET_OUT# <15,9> 2 1
JTAG_TDO PCH_PCIE_WAKE# BAY_SMBCLK
JTAG_CLK B56 GPIO146/I2C1K_CLK/JTAG_TDO GPIO125/GPTP-IN5 B47 PCH_RSMRST# PCH_PCIE_WAKE# <9> 2.2K_0402_5% R452
A53 GPIO147/I2C1J_DATA/I2C2C_DATA/JTAG_CLK GPIO126 A54 PCH_RSMRST# <38> 2 1
JTAG_TMS AC_PRESENT DDR_HVREF_RST_GATE
A57 GPIO150/I2C1J_CLK/I2C2C_CLK/JTAG_TMS GPIO151/GPTP-IN4 B58 AC_PRESENT <9>
+3.3V_ALW JTAG_RST# SIO_PWRBTN# 100K_0402_5% R353
JTAG_RST# GPIO152/GPTP-OUT4 SIO_PWRBTN# <9>
RP18 RP15
8 1 BC_DAT_ECE1117 FAN1_TACH B22 A3 DOCK_SMB_DAT DOCK_SMB_DAT 1 8
7 2 A21 GPIO050/FAN_TACH1/GTACH GPIO003/I2C1A_DATA/GANG_MODE B4 DOCK_SMB_DAT <34> 2 7
PCH_ALW_ON DOCK_POR_RST# DOCK_SMB_CLK DOCK_SMB_CLK
6 3 <34> DOCK_POR_RST# B23 GPIO051/FAN_TACH2 GPIO004/I2C1A_CLK/GANG_START A4 DOCK_SMB_CLK <34> 3 6
DOCK_POR_RST# LCD_SMBDAT LCD_SMBDAT
5 4 <12> EC_WAKE# B24 GPIO052/FAN_TACH3 GPIO005/I2C1B_DATA/BCM_B_DAT/GANG_STROBE B5 4 5
A_ON A_ON LCD_SMBCLK LCD_SMBCLK
<39,44> A_ON A23 GPIO053/PWM0 GPIO006/I2C1B_CLK/BCM_B_CLK/GANG_FULL B7
PCH_ALW_ON BAY_SMBDAT
<39> PCH_ALW_ON B25 GPIO054/PWM1 GPIO012/I2C1H_DATA/I2C2D_DATA/GANG_DATA1 A7
100K_0804_8P4R_5% <22> BIA_PWM_EC BIA_PWM_EC BAY_SMBCLK 2.2K_0804_8P4R_5%
FAN1_PWM A24 GPIO055/PWM2 GPIO013/I2C1H_CLK/I2C2D_CLK/GANG_DATA2 B48 GPU_SMBDAT
GPIO056/PWM3/GPWM GPIO130/I2C2A_DATA/BCM_C_DAT B49 GPU_SMBCLK RP16
GPIO131/I2C2A_CLK/BCM_C_CLK A47 CHARGER_SMBDAT GPU_SMBDAT 1 8
1 2 GPIO132/I2C1G_DATA B50 CHARGER_SMBDAT <47> 2 7
MSDATA CHARGER_SMBCLK GPU_SMBCLK
A43 GPIO140/I2C1G_CLK B52 CHARGER_SMBCLK <47> 3 6
R366 10K_0402_5% BC_CLK_ECE5048 CARD_SMBDAT CARD_SMBCLK
1 2 EN_INVPWR <36> BC_CLK_ECE5048 BC_DAT_ECE5048 B45 GPIO123/BCM_A_CLK GPIO141/I2C1F_DATA/I2C2B_DATA A49 CARD_SMBCLK CARD_SMBDAT 4 5
<36> BC_DAT_ECE5048 A42 GPIO122/BCM_A_DAT GPIO142/I2C1F_CLK/I2C2B_CLK B53
R371 100K_0402_5% BC_INT#_ECE5048 USH_SMBDAT
1 2 <36> BC_INT#_ECE5048 B20 GPIO121/BCM_A_INT# GPIO143/I2C1E_DATA A50 USH_SMBDAT <29>
RESET_OUT# ACAV_IN_NB USH_SMBCLK 2.2K_0804_8P4R_5%
C <47,48> ACAV_IN_NB A18 GPIO032/BCM_E_CLK GPIO144/I2C1E_CLK USH_SMBCLK <29> C
@ R373 8.2K_0402_5% SIO_SLP_S5#
<9> SIO_SLP_S5# BEEP B19 GPIO031/GPTP-OUT2/BCM_E_DAT A59 1 2 RP17
<26> BEEP GPIO030/GPTP-IN2/BCM_E_INT# SYSPWR_PRES +3.3V_ALW2
BC_CLK_ECE1117 A20 R367 1K_0402_5% THERMATRIP3# 1 8 +RTC_CELL
<38> BC_CLK_ECE1117 GPIO047/LSBCM_D_CLK
1
100K_0402_5%
BC_DAT_ECE1117 B21 A64 ACAV_IN DEVICE_DET# 2 7
<38> BC_DAT_ECE1117 GPIO046/LSBCM_D_DAT VCI_OVRD_IN ACAV_IN <47,48>
BC_INT#_ECE1117 A19 A60 ALWON POA_WAKE# 3 6
<38> BC_INT#_ECE1117 GPIO045/LSBCM_D_INT# VCI_OUT ALWON <42>
R370
B67 POWER_SW_IN# VCI_IN2# 4 5
SIO_EXT_SMI# A6 VCI_IN0# A63 DOCK_PWR_SW#
<12> SIO_EXT_SMI# A27 GPIO011/nSMI/GANG_DATA0 VCI_IN1# B63
SIO_RCIN# VCI_IN2# 100K_0804_8P4R_5% +3.3V_ALW
2
<12> SIO_RCIN# IRQ_SERIRQ A28 GPIO061/LPCPD# VCI_IN2# B68 POA_WAKE#
<12,29,36> IRQ_SERIRQ PCH_PLTRST#_EC B30 SER_IRQ VCI_IN3# RP19
<29,31,36,9> PCH_PLTRST#_EC LRESET# R866 close to U38 at least 250mils
CLK_PCI_MEC A29 B51 +PECI_VREF 1 2 HOST_DEBUG_RX 1 8
<7> CLK_PCI_MEC PCI_CLK VREF_PECI +1.05V_RUN
LPC_LFRAME# B31 A48 PECI_EC_R 1 2 @ R374 0_0402_5% CHARGER_SMBDAT 2 7
<29,36,7> LPC_LFRAME# LFRAME# PECI_DAT PECI_EC <9>
0.1U_0402_25V6
LPC_LAD0 A30 R375 43_0402_5% CHARGER_SMBCLK 3 6
<29,36,7> LPC_LAD0 B32 LAD0 4 5
LPC_LAD1 PCH_RSMRST#
<29,36,7> LPC_LAD1 LAD1
C360
LPC_LAD2 A31 B13 REM_DIODE1_N C358 1 2 2200P_0402_50V7K
<29,36,7> LPC_LAD2 B33 LAD2 DN1-THERM A13
LPC_LAD3 REM_DIODE1_P 10K_8P4R_5%
<29,36,7> LPC_LAD3 A32 LAD3 DP1-VREF_T B14
CLKRUN# REM_DIODE2_N C359 1 2 2200P_0402_50V7K
<12,29,36,9> CLKRUN#
2
SIO_EXT_SCI# A33 CLKRUN# DN2 A14 REM_DIODE2_P
<12> SIO_EXT_SCI# GPIO100/NEC_SCI DP2 A15
MEC_XTAL1 A61 DN3 B16
MEC_XTAL2 2 1 MEC_XTAL2_R A62 XTAL1 DP3 A16 REM_DIODE4_N C361 1 2 2200P_0402_50V7K
@ R378 1 2 0_0402_5% B62 XTAL2 DN4 B17 REM_DIODE4_P
<36> EC_32KHZ_ECE5048 GPIO160/32KHZ_OUT DP4 B15
+3.3V_ALW @ R379 0_0402_5% C283, C285, C286, C287 Place near U38
VIN A17 VSET_5075
VSET A12
VCP VCP <47>
1
100K_0402_5%
B34 THERMATRIP2#
32 KHz Clock THERMTRIP2#
GPIO002/THERMTRIP3#
A2 THERMATRIP3#
R380
B29 THSEL_STRAP
VSS_ADC
GPIO024/THSEL_STRAP
VSS_RO
VR_CAP
A46 PROCHOT#_EC
H_VSS
PROCHOT_IN#/PROCHOT_IO#
AGND
B61 1 2
V_SYS <47>
VSS
2
V_ISYS R381 4.7K_0402_5%
EP
MEC_XTAL1 1 2 MEC_XTAL2
JTAG_RST# MEC5075-LZY_DQFN132_11X11~D
B66
B11
B60
+VR_CAP B12
B54
B18
C1
22P_0402_50V8J
22P_0402_50V8J
Y4
32.768KHZ_12.5PF_Q13FC135000040
1
15mil
1U_0402_6.3V6K
C364
C365
1
1
@SHORT PADS~D
JTAG1 CONN@
100_0402_1%
2
1
@ R384
4.7U_0603_6.3V6K
5075 Setting for Thermal Design
C362
1
2
C366
2
2
2
2
ESR <2ohms
JFAN1
Thermal diode mapping 1
1 2 FAN1_PWM
2 3 FAN1_TACH
5075 Channel Location 3 4
+5V_RUN
B 4 B
22U_0805_6.3V6M
RB751V40_SC76-2
5
DP1/DN1 CPU GND1
1
CLK_PCI_MEC 6
GND2
1
+3.3V_RUN
@ D1
DOCK_POR_RST#
1
10_0402_1%
C7
ACES_50271-0040N-001
DP2/DN2 DIMM
@ R382
10K_0402_5%
CONN@
2
1
2
0.1U_0402_25V6
R35
+3.3V_ALW DP4/DN4 V.R
2
1
4.7P_0402_50V8C
C357
+3.3V_ALW
2
100K_0402_5%
Place under CPU reserve for DC fan
2
1
1
@ C363
RUNPWROK
Place C266 close to the Q11 as possible
R36
8.2K_0402_5%
1
REM_DIODE1_P
2
Q5B
R402
100P_0402_50V8J
EMI depop location 2
1
C
@ C370
RUN_ON# 5 2
Place close pin A29 Place close pin A21
2
B
1
6
E Q11
3
MMBT3904WT1G_SC70-3~D THERMATRIP2#
Q5A
REM_DIODE1_N
+1.05V_RUN
MMST3904-7-F_SOT323-3
2
+3.3V_ALW <26,36,39> RUN_ON
0.1U_0402_25V6
1
C
DP2/DN2 for SODIMM on Q13, place Q13 close
1
1 2 2
1
to SODIMM and C372 close to Q13
Q12
C371
R403 2.2K_0402_5% B
49.9_0402_1%
3
1
8
7
6
5
+3.3V_ALW
10K_8P4R_5%
REM_DIODE2_P
2
R388
RP1
100P_0402_50V8J
1
@ C372
C
1
1
10K_0402_5%
10K_0402_5%
10K_0402_5%
100K_0402_5%
CONN@ 2
<12> H_THERMTRIP#
2
1
2
3
4
@ R398
JDEG1 B
2
R395
R396
R397
1 E Q13
3
1 2 JTAG_TDI MMBT3904WT1G_SC70-3~D
2 3 JTAG_TMS
2
3 4 JTAG_CLK REM_DIODE2_N VSET_5075

4 5 JTAG_TDO
5
0.1U_0402_25V6
11 6 MSCLK
G1 6
1
1.58K_0402_1%
12 7 MSDATA R392 C368 REV +3.3V_ALW +3.3V_ALW +3.3V_ALW
G2 7 DP4/DN4 for Skin on Q14, place Q14 close to Vcore VR choke.
1
8 HOST_DEB_TX 1 2 HOST_DEBUG_TX THSEL_STRAP 1 2
8
C367
R394
9 @ R400 0_0402_5% REM_DIODE4_P R383 1K_0402_5%
9 EC5048_TX <31,36> 240K 4700p X00
1K_0402_5%
1K_0402_5%
10K_0402_5%
10
2
10
1
100P_0402_50V8J
Pin8 5075_TXD for EC Debug
130K 4700p X01
2
R392
R386
R393
HB_A531015-SCHR21 pin9 5048_TXD for SBIOS
1
@C373
debug C
62K 4700p *** 2
1: Channel 1 will provide Thermistor Readings
B
33K 4700p X02
2
1
E Q14
0: Channel 1 will provide Diode Readings
3
+3.3V_RUN
4700P_0402_25V7K
CONN@ BOARD_ID SYSTEM_ID FWP# MMBT3904WT1G_SC70-3~D

A JLPDE1 8.2K 4700p *** Rest=1.58K , Tp=96 degree A
4700P_0402_25V7K
1 REM_DIODE4_N
1 4.3K 4700p ***
1
2
10K_0402_5%
2
2
1
C369
@ R399
3 LPC_LAD0
3 2K 4700p ***
C368
4 LPC_LAD1
2
4 5 LPC_LAD2
* 1K 4700p A00
2
11 5 6 LPC_LAD3
1
12 G1 6 7 LPC_LFRAME#
G2 7 8 PCH_PLTRST#_EC
8 9
9 10
10 CLK_PCI_LPDEBUG <7> BOARD_ID rise time is measured from 5%~68%. CHIPSET_ID for BID function
HB_A531015-SCHR21
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT MEC5075
LA-9591P
5 4 3 2 1
5 4 3 2 1
D D
Touch Pad
+3.3V_RUN +3.3V_TP
+3.3V_TP Keyboard 18
JKBTP1
PJP8 17 GND2
1 2 GND1
4.7K_0402_5%
4.7K_0402_5%
16
<12> KB_DET# 16
1
PAD-OPEN1x1m 15
15
R404
R405
14
13 14
12 13
+5V_RUN 12 +3.3V_TP +3.3V_ALW +5V_RUN
@ R444 1 2 0_0402_5%
+3.3V_ALW
11
<37> DAT_TP_SIO
2
10 11
@ R450 1 2 0_0402_5% TP_DATA <37> BC_INT#_ECE1117 9 10
<12> I2C1_SDA_TCH_PAD <37> BC_DAT_ECE1117 9
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
8
@ R441 1 2 0_0402_5% TP_CLK 7 8
<37> CLK_TP_SIO <37> BC_CLK_ECE1117 7
1
@ C374
@ C375
@ C376
6
@ R449 1 2 0_0402_5% 5 6
<12> I2C1_SCL_TCH_PAD +3.3V_TP 5
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
TP_DATA 4
2
TP_CLK 3 4
3
1
@ C377
@ C378
@ C379
@ C380
2
1 2
1
2
CONN@
ACES_50506-01641-P01
C Place close to JKBTP1 C
EMI depop location
RSMRST circuit @IO FFC @MEDIA Board FFC

@ R414 1 2 0_0402_5%
Part Number Description Part Number Description
+5V_ALW +3.3V_ALW
+3.3V_ALW DA30000GZ00 FPC 0VN LF-9591P REV0 M/B-IO/B NBX0001CW00 FFC 8P G P0.5 PAD0.3 50MM MB-MEDIA/B 0VN
@ C386
1
1
33_0402_5%
10K_0402_5%
1 2 @eDP TS Cable @KBTP FFC

R411
R440
0.1U_0402_25V6 Part Number Description Part Number Description
U41 DC02C004S00 H-CONN SET 0VN MB-LCD-LED-CAM-TS NBX0001CZ00 FFC 15P G P.5 PAD.3 85MM MB-NFC MODU 0VN
5
2
1
P
<37> PCH_RSMRST# B
+5V_ALW_U41 1 4 1 2 @eDP Cable @NFC Board FFC
B VCC O PCH_RSMRST#_Q <9> B
3 RSMRST# 2 @ R413 0_0402_5%
RESET# A
G
Part Number Part Number

0.01U_0402_16V7K
2 Description Description
GND U42
3
DC02C004T00 H-CONN SET 0VN MB-LCD-LED-CAM NBX0001CZ00 FFC 15P G P.5 PAD.3 85MM MB-NFC MODU 0VN
1
C387
TC7SH08FU_SSOP5~D
RT9818A-44GU3_SC70-3
@SATA Cable @USH Board FFC
2

DC02C004K00 H-CONN SET 0VN MB-HDD NBX0001CY00 FFC 20P G P0.5 PAD=0.3 75MM MB-USH/B 0VN
@DC-IN Cable @FP FFC

DC30100MF00 CONN SET 0VN DCJACK-MB 2DW1003-038110F NBX0001D100 FFC 6P G P0.5 PAD=0.3 75MM USH/B-FP 0VN
@RTC BATT @ Speak

DC30100MF00 CONN SET 0VN DCJACK-MB 2DW1003-038110F PK230003Q0L SPK PACK ZJX 2.0W 4 OHM FG
@FAN
Part Number Description
DC28A000800 FAN SET DAQ20 DC5V AB7405HB-HB3 ADDA
A A
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Keyboard
LA-9591P
5 4 3 2 1
5 4 3 2 1
+1.05V_MODPHY +5V_ALW
+1.05V_M Q125
SI3456DDV-T1-GE3_TSOP6
+1.05V_MODPHY
+3.3V_ALW_PCH/+1.05V_RUN source
D
6
S
1
10K_0402_5%
5 4
2 +3.3V_ALW_PCH
R445
10U_0603_6.3V6M
1 U43
1
+3.3V_ALW2
20K_0402_5%
1 14 1 2
G
+3.3V_ALW VIN1 VOUT1
C413
@ R447
2 13 C389 0.1U_0402_10V7K
3
VIN1 VOUT1
1
100K_0402_5%
D 1 2 3 12 1 2 D
<37> PCH_ALW_ON
2
ON1 CT1
R442
1.05V_MODPHY_EN @ R416 0_0402_5% C390 470P_0402_50V7K
2
2200P_0402_50V7K
+5V_ALW 4 11
VBIAS GND
3
1 2 5 10 1 2
<26,36,37> RUN_ON
2
ON2 CT2
C412
@ R418 0_0402_5% C391 470P_0402_50V7K
Q124B
1 2 +1.05V_M 6 9
<36,43,9> SIO_SLP_S3# VIN2 VOUT2
MPHYP_PWR_EN# 5 @ R417 0_0402_5% 7 8 +1.05V_RUN
2
VIN2 VOUT2
15
4
GPAD
0.1U_0402_10V7K
2
Q124A
C393
1 2 2
<12> MPHYP_PWR_EN
1
@ R420 0_0402_5%
+3.3V_SUS/+3.3V_M source
C C
+3.3V_ALW +3.3V_SUS
1 2 U45
<36> USH_PWR_ON
@ R439 0_0402_5% 1 14 1 2
1 2 2 VIN1 VOUT1 13 C396 0.1U_0402_10V7K
<36,43,9> SIO_SLP_S4# VIN1 VOUT1
@ R421 0_0402_5%
1 2 3 12 1 2
<36,43> SUS_ON ON1 CT1
@ R422 0_0402_5% C397 470P_0402_50V7K
+5V_ALW 4 11
VBIAS GND
1 2 5 10 1 2
<36,44,9> SIO_SLP_A# ON2 CT2
@ R423 0_0402_5% C398 470P_0402_50V7K
1 2 6 9
<37,44> A_ON VIN2 VOUT2
@ R424 0_0402_5% 7 8 +3.3V_M
VIN2 VOUT2
15
GPAD
0.1U_0402_10V7K
1
C399
2
B
+3.3V_RUN/+5V_RUN source B
+5V_ALW +5V_RUN
U46
1 14 1 2
2 VIN1 VOUT1 13 C400 0.1U_0402_10V7K
VIN1 VOUT1
3 12 1 2
ON1 CT1 C401 470P_0402_50V7K
SIO_SLP_S3# 1 2 4 11
@ R425 0_0402_5% VBIAS GND
RUN_ON 1 2 5 10 1 2
@ R426 0_0402_5% ON2 CT2 C402 1000P_0402_50V7K
+3.3V_ALW 6 9
7 VIN2 VOUT2 8
VIN2 VOUT2 +3.3V_RUN
0.1U_0402_10V7K
15
GPAD
1
C403
2
A A
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Power control
LA-9591P
5 4 3 2 1
5 4 3 2 1
HDD LED solution for White LED Battery LED

+3.3V_ALW
+5V_ALW +5V_ALW
1
10K_0402_5%
R428
LED7
3
Q23B LTW-295DSKS-5A_YEL-WHITE
2
Q24B Q24A DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6 D23 DMN66D0LDW-7_SOT363-6 4 3 BAT2_LED#_Q 1 2 BATT_WHITE# 1 2
4 3 1 2 1 6 2 <36> BAT2_LED# W
R427 390_0402_5%
<6> SATA_ACT#
RB751S40T1G_SOD523-2 Q15 BATT_YELLOW# 3 4
5
D PDTA114EU_SC70-3 D
MASK_BASE_LEDS# Y
2
<36> MASK_SATA_LED#
1
D24 LED6
1 2 LTW-193ZDS5_WHITE 1 2 BATT_WHITE_LED# <22>
<36> LED_SATA_DIAG_OUT# 1 2 SATA_LED 2 1
MASK_BASE_LEDS# R429 220_0402_5%
RB751S40T1G_SOD523-2 R430 330_0402_5%
Q23A
PANEL_HDD_LED# <22>
DMN66D0LDW-7_SOT363-6 BATT_YELLOW_LED# <22>
1 6 BAT1_LED#_Q 1 2
<36> BAT1_LED#
R431 330_0402_5%
3
Q25B
2
4 3 2 MASK_BASE_LEDS#
Q26 1 2
PDTA114EU_SC70-3 R433 330_0402_5%
1
SYS_LED_MASK# 1 2
R438 150_0402_5%
WLAN LED solution for White LED

+3.3V_ALW
Breath LED Q28B
1
100K_0402_5%
+5V_ALW 4 3
C C
R432
5
3
2
Q25A
DMN66D0LDW-7_SOT363-6 +5V_ALW
1 6 2 Q28A LED1
<31,36> WIRELESS_LED#
Q16 DMN66D0LDW-7_SOT363-6 LTW-193ZDS5_WHITE
PDTA114EU_SC70-3 1 6 BREATH_LED#_Q 1 2 BREATH_WHITE_LED_SNIFF 1 2
<34,36> BREATH_LED#
R434 330_0402_5%
2
Place LED1 close to SW5

1
2
MASK_BASE_LEDS#
1 2 WLAN_LED 2 1 MASK_BASE_LEDS#
R435 390_0402_5%
LED5
LTW-193ZDS5_WHITE 1 2 BREATH_WHITE_LED# <22>
R436 220_0402_5%
+3.3V_ALW
@ C404
1 2
0.1U_0402_25V6
5
1
P
<36> SYS_LED_MASK# B 4
2 O MASK_BASE_LEDS# <28>
<35,36> LID_CL# A
G
U47
TC7SH08FU_SSOP5~D
3
B B
POWER & INSTANT ON SWITCH

Media board CONN
2 SW1 1
EMI CLIP 1
JMEDIA
<37,9> POWER_SW#_MB 2 1
CLIP1 3 2
EMI_CLIP <37> VOL_MUTE 4 3
<37> VOL_DOWN 5 4 7
4 3 1 <37> VOL_UP 6 5 GND 8
GND 6 GND
SKRBAAE010_4P
CONN@
ACES_50506-00641-P01
LED Circuit Control Table

Fiducial Mark
@ FD1
1 SYS_LED_MASK# LID_CL#
FIDUCIAL MARK~D
@ FD2
Mask All LEDs (Sniffer Function) 0 X
1
A
Mask Base MB LEDs (Lid Closed) 1 0 A
FIDUCIAL MARK~D
Do not Mask LEDs (Lid Opened) 1 1
@ FD3
1
FIDUCIAL MARK~D @ ST1 @ ST2

@ H1 @ H2 @ H3 @ H4 @ H5 @ H6 @ H8 @ H9 @ H10 @ H11 @ H12 @ H13 @ H14 @ H15 @ H16 @ H17 @ H18 @ H19 @ H21 @ H22 @ H23 @ H24 CLIP_C5P5 CLIP_C5P5
@ FD4 H_2P8 H_2P8 H_3P1 H_2P8 H_2P8 H_3P1 H_3P8 H_3P8 H_3P8 H_3P8 H_5P0 H_2P8 H_2P3 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_1P0N H_1P0N H_2P1 H_2P1X2P6
1 DELL CONFIDENTIAL/PROPRIETARY
1
FIDUCIAL MARK~D
1
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT PAD, LED
LA-9591P
5 4 3 2 1
5 4 3 2 1
+COINCELL
COIN RTC Battery
1
PR1
1K_0402_5%~D
+3.3V_RTC_LDO
2
@ JRTC1
Z4012
1 3
+COINCELL 2 1 G 4
2 G
D D
TYCO_2-1775293-2~D
2
+RTC_CELL
1
PD1 PD2
TVNST52302AB0_SOT523-3 TVNST52302AB0_SOT523-3 PD3
PL1
1
FBMJ4516HS720NT_2P~D +3.3V_ALW BAS40CW SOT-323 1
1 2 PC1
3
Primary Battery Connector 1U_0603_10V4Z~D
PL2
1
FBMJ4516HS720NT_2P~D 2
PBATT+_C 1 2 +PBATT
PR2
1
LLTOP_ALLTOP C144LS-109A9-L 9P BATT P2 @ PC2
1 0.1U_0603_25V7K~D 100K_0402_5%~D
2
1 2 PRP2
2
2 3 Z4304 8 1
2200P_0402_50V7K~D
3 4 PBAT_SMBCLK <37>
Z4305 7 2
4 5 PBAT_SMBDAT <37>
Z4306 6 3
5 6 PBAT_PRES# <36,48>
1
PC3
5 4
6 7
7 8 100_0804_8P4R_5% PQ1
2
8 9 ME2301D-G 1P SOT-23-3
9 10 PD4
GND 11 1 2 1 3
3
GND DOCK_SMB_ALERT# <34,36,48>
@ PBATT1 SDMK0340L-7-F_SOD323-2~D
2
2
@ PR6
GND 1 2
<34,36,48> SLICE_BAT_PRES#
0_0402_5%
1
PC4
C C
1500P_0402_7K~D
2
+5V_ALW
+3.3V_ALW
2
@ PD5
DA204U_SOT323~D GND
@ PR7 PU111
2
change from 0603 to 0402 size PN: SM010028600 1 2
<34> DOCK_PSID
1
NO IN
6
GPIO_PSID_SELECT <36>
0_0402_5%~D
PR8
1
2 5
PL3 PR9
2.2K_0402_5%~D GND V+ +5V_ALW
1
BLM15AG102SN1D_2P 33_0402_5%~D
NB_PSID 2 1 1 3 1 2 NB_PSID_TS5A63157 3 4
D
S
NC COM PS_ID <37>
PQ2 TS5A63157DCKR_SC70-6~D
2
FDV301N_G_NL_SOT23-3~D +5V_ALW
G
2
PR10
100K_0402_1%~D
1
1
B B
C
2 PQ3 PR11
B MMST3904-7-F_SOT323~D 10K_0402_1%~D
E
3
2
2
PR12
@ PR13
15K_0402_1%~D
1 2
PSID_DISABLE# <36>
1
10K_0402_5%~D
DC_IN+ Source
+DC_IN +DC_IN_SS
PQ4
FDMC6679AZ_MLP8-5
DCX124EK-7-F PNP/NPN_SC74-6~D
1
PL4 2
FBMJ4516HS720NT_2P~D 3 5
1 2 +DC_IN
3
1
1M_0402_5%~D
0.022U_0805_50V7K~D
4
2
PQ6B
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
100K_0402_5%~D
10U_0805_25V6K
PR14
0.1U_0603_25V7K~D
1
1
PC5
2
VZ0603M260APT_0603
1
1
PC10
PC8
ACES_50299-00501-003
PR15
PC7
1000P_0603_50V7K~D
PC6
2
2
1
7
0.1U_0603_25V7K~D
PR17
4.7K_0805_5%~D
PD6
GND 6
1
1 2
SOFT_START_GC @ <48> @ @
2
GND
1
PC9
PC11
2
5 -DCIN_JACK @ 10K_0402_5%~D
PR16
5
1
4 2
2
4 3 +DCIN_JACK 5
@ AC_DIS <36,48>
2
3 2
A PR18 A
@
2 1 PQ6A
1 1M_0402_5%~D
2
DCX124EK-7-F PNP/NPN_SC74-6~D
6
@ PJPDC1 PJP1
1 2
PAD-OPEN 1x3m
1
PC12 @ Compal Electronics, Inc.

2
0.1U_0603_25V7K~D Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D +DCIN
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Size Document Number Rev
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 0.4
LA-9591P
5 4 3 2 1
A B C D E
+3.3V_RTC_LDO
1 1
+3.3V_ALW2
PR100 PR101
6.49K_0402_1%~D 15K_0402_1%
1 2 2 1
PR102 PR104
4.7U_0603_10V6K
10K_0402_5%~D 10K_0402_5%~D
1 2 @ PR103 2 1
1
PC100
0_0402_5%
@ PJP100
2
1 2 <37> ALW_PWRGD_3V_5V
2
PR105
+DC1_PWR_SRC
2
PR106
PAD-OPEN 1x3m 20K_0402_1%~D
16.9K_0402_1%
+DC1_PWR_SRC +3.3V_ALW
1
1
PL100
1UH_PCMB053T-1R0MS_7A_20%
2200P_0402_50V7K
2 1 PU100
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
1
1
PR107
PC106
PC102
PC103
CS2
VFB2
VREG3
VFB1
CS1
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
PC101
0.1U_0402_25V6
100K_0402_1%~D 21
PAD
1
1
PC104
6
PC107
EN
2
EN2
5
PC108
PC105
14 @
@
1
VO1
5
2 @ PR108 2
PR114 @
2
1 2 PGOOD_3V_5V 7 200_0402_1%
@ PGOOD 19 2 1
@ @
0_0402_5% VCLK
4 UG_3V 10 TPS51285BRUKR QFN 20P
+PWR_SRC PC109 PR110 DRVH2 16 UG_5V 4
PQ100 0.1U_0603_25V7K 2.2_0603_5% DRVH1 PR109 PC110
FDMC8884_POWER33-8-5 1 2 1 2 BST_3V 9 2.2_0603_5% 0.1U_0603_25V7K
VBST2 17 BST_5V 1 2 1 2 PQ101
1
2
3
VBST1
3
2
1
SW2 8 FDMC8884_POWER33-8-5
SW2 18 SW1
VREG5
DRVL2
DRVL1
PL101 SW1 PL102
+3.3V_ALWP +5V_ALWP
EN1
VIN
2.2UH_ETQP3W2R2WFN_8.5A_20% 3.3UH_ETQP3W3R3WFN_7A_20%
2 1 1 2
11
12
13
20
15
5
5
0.1U_0603_25V7K
220U_6.3V_R18M
220U_6.3V_R18M
1
1 @ PC111 1
EN
0.1U_0603_25V7K
680P_0603_50V7K LG_3V LG_5V
1
PC112
PC113
PC115
+ PC114 @ +
2
680P_0603_50V7K
PC116
4 4
2
2 2
@ @ PQ102 @
2
1
0.1U_0603_25V7K
4.7U_0603_10V6K
FDMC7692S_POWER33-8-5 PQ103 @
1
1
2
3
3
2
1
1
1
FDMC7692S_POWER33-8-5
PC117
PC118
PR112 @
@ PR111
4.7_1206_5% 4.7_1206_5%
2
2
20130510: 20130510:
3 3
PC113_X76 to control PC115_X76 to control
X7651731L21 for ECAP MAIN +DC1_PWR_SRC +5V_ALW2 X7651731L21 for ECAP MAIN
X7651731L22 for ECAP 2ND X7651731L22 for ECAP 2ND
EN
3VALWP
TDC 6.7 A
Peak Current 8.1 A @ PR113
PJP101
2 1
OCP Current 9.72 A <37> ALWON
+5V_ALWP 1 2
+5V_ALW 5VALWP
0_0402_5%
Rds(on): 13.6m ohm (max) TDC 4.88 A
PAD-OPEN 1x3m
PJP102
Peak Current 6.89 A
1 2
+3.3V_ALW OCP Current 8.268 A
+3.3V_ALWP
Rds(on):13.6m ohm (max)
PAD-OPEN 1x3m
1U_0603_10V6K
1
PC119
4 4

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +5V_ALW/3.3V_ALW
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9591P
A B C D E
5 4 3 2 1
1.35Volt +/- 5%
TDC: 7.2 A 0.75Volt +/- 5%
Peak Current: 10 A TDC 0.525A
OCP current: 12 A Peak Current 0.75A
Rds(on): 13.6m ohm(max) OCP Current 0.9A
+PWR_SRC PJP200
D 2 1 1.35V_B+ D
PJP201
PR200
PAD-OPEN 1x2m~D 1 2 BOOT_1.35V +VLDOIN_1.35V 2 1 +1.35V_MEN_P
2.2_0603_5%~D
PAD-OPEN1x1m
+0.675V_P
2200P_0402_50V7K~D
0.1U_0402_25V6
DH_1.35V
4.7U_0805_25V6K~D
4.7U_0805_25V6K~D
0.22U_0603_16V7K~D
22U_0805_6.3V6M
1
2
SW _1.35V
PC202
PC200
PC201
PC203
PC204
2
1
5
PC205
DL_1.35V
16
17
18
19
20
@ @ PU11
VLDOIN
PHASE
UGATE
BOOT
VTT
2
21
PAD
4 15 1
+1.35V_MEN_P PQ200 LGATE VTTGND
FDMC8884_POWER33-8-5
PR201 14 2
PL200 23.7K_0402_1% PGND VTTSNS +V_DDR_REF
1
2
3
1UH_PCMB063T-1R0MS_12A_20% 1 2 CS_1.35V
1 2 13 3
PC209 CS RT8207MZQW_WQFN20_3X3 GND
5
1U_0603_10V6K~D
12 4 +V_DDR_REF
@ PC208 VDDP VTTREF
1
330U_2.5V_ESR16M
1 @
680P_0603_50V7K PR202
+1.35V_MEN_P
PC207
C + 1 2 VDD_1.35V 11 5 C
SNUB_1.35V 2
VDD VDDQ
PGOOD
4 5.1_0603_5%~D
+5V_ALW
TON
2 PQ201
PC212
FB sense trace
FB
S5
S3
PC211
FDMC7692S_POWER33-8-5 0.033U_0402_16V7~D
1U_0603_10V6K~D when FB pull down to GND
1
2
3
10
6
+5V_ALW
+3.3V_ALW
20130510:
1
PR205
1
PC207_X76 to control @ PR203 8.06K_0402_1%~D
PR204 1.35V_FB 2 1
X7651731L21 for ECAP MAIN 4.7_1206_5%
100K_0402_1%~D
X7651731L22 for ECAP 2ND
2
PC213
2
100P_0402_50V8J~D
<37> 1.35V_SUS_PWRGD 1.35V_SUS_PWRGD 2 1
PR206
@ PR207 1.35V_B+ 1 2
0_0402_5%~D
1M_0402_1%~D
1 2 S5_1.35V
<36,39,9> SIO_SLP_S4#
1
@ PR208 PR209 @ PC214
1 2 10K_0402_1%
<36,39> SUS_ON @ PR210 0.1U_0402_16V7K~D
0_0402_5%
2
1 2
<18> 0.675V_DDR_VTT_ON
1
1
@ PC215 0_0402_5%
B B
0.1U_0402_16V7K~D @ PR211
2
1 2
<36,39,9> SIO_SLP_S3#
0_0402_5%~D
Mode S3 S5 +1.5V_MEN +V_DDR_REF +0.75V_P
S5 L L off off off
S3 L H on on off(Hi-Z)
+1.35V_MEN_P
S0 H H on on on
FB sense trace
PJP203
2 1
2 1
JUMP_1x3m
PJP204
PJP202
+1.35V_MEN_P 2 1
+1.35V_MEM
2 1
+0.675V_P 2 1 +0.675V_DDR_VTT
JUMP_1x3m
PAD-OPEN1x1m
A A
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +1.35V_MEN/+0.675V_DDR_VTT
5 4 3 2 1
5 4 3 2 1
PJP300
+V1.05SP_B+ 2 1
+PWR_SRC
PAD-OPEN 1x2m~D
2200P_0402_50V7K
4.7U_0805_25V6K~D
0.1U_0402_25V6
10U_0805_25V
1
1
D D
+3.3V_ALW
PC300
PC301
PC302
PC303
2
2
1
@ @
4 @
PR300
PR301 PC304
100K_0402_1%~D 2.2_0603_5% 0.1U_0603_25V7K
1 2 1 2 PQ300
2
FDMC8884_POWER33-8-5
3
2
1
<37> 1.05V_A_PWRGD PU300
1 10 BST_+V1.05SP
PGOOD VBST
1 PR302 2 2 9
TRIP_+V1.05SP UG_+V1.05SP PL300
TRIP DRVH 2.2UH_ETQP3W2R2WFN_8.5A_20%
95.3K_0402_1%
EN_+V1.05SP 3
EN SW
8 SW_+V1.05SP 1 2 +1.05V_MP
5
@ PR303 FB_+V1.05SP 4 7
<36,39,9> SIO_SLP_A# 1 2 VFB V5IN +5V_ALW
0_0402_5%~D RF_+V1.05SP 5 6 LG_+V1.05SP 1
RF DRVL
1
S0 mode be high level
1
11 @ PC306 +
TP PC305 PC307
4
2
C 680P_0603_50V7K C
@ PR304 TPS51212DSCR_SON10_3X3 1U_0402_6.3V6K~D 220U_B2_2.5VM_R15M
2
1 2 PQ301 2
<37,39> A_ON
1
0_0402_5% FDMC7692S_POWER33-8-5
1
@ PR306
3
2
1
PR305
4.7_1206_5%
1
@ PC308 470K_0402_1%
2
2
0.1U_0402_16V7K
2
PR307
2 1
4.99K_0402_1%
+1.05Volt +/- 5%
2
TDC 3.67 A
B PR308 B
Peak Current 5.25 A
10K_0402_1%
PJP301 OCP current 6.3 A
1
+1.05V_MP 2 1 +1.05V_M Rds(on): 13.6m ohm (max)

PAD-OPEN 1x2m~D
A
DELL CONFIDENTIAL/PROPRIETARY A

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +1.05V_M
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN +3.3V_ALW
D D
+5V_ALW
1
PJP400 @ PJP402
PAD-OPEN1x1m PAD-OPEN1x1m
1
PC400
2
1U_0402_6.3V6K
2
6
1
5
VCNTL
7 VIN PC401
POK 4.7U_0805_6.3V6K
+3.3V_RUN 4
PJP401
2
VOUT
3 1.5VSP 2 1
PR400
VOUT
+1.5V_THERMAL
1
1 2 8 2 PAD-OPEN1x1m
EN FB
1
GND
100K_0402_5%~D
9 PR402 PC403
VIN
1
1.54K_0402_1% 0.01U_0402_25V7K
1
@ PR401 @ PC402 PU400 PC404
2
2
47K_0402_5% 0.1U_0402_16V7K APL5930KAI-TRG_SO8 22U_0805_6.3V6M
2
1
2
C PR403 C
1.74K_0402_1%
2
B B
A A
Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date <Issued_Date> Deciphered Date <Deciphered_Date> Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.05VS_VTTP/+1.0VSP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Chief River VC 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2 1
5 4 3 2 1
20120911 TI-Alex Note: Although there is no pulse-overlap in 1-phase mode, during USR, the pulse comes in immediately.
So, the problem with PR504 = DNP is that if there is a high ripple, and USR is faultily detected, you will get a double-pulse.
So, we want to make sure USR is not active if it is not necessary. So, I moved it all the way to highest level so PR504 works to 8.87k.
VREF
100K_0402_1%_NCP15WF104F03RC
1
IMON
8.87K_0402_1%
PH500
2
2
365K_0402_1%
1M_0402_1%
4700P_0603_50V7K
75_0402_1%
PC500
PR502
PR501
PR503
1 PR504
@ PR500
1
75_0402_1%
@
1
10K_0402_5%~D
0.1U_0402_16V7K~D
2
D OCP-I B-RAMP F-IMAX O-USR D
1
PR505
SLEWA
2
150K_0402_1%
75K_0402_1%
150K_0402_1%
150K_0402_1%
PC501
PR508
+PWR_SRC
1 PR506
PR507
PR509
2
2
@ PJP500
1
PR510
1 2 +VCC_PWR_SRC
39K_0402_5%~D
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
PAD-OPEN 4x4m
330U_2.5V_ESR17M
1 1 1
33U_D_25VM_R60M
100U_D3L_20VM_R55M
1
PC735
PC736
PC731
PC732
PC734
+
PC738
+ +
PC739
PL501
PR511
+VCC_PWR_SRC 1 2 1 2
2
FBMA-L11-453215-121LMA90T @ 2 2 @ 2
10K_0402_5%~D @PR536
@ PR536
2 1
H_VR_EN <15>
0_0402_5%
CSP1 2 1
16
15
14
13
12
11
10
9
PU500 IMVP_VR_ON <36>
@ PR537 0_0402_5%
CSN1
SLEWA
B-RAMP
F-IMAX
IMON
O-USR
OCP-I
THERM
VBAT SKIP#
PWM1
+3.3V_RUN 17 8
18 CSP1 VR_ON 7 @ PR513
+3.3V_RUN 19 CSN1 SKIP# 6 1 2 2
@ PR539
1
20 CSN2 PWM1 5 75_0402_1% H_VR_READY <15>
CSP2 PWM2 0_0402_5%
21 4
PU3 N/C @ PR540
22 3 2 1
23 N/C PGOOD 2 IMVP_PWRGD <36>
GFB VDD 0_0402_5%
24 1 @ PR516
VFB VDIO
GFB
VFB
1 2
+3.3V_RUN
VIDSOUT
1.91K_0402_1%~D
VR_HOT#
ALERT#
PU501
COMP
DROP
VREF
VCLK
GND
GND
9 +VCC_CORE
V5A
C PC504 C
PR519 PWM1 8 PGND2
2 1 PWM PL500
1_0603_5%
+3.3V_RUN 1 2 7
BOOT VSW
4 0.22UH_FDUE0640J-H-R22M=P3_25A_20%
3
25
26
27
28
29
30
31
32
33
TPS51622RSM PC503 0.1U_0402_25V6 4 1

2 1 6 PGND1 2 PR520
BOOT_R VDD
4.7_1206_5%~D
5 1SKIP#1 1 2
SKIP#
2
1
1000P_0402_50V7K~D PR517 VIN SKIP# 3 2
1 2 0_0603_5%~D
@ PC506 PC505
1U_0603_10V6K
1 2 PR522
PR521 @ 0_0402_5%
1 2 1 2
1
100P_0402_50V8~D
2.32K_0402_1% TI recommend 1nF CSD97374CQ4M_SON8_3P5X4P5
@
1 PR523 2
1VR_HOT#
VREF
680P_0603_50V7K~D
10K_0402_5%~D
PC508
2
2
1 2 1 2 PC507
VIDALERT_N
0_0402_5%
PR534
0.33U_0603_10V7K~D @
2
1
PR535 PC509
VIDSCLK
PC512
4.87K_0402_1% 1500P_0402_50V7K 1U_0603_10V7K~D
2 1 @ +5V_RUN
1
2
+5V_ALW
1U_0603_10V7K~D
PR526
2
PC510
10_0603_1%
1
PR512
47P_0402_50V8J~D
2
2.1K_0402_1%~D
2 1 CSP1
1
10K_0402_1%_TSM0A103F34D1RZ
PC514
<37,47,48,9> H_PROCHOT#
PH501
+1.05V_VCCST
0.068U_0402_16V7K
0.068U_0402_16V7K
2
2
B B
3.01K_0402_1%
43.2K_0402_1%
1
1
PC502
1
1
1
PC513
54.9_0402_1%
110_0402_1%
PR515
75_0402_1%
PR514
PR529
PC511
PR527
PR528
0.1U_0402_25V6
2
2
2
@
2
@ PR531
2 1 VFB CSN1
<15> VIDSCLK <15> VCCSENSE
0_0402_5%
<15> VIDALERT_N
from processor
<15> VIDSOUT @ PR532
2 1 GFB
<17> VSSSENSE
0_0402_5%
CPU
TDC 10 A
Peak Current 32 A
OCP Current 38.4 A
DCR: 0.82m +-5% ohm
PH500 B value: 4250k 1%
PH501 B value: 3435k 1%
A A
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc.

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +VCC_CORE
5 4 3 2 1
5 4 3 2 1
PL700
1UH_PCMB042T-1R0MS_4.5A_20%
2 1
PQ700 V30415-T1-GE3 1P POWERPAK1212-8
+PWR_SRC_AC CHAGER_SRC
1
+SDC_IN PR700
0.01_1206_1%~D @ PJP700
2
5 3 4 1 1 2
+DC_IN_SS sense adapter
0.1U_0603_25V7K~D
3 2 PAD-OPEN 4x4m
0.1U_0603_25V7K~D
47P_0402_50V8J~D
@
1
@ PR710
PC701
PC702
@ PR701 <37> VCP 1 2
PC700
1 2 0_0402_5%
DC_BLOCK_GC <48>
2
1
@ PR702 D @ @
0_0402_5% 1 2 2 PQ701
<48> CSS_GC
G NTR4502PT1G_SOT23-3~D
0_0402_5%
1
D D
D S PU703
3
2 PQ703A 1 6
G SI3993CDV-T1-GE3_TSOP6~D REF Out
PQ702 S CSSN_1
S
NTR4502PT1G_SOT23-3~D 5 6
D
PD701 DOCK_DCIN_IS+ <34>
PR748
2 44.2_0402_1%~D
+DOCK_PWR_BAR
CSSN_1
CSSP_1
2 5 2 1
G
1
1 PQ703B GND IN-
3
PR703 SI3993CDV-T1-GE3_TSOP6~D +SDC_IN 3
V+ IN+
4
10K_0402_5%~D
+DC_IN_SS PR749
10_0402_5%~D
10_0402_5%~D
S
2 1 2 4 2 1 CSSP_1
D
100K_0402_1%~D
DOCK_DCIN_IS- <34>
BAT54CW_SOT323~D INA199A1DCKR_SC70-6~D
PC733 59_0402_1%
1
PR704
PR705
PR706
100K_0402_1%~D
1
1
@ PR708
G
0.1U_0603_25V7K~D
3
1 2
<48> +CHGR_DC_IN
2
PR707
PC703 PC704
1_0805_1%~D 1U_0603_25V6K 0.1U_0603_25V7K~D PC705 Discrete current monitor circuit
2
10_1206_5%~D
1 2 1 2 1 2 @ PR709
2
1
1 2
DK_CSS_GC <48>
PR745
0.1U_0603_25V7K~D 0_0402_5%
+SDC_IN GNDA_CHG
GNDA_CHG PC709
1
PC706 PU700 1 2
10U_0805_25V6K
ACP
ACN
2
2
PR713 2 1 +DCIN 20 16 BQ24715_REGN 1U_0603_10V6K~D
VCC REGN PD702
261K_0402_1%
+SDC_IN BAT54HT1G_SOD323-2~D
22U_0805_25V6M
22U_0805_25V6M
22U_0805_25V6M
22U_0805_25V6M
22U_0805_25V6M
22U_0805_25V6M
2200P_0402_50V7K~D
0.1U_0603_25V7K~D
PR714 @ PR725
49.9K_0402_1%~D 1 2 3 17 PR715
1
2 1 CMSRC BTST 2.2_0603_5%
0_0402_5%
1
1
1
PC742
PC744
PC707
PC710
PC711
PC712
PC741
PC743
1 2
2 1 4 18 CHG_UGATE 4
2
2
2
ACDRV HIDRV
0.047U_0603_25V7M
@ @ @
1
PC708 0.1U_0402_25V6
PC713
C GNDA_CHG C
6 19
3
2
1
ACDET PHASE
PQ704
BQ24715_REGN SIRA14DP-T1GE3_POWERPAK-SO8-5
+PWR_SRC
100K_0402_1%~D
<37> CHARGER_SMBDAT 8 15 CHG_LGATE

SDA LODRV
1
PR747
9 14 PR716
+VCHGR
<37> CHARGER_SMBCLK SCL GND PL701
0.01_1206_1%~D
3.3UH_FDVE1040-H-3R3M=P3_11.3A_20%~D
2
@ PR717 2 1 4 1
1 2 5 13
<37,47,48> ACAV_IN ACOK SRP
1000P_0603_50V7K~D
3 2
10U_0805_25V6K
0_0402_5%
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0603_25V7K~D
121K_0402_1%~D
1
PC714
2
PC737
PC716
7 12
0_0402_5%
0_0402_5%
<37> V_SYS IOUT SRN
PR718
PR719
1
PR746
PC715
PC717
PC718
PC745
PC746
100P_0402_50V8J~D
PR722 @
2
+3.3V_ALW @ PR726 4.02K_0402_1%
@
2
2
@
2
PC719
1 2 10 11 1 2 4
1
CELL /BATDRV
2
@
TP
10K_0402_1%~D @ @
4.7_1206_5%~D
1
BQ24715RGRR_QFN
21
PR711 @ PC720 PC721
BQ24715_REGN1 2
3
2
1
GNDA_CHG GNDA_CHG PQ706 0.1U_0603_25V7K~D 0.1U_0603_25V7K~D PC722
PR724
1
10K_0402_1%~D 1 2 1 2 1 2
GNDA_CHG SIRA06DP-T1-GE3_POWERPAKSO-8
@ PR750 0.1U_0603_25V7K~D
1 2 @
<48> CHARGER_CELL_PIN
0_0402_5%
PJP701 GNDA_CHG
1 2 GNDA_CHG
@ PR751
1 2
+3.3V_ALW2 10K_0402_1%~D PAD-OPEN1x1m
GNDA_CHG
B BATDRV# <48> B
+5V_ALW H_PROCHOT# <37,46,48,9>
100P_0402_50V8J~D
0.01U_0402_25V7K~D
DYN_TUR_CURRENT_SET#
1
1
PC724
PC725
PR727
2
221K_0402_1%~D
45W High
2
+3.3V_ALW2 +5V_ALW @ @
PR729
@ PR728
0_0402_5%
1.8M_0402_1%
1
1 2
65W Low
1
1
PR730
150K_0402_1% PR732 BQ24715_REGN
+3.3V_ALW2
8
20K_0402_1%~D PU2A
DMN66D0LDW-7 2N SOT363-6
VCP 1 2 3
P
2
+
1
O
6
3
PQ710A
PQ710B
2
-
G
220P_0402_50V8J~D
LM393DR_SO8~D
4
210K_0402_1%
2 5 +DC_IN
69.8K_0402_1%
PC727
100P_0402_50V8J~D
+3.3V_ALW
1
10K_0402_1%~D
@ PC740 PR736
1
4
1
PR734
PR735
PC726
232K_0402_1%~D
1M_0402_1%~D
+3.3V_ALW
48.7K_0402_1%
2
1
220P_0402_50V8J
1
1 2
2
PR737
PR739
PR738
2
PC728
+5V_ALW
6 2
0.1U_0402_25V4Z~D
PQ712A 2 1
PR740
2
2
DMN66D0LDW-7 2N SOT363-6 100K_0402_5%~D
8
PU2B
5
2 PU3 5 @ PR741
P
<37> DYN_TUR_CURRNT_SET#
2
1 + 7 1 2 ACAV_IN_NB <37,48>
P
4 B 6 O
22.6K_0402_1%~D
42.2K_0402_1%~D
0_0402_5%
1
O 100P_0402_50V8J~D -
G
2
1
10K_0402_1%~D
PROCHOT_GATE <36>
100P_0402_50V8J~D
A
1
G
LM393DR_SO8~D
4
3
1
PC729
PR742
PR743
PC730
A A
3
TC7SH08FU_SSOP5~D
PR744
2
2
5
ACAV_IN <37,47,48>
2
2
PQ712B
Adapter Protection Circuit for Turbo Mode
4
Title
+GPU_CORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-9591P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Friday, May 17, 2013 Sheet 47 of 57
5 4 3 2 1
5 4 3 2 1
PD807 PQ801
PD806 NTR4502PT1G 1P SOT23-3 +3.3V_ALW
PDS5100H-13_POWERDI5-3~D
SDMK0340L-7-F_SOD323-2~D Purpose: Trigger PROCHOT# when PC801 PR801
+PBATT_IN_SS active battery is removed from
1
3 2 1 3 1 0.1U_0402_10V7K 100K_0402_5%~D
1 +NBDOCK_DC_IN_SS 1 2 2 1
2 system. +3.3V_ALW
6
2
Allows EC to re-establish
5
PQ809 PQ802A
SI4835DDY-T1-GE3_SO8~D PR802 system performance for battery SLICE_BAT_PRES# 1
P
1 8 B 4 2 DMN66D0LDW-7 2N_SOT363-6~D
100K_0402_5%~D
+BATT_SUM 2 7 next in line. SLICE_BAT_ON 2 O
+3.3V_ALW
1
A
G
3 6 H_PROCHOT# <37,46,47,9>
1
5
PU801
3
1
100K_0402_5%~D
+3.3V_ALW2
2
PR804 +PWR_SRC_AC TC7SH08FU_SSOP5~D
1
PR813
100K_0402_5%~D PR807
3
+3.3V_ALW 100K_0402_5%~D
6 2
PR808
1
PD800 100K_0402_5%~D PQ805B
2
PDS5100H-13_POWERDI5-3~D PC803 5 DMN66D0LDW-7 2N_SOT363-6~D
1
D 3 1 2 D
+3.3V_ALW2
2
DMN66D0LDW-7 2N_SOT363-6~D
+VCHGR 1 2 PR810
10K_0402_5%~D
SDMK0340L-7-F_SOD323-2~D
4
1
2 PQ807A 0.1U_0603_25V7K~D 100K_0402_5%~D
PR815
PC806
3
PQ800 1 2
2
2
SI4835DDY-T1-GE3_SO8~D PQ811
+PBATT +3.3V_ALW
PQ806B
1 8 PR816 1 8 PR817 2200P_0402_50V7K~D
2 2
2 DMN66D0LDW-7 2N_SOT363-6~D
6
PQ806A
2 7 100K_0402_5%~D 2 7 1 5 PC807 PC805
SLICE_BAT_PRES# <34,36,41,48> PR811
6
3 6 3 6 PQ807B 0.1U_0402_10V7K
330K_0402_5%~D 1 2 2 1 PQ805A
PD811
5 5 1 2
4
0.47U_0805_25V7K~D @ 0_0402_5% 2 DMN66D0LDW-7 2N_SOT363-6~D
FDS6679AZ-G_SO8~D SLICE_BAT_ON 5 2
4
1
1
PBAT_PRES# 1
P
4
1
B
STSTART_DCBLOCK_GC
1
2
3
<47> BATDRV# 4
6
2 O
A
G
PQ812A
1
4 PU804
3
2 @ PD818
DMN66D0LDW-7 2N_SOT363-6~D PD808
PQ810
PDS5100H-13_POWERDI5-3~D SDMK0340L-7-F_SOD323-2~D
3
@ PR812 TC7SH08FU_SSOP5~D
1
FDS6679AZ-G_SO8~D
PR821 1 2 1 2
PQ812B
<36> DIS_BAT_PROCHOT# CHARGER_CELL_PIN <47>

820_0603_5%~D
0_0402_5%
<36,41> PBAT_PRES# 5 1 2 3301_DSCHRG_FET_GC
SLICE_BAT_ON <36,48>
8
7
6
5
2
3
PR814
330K_0402_5%~D
4
2 1
1
PC811
0.01U_0603_25V7K~D
+DOCK_PWR_BAR
5
PQ826
FDMC6679AZ_MLP8-5
4 +3.3V_ALW2
PC808
0.1U_0402_10V7K
Purpose: Turn on the PQ817
2 1 for primary or module bay
1
2
3
PU805
+3.3V_ALW2 TC7SH08FU_SSOP5~D battery to provide power to
5
100K_0402_5%~D
C PC810 1 SLICE_BAT_PRES#
dock side without AC exist.
<34,36,41,48>
C
P
@ B
2 1 4
1
PC809 PU806 O PR819 2
PR818
2 1
A +3.3V_ALW2
G
1500P_0402_7K~D TC7SH08FU_SSOP5~D 0.1U_0402_10V7K 100K_0402_5%~D
5
2
1
1 D
P
B
1
2
3
1 2 4 @ PR820 2 DOCK_DET# <34,36,48>
O 2 1 2 ACAV_IN# G
PD810
10K_0402_5%~D
A
G
S PQ817
0_0402_5%
3
1
4 SDMK0340L-7-F_SOD323-2~D DMN65D8LW-7_SOT323-3~D
PQ815
3
PR822
FDS6679AZ-G_SO8~D
2
AO3418_SOT23-3
8
7
6
5
1
D
2 +3.3V_ALW2 +3.3V_ALW2 Purpose: Turn on the PQ817
PQ816
G +3.3V_ALW2 for Slice battery discharge
S PC812
3
@ PR894
without AC exist
2
1 2 0.1U_0402_10V7K
+3.3V_ALW2 0_0402_5%~D
PQ829 2 1 PR823 PR824 @
1
SI2301CDS-T1-GE3 1P_SOT23-3 PU807
@ PR895 TC7SH08FU_SSOP5~D 100K_0402_5%~D 100K_0402_5%~D
PD813
3
1 2 3 1
5
PD814
+3.3V_ALW
1
0_0402_5% SDMK0340L-7-F_SOD323-2~D SDMK0340L-7-F_SOD323-2~D 1
P
B SLICE_BAT_ON <36,48>
1 2 4
1
@ PR825
2
O
3
2
2 1 2
2
PR830 A
PQ819B
100K_0402_5%~D 0_0402_5%
DMN65D8LW-7_SOT323-3~D
1
D 5 ACAV_IN#
PD820 PQ813A 2
2
NTR4502PT1G 1P SOT23-3
SDMK0340L-7-F_SOD323-2~D DMN66D0LDW-7 2N_SOT363-6~D @
PR826 PD819 G
4
<34,36,41,48> SLICE_BAT_PRES# 1 2 1 6 2 1 SDMK0340L-7-F_SOD323-2~D S
PQ818
3
100K_0402_5%~D 1 2
DOCK_SMB_ALERT# <34,36,41>
D PQ832
1
PR828 PQ813B
6
<36,41> AC_DIS DMN65D8LW-7_SOT323-3~D
2
1 2 2
1
DMN66D0LDW-7 2N_SOT363-6~D 1
PQ814
10K_0402_5%~D G 4 3 2
S PR829
2 1 2 2
3
SLICE_PERF_EN <37,48>
+3.3V_ALW2 3
3
100K_0402_5%~D @ PQ819A
5
1
@ PR832 DMN66D0LDW-7 2N_SOT363-6~D
PR827
0_0402_5% 1 2
@ PR834
0_0402_5%
2
@ PR831 2 1
0_0402_5%~D
PR853
B 100K_0402_5%~D 1 2 B
0_0402_5% +DOCK_PWR_BAR SLICE_BAT_PRES# <34,36,41,48>
PR848
+DC_IN_SS 1 2 +NBDOCK_DC_IN_SS 0_0402_5%
1
@ SLICE_BAT_PRES# <34,36,41,48>
@
3
S
1 2
DSCHRG_MOSFET_GC
2 PR841 1 3301_DSCHRG_FET_GC @
1
G
1 2 @ PR861 2 PQ828 PD816
1
<47> +CHGR_DC_IN 0_0402_5%
@ PR833 <37,48> 0_0402_5% DMN65D8LW-7_SOT323-3~D SDMK0340L-7-F_SOD323-2~D
CHGVR_DCIN
PR835 SLICE_PERF_EN DOCK_DET# D PD821

0_0402_5%
DK_PWRBAR
1
PD815
2
1 2 CD3301_DCIN PQ821A SDMK0340L-7-F_SOD323-2~D
+DC_IN
DC_IN_SS
<34,36,48>
2 DMN66D0LDW-7 2N_SOT363-6~D PR839
47_0805_5%~D
NTR4502PT1G_SOT23-3~D
@PR838
@ 1 6 2 1
2
PR838
1
PC813 2 1 1 100K_0402_5%~D
DOCK_AC_OFF <34>
0.1U_0603_50V4Z~D 0_0402_5%
+PBATT PQ821B PQ831
@ PR843 3
2
2
1
1
DMN66D0LDW-7 2N_SOT363-6~D 1 DMN65D8LW-7_SOT323-3~D
0_0402_5%
1
1
PQ830
P50ALW 1 2 BAT54CW_SOT323~D 4 3 PR849 2 PQ822
36
35
34
33
32
31
30
29
28
@ PR844
PR846 PU800 +5V_ALW 2 1 2 2 1 1 3
+3.3V_ALW2
S
2
+3.3V_ALW2 <41> 1 SOFT_START_GC
2 @PR850
@ 10K_0402_5%~D +3.3V_ALW2 3
NTR4502PT1G 1P SOT23-3
2
NC
CHARGERVR_DCIN
DK_PWRBAR
GND
NC
BLK_MOSFET_GC
DSCHRG_MOSFET_GC
DC_IN_SS
PBatt+
PR850
3
1 2 100K_0402_5%~D PR837 PC814
CD_PBATT_OFF 3
3
SLICE_BAT_ON <36,48>
2
100K_0402_5%~D 100K_0402_5%~D 0.1U_0402_10V7K

@ PR847
G
0_0402_5%
2
1 2ACAVDK_SRC 1 PR840 2 2 1
<34> ACAV_DOCK_SRC#
2 1 +3.3V_ALW2
0_0402_5% 100K_0402_5%~D
2
1 27
5
2 DC_IN P50ALW 26 PR836
@ PR854 @ PR851
1
SS_GC PBATT_OFF @ PR855 @ PR852
1 2 ERC1 3 25 DK_AC_OFF 100K_0402_5%~D 1
+SDC_IN
P
ERC1 DK_AC_OFF_EN 0_0402_5% 0_0402_5%~D 0_0402_5% B SLICE_BAT_PRES# <34,36,41,48> PR864
4 24 3301_ACAV_IN_NB 1 2 4
0_0402_5%
5 ACAVDK_SRC ACAV_IN_NB 23
ACAV_IN_NB <37,47> +DC_IN_SS O 2 DOCK_DET# <34,36,48> 100K_0402_5%~D
+PBATT
1
G
GND GND
1
CD3301_SDC_IN 6 22 DK_AC_OFF_EN 1 2 <34,36,48>

SDC_IN DK_AC_OFF_EN DOCK_AC_OFF_EC <36> PU808
7 21 SL_BAT_PRES# @ PR857
2
3
<47> DC_BLOCK_GC ACAVIN 8 DC_BLK_GC SL_BAT_PRES# 20 0_0402_5% TC7SH08FU_SSOP5~D
PR858 <37,48> SLICE_PERF_EN DOCK_DET#
P33ALW2 9 ACAV_IN BLKNG_MOSFET_GC 19 1 2 ACAV_IN#
@ PR859
1 2 P33ALW2 NBDK_DCINSS
EN_DK_PWRBAR
<37,47,48> ACAV_IN @ PR860 1M_0402_5%~D

SS_DCBLK_GC
0_0402_5%
1
0_0402_5% @ PR872 D
1 2
DK_CSS_GC
SLICE_BAT_PRES# <34,36,41,48> 1 2 2
PWR_SRC
@ PQ823 <37,47,48> ACAV_IN

CSS_GC
G
P33ALW
@ PR862 37 ME2301D-G 1P SOT-23-3 0_0402_5%

1 2 TP S
ERC3
ERC2
@ PR863
+3.3V_ALW2
3
GND
PQ825
3
1 2 3 1
0_0402_5%
0_0402_5%
+NBDOCK_DC_IN_SS DMN65D8LW-7_SOT323-3~D
PR866
CD3301BRHHR_QFN36_6X6~D
0_0402_5%
10
11
12
13
14
15
16
17
18
2@ 1 @ PQ824A
2
EN_DOCK_PWR_BAR <36>
2
@ PR869 @ PR870 DMN66D0LDW-7 2N_SOT363-6~D

0.1U_0603_25V7K~D
<47> CSS_GC @ PR868

P33ALW 1 2 1 2 1 2 1 6
ERC2
<47> DK_CSS_GC
0_0402_5% +3.3V_ALW
1
240K_0402_5%~D 47K_0402_5%~D
PC815
ERC3
A @ PQ824B A
2
EN_DK_PWRBAR DMN66D0LDW-7 2N_SOT363-6~D

0.047U_0603_25V7M
2
@ PR856 1 2 4 3
0.1U_0402_25V4Z~D
PR874
+3.3V_ALW2
1
1 2 D
0_0402_5%~D DOCK_DET# <34,36,48> @ PR875
PC816
1M_0402_5%~D 2 2 1
1
100K_0402_5%~D
PC817
STSTART_DCBLOCK_GC G
5
S PQ827 @
3
@ PR877 <37,48> SLICE_PERF_EN

2
@ 3301_PWRSRC 1 2 DMN65D8LW-7_SOT323-3~D
0_0402_5% +PWR_SRC_AC
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Selector
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 0.4
LA-9591P
5 4 3 2 1
5 4 3 2 1
Based on PDDG rev 0.7 Table 5-1.
+VCC_CORE
D D
1 1 1 1 1
PC900 @ PC901 PC902 @ PC903 @ PC904 @
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
2 2 2 2 2
1 1 1 1 1
PC905 PC906 PC907 @ PC908 @ PC909
2 2 2 2 2
1 1 1 1 1
PC910 PC911@ PC912 @ PC913 PC914
2 2 2 2 2
C C
1 1 1 1
PC915 @ PC917 PC918 PC919 @
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
2 2 2 2
1 1 1 1
PC921 PC922 @ PC923 PC924 @
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
2 2 2 2
1
1 PC930
+
PC928 @ 330U_D2_2.5VY_R9M
22U_0805_6.3V6M
2 2
B B
A A
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL PROCESSOR DECOUPLING
5 4 3 2 1
5 4 3 2 1
Version Change List ( P. I. R. List ) Page 1

Request
Item Page# Title Date Owner Issue Description Solution Description Rev.
1 P45 1.5VSP 8/17 Compal Base power budget request, add 1.5V powre rail Add PU400
D D
2 P42 +5V/+3.3V 8/17 Compal reserver PR114 for TPS51282 application ADD @PR114
3 P47 Charger 8/17 Compal EC can't detect charger IC cause can't charger modify SMBus net for correct connect
4 P46 Vcore 8/17 Compal schematic control error cause can't set OCP add Vref net for correct connect
5 P48 Selector 8/17 Compal in order to meet latest multi-battery request change control signal for meet E5 request
6 P43 1.35V/0.675V 8/17 Compal chagne OCP setting change PR201 from 20k to 24.9k.
7 P42 +5V/+3.3V 10/22 Compal Reserve 0ohm for 3v5v enable debug Change PR113 X01
from SD03420018L (S RES 1/16W 2K +-1% 0402)
to SD028000080 (S RES 1/16W 0 +-5% 0402)
C C
8 10/22 Change PL300

P44 +1.05V_MP Compal +1.05V_MP EA for ripple portion can't meet
from SH00000PJ00 (S COIL 1UH +-20% PCMB063T-1R0MS 12A) X01
spec. 31.5mv, after change from 1u to 2.2u test is pass
to SH00000MR00 (S COIL 2.2UH +-20% ETQP3W2R2WFN 8.5A)
Change PU100
9 P42 +5V/+3.3V 10/22 Compal Original 3v5v IC -TPS51225 can't support 2cell battery from SA00005LS00 (S IC TPS51225CRUKR QFN 20P PWM) X01
follow TI suggestion, When TPS51285A/B is used, to SA000064T00 (S IC TPS51285BRUKR QFN 20P PWM)
please update the below four components. 1)2)Change PC118(VREG5 Cap) and PC100(VREG3 Cap)
1)VREG5 cap to 4.7uF from SE080105K80(S CER CAP 1U 10V K X5R 0603)
2)VREG3 cap to 4.7uF to SE00000MA00(S CER CAP 4.7U 10V K X5R 0603)
3)CS1 resistor to 1/5 of the Tps51275’s value
4)CS2 resistor to 1/5 of the Tps51275’s value 3) Change PR106(for CS1)
5)VCLK connection (when not be used): add 200-ohm to GND from SD03484528L (S RES 1/16W 84.5K +-1% 0402)
to SD034169280 (S RES 1/16W 16.9K +-1% 0402)
4) Change PR105(for CS2)

from SD03410038L (S RES 1/16W 100K +-1% 0402)
to SD034200280 (S RES 1/16W 20K +-1% 0402)
5) Add PR114 SD034200080(S RES 1/16W 200 +-1% 0402)

B B
P47 Charger 10/22 Compal To avoid HW and Power SMT materials can't entirely X01
10 replace
Change PU3,PU801,PU804,PU805,PU806,PU807
from SA74108040L(S IC 74AHC1G08GW SOT353 AND)
P48 Selector to SA00708012L(S IC TC7SH08FU SSOP 5P AND)
11 P47 Charger 10/22 Compal follow E5- Salado 14"15" schematic 1) @PQ819, @PQ824 X01
2) EMI request for add PL700
SH00000IW00(S COIL 1UH +-20% PCMB042T-1R0MS 4.5A)
Vcore 11/02 Compal follow TI suggestion modify setting value to meet Intel 1) Change PR501 X01
12 P46 VR12.6(ULV) validation EA from SD034422380 (S RES 1/16W 422K +-1% 0402)
1) Imon to SD034365380 (S RES 1/16W 365K +-1% 0402)
2) Loadline
3) transient 2) Change PR521
from SD000009M80 (S RES 1/16W 2.61K +-1% 0402)
to SD00000WS8L(S RES 1/16W 2.32K +-1% 0402)
3) @PC506 100p_0402 and change PR535

from SD02810028L(S RES 1/16W 10K +-5% 0402)
A to SD034487100 (S RES 1/16W 4.87K +-1% 0402 (LF)) A
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL PWR_PIR 1
5 4 3 2 1
5 4 3 2 1

Request
1) Change PR711
P47 Charger 11/05 Compal 1) TI suggestion BQ24715 cell pin pull high 3.3V change
D
13 to V_regn(6v) for sequence issue
from SD02800008L (S RES 1/16W 0 +-5% 0402) X01 D
to SD034100280 (S RES 1/16W 10K +-1% 0402)
,add PR750 SD028000080(S RES 1/16W 0 +-5% 0402)
2) Reserve 0 ohm for debug
2) Add @PR751
Compal 1) @PR863, @PR870, @PR869, @PR824, @PR875, @PQ823

14 P42 +5V/+3.3V 11/05 follow E5- Salado 14"15" schematic X01
2) Add @PR848, @PR851
and add PR834, PR852, PR853, all is
SD028000080(S RES 1/16W 0 +-5% 0402)
3) Add PR874 SD028100480(S RES 1/16W 1M +-5% 0402)
4) Add PD819 SCS0340L01L(S SCH DIO SDMK0340L-7-F SOD-323)
15 P47 Charger 11/05 Compal Improve charger efficiency Change PR715 X01
from SD028200A80 (S RES 1/16W 20 +-5% 0402)
to SD013220B80 (S RES 1/10W 2.2 +-5% 0603)
C C
16 P47 Charger 11/05 Compal Delete @PR731, @PR733, @PU702 X01

follow E5- Salado 14"15" schematic
Compal Support QAD WCEPTA analysis, to modify 1.05 OCP Rtrip Change PR302 X01
17 P44 +1.05VTTP 11/05 -QAD team from SD00000H880 (S RES 1/16W 54.9K +-1% 0402)
resistance to 95K, Cpk value will pass specification.
-Huang.Hanks to SD034953280 (S RES 1/16W 95.3K +-1% 0402 )
(PCP)
Compal EMC team suggestion @PC105, @PC203, @PC301 X01

18 P48 +5V/+3.3V 11/05
- EMC team
1.35V/0.675V Wen. Andy
+1.05V_MP
Add
B
19 P48 Selector 11/15 Compal follow E5- Salado 14"15" schematic
PQ827 SB00000UO00 (S TR DMN65D8LW-7 1N SOT323-3), X01 B
for undock shutdown issue @PR856 SD028000080 (S RES 1/16W 0 +-5% 0402),
PQ816 SB534020000 (S TR AO3402 1N SOT-23),
PQ828 SB00000UO00 (S TR DMN65D8LW-7 1N SOT323-3),
PR861 SD028000080 (S RES 1/16W 0 +-5% 0402)
PR802, PR827, PR840 change

from SD028240380 (S RES 1/16W 240K +-5% 0402)
to SD028470280 (S RES 1/16W 47K +-5% 0402),
PR804, PR826, PR839 change

from SD028470280 (S RES 1/16W 47K +-5% 0402),
to SD028240380 (S RES 1/16W 240K +-5% 0402)
P47 Charger 12/12 Compal Change PR713 X01

20 from SD034294380 (S RES 1/16W 294K +-1% 0402)
to SD034261380 (S RES 1/16W 261K +-1% 0402)
P48 Selector
A @PR844 A
21 P41 +DCIN 2013 Compal- ESD team's PD1 vendor(NXP) proposal PD1 pin 5 PD1 pin5 connect to +3.3V_ALW X01_2
connected to the VCC (5V or 3.3V). DELL CONFIDENTIAL/PROPRIETARY
/01/11 ESD team
Title
5 4 3 2 1
5 4 3 2 1

Request
1). Add PU808
22 P48 Selector 2013/ Compal To avoid +DOCK_PWR_BAR leakage voltage when system P/N: SA007080120 (S IC TC7SH08FU SSOP 5P AND)
X01_2
only with main battery
D
01/23 D
2). Add PQ830

P/N: SB000007900 (S TR NTR4502PT1G 1P SOT23-3)
3). Add PQ831

P/N: SB00000UO00 (S TR DMN65D8LW-7 1N SOT323-3)
4). Add PD821

P/N: SCS0340L010 (S SCH DIO SDMK0340L-7-F SOD-323)
5). Add PR836, PR837

P/N: SD028100380 (S RES 1/16W 100K +-5% 0402)
6). Add PC814

P/N: SE102104K00 (S CER CAP 0.1U 10V +-10% X7R 0402)
23 P41 +DCIN 2013 Compal PPM-Jovins_Chang and Sourcer-Willie_Zeng highlight Change PQ6 X02
SB000009N8L will shortage after 2013/05 From : SB000009N8L (S TR IMD2AT-108 PNP/NPN SC74-62)
C /02/07 To : SB000009P80 (TR DCX124EK-7-F PNP/NPN SC74R-6)
C
24 P48 Selector 2013/ Compal AC_DIS# should be change to AC_DIS because it’s 1). Change PQ6A.5 and PR828.1 net name from AC_DIS# X02
high active not low active for our application. to AC_DIS
02/18
2). Add PQ829
P/N: SB00000H500 (S TR SI2301CDS-T1-GE3 1P SOT23-3)
, PQ832
P/N: SB00000UO00 (S TR DMN65D8LW-7 1N SOT323-3)
, PD820
P/N: SCS0340L010 (S SCH DIO SDMK0340L-7-F SOD-323)
, @PR894
, PR895
P/N: SD028000080 (S RES 1/16W 0 +-5% 0402)
3). modify PR828,PR830

4). Delete PQ820
B 5). Delete PL5, add PJP1 B
25 P41 2013/ Compal-ME DFX highlight Battery connetor(locattion:PBATT1) Battery connetor(locattion:PBATT1) footprint follow
+DCIN ME team Iris requesti to change
X02
hard to insert.
02/18 from SUYIN_200277GR009M262ZR_9P-T
to ALLTO_C144LS-109A9-L_9P-T
26 P48 Selector 2013/ Compal layout spec limit Delete PD817, modify PD815 footprint same as PD701,
X02
from SDMK0340L-7-F_SOD323-2
02/18 to RB717F_SOT323-3
27 P41 +DCIN 2013 Compal- follow ESD team request Goliad 14 need change PD1(6 pin*1) as Goliad 12 X02
(3 pin*2), the main and 2nd source also,
/02/21 ESD team these two ESD diode need to close battery connector
Anderson as possible.
Change PD1 and add PD2

From : SC300001100 (S DIO(BR) IP4223CZ6 SO-6 ESD)
To : SCA00001W00 (S ZEN ROW TVNST52302AB0 C/C SOT523
ESD after check 1.75X1.7xH=0.9mm <ME H=1.5mm)
A A
Title
5 4 3 2 1
5 4 3 2 1

Request
1). Change PC703 from 0.1U to 1U
28 P48 Selector 2013/ Compal follow E5- Salado 14"15" schematic P/N: SE000006900 (S CER CAP 1UF 25V K X5R 0603) X02
D
02/21 D
2). Change PC706 from 1U to 10U

1) For Input current sense stablilze P/N: SE00000QK00 (S CER CAP 10U 25V K X5R 0805 H1.25)
2) To provent charger into sleep mode dual 3). Change PC708 from 0.01U to 0.1U
AC transient. P/N: SE00000G880 (S CER CAP 0.1U 25V K X5R 0402)
4). Change PR734 from 100K ohm to 210K ohm

3) Fine tune ACOK response time. P/N: SD034210380 (S RES 1/16W 210K +-1% 0402)
Change PR735 from 46.4K ohm to 69.8K ohm
P/N: SD034698280 (S RES 1/16W 69.8K +-1% 0402)
4) Adapter protect rating setting
5) Fine tune H_PROCHOT# response time. 5). Add @PC740
6). Change PR738.pin1 from BQ24715_REGN connect to +3.3V_ALW2.

6) Improve ACAV_IN_NB ref voltage accuracy.
Change PR738 from 118K ohm to 48.7K ohm
P/N: SD034487280 (S RES 1/16W 48.7K +1% 0402)
C
7) Improve current sense accuracy. Change PR744 from 12K ohm to 10K ohm
C
P/N: SD034100280 (S RES 1/16W 10K +-1%
7). Change PR748 from 6.8 ohm to 210K ohm

P/N: SD034442A80 (S RES 1/16W 44.2 +-1% 0402)
Change PR749 from 10 ohm to 69.8K ohm
P/N: SD00000W200 (S RES 1/16W 59 +-1% 0402)
29 P48 Selector 2013/ Compal Modify resistor value to meet voltage 1). Change PR802,PR827,PR840 from 47K ohm to 100K X02
02/27 tolerence P/N: SD028100380 (S RES 1/16W 100K +-5% 0402)
2). Change PR804,PR826,PR839 from 240K to 100K

P/N: SD028100380 (S RES 1/16W 100K +-5% 0402)
30 P47 Charger 2013/ Compal follow E5- Salado 14"15" schematic to 1). Add PC741, PC742 X02_1
03/18 add charger input MLCC to 88u P/N: SE00000XH80 (S CER CAP 22U 25V M X5R 0805 H1.25)
31 P42 +5V/+3.3V 2013/ Compal support DFX team change choke layout pad 1). Change PL101, PL102, PL200, PL300 PCB FootPrint X02_1 B
to avoid soldering issue change

P43 1.35V/0.675V 03/20 from CYNTE_PCMC063T-2R2MN_2P
P44 +1.05V_MP to CYNTE_PCMB064T-3R3MS_2P
1). Add PC930

32 P47 Charger 2013/ Compal Support acoustic team to reduce noise P/N: SGA00002680 (S POLY C 330U 2.5V Y D2 LESR9M X02_1
03/21 EEFS H1.9)
P49 PROCESSOR 2). Del PC916, PC920, PC925, PC926, PC927, PC929
DECOUPLING P/N: SE000001120 (S CER CAP 22U 6.3V M X5R 0805 H0.85)
3). Change PC738
P46 Vcore from 33U(SGA00005M00) to 100U
P/N: SGA00008R00 (S POLY C 100U 20V M D ESR55M
(D3L_H=2.8mm)
4). Depop PC928, PC924, PC919, PC915, PC911
and Add PC901
P/N: SE000001120 (S CER CAP 22U 6.3V M X5R 0805 H0.85)
A A
Title
5 4 3 2 1
5 4 3 2 1
Version Change List ( P. I. R. List )

Request
Item Page# Title Date Issue Description Solution Description Rev.
Owner
D D
1 40 36 HW 10/23/2012 DELL DELL drop Media LED function Remove backlight LED function and change connector to 6pin X01
2 10 HW 10/23/2012 COMPAL Remove EMI solution at Speaker side Remove R132, R133, R134 and R135 X01
3 22 HW 10/23/2012 DELL DELL drop ALS function Remove ALS interface from EC and CPU side than move touch screen X01
signal to eDP side
4 22 HW 10/23/2012 COMPAL change LCDVDD power control circuit change U9 from TPS22966 to APL3512 solution X01
5 22 HW 10/23/2012 COMPAL change Webcam power enable from PCH pop R106 and de-pop R102 X01
6 10 HW 10/23/2012 COMPAL remove eDP backlight control pull up resistor Remove RC150 X01
change +1.05V_RUN_VMM power enable signal from LP_EN to DOCKED and add
+3.3V_RUN_VMM for DP2320 series 3.3V power rail
remove L3 and move U6.E5 to +1.05V_VMM_VDD power rail
X01
C 7 21 HW 10/23/2012 COMPAL Vendor update schematic for power saving change U6.J4 to +3.3V_RUN_VDDA C
R85 change to 3.74K_1%

remove LP_EN, R232 and U6A.A5 to NC
remove R55 and pop-option R207 when use VMM2310
8 21 HW 10/23/2012 COMPAL change VMM2320 config remove DP to VGA PTN3392 circuit and add 0ohm pop option for 2320 config X01
9 18 19 HW 10/23/2012 COMPAL Remove DIMM VERF power rail from power side Remove RD2, RD4, RD8 and RD9 X01
10 26 HW 10/23/2012 COMPAL change miniDP OCP solution remove D10 R160 F2 and add U50 de-pop C383 X01
11 26 HW 10/23/2012 COMPAL refer salado 14" to change PCBEEP circuit remove C132,C146,R146,R138,C133 and C143 than add C145,C146,R147,R151 X01
and de-pop R194 R153
12 26 HW 10/23/2012 COMPAL If doesn't has external power, Sleeve will Add AUD_NB_MUTE# to control Sleeve pin.
be floating mode and no reference GND. X01
Move EC_WAKE# from ECE5048[L]5 to MEC5075 GPIO52.
HW X01
B 13 37,36,12 20 10/23/2012 COMPAL GPIO map update to 2.7 version Change name: 1.5V_SUS_PWRGD to 1.35V_SUS_PWRGD for DDR3L. B
Add NFC_DET# ECE5048 GPIOL[5] to NFC moudle and add pull

up 10K resistor
14 37 HW 11/8/2012 COMPAL Change board ID to X01 change R392 form 240K to 130Kohm X01
remove RC167,RC202,RC293 and RC290 then add RP4
10 remove R299,RC300,R301 and R296 then add RP8
12 remove R53,R54,R70 and R72 then add RP9
21 remove RC216,RC178,RC80 and RC21 then add RP11
15 HW 11/8/2012 COMPAL change to network resistor remove RC77,RC85,RC71 and RC215 then add RP12 X01
36
37 remove RC207,RC214,RC205 and RC164 then add RP13
remove R359,R361,R451 and R387 then add RP15
A
remove R344,R368,R369 and R372 then add RP18 A
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT EE P.I.R (1/5)
LA-9591P
5 4 3 2 1
5 4 3 2 1

Request
Owner
D D
16 22 HW 11/8/2012 COMPAL Add Mic power and remove DBC function Add 3.3V_RUN for Mic power and remove DBC function at JeDP.2 X01
17 39 HW 11/8/2012 COMPAL +1.05V_MODPHY can't meet INTEL timing spec change +1.05V_MODPHY to MOS solution X01
refer PDG1.0 to change SODIMM control change RC68, RC126 and RC173 from 2.2 to 2ohm 1%
18 19 HW 11/8/2012 COMPAL circuit resistor change RC67,RC69,RC130,RC132,RC217 and RC221 X01
from 1.82K to 1.8Kohm 1%
19 27,32,26,20,40 ME 11/8/2012 COMPAL ME change connector change JmDP1,JSIM1,JSPK1,JNFC1,JMEDIA,SW1,JSD1 X01
20 2, 3, 6, 34 HW 11/13/2012 COMPAL update SATA topology fro Mainstream CPU exchange SATA1&SATA2 topology
X01
21 12 HW 11/13/2012 COMPAL refer Goliad 12" add LAN_WAKE# T-topology add RC177 to link LAN_WAKE# and EC_WAKE# X01
22 15 HW 11/13/2012 COMPAL remove RC252 for cost saving change RC252 to PJP11(1mm jumper-short) X01
23 34 ME 11/14/2012 COMPAL ME change Docking connector change JDOCK1 X01

C C
MOW_WW46 request change for VCCUSB3PLL and change CC42 and CC49 from 1u_0402 to 22u_0603
24 16 HW 11/14/2012 INTEL VCCSATA3PLL change CC76 and CC77 from 100u_1206 to X01
22u_0603
25 20,28,30,31 HW 11/14/2012 COMPAL change AND gate to same source Change U20, U26, U29 and U30 from SA74108040L to SA00708012L X01
26 33 HW 11/14/2012 COMPAL add USB power cap 150u co-layout with 100u add C86,C89(1206) co-layout with C280,C290(B2) X01
27 24 HW 11/14/2012 COMPAL change AUX/DDC power rail same as VMM2320 Change U11,U13 power rail from +3.3V_RUN to +3.3V_RUN_VMM X01
28 38,12 HW 11/14/2012 COMPAL remove +3.3V_TP power load switch solution remove U40, R458,C424 and C423 X01
29 31 HW 11/14/2012 COMPAL remove TPS22965 solution remove U51(TPS22965) and U34(TPS22965) than add U3(TPS22966) X01
30 22 HW 11/15/2012 COMPAL change diode to daul-diode fro cost saving remove D4,D5,D6,D7 and add D10,D21 X01
B 31 9 HW 11/16/2012 COMPAL change APS pin 11 net_name for DELL APS debug Change JAPS1.11 net name from SIO_PWRBTN# to POWER_SW#_MB X01 B
add mSATA_DEVSLP from UC1.P2(DEVSLP1/GPIO38) to mSATA_HDD(JMINI2.44)

32 31,12 HW 11/16/2012 COMPAL add mSATA_DSLP for mSATA HDD and pull up 10K(R160 depop) to +3.3V_mSATA_WWAN. X01
de pop HDD_DEVSLP pull up resistor R155
33 37 HW 11/16/2012 COMPAL change thermal diode for cost saving change D11,D13 and D14 form SB000008P0L to SB33904510L X01
change net name from HOST_ALERT1_R_N to PCH_GPIO15, and pop RC190

34 12,28 HW 11/16/2012 COMPAL support TLS confidentility remove R188 X01
change L44 and L45 from SM01000558L to SM01000C500

35 38,26,30,22 HW 11/16/2012 COMPAL change Bead for cost reduce change L35 and L36 from SM01000AM0L to SM01000C500 X01
change LE1 from SM01000DH0L to SM01000BV00
change L21 from SM01001788L to SM010005N00
A A
LA-9591P
5 4 3 2 1
5 4 3 2 1

Request
Owner
D D
36 29 HW 11/19/2012 COMPAL exchange JUSH1,JMEDIA pin define for ME update exchange JUSH1 and JMEDIA pin define X01
37 25 HW 11/19/2012 COMPAL remove HDD_DEVSLP resisrtor remove R189 X01
38 37 HW 11/19/2012 COMPAL change thermal OTP to 98 degree change R394 from 1.24K to 1.82K_1% X01
39 28 HW 11/20/2012 COMPAL LOM LED issue reverse Q32,Q33 of C & D gate X01
22 40 38
40 HW 11/22/2012 COMPAL Remove ESD reserve location Per ESD experiment, D3,D27,D22,DE1,DE2 can be remove X01
26
41 15 HW 11/23/2012 COMPAL Per Intel CRB updated Change VCCST_PWRGD pull high value from 10K ohm to 1K ohm. X01
42 26 HW 11/23/2012 COMPAL Universal Jack no longer supported on X5 Remove D9,D11,R209,R210,C195,C196,R198,R199 X01

C C
43 12 HW 11/27/2012 COMPAL Change GPIO connection change NFC_DET# connection from EC GPIOL[5]/PWM2 to LPT_LP GPIO59 X01
To support mainstream and Premium CPU, Change docking SATA port form SATA port 1 to SATA port 0 and spindle HDD
44 6 HW 11/28/2012 COMPAL change to SATA port assignment. from port 0 to port 1
X01
To support the SATA DevSLP Change DEVSLP0/GPIO33 to mSATA_DEVSLP X01

45 12 HW 11/28/2012 COMPAL function for new SATA port assignment. and DEVSLP1 to HDD_DEVSLP
46 12 HW 11/28/2012 COMPAL USB port 0 EA result Change L42 from DLW21SN900SQ2L to OCE2012120YZF
X01
Change power control signal from 3.3V_WWAN_EN X01

47 31 HW 11/28/2012 COMPAL Change WWAN power control. & 3.3V_mSATA_EN to MCARD_WWAN_PWREN
Change power control signal from 3.3_1.5V_WLAN_EN

48 31 HW 11/28/2012 COMPAL Change WLAN power control. to AUX_EN_WOWL X01
B B
X01
49 38 HW 11/28/2012 COMPAL Per EMI test result Remove L44,L45
HW 11/28/2012 COMPAL Per EMI test result Change R259,R252,R253,R255,R257,R263,R265,R266

50 34 R260,R261,R254,R256,R262,R264,R258,R267 from 0 ohm to 33 ohm. X01
51 9 HW 1/9/2013 COMPAL add RSMRST pull down resistor add RC136 X01
52 38 HW 1/9/2013 COMPAL add repeater at USB3 RX IO connector side add U51 circuit X01
53 22 HW 1/9/2013 COMPAL change LCDVDD power chip soft start cap change C430 from 0.1u to 0.01u X01
54 36 HW 1/9/2013 COMPAL change dock SMbus alert pull up resistor change R292 from 10K to 100Kohm X01
55 40 HW 1/17/2013 COMPAL change LED series resistor form LED measure change R435 from 1.8K to 390ohm, change R430 from 2.2K to 220ohm,
A
change R434 from 220 to 150ohm, change R427 from 1K to 390ohm. X01 A
LA-9591P
5 4 3 2 1
5 4 3 2 1

Request
Owner
D D
56 1 9 HW 1/23/2013 COMPAL add XDP@ for XDP component change XDP circuit to XDP@ X02
57 37 HW 1/23/2013 COMPAL change board ID to ST config change R392 from 130K to 33Kohm X02
58 37 HW 1/30/2013 COMPAL change HW thermal shortdwon temperature change R394 from 1.82K to 1.58Kohm X02
change eDP connector pin define for factory 1.add pull down 1Kohm at JEDP1.29
59 22 HW 2/1/2013 COMPAL burn out issue 2.Swap JEDP1.1 and JEDP1.2 X02
update speaker EMI bead for audio precsison

60 26 HW 2/1/2013 COMPAL fail issue change L22~L25 from SM01000L300 to SM010019400 X02
61 26 HW 2/1/2013 COMPAL update XDP circuit for INTEL ITE can't boot remove RC121 and pop RC102 X02
62 36 HW 2/18/2013 COMPAL power update AC_DIS# circuit to high active change AC_DIS# net name to AC_DIS X02
Fixed 2 USB IO Port use the same OC# signal 1.change IO/B USB OC# from USB_OC0# to USB_OC1#
C 63 11 35 HW 2/21/2013 COMPAL issue 2.change USB_OC1#/3# to USB_OC1#, USB_OC3# and add RC166 for OC3# pull C
X02
up resistor
64 7 HW 2/21/2013 COMPAL add jumper for clock buffer co-layout add PJP12, PJP13 and PJP14 beween UC5 X02
65 7 HW 2/21/2013 COMPAL change TAA connector from ME request change JTAA1 from ACES_50185-02041-001 to PANAS_AXK820145WG X02
1.Pop CC71 and CC72

66 16 HW 2/22/2013 COMPAL add ESD solution 2.Add two 22u 0603 between +VCC_CORE and +1.05V_RUN power plan X02
3.Add 22u 0603 between +1.05V_RUN and +3.3V_RUN power plan
67 33 HW 2/22/2013 COMPAL change USB charge solution for SAMSUNG phone change U39 from SA00004VH00 to SA00006L600 X02
1. add CC86~CC89 between clock signal

68 7 HW 2/25/2013 COMPAL add RF noise solution at clock buffer X02
2. add RC62 for UC5 power rail
3. change RC100 from 0ohm short to 10ohm
4. change UC5 from IDT_5V60034DCG8 to CYPRESS_CY2304SXI-1T
B B
69 23 HW 2/25/2013 COMPAL refer INTEL MOW to update HDMI cost reduce cahnge R462~R469 resistor from 680(SD034680080) to 470ohm(SD034470080) X02
level shifter main link
For AOAC function, can’t wake up from S3 change net name from USB_OC3# to SIO_EXT_SMI#, and change SIO_EXT_SMI#
70 11 12 HW 2/25/2013 COMPAL X02
through SIO_EXT_SMI# to PCH_GPIO45
71 9 HW 2/26/2013 COMPAL add EMI solution at H_PROCHOT# add CC149_22P_0402(SE071220J80) depop for EMI request X02
72 26 HW 2/26/2013 COMPAL for Fixed BIOS flash HOTSOS issue change R154 from PCH_AUDIO_EN to RUN_ON X02
1.remove item 68 location and CC25 CC57 CC80 CC22 UC5 RC100 and CC23 X02
73 7 HW 2/28/2013 COMPAL remove clock Buffer solution 2.change RC65 to 0ohm_short
74 7 29 HW 2/28/2013 COMPAL refer GPIO3.0 to add PCH_TPM_LPC_EN add RC56 for pull up enable signal and add R198 for pop option X02
1. SD/MMCCD# add C256(0.1uF) & R493(1M) pull-down to GND
A 75 30 HW 3/12/2013 COMPAL For O2 enters into test mode unexpectedly 2. C222 change to 1uF(SE000000K80) from 0.1u(SE00000G880) X02 A
with SD card inserted incompletely issue.
LA-9591P
5 4 3 2 1
5 4 3 2 1

Request
Owner
D D
1. LANCLK_REQ# change to UC1.AD1 from UC1.Y5
2. MINI1CLK_REQ# change to UC1.T2 from UC1.U2
76 7 HW 3/13/2013 COMPAL Base on INTEL EDS SPEC Update Rev 1.5.1 3. MINI2CLK_REQ# change to UC1.N1 from UC1.T2 X02
4. MMICLK_REQ# change to UC1.U5 from UC1.AD1
5. PCH_TPM_LPC_EN change to UC1.Y5 from UC1.U5
1. CLK_PCIE_LAN change CLKOUT_PCIE port2

77 7 HW 3/14/2013 COMPAL For PCIE CLK & PCIE CLK REQ signal mapping 2. CLK_PCIE_MINI2 change CLKOUT_PCIE port3
3. CLK_PCIE_MMI change CLKOUT_PCIE port4 X02
4. CLK_PCIE_MINI1 change CLKOUT_PCIE port5
78 21 HW 3/15/2013 COMPAL remove VMM2310 co-layout schematic remove U8, R93, R98, R105 circuit X02
79 15 HW 3/15/2013 COMPAL add ESD solution add CC22 and CC57 X02
80 7 HW 3/18/2013 COMPAL For INTEL request PCIECLK_REQ0# add RC57(10k) pull-high to+3.3V_RUN X02
C C
21 HW 3/20/2013 COMPAL For Synaptics vender request 1. Delete R78/R80/R82 X02

81 2. add C132
82 9 12 HW 3/21/2013 COMPAL add ESD solution add CC90 and CC91 X02
83 35 HW 4/02/2013 COMPAL For USB3.0 1M cable Pop R478, R479 and change R476 to 3.01K ohm X02
84 37 HW 4/25/2013 COMPAL change board ID to A00 version change R392 from 33K to 1K ohm A00
85 33 HW 4/25/2013 COMPAL for JUSB2 can't wake from S3 issue change U33 power rail from +3.3V_RUN to +3.3V_SUS A00
86 9 HW 4/25/2013 COMPAL for XDP signal should be contact to PCH change RC97 and RC135 to 0ohm short A00
87 28 HW 4/25/2013 COMPAL for support Vpro reset pin depop U20 and add R145 A00
B 88 12 HW 4/25/2013 COMPAL reserve for support non vpro pop option pin reserve RC292 pull down A00 B
R434 change from 150 to 330ohm, R430 change from 220 to 330ohm, R438
89 40 HW 4/25/2013 COMPAL current LED resistor for LED EA measure change to 2.2K to 150ohm, R436 change from 2.2K to 220ohm and R429 A00
change from 620 to 220ohm
90 10 HW 5/14/2013 COMPAL HDD Free Fall Sensor add R494 & R495 A00
91 15 16 HW 5/16/2013 COMPAL add ESD solution Pop CC57, depop CC71 , CC72 A00
91 12 HW 5/16/2013 COMPAL reserve for support non vpro pop option pin Follow Goliad12, Pop RC290 & change RC292 from 10K to 100ohm. A00
A X02 A
LA-9591P
5 4 3 2 1

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A B C D E

PCB NO : LA-9591P (DAA00005W10)

XDP@ : XDP Component

Goliad 14 Block Diagram

USB DOCKED DOCK _USB2.0[0] USB3.0/2.0+PS

Intel Clarkville WLAN+BT/ Full Mini Card Near Field PAGE 20

PI3L720 Touch Screen

KB and TP CONN SW & LED PAGE 40

+5V_ALW +3.3V_SUS +5V_RUN +3.3V_M +3.3V_M SATA 1 HDD

USB PORT# DESTINATION

State 0 JUSB1 // E-Dock 1

+VCC_CORE +1.35V_MEM +5V_RUN +3.3V_RUN

+3.3V_M +3.3V_WLAN +3.3V_LAN +LCDVDD

FLASH DESCRIPTOR SECURITY OVERRIDE

LOW = ENABLE (DEFAULT)

+1.05V_M_JTAG 2 1 PCH_JTAG_TDI SATA Impedance Compensation

Reserve for EMI

LPC_LAD0 AU14 AN2 PCH_SMB_ALERT#

PCH_SPI_DO 2@ R11 1 2 33_0402_5% TAA_DO64 1 2

SPI_CLK32 SPI_CLK64 CC7

C43 A25 XTAL24_IN CC6

C42 B25 XTAL24_OUT 2 1

B41 RSVD M21

D UC1C HASWELL_MCP_E UC1D HASWELL_MCP_E D

@ RC72 1 2 0_0402_5% +RTC_CELL

SYSTEM POWER MANAGEMENT

BPM#1 H61 XDP_OBS2_R PAD~D T122 @ 51_0402_1%

DDR3 COMPENSATION SIGNALS H_CPUPWRGD

200_0402_1% 2 1 RC125 SM_RCOMP0

100_0402_1% 2 1 RC133 SM_RCOMP2

Compal Electronics, Inc.

DDI1_LANE_N0 C54 C45 EDP_CPU_LANE_N0

1 2 ENVDD_PCH UC1I HASWELL_MCP_E RP3

PCIE_PRX_MMITX_N5 F10 AN8 USBP0-

+3.3V_RUN +3.3V_RUN I2C1_SCL_TCH_PAD <38>

+3.3V_ALW_PCH +3.3V_RUN 10K_8P4R_5%

CFG STRAPS for CPU

DC_TEST_AY2_AW2 AY2 A3 DC_TEST_A3_B3

Package Daisy Chain:

@ T66 PAD~D L59 C36

@ RC246 1 2 0_0402_5% VR_EN F60 F52

@ RC247 1 2 0_0402_5% VR_READY C59 F56

P62 PWR_DEBUG VCC G29

@ T81 AA59 G45

@ T83 AC59 G49

RSVD VCC G57

CAD Note: RC250 SHOULD BE PLACED CLOSE TO CPU

ESD test request

CC35,CC38, CC39 place near AG10

AE20 RSVD AC20 +3.3V_ALW

CC66 place near AH13

UC1N HASWELL_MCP_E UC1O HASWELL_MCP_E

A11 AJ35 AP22 AV59

DDR_A_MA8 89 VDD5 VDD6 90 DDR_A_MA6

151 152 DDR_A_DQS#2 1 3 1 2 M_ODT0

153 154 DDR_A_DQS2 R29 66.5_0402_1%

DDR_B_MA3 95 96 DDR_B_MA2 RC126 2_0402_1%

DDR_B_D33 165 166 DDR_B_D32

DDR_B_DQS#4 169 170

DDR_B_D35 175 VSS44 DQ54 176 DDR_B_D38

C24 2 1 VMM_GPIO9 VMM_SPI_CS# A4 H14

J2 2 1 BLUE_DOCK B14 M6 VMM2310_TX2N3

J5 150_0402_1% R351 B13 L6