Synchronization Techniques for a Frequency-Hoppe

Wireless Transceiver
Jonathan Min* and Henry Samuel?

* Broadcom Corporation + Electrical Engineering Department

Irvine. CA 92718 University of California, Los Angeles
Los Angeles, CA 90095

Abstract - The implementation of robust synchronization

algorithms and architectures for master-slave configured fre-
quency-hopped radios with frequency-shifted keying (FSK)
modulation is described. The synchronization scheme, both
acquisition and tracking, is based on a simple time division
duplexing (TDD) frame structure, which consists of a pilot
tone, a frame ID (Word Sync), and actual data. The acquisition
process is accomplished by means of frame synchronization,
based on coarse energy detection of the received signal and
the pattern matching of a 21-digit Barker code. The proposed
scheme for synchronous-access frequency-hopped transceiv-
ers is much simpler than a parallel search method based on
parallel matched filters, and relatively faster compared to a PN
acquisition scheme based on serial search. Although FSK sig-
nals are detected noncoherently, a frequency lracking loop is
required to compensate for the carrier frequency offset
between the transmitter and receiver. The receiver also needs
a time tracking loop to recover the clock from the received
data. Both loops use a digital phase-locked loop architecture Fig. 1 FH/SS transceiver architecture
with programmable loop bandwidths.
limiting, and multiplierless correlation FSK demodulation.
Dual antenna diversity is incorporated into the transceiver
I. INTRODUCTION
design for robust transmission over fading channels. A direct-
Spread spectrum techniques, both frequency hopping (FH) conversion architecture from RF to baseband eliminates IF
and direct sequence (DS), have been gaining much attention components and discrete surface acoustic wave (SAW) filters,
for digital wireless communications, owing to their inherent thereby making high levels of integration possible. This
immunity to multipath interference and multiple access capa- enables low powier dissipation, smalller size, and low cost to
bility. PN acquisition is one of the key issues for spread-spec- be achieved for portable wireless transceivers. Both hop and
trum receivers. A PN serial correlation method, though it is FSK tone frequencies are easily generated using a direct digi-
simple to implement, takes a relatively long time to acquire. tal frequency synthesizer (DDFS). Since FSK signalling only
To speed up the acquisition time, a parallel correlation scheme involves the frequency information, not amplitude or phase, a
where a bank of correlators are employed to sum up the corre- hard-limiter capable of more than 80 dB of dynamic range
lation energy for different hop frequencies (for an FH system) replaces an expensive (in power and hardware complexity)
or PN codes (for a DS system) could be used [l]. This archi- AGC loop. An all-digital quadrature FSK demodulator using
tecture, however, is too complex to implemenl. for low-power an oversampled one-bit correlation scheme has been designed
receivers. Alternatively, a simple and yet fast acquisition for use in our frequency-hopped direct-conversion receiver.
scheme for synchronous-access FH transceiviers is proposed Due to odd harmonics produced by hard-limiting the sine
here. waves, our approach limits the modulation scheme to binary
The synchronization blocks described here are key building FSK for real signal detection and to quaternary FSK for com-
blocks for implementing a robust frequency-hopped spread- plex signal detection [3].
spectrum (FH/SS) transceiver for 902-928 R4Hz ISM band The worst-casle accuracy of a crystal oscillator without
applications with data rates up to 160kbh [2].The low-power complicated compensation techniques is typically +50 ppm
transceiver (Fig. 1) employs architectural techniques, such as (parts per million). With open-loop direct conversion from a
dual antenna diversity, direct conversion, direct digital fre- 915 MHz RF to baseband, the carrier frequency error could
quency synthesis, single sideband (SSB) modulation, hard- amount to +lo0 EcHz (including the transmitter error as well).

0-7803-3157-5/96$5.00 0 1996 IEEE 183

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The receiver therefore requires a means to compensate for this Poy*r-up SIB =Signal Indicator Bn from RSSI

substantial frequency offset. In fact, this frequency offset

problem is one of the serious challenges for implementing
robust receivers for DECT or CT2. Since an analog FM detec-
tor is typically used to demodulate Gaussian FSK signals, the
frequency error directly translates into a threshold voltage
shift for the demodulated output for these receivers. There- I (C2) I
fore, a complicated DC averaging scheme must be employed
Fig. 3 Frame synchronization control flow
to handle this problem. Since DECT and CT2 utilize TDD as a
duplexing scheme, the DC feedback loop gets more complex
tion, a total frame length of 20 ms, 10 ms each for the transmit
to deal with the charge leakage occurring during inactive time
subframe and the receive subframe, is chosen. The combina-
slots. For our frequency-hopped FSK transceivers, however,
tion of CO, C1 and D slots compose 20% of the total frame
frequency-offset compensation is done directly on the fre-
slots. Thus, an 80% channel utilization can be achieved.
quency-modulated signals using a very stable, digital phased-
locked loop.
111. ACQUISITION
11. FRAME STRUCTURE Acquisition in time, frequency, and hopping code is accom-
plished by means of frame synchronization. The control flow
A simple frame structure with time-division duplexing
of this process is shown in Fig. 3. It is achieved in two steps:
(TDD) has been developed for transmitter and receiver syn-
coarse acquisition (energy detection) and fine acquisition (pat-
chronization, as shown in Fig. 2 . The frame structure consists
tern matching of the frame ID).
of a pilot tone (CO), a frame ID (Cl), and actual data (C2).
The CO and C1 fields are for control slots and used in the A. Coarse Acquisition
acquisition process: CO for energy detection and C1 for pat-
A purely digital Receiver Signal Strength Indicator (RSSI)
tern matching (Word Sync). Their carrier frequency can be
detection scheme using both energy detection and relative
either fixed to a predefined acquisition frequency or hopped to
slope detection cannot be utilized since the hard-limiter elimi-
a limited number of known frequencies. The acquisition time
nates absolute energy detection capability in the digital
is shorter if the acquisition frequency is fixed since there is no
domain. Moreover, the required, digital matched filter has a
need for sequential search. However, if the preassigned acqui-
sinc-shaped frequency spectrum associated with it. If the fre-
sition frequency receives interference or jamming for some
quency offset pushes the tone frequency to the null locations,
unexpected reasons, a set of frequencies (even two) would be
this scheme has no way of distinguishing the pilot tone.
helpful to initiate a robust acquisition link. The carrier will of
Therefore, the analog RSSI-aided energy detection scheme is
course be hopping during the C2 slots, where time and fre-
used instead. In this scheme, the RSSI output, which is gener-
quency are tracked. Although the baseline modulation scheme
ated by a cascade of logarithmic amplifiers after the channel-
is quaternary FSK, only binary tones will be sent during the
select filter, is used to coarsely indicate whether the CO pilot
control slots (CO and C l ) to make acquisition easier. A dead
tone is present or not. The slave handset first listens for the
zone (D) is inserted between the transmit and receive frames
pilot tone of the frame (CO) which is broadcast by the master
to account for the processing delay of the transceiver and the
on a pre-assigned acquisition carrier frequency. The RSSI out-
average propagation delay of the radio channel.
put is then compared to a programmable energy threshold
A typical frame length proposed for digital wireless sys- value to produce either high or low output (Fig. 4). This Sig-
tems ranges from 2 ms to 20 ms. The choice of the frame nal Indicator Bit (SIB) indicates whether a signal is present at
length trades off the overall link delay with the channel effi- a particular acquisition frequency or not. The energy threshold
ciency, which is defined as the ratio of control slots to the total
voltage is generated by an 8-bit digitally controlled sigma-
number of frame slots. The shorter the frame, the shorter the
delta digital-to-analog converter (DAC). In theory, the thresh-
link delay becomes. However, this implies a lower channel
old value can just be slightly above the noise level, since there
bandwidth efficiency since control signal overhead is required is another level of security checked by the pattern matching
for acquisition and other functions. Since an overall transmis- logic. However, it should be set sufficiently high enough to
sion delay of 20-40 ms is acceptable for voice communica-
optimize the total acquisition time by reducing the probability
of false alarms.
Master
Once the SIB goes high, frequency acquisition takes place
by sweeping the frequency of the DDFS with a step size of
FtonJ4 (20 kHz). The frequency sweeping is required since
Slave
the worst possible frequency error (5100 kHz) may be more
than what the frequency tracking loop can handle. The 5-bit
Fig. 2 TDD frame structure correlation value of a pre-determined tone (+Ft,n,) is evalu-

184
 Limiter
1-bit FSK
LPF

8-bit
Control

Z-A DAG

Fig. 4 Signal Indicator Bit (SIB) generator

ated to indicate a coarse frequency lock. After coarse fre-

quency acquisition, the rest of the CO slots are used to detect a
-0.15 -0.4
signal transition from +Ftone to -F,,,,. The timing acquired
during the CO slots still has a fTbuud uncertainty associated Fig. 6 Pattern matching simulation
with it since bit synchronization has not been yet achieved.
Therefore, the received data needs to be matched with the this threshold wa,s able to discriminate the pattern from noise.
unique ID pattern before frame synchronization is declared. The peak value was 17 while the next highest value near the
Once frame sync is declared, the receiver starts demodulating symbol digit (witlhin f 4 symbol durations) was only 3 with the
data. The hopping code synchronization relies on the fact that following conditions: timing phase error (Terr)= TbaudJ4 and
once the frame is synchronized, a pre-defined frequency hop- frequency error (Fer,.) = Fbuud/8 (10 kHz). Alternatively, a
ping pattern is repeated every frame. Thus, nlo extra pseudo- threshold of 18 can be used if a tighter acquisition condition
noise (PN) code acquisition is required as in a DS system. (for example, Terr= Tbuud/8and Fer,. = FtOne/16)is required.
B. C l Pattern Recognizer Since a coarse acquisition is achieved by detecting the signal
transition at a pre-defined location in the CO field, the pattern
Pattern matching of the C1 code is required for group syn-
matching process can be enabled only over a certain window
chronization (or frame synchronization). A 21-digit binary
period, for example plus or minus four baud cycles around the
Barker code [4] is used for this purpose. The Barker code is
expected time instant. This makes the fine acquisition process
somewhat similar to the M-sequence code, often used as a
more robust and a 21-digit pattern sufficient for our purpose.
spreading code in DS systems. The number of positive one's
and negative one's only differs by one. The autocorrelation C. Reacquisition
value peaks when the reference and received codes align; oth-
A reacquisition process is requiredl when the receiver loses
erwise, its value is quite small. Rather than having 21 inde-
its lock temporarily due to long time-selective fading such as
pendent digits, the pattern consists of three subsets of a seven-
ducting or tunnelling. After the SIB goes high for a while, a
digit code { 1 1 1 -1 -1 1 -1}: the first two sets have a positive
signal transition is detected, indicating a coarse acquisition.
polarity and the third one has a negative polarity. This way,
This enables the receive frame counter, which in turn gener-
the number of fan-ins to the summing adder can be substan-
ates a pattern-match window at the proper time. The frame
tially reduced. The maximum correlation value is +21; there-
resets itself and generates a pulse wlhere it thinks the pattern
fore, a 5-bit programmable threshold value is sufficient. The
match should occur. The pattern match signal detected by the
block diagram of the C1 pattern recognin,eris shown in Fig. 5.
C 1 recognizer, though, overrides the one generated by the
Simulation results have shown that a threshold of 16, which
frame counter, resetting the frame counter. If no match is
allows two random errors in the pattern, is a reasonable choice
detected over the windowed period by the pattern recognizer,
to declare a pattern match (Fig. 6). Even with 15 dB of SNR,
the synchronization circuit generates a miss. If more than five
consecutive misses are reported, the receiver goes through a
reacquisition process and the entire synchronization process
1 starts over.

IV. TRACKING

The acquisition process only guarantees the accuracy of the

(+21, -21)
p Paltern March
baud clock and carrier frequency to within a reasonable range
of error. It is thus up to the time and frequency tracking loops
to pull in the remaining errors and maintain lock. A tracking
loop requires plhase-locked loop (PLL) techniques whose
Fig. 5 C1 pattern recognizer implementation can be completely analog, digital, or a combi-

185
 FSK Demodulator
Fig. 7 Baseband receiver with tracking loops
nation of both. Since a DDFS is used for hopping carrier gen-
eration and the baud clock frequency is relatively low (80
kHz) in the FWSS transceiver, both the time and frequency
tracking loops have adopted a fully digital-PLL architecture
(Fig. 7). Since our system is slow frequency-hopped, the hop
rate is lower than the symbol rate, thus allowing the use of an
open-loop hop time synchronization scheme in which the hop
time is aligned with the symbol time plus a programmable
delay to compensate for the delay between the two loops. The
delay should account for the average group delay of the low-
pass filter plus the pipeline delay of the DDFSDAC combina-
tion.
A. Time Tracking Loop
The time tracking loop (TTL) consists of a phase detector
(PD), a loop filter, and an numerically-controlled oscillator
(NCO). An early-late phase detection scheme is used to gener-
ate a phase discriminant. The correlation energy of the first-
half symbol minus that of the second-half symbol is detected
for each tone and the output from one of the four tones, cho-
sen by the hard decision bits, is fed into the loop filter. For the
PD output, four-bit quantization with the rounding scheme is
chosen over one-bit hard decisions since soft decisions reduce
the phase jitter for the same set of coefficients when a stable
condition is reached. Both filter coefficients KO and K1 have
programmable powers-of-two coefficients so that the loop can
handle various tracking ranges depending on the required
clock jitter of the overall system. The loop architecture is sim-
plified by replacing an expensive digital multiplier with an
add-and-shift operator and limiting the number of coefficient
choices to only eight. The set of coefficients was carefully
chosen by simulation. When the data is not changing, the out-
put of the PD should be theoretically zero. The loop is thus
enabled only when symbol transitions occur during the C2
slots of the receive frame. For the case where only one
antenna branch is active, an autoscaler for the PD is used to
guarantee the same loop gain as in the dual antenna case. A
24-bit internal wordlength is chosen for the loop filter. The
NCO logic thus uses a 24-bit accumulator, which results in a
0.5 Hz tuning resolution at a 7.15 MHz demodulator clock
rate.
186
1.01 /1
Time-Error Phase Discriminant =
f
(@ Data Transitions only) -1.o
-0.5
Time Error (w.r.t. Tbaud)
(a) Detection algorithm (b) S-curve
Fig. 8 Phase error detection of TTL.
An “S-curve” is used to measure the quality of the PD algo-
rithm. Our FSK demodulator uses only one-bit signal correla-
tion, and the magnitude calculation is performed by
summation of two absolute values [5]. Due to these simplifi-
cations, the PD S-curve deviates from the ideal case. Unlike
its ideal counterpart, the shape of the S-curve varies depend-
ing on the carrier phase offset. One-bit approximation results
in a flat region in the middle of the S-curve, while the abso-
lute-value magnitude calculation results in a dead zone at the
edges of the curve. However, when the PD output is averaged
over different carrier phases, simulation results have shown
that the shape of our S-curve closely resembles that of the
ideal one (Fig. 8). Due to an inherent frequency offset
between the transmit and receive carriers, the loop tends to
rotate around all carrier phases until it locks. Furthermore, the
channel-select lowpass filter averages out different phases.
Therefore, this carrier phase-averaged scheme is acceptable
for our receiver.
B. Frequency Tracking Loop
A second-order PLL is typically employed in a receiver
where both phase and small frequency offset errors need to be
corrected. The Costas loops used in phase- or amplitude-mod-
ulation receivers are one such example. However, the total
frequency offset that can be corrected is limited by the delays
in the loop. When the frequency offset is relatively large, as in
this FH system, a frequency-locked loop ( E L ) is required
rather than a PLL. The digital FLL consists of a frequency
detector (FD), a loop filter, and a DDFS (Fig. 7). The maxi-
mum frequency error it can correct is now limited by the S-
curve characteristics of the frequency detector, typically up to
half of the symbol rate. The DDFS in this case just maps the
input frequency to the output frequency with a linear gain KO.
Since the VCO is no longer an integrator, a loop filter with
only the integrator term ( K l ) is required to average out the
instantaneous frequency errors. The overall loop is thus first-
order.
The difference between the two correlation energies at fre-
quency nulls of the +Ftflneand -F,,,, data can be used as the
FD output; however, this provides a lower overall loop gain.
Thus, it is not selected. Instead, the difference between the
two correlation energies at +FtOne/2and -F,,J2 is used as the
baseline frequency discriminator (Fig. 9(a)). When a signal
with either +Fro,, or -Ftfl,, is received, its correlation value is
 WB= { KO = 2-l0
K1 = 2-18
(Acquisition)

Freauencv-Error Discriminant =
2 0.0
5
NB= { K0=2-”
K1 = 2-*‘
4

(@ Data Transitions between t F t 8 -Ft) Freq Error (w.r.t ),,F

,, (Track)
-1.0
0.0
(a) Detection algorithm (b) S-curve No. of Baud

Fig. 9 Frequency error detection of FTL (a) TTL loop filter output trajectory

stored and compared with the other correlatioln value. The 4-

W E = KI =2-15 0.5
bit FD output is then fed into the loop filter only when a tran- (Acquisition) I3
sition from +Ftoneto -Fto,, or vice versa occurs. This scheme Q

simplifies the frequency error detection block significantly NE= K1 = y 2 1 a O’O

and thus justifies its usage in our FTL. The loop filter has a
24-bit internal wordlength. The input frequency control word
of the DDFS has been chosen to be 24 bits wide as well.
Although the simulation shows a 20-bit implementation
would have been sufficient, this choice fully utilizes the preci-
sion of the loop filter output and guarantees a 5 Hz frequency
tuning capability at a DDFS clock rate of 76 MHz.
Due to hardware simplifications for the FSK detector, the
FD S-curve results also depend on the carrier phase offset.
Again, the phase-averaged scheme shows acceptable charac-
teristics (Fig. 9(b)). Statistically speaking, the loop is acti-
vated only in one out of eight clocks due to thle data transition
restriction in our FD scheme, thus slowing down the fre-
quency tracking process. To speed up the tracking process, the
difference between two correlation values at +3Ft0,,12 and
-3Ft0,J2 can also be used; however, this scheme requires
more complex circuits, especially since the 3Ft0,$2 tone can-
not be generated by simple binary division from the 2Ft,,,
reference tone. Thus, it is not utilized.
C. Loop Simulation Example
Fig. 10(a) shows an example of I T L simulations. The loop
filter output trajectory is shown as the number of baud inter-
vals increases for a worst case condition with a phase error of
180 degrees and a clock frequency error of 250 Hz (-3000
ppm with respect to Fsym = 80 kHz). Two different sets of
coefficients are used for acquisition: an initial wide loop band-
width and a narrow loop bandwidth for final tracking. A
steady-state condition (or lock) is accomplished in about 500
baud cycles and the loop is switched to a tracking mode at
about the 1600th baud cycle. Fig. lO(b) shows a simulation
example with a frequency error of 20 kIIz (FtO,J4). Acquisi-
tion is achieved in about 1000 baud cycles.
V. CONCLUSIONS
In this paper, we have described the synchronization algo-
rithms and architectures of a low-power frequency-hopped
transceiver. The proposed wake-up tone scheme for a syn-
chronous frequency-hopped system is much simpler and
(Track) 4
-0.5
t
-1.01
0.0 1000.0 2000.0 40.0
No. of Baud
(b) FTL loop filter output trajectory
Fig. 10 Loop simulation
faster than the, serial PN correlation search process typically
employed in a direct-sequence (DS) system. Two levels of
detection, coarse energy detection of the RSSI signal and pat-
tern matching of the frame ID, enhances the robustness of the
acquisition process. Tracking of the carrier frequency and
hoplsymbol timing phase is maintained by a stable digital
phase-locked loop with programmable powers-of-two coeffi-
cients to handle various loop bandwidths. The proposed syn-
chronization techniques are well-suited for low-power
portable wireless systems based on frequency-hopped spread
spectrum transceiivers.
REFERENCES
S.S. Rappaport and D.M. Grieco, “Spread-Spectrum Signal
Acquisition: Method and Technology,” IEEE Communications
Magazine, pp. 6-21, Jun. 1984.
J. Min, A. Rofougaran, V. Lin, M. Jensen, H. Samueli, A.A.
Abidi, G. Pottie, and Y. Rahmat-Samii, “A Low-Power Hand-
held Frequercy-Hopped Spread Spectrum Transceiver Hard-
ware Architecture,” in Wireless Personal Communications:
Trends and Challenges (T.S. Rappaport, B.D. Werner, and J.H.
Reed, Eds.), pp. 119-126, Kluwer Academic Publishers, 1994.
J. Min, H-C. Liu, A. Rofougaran, S . Khorram, H. Samueli, and
A.A. Abidi, “Low Power Correlation Detector for Binary FSK
Direct-Conversion Receivers,”Electronics Letters, vol. 3 1 , pp.
1030-1032,Jun. 22,1995.
R.H. Barker., “Group Synchronizing of Binary Digital Sys-
tems,” in Communication Theory. ]London:Butterworth, 1953,
pp. 273-287.
H-C. Liu, J. Min, and H. Samueli, “A Low-Power Baseband
Receiver IC for Frequency-Hopped Spread Spectrum Applica-
tions,” Proceedings of IEEE Custom Integrated Circuits Con-
ference, pp. 311-314, Santa Clara, CA, May 1995.

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