Bluespec Compiler, Bluesim, emVM,

and Development Workstation

Release Notes

Version 2011.06

2011.06 Release Highlights

The 2011.06 release introduces emVMTM, which provides host-based virtual emulation capabilities,
including visibility, debug and co-emulation, in conjunction with multiple supported FPGA emulation
boards. As part of emVM, extensive enhancements were made to SCE-MI-based system
implementation. New packages have been added to the AzureIP libraries along with enhancements to
existing library packages. Scheduling annotations for wires have changed; the previous scheduling
annotations are still provided as the “Unsafe” versions. Usability enhancements, including source-level
debug in conjunction with supported waveform viewers, are included for the workstation. The release
includes three new documents: BSV by Example and an emVM tutorial, both distributed with
executable source code examples and the emVM user manual which includes material previously
provided in the SCE-MI manual.
Documentation references are provided in parentheses. The following documents are referenced:
Reference Guide: rg
User Guide: ug
emVM Manual: em
Know Problems and Solutions: kpns

Prelude Enhancements
Note: Due to improved provisos support, designs which in previous releases compiled with
provisos warnings may generate errors, requiring code modifications to compile
• Scheduling annotations for Wires have changed. The previous scheduling annotations are now
implemented by the new “Unsafe” versions of wires (rg B.4.2, B.4.3, B.4.4, B.4.5, B.4.6)
• Changed RWire scheduling constraints: wset SBR wget (rg B.4.2)
• Added SizedLiteral typeclass (rg B.1.5)
• Added msb, lsb functions to BitWise typeclass with instances added for Bit, UInt, Int, and
FixedPoint (rg B.1.9)
• Added Saturating Arith typeclass with instances for Int, UInt, FixedPoint (rg B1.12)
• Added Alias, NumAlias typeclasses (rg B.1.13)
• Added Void data type (rg B.2.9)
• Added TMax, TMin, Min (rg B.3.2)
 • Fixed internal errors around use of TAdd, TMul, SizeOf (rg B.3.2 and B.3.3)
• Improved provisos support
◦ fewer provisos are required by compiler
◦ messages around provisos have been improved
◦ designs which compiled with warnings may generate errors, requiring code modifications to
compile
• Added pulseWireToReadOnly and readReadOnly functions (rg B.4.7)
• Added WriteOnly interface (rg B.4.8)
• Added curry and uncurry functions to Prelude package (rg B.5.3)

Compiler
• Changed unknown size warnings to errors. Designs compiled with the previous general release
(2009.10.B) may generate errors and not compile, instead of warnings from the previous
release. These type errors should be fixed to ensure a correct design.
• Added bsenv environment utility (ug 4.3.2)
• Replaced c++family with bsenv c++_family (ug 4.3.2)

AzureIP Library
• Added ToGet and ToPut instances for AlignedFIFO (rg C.2.8)
• Added Vector package functions find, and, or, toChunks (rg C.3.4, C.3.13)
• Added FixedPoint truncate with round and saturate functions (rg C.5.3)
• Added NumberTypes package (rg C.5.5)
• StmtFSM updates (rg C.6.1)
◦ Predicates now being checked on first clock cycle for start method
◦ Quicker compile times for large FSMs
◦ Reduced scheduling warnings
• Added instance of ToGet#(ActionValue#(a) , a) to GetPut package (rg C .7.1)
• Added CRC package (rg C.8.16)
• Changes to SyncHandshake.v (rg C.9.5)
◦ mkSyncHandshake modules changed to reduce latency. Pulses on the destination side will
occur with a minimum separation of 1 cycle. In the previous implementation the minimum
separation was 2 cycles.
◦ Methods are not ready in reset.
◦ Impacts mkSyncReg and mkSyncLevelFIFO as well.
 • Changes to SyncFIFO and SyncFIFOLevel (rg C.9.7)
◦ Added output register to improve timing for synthesis. Latency remains the same.
◦ Modules mkSyncFIFOFull, mkSyncFIFOFromCCFull, mkSyncFIFOToCCFull have been
deprecated
◦ Added mkSyncFIFO1 module (single-element FIFO)
• Added Clocks package module mkNullCrossingReg (rg C.9.9)
• Added the following Collections packages:
◦ ModuleContext (rg C.10.1)
◦ HList (rg C.10.4)
◦ UnitAppendList (rg C.10.5)
• TLM package changes (rg C.11.1)
◦ TLM2 has been added and is the recommended package for TLM implementation.
◦ Timing for synthesis when using the mkTLMRam module has been improved. The request
is now registered within the module, removing the combinational path between the request
and the response. Latency is now one cycle. The schedule of existing designs using the
mkTLMRam module will be different than with previous releases. To maintain the old
schedule, use the mkTLMRam_unbuffered module.
• Updated AHB, Axi packages (rg C.12.1, C.12.2)
◦ AXI has been replaced with Axi
• Synthesis constraints
◦ Synthesis directives (// synopsis template) have been removed from provided Verilog files to
remove warnings generated during FPGA synthesis. The directives are no longer supported
by the ASIC tools that once required them.
◦ Xilinx tool constraints have been moved from the board support area to the
lib/Verilog/Bluespec.xcf.. The build utility pulls in this constraint file depending on the
target flow and tools. (em C)

Workstation
• Added search capability to module browser, keeps list of searched words (ug 5.3)
• Enhanced control of workstation module hierarchy (ug 5.3)
• Improved startup - removed use of EDITOR global variable
• Improved support for waveform viewers (ug 5.3.2)
◦ allow viewers and bsc to run on different machines, via a common directory specified by
BLUESPECTMP environment
◦ improved reporting of communications problems between viewer and bsc
◦ Support attaching to gtk viewers
emVM
First release of emVM, which provides host-based virtual emulation capabilities, including visibility,
debug and co-emulation, in conjunction with multiple supported FPGA emulation boards. This release
includes major enhancements and updates to the Bluespec implementation of the SCE-MI standard.
Designs utilizing SCE-MI which were compiled with the last general release (2009.10.B) may require
modifications to compile. EmVM is a separately licensed product which includes the following new
features:

• Third-party FPGA emulation board support, including:

◦ Dini 7002
◦ Xilinx ML605
• HDL Editor and Probe Insertion Tool (em 7)
• build utility to simplify build process for simulation and emulation environments - requires
python 2.4 or later (em C)
• Extensive standard and licensable library of hardware-side transactors (em 3.3.3)
• Extensive library of software-side C++ components (em A.9)
• Support for a testbench GUI interface (em 5)
• Tcl/Tk script to generate C++ definitions for BSV data types (generateSceMiHeaders.tcl) (em B
4.2)
SCE-MI implementation updates:
• Major changes to the implementation of SCE-MI clocking (em A.6). Designs compiled with
the last general release (2009.10.B) using clocks will require modifications to compile.

Documentation
Design advisory issued when targeting Block RAMS on Virtex devices (kpns #034)
The following new documents are in this release:
• BSV by Example
• emVM tutorial
• emVM manual – includes previous SCE-MI manual
• PAClib example and whitepaper
Corrections and updates have been made in all manuals
Licensing
The following Bluespec components are licensed independently:
• Bluespec compiler (bsc)
• Bluespec Development Workstation (BDW) (can use a bsc or BDW license to run the
workstation)
• Bluesim
• emVM
• AMBA AHB/AXI Libraries
◦ Requires a separate software license to use. Please contact sales.
• PAClib
◦ Requires a separate software license to use. Please contact sales for the package and
license.