Bluespec Compiler, Bluesim,

and Development Workstation

Release Notes
Version 2017.07

2017.07 Release Highlights

The 2017.07 release provides product fixes, performance improvements, and enhancements
throughout the product set. BlueNoC support has been added for new boards, with library
updates to support PCIe Gen3 and Xilinx Ultrascale FPGAs.

BlueNoC
• Support for new boards (VC709, VCU108, DNVUF4A, KLVUF4A)

• Added a Vivado script for programming 7-Series Xilinx boards (KC705, VC707, VC709)

• Updated DDR3 controller and Zynq FPGA image for B2000T

• Updated DDR3 constraints for VC707

• BlueNoC driver updated for Linux 4.7

◦ These changes are likely to be incompatible with older versions of Linux, and
certainly incompatible with very old versions

• Updates to both the BlueNoC client program and BlueNoC hotswap script to better
report errors

• Added attributes to the PCIe endpoints for KC705 and VC707 to address Vivado
synthesis issues (Xilinx AR# 62296)

AzureIP Library
• New libraries for Xilinx PCIe Gen3 IP for 7-Series and Ultrascale

• New libraries for Xilinx Ultrascale clock generators and clock buffers

• Improved libraries for Xilinx 7-Series clock generators, to avoid Vivado warnings about
unconnected ports
 • Fixes to the AHB library

• Improvements to the I2C module, to provide stricter support for the protocol (as
required by the OV7670 camera module, for example)

• Fixes to the extend functions in BUtils to work for size zero

• Fixes to the FloatingPoint Math library

• Improvements to the Divide and SquareRoot Math libraries

◦ Simplified the mkDivider and mkSquareRooter module with functions from BUtils

◦ Added mkNonPipelinedDivider and mkNonPipelinedSquareRooter modules

Prelude Enhancements
• Updates to the CReg family of modules, to support clocking by gated clocks

• Fixes to mkSyncFIFO, mkSyncFIFOLevel, mkSyncFIFOCount, and mkGSyncFIFOCount

to support zero-width data

o Added zero-width variants for the underlying SyncFIFO, SyncFIFO1, and

SyncFIFOLevel Verilog modules

Compiler
• Many efficiency improvements, error message improvements, and bug fixes

• Fixes to the parsing of import-BVI blocks to allow multiple unnamed clocks and resets
and to improve error messages

• Support for typeclass instances that make recursive use of themselves

• Improvements to scheduling analysis of methods within a rule

• Fixes to the analysis of don't-care values, to treat them as any possible variable, where
previously a specific value was chosen. Relying on that choice could hide formal
problems with the specification.

Development Workstation
• Fixes to the import-BVI wizard, to not fail when parsing Verilog files in some cases
Bluesim
• Support for compiling Bluesim models into standalone executable binaries that do not
require Bluetcl to run – a template in the 'util' directory

Build Utility
• Support for Vivado out-of-context (OOC) synthesis, with a new 'xilinx-ooc-synthesis'
directive

• Support for preserving signals in Vivado synthesis – to allow more signals to be visible
when debugging with ChipScope, for example – with a new 'xilinx-preserve-signals'
directive

• Fixes so that Verilog directories and imported files can be specified with relative paths

• Fixes to the stage which prepares the Vivado batch script, to properly find all the
imported packages

• Fixes to the stage which prepares the ISE batch script, to not fail due to unrecognized
flags

SceMi
• Fixes to the SceMi BSV inpipe proxies, to start a SceMi service loop

• Fixes to the SceMi BSV proxies, to fix a bug which occasionally resulted in a segfault
when a pipe is used

• Separated the Readback C++ library from the SceMi library, so that it may be used
without SceMi