Compal LA-4732P Montevina UMA 2009.02.16 Rev1.0 PDF

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Compal confidential

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Schematics Document

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Mobile Penryn uFCPGA with Intel
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Cantiga_GM+ICH9-M core logic
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2009-02-16
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REV:1.0

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Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/08/28 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Montevina UMA 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 18, 2009 Sheet 1 of 46
A B C D E
A B C D E

Compal confidential Montevina Consumer UMA


CK505 72QFN
Clock Generator
Thermal Sensor Mobile Penryn
1 SLG8SP553V 1

EMC1402 uFCPGA-478 CPU P17


P06

P6, 7, 8

Fan conn P06 H_A#(3..35)


FSB
H_D#(0..63) 667/800/1066 MHz 1.05V

LVDS Panel DDR2 800MHz 1.8V DDR2 SO-DIMM X2


BANK 0, 1, 2, 3 P15, 16
Interface P19
Intel Cantiga MCH

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Dual Channel
CRT

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P18 FCBGA 1329 USB conn x1
GM47 P30
Support V1.3
P9,10, 11, 12, 13, 14
HDMI

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P35
2 BT Conn P30
2

USB2.0 X12
DMI X4 C-Link

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USB Camera
P19

PCI-E BUS*4

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Azalia

Intel ICH9-M SATA Master-1 Finger print


P30

SATA Slave
RTL8103EL Mini-Card Mini-Card mBGA-676 CardReader 5 in1 Slot

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SATA Slave
(10/100M) WLAN WWAN New Card P20,21,22,23
P27 P27

P25 P26 P26 P26


Audio CKT AMP & Audio Jack

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Codec_IDT92HD75B TPA6047
P28 P29

RJ45/11 CONN
// LPC BUS
P25
3 MDC 3
P28
p:

SATA HDD Connector


P24
ENE
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KB926 SATA ODD ConnectorP24


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SPI
P32

Int.KBD e-SATA Connector P30


RTC CKT. LED Touch Pad CONN.
P33 P32
P21 P33

ACCELEROMETER-1 SPI ROM USB Board Conn


SST25VF080P31 USB port x2 P30
ST P24
4 4

K/B backlight Conn Capsense switch Conn


P33
P33

Security Classification Compal Secret Data Compal Electronics, Inc.


2006/02/13 2006/03/10 Title
DC/DC Interface CKT. Issued Date Deciphered Date
Block Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P36 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Montevina UMA 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 18, 2009 Sheet 2 of 46
A B C D E
A

Symbol Note :
Voltage Rails O MEANS ON X MEANS OFF USB assignment:
: means Digital Ground USB-0 Right side(with eSATA)
USB-1 Left side
USB-2 Left side
: means Analog Ground USB-3 Cardreader
power USB-4 Camera
plane USB-5 WLAN
+B +5VALW +1.5V +5VS @ : means just reserve , no build USB-6 Bluetooth
+3VS USB-7 Finger Printer
+3VALW +1.5VS 45@ : means need be mounted when 45 level assy or rework stage. USB-8 MiniCard(WWAN/TV)
+0.75V DEBUG@ : means just reserve for debug. USB-9 Express card
State +VCCP USB-10 X
+CPU_CORE BATT @ : means need be mounted when 45 level assy or rework stage. USB-11 X
+2.5VS CONN@ : means ME part
+1.8V
ESATA @ : means just reserve for ESATA PCIe assignment:

/
GS @ : means just reserve for G sensor PCIe-1 WWAN

/x
S0 O O O O FP @ : means just reserve for Finger Print
PCIe-2 X
PCIe-3 WLAN
S1 O O O O Multi @ : means just reserve for Multi Bay PCIe-4 GLAN (Realtek)

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PCIe-5 X
NewC@ : means just reserve for New card
S3 O O O X PCIe-6 New Card
Main@ : means just reserve for Main stream

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S5 S4/AC O O X X OPP@ : means just reserve for OPP
I2C / SMBUS ADDRESSING
S5 S4/ Battery only O X X X 2MiniC@ : means just reserve for 2nd Mini card slot

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S5 S4/AC & Battery PA @ : means just reserve for PA DEVICE HEX ADDRESS
don't exist X X X X
1

PR @ : means just reserve for PR DDR SO-DIMM 0 A0 10100000 1

DDR SO-DIMM 1 A4 10100100

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CLOCK GENERATOR (EXT.) D2 11010010
SMBUS Control Table

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SERIAL Thermal Cap sensor
SOURCE INVERTER BATT EEPROM Sensor SODIMM CLK CHIP MINI CARD LCD board NEW CARD G sensor
SMB_EC_CK1
X V V X X X X X V X X
//
SMB_EC_DA1
KB926
SMB_EC_CK2
SMB_EC_DA2
KB926 X X X V X X X X X X X
p:

SMB_CK_CLK1
SMB_CK_DAT1
ICH9 X X X X V V V X X V V
X X X X X X X V X X X
tt

LCD_CLK
LCD_DAT
Cantiga
h

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/08/28 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom Montevina UMA 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 18, 2009 Sheet 3 of 46
A
5 4 3 2 1

60mA
+3VAUX_BT

50mA
Finger printer

25mA +3VS_DVDD
1A ALC268
D
+V_BATTERY D

20mA
+3VALW_EC

10mA
SPI ROM
177mA
0.3A ICH9 1A
INVPWR_B+ LVDS CON New card
300mA
LAN 278mA
AC VIN ICH9
1.7A 5.89A 3.39A
+3VALW +3VS

/
1.5A
2A +LCDVDD LVDS CON

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B++ RT5158
250mA
+3VS_CK505

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657mA ICH_VCC1_5
C
1A C

0.3A 2.2A ICH9 Mini card (WLAN)


+1.5VS 1.56A
ICH9

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1A
Mini card (TV tu/WWAN/Robeson)

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0.58A 1.3A 35mA +VDDA
+5VALW +5VS IDT 9275B
B+

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7A 10mA
+5VAMP

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1.8A
ODD
// 700mA
B
SATA B
3.7A
3.7 X 3=11.1V MCH
50mA
p:

DC BATT PC Camera(4.75V)
1.9A 12.11A DDR2 800Mhz 4G x2
B+++ +1.8V
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50mA
+0.9V
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1.17A
ICH9

4.7A 1.26A
1.05V_B+ +VCCP MCH

2.3A
CPU

2A 10mA 34A/1.025V
CPU_B+ +VCC_CORE CPU
A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/08/28 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power delevry
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C Montevina UMA 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 18, 2009 Sheet 4 of 46
5 4 3 2 1
A

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1 1

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h

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/08/28 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom Montevina UMA 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 18, 2009 Sheet 5 of 46
A
5 4 3 2 1

ITP-XDP Connector
+VCCP

XDP_TDI R2 1 2 54.9_0402_1%

XDP_TMS R3 1 2 54.9_0402_1%
D D
XDP_TDO R4 1 2 54.9_0402_1%

XDP_TRST# R7 1 2 54.9_0402_1%
9 H_A#[3..16]
JCPU1A
H_A#3 J4 H1 H_ADS# XDP_TCK R8 1 2 54.9_0402_1%
A[3]# ADS# H_ADS# 9

ADDR GROUP_0
H_A#4 L5 E2 H_BNR#
H_A#5 A[4]# BNR# H_BPRI# H_BNR# 9
L4 A[5]# BPRI# G5 H_BPRI# 9
H_A#6 K5 This shall place near CPU
H_A#7 A[6]# H_DEFER#
M3 A[7]# DEFER# H5 H_DEFER# 9
H_A#8 N2 F21 H_DRDY#
H_A#9 A[8]# DRDY# H_DBSY# H_DRDY# 9
J1 A[9]# DBSY# E1 H_DBSY# 9
H_A#10 N3
H_A#11 A[10]# H_BR0#
P5 A[11]# BR0# F1 H_BR0# 9
H_A#12 P2 A[12]#

CONTROL
H_A#13 L2 D20 H_IERR# T1
H_A#14 A[13]# IERR# H_INIT#
P4 A[14]# INIT# B3 H_INIT# 21
Place TP with a

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H_A#15 P1
H_A#16 A[15]# H_LOCK#
R1 H4
9 H_ADSTB#0
H_ADSTB#0 M1
A[16]# LOCK# H_LOCK# 9 GND 0.1" away
ADSTB[0]# H_RESET#

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RESET# C1 H_RESET# 9
H_REQ#0 K3 F3 H_RS#0
9 H_REQ#0 H_REQ#1 REQ[0]# RS[0]# H_RS#1 H_RS#0 9
9 H_REQ#1 H2 REQ[1]# RS[1]# F4 H_RS#1 9
H_REQ#2 K2 G3 H_RS#2
9 H_REQ#2 H_REQ#3 REQ[2]# RS[2]# H_TRDY# H_RS#2 9
9 H_REQ#3 J3 REQ[3]# TRDY# G2 H_TRDY# 9
H_REQ#4 L1
9 H_REQ#4 REQ[4]#
G6 H_HIT#

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9 H_A#[17..35] H_A#17 HIT# H_HITM# H_HIT# 9
Y2 A[17]# HITM# E4 H_HITM# 9
C H_A#18 C
U5 A[18]#
H_A#19 R3 AD4
A[19]# BPM[0]#
ADDR GROUP_1

H_A#20 W6 AD3
H_A#21 A[20]# BPM[1]#
U4 A[21]# BPM[2]# AD1
H_A#22 Y5 AC4
A[22]# BPM[3]#

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XDP/ITP SIGNALS

H_A#23 U1 AC2
H_A#24 A[23]# PRDY#
R4 A[24]# PREQ# AC1
H_A#25 T5 AC5 XDP_TCK +3VS
H_A#26 A[25]# TCK XDP_TDI
T3 AA6
H_A#27 A[26]# TDI XDP_TDO
W2 AB3
A[27]# TDO

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H_A#28 W5 AB5 XDP_TMS
A[28]# TMS

0.1U_0402_16V4Z
H_A#29 Y4 AB6 XDP_TRST# 1
H_A#30 A[29]# TRST# XDP_DBRESET#
U2 C20 XDP_DBRESET# 22
H_A#31 A[30]# DBR# C2
V4
H_A#32 A[31]# U1
W3
H_A#33 A[32]# 2
AA4
A[33]# THERMAL
H_A#34 AB2 H_PROCHOT# R13 1 2 56_0402_1%
H_A#35 A[34]# +VCCP SMB_EC_CK2
AA3 D21 1 8 SMB_EC_CK2 32
A[35]# PROCHOT# VDD SMCLK

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H_ADSTB#1 V1 A24 H_THERMDA_R R14 1 2 0_0402_5% H_THERMDA
9 H_ADSTB#1 ADSTB[1]# THERMDA H_THERMDC_R H_THERMDC H_THERMDA SMB_EC_DA2
B25 R15 1 2 0_0402_5% 2 7
H_A20M# THERMDC DP SMDATA SMB_EC_DA2 32
A6 C3
21 H_A20M# A20M#
ICH

H_FERR# A5 C7 H_THERMTRIP# 1 2 H_THERMDC 3 6 R6 1 2 10K_0402_5%


21 H_FERR# FERR# THERMTRIP# H_THERMTRIP# 9,21 DN ALERT# +3VS
H_IGNNE# C4 2200P_0402_50V7K
21 H_IGNNE# IGNNE# THERM# 4 5
THERM# GND

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H_STPCLK# D5
21 H_STPCLK# H_INTR STPCLK#
C6 H CLK R16
21 H_INTR H_NMI LINT0 CLK_CPU_BCLK
21 H_NMI B4 A22 CLK_CPU_BCLK 17 +3VS 1 2
H_SMI# LINT1 BCLK[0] CLK_CPU_BCLK# 10K_0402_5%
21 H_SMI# A3 A21 CLK_CPU_BCLK# 17 EMC1402-1-ACZL-TR_MSOP8
SMI# BCLK[1]
Address:100_1100
M4
N5
RSVD[01]
RSVD[02]
//
H_THERMDA, H_THERMDC routing
B
T2
V3
RSVD[03] together, Trace width / Spacing = 10 / 10 B
RSVD[04]
mil
RESERVED

B2
RSVD[05]
D2
RSVD[06]
D22
p:

RSVD[07]
D3
RSVD[08]
F6

Fan Control circuit


RSVD[09]
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SI-1 Change to voltage control circuit


Penryn
+5VS
h

+VCCP
+3VS
1
C4 2.2U_0603_6.3V4Z 1
C5
1

2
@ 0.1U_0402_16V4Z
R17 R1209 U51 2
56_0402_5% 10K_0402_5% 9 1 2 CONN@
Thermal Pad VEN JFAN1
8 2
GND VIN +5VS_FAN
7 3 1
2 2

GND VO FAN_SPEED 1
6 4 1 2 4
GND VSET 2 G1
B

FAN_SPEED 5 C1509 3 5
32 FAN_SPEED GND 3 G2
E

H_PROCHOT# 3 1 OCP# 1 G996RD1U_TDFN8_3X3 2.2U_0603_6.3V4Z ACES_85204-03001


OCP# 22 2 +5VS
C

@ Q1 C1510
MMBT3904_NL_SOT23-3 1000P_0402_50V7K D63
32 FAN_SET 3
2 Vcc
2
+VCCP Line to be protected
1 GND
A A
DLPT05-7-F_SOT23-3
2

R18
56_0402_5%
1

H_IERR# Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/08/28 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Penryn(1/3)-AGTL+/ITP-XDP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Montevina UMA 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 18, 2009 Sheet 6 of 46
5 4 3 2 1
5 4 3 2 1

+VCC_CORE +VCC_CORE
9 H_D#[0..15] H_D#[32..47] 9
JCPU1B JCPU1C
H_D#0 E22 Y22 H_D#32 A7 AB20
H_D#1 D[0]# D[32]# H_D#33 VCC[001] VCC[068]
F24 AB24 A9 AB7
H_D#2 D[1]# D[33]# H_D#34 VCC[002] VCC[069]
E26 V24 A10 AC7
D[2]# D[34]# VCC[003] VCC[070]

DATA GRP 0
H_D#3 G22 V26 H_D#35 A12 AC9

DATA GRP 2
D H_D#4 D[3]# D[35]# H_D#36 VCC[004] VCC[071] D
F23 V23 A13 AC12
H_D#5 D[4]# D[36]# H_D#37 VCC[005] VCC[072]
G25 T22 A15 AC13
H_D#6 D[5]# D[37]# H_D#38 VCC[006] VCC[073]
E25 U25 A17 AC15
H_D#7 D[6]# D[38]# H_D#39 VCC[007] VCC[074]
E23 U23 A18 AC17
H_D#8 D[7]# D[39]# H_D#40 VCC[008] VCC[075]
K24 Y25 A20 AC18
H_D#9 D[8]# D[40]# H_D#41 VCC[009] VCC[076]
G24 W22 B7 AD7
H_D#10 D[9]# D[41]# H_D#42 VCC[010] VCC[077]
J24 Y23 B9 AD9
H_D#11 D[10]# D[42]# H_D#43 VCC[011] VCC[078]
J23 W24 B10 AD10
H_D#12 D[11]# D[43]# H_D#44 VCC[012] VCC[079]
H22 W25 B12 AD12
H_D#13 D[12]# D[44]# H_D#45 VCC[013] VCC[080]
F26 AA23 B14 AD14
H_D#14 D[13]# D[45]# H_D#46 VCC[014] VCC[081]
K22 AA24 B15 AD15
H_D#15 D[14]# D[46]# H_D#47 VCC[015] VCC[082]
H23 D[15]# D[47]# AB25 B17 VCC[016] VCC[083] AD17
H_DSTBN#0 J26 Y26 H_DSTBN#2 B18 AD18
9 H_DSTBN#0 H_DSTBP#0 DSTBN[0]# DSTBN[2]# H_DSTBP#2 H_DSTBN#2 9 VCC[017] VCC[084]
9 H_DSTBP#0 H26 DSTBP[0]# DSTBP[2]# AA26 H_DSTBP#2 9 B20 VCC[018] VCC[085] AE9
H_DINV#0 H25 U22 H_DINV#2 C9 AE10
9 H_DINV#0 DINV[0]# DINV[2]# H_DINV#2 9 VCC[019] VCC[086]
9 H_D#[16..31] H_D#[48..63] 9 C10 VCC[020] VCC[087] AE12
C12 VCC[021] VCC[088] AE13
H_D#16 N22 AE24 H_D#48 C13 AE15
H_D#17 D[16]# D[48]# H_D#49 VCC[022] VCC[089]
K25 D[17]# D[49]# AD24 C15 VCC[023] VCC[090] AE17
H_D#18 P26 AA21 H_D#50 C17 AE18
H_D#19 D[18]# D[50]# H_D#51 VCC[024] VCC[091]
R23 D[19]# D[51]# AB22 C18 VCC[025] VCC[092] AE20

/
H_D#20 L23 AB21 H_D#52 D9 AF9
D[20]# D[52]# VCC[026] VCC[093]

DATA GRP 1
H_D#21 M24 AC26 H_D#53 D10 AF10

DATA GRP 3
H_D#22 D[21]# D[53]# H_D#54 VCC[027] VCC[094]
L22 D[22]# D[54]# AD20 D12 VCC[028] VCC[095] AF12
H_D#23 H_D#55

/x
M23 D[23]# D[55]# AE22 D14 VCC[029] VCC[096] AF14
H_D#24 P25 AF23 H_D#56 D15 AF15
H_D#25 D[24]# D[56]# H_D#57 VCC[030] VCC[097]
P23 D[25]# D[57]# AC25 D17 VCC[031] VCC[098] AF17
H_D#26 P22 AE21 H_D#58 D18 AF18
H_D#27 D[26]# D[58]# H_D#59 VCC[032] VCC[099] +VCCP
T24 D[27]# D[59]# AD21 E7 VCC[033] VCC[100] AF20
H_D#28 R24 AC22 H_D#60 E9 R19
H_D#29 D[28]# D[60]# H_D#61 VCC[034]
L25 AD23 E10 G21 +VCCPA 1 2 0_0402_5%

su
H_D#30 D[29]# D[61]# H_D#62 VCC[035] VCCP[01] +VCCPB 0_0402_5%
T25 D[30]# D[62]# AF22 E12 VCC[036] VCCP[02] V6 1 2
C H_D#31 H_D#63 R20 C
N25 D[31]# D[63]# AC23 E13 VCC[037] VCCP[03] J6
H_DSTBN#1 L26 AE25 H_DSTBN#3 E15 K6 1
9 H_DSTBN#1 DSTBN[1]# DSTBN[3]# H_DSTBN#3 9 VCC[038] VCCP[04]
H_DSTBP#1 M26 AF24 H_DSTBP#3 E17 M6
9 H_DSTBP#1 H_DINV#1 DSTBP[1]# DSTBP[3]# H_DINV#3 H_DSTBP#3 9 VCC[039] VCCP[05] + C6
9 H_DINV#1 N24 DINV[1]# DINV[3]# AC20 H_DINV#3 9 E18 VCC[040] VCCP[06] J21
E20 K21 330U_D2E_2.5VM_R7
VCC[041] VCCP[07]

p.
+V_CPU_GTLREF AD26 R26 COMP0 F7 M21
@ R21 TEST1 GTLREF COMP[0] COMP1 VCC[042] VCCP[08] 2
1 2 1K_0402_5% C23 MISC U26 F9 N21
@ R22 TEST2 TEST1 COMP[1] COMP2 VCC[043] VCCP[09]
1 2 1K_0402_5% D25 AA1 F10 N6
TEST3 TEST2 COMP[2] COMP3 VCC[044] VCCP[10]
T2 C24 Y1 F12 R21
TEST4 TEST3 COMP[3] VCC[045] VCCP[11]
T3 AF26 F14 R6
TEST4 VCC[046] VCCP[12]

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TEST5 AF1 E5 H_DPRSTP# R23 R24 R25 R26 F15 T21
T4 TEST5 DPRSTP# H_DPRSTP# 9,21,42 VCC[047] VCCP[13]

54.9_0402_1%

27.4_0402_1%

54.9_0402_1%

27.4_0402_1%
TEST6 A26 B5 H_DPSLP# F17 T6
T5 TEST6 DPSLP# H_DPSLP# 21 VCC[048] VCCP[14]

1
TEST7 C3 D24 H_DPWR# F18 V21
T6 TEST7 DPWR# H_DPWR# 9 VCC[049] VCCP[15]
CPU_BSEL0 B22 D6 H_PWRGOOD F20 W21
17 CPU_BSEL0 CPU_BSEL1 BSEL[0] PWRGOOD H_CPUSLP# H_PWRGOOD 21 VCC[050] VCCP[16]
17 CPU_BSEL1 B23 D7 H_CPUSLP# 9 AA7
CPU_BSEL2 BSEL[1] SLP# H_PSI# VCC[051]
17 CPU_BSEL2 C21 AE6 H_PSI# 42 AA9 B26
BSEL[2] PSI# VCC[052] VCCA[01] +1.5VS
AA10 C26

2
VCC[053] VCCA[02]

10U_0805_6.3V6M

0.01U_0402_16V7K
Penryn AA12
VCC[054]

yc
AA13 AD6
* Route the TEST3 and TEST5 signals through VCC[055] VID[0] CPU_VID0 42
AA15 AF5 CPU_VID1 42 1 1
VCC[056] VID[1]
a ground referenced Zo = 55-ohm trace that
AA17 AE5 CPU_VID2 42
VCC[057] VID[2] C7 C8
AA18 AF4 CPU_VID3 42
VCC[058] VID[3]
ends in a via that is near a GND via and is Resistor placed within 0.5"
AA20
AB9
VCC[059] VID[4]
AE3
AF3
CPU_VID4 42 2 2
accessible through an oscilloscope VCC[060] VID[5] CPU_VID5 42

m
of CPU pin.Trace should be
AC10 AE2 CPU_VID6 42
VCC[061] VID[6]
connection.
AB10
VCC[062]
at least 25 mils away from AB12
AB14
VCC[063]
AF7 VCCSENSE
any other toggling signal. Near pin B26
VCC[064] VCCSENSE VCCSENSE 42
AB15
VCC[065]
// COMP[0,2] trace width is 18
AB17
AB18
VCC[066]
VCC[067] VSSSENSE
AE7 VSSSENSE
VSSSENSE 42
B
CPU_BSEL CPU_BSEL2 CPU_BSEL1 CPU_BSEL0 mils. COMP[1,3] trace width Penryn B

is 4 mils. .
p:

166 0 1 1

200 0 1 0 Length match within 25 mils.


The trace width/space/other is 20/7/25.
tt

+VCCP
266 0 0 0
h

R27
1K_0402_1%
+VCC_CORE
2

+V_CPU_GTLREF

R28 1 2 100_0402_1% VCCSENSE


1

R29
2K_0402_1% R30 1 2 100_0402_1% VSSSENSE
2

Close to CPU pin within


Close to CPU pin AD26 500mils.
A
within 500mils. A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/08/28 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Penryn(2/3)-AGTL+/ITP-XDP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Montevina UMA 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 18, 2009 Sheet 7 of 46
5 4 3 2 1
5 4 3 2 1

+VCC_CORE

1 1 1 1 1 1 1 1
Place these capacitors on C9 C10 C11 C12 C13 C14 C15 C16
L8 (North side,Secondary 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
Layer) 2 2 2 2 2 2 2 2

D D
+VCC_CORE
JCPU1D
A4 P6
VSS[001] VSS[082]
A8
VSS[002] VSS[083]
P21 Place these capacitors on 1 1 1 1 1 1 1 1
A11
A14
VSS[003] VSS[084]
P24
R2
L8 (North side,Secondary C17 C18 C19 C20 C21 C22 C23 C24

A16
VSS[004]
VSS[005]
VSS[085]
VSS[086]
R5 Layer) 2
10U_0805_6.3V6M
2
10U_0805_6.3V6M
2
10U_0805_6.3V6M
2
10U_0805_6.3V6M
2
10U_0805_6.3V6M
2
10U_0805_6.3V6M
2
10U_0805_6.3V6M
2
10U_0805_6.3V6M
A19 R22
VSS[006] VSS[087]
A23 R25
VSS[007] VSS[088]
AF2 T1
VSS[008] VSS[089]
B6 VSS[009] VSS[090] T4
B8 T23 +VCC_CORE
VSS[010] VSS[091]
B11 VSS[011] VSS[092] T26
B13 VSS[012] VSS[093] U3
B16 VSS[013] VSS[094] U6 Place these capacitors on 1 1 1 1 1 1 1 1
B19
B21
VSS[014] VSS[095] U21
U24
L8 (North side,Secondary C25 C26 C27 C28 C29 C30 C31 C32

B24
VSS[015]
VSS[016]
VSS[096]
VSS[097] V2 Layer) 2
10U_0805_6.3V6M
2
10U_0805_6.3V6M
2
10U_0805_6.3V6M
2
10U_0805_6.3V6M
2
10U_0805_6.3V6M
2
10U_0805_6.3V6M
2
10U_0805_6.3V6M
2
10U_0805_6.3V6M
C5 VSS[017] VSS[098] V5
C8 VSS[018] VSS[099] V22

/
C11 VSS[019] VSS[100] V25
C14 VSS[020] VSS[101] W1
C16 W4 +VCC_CORE
VSS[021] VSS[102]

/x
C19 VSS[022] VSS[103] W23
C2 VSS[023] VSS[104] W26
C22 VSS[024] VSS[105] Y3 Place these capacitors on 1 1 1 1 1 1 1 1
C25
D1
VSS[025] VSS[106] Y6
Y21
L8 (North side,Secondary C33 C34 C35 C36 C37 C38 C39 C40

D4
VSS[026]
VSS[027]
VSS[107]
VSS[108] Y24 Layer) 2
10U_0805_6.3V6M
2
10U_0805_6.3V6M
2
10U_0805_6.3V6M
2
10U_0805_6.3V6M
2
10U_0805_6.3V6M
2
10U_0805_6.3V6M
2
10U_0805_6.3V6M
2
10U_0805_6.3V6M
D8 AA2

su
VSS[028] VSS[109]
D11 VSS[029] VSS[110] AA5
C C
D13 VSS[030] VSS[111] AA8
D16 AA11
Mid Frequence Decoupling
VSS[031] VSS[112]
D19 VSS[032] VSS[113] AA14
D23 VSS[033] VSS[114] AA16
D26 VSS[034] VSS[115] AA19

p.
E3 VSS[035] VSS[116] AA22
E6 VSS[036] VSS[117] AA25
E8 AB1
VSS[037] VSS[118]
E11 AB4
VSS[038] VSS[119]
E14 AB8
VSS[039] VSS[120]

om
E16 AB11

ESR <= 1.5m ohm


VSS[040] VSS[121]
E19 AB13
VSS[041] VSS[122]
E21 AB16
Near CPU CORE regulator
VSS[042] VSS[123]

Capacitor > 1980uF


E24 AB19
VSS[043] VSS[124]
F5 AB23
VSS[044] VSS[125]
F8 AB26
VSS[045] VSS[126]
F11 AC3
VSS[046] VSS[127]
F13 AC6
VSS[047] VSS[128] +VCC_CORE

yc
F16 AC8
VSS[048] VSS[129]
F19 AC11
VSS[049] VSS[130]
F2 AC14
VSS[050] VSS[131]
F22 AC16
VSS[051] VSS[132]
330U_D2_2VY_R7M

330U_D2_2VY_R7M

330U_D2_2VY_R7M

330U_D2_2VY_R7M
F25 AC19
VSS[052] VSS[133]
G4 AC21
VSS[053] VSS[134]

m
G1 AC24 1 1 1 1
VSS[054] VSS[135] @
G23 AD2
VSS[055] VSS[136] C41 + C42 + C43 + C44 +
G26 AD5
VSS[056] VSS[137]
H3 AD8
VSS[057] VSS[138]
H6 AD11
VSS[058] VSS[139] 2 2 2 2
H21
H24
VSS[059]
VSS[060]
VSS[140]
VSS[141]
AD13
AD16
//
J2 AD19
B VSS[061] VSS[142] B
J5 AD22
VSS[062] VSS[143]
J22 AD25
VSS[063] VSS[144]
J25 AE1
VSS[064] VSS[145]
K1 AE4
p:

VSS[065] VSS[146]
K4 AE8
VSS[066] VSS[147]
K23 AE11
VSS[067] VSS[148]
K26 AE14
VSS[068] VSS[149]
L3 AE16
VSS[069] VSS[150]
L6 AE19
tt

VSS[070] VSS[151]
L21 AE23
VSS[071] VSS[152]
L24 AE26
VSS[072] VSS[153]
M2 A2
Inside CPU center cavity in 2 rows
VSS[073] VSS[154]
M5 AF6
VSS[074] VSS[155]
h

M22 AF8 +VCCP


VSS[075] VSS[156]
M25 AF11
VSS[076] VSS[157]
N1 AF13
VSS[077] VSS[158]
N4 AF16 1 1 1 1 1 1
VSS[078] VSS[159] C45 C46 C47 C48 C49 C50
N23 AF19
VSS[079] VSS[160]
N26 AF21
VSS[080] VSS[161] 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
P3 A25
VSS[081] VSS[162] 2 2 2 2 2 2
AF25
VSS[163]
Penryn
.

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/08/28 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Penryn(3/3)-AGTL+/ITP-XDP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Montevina UMA 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 18, 2009 Sheet 8 of 46
5 4 3 2 1
5 4 3 2 1

H_A#[3..35] 6 U2B
7 H_D#[0..63] U2A

DDR CLK/ CONTROL/COMPENSATION


A14 H_A#3 M36
H_D#0 H_A#_3 H_A#4 T7 RESERVED M_CLK_DDR0
F2 H_D#_0 H_A#_4 C15 T8 N36 RESERVED SA_CK_0 AP24 M_CLK_DDR0 15

0.01U_0402_25V7K
H_D#1 H_A#5 M_CLK_DDR1

2.2U_0603_6.3V4Z
G8 H_D#_1 H_A#_5 F16 T9 R33 RESERVED SA_CK_1 AT21 M_CLK_DDR1 15
H_D#2 F8 H13 H_A#6 T33 AV24 M_CLK_DDR2 M_CLK_DDR2 16
H_D#3 H_D#_2 H_A#_6 H_A#7 +1.8V T10 RESERVED SB_CK_0 M_CLK_DDR3
E6 H_D#_3 H_A#_7 C18 T11 AH9 RESERVED SB_CK_1 AU20 M_CLK_DDR3 16
H_D#4 G2 M16 H_A#8 AH10
H_D#5 H_D#_4 H_A#_8 H_A#9 T12 RESERVED M_CLK_DDR#0
H6 H_D#_5 H_A#_9 J13 1 1 T13 AH12 RESERVED SA_CK#_0 AR24 M_CLK_DDR#0 15

1
C51

C52
H_D#6 H2 P16 H_A#10 AH13 AR21 M_CLK_DDR#1
H_D#7 H_D#_6 H_A#_10 H_A#11 T14 RESERVED SA_CK#_1 M_CLK_DDR#2 M_CLK_DDR#1 15
F6 R16 R31 K12 AU24
H_D#8 H_D#_7 H_A#_11 H_A#12 T15 RESERVED SB_CK#_0 M_CLK_DDR#3 M_CLK_DDR#2 16
D4 N17 1K_0402_1% AL34 AV20
H_D#9 H_D#_8 H_A#_12 H_A#13 2 2 T16 RESERVED SB_CK#_1 M_CLK_DDR#3 16
H3 M13 T17 AK34
H_D#10 H_D#_9 H_A#_13 H_A#14 RESERVED DDR_CKE0_DIMMA
M9 E17 T18 AN35 BC28 DDR_CKE0_DIMMA 15

2
H_D#11 H_D#_10 H_A#_14 H_A#15 SMRCOMP_VOH RESERVED SA_CKE_0 DDR_CKE1_DIMMA
80% of 1.8V VCC_SM
M11 P17 T19 AM35 AY28 DDR_CKE1_DIMMA 15
D H_D#12 H_D#_11 H_A#_15 H_A#16 RESERVED SA_CKE_1 DDR_CKE2_DIMMB D
J1 F17 T20 T24 AY36 DDR_CKE2_DIMMB 16
H_D#_12 H_A#_16 RESERVED SB_CKE_0

1
H_D#13 J2 G20 H_A#17 BB36 DDR_CKE3_DIMMB
H_D#_13 H_A#_17 SB_CKE_1 DDR_CKE3_DIMMB 16

RSVD
H_D#14 N12 B19 H_A#18 R32 B31
H_D#15 H_D#_14 H_A#_18 H_A#19 3.01K_0402_1% RESERVED DDR_CS0_DIMMA#
20% of 1.8V VCC_SM
J6 J16 T22 B2 BA17 DDR_CS0_DIMMA# 15
H_D#16 H_D#_15 H_A#_19 H_A#20 RESERVED SA_CS#_0 DDR_CS1_DIMMA#
P2 E20 T23 M1 AY16 DDR_CS1_DIMMA# 15
H_D#17 H_D#_16 H_A#_20 H_A#21 RESERVED SA_CS#_1 DDR_CS2_DIMMB#
L2 H16 AV16 DDR_CS2_DIMMB# 16

2
H_D#18 H_D#_17 H_A#_21 H_A#22 SMRCOMP_VOL SB_CS#_0 DDR_CS3_DIMMB#
R2 J20 AR13 DDR_CS3_DIMMB# 16
H_D#19 H_D#_18 H_A#_22 H_A#23 SB_CS#_1
N9 L17 T24 AY21
H_D#_19 H_A#_23 RESERVED

1
0.01U_0402_25V7K
H_D#20 H_A#24 M_ODT0

2.2U_0603_6.3V4Z
L6 A17 BD17 M_ODT0 15
H_D#21 H_D#_20 H_A#_24 H_A#25 R33 SA_ODT_0 M_ODT1
M5 B17 1 1 AY17 M_ODT1 15
H_D#_21 H_A#_25 SA_ODT_1 +1.8V

C53

C54
H_D#22 J3 L16 H_A#26 1K_0402_1% BF15 M_ODT2 M_ODT2 16
H_D#23 H_D#_22 H_A#_26 H_A#27 SB_ODT_0 M_ODT3
N2 H_D#_23 H_A#_27 C21 T25 BG23 RESERVED SB_ODT_1 AY13 M_ODT3 16
H_D#24 R1 J17 H_A#28 BF23
T26

2
H_D#25 H_D#_24 H_A#_28 H_A#29 2 2 RESERVED SMRCOMP R34
N5 H20 T27 BH18 BG22 1 2 80.6_0402_1%
H_D#26 H_D#_25 H_A#_29 H_A#30 RESERVED SM_RCOMP SMRCOMP# R35 2 80.6_0402_1%
Follow Design Guide
N6 H_D#_26 H_A#_30 B18 T28 BF18 RESERVED SM_RCOMP# BH21 1
H_D#27 P13 K17 H_A#31
H_D#_27 H_A#_31
For Cantiga: 80.6ohm
H_D#28 N8 B20 H_A#32 BF28 SMRCOMP_VOH
H_D#29 H_D#_28 H_A#_32 H_A#33 +3VS SM_RCOMP_VOH SMRCOMP_VOL
L7 H_D#_29 H_A#_33 F21 SM_RCOMP_VOL BH28
H_D#30 N10 K21 H_A#34
H_D#31 H_D#_30 H_A#_34 H_A#35 PM_EXTTS#0 R38 V_DDR_MCH_REF
M3 H_D#_31 H_A#_35 L20 1 2 10K_0402_5% SM_VREF AV42
H_D#32 Y3 AR36 SM_PWROK R36 1 2 0_0402_5%
H_D#_32 SM_PWROK

/
H_D#33 AD14 H12 H_ADS# BF17 SM_REXT R37 1 2 499_0402_1%
H_D#34 H_D#_33 H_ADS# H_ADSTB#0 H_ADS# 6 PM_EXTTS#1 SM_REXT TP_SM_DRAMRST#
Y6 B16 R39 1 2 10K_0402_5% BC36
H_D#35 H_D#_34 H_ADSTB#_0 H_ADSTB#1 H_ADSTB#0 6 SM_DRAMRST# T29
Y10 H_D#_35 H_ADSTB#_1 G17 H_ADSTB#1 6
H_D#36 H_BNR# CLK_MCH_DREFCLK

/x
Y12 H_D#_36 H_BNR# A9 H_BNR# 6 DPLL_REF_CLK B38 CLK_MCH_DREFCLK 17
H_D#37 Y14 F11 H_BPRI# CLKREQ#_7 R40 1 2 10K_0402_5% A38 CLK_MCH_DREFCLK#
H_D#38 H_D#_37 H_BPRI# H_BR0# H_BPRI# 6 DPLL_REF_CLK# MCH_SSCDREFCLK CLK_MCH_DREFCLK# 17
Y7 H_D#_38 H_BREQ# G12 H_BR0# 6 DPLL_REF_SSCLK E41 MCH_SSCDREFCLK 17
H_D#39 W2 E9 H_DEFER# F41 MCH_SSCDREFCLK#
HOST

H_D#40 H_D#_39 H_DEFER# H_DBSY# H_DEFER# 6 DPLL_REF_SSCLK# MCH_SSCDREFCLK# 17


AA8 H_D#_40 H_DBSY# B10 H_DBSY# 6

CLK
H_D#41 Y9 AH7 CLK_MCH_BCLK F43 CLK_MCH_3GPLL
H_D#_41 HPLL_CLK CLK_MCH_BCLK 17 PEG_CLK CLK_MCH_3GPLL 17
H_D#42 AA13 AH6 CLK_MCH_BCLK# E43 CLK_MCH_3GPLL#

su
H_D#43 H_D#_42 HPLL_CLK# H_DPWR# CLK_MCH_BCLK# 17 PEG_CLK# CLK_MCH_3GPLL# 17
AA9 H_D#_43 H_DPWR# J11 H_DPWR# 7
C H_D#44 H_DRDY# C
AA11 H_D#_44 H_DRDY# F9 H_DRDY# 6
H_D#45 AD11 H9 H_HIT#
H_D#_45 H_HIT# H_HIT# 6
H_D#46 AD10 E12 H_HITM# AE41 DMI_TXN0
H_D#47 H_D#_46 H_HITM# H_LOCK# H_HITM# 6 DMI_RXN_0 DMI_TXN1 DMI_TXN0 22
AD13 H_D#_47 H_LOCK# H11 H_LOCK# 6 DMI_RXN_1 AE37 DMI_TXN1 22
H_D#48 AE12 C9 H_TRDY# AE47 DMI_TXN2
H_D#_48 H_TRDY# H_TRDY# 6 DMI_RXN_2 DMI_TXN2 22

p.
H_D#49 AE9 AH39 DMI_TXN3
H_D#50 H_D#_49 DMI_RXN_3 DMI_TXN3 22
AA2 H_D#_50
H_D#51 AD8 AE40 DMI_TXP0
H_D#52 H_D#_51 MCH_CLKSEL0 DMI_RXP_0 DMI_TXP1 DMI_TXP0 22
AA3 17 MCH_CLKSEL0 T25 AE38 DMI_TXP1 22
H_D#53 H_D#_52 H_DINV#0 MCH_CLKSEL1 CFG_0 DMI_RXP_1 DMI_TXP2
AD3 J8 H_DINV#0 7 17 MCH_CLKSEL1 R25 AE48 DMI_TXP2 22
H_D#_53 H_DINV#_0 CFG_1 DMI_RXP_2

om
H_D#54 AD7 L3 H_DINV#1 MCH_CLKSEL2 P25 AH40 DMI_TXP3
H_D#_54 H_DINV#_1 H_DINV#1 7 17 MCH_CLKSEL2 CFG_2 DMI_RXP_3 DMI_TXP3 22
H_D#55 AE14 Y13 H_DINV#2 P20
H_D#_55 H_DINV#_2 H_DINV#2 7 T85 CFG_3
H_D#56 AF3 Y1 H_DINV#3 P24 AE35 DMI_RXN0
H_D#_56 H_DINV#_3 H_DINV#3 7 T86 CFG_4 DMI_TXN_0 DMI_RXN0 22
H_D#57 AC1 CFG5 C25 AE43 DMI_RXN1
H_D#58 H_D#_57 H_DSTBN#0 11 CFG5 CFG6 CFG_5 DMI_TXN_1 DMI_RXN2 DMI_RXN1 22
AE3 L10 H_DSTBN#0 7 11 CFG6 N24 AE46 DMI_RXN2 22
H_D#59 H_D#_58 H_DSTBN#_0 H_DSTBN#1 CFG7 CFG_6 DMI_TXN_2 DMI_RXN3
AC3 M7 H_DSTBN#1 7 11 CFG7 M24 AH42 DMI_RXN3 22
H_D#60 H_D#_59 H_DSTBN#_1 H_DSTBN#2 CFG8 CFG_7 DMI_TXN_3
AE11 AA5 H_DSTBN#2 7 11 CFG8 E21
H_D#_60 H_DSTBN#_2 CFG_8

CFG
H_D#61 AE8 AE6 H_DSTBN#3 CFG9 C23 AD35 DMI_RXP0
H_DSTBN#3 7 11 CFG9 DMI_RXP0 22

DMI
H_D#_61 H_DSTBN#_3 CFG_9 DMI_TXP_0

yc
H_D#62 AG2 CFG10 C24 AE44 DMI_RXP1
H_D#63 H_D#_62 H_DSTBP#0 11 CFG10 CFG11 CFG_10 DMI_TXP_1 DMI_RXP2 DMI_RXP1 22
AD6 L9 H_DSTBP#0 7 11 CFG11 N21 AF46 DMI_RXP2 22
H_D#_63 H_DSTBP#_0 H_DSTBP#1 CFG12 CFG_11 DMI_TXP_2 DMI_RXP3
M8 H_DSTBP#1 7 11 CFG12 P21 AH43 DMI_RXP3 22
H_DSTBP#_1 H_DSTBP#2 CFG13 CFG_12 DMI_TXP_3
AA6 H_DSTBP#2 7 11 CFG13 T21
+H_SWNG H_DSTBP#_2 H_DSTBP#3 CFG14 CFG_13
C5 AE5 H_DSTBP#3 7 11 CFG14 R20
H_RCOMP H_SWING H_DSTBP#_3 CFG15 CFG_14
E3 11 CFG15 M20
H_RCOMP CFG_15

m
B15 H_REQ#0 CFG16 L21
H_REQ#_0 H_REQ#1 H_REQ#0 6 11 CFG16 CFG17 CFG_16

GRAPHICS VID
K13 H_REQ#1 6 11 CFG17 H21
H_REQ#_1 H_REQ#2 CFG18 CFG_17
F13 H_REQ#2 6 11 CFG18 P29
H_REQ#_2 H_REQ#3 CFG19 CFG_18
B13 H_REQ#3 6 11 CFG19 R28
H_RESET# H_REQ#_3 H_REQ#4 CFG20 CFG_19
6 H_RESET# C12 B14 H_REQ#4 6 11 CFG20 T28 B33 T30
H_CPURST# H_REQ#_4 CFG_20 GFX_VID_0
7 H_CPUSLP#
H_CPUSLP# E11
H_CPUSLP#
H_RS#_0
B6 H_RS#0 H_RS#0 6
// GFX_VID_1
GFX_VID_2
B32
G33
T31
F12 H_RS#1 H_RS#1 6 F33
B H_RS#_1 H_RS#2 PM_BMBUSY# GFX_VID_3 B
C8 H_RS#2 6 22 PM_BMBUSY# R29 E33
+H_VREF H_RS#_2 H_DPRSTP# PM_SYNC# GFX_VID_4
A11 7,21,42 H_DPRSTP# B7
H_AVREF PM_EXTTS#0 PM_DPRSTP#
B11 15 PM_EXTTS#0 N33
H_DVREF PM_EXTTS#1 PM_EXT_TS#_0
P32
p:

16 PM_EXTTS#1 PM_EXT_TS#_1

PM
CANTIGA ES_FCBGA1329 PM_PWROK AT40 C34
Layout note: PLT_RST# 22,32 PM_PWROK PWROK GFX_VR_EN T35 +VCCP
R41 1 2 AT11
20,25,26 PLT_RST# RSTIN#
R42 1 2 100_0402_5% THERMTRIP# T20
6,21 H_THERMTRIP#
Route H_SCOMP and H_SCOMP# with trace 22,42 DPRSLPVR 0_0402_5% DPRSLPVR R32
THERMTRIP#
DPRSLPVR

1
width, spacing and impedance (55 ohm) same as
tt

AH37 CL_CLK0 R43


CL_CLK CL_CLK0 22
FSB data traces

0.1U_0402_16V4Z
AH36 CL_DATA0 1K_0402_1%
CL_DATA CL_DATA0 22
1 @ BG48 AN36 M_PWROK
NC CL_PWROK CL_RST# M_PWROK 22,32
C55 BF48 AJ35
Layout Note: Layout Note: V_DDR_MCH_REF
CL_RST# 22

2
NC CL_RST#
h

BD48 AH34 +CL_VREF

ME
NC CL_VREF
H_RCOMP / H_VREF / H_SWNG trace width and spacing is 20/20.
BC48
NC

1
2 BH47 0621 add CLK and DAT for DVI
NC 1
trace width and spacing is 10/20 BG47
BE47
NC
NC DDPC_CTRLCLK
N28 T36
C56
0.1U_0402_16V4Z
R44
499_0402_1%
+1.8V BH46 M28
+V_DDR_MCH_REF generated by DC-DC NC DDPC_CTRLDATA HDMICLK_NB T37 2
BF46 G36 HDMICLK_NB 34

2
+VCCP NC SDVO_CTRLCLK

NC
BG45 E36 HDMIDAT_NB
NC SDVO_CTRLDATA HDMIDAT_NB 34
1

+VCCP BH44 K36 CLKREQ#_7


NC CLKREQ# CLKREQ#_7 17

MISC
R45 BH43 H36 MCH_ICH_SYNC#
NC ICH_SYNC# MCH_ICH_SYNC# 22
1K_0402_1%

221_0603_1%

10K_0402_1%
*R44*Follow
BH6
NC
1

BH5 1 R737 2 56_0402_5% +VCCP


NC
Intel feedback
R46 R47 BG4 B12 TSATN#
TSATN# 32
2

V_DDR_MCH_REF NC TSATN#
15,16 V_DDR_MCH_REF BH3
NC
BF3
NC
1
0.1U_0402_16V4Z

BH2
2

+H_VREF H_RCOMP +H_SWNG R48 NC


1 BG2 B28 HDA_BITCLK_NB 21
C57 10K_0402_1% NC HDA_BCLK R210
BE2 B30 HDA_RST#_NB 21
NC HDA_RST#
24.9_0402_1%

0.1U_0402_16V4Z

BG1 NC HDA_SDI B29 HDA_SDIN2_NB 1 2 HDA_SDIN2 21


1

1
100_0402_1%

A A
0.1U_0402_16V4Z

1 1 BF1 C29 HDA_SDOUT_NB 21


2

2 NC HDA_SDO
2K_0402_1%

R52 C58 R54 R55 C59 BD1 A28 33_0402_5%


NC HDA_SYNC HDA_SYNC_NB 21

HDA
BC1 NC
F1 NC
2 2 0830 Add pull-up and pull-down resistor.
A47
2

NC
CANTIGA ES_FCBGA1329
Security Classification Compal Secret Data Compal Electronics, Inc.
within 100 mils from NB Near B3 pin Issued Date 2007/08/28 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga(1/6)-AGTL/DMI/DDR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Montevina UMA 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 18, 2009 Sheet 9 of 46
5 4 3 2 1
5 4 3 2 1

D D

15 DDR_A_D[0..63] 16 DDR_B_D[0..63]
U2D U2E
DDR_A_D0 AJ38 BD21 DDR_A_BS0 DDR_B_D0 AK47 BC16 DDR_B_BS0
DDR_A_D1 SA_DQ_0 SA_BS_0 DDR_A_BS1 DDR_A_BS0 15 DDR_B_D1 SB_DQ_0 SB_BS_0 DDR_B_BS1 DDR_B_BS0 16
AJ41 BG18 DDR_A_BS1 15 AH46 BB17 DDR_B_BS1 16
DDR_A_D2 SA_DQ_1 SA_BS_1 DDR_A_BS2 DDR_B_D2 SB_DQ_1 SB_BS_1 DDR_B_BS2
AN38 AT25 DDR_A_BS2 15 AP47 BB33 DDR_B_BS2 16
DDR_A_D3 SA_DQ_2 SA_BS_2 DDR_B_D3 SB_DQ_2 SB_BS_2
AM38 AP46
DDR_A_D4 SA_DQ_3 DDR_A_RAS# DDR_B_D4 SB_DQ_3
AJ36 BB20 DDR_A_RAS# 15 AJ46
DDR_A_D5 SA_DQ_4 SA_RAS# DDR_A_CAS# DDR_B_D5 SB_DQ_4 DDR_B_RAS#
AJ40 BD20 DDR_A_CAS# 15 AJ48 AU17 DDR_B_RAS# 16
DDR_A_D6 SA_DQ_5 SA_CAS# DDR_A_WE# DDR_B_D6 SB_DQ_5 SB_RAS# DDR_B_CAS#
AM44 AY20 DDR_A_WE# 15 AM48 BG16 DDR_B_CAS# 16
DDR_A_D7 SA_DQ_6 SA_WE# DDR_B_D7 SB_DQ_6 SB_CAS# DDR_B_WE#
AM42 AP48 BF14 DDR_B_WE# 16
DDR_A_D8 SA_DQ_7 DDR_B_D8 SB_DQ_7 SB_WE#
AN43 SA_DQ_8 AU47 SB_DQ_8
DDR_A_D9 AN44 DDR_B_D9 AU46
DDR_A_D10 SA_DQ_9 DDR_A_DM[0..7] 15 DDR_B_D10 SB_DQ_9
AU40 SA_DQ_10 BA48 SB_DQ_10
DDR_A_D11 AT38 AM37 DDR_A_DM0 DDR_B_D11 AY48
DDR_A_D12 SA_DQ_11 SA_DM_0 DDR_A_DM1 DDR_B_D12 SB_DQ_11 DDR_B_DM0 DDR_B_DM[0..7] 16
AN41 SA_DQ_12 SA_DM_1 AT41 AT47 SB_DQ_12 SB_DM_0 AM47
DDR_A_D13 AN39 AY41 DDR_A_DM2 DDR_B_D13 AR47 AY47 DDR_B_DM1
DDR_A_D14 SA_DQ_13 SA_DM_2 DDR_A_DM3 DDR_B_D14 SB_DQ_13 SB_DM_1 DDR_B_DM2
AU44 SA_DQ_14 SA_DM_3 AU39 BA47 SB_DQ_14 SB_DM_2 BD40
DDR_A_D15 AU42 BB12 DDR_A_DM4 DDR_B_D15 BC47 BF35 DDR_B_DM3
DDR_A_D16 SA_DQ_15 SA_DM_4 DDR_A_DM5 DDR_B_D16 SB_DQ_15 SB_DM_3 DDR_B_DM4
AV39 SA_DQ_16 SA_DM_5 AY6 BC46 SB_DQ_16 SB_DM_4 BG11
DDR_A_D17 AY44 AT7 DDR_A_DM6 DDR_B_D17 BC44 BA3 DDR_B_DM5
SA_DQ_17 SA_DM_6 SB_DQ_17 SB_DM_5

/
DDR_A_D18 BA40 AJ5 DDR_A_DM7 DDR_B_D18 BG43 AP1 DDR_B_DM6
SA_DQ_18 SA_DM_7 SB_DQ_18 SB_DM_6

A
DDR_A_D19 BD43 DDR_B_D19 BF43 DDR_B_DM7

B
SA_DQ_19 DDR_A_DQS[0..7] 15 SB_DQ_19 SB_DM_7 AK2
DDR_A_D20 AV41 AJ44 DDR_A_DQS0 DDR_B_D20 BE45
DDR_A_D21 SA_DQ_20 SA_DQS_0 DDR_A_DQS1 DDR_B_D21 SB_DQ_20 DDR_B_DQS0 DDR_B_DQS[0..7] 16

/x
AY43 SA_DQ_21 SA_DQS_1 AT44 BC41 SB_DQ_21 SB_DQS_0 AL47
DDR_A_D22 BB41 BA43 DDR_A_DQS2 DDR_B_D22 BF40 AV48 DDR_B_DQS1
DDR_A_D23 SA_DQ_22 SA_DQS_2 DDR_A_DQS3 DDR_B_D23 SB_DQ_22 SB_DQS_1 DDR_B_DQS2
BC40 SA_DQ_23 MEMORY SA_DQS_3 BC37 BF41 SB_DQ_23 SB_DQS_2 BG41
DDR_A_D24 DDR_A_DQS4 DDR_B_D24 DDR_B_DQS3

MEMORY
AY37 SA_DQ_24 SA_DQS_4 AW12 BG38 SB_DQ_24 SB_DQS_3 BG37
DDR_A_D25 BD38 BC8 DDR_A_DQS5 DDR_B_D25 BF38 BH9 DDR_B_DQS4
DDR_A_D26 SA_DQ_25 SA_DQS_5 DDR_A_DQS6 DDR_B_D26 SB_DQ_25 SB_DQS_4 DDR_B_DQS5
AV37 SA_DQ_26 SA_DQS_6 AU8 BH35 SB_DQ_26 SB_DQS_5 BB2
DDR_A_D27 AT36 AM7 DDR_A_DQS7 DDR_B_D27 BG35 AU1 DDR_B_DQS6

su
DDR_A_D28 SA_DQ_27 SA_DQS_7 DDR_A_DQS#0 DDR_A_DQS#[0..7] 15 DDR_B_D28 SB_DQ_27 SB_DQS_6 DDR_B_DQS7
AY38 SA_DQ_28 SA_DQS#_0 AJ43 BH40 SB_DQ_28 SB_DQS_7 AN6 DDR_B_DQS#[0..7] 16
C DDR_A_D29 DDR_A_DQS#1 DDR_B_D29 DDR_B_DQS#0 C
BB38 SA_DQ_29 SA_DQS#_1 AT43 BG39 SB_DQ_29 SB_DQS#_0 AL46
DDR_A_D30 AV36 BA44 DDR_A_DQS#2 DDR_B_D30 BG34 AV47 DDR_B_DQS#1
DDR_A_D31 SA_DQ_30 SA_DQS#_2 DDR_A_DQS#3 DDR_B_D31 SB_DQ_30 SB_DQS#_1 DDR_B_DQS#2
AW36 SA_DQ_31 SA_DQS#_3 BD37 BH34 SB_DQ_31 SB_DQS#_2 BH41
DDR_A_D32 BD13 AY12 DDR_A_DQS#4 DDR_B_D32 BH14 BH37 DDR_B_DQS#3
DDR_A_D33 SA_DQ_32 SA_DQS#_4 DDR_A_DQS#5 DDR_B_D33 SB_DQ_32 SB_DQS#_3 DDR_B_DQS#4
AU11 SA_DQ_33 SA_DQS#_5 BD8 BG12 SB_DQ_33 SB_DQS#_4 BG9

p.
DDR_A_D34 BC11 AU9 DDR_A_DQS#6 DDR_B_D34 BH11 BC2 DDR_B_DQS#5
DDR_A_D35 SA_DQ_34 SA_DQS#_6 DDR_A_DQS#7 DDR_B_D35 SB_DQ_34 SB_DQS#_5 DDR_B_DQS#6
BA12 SA_DQ_35 SA_DQS#_7 AM8 DDR_A_MA[0..14] 15 BG8 SB_DQ_35 SB_DQS#_6 AT2
DDR_A_D36 AU13 DDR_B_D36 BH12 AN5 DDR_B_DQS#7
SYSTEM

SA_DQ_36 SB_DQ_36 SB_DQS#_7

SYSTEM
DDR_A_D37 AV13 BA21 DDR_A_MA0 DDR_B_D37 BF11 DDR_B_MA[0..14] 16
DDR_A_D38 SA_DQ_37 SA_MA_0 DDR_A_MA1 DDR_B_D38 SB_DQ_37 DDR_B_MA0
BD12 BC24 BF8 AV17
SA_DQ_38 SA_MA_1 SB_DQ_38 SB_MA_0

om
DDR_A_D39 BC12 BG24 DDR_A_MA2 DDR_B_D39 BG7 BA25 DDR_B_MA1
DDR_A_D40 SA_DQ_39 SA_MA_2 DDR_A_MA3 DDR_B_D40 SB_DQ_39 SB_MA_1 DDR_B_MA2
BB9 BH24 BC5 BC25
DDR_A_D41 SA_DQ_40 SA_MA_3 DDR_A_MA4 DDR_B_D41 SB_DQ_40 SB_MA_2 DDR_B_MA3
BA9 BG25 BC6 AU25
DDR_A_D42 SA_DQ_41 SA_MA_4 DDR_A_MA5 DDR_B_D42 SB_DQ_41 SB_MA_3 DDR_B_MA4
AU10 BA24 AY3 AW25
DDR_A_D43 SA_DQ_42 SA_MA_5 DDR_A_MA6 DDR_B_D43 SB_DQ_42 SB_MA_4 DDR_B_MA5
AV9 BD24 AY1 BB28
DDR_A_D44 SA_DQ_43 SA_MA_6 DDR_A_MA7 DDR_B_D44 SB_DQ_43 SB_MA_5 DDR_B_MA6
BA11 BG27 BF6 AU28
DDR_A_D45 SA_DQ_44 SA_MA_7 DDR_A_MA8 DDR_B_D45 SB_DQ_44 SB_MA_6 DDR_B_MA7
BD9 BF25 BF5 AW28
DDR_A_D46 SA_DQ_45 SA_MA_8 DDR_A_MA9 DDR_B_D46 SB_DQ_45 SB_MA_7 DDR_B_MA8
AY8 AW24 BA1 AT33
SA_DQ_46 SA_MA_9 SB_DQ_46 SB_MA_8

yc
DDR_A_D47 BA6 BC21 DDR_A_MA10 DDR_B_D47 BD3 BD33 DDR_B_MA9
DDR_A_D48 SA_DQ_47 SA_MA_10 DDR_A_MA11 DDR_B_D48 SB_DQ_47 SB_MA_9 DDR_B_MA10
AV5 BG26 AV2 BB16
SA_DQ_48 SA_MA_11 SB_DQ_48 SB_MA_10
DDR

DDR_A_D49 AV7 BH26 DDR_A_MA12 DDR_B_D49 AU3 AW33 DDR_B_MA11


SA_DQ_49 SA_MA_12 SB_DQ_49 SB_MA_11

DDR
DDR_A_D50 AT9 BH17 DDR_A_MA13 DDR_B_D50 AR3 AY33 DDR_B_MA12
DDR_A_D51 SA_DQ_50 SA_MA_13 DDR_A_MA14 DDR_B_D51 SB_DQ_50 SB_MA_12 DDR_B_MA13
AN8 AY25 AN2 BH15
DDR_A_D52 SA_DQ_51 SA_MA_14 DDR_B_D52 SB_DQ_51 SB_MA_13 DDR_B_MA14
AU5 AY2 AU33
SA_DQ_52 SB_DQ_52 SB_MA_14

m
DDR_A_D53 AU6 DDR_B_D53 AV1
DDR_A_D54 SA_DQ_53 DDR_B_D54 SB_DQ_53
AT5 AP3
DDR_A_D55 SA_DQ_54 DDR_B_D55 SB_DQ_54
AN10 AR1
DDR_A_D56 SA_DQ_55 DDR_B_D56 SB_DQ_55
AM11 AL1
DDR_A_D57 SA_DQ_56 DDR_B_D57 SB_DQ_56
AM5 AL2
SA_DQ_57 SB_DQ_57
DDR_A_D58
DDR_A_D59
AJ9
AJ8
SA_DQ_58
SA_DQ_59
// DDR_B_D58
DDR_B_D59
AJ1
AH1
SB_DQ_58
SB_DQ_59
DDR_A_D60 AN12 DDR_B_D60 AM2
B DDR_A_D61 SA_DQ_60 DDR_B_D61 SB_DQ_60 B
AM13 AM3
DDR_A_D62 SA_DQ_61 DDR_B_D62 SB_DQ_61
AJ11 AH3
DDR_A_D63 SA_DQ_62 DDR_B_D63 SB_DQ_62
AJ12 AJ3
SA_DQ_63 SB_DQ_63
p:

CANTIGA ES_FCBGA1329 CANTIGA ES_FCBGA1329


tt
h

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/08/28 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga(2/6)-DDR2 A/B CH
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Montevina UMA 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 18, 2009 Sheet 10 of 46
5 4 3 2 1
5 4 3 2 1

1
R148
2 ENBKL
U2C
Strap Pin Table
19 NB_BKLT_CTRL NB_BKLT_CTRL L32 R57 +VCC_PEG
000 = FSB
100K_0402_5%
32 ENBKL ENBKL
R58 1 2 10K_0402_5%
G32
L_BKLT_CTRL
L_BKLT_EN PEG_COMPI T37 1 2
49.9_0402_1%
CFG[2:0] FSB Freq 0101066MHz
= FSB
select
+3VS M32 L_CTRL_CLK PEG_COMPO T36
800MHz
011 = FSB
R59 1 2 10K_0402_5% M33 PEGCOMP trace width 667MHz
Others =
DDC2_CLK L_CTRL_DATA
and spacing is 20/25 mils.
19 DDC2_CLK K33 L_DDC_CLK PEG_RX#_0 H44
DDC2_DATA
19 DDC2_DATA J33 L_DDC_DATA PEG_RX#_1 J46
L44 Reserved
ENAVDD M29
PEG_RX#_2
PEG_RX#_3
L40
N41
CFG[4:3] Reserved
19 ENAVDD
R60 1 2 4.75K_0402_1% C44
L_VDD_EN PEG_RX#_4
P48 0 = DMI x
D
Follow Intel DG & B43
LVDS_IBG
LVDS_VBG
PEG_RX#_5
PEG_RX#_6
N44 CFG5 (DMI select) 12 = DMI x
* Interface is
D

Checklist
E37
E38
LVDS_VREFH PEG_RX#_7
T43
U43 40 = The iTPM Host
LVDS_VREFL PEG_RX#_8
CFG6

LVDS
enable
LVDS_ACLK- C41 Y43
LVDS_ACLK+ C40
LVDSA_CLK# PEG_RX#_9
Y48 1 = The iTPM Host Interface is
LVDS_BCLK-
LVDS_BCLK+
B37
A37
LVDSA_CLK
LVDSB_CLK#
PEG_RX#_10
PEG_RX#_11
Y36
AA43 0disable
=(TLS)chiper suite with no
*
LVDSB_CLK PEG_RX#_12
AD37 CFG7 (Intel Management confidentiality
Engine Crypto strap) 1confidentiality
=(TLS)chiper suite with
LVDS_A0- PEG_RX#_13
H47 AC47
LVDS_A1-
LVDS_A2-
E46
G40
LVDSA_DATA#_0
LVDSA_DATA#_1
PEG_RX#_14
PEG_RX#_15
AD39 *
LVDS_A3- LVDSA_DATA#_2
A40 H43
CFG8 Reserved
T38 LVDSA_DATA#_3 PEG_RX_0
PEG_RX_1 J44

GRAPHICS
LVDS_A0+ H48 L43
LVDS_A1+ LVDSA_DATA_0 PEG_RX_2 TMDS_B_HPD#
D45 L41
CFG9 (PCIE Graphics 0 = Reverse Lane,15->0,
LVDS_A2+ LVDSA_DATA_1 PEG_RX_3 TMDS_B_HPD# 34
F40 LVDSA_DATA_2 PEG_RX_4 N40

114->1
LVDS_A3+
Lane Reversal)
B40 P47
T39 LVDSA_DATA_3 PEG_RX_5
N43 = Normal Operation,Lane Number
LVDS_B0-
LVDS_B1-
A41
H38
LVDSB_DATA#_0
PEG_RX_6
PEG_RX_7 T42
U42 in order *
LVDS_B2- LVDSB_DATA#_1 PEG_RX_8
G37 Y42
LVDSB_DATA#_2 PEG_RX_9
CFG10 (PCIE 0=

/
LVDS_B3- J37 W47
T40 LVDSB_DATA#_3 PEG_RX_10
LVDS_B0+ B42
PEG_RX_11 Y37
AA42 Lookback Enable
1 = Disable
LVDSB_DATA_0 PEG_RX_12
*
CFG11 enable)
LVDS_B1+

/x
G38 AD36
LVDS_B2+
LVDS_B3+
F37
K37
LVDSB_DATA_1
LVDSB_DATA_2
PEG_RX_13
PEG_RX_14 AC48
AD40
Reserved
T41 TV_COMPS LVDSB_DATA_3 PEG_RX_15
00 = Reserved

PCI-EXPRESS
CFG[13:12] 01 = XOR Mode
T48 TV_LUMA TMDS_BDATA2#
J41 C274 1 2 0.1U_0402_10V7K TMDS_B_DATA2# 34
10 = All Z Mode
T49 PEG_TX#_0
Enabled
TV_CRMA TMDS_BDATA1# C275 0.1U_0402_10V7K
(XOR/ALLZ)
M46 1 2 TMDS_B_DATA1# 34
11 = Normal (Default)
T50 PEG_TX#_1
Enabled
F25 M47 TMDS_BDATA0# C276 1 2 0.1U_0402_10V7K TMDS_B_DATA0# 34
*

su
TVA_DAC PEG_TX#_2
1

Operation
H25 M40 TMDS_BCLK# C277 1 2 0.1U_0402_10V7K
Follow Intel DG & TVB_DAC PEG_TX#_3 TMDS_B_CLK# 34
75_0402_1%

75_0402_1%

75_0402_1%

C C
K25 M42
TVC_DAC PEG_TX#_4
CFG[15:14] Reserved

TV
R61 R62 R63
Checklist PEG_TX#_5 R48
H24 TV_RTN PEG_TX#_6 N38
T40
CFG16 (FSB Dynamic ODT) 01 ==
2

PEG_TX#_7
PEG_TX#_8 U37

p.
PEG_TX#_9 U40
Disabled *
+3VS @ R64 1 2 2.2K_0402_5%
C31
E32
TV_DCONSEL_0 PEG_TX#_10 Y40
AA46 Enabled
R406
M_BLUE
1 2 0_0402_5% TV_DCONSEL_1 PEG_TX#_11
PEG_TX#_12
AA37
AA40
CFG[18:17] Reserved
18 M_BLUE PEG_TX#_13

om
M_GREEN AD43
CFG19 (DMI Lane Reversal) 0 = Normal
18 M_GREEN PEG_TX#_14
M_RED AC46
18 M_RED PEG_TX#_15
(Lane number in
Operation *
1

1
150_0402_1%

150_0402_1%

150_0402_1%

1 = Order)
E28 J42 TMDS_BDATA2 C278 1 2 0.1U_0402_10V7K TMDS_B_DATA2 34
Follow Intel DG & R65 R66 R67
CRT_BLUE PEG_TX_0
PEG_TX_1
L46 TMDS_BDATA1
TMDS_BDATA0
C279
C280
1 2 0.1U_0402_10V7K
0.1U_0402_10V7K
TMDS_B_DATA1 34 Reverse Lane
Checklist
G28 M48 1 2 TMDS_B_DATA0 34
CRT_GREEN PEG_TX_2 TMDS_BCLK C281 0.1U_0402_10V7K
M39 1 2 TMDS_B_CLK 34
PEG_TX_3
J28 M43
CFG20 (PCIE/SDVO 0 = Only PCIE or SDVO is
2

CRT_RED PEG_TX_4
VGA

yc
R47
G29
CRT_IRTN
PEG_TX_5
PEG_TX_6
N37
T39 concurrent) operational.
1 = PCIE/SDVO are operating
*
PEG_TX_7
simu.
3VDDCCL H32 U36
18 3VDDCCL CRT_DDC_CLK PEG_TX_8
3VDDCDA J32 U39
18 3VDDCDA CRT_HSYNC R68 1 HSYNC CRT_DDC_DATA PEG_TX_9
18 CRT_HSYNC 2 J29 Y39
CRT_HSYNC PEG_TX_10

m
30.1_0402_1% E29 Y46
CRT_VSYNC R69 1 VSYNC CRT_TVO_IREF PEG_TX_11 +3VS
18 CRT_VSYNC 2 L29 AA36
30.1_0402_1% CRT_VSYNC PEG_TX_12
AA39
PEG_TX_13
AD42
PEG_TX_14
1

AD46
PEG_TX_15

1
+3VS
R70
1.02K_0402_1%
// @ R71
4.02K_0402_1%
CANTIGA ES_FCBGA1329
B B
2

@ R72 1 2
9 CFG16

2
CFG5 4.02K_0402_1%
9 CFG5
p:

1
@ R73 1 2
9 CFG19
@ R74 4.02K_0402_1%
2.21K_0402_1%
@R75 1 2
9 CFG20
4.02K_0402_1%

2
tt

For 3G For 3G 9 CFG11


@R76 1 2
h

2.21K_0402_1%

WWAN 19 LVDS_ACLK+
LVDS_ACLK+ 1
@
WWAN19 LVDS_BCLK+
LVDS_BCLK+ 1
@
9 CFG12
@ R77 1 2
2.21K_0402_1%
C60 C1500
LVDS_ACLK- 0.1U_0402_10V6K LVDS_BCLK- 0.1U_0402_10V6K @ R78 1 2
19 LVDS_ACLK- 2 19 LVDS_BCLK- 2 9 CFG13
19 LVDS_A0+ LVDS_A0+ 1 19 LVDS_B0+ LVDS_B0+ 1 2.21K_0402_1%
@ @ @R79 1 2
9 CFG6
C61 C1501 2.21K_0402_1% @R80 1 2
LVDS_A0- 0.1U_0402_10V6K LVDS_B0- 0.1U_0402_10V6K 9 CFG14
19 LVDS_A0- 19 LVDS_B0- 2.21K_0402_1%
LVDS_A1+ 2 LVDS_B1+ 2 @ R81 1 2
19 LVDS_A1+ 1 19 LVDS_B1+ 1 9 CFG7
@ @ 2.21K_0402_1% @R82 1 2
9 CFG15
C62 C1502 2.21K_0402_1%
LVDS_A1- 0.1U_0402_10V6K LVDS_B1- 0.1U_0402_10V6K @R83 1 2
19 LVDS_A1- 2 19 LVDS_B1- 2 9 CFG8
LVDS_A2+ 1 LVDS_B2+ 1 2.21K_0402_1%
19 LVDS_A2+ 19 LVDS_B2+
@ @
C63 C1503 @R84 1 2 @R85 1 2
0.1U_0402_10V6K 0.1U_0402_10V6K 9 CFG9 9 CFG17
LVDS_A2- LVDS_B2- 2.21K_0402_1% 2.21K_0402_1%
19 LVDS_A2- 2 19 LVDS_B2- 2
A @R86 @R87 A
9 CFG10 1 2 9 CFG18 1 2
2.21K_0402_1% 2.21K_0402_1%

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/08/28 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga(3/6)-VGA/LVDS/TV
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Montevina UMA 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 18, 2009 Sheet 11 of 46
5 4 3 2 1
5 4 3 2 1

+3VS_DAC_BG +3VS **RED Mark: Means UMA & dis@ Power select**
~It check by INTEL Graphics Disable Guidelines~
R88
1 2
+VCCP +1.05VS_DPLLA +VCCP

0.022U_0402_16V7K
BLM18PG181SN1D_0603
+VCCP

0.1U_0402_16V4Z

10U_0805_10V4Z
+V1.05VS_AXF
1 1 1 U2H 1 2 R93
C68

C69

C70
R90 1 2

0.1U_0402_16V4Z

10U_0805_10V4Z

10U_0805_10V4Z

1U_0603_10V4Z
852mA U13 10U_FLC-453232-100K_0.25A_10% 0_0603_5%
VTT

4.7U_0805_10V4Z

C73

C74
73mA T13 1 1 1
2 2 2 VTT

220U_D2_4VM
B27 U12 1 1 1
VCCA_CRT_DAC VTT

C71

C72

C78

C79
A26 T12 +
+3VS_DAC_CRT VCCA_CRT_DAC VTT
U11
2.68mA VTT 2 2
T11
VTT 2 2 2 2
+3VS_DAC_BG A25 U10

CRT
VCCA_DAC_BG VTT
B25 T10
VSSA_DAC_BG VTT
D
+3VS_DAC_CRT U9 D
+3VS VTT
T9
R91 VTT
U8
64.8mA VTT
1 2 +1.05VS_DPLLA F47
VCCA_DPLLA VTT
T8
0.022U_0402_16V7K

0.47U_0603_10V7K

4.7U_0805_10V4Z

2.2U_0805_16V4Z
BLM18PG181SN1D_0603 U7

VTT
VTT +1.8V_SM_CK
0.1U_0402_16V4Z

+1.05VS_DPLLB L48 64.8mA T7 1 1 1 +1.8V

PLL
VCCA_DPLLB VTT +1.05VS_DPLLB +VCCP
C75

C76

1 1 U6 R95
VTT

0.1U_0402_16V4Z
C80

C81

C82
+1.05VS_HPLL AD1 24mA T6 R94 1 2
VCCA_HPLL VTT

10U_0805_10V4Z

10U_0805_10V4Z
U5 1 2 0_0805_5%
VTT 2 2 2

0.1U_0402_16V4Z
+1.05VS_MPLL AE1 139.2mA T5 10U_FLC-453232-100K_0.25A_10% @ 1 1 1
2 2 VCCA_MPLL VTT

C86

C87

10U_0805_10V4Z

C84

C85
V3
13.2mA VTT
U3 1 1

A LVDS
VTT

C83
+1.8V_TXLVDS J48 VCCA_LVDS VTT V2
U2 2 2 2
1 VTT
C88 J47 T2
VSSA_LVDS VTT 2 2
VTT V1
@ R96 1000P_0402_50V7K 414uA U1
2 VTT
+3VS 1 2
0_0603_5% AD48
+1.5VS_PEG_BG VCCA_PEG_BG
R97

A PEG
+1.5VS 1 2 +1.5VS_TVDAC
0_0603_5% 50mA +1.05VS_HPLL +VCCP +1.5VS

/
1 +1.05VS_PEGPLL AA48 R98 R99
C89 VCCA_PEG_PLL
1 2 1 2

0.022U_0402_16V7K

0.1U_0402_16V4Z
MBK2012121YZF_0805 0_0805_5%

/x
0.1U_0402_16V4Z AR20
2 VCCA_SM

0.1U_0402_16V4Z

10U_0805_10V4Z
AP20 VCCA_SM 1 1 1 1

C90

C91
AN20 720mA
VCCA_SM
POWER

C92

C93
AR17 VCCA_SM
AP17 VCCA_SM
+VCCP AN17 2 2 2 2
+1.05VS_A_SM VCCA_SM
AT16 VCCA_SM

su
R100 AR16 VCCA_SM

A SM
C
1 2 AP16 VCCA_SM C
10U_0805_10V4Z

1 0_0805_5%
1 1 1
C94

C95

+ C96 C97
+VCC_PEG +VCCP
220U_D2_4VM 4.7U_0805_10V4Z

p.
2 2 2 2 321.35mA +1.05VS_MPLL +VCCP R102
1U_0603_10V4Z AP28 R101 1 2
VCCA_SM_CK 0_0805_5%
AN28 B22 +V1.05VS_AXF 1 2
VCCA_SM_CK VCC_AXF

10U_0805_10V4Z
AP25 26mA B21 MBK2012121YZF_0805 1

AXF
+1.05VS_A_SM_CK VCCA_SM_CK VCC_AXF

220U_D2_4VM
R103 AN25 A21 1
VCCA_SM_CK VCC_AXF

om

C101
1 2 AN24 26mA +
VCCA_SM_CK 1 1
1U_0603_10V4Z

0.1U_0402_16V4Z

C98
0_0603_5% AM28 124mA C99 C100
VCCA_SM_CK_NCTF
10U_0805_10V4Z

AM26
VCCA_SM_CK_NCTF 2 2
1 1 1 1 AM25
VCCA_SM_CK_NCTF A CK 0.1U_0402_16V4Z
2 2
10U_0805_10V4Z
C103

C104

C105

C102 AL25 BF21

SM CK
VCCA_SM_CK_NCTF VCC_SM_CK +1.8V_SM_CK
AM24 BH20
1U_0603_10V4Z VCCA_SM_CK_NCTF VCC_SM_CK
AL24 BG20
2 2 2 2 VCCA_SM_CK_NCTF VCC_SM_CK
AM23 BF20
VCCA_SM_CK_NCTF VCC_SM_CK
AL23

yc
VCCA_SM_CK_NCTF 118.8mA
TVA 24.15mA
+1.05VS_PEGPLL +VCCP +1.05VS_DMI +VCCP
TVB 39.48mA VCC_TX_LVDS
K47 +1.8V_TXLVDS
B24 TVX 24.15mA L1 R104
VCCA_TV_DAC +3VS_HV
+3VS_TVDAC A24 C35 1 2 1 2
TV

VCCA_TV_DAC 105.3mA VCC_HV BLM18PG121SN1D_0603 0_0603_5%


B35
VCC_HV

0.1U_0402_16V4Z

10U_0805_10V4Z

0.1U_0402_16V4Z
A35
HV

VCC_HV
1 1

0.1U_0402_16V4Z

C106

C108
+1.5VS A32 50mA 1
HDA

VCC_HDA

C109
V48 +VCC_PEG 1
VCC_PEG

C107
1732mA U48
VCC_PEG 2 2
// V47
PEG

VCC_PEG 2
U47
D TV/CRT

58.67mA VCC_PEG 2
+1.5VS_TVDAC M25 U46
VCCD_TVDAC VCC_PEG
B +1.5VS_QDAC L28 48.363mA B
VCCD_QDAC
AH48 +1.05VS_DMI
157.2mA VCC_DMI
+1.05VS_HPLL AF1 AF48
VCCD_HPLL VCC_DMI
p:
AH47
DMI

50mA VCC_DMI
+1.05VS_PEGPLL AA47 AG47
VCCD_PEG_PLL VCC_DMI +VCCP_D
456mA
M38
LVDS

VCCD_LVDS D3 R105 R106


+1.8V_LVDS L37 A8
VTTLF

VCCD_LVDS VTTLF
tt

L1 +VCCP 2 1 1 2 1 2 +3VS_HV
60.31mA VTTLF 10_0402_5% 0_0402_5%
AB2
VTTLF CH751H-40PT_SOD323-2
0.47U_0603_10V7K

0.47U_0603_10V7K

0.47U_0603_10V7K

+3VS
1 1 1
h

C110

C111

C112

CANTIGA ES_FCBGA1329

2 2 2

+1.8V_LVDS +1.8V_TXLVDS
40 mils
R107 R108

1000P_0402_50V7K
1 2 +1.8V 1 2 +1.8V

10U_0805_10V4Z

1U_0603_10V4Z
0_0603_5% 0_0603_5%

C116
+1.5VS_QDAC 1 1 1
+1.5VS

C113

C114
+3VS_TVDAC +3VS
R111 R112
1 2 1 2 2 2 2
0.022U_0402_16V7K

0.022U_0402_16V7K

BLM18PG181SN1D_0603 100_0603_1%
A A
0.1U_0402_16V4Z

0.1U_0402_16V4Z
C117

C118

C119

C120

1 1 1 1

2 2 2 2

Security Classification
2007/08/28
Compal Secret Data
2006/03/10 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga(4/6)-PWR
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom Montevina UMA 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 18, 2009 Sheet 12 of 46
5 4 3 2 1
5 4 3 2 1

U2G +VCCP
3000mA
Extnal Graphic: 1210.34mA AP33 VCC_SM VCC_AXG_NCTF W28

integrated Graphic: 1930.4mA


AN33 VCC_SM VCC_AXG_NCTF V28
+1.8V BH32 W26 0.1U_0402_16V4Z 4.7U_0603_6.3V6M
U2F VCC_SM VCC_AXG_NCTF
BG32 VCC_SM VCC_AXG_NCTF V26
+VCCP

330U_D2E_2.5VM_R7

0.01U_0402_16V7K
BF32 W25 1 1 1
VCC_SM VCC_AXG_NCTF

10U_0805_10V4Z

10U_0805_10V4Z
1 BD32 V25 C127 C128 C129
VCC_SM VCC_AXG_NCTF
1 1 2 BC32 W24
VCC_SM VCC_AXG_NCTF

C126

C122

C130

C123
D
AG34 + BB32 V24 D
VCC VCC_SM VCC_AXG_NCTF 2 2 2
AC34 BA32 W23
VCC VCC_SM VCC_AXG_NCTF
AB34 AY32 V23
VCC 2 2 2 1 VCC_SM VCC_AXG_NCTF 0.22U_0402_10V4Z
AA34 AW32 AM21
VCC VCC_SM VCC_AXG_NCTF
Y34 AV32 AL21
VCC VCC_SM VCC_AXG_NCTF
V34 AU32 AK21
VCC VCC_SM VCC_AXG_NCTF
U34 AT32 W21
VCC 0317 change value VCC_SM VCC_AXG_NCTF
AM33 AR32 V21
VCC VCC_SM VCC_AXG_NCTF
AK33 AP32 U21
VCC VCC_SM VCC_AXG_NCTF

POWER
AJ33 AN32 AM20
VCC VCC_SM VCC_AXG_NCTF
0.22U_0402_10V4Z

0.22U_0402_10V4Z

0.1U_0402_16V4Z
AG33 BH31 AK20
VCC VCC_SM VCC_AXG_NCTF
220U_D2_4VM

10U_0805_10V4Z

1 AF33 BG31 W20

VCC CORE
VCC VCC_SM VCC_AXG_NCTF
1 1 1 1 BF31 VCC_SM VCC_AXG_NCTF U20
C131

C124

C132

C133

+ C125
AE33 VCC BG30 VCC_SM VCC_AXG_NCTF AM19
AC33 VCC BH29 VCC_SM VCC_AXG_NCTF AL19
AA33 VCC BG29 VCC_SM VCC_AXG_NCTF AK19
2 2 2 2 2 Y33 BF29 AJ19
VCC VCC_SM VCC_AXG_NCTF
W33 VCC BD29 VCC_SM VCC_AXG_NCTF AH19
V33 BC29 AG19

VCC SM
VCC VCC_SM VCC_AXG_NCTF
U33 VCC BB29 VCC_SM VCC_AXG_NCTF AF19
AH28 VCC BA29 VCC_SM VCC_AXG_NCTF AE19

/
AF28 VCC AY29 VCC_SM VCC_AXG_NCTF AB19
AC28 VCC AW29 VCC_SM VCC_AXG_NCTF AA19
AA28 VCC AV29 VCC_SM VCC_AXG_NCTF Y19

/x
AJ26 VCC AU29 VCC_SM VCC_AXG_NCTF W19
AG26 VCC AT29 VCC_SM VCC_AXG_NCTF V19
AE26 VCC AR29 VCC_SM VCC_AXG_NCTF U19
AC26 VCC AP29 VCC_SM VCC_AXG_NCTF AM17
AH25 VCC VCC_AXG_NCTF AK17
AG25 VCC BA36 VCC_SM/NC VCC_AXG_NCTF AH17
AF25 BB24 AG17

su
VCC VCC_SM/NC VCC_AXG_NCTF
AG24 VCC BD16 VCC_SM/NC VCC_AXG_NCTF AF17
C
AJ23 +VCCP BB21 AE17 C
VCC VCC_SM/NC VCC_AXG_NCTF
AH23 VCC AW16 VCC_SM/NC VCC_AXG_NCTF AC17
AF23 VCC AW13 VCC_SM/NC VCC_AXG_NCTF AB17
POWER
VCC_NCTF AM32 AT13 VCC_SM/NC VCC_AXG_NCTF Y17
T32 VCC VCC_NCTF AL32 VCC_AXG_NCTF W17

p.
VCC_NCTF AK32 6326.84mA VCC_AXG_NCTF V17

VCC GFX NCTF


VCC_NCTF AJ32 VCC_AXG_NCTF AM16
AH32 Y26 AL16
VCC_NCTF VCC_AXG VCC_AXG_NCTF
AG32 AE25 AK16
VCC_NCTF VCC_AXG VCC_AXG_NCTF
AE32 AB25 AJ16
VCC_NCTF VCC_AXG VCC_AXG_NCTF

om
AC32 SI-1 Add C for GM47 +VCCP AA25 AH16
VCC_NCTF VCC_AXG VCC_AXG_NCTF
AA32 AE24 AG16
VCC_NCTF 1U_0603_10V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z VCC_AXG VCC_AXG_NCTF
Y32 AC24 AF16
VCC_NCTF VCC_AXG VCC_AXG_NCTF
W32 AA24 AE16
VCC_NCTF VCC_AXG VCC_AXG_NCTF

330U_D2E_2.5VM_R7

330U_D2E_2.5VM_R7
U32 Y24 AC16
VCC_NCTF VCC_AXG VCC_AXG_NCTF
AM30 1 1 1 1 1 1 AE23 AB16
VCC_NCTF GM47@ C134 C136 C137 C138 VCC_AXG VCC_AXG_NCTF
AL30 AC23 AA16
VCC_NCTF + C1508 + C135 VCC_AXG VCC_AXG_NCTF
AK30 AB23 Y16
VCC_NCTF VCC_AXG VCC_AXG_NCTF

yc
AH30 AA23 W16
VCC_NCTF 2 2 2 2 VCC_AXG VCC_AXG_NCTF
AG30 AJ21 V16
VCC_NCTF 2 2 VCC_AXG VCC_AXG_NCTF
AF30 AG21 U16
VCC_NCTF 10U_0805_10V4Z VCC_AXG VCC_AXG_NCTF
AE30 AE21
VCC_NCTF VCC_AXG
AC30 AC21
VCC_NCTF VCC_AXG
AB30 AA21
VCC_NCTF VCC_AXG

m
AA30 Y21
VCC_NCTF VCC_AXG
Y30 AH20
VCC NCTF

VCC_NCTF VCC_AXG
W30 AF20
VCC_NCTF VCC_AXG

22P_0402_25V8K

22P_0402_25V8K

22P_0402_25V8K
V30 AE20
VCC_NCTF VCC_AXG
VCC_NCTF
U30 1 @ 1 @ 1 @ AC20
VCC_AXG
VCC_NCTF
VCC_NCTF
AL29
AK29
// C1490 C1491 C1492 AB20
AA20
VCC_AXG
VCC_AXG
AJ29 T17
B VCC_NCTF 2 2 2 VCC_AXG B
AH29 T16
VCC_NCTF VCC_AXG
AG29 AM15
VCC_NCTF VCC_AXG
AE29 AL15
VCC_NCTF VCC_AXG
AC29 AE15
p:

VCC_NCTF VCC_AXG
AA29 AJ15
VCC_NCTF VCC_AXG
Y29 AH15
VCC_NCTF VCC_AXG
W29 AG15
VCC_NCTF VCC_AXG
V29 AF15
VCC_NCTF VCC_AXG
AL28 AB15
tt

VCC_NCTF VCC_AXG
22P_0402_25V8K

22P_0402_25V8K

22P_0402_25V8K
AK28 AA15
VCC_NCTF VCC_AXG
AL26 1 @ 1 @ 1 @ Y15

VCC GFX
VCC_NCTF C1493 C1494 C1495 VCC_AXG
AK26 V15
VCC_NCTF VCC_AXG
AK25 U15
VCC_NCTF VCC_AXG
h

AK24 AN14
VCC_NCTF 2 2 2 VCC_AXG
AK23 AM14
VCC_NCTF VCC_AXG
U14 AV44 VCCSM_LF1
VCC_AXG VCC_SM_LF
T14 BA37 VCCSM_LF2

VCC SM LF
VCC_AXG VCC_SM_LF
AM40 VCCSM_LF3
VCC_SM_LF
AV21 VCCSM_LF4
VCC_SM_LF
AY5 VCCSM_LF5
VCC_SM_LF
Reserve for WWAN AM10 VCCSM_LF6
VCC_SM_LF
CANTIGA ES_FCBGA1329 BB13 VCCSM_LF7
VCC_SM_LF

C139 0.1U_0402_16V4Z

C140 0.1U_0402_16V4Z

C141

C142

C143

C144

C145
1 1 1 1 1 1 1

PAD T42 AJ14


VCC_AXG_SENSE
PAD T43 AH14
VSS_AXG_SENSE 2 2 2 2 2 2 2

0.22U_0603_10V7K

0.22U_0603_10V7K

0.47U_0402_6.3V6K

1U_0603_10V4Z

1U_0603_10V4Z
A A

CANTIGA ES_FCBGA1329

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/08/28 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga(5/6)-PWR/GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Montevina UMA 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 18, 2009 Sheet 13 of 46
5 4 3 2 1
5 4 3 2 1

U2J
U2I BG21 AH8
VSS VSS
L12 VSS VSS Y8
AU48 VSS VSS AM36 AW21 VSS VSS L8
AR48 VSS VSS AE36 AU21 VSS VSS E8
AL48 VSS VSS P36 AP21 VSS VSS B8
BB47 VSS VSS L36 AN21 VSS VSS AY7
AW47 VSS VSS J36 AH21 VSS VSS AU7
AN47 F36 AF21 AN7
VSS VSS VSS VSS
AJ47 B36 AB21 AJ7
VSS VSS VSS VSS
AF47 AH35 R21 AE7
D VSS VSS VSS VSS D
AD47 AA35 M21 AA7
VSS VSS VSS VSS
AB47 Y35 J21 N7
VSS VSS VSS VSS
Y47 U35 G21 J7
VSS VSS VSS VSS
T47 T35 BC20 BG6
VSS VSS VSS VSS
N47 BF34 BA20 BD6
VSS VSS VSS VSS
L47 AM34 AW20 AV6
VSS VSS VSS VSS
G47 AJ34 AT20 AT6
VSS VSS VSS VSS
BD46 AF34 AJ20 AM6
VSS VSS VSS VSS
BA46 AE34 AG20 M6
VSS VSS VSS VSS
AY46 W34 Y20 C6
VSS VSS VSS VSS
AV46 B34 N20 BA5
VSS VSS VSS VSS
AR46 VSS VSS A34 K20 VSS VSS AH5
AM46 VSS VSS BG33 F20 VSS VSS AD5
V46 VSS VSS BC33 C20 VSS VSS Y5
R46 VSS VSS BA33 A20 VSS VSS L5
P46 VSS VSS AV33 BG19 VSS VSS J5
H46 VSS VSS AR33 A18 VSS VSS H5
F46 VSS VSS AL33 BG17 VSS VSS F5
BF44 VSS VSS AH33 BC17 VSS VSS BE4
AH44 VSS VSS AB33 AW17 VSS
AD44 P33 AT17 BC3
VSS VSS VSS
VSS VSS

/
AA44 VSS VSS L33 R17 VSS VSS AV3
Y44 VSS VSS H33 M17 VSS VSS AL3
U44 VSS VSS N32 H17 VSS VSS R3

/x
T44 K32 C17 P3
M44
F44
VSS
VSS
VSS
VSS VSS
VSS
VSS
F32
C32 BA16
VSS

VSS
VSS
VSS
VSS
F3
BA2
BC43 VSS VSS A31 VSS AW2
AV43 VSS VSS AN29 AU16 VSS VSS AU2
AU43 VSS VSS T29 AN16 VSS VSS AR2
AM43 N29 N16 AP2

su
VSS VSS VSS VSS
J43 VSS VSS K29 K16 VSS VSS AJ2
C C
C43 VSS VSS H29 G16 VSS VSS AH2
BG42 VSS VSS F29 E16 VSS VSS AF2
AY42 VSS VSS A29 BG15 VSS VSS AE2
AT42 VSS VSS BG28 AC15 VSS VSS AD2
AN42 VSS VSS BD28 W15 VSS VSS AC2

p.
AJ42 VSS VSS BA28 A15 VSS VSS Y2
AE42 VSS VSS AV28 BG14 VSS VSS M2
N42 AT28 AA14 K2
VSS VSS VSS VSS
L42 AR28 C14 AM1
VSS VSS VSS VSS
BD41 AJ28 BG13 AA1
VSS VSS VSS VSS

om
AU41 AG28 BC13 P1
VSS VSS VSS VSS
AM41 AE28 BA13 H1
VSS VSS VSS VSS
AH41 AB28
VSS VSS
AD41 Y28 U24
VSS VSS VSS
AA41 P28 AN13 U28
VSS VSS VSS VSS
Y41 K28 AJ13 U25
VSS VSS VSS VSS
U41 H28 AE13 U29
VSS VSS VSS VSS
T41 F28 N13
VSS VSS VSS

yc
M41 C28 L13
VSS VSS VSS
G41 BF26 G13 AF32
VSS VSS VSS VSS_NCTF
B41 AH26 E13 AB32
VSS VSS VSS VSS_NCTF
BG40 AF26 BF12 V32
VSS VSS VSS VSS_NCTF
BB40 AB26 AV12 AJ30
VSS VSS VSS VSS_NCTF
AV40 AA26 AT12 AM29
VSS VSS VSS VSS_NCTF

m
AN40 C26 AM12 AF29
VSS VSS VSS VSS_NCTF
H40 B26 AA12 AB29

VSS NCTF
VSS VSS VSS VSS_NCTF
E40 BH25 J12 U26
VSS VSS VSS VSS_NCTF
AT39 BD25 A12 U23
VSS VSS VSS VSS_NCTF
AM39 BB25 BD11 AL20
VSS VSS VSS VSS_NCTF
AJ39
AE39
VSS
VSS
VSS
VSS
AV25
AR25
// BB11
AY11
VSS
VSS
VSS_NCTF
VSS_NCTF
V20
AC19
N39 AJ25 AN11 AL17
B VSS VSS VSS VSS_NCTF B
L39 AC25 AH11 AJ17
VSS VSS VSS VSS_NCTF
B39 Y25 AA17
VSS VSS VSS_NCTF
BH38 N25 Y11 U17
VSS VSS VSS VSS_NCTF
BC38 L25 N11
p:

VSS VSS VSS


BA38 J25 G11
VSS VSS VSS
AU38 G25 C11 BH48

VSS SCB
VSS VSS VSS VSS_SCB
AH38 E25 BG10 BH1
VSS VSS VSS VSS_SCB
AD38 BF24 AV10 A48
VSS VSS VSS VSS_SCB
AA38 AD12 AT10 C1
tt

VSS VSS VSS VSS_SCB


Y38 AY24 AJ10 A3
VSS VSS VSS VSS_SCB
U38 AT24 AE10
VSS VSS VSS
T38 AJ24 AA10 E1
VSS VSS VSS NC
J38 AH24 M10 D2
VSS VSS VSS NC
h

F38 AF24 BF9 C3


VSS VSS VSS NC
C38 AB24 BC9 B4
VSS VSS VSS NC
BF37 R24 AN9 A5
VSS VSS VSS NC
BB37 L24 AM9 A6
VSS VSS VSS NC
AW37 K24 AD9 A43
VSS VSS VSS NC
AT37 J24 G9 A44
VSS VSS VSS NC
AN37 G24 B9 B45

NC
VSS VSS VSS NC
AJ37 F24 BH8 C46
VSS VSS VSS NC
H37 E24 BB8 D47
VSS VSS VSS NC
C37 BH23 AV8 B47
VSS VSS VSS NC
BG36 AG23 AT8 A46
VSS VSS VSS NC
BD36 Y23 F48
VSS VSS NC
AK15 B23 E48
VSS VSS NC
AU36 A23 C48
VSS VSS NC
AJ6 B48
VSS NC

CANTIGA ES_FCBGA1329 CANTIGA ES_FCBGA1329


A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/08/28 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga(6/6)-PWR/GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Montevina UMA 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 18, 2009 Sheet 14 of 46
5 4 3 2 1
5 4 3 2 1

+1.8V +1.8V

V_DDR_MCH_REF
10 DDR_A_DQS#[0..7] V_DDR_MCH_REF 9,16

10 DDR_A_D[0..63] JDIMM1

2.2U_0805_16V4Z

0.1U_0402_16V4Z
1 VREF VSS 2

C146

C151
3 4 DDR_A_D5 1 1
10 DDR_A_DM[0..7] VSS DQ4
DDR_A_D4 5 6 DDR_A_D0
DDR_A_D1 DQ0 DQ5
10 DDR_A_DQS[0..7] 7 DQ1 VSS 8
9 10 DDR_A_DM0
DDR_A_DQS#0 VSS DM0 2 2
10 DDR_A_MA[0..14] 11 DQS0# VSS 12
DDR_A_DQS0 13 14 DDR_A_D6
DQS0 DQ6 DDR_A_D7
15 16
DDR_A_D2 VSS DQ7
17 18
D DDR_A_D3 DQ2 VSS DDR_A_D13 D
19 20
Layout Note: DDR_A_D8
21
DQ3
VSS
DQ12
DQ13
22 DDR_A_D12

Place near
23 24
DDR_A_D9 DQ8 VSS DDR_A_DM1
25 26
DQ9 DM1
JP3 DDR_A_DQS#1
27
29
VSS
DQS1#
VSS
CK0
28
30 M_CLK_DDR0
M_CLK_DDR0 9
DDR_A_DQS1 31 32 M_CLK_DDR#0
DQS1 CK0# M_CLK_DDR#0 9
33 34
DDR_A_D11 VSS VSS DDR_A_D15
35 36
DDR_A_D10 DQ10 DQ14 DDR_A_D14
37 38
+1.8V DQ11 DQ15
39 40
VSS VSS

330U_D2E_2.5VM_R7
41 VSS VSS 42
2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1 DDR_A_D16 43 44 DDR_A_D20
DDR_A_D17 DQ16 DQ20 DDR_A_D21
1 1 1 1 1 1 1 1 1 45 DQ17 DQ21 46
C152

C147

C153

C154

C155

C156

C148

C149

C157

C150
+ 47 48
DDR_A_DQS#2 VSS VSS
49 DQS2# NC 50 PM_EXTTS#0 9
DDR_A_DQS2 51 52 DDR_A_DM2
2 2 2 2 2 2 2 2 2 2 DQS2 DM2
53 VSS VSS 54
DDR_A_D18 55 56 DDR_A_D23
DQ18 DQ22

/
DDR_A_D19 57 58 DDR_A_D22
DQ19 DQ23
59 VSS VSS 60
DDR_A_D29 61 62 DDR_A_D28
DDR_A_D24 DQ24 DQ28 DDR_A_D25

/x
63 DQ25 DQ29 64
65 VSS VSS 66
DDR_A_DM3 67 68 DDR_A_DQS#3
DM3 DQS3# DDR_A_DQS3
69 NC DQS3 70
71 VSS VSS 72
DDR_A_D26 73 74 DDR_A_D31
DDR_A_D27 DQ26 DQ30 DDR_A_D30
75 76

su
DQ27 DQ31
77 78
C
Layout Note: 9 DDR_CKE0_DIMMA
DDR_CKE0_DIMMA 79
VSS
CKE0
VSS
NC/CKE1 80 DDR_CKE1_DIMMA
DDR_CKE1_DIMMA 9
C

Place one cap close to every 2


81 VDD VDD 82
83 NC NC/A15 84
pullup 10 DDR_A_BS2
DDR_A_BS2 85
87
BA2 NC/A14 86
88
DDR_A_MA14

resistors terminated to +0.9VS VDD VDD

p.
DDR_A_MA12 89 90 DDR_A_MA11
DDR_A_MA9 A12 A11 DDR_A_MA7
91 A9 A7 92
DDR_A_MA8 93 94 DDR_A_MA6
A8 A6
95 96
DDR_A_MA5 VDD VDD DDR_A_MA4
97 98
A5 A4

om
DDR_A_MA3 99 100 DDR_A_MA2
DDR_A_MA1 A3 A2 DDR_A_MA0
101 102
+0.9V A1 A0
103 104
DDR_A_MA10 VDD VDD DDR_A_BS1
105 106 DDR_A_BS1 10
DDR_A_BS0 A10/AP BA1 DDR_A_RAS#
10 DDR_A_BS0 107 108 DDR_A_RAS# 10
DDR_A_WE# BA0 RAS# DDR_CS0_DIMMA#
109 110 DDR_CS0_DIMMA# 9
10 DDR_A_WE# WE# S0#
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

111 112
DDR_A_CAS# VDD VDD M_ODT0
10 DDR_A_CAS# 113 114 M_ODT0 9
CAS# ODT0

yc
1 1 1 1 1 1 1 1 1 1 1 1 1 DDR_CS1_DIMMA# 115 116 DDR_A_MA13
9 DDR_CS1_DIMMA# NC/S1# NC/A13
117 118
M_ODT1 VDD VDD
9 M_ODT1 119 120
NC/ODT1 NC
121 122
2 2 2 2 2 2 2 2 2 2 2 2 2 DDR_A_D37 VSS VSS DDR_A_D32
123 124
DQ32 DQ36
C158

C159

C160

C161

C162

C163

C164

C165

C166

C167

C168

C169

C170

DDR_A_D36 125 126 DDR_A_D33


DQ33 DQ37

m
127 128
DDR_A_DQS#4 VSS VSS DDR_A_DM4
129 130
DDR_A_DQS4 DQS4# DM4
131 132
DQS4 VSS DDR_A_D34
133 134
DDR_A_D39 VSS DQ38 DDR_A_D35
135 136
DQ34 DQ39
// DDR_A_D38 137
139
DQ35
VSS
VSS
DQ44
138
140 DDR_A_D40
DDR_A_D45 141 142 DDR_A_D41
B DDR_A_D44 DQ40 DQ45 B
143 144
DQ41 VSS DDR_A_DQS#5
145 146
+0.9V Layout Note: DDR_A_DM5 147
VSS
DM5
DQS5#
DQS5
148 DDR_A_DQS5

Place these resistor


149 150
p:

DDR_A_D47 VSS VSS DDR_A_D43


151 152
DQ42 DQ46
DDR_A_BS2 1
RP29
8 1
RP30
8 DDR_A_MA14 closely JP3,all DDR_A_D46 153
155
DQ43 DQ47
154
156
DDR_A_D42

DDR_CKE0_DIMMA
DDR_A_MA12
2
3
7
6
2
3
7
6
DDR_CKE1_DIMMA
DDR_A_MA6
trace length Max=1.5" DDR_A_D49
DDR_A_D48
157
159
VSS
DQ48
VSS
DQ52
158
160
DDR_A_D52
DDR_A_D53
tt

DDR_A_MA9 DDR_A_MA7 DQ49 DQ53


4 5 4 5 161
VSS VSS
162
163 164 M_CLK_DDR1
NC,TEST CK1 M_CLK_DDR1 9
56_8P4R_0.05 56_8P4R_0.05 165 166 M_CLK_DDR#1
DDR_A_DQS#6 VSS CK1# M_CLK_DDR#1 9
167 168
DQS6# VSS
h

RP31 RP32 DDR_A_DQS6 169 170 DDR_A_DM6


DDR_A_MA8 DDR_A_MA2 DQS6 DM6
1 8 1 8 171
VSS VSS
172
DDR_A_MA5 2 7 2 7 DDR_A_MA4 DDR_A_D54 173 174 DDR_A_D51
DDR_A_MA1 DDR_A_BS1 DDR_A_D50 DQ50 DQ54 DDR_A_D55
3 6 3 6 175 176
DDR_A_MA3 DDR_A_MA0 DQ51 DQ55
4 5 4 5 177 178
DDR_A_D61 VSS VSS DDR_A_D57
179 180
56_8P4R_0.05 56_8P4R_0.05 DDR_A_D60 DQ56 DQ60 DDR_A_D56
181 182
DQ57 DQ61
183 184
RP33 RP34 DDR_A_DM7 VSS VSS DDR_A_DQS#7
185 186
DDR_A_BS0 DDR_A_MA13 DM7 DQS7# DDR_A_DQS7
1 8 1 8 187 188
DDR_A_MA10 M_ODT0 DDR_A_D59 VSS DQS7
2 7 2 7 189
DQ58 VSS
190
DDR_A_CAS# 3 6 3 6 DDR_CS0_DIMMA# DDR_A_D58 191 192 DDR_A_D62
DDR_A_WE# DDR_A_RAS# DQ59 DQ62 DDR_A_D63
4 5 4 5 193 194
CLK_SMBDATA VSS DQ63
16,17,24 CLK_SMBDATA 195 196
56_8P4R_0.05 56_8P4R_0.05 CLK_SMBCLK SDA VSS
16,17,24 CLK_SMBCLK 197 198
SCL SAO
+3VS 199 200

VSS

VSS
VDDSPD SA1

1
+0.9V

10K_0402_5%

10K_0402_5%
2.2U_0603_6.3V4Z

1 1
0.1U_0402_16V4Z

56_0404_4P2R_5% RP11 FOX_ASOA426-M4R-TR


203

204
A

R115

R116
DDR_CS1_DIMMA# 2 C171 C172 CONN@ A
3
M_ODT1 1 4
2 2

2
DDR_A_MA11

R117 56_0402_5%
1 2
SO-DIMM A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRII-SODIMM SLOT1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Montevina UMA 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 18, 2009 Sheet 15 of 46
5 4 3 2 1
5 4 3 2 1

+1.8V +1.8V
10 DDR_B_DQS#[0..7]

10 DDR_B_D[0..63] V_DDR_MCH_REF
V_DDR_MCH_REF 9,15

10 DDR_B_DM[0..7] JDIMM2

2.2U_0805_16V4Z

0.1U_0402_16V4Z
1 VREF VSS 2
3 4 DDR_B_D5 1 1
10 DDR_B_DQS[0..7] VSS DQ4
DDR_B_D0 5 6 DDR_B_D4
DQ0 DQ5

C173

C182
10 DDR_B_MA[0..14] DDR_B_D1 7 8
DQ1 VSS DDR_B_DM0
9 VSS DM0 10
DDR_B_DQS#0 11 12 2 2
DDR_B_DQS0 DQS0# VSS DDR_B_D6
13 14
DQS0 DQ6 DDR_B_D7
15 16
D DDR_B_D2 VSS DQ7 D
17 18
Layout Note: DDR_B_D3 19
DQ2
DQ3
VSS
DQ12
20 DDR_B_D12
DDR_B_D13
Place near
21 22
DDR_B_D8 VSS DQ13
23 24
DQ8 VSS
JP10 DDR_B_D9 25
27
DQ9
VSS
DM1
VSS
26
28
DDR_B_DM1

DDR_B_DQS#1 29 30 M_CLK_DDR2
DDR_B_DQS1 DQS1# CK0 M_CLK_DDR#2 M_CLK_DDR2 9
31 32
DQS1 CK0# M_CLK_DDR#2 9
33 34
DDR_B_D10 VSS VSS DDR_B_D14
35 36
DDR_B_D11 DQ10 DQ14 DDR_B_D15
37 38
+1.8V DQ11 DQ15
39 VSS VSS 40

41 VSS VSS 42
2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
DDR_B_D21 43 44 DDR_B_D16
DDR_B_D20 DQ16 DQ20 DDR_B_D17
1 1 1 1 1 1 1 1 1 45 DQ17 DQ21 46
C174

C175

C176

C183

C177

C178

C179

C180

C181
47 VSS VSS 48
DDR_B_DQS#2 49 50
DDR_B_DQS2 DQS2# NC DDR_B_DM2 PM_EXTTS#1 9
51 DQS2 DM2 52
2 2 2 2 2 2 2 2 2
53 VSS VSS 54

/
DDR_B_D19 55 56 DDR_B_D22
DDR_B_D18 DQ18 DQ22 DDR_B_D23
57 DQ19 DQ23 58
59 VSS VSS 60
DDR_B_D28 DDR_B_D29

/x
61 DQ24 DQ28 62
DDR_B_D25 63 64 DDR_B_D24
DQ25 DQ29
65 VSS VSS 66
DDR_B_DM3 67 68 DDR_B_DQS#3
DM3 DQS3# DDR_B_DQS3
69 NC DQS3 70
71 VSS VSS 72
DDR_B_D30 73 74 DDR_B_D26
Layout Note:

su
DDR_B_D31 DQ26 DQ30 DDR_B_D27
75 DQ27 DQ31 76
C C
Place one cap close to every 2
77 VSS VSS 78
DDR_CKE2_DIMMB 79 80 DDR_CKE3_DIMMB
9 DDR_CKE2_DIMMB CKE0 NC/CKE1 DDR_CKE3_DIMMB 9
pullup 81
83
VDD VDD 82
84
resistors terminated to +0.9VS 10 DDR_B_BS2
DDR_B_BS2 85
NC
BA2
NC/A15
NC/A14 86 DDR_B_MA14

p.
87 VDD VDD 88 0612 add
DDR_B_MA12 89 90 DDR_B_MA11
DDR_B_MA9 A12 A11 DDR_B_MA7
91 92
DDR_B_MA8 A9 A7 DDR_B_MA6
93 94
A8 A6
95 96
VDD VDD

om
DDR_B_MA5 97 98 DDR_B_MA4
+0.9V DDR_B_MA3 A5 A4 DDR_B_MA2
99 100
DDR_B_MA1 A3 A2 DDR_B_MA0
101 102
A1 A0
103 104
DDR_B_MA10 VDD VDD DDR_B_BS1
105 106 DDR_B_BS1 10
A10/AP BA1
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

DDR_B_BS0 107 108 DDR_B_RAS#


10 DDR_B_BS0 DDR_B_WE# BA0 RAS# DDR_CS2_DIMMB# DDR_B_RAS# 10
10 DDR_B_WE# 109 110 DDR_CS2_DIMMB# 9
WE# S0#
1 1 1 1 1 1 1 1 1 1 1 1 1 111 112
VDD VDD

yc
DDR_B_CAS# 113 114 M_ODT2
10 DDR_B_CAS# DDR_CS3_DIMMB# CAS# ODT0 DDR_B_MA13 M_ODT2 9
9 DDR_CS3_DIMMB# 115 116
NC/S1# NC/A13
117 118
2 2 2 2 2 2 2 2 2 2 2 2 2 M_ODT3 VDD VDD
9 M_ODT3 119 120
NC/ODT1 NC
C184

C185

C186

C187

C188

C189

C190

C191

C192

C193

C194

C195

C196

121 122
DDR_B_D32 VSS VSS DDR_B_D36
123 124
DQ32 DQ36

m
DDR_B_D37 125 126 DDR_B_D33
DQ33 DQ37
127 128
DDR_B_DQS#4 VSS VSS DDR_B_DM4
129 130
DDR_B_DQS4 DQS4# DM4
131 132
DQS4 VSS DDR_B_D39
133 134
VSS DQ38
// DDR_B_D34
DDR_B_D35
135
137
DQ34
DQ35
DQ39
VSS
136
138
DDR_B_D38

139 140 DDR_B_D44


B
Layout Note: DDR_B_D40
DDR_B_D41
141
VSS
DQ40
DQ44
DQ45
142 DDR_B_D45 B

Place these resistor


143 144
+0.9V DQ41 VSS DDR_B_DQS#5
145 146
VSS DQS5#
closely JP3,all
+0.9V DDR_B_DM5 147 148 DDR_B_DQS5
p:

RP35 DM5 DQS5


149 150

56_0404_4P2R_5% RP14
1
2
8
7
DDR_B_MA14
DDR_B_MA11
trace length Max=1.5" DDR_B_D42
DDR_B_D43
151
153
VSS
DQ42
VSS
DQ46
152
154
DDR_B_D46
DDR_B_D47
DDR_B_MA3 DDR_B_MA7 DQ43 DQ47
1 4 3 6 155
VSS VSS
156
DDR_B_MA1 2 3 4 5 DDR_B_MA6 DDR_B_D48 157 158 DDR_B_D52
tt

DDR_B_D49 DQ48 DQ52 DDR_B_D53


159 160
56_8P4R_0.05 DQ49 DQ53
161 162
56_0404_4P2R_5% RP16 VSS VSS M_CLK_DDR3
163 164 M_CLK_DDR3 9
DDR_B_BS0 RP36 NC,TEST CK1 M_CLK_DDR#3
1 4 165 166 M_CLK_DDR#3 9
VSS CK1#
h

DDR_B_MA10 2 3 1 8 DDR_B_MA4 DDR_B_DQS#6 167 168


DDR_B_MA2 DDR_B_DQS6 DQS6# VSS DDR_B_DM6
2 7 169
DQS6 DM6
170
3 6 DDR_B_BS1 171 172
56_0404_4P2R_5% RP24 DDR_B_MA0 DDR_B_D54 VSS VSS DDR_B_D50
4 5 173 174
DDR_CS3_DIMMB# 2 DDR_B_D55 DQ50 DQ54 DDR_B_D51
3 175 176
M_ODT3 56_8P4R_0.05 DQ51 DQ55
1 4 177 178
DDR_B_D60 VSS VSS DDR_B_D56
179 180
RP37 DDR_B_D61 DQ56 DQ60 DDR_B_D57
181 182
DDR_CKE3_DIMMB 1 DDR_B_RAS# DQ57 DQ61
2 1 8 183
VSS VSS
184
R120 56_0402_5% 2 7 DDR_CS2_DIMMB# DDR_B_DM7 185 186 DDR_B_DQS#7
M_ODT2 DM7 DQS7# DDR_B_DQS7
3 6 187
VSS DQS7
188
4 5 DDR_B_MA13 DDR_B_D63 189 190
DDR_B_D58 DQ58 VSS DDR_B_D59
191 192
56_8P4R_0.05 DQ59 DQ62 DDR_B_D62
193 194
CLK_SMBDATA VSS DQ63
15,17,24 CLK_SMBDATA 195 196
RP38 CLK_SMBCLK SDA VSS R118
15,17,24 CLK_SMBCLK 197 198
DDR_B_BS2 SCL SA0
1 8 +3VS 199 200 1 2 +3VS

VSS

VSS
DDR_CKE2_DIMMB VDDSPD SA1
2 7

1
10K_0402_5%
0.1U_0402_16V4Z

DDR_B_MA9
2.2U_0603_6.3V4Z

3 6 1 1 10K_0402_5%

R119
A DDR_B_MA12 FOX_AS0A426-N8RN-7F A
4 5
201

202
C197 C198 CONN@
56_8P4R_0.05
2 2

2
RP39
1
2
3
8
7
6
DDR_B_MA8
DDR_B_MA5
DDR_B_WE#
SO-DIMM B
4 5 DDR_B_CAS# Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title
56_8P4R_0.05
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRII-SODIMM SLOT2
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina UMA 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 18, 2009 Sheet 16 of 46
5 4 3 2 1
5 4 3 2 1

FSC FSB FSA CPU SRC PCI REF DOT_96 USB +3VS
R121
+3VS_CK505

CLKSEL2 CLKSEL1 CLKSEL0 MHz MHz MHz MHz MHz MHz 1 2


1 1 1 1 1 1 1 1
0_0805_5% C199 C200 C201 C202 C203 C204 C205 C1496
0 0 0 266 100 33.3 14.318 96.0 48.0 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 47P_0402_50V8J
2 2 2 2 2 2 2 2
0 0 1 133 100 33.3 14.318 96.0 48.0
Routing the trace at least For WWAN
0 1 0 200 100 33.3 14.318 96.0 48.0 10mil CLK_XTAL_OUT
+VCCP +1.05VS_CK505

Place close to U3
D
0 1 1 166 100 33.3 14.318 96.0 48.0 CLK_XTAL_IN R122
1 2 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z 47P_0402_50V8J
D

Y1 0_0805_5% 1 1 1 1 1 1 1 1 1
1 0 0 333 100 33.3 14.318 96.0 48.0 1 2
14.318MHZ_16PF_7A14300083
C206 C207 C208 C209 C210 C211 C212 C1506 C1507

1 0 1 100 100 33.3 14.318 96.0 48.0 2


10U_0805_10V4Z
2 2
0.1U_0402_16V4Z
2 2
0.1U_0402_16V4Z
2 2
0.1U_0402_16V4Z
2 2
47P_0402_50V8J
2 2
1 1 0 400 100 33.3 14.318 96.0 48.0 C213
18P_0402_50V8J
C214
18P_0402_50V8J
For WWAN
1 1 1 Reserved 1 1

R123 +3VS_CK505 +1.05VS_CK505


1 2 +VCCP
1

56_0402_5%
CLRP1

/
NO SHORT PADS R126 1 2 475_0402_1% R_CLKREQ#_7
9 CLKREQ#_7 CLK_MCH_3GPLL 9
3G_PLL
2

R128
NB
FSA 9 CLK_MCH_BCLK# R_CLKREQ#_6 CLK_MCH_3GPLL# 9
1 2 1 2 R133 1 2 475_0402_1%
MCH_CLKSEL0 9 9 CLK_MCH_BCLK CLKREQ#_6 26
2.2K_0402_5% R129

/x
CPU MiniCard_2(WLAN)
6 CLK_CPU_BCLK# CLK_PCIE_MCARD2 26
R138 1K_0402_5%
6 CLK_CPU_BCLK CLK_PCIE_MCARD2# 26
7 CPU_BSEL0 1 2 +3VS_CK505
0_0402_5%
1

72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
R139 U3

su
1K_0402_5% +3VS_CK505 +1.05VS_CK505

VDD_CPU_IO

VDD_SRC_IO
CPU_0
CPU_0#

CPU_1
CPU_1#

CLKREQ_7#

SRC_8#/CPU_ITP#

SRC_7
SRC_7#

CLKREQ_6#
SRC_6
SRC_6#
SRC_8/CPU_ITP
VDD_CPU

VSS_CPU

VSS_SRC

VDD_SRC
C C
2

@ R141 1 2 0_0402_5%
22,42 VGATE @ R142 1 2 0_0402_5%
+VCCP 42 CLK_ENABLE# R140 1 2 0_0402_5% R_CKPWRGD 1 54 H_STP_PCI#
CKPWRGD/PD# PCI_STOP# H_STP_PCI# 22

p.
22 CK_PWRGD FSB 2 53 H_STP_CPU#
FS_B/TEST_MODE CPU_STOP# H_STP_CPU# 22
3 VSS_REF VDD_SRC_IO 52
2

@ CLK_XTAL_OUT 4 51
MiniCard_0
CLK_XTAL_IN XTAL_OUT SRC_10# CLK_PCIE_MCARD0# 26
R143 5 50
XTAL_IN SRC_10 R_CLKREQ#_10 CLK_PCIE_MCARD0 26
1K_0402_5% 6 49 R146 1 2 475_0402_1%
VDD_REF CLKREQ_10# CLKREQ#_10 26

om
R147 1 2 33_0402_1% FSC 7 48
22 CLK_14M_ICH REF1 REF_0/FS_C/TEST_ SRC_11
8 47
1

FSB T44 CLK_SMBDATA REF_1 SRC_11#


1 2 MCH_CLKSEL1 9 15,16,24 CLK_SMBDATA 9
SDA CLKREQ_11#
46
R150 CLK_SMBCLK 10 45
LAN
15,16,24 CLK_SMBCLK SCL SRC_9# CLK_PCIE_LAN# 25
R154 1K_0402_5% 11 44
NC SRC_9 R_CLKREQ#_9 CLK_PCIE_LAN 25
1 2 12 43 R738 1 2 475_0402_1%
7 CPU_BSEL1 VDD_PCI CLKREQ_9# CLKREQ#_9 25
0_0402_5% R393 1 2 39_0402_1% PCI2_1 13 42
PCI_1 VSS_SRC
1

26 CLK_DEBUG_PORT_1 T83 PCI2_TME 14 41 R_CLKREQ#_4 R156 1 2 475_0402_1%


PCI_2 CLKREQ_4# CLKREQ#_4 26

yc
@ R158 1 2 33_0402_1% 27_SEL 15 40
New Card
32 CLK_PCI_EC PCI_CLK3 PCI_3 SRC_4# CLK_PCIE_NCARD# 26
R157 16 39
PCI_4/SEL_LCDCL SRC_4 CLK_PCIE_NCARD 26

USB_1/CLKREQ_A#
0_0402_5% R161 1 2 33_0402_1% ITP_EN 17 38

LCDCLK#/27M_SS
20 CLK_PCI_ICH PCIF_5/ITP_EN VDD_SRC_IO

SRC_0#/DOT_96#
18 37 R_CLKREQ#_C R162 1 2 475_0402_1% CLKREQ#_C 22
2

VSS_PCI CLKREQ_3#

SRC_0/DOT_96

VDD_PLL3_IO
LCDCLK/27M
USB_0/FS_A

VDD_PLL3
m

VSS_PLL3

VSS_SRC
73
+VCCP thm_pad

VDD_48

SRC_2#

SRC_3#
VDD_IO
VSS_48

VSS_IO

SRC_2

SRC_3
1

@
R163
// SLG8SP553VTR_QFN72_10x10

19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
1K_0402_5% SI-1 Using USB_0 for CLK_48M_CR +3VS_CK505

B R164 B

SATA
CLK_PCIE_SATA# 21
2

FSC 1 2 1 2 R167 1 2 22_0402_1% FSA


MCH_CLKSEL2 9 22 CLK_48M_ICH CLK_PCIE_SATA 21
10K_0402_5% R165 R1101 1 2 22_0402_1%
R171 1K_0402_5% 27 CLK_48M_CR
p:

ICH
CLK_PCIE_ICH# 22
7 CPU_BSEL2 1 2 +1.05VS_CK505 CLK_PCIE_ICH 22
0_0402_5% +1.05VS_CK505
1

NB
9 CLK_MCH_DREFCLK
@
R174
(UMA)
9 CLK_MCH_DREFCLK# MCH_SSCDREFCLK# 9
MCH_SSCDREFCLK 9 NB_SSC (UMA)
tt

0_0402_5%
2

+3VS
h

+3VS

0= EMI
ITP_EN SRC8/SRC8#
1= +3VS
R178 R179
0ITP/ITP#
= Enable DOT96 & @ C1482 2 1 CLK_48M_CR

PCI_CLK3 SRC1(UMA)
1 = Enable SRC0 &
2.2K_0402_5% 2.2K_0402_5% 5P_0402_50V8C
@ C215 2 1 CLK_48M_ICH
2

Q3A 5P_0402_50V8C
27MHz(DIS) 22,26 ICH_SMBDATA 6 1 CLK_SMBDATA
C216
12P_0402_50V8J
2 1 CLK_14M_ICH

+3VS +3VS @ C217 2 1 CLK_PCI_ICH


SB, MINI
5

Q3B 2N7002DW-7-F_SOT363-6 47P_0402_50V8J

PCI22,26 ICH_SMBCLK
@ C218 2 1 CLK_PCI_EC
1

@ 3 4 CLK_SMBCLK 47P_0402_50V8J
R180 R181 @ C219 2 1 CLK_DEBUG_PORT_1
10K_0402_5% 10K_0402_5% 2N7002DW-7-F_SOT363-6 47P_0402_50V8J
A A
2

ITP_EN PCI_CLK3
Install C217,C218,C219 for WWAN
noise
1

@
R182 R183
10K_0402_5% 10K_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/28 Deciphered Date 2006/03/10 Title
Clock Generator CK505
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina UMA 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 18, 2009 Sheet 17 of 46
5 4 3 2 1
A B C D E

BLUE
GREEN
RED
Place close to
@ D5 @ D6 @ D7 JCRT1

1
1 +5VS +RCRT_VCC +CRTVDD 1

DAN217T146_SC59-3

DAN217T146_SC59-3

DAN217T146_SC59-3
W=40mils
D4 F1
2 1 1 2
1
RB491D_SC59-3 1.1A_6VDC_FUSE

3
+CRTVDD
0.1U_0402_16V4Z
C220 2
JCRT1
6
11
RED 1
7
12
GREEN 2
8
13
BLUE 3
9
14

/
4 16
+5VS +5VS 10 17
15
C221 C222

/x
5
0.1U_0402_16V4Z 0.1U_0402_16V4Z
1 2 1 2 SUYIN_070546FR015S263ZR
CONN@
+3VS
+CRTVDD +CRTVDD +3VS
5
1

U4

su
SN74AHCT1G125GW_SOT353-5 R184
OE#
P

1
1
2 CRT_HSYNC HSYNC_G_A D_HSYNC 2
11 CRT_HSYNC 2 A Y 4 1 2 0_0603_5%
R185 R186 R187 R188
G

5
1

2.2K_0402_5% 2.2K_0402_5%

2
R189 2.2K_0402_5% 2.2K_0402_5%
OE#
P
3

CRT_VSYNC 2 4 VSYNC_G_A 1 2 0_0603_5% D_VSYNC


11 CRT_VSYNC

2
2
A Y

p.
D_DDCDATA 6 1 3VDDCDA
3VDDCDA 11
G

U5 1 @ 1 @
SN74AHCT1G125GW_SOT353-5 C223 C224
3

Q5A

5
5P_0402_50V8C 5P_0402_50V8C 2N7002DW-7-F_SOT363-6

om
2 2 D_DDCCLK 3 4 3VDDCCL
3VDDCCL 11

Q5B
2N7002DW-7-F_SOT363-6

yc
m
CRT Termination/EMI Filter //
3 3
p:

C_RED L2 1 2 RED
11 M_RED
HLC0603CSCCR11JT_0603
tt

C_GRN L3 1 2 GREEN
11 M_GREEN
HLC0603CSCCR11JT_0603
h

C_BLU L4 1 2 BLUE
11 M_BLUE
HLC0603CSCCR11JT_0603
22P_0402_50V8J

22P_0402_50V8J

22P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J
1

1
150_0402_1%

150_0402_1%

150_0402_1%

1 1 1 1 1 1
R195

R196

R197
2

2 2 2 2 2 2

@ C225 @ C226 @ C227 C228 C229 C230

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/08/28 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT Connector
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina UMA 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 18, 2009 Sheet 18 of 46
A B C D E
5 4 3 2 1

+3VS +LCDVDD INVPWR_B+

C235 C236 C237


LVDS CONN & USB Camera + Dig Mic
680P_0402_50V7K

680P_0402_50V7K

680P_0402_50V7K
D D

1
+LCDVDD +3VS
+LCDVDD +5VALW Q7
2

2
2 SI2301BDS-T1-E3_SOT23-3
JLVDS1

1
1 2 LVDS_A2- +LCDVDD 1 3

S
D
1 2 LVDS_A2- 11

4.7U_0805_10V4Z
3 4 LVDS_A2+ BKOFF# 1
3 4 LVDS_A2+ 11
5 6 LVDS_A1- R198 R199
5 6 LVDS_A1+ LVDS_A1- 11
7 8 100_0805_5% 1M_0402_5% C233 1

G
LVDS_A1+ 11

2
7 8

2
9 10 LVDS_A0- 4.7U_0805_10V4Z
LVDS_A0- 11

6 2

2
9 10 LVDS_A0+ @ R245 2 C234
11 11 12 12 LVDS_A0+ 11 1 1
USB20_P4 13 14 LVDS_ACLK- 10K_0402_5% C231 C232
22 USB20_P4 USB20_N4 13 14 LVDS_ACLK+ LVDS_ACLK- 11 2
22 USB20_N4 15 15 16 16 LVDS_ACLK+ 11
17 18 0.1U_0402_16V4Z 0.1U_0402_16V4Z R200

1
+3VS 17 18 2 2
19 19 20 20 2 2 1
21 21 22 22
LVDS_BCLK+ 23 24 DMIC_DAT 2N7002DW-7-F_SOT363-6 100K_0402_5%
11 LVDS_BCLK+ DMIC_DAT 28

1
LVDS_BCLK- 23 24 DMIC_CLK C238
11 LVDS_BCLK- 25 25 26 26 DMIC_CLK 28 Q8A
27 28 +3V_LOGO R727 1 2 +5VS
27 28

/
LVDS_B0+ 29 30 100_0805_5% 2 1 INV_PWM 0.047U_0402_16V7K
11 LVDS_B0+ LVDS_B0- 29 30 BKOFF# INV_PWM 32
31 32 @ R1237 0_0402_5%
Limited Current < 1A
11 LVDS_B0- 31 32 BKOFF# 32

3
LVDS_B1+ 33 34
11 LVDS_B1+ LVDS_B1- 33 34

/x
11 LVDS_B1- 35 35 36 36 +USB_CAM
LVDS_B2+ 37 38 DDC2_CLK Q8B
11 LVDS_B2+ LVDS_B2- 37 38 DDC2_DATA DDC2_CLK 11
39 40 5 2N7002DW-7-F_SOT363-6
11 LVDS_B2- 39 40 DDC2_DATA 11 11 ENAVDD
41 GND GND 42

4
ACES_88242-4001 2 1 R201
NB_BKLT_CTRL 11
CONN@ R1238 0_0402_5% 100K_0402_5%

su
C C
1

2
+5VALW
C434
D61 680P_0402_50V7K
4 VIN IO1 2 USB20_N4 2
Avoid Panel display garbage after power on.

p.
USB20_P4 3 1
IO2 GND
PRTR5V0U2X_SOT143-4
EMI request.

om
B+ INVPWR_B+
LVDS_ACLK+
LVDS_ACLK-
@ C1399 1
@ C1400 1
2
2
100P_0402_50V8J
100P_0402_50V8J +3VS Must close JLVDS1pin 24、26 @
L5 1 2 0_0805_5%
DDC2_CLK @ C1401 1 2 100P_0402_50V8J
DDC2_DATA @ C1402 1 2 100P_0402_50V8J DMIC_CLK

yc
LVDS_BCLK+ @ C1504 1 2 100P_0402_50V8J L6 1 2
LVDS_BCLK- @ C1505 1 2 100P_0402_50V8J DMIC_DAT FBMA-L11-201209-221LMA30T_0805
2

R202 R203 1 1
EMI request 2.2K_0402_5% 2.2K_0402_5% @ C302 @ C303

m
220P_0402_25V8J 220P_0402_25V8J
1

DDC2_CLK 2 2
DDC2_DATA

EMI reserver
//
B B
p:

USB Camera
tt

+5VS +USB_CAM
h

U42
1

1 5 R1091
IN OUT 215K_0603_1%
2
GND
1
2

3 4 C1391
SHDN BYP
2

1
1

C1392 R440 G916-390T1UF_SOT23-5 10U_0805_6.3V6M


10U_0805_6.3V6M 0_0402_5% R1093 2
100K_0402_1%
2
1

A
+USB_CAM is +3.9VS, R1091:215K; R1093:100Kohm +USB_CAM=1.25(1+R1091/R1093) A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/08/28 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LCD CONN.
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina UMA 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 18, 2009 Sheet 19 of 46
5 4 3 2 1
5 4 3 2 1

+3VS

R274 1 2 8.2K_0402_5% PCI_TRDY#

R275 1 2 8.2K_0402_5% PCI_FRAME#

R277 1 2 8.2K_0402_5% PCI_IRDY#

R278 1 2 8.2K_0402_5% PCI_SERR# U12B


D11 F1 PCI_REQ0#
R279 1 PCI_PERR# AD0 REQ0# PCI_GNT0#
2 8.2K_0402_5% C8
AD1 GNT0#
G4
D PCI_REQ1# D
D9
E12
AD2 PCI REQ1#/GPIO50
B6
A7
+3VS AD3 GNT1#/GPIO51 PCI_REQ2#
E9 F13
AD4 REQ2#/GPIO52
C9 F12
AD5 GNT2#/GPIO53 PCI_REQ3#
E10 E6
R281 1 PCI_PIRQA# AD6 REQ3#/GPIO54 PCI_GNT3#
2 8.2K_0402_5% B7
AD7 GNT3#/GPIO55
F6
C7
R283 1 PCI_PIRQC# AD8
2 8.2K_0402_5% C5 D8

R284 1 2 8.2K_0402_5% PCI_PIRQD#


G11
F8
AD9
AD10
C/BE0#
C/BE1#
B4
D6
Place closely pin D4
AD11 C/BE2#
F11 A5
R286 1 PCI_PIRQF# AD12 C/BE3# CLK_PCI_ICH
2 8.2K_0402_5% E7 AD13
A3 D3 PCI_IRDY#
AD14 IRDY#

1
R288 2 1 8.2K_0402_5% PCI_PIRQH# D2 E3 @
AD15 PAR PCI_RST# R280
F10 AD16 PCIRST# R1 PCI_RST# 32
R292 1 2 8.2K_0402_5% PCI_REQ2# D5 C6 PCI_DEVSEL# 10_0402_5%
AD17 DEVSEL# PCI_PERR#
D10 AD18 PERR# E4
R293 1 2 8.2K_0402_5% PCI_REQ3# B3 C2 PCI_PLOCK#

2
AD19 PLOCK# PCI_SERR#
F7 AD20 SERR# J4 PCI_SERR# 32
C3 A4 PCI_STOP# 1
+3VS AD21 STOP# PCI_TRDY# @
F3 AD22 TRDY# F5

/
F4 D7 PCI_FRAME# C425
R272 1 PCI_DEVSEL# AD23 FRAME#
2 8.2K_0402_5% C1 8.2P_0402_50V
AD24 PLT_RST# 2
G7 AD25 PLTRST# C14 PLT_RST# 9,25,26
R290 1 2 8.2K_0402_5% PCI_REQ1# CLK_PCI_ICH

/x
H7 AD26 PCICLK D4 CLK_PCI_ICH 17
D1 R2 PCI_PME#
PCI_STOP# AD27 PME# PCI_PME# 32
R273 1 2 8.2K_0402_5% G5 AD28
H6 AD29
R276 1 2 8.2K_0402_5% PCI_PLOCK# G1 AD30
H3 AD31

su
C C
PCI_PIRQA# J5
Interrupt I/F H4 PCI_PIRQE#
PCI_PIRQB# PIRQA# PIRQE#/GPIO2 PCI_PIRQF#
E1 PIRQB# PIRQF#/GPIO3 K6
RP28 PCI_PIRQC# J6 F2 PCI_PIRQG#
PCI_PIRQE# PCI_PIRQD# PIRQC# PIRQG#/GPIO4 PCI_PIRQH#
1 8 C4 G2 1 2 ACCEL_INT 24
PIRQD# PIRQH#/GPIO5

p.
2 7 PCI_PIRQB# R291 0_0402_5%
3 6 PCI_PIRQG# ICH9-M ES_FCBGA676
4 5 PCI_REQ0#

8.2K_0804_8P4R_5%

om
yc
m
A16 swap override Strap
//
Boot BIOS Strap
B
Low= A16 swap override Enble B

PCI_GNT3# High= Default* PCI_GNT0# SPI_CS#1 Boot BIOS Location


p:

@R294 0 1 SPI
PCI_GNT3# 1 2
tt

1K_0402_5%
1 0 PCI
h

1 1 LPC *

+3VALW

@ R295
SPI_CS1#_R 1 2
22 SPI_CS1#_R
1K_0402_5%
@ R296
PCI_GNT0# 1 2
1K_0402_5%

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/08/28 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH9(1/4)-PCI/INT
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina UMA 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 18, 2009 Sheet 20 of 46
5 4 3 2 1
5 4 3 2 1

ICH9M Internal VR Enable Strap


+RTCVCC
(Internal VR for VccSus1.05, VccSus1.5, VccCL1.5)
+3VS

SM_INTRUDER#
ICH_INTVRMEN Low = Internal VR Disabled R298
High = Internal VR Enabled(Default)
1 2
R297 1M_0402_5% GATEA20 1 2
1 2 LAN100_SLP 8.2K_0402_5%
R299 330K_0402_5%

R300
1 2
330K_0402_5%
ICH_INTVRMEN
ICH9M LAN100 SLP Strap KB_RST#
R301

(Internal VR for VccLAN1.05 and VccCL1.05)


1 2
1 2 ICH_SRTCRST# 10K_0402_5%
R302 180K_0402_5%

1
0_0402_5%

0_0402_5%
D D
1
C426 @
R303
@
R304
ICH_LAN100_SLP Low = Internal VR Disabled +VCCP

0.1U_0402_16V4Z
2
High = Internal VR Enabled(Default) H_DPRSTP#
@ R305
1 2

2
56_0402_5%
LPC_AD[0..3] 26,32
U12A @ R306
ICH_RTCX1 C23 K5 LPC_AD0 H_DPSLP# 1 2
ICH_RTCX2 RTCX1 FWH0/LAD0 LPC_AD1 56_0402_5%
C24 K4
R307 RTCX2 FWH1/LAD1 LPC_AD2
L6
ICH_RTCRST# FWH2/LAD2 LPC_AD3
+RTCVCC 1 2 A25 RTCRST# FWH3/LAD3 K2
20K_0402_5% ICH_SRTCRST# F20
SM_INTRUDER# SRTCRST# LPC_FRAME#
C22 INTRUDER# FWH4/LFRAME# K3 LPC_FRAME# 26,32
+VCCP

RTC
1

LPC
1

CLRP2 C427 ICH_INTVRMEN B22 J3


SHORT PADS LAN100_SLP INTVRMEN LDRQ0#
A22 LAN100_SLP LDRQ1#/GPIO23 J1
1U_0603_10V4Z T54 PAD
2

2
2 E25 N7 GATEA20
GLAN_CLK A20GATE H_A20M# GATEA20 32
AJ27 R308
A20M# H_A20M# 6
C13 56_0402_5%
LAN_RSTSYNC

/
AJ25 H_DPRSTP_R# R309 1 2 H_DPRSTP#
DPRSTP# H_DPSLP# H_DPRSTP# 7,9,42
F14 AE23 0_0402_5%
H_DPSLP# 7

1
LAN_RXD0 DPSLP#
G13 LAN_RXD1 R_H_FERR# R310 H_FERR#

/x
D14 LAN_RXD2 FERR# AJ26 1 2 H_FERR# 6

LAN / GLAN
56_0402_5%
D13 AD22 H_PWRGOOD
+1.5VS LAN_TXD_0 CPUPWRGD H_PWRGOOD 7
D12 LAN_TXD_1
R311 E13 AF25 H_IGNNE#
LAN_TXD_2 IGNNE# H_IGNNE# 6
24.9_0402_1% within 2" from R379
1 2 GLAN_COMP B10 AE22 H_INIT#

su
GPIO56 INIT# H_INTR H_INIT# 6 +VCCP
R312 33_0402_5% 1 2 R259 AG25

CPU
C 28 HDA_BITCLK_CODEC HDABITCLK 1 INTR KB_RST# H_INTR 6 C
2 B28 GLAN_COMPI RCIN# L3 KB_RST# 32
R207 33_0402_5% 1 2 0_0402_5% B27
9 HDA_BITCLK_NB GLAN_COMPO

1
R316 33_0402_5% 1 2 AF23 H_NMI
28 HDA_SYNC_CODEC HDA_BITCLK NMI H_SMI# H_NMI 6
AF6 AF24 R315
HDA_SYNC HDA_BIT_CLK SMI# H_SMI# 6
R208 33_0402_5% 1 2 AH4 56_0402_5%
9 HDA_SYNC_NB HDA_SYNC

p.
R317 33_0402_5% 1 2 AH27 H_STPCLK#
28,32 HDA_RST#_CODEC HDARST# STPCLK# H_STPCLK# 6
AE7

2
R209 33_0402_5% HDA_RST# THRMTRIP_ICH# R319
9 HDA_RST#_NB 1 2 AG26 1 2 54.9_0402_1% H_THERMTRIP# 6,9
HDA_SDIN0 THRMTRIP#
28 HDA_SDIN0 AF4
HDA_SDIN0
AG4
HDA_SDIN1 TP12
AG27 placed within 2"

om
HDA_SDIN2
9 HDA_SDIN2 AH3
AE5
HDA_SDIN2 from ICH9M

IHDA
HDA_SDIN3
AH11 SATA_RXN4_C 24
R321 33_0402_5% HDA_SDOUT SATA4RXN 0.01U_0402_16V7K
28 HDA_SDOUT_CODEC 1 2 AG5 AJ11 SATA_RXP4_C 24
R204 33_0402_5% HDA_SDOUT SATA4RXP SATA_TXN4_C SATA_TXN4
9 HDA_SDOUT_NB 1 2 SATA4TXN
AG12 2 1 C428 SATA_TXN4 24 ODD
PAD T55 AG7 AF12 SATA_TXP4_C 2 1 C429 SATA_TXP4
HDA_DOCK_EN#/GPIO33 SATA4TXP SATA_TXP4 24
PAD T56 AE8
HDA_DOCK_RST#/GPIO34 0.01U_0402_16V7K

yc
SATA_LED# AG8
33 SATA_LED# SATALED#
AH9 SATA_RXN5_C 30
SATA5RXN 0.01U_0402_16V7K
24 SATA_RXN0_C
0.01U_0402_16V7K
AJ16
AH16
SATA0RXN SATA5RXP
AJ9
AE10 SATA_TXN5_C 2 1 C430 SATA_TXN5
SATA_RXP5_C 30 e-SATA
P- HDD
24 SATA_RXP0_C SATA0RXP SATA5TXN SATA_TXN5 30
SATA_TXN0 C431 1 2 SATA_TXN0_C AF17 AF10 SATA_TXP5_C 2 1 C432 SATA_TXP5 De-feature disable
24 SATA_TXN0 SATA_TXP0 SATA_TXP0_C SATA0TXN SATA5TXP SATA_TXP5 30
C433 1 2 AG17 0.01U_0402_16V7K
24 SATA_TXP0 SATA0TXP

m
AH18 CLK_PCIE_SATA#
SATA_CLKN CLK_PCIE_SATA# 17

SATA
0.01U_0402_16V7K AH13 AJ18 CLK_PCIE_SATA
SATA1RXN SATA_CLKP CLK_PCIE_SATA 17
AJ13 AJ7
SATA1RXP SATARBIAS# R322
AG14 AH7 1 2
SATA1TXN SATARBIAS 24.9_0402_1%
AF14
SATA1TXP
// Within 500 mils
B Add 12p on HDA_SDOUT and HDA_SDOUT SI-1 Remove SSC
ICH9-M ES_FCBGA676
B

Add 12p on HDA_BITCLK_CODE and HDA_BITCLK_NB


Reserve cap on HDA_BITCLK for WWAN noise issue
Reserve SSC for EMI
p:

HDA_SDOUT_CODEC C312 1 2 12P_0402_50V8J

HDA_SDOUT_NB C66 1 2 12P_0402_50V8J


tt

HDA_BITCLK_CODEC C316 1 2 12P_0402_50V8J

HDA_BITCLK_NB C67 1 2 12P_0402_50V8J


BATT1
h

XOR CHAIN ENTRANCE STRAP:RSVD


+3VS @ CR2032 RTC BATTERY
+RTCVCC +3VL
@ R325
1 2 HDA_SDOUT_CODEC BATT1.1
1K_0402_5% D8
@ R326 R329 W=20mils 2
1 2 ICH_RSVD 1 2 1 R330 W=20mils JBATT1
ICH_RSVD 22 ICH_RTCX1 W=20mils
1K_0402_5% 3 1 2 1
0_0402_5% W=20mils 1
2
R328 DAN202U_SC70 1K_0402_5% 2
1 3
ICH_RTCX2 C438 GND
1 2 4
GND
1
10M_0402_5% 2.2U_0603_6.3V4Z C435 ACES_85205-02001
A
ICH_RSVD HDA_SDOUT_CODEC C436
1 1
C437
2
Place near ICH9 0.1U_0402_16V4Z
CONN@ A

15P_0402_50V8J 15P_0402_50V8J
PV for ESD 2

0 0
2 2

0 1 Y2 Security Classification Compal Secret Data Compal Electronics, Inc.


1 4 Issued Date 2007/08/28 Deciphered Date 2006/03/10 Title
1 0 2 3 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH9(2/4)_LAN,HD,IDE,LPC
Size Document Number Rev
1 1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
32.768KHZ_12.5P_MC-146 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Montevina UMA 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 18, 2009 Sheet 21 of 46
5 4 3 2 1
5 4 3 2 1

+3VS +3VALW R331 1


R332 1
2 2.2K_0402_5%
2 2.2K_0402_5%
Place closely pin Place closely pin
ICH_SMBCLK
U12C
GPIO21
AF3 CLK_48M_ICH H1 CLK_14M_ICH
17,26 ICH_SMBCLK G16 SMBCLK SATA0GP/GPIO21 AH23
SIRQ ICH_SMBDATA HDDHALT_LED#
R333
1 2
10K_0402_5%
17,26 ICH_SMBDATA LINKALERT#
A13
E17
SMBDATA SMB SATA1GP/GPIO19 AF19
AE21 GPIO36 HDDHALT_LED# 33

SATA
GPIO
LINKALERT#/GPIO60/CLGPIO4 SATA4GP/GPIO36

1
1 2 PM_CLKRUN# ME_EC_CLK1 C17 AD20 GPIO37
R334 8.2K_0402_5% ME_EC_DATA1 SMLINK0 SATA5GP/GPIO37 @ R342 @ R343
B18 SMLINK1
1 2 OCP# H1 CLK_14M_ICH
+3VS ICH_RI# CLK14 CLK_48M_ICH CLK_14M_ICH 17
R335 10K_0402_5% F19 clocks AF3 10_0402_5% 10_0402_5%
THERM_SCI# RI# CLK48 CLK_48M_ICH 17
1 2

2
@ R336 8.2K_0402_5% PAD T57 SUS_STAT# R4 P1 ICH_SUSCLK T58 PAD
CLKREQ#_C XDP_DBRESET# SUS_STAT#/LPCPD# SUSCLK
1 2 6 XDP_DBRESET# G19 1 1
SYS_RESET#

1
R337 10K_0402_5% C16 SLP_S3# @ C440 @ C441
D PM_BMBUSY# PM_BMBUSY# SLP_S3# SLP_S4# SLP_S3# 29,32 D
1 2 @ R339 @ R340 M6 E16
9 PM_BMBUSY# PMSYNC#/GPIO0 SLP_S4# SLP_S5# SLP_S4# 32
@ R338 8.2K_0402_5% 10K_0402_5% 10K_0402_5% G17 4.7P_0402_50V8C 4.7P_0402_50V8C
SLP_S5# 32

SYS / GPIO
EC_SCI# EC_LID_OUT# SLP_S5# 2 2
1 2 32 EC_LID_OUT# A17
SMBALERT#/GPIO11
R341 8.2K_0402_5% C10 S4_STATE#

2
CR_CPPE# H_STP_PCI# S4_STATE#/GPIO26
1 2 17 H_STP_PCI# A14
R344 8.2K_0402_5% R345 R_STP_CPU# STP_PCI# PM_PWROK
17 H_STP_CPU# 1 2 0_0402_5% E19
STP_CPU# PWROK
G20 PM_PWROK 9,32
R346 10K_0402_5%
1 2 CR_WAKE# 1 2
R356 8.2K_0402_5% PM_CLKRUN# L4 M2 R348 1 2 0_0402_5% DPRSLPVR 9,42

Power MGT
GPIO18 CLKRUN# DPRSLPVR/GPIO16
1 2
R349 8.2K_0402_5% ICH_PCIE_WAKE# E20 B13 ICH_LOW_BAT#
HDDHALT_LED# 25,26 ICH_PCIE_WAKE# SIRQ WAKE# BATLOW#
1 2 32 SIRQ M5
SERIRQ
R350 8.2K_0402_5% THERM_SCI# AJ23 R3 PWRBTN_OUT#
GPIO20 32 THERM_SCI# THRM# PWRBTN# PWRBTN_OUT# 32
1 2
R351 8.2K_0402_5% VGATE D21 D20
GPIO21 17,42 VGATE VRMPWRGD LAN_RST# R_EC_RSMRST# 38
1 2
R352 8.2K_0402_5% R353 1 2 PAD T59 A20 D22 R_EC_RSMRST# R354 1 2 100_0402_5%
GPIO36 TP11 RSMRST# EC_RSMRST# 32
1 2 100K_0402_5% R355 1 2 10K_0402_5%
R357 8.2K_0402_5% OCP# AG19 R5 CK_PWRGD
6 OCP# GPIO1 CK_PWRGD CK_PWRGD 17
1 2 GPIO37 CR_CPPE# AH21
R358 8.2K_0402_5% R225 EC_SCI#_SB GPIO6 M_PWROK
32 EC_SCI# 1 2 0_0402_5% AG21 GPIO7 CLPWROK R6 M_PWROK 9,32
1 2 GPIO39 32 EC_SMI# EC_SMI# A21 GPIO8

/
R359 10K_0402_5% @ R226 1 2 0_0402_5% EC_SCI#_GPIO12 C12 B16 +3VS
GPIO48 GPIO12 SLP_M#
1 2 PAD T46 C21
@ R361 8.2K_0402_5% 17/14 GPIO13 CL_CLK0 R360
AE18 GPIO17 CL_CLK0 F24 CL_CLK0 9
GPIO57 GPIO18

/x
1 2 K1 B19 1 2

GPIO
GPIO18 CL_CLK1

Controller Link

0.1U_0402_16V4Z
R362 8.2K_0402_5% GPIO20 AF8 GPIO20

1
CR_WAKE# AJ22 F22 CL_DATA0 3.24K_0402_1%
DIS/UMA SCLOCK/GPIO22 CL_DATA0 CL_DATA0 9
A9 GPIO27 CL_DATA1 C19 1
PAD T47 D19 C442 R363
CLKREQ#_C GPIO28 CL_VREF0_ICH 453_0402_1%
17 CLKREQ#_C L1 SATACLKREQ#/GPIO35 CL_VREF0 C25
+3VS 1 2 GPIO38 AE19 A19 CL_VREF1_ICH

su

2
GPIO49 R364 8.2K_0402_5% GPIO39 SLOAD/GPIO38 CL_VREF1 2 NA lead free
1 2 AG22
C @ R365 10K_0402_5% @ R739 1 GPIO48 SDATAOUT0/GPIO39 CL_RST# +3VALW C
26 EXP_CPPE# 2 AF21 SDATAOUT1/GPIO48 CL_RST0# F21 CL_RST# 9
0_0402_5% GPIO49 AH24 D18
GPIO57 GPIO49 CL_RST1# R367
A8 GPIO57/CLGPIO5
@ R366 1 2 1K_0402_5% A16 XMIT_OFF 1 2
+3VS MEM_LED/GPIO24 XMIT_OFF 26
SB_SPKR GPIO10

0.1U_0402_16V4Z
28 SB_SPKR M7 SPKR GPIO10/SUS_PWR_ACK C18

p.
MCH_ICH_SYNC# AJ24 C11 GPIO14 3.24K_0402_1%

MISC
9 MCH_ICH_SYNC# MCH_SYNC# GPIO14/AC_PRESENT

1
+3VALW ICH_RSVD B21 C20 LAN_WOL_EN
21 ICH_RSVD TP3 WOL_EN/GPIO9 1
AH20 C443 R368
TP8 R370 453_0402_1%
AJ20
1 2 LINKALERT# R366 AJ21
TP9
2 1
Low TP10 +3VALW

om
R369 10K_0402_5% 2
High -->No

2
-->default
1 2 ICH_LOW_BAT# ICH9-M ES_FCBGA676 100K_0402_5%

boot
R371 8.2K_0402_5%
1 2 ICH_PCIE_WAKE# U12D
R372 1K_0402_5% PCIE_RXN1 N29 V27 DMI_RXN0
26 PCIE_RXN1 PERN1 DMI0RXN DMI_RXN0 9
1 2 ICH_RI# PCIE_RXP1 N28 V26 DMI_RXP0
WWAN
26 PCIE_RXP1 PERP1 DMI0RXP DMI_RXP0 9
R374 10K_0402_5% 26 PCIE_TXN1 C445 1 2 0.1U_0402_16V4Z PCIE_C_TXN1 P27 U29 DMI_TXN0
DMI_TXN0 9
XDP_DBRESET# PETN1 DMI0TXN
1 2 C444 1 2 0.1U_0402_16V4Z PCIE_C_TXP1 P26 U28 DMI_TXP0 D22

Direct Media Interface


26 PCIE_TXP1 PETP1 DMI0TXP DMI_TXP0 9

yc
R375 10K_0402_5% PM_PWROK 2 1 R_EC_RSMRST#
1 2 S4_STATE# L29 Y27 DMI_RXN1
PERN2 DMI1RXN DMI_RXN1 9
R376 10K_0402_5% L28 Y26 DMI_RXP1 CH751H-40PT_SOD323-2
PERP2 DMI1RXP DMI_RXP1 9
1 2 ME_EC_CLK1 M27 W29 DMI_TXN1
PETN2 DMI1TXN DMI_TXN1 9
R377 10K_0402_5% M26 W28 DMI_TXP1 DMI_TXP1 9
ME_EC_DATA1 PETP2 DMI1TXP
1 2

m
PCIE_RXN3

PCI - Express
R378 10K_0402_5% J29 AB27 DMI_RXN2
26 PCIE_RXN3 PERN3 DMI2RXN DMI_RXN2 9
1 2 GPIO10 PCIE_RXP3 J28 AB26 DMI_RXP2
WLAN
26 PCIE_RXP3 PERP3 DMI2RXP DMI_RXP2 9
R379 10K_0402_5% 26 PCIE_TXN3 C448 1 2 0.1U_0402_16V4Z PCIE_C_TXN3 K27 AA29 DMI_TXN2
DMI_TXN2 9
EC_LID_OUT# PETN3 DMI2TXN
1 2 26 PCIE_TXP3 C449 1 2 0.1U_0402_16V4Z PCIE_C_TXP3 K26
PETP3 DMI2TXP
AA28 DMI_TXP2 DMI_TXP2 9
R373 10K_0402_5%

R380
1 2
8.2K_0402_5%
EC_SMI#
25 GLAN_RXN
// GLAN_RXN
GLAN_RXP
G29
G28
PERN4 DMI3RXN
AD27
AD26
DMI_RXN3
DMI_RXP3
DMI_RXN3 9

LAN
25 GLAN_RXP PERP4 DMI3RXP DMI_RXP3 9
1 2 GPIO14 C452 1 2 0.1U_0402_16V4Z GLAN_TXN_C H27 AC29 DMI_TXN3
B 25 GLAN_TXN PETN4 DMI3TXN DMI_TXN3 9 B
R381 8.2K_0402_5% 25 GLAN_TXP C453 1 2 0.1U_0402_16V4Z GLAN_TXP_C H26 AC28 DMI_TXP3
DMI_TXP3 9
PETP4 DMI3TXP
E29 T26 CLK_PCIE_ICH#
PERN5 DMI_CLKN CLK_PCIE_ICH CLK_PCIE_ICH# 17
E28 T25
p:

Board ID
+3VS +3VS PERP5 DMI_CLKP CLK_PCIE_ICH 17
F27
F26
PETN5
PETP5 DMI_ZCOMP
AF29
AF28 DMI_IRCOMP
R382
1
24.9_0402_1%
2
Within 500 mils
DMI_IRCOMP +1.5VS
2

PCIE_RXN4 C29
26 PCIE_RXN4 PCIE_RXP4 PERN6/GLAN_RXN USB20_N0
C28 AC5
New Card USB-0 Right side(with ESATA)
26 PCIE_RXP4 USB20_N0 30
tt

PERP6/GLAN_RXP USBP0N
@ R745 @ R747 26 PCIE_TXN4 C450 1 2 0.1U_0402_16V4Z PCIE_C_TXN4 D27
PETN6/GLAN_TXN USBP0P
AC4 USB20_P0
USB20_P0 30
10K_0402_5% 10K_0402_5% 26 PCIE_TXP4 C451 1 2 0.1U_0402_16V4Z PCIE_C_TXP4 D26 AD3 USB20_N1
USB-1 Left side
PETP6/GLAN_TXP USBP1N USB20_N1 30
AD2 USB20_P1
USB20_P1 30
1

DIS/UMA 17/14 USBP1P USB20_N2


D23 AC1
USB-2 Left side
SPI_CLK USBP2N USB20_N2 30
h

D24 AC2 USB20_P2


SPI_CS0# USBP2P USB20_P2 30
2

SPI_CS1#_R F23 AA5 USB20_N3


20 SPI_CS1#_R
USB-3 Cardreader
SPI_CS1#GPIO58/CLGPIO6 USBP3N USB20_N3 27
AA4 USB20_P3
USBP3P USB20_P3 27
R746 R748 USB20_N4
D25 SPI AB2
USB-4 Camera
SPI_MOSI USBP4N USB20_P4 USB20_N4 19
10K_0402_5% 10K_0402_5% E23 AB3
SPI_MISO USBP4P USB20_N5 USB20_P4 19
AA1
USB-5 WLAN
USB20_N5 26
1

USB_OC#0 USBP5N USB20_P5


N4 AA2 USB20_P5 26
R383 1 USB_OC#1 OC0#/GPIO59 USBP5P USB20_N6
2 0_0402_5% N5 W5
USB-6 Bluetooth
30 BT_OFF OC1#/GPIO40 USBP6N USB20_N6 30
USB_OC#2 USB20_P6
WXMIT_OFF#
N6
P6
OC2#/GPIO41 USB USBP6P
W4
Y3 USB20_N7 USB20_P6 30

USB-7 Finger Printer


26 WXMIT_OFF# USB_OC#4 OC3#/GPIO42 USBP7N USB20_P7 USB20_N7 30
M1 Y2 USB20_P7 30
USB_OC#5 OC4#/GPIO43 USBP7P USB20_N8
N2 W1
USB-8
USB_OC#6 OC5#/GPIO29 USBP8N USB20_P8 USB20_N8 26
M4 W2 USB20_P8 26
USB_OC#7 OC6#/GPIO30 USBP8P USB20_N9
MiniCard(WWAN/WiMAX)
M3 V2
USB-9 Express card
USB_OC#6 USB_OC#8 OC7#/GPIO31 USBP9N USB20_P9 USB20_N9 26
1 2 +3VALW N3 V3 USB20_P9 26
USB_OC#1 R1179 USB_OC#9 OC8#/GPIO44 USBP9P
110K_0402_5%
2 N1 U5
USB_OC#2 R1180 USB_OC#10 OC9#/GPIO45 USBP10N
110K_0402_5%
2 P5
OC10#/GPIO46 USBP10P
U4
USB_OC#4 R1181 110K_0402_5%
2 USB_OC#11 P3 U1
R1182 10K_0402_5% OC11#/GPIO47 USBP11N
USBP11P U2
A USB_OC#7 USBRBIAS A
1 2 AG2
USB_OC#8 R1183 USBRBIAS
110K_0402_5%
2 AG1
Within 500 mils USBRBIAS#
1

USB_OC#9 R1184 110K_0402_5%


2
USB_OC#0 R1185 110K_0402_5%
2 ICH9-M ES_FCBGA676
R1186 10K_0402_5% R384
WXMIT_OFF# 1 2 22.6_0402_1%
USB_OC#5 R1187 110K_0402_5%
2
2

USB_OC#10 R1188 110K_0402_5%


2
USB_OC#11 R1189
R1190
110K_0402_5%
2
10K_0402_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/28 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH9(3/4)_DMI,USB,GPIO,PCIE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Montevina UMA 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 18, 2009 Sheet 22 of 46
5 4 3 2 1
5 4 3 2 1

+RTCVCC +VCCP U12E


U12F AA26 H5
VSS[001] VSS[107]
20 mils A23 VCCRTC
G3: 6uA
VCC1_05[01] A15 AA27 VSS[002] VSS[108] J23

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1634mA B15 AA3 J26
ICH_V5REF_RUN 2mA VCC1_05[02] 0.1U_0402_16V4Z 0.1U_0402_16V4Z VSS[003] VSS[109]
1 1 A6 V5REF VCC1_05[03] C15 AA6 VSS[004] VSS[110] J27

C462

C454
VCC1_05[04] D15 1 1 AB1 VSS[005] VSS[111] AC22
E15 C457 C455 AA23 K28
ICH_V5REF_SUS 2mA VCC1_05[05] VSS[006] VSS[112]
AE1 V5REF_SUS VCC1_05[06] F15 AB28 VSS[007] VSS[113] K29
2 2 L11 AB29 L13
VCC1_05[07] 2 2 VSS[008] VSS[114]
AA24 646mA L12 AB4 L15
VCC1_5_B[01] VCC1_05[08] VSS[009] VSS[115]
AA25 VCC1_5_B[02] VCC1_05[09] L14 AB5 VSS[010] VSS[116] L2
AB24 VCC1_5_B[03] VCC1_05[10] L16 AC17 VSS[011] VSS[117] L26
40 mils AB25
VCC1_5_B[04] VCC1_05[11]
L17 AC26
VSS[012] VSS[118]
L27
R387 AC24 L18 AC27 L5
+1.5VS_SB_B 10U_0805_10V4Z VCC1_5_B[05] VCC1_05[12] R385 VSS[013] VSS[119]
+1.5VS 1 2 AC25
VCC1_5_B[06] VCC1_05[13]
M11 AC3
VSS[014] VSS[120]
L7
D CHB1608U301_0603 0.01U_0402_16V7K D
1 AD24 M18 1 2 +1.5VS AD1 M12
VCC1_5_B[07] VCC1_05[14] CHB1608U301_0603 VSS[015] VSS[121]
AD25 P11 AD10 M13

CORE
1 1 1 VCC1_5_B[08] VCC1_05[15] VSS[016] VSS[122]

220U_D2_4VM
+ C459 C460 C456 AE25 P18 AD12 M14
VCC1_5_B[09] VCC1_05[16] 1 1 VSS[017] VSS[123]

C458
AE26 T11 C461 C463 AD13 M15
VCC1_5_B[10] VCC1_05[17] VSS[018] VSS[124]
AE27 T18 AD14 M16
2 2 2 2 VCC1_5_B[11] VCC1_05[18] 10U_0805_10V4Z VSS[019] VSS[125]
AE28 U11 AD17 M17
VCC1_5_B[12] VCC1_05[19] 2 2 VSS[020] VSS[126]
AE29 U18 AD18 M23
+5VS +3VS 10U_0805_10V4Z 2.2U_0603_6.3V4Z VCC1_5_B[13] VCC1_05[20] VSS[021] VSS[127]
F25 V11 AD21 M28
VCC1_5_B[14] VCC1_05[21] VSS[022] VSS[128]
G25 V12 AD28 M29
VCC1_5_B[15] VCC1_05[22] VSS[023] VSS[129]
H24 V14 AD29 N11
VCC1_5_B[16] VCC1_05[23] VSS[024] VSS[130]
1

H25 V16 AD4 N12


R386 D9 VCC1_5_B[17] VCC1_05[24] VSS[025] VSS[131]
J24 VCC1_5_B[18] VCC1_05[25] V17 +VCCP AD5 VSS[026] VSS[132] N13

VCCA3GP

22U_0805_6.3VAM
J25 VCC1_5_B[19] VCC1_05[26] V18 AD6 VSS[027] VSS[133] N14
100_0402_5% CH751H-40PT_SOD323-2 K24 1 AD7 N15
VCC1_5_B[20] C464 VSS[028] VSS[134]
K25 AD9 N16
2

VCC1_5_B[21] VSS[029] VSS[135]


L23 VCC1_5_B[22] AE12 VSS[030] VSS[136] N17
ICH_V5REF_RUN L24 R29 AE13 N18
VCC1_5_B[23] VCCDMIPLL VSS[031] VSS[137]
1 20 mils L25 VCC1_5_B[24]
2 AE14 VSS[032] VSS[138] N26
C465 M24 W23 AE16 N27
VCC1_5_B[25] 23mA VCC_DMI[1] +VCCP VSS[033] VSS[139]
M25 VCC1_5_B[26] VCC_DMI[2] Y23 AE17 VSS[034] VSS[140] P12
0.1U_0402_10V6K N23 AE2 P13
2 VCC1_5_B[27] VSS[035] VSS[141]

/
N24 VCC1_5_B[28] V_CPU_IO[1] AB23 AE20 VSS[036] VSS[142] P14
N25 48mA AC23 AE24 P15
VCC1_5_B[29] V_CPU_IO[2] VSS[037] VSS[143]

4.7U_0603_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z
P24 VCC1_5_B[30] AE3 VSS[038] VSS[144] P16
+3VS

/x
P25 VCC1_5_B[31] VCC3_3[01] AG29 1 1 1 AE4 VSS[039] VSS[145] P17
+5VALW +3VALW

C466

C467

C468
R24 2mA AJ6 AE6 P2
VCC1_5_B[32] VCC3_3[02] VSS[040] VSS[146]
R25 VCC1_5_B[33] VCC3_3[07] AC10 AE9 VSS[041] VSS[147] P23

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
R26 VCC1_5_B[34] AF13 VSS[042] VSS[148] P28
1

2 2 2
R27 VCC1_5_B[35] VCC3_3[03] AD19 1 1 1 AF16 VSS[043] VSS[149] P29

VCCP_CORE
R388 D10 T24 AF20 AF18 P4
VCC1_5_B[36] VCC3_3[04] VSS[044] VSS[150]

C469

C470

C471
T27 AG24 AF22 P7

su
10_0402_5% CH751H-40PT_SOD323-2 VCC1_5_B[37] VCC3_3[05] VSS[045] VSS[151]
T28 VCC1_5_B[38] VCC3_3[06] AC20 AH26 VSS[046] VSS[152] R11
C
T29 +3VS 2 2 2 (DMI) AF26 R12 C
2

ICH_V5REF_SUS VCC1_5_B[39] VSS[047] VSS[153]


U24 VCC1_5_B[40]
308mA AF27 VSS[048] VSS[154] R13
20 mils U25 VCC1_5_B[41] VCC3_3[08] B9 0.1U_0402_16V4Z
+1.5VS
AF5 VSS[049] VSS[155] R14
1 V24 VCC1_5_B[42] VCC3_3[09] F9 1 AF7 VSS[050] VSS[156] R15
C472 V25 G3 C473 AF9 R16
VCC1_5_B[43] VCC3_3[10] VSS[051] VSS[157]

p.
U23 VCC1_5_B[44] VCC3_3[11] G6 AG13 VSS[052] VSS[158] R17

2
PCI
0.1U_0402_10V6K W24 J2 AG16 R18
2 VCC1_5_B[45] VCC3_3[12] 2 R212 @ VSS[053] VSS[159]
W25 J7 AG18 R28
VCC1_5_B[46] VCC3_3[13] VSS[054] VSS[160]
K23 K7 0_0402_5% AG20 T12
VCC1_5_B[47] VCC3_3[14] VSS[055] VSS[161]
Y24 AG23 T13
VCC1_5_B[48] VSS[056] VSS[162]

om
Y25 AG3 T14

1
VCC1_5_B[49]
47mA VSS[057] VSS[163]
11mA AJ4 0.1U_0402_16V4Z +1.5VS AG6 T15
VCCHDA R740 VSS[058] VSS[164]
1 AG9 T16
VSS[059] VSS[165]
R389 11mA AJ3 0.1U_0402_16V4Z 1 2 180_0402_1% +3VALW C474 AH12 T17
VCCSUSHDA VSS[060] VSS[166]
+1.5VS 1 2 AJ19
VCCSATAPLL 1 AH14
VSS[061] VSS[167]
T23

1
1U_0603_10V4Z

CHB1608U301_0603 C475 AH17 B26


2 VSS[062] VSS[168]
10U_0805_10V4Z

AC8 R741 AH19 U12


VCCSUS1_05[1] VSS[063] VSS[169]
1 1 +1.5VS AC16
VCC1_5_A[01] VCCSUS1_05[2]
F17 T65
T66 2
150_0402_1% +1.5VALW AH2
VSS[064] VSS[170]
U13
C476

C477

yc
AD15 AH22 U14
0316 change design VCC1_5_A[02] VSS[065] VSS[171]
1 AD16 AH25 U15

2
VCC1_5_A[03] VSS[066] VSS[172]
C478 AE15 AD8 VCCSUS1_5_ICH_1 AH28 U16
2 2 VCC1_5_A[04] VCCSUS1_5[1] T67 VSS[067] VSS[173]
ARX

AF15 AH5 U17


1U_0603_10V4Z VCC1_5_A[05] VCCSUS1_5_ICH_2 VSS[068] VSS[174]
AG15 F18 AH8 AD23
2 VCC1_5_A[06] VCCSUS1_5[2] T68 +3VALW VSS[069] VSS[175]
AH15 AJ12 U26
VCC1_5_A[07] VSS[070] VSS[176]

m
AJ15 AJ14 U27
VCC1_5_A[08] 0.1U_0402_16V4Z VSS[071] VSS[177]
A18 AJ17 U3
VCCSUS3_3[01] VSS[072] VSS[178]

0.1U_0402_16V4Z
AC11 212mA D16 1 1 AJ8 V1
VCCPSUS

VCC1_5_A[09] VCCSUS3_3[02] VSS[073] VSS[179]


AD11 D17 B11 V13
VCC1_5_A[10] VCCSUS3_3[03] VSS[074] VSS[180]

C479

C480
AE11 E22 B14 V15
+1.5VS VCC1_5_A[11] VCCSUS3_3[04] VSS[075] VSS[181]
AF11
VCC1_5_A[12]
// 2 2
B17
VSS[076] VSS[182]
V23
ATX

1 AG10 B2 V28
C481 VCC1_5_A[13] VSS[077] VSS[183]
AG11 B20 V29
B VCC1_5_A[14] VSS[078] VSS[184] B
AH10 B23 V4
1U_0603_10V4Z VCC1_5_A[15] VSS[079] VSS[185]
AJ10 AF1 B5 V5
2 VCC1_5_A[16] VCCSUS3_3[05] VSS[080] VSS[186]
B8 W26
VSS[081] VSS[187]
AC9 1342mA C26 W27
p:

VCC1_5_A[17] VSS[082] VSS[188]


C27 W3
VSS[083] VSS[189]
AC18 E11 Y1
VCC1_5_A[18] VSS[084] VSS[190]
AC19 E14 Y28
VCC1_5_A[19] VSS[085] VSS[191]
T1 E18 Y29
VCCSUS3_3[06] VSS[086] VSS[192]
AC21 T2 E2 Y4
tt

VCC1_5_A[20] VCCSUS3_3[07] VSS[087] VSS[193]


T3 E21 Y5
VCCSUS3_3[08] +3VALW VSS[088] VSS[194]
+1.5VS G10 T4 E24 AG28
VCC1_5_A[21] VCCSUS3_3[09] VSS[089] VSS[195]
G9 T5 E5 AH6
VCC1_5_A[22] VCCSUS3_3[10] VSS[090] VSS[196]
1 11mA 11mA VCCSUS3_3[11]
T6 E8
VSS[091] VSS[197]
AF2
h

C483 AC12 U6 F16 B25


VCCPUSB

+1.5VS VCC1_5_A[23] VCCSUS3_3[12] 1 VSS[092] VSS[198]


1 AC13 U7 C482 F28
0.1U_0402_16V4Z C484 VCC1_5_A[24] VCCSUS3_3[13] VSS[093]
AC14 V6 F29
2 VCC1_5_A[25] VCCSUS3_3[14] 4.7U_0603_6.3V6M VSS[094]
V7 G12
0.1U_0402_16V4Z VCCSUS3_3[15] 2 VSS[095]
AJ5 W6 G14 A1
2 VCCUSBPLL VCCSUS3_3[16] VSS[096] VSS_NCTF[01]
W7 G18 A2
VCCSUS3_3[17] VSS[097] VSS_NCTF[02]
USB CORE

AA7 Y6 G21 A28


VCC1_5_A[26] VCCSUS3_3[18] VSS[098] VSS_NCTF[03]
AB6 Y7 G24 A29
VCC1_5_A[27] VCCSUS3_3[19] VSS[099] VSS_NCTF[04]
AB7 T7 G26 AH1
VCC1_5_A[28] VCCSUS3_3[20] VSS[100] VSS_NCTF[05]
AC6 G27 AH29
VCC1_5_A[29] VSS[101] VSS_NCTF[06]
AC7 G8 AJ1
VCC1_5_A[30] VSS[102] VSS_NCTF[07]
H2 AJ2
T69 VCC_LAN1_05_INT_ICH_1 VSS[103] VSS_NCTF[08]
A10 H23 AJ28
T70 VCC_LAN1_05_INT_ICH_2 VCCLAN1_05[1] VCCCL1_05_ICH VSS[104] VSS_NCTF[09]
A11 G22 H28 AJ29
+3VS VCCLAN1_05[2] VCCCL1_05 T71 VSS[105] VSS_NCTF[10]
G23 H29 B1
VCCCL1_5 VSS[106] VSS_NCTF[11]
A12 B29
VCCLAN3_3[1] VSS_NCTF[12]
B12 19/78/78mA 19/73/73mA
VCCLAN3_3[2]
0.1U_0402_16V4Z

1 23mA A24 +3VS 1 @


C485 R390 CHB1608U301_0603 VCCCL3_3[1] C486 ICH9-M ES_FCBGA676
VCCCL3_3[2] B24
GLAN POWER

A 1U_0603_10V4Z A
1 2 A27
R391 4.7U_0805_10V4Z VCCGLANPLL
80mA
2 +1.5VS 2
10U_0805_10V4Z

2.2U_0603_6.3V4Z

+1.5VS 1 2 D28 VCCGLAN1_5[1]


D29 VCCGLAN1_5[2]
1 1 CHB1608U301_0603 E26
C487 C488 VCCGLAN1_5[3]
1 E27 VCCGLAN1_5[4]
1mA
A26
2 2
0316 change design
C489
2
+3VS VCCGLAN3_3
ICH9-M ES_FCBGA676
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/28 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH9(4/4)_POWER&GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Montevina UMA 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 18, 2009 Sheet 23 of 46
5 4 3 2 1
5 4 3 2 1

HDD Connector
Pleace near HDD CONN (JP3) +3VS_ACL
+5VS
ACCELEROMETER (ST)

10U_0805_6.3V6M
0.1U_0402_16V4Z
C713

C714
10U_0805_10V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
CONN@
JHDD 1 1 1 1 1 1
+3VS +3VS_ACL +3VS_ACL_IO

C490
C491 C492 C493
GND 1
2 SATA_TXP0 D23 R564
A+ SATA_TXN0 SATA_TXP0 21 2 2 2 2 2 2
3 0_0603_5%
A- SATA_TXN0 21
4 0.01U_0402_16V7K 2 1 1 2
D GND SATA_RXN0 2 D
B-
5 1 C494 SATA_RXN0_C SATA_RXN0_C 21
6 SATA_RXP0 2 1 C495 SATA_RXP0_C CH751H-40PT_SOD323-2
B+ SATA_RXP0_C 21
7 0.01U_0402_16V7K
Near CONN side.
GND

8
V33 +3VS
9
V33
10
V33
11
GND CLK_SMBCLK
12 CLK_SMBCLK 15,16,17
GND
13
GND
14 0011101b

14
V5 +5VS U29
V5 15
16
VDDIO absolute man

SCL / SPC
V5
GND 17 rating is VDD+0.1
Reserved 18
GND 19
20 1 13 CLK_SMBDATA
V12 +3VS_ACL_IO Vdd_IO SDA / SDI / SDO CLK_SMBDATA 15,16,17
24 GND V12 21
23 22 R568 2 12 R570
GND V12 0_0402_5% GND SDO 0_0402_5%

/
1 2 3 Reserved Reserved 11 1 2
OCTEK_SAT-22EH1G_RV
4 GND GND 10

/x
5 GND INT 2 9

+3VS_ACL 6 Vdd INT 1 8 ACCEL_INT 20

CD-ROM Connector

su
C C

CS
LIS302DLTR_LGA14_3x5

7
p.
+5VS 2 1
R569 10K_0402_5%
JODD
Placea caps. near ODD CONN.
13
GND

om
12 SATA_TXP4
A+ SATA_TXP4 21
11 SATA_TXN4
A- SATA_TXN4 21

1U_0603_10V4Z

10U_0805_10V4Z

10U_0805_10V4Z
0.1U_0402_16V4Z
10 0.01U_0402_16V7K
GND SATA_RXN4
9 2 1 C510 SATA_RXN4_C SATA_RXN4_C 21 1 1 1 1
B- SATA_RXP4
B+
8 2 1 C511 SATA_RXP4_C SATA_RXP4_C 21
C512 C513 C514 C515
7 0.01U_0402_16V7K
Near CONN side.
GND
2 2 2 2

yc
6
DP
5
V5
4 +5VS
V5
3
MD
2
GND
1
GND

m
SUYIN_127382FR013GX09ZR
CONN@ //
B B
p:
tt

PA@ PR@
ZZZ ZZZ
h

PCB-MB PCB-MB

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/08/28 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD & CDROM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Montevina UMA 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 18, 2009 Sheet 24 of 46
5 4 3 2 1
5 4 3 2 1

LAN_DI 1 2 +3V_LAN
R695 3.6K_0402_5%
LAN_CS 2 1
R696 1K_0402_1%
9/17 RT suggestion: R696 change to 1K ohm
LAN Conn.
JRJ45
Place Close to Chip R697 +3V_LAN 13
U44 300_0402_5% Yellow LED+
LAN_ACTIVITY# 2 1 LANLED_ACT# 14
Yellow LED-
22 GLAN_RXP C240 2 1 0.1U_0402_16V7K PCIE_PTX_IRX_P2 20 33 LAN_DO
T82 1 16
HSOP LED3/EEDO LAN_DI SHLD1
34 8
D LED2/EEDI/AUX PR4- D
22 GLAN_RXN C241 2 1 0.1U_0402_16V7K PCIE_PTX_IRX_N2 21
HSON LED1/EESK
35 LAN_SK_LAN_LINK# LANLED_ACT# C268
DETECT PIN1
9
32 LAN_CS 0.1U_0402_16V4Z 7
EECS LANLED_LINK# 2 PR4+
22 GLAN_TXP 15
HSIP LAN_ACTIVITY# RJ45_MIDI1-
38 6
LED0 PR2-
22 GLAN_TXN 16
HSIN

2
RTL8102EL 2 LAN_MDI0+ 5
MDIP0 LAN_MDI0- @ PR3-
17 CLK_PCIE_LAN 17 3
REFCLK_P MDIN0 LAN_MDI1+ D20
17 CLK_PCIE_LAN# 18 5 4
REFCLK_M MDIP1 LAN_MDI1- PACDN042_SOT23~D PR3+
6
MDIN1 RJ45_MIDI1+
17 CLKREQ#_9 25 8 3
CLKREQB NC PR2+
9

1
NC RJ45_MIDI0-
9,20,26 PLT_RST# 27 PERSTB NC 11 2 PR1-
NC 12 DETCET PIN2 10
2 RJ45_MIDI0+ 1
R688 1 PR1+
2 2.49K_0402_1% 46 RSET NC 4 C269
SHLD1 15
0.1U_0402_16V4Z +3V_LAN 11
VCTRL12 Green LED+
22,26 ICH_PCIE_WAKE# 26 LANWAKEB VCTRL12A 48
ISOLATEB 28 LAN_SK_LAN_LINK# 1 2 1 LANLED_LINK# 12
ISOLATEB Green LED-
VDDTX 19 +EVDD12
LAN_X1 41 30 R698 FOX_JM36113-P1122-7F
CKXTAL1 DVDD12 +LAN_VDD12
LAN_X2 42 36 300_0402_5% CONN@
CKXTAL2 DVDD12

/
DVDD12 13
10 LANGND
DVDD12
1 1
C271 C272

/x
NC 39
+3VS
23 44 R1162 0_0603_5% 0.1U_0402_16V4Z 4.7U_0805_10V4Z
NC NC 2 2
24 NC VCTRL12D 45 1 2 +LAN_VDD12
1

R1177 0_0603_5%
R215 7 29 +3V_LAN_IC 1 2
GND VDD33 +3V_LAN
1K_0402_1% 14 37

su
GND VDD33
31 GND
C C
47 1
2

ISOLATEB GND AVDD33


NC 40
22 GNDTX NC 43

p.
R216 RTL8103EL-GR_LQFP48_7X7
15K_0402_5%
U46

LAN_MDI0+ 1 16 RJ45_MIDI0+
RD+ RX+

om
LAN_MDI0- 2 15 RJ45_MIDI0- R693
C247 1 LAN_CT0 RD- RX- RJ45_CT0
2 0.01U_0402_16V7K 3 14 75_0402_1%
CT CT
4
NC NC
13 C257 1 2 0.01U_0603_100V7-M RJ45_CT0_C 1 2
5 12 C258 1 2 0.01U_0603_100V7-M RJ45_CT1_C 1 2 RJ45_GND
+3VALW C248 1 LAN_CT1 NC NC RJ45_CT1
2 0.01U_0402_16V7K 6
CT CT
11
LAN_MDI1+ 7 10 RJ45_MIDI1+ R694 1
LAN_MDI1- TD+ TX+ RJ45_MIDI1- 75_0402_1% C259
8 9
TD- TX-
40 mils
S

yc
1000P_1206_2KV7K
D

3 1 +3V_LAN
X'FORM_ HD-024A 2
2
@
G
2

C255 Q19
SI2301BDS-T1-E3_SOT23-3
1

m
32 LAN_POWER_OFF 1 2
R218 10K_0402_5% 0.1U_0402_16V4Z
//
B B

Close to Pin1,37,29 +3V_LAN


p:

Close to Pin10,13,30,36 +LAN_VDD12


0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2 2 2
tt

2 2 2 2 C253 C254 C261


C249 C250 C251 C252
1 1 1
1 1 1 1
h

Close to Pin19 Close to Pin45 Close to Pin48


+EVDD12 +LAN_VDD12 Y3
VCTRL12 LAN_X1 2 1 LAN_X2
10U_0805_10V4Z

0.1U_0402_16V4Z

25MHz_20pF_6X25000017
10U_0805_10V4Z
1U_0402_6.3V4Z

1U_0402_6.3V4Z

0.1U_0402_16V4Z

@ 1 2 1 1
2 2 2 1 @ C262 C263 C244 C245
C266 C267 C264 C265
27P_0402_50V8J
2 1 2 27P_0402_50V8J 2
A 1 1 1 2 A

9/17 RT suggestion: C267 change to 1uF


Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/06/30 Title
2007/08/28 Deciphered Date
RTL8102EL LAN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Montevina UMA 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 18, 2009 Sheet 25 of 46
5 4 3 2 1
A B C D E

+3VALW +3VALW +3VS_WLAN


R432 0.01U_0402_16V7K
+1.5VS_WLAN Reserve for WWAN
R431
Mini Card Slot ---WLAN,WWAN
0.1U_0402_16V4Z 2 1 +3VS 4.7U_0805_10V4Z 2 1 +1.5VS JMINIA
0_0805_5% 0_0805_5% ICH_PCIE_WAKE# A1 A2
WAKE# +3.3Vaux +3VS_WLAN
1 1 1 @ 1 1 1 1 CH_DATA A3
30 CH_DATA COEX1 GND
0.1U_0402_16V4Z

0.1U_0402_16V4Z
1 1 C566 C567 C1497 C569 C570 C571 @ CH_CLK A5 A6
30 CH_CLK COEX2 +1.5V +1.5VS_WLAN
C568 C572 C1498 17 CLKREQ#_6 CLKREQ#_6 A7 A8 LPC_FRAME#
CLKREQ# UIM_PWR LPC_AD3 LPC_FRAME# 21,32
47P_0402_50V8J 47P_0402_50V8J A9 A10
2 2 2 2 2 2 2 CLK_PCIE_MCARD2# GND UIM_DATA LPC_AD2 LPC_AD3 21,32
17 CLK_PCIE_MCARD2# A11 REFCLK- UIM_CLK A12 LPC_AD2 21,32
2 2 4.7U_0805_10V4Z CLK_PCIE_MCARD2 A13 A14 LPC_AD1
17 CLK_PCIE_MCARD2 REFCLK+ UIM_RESET LPC_AD0 LPC_AD1 21,32
0.1U_0402_16V4Z
Reserve for WWAN SI-1 Connect PLT_RST# to JP7.A17 PLT_RST#
A15
A17
GND UIM_VPP
A16 LPC_AD0 21,32
1 Reserved GND XMIT_OFF# 2 1
17 CLK_DEBUG_PORT_1 A19 A20 1 XMIT_OFF 22
Reserved W_DISABLE# PLT_RST# D19 CH751H-40PT_SOD323-2
A21 A22
R423 1 PCIE_C_RXN3 GND PERST#
2 0_0402_5% @ R424 1 2 0_0805_5%

SIM card Connector


22 PCIE_RXN3 A23 A24 +3VALW
R425 1 PCIE_C_RXP3 PERn0 +3.3Vaux
22 PCIE_RXP3 2 0_0402_5% A25 GND R426 1 2 0_0805_5% +3VS_WLAN
PERp0
A27 A28 +1.5VS_WLAN
GND +1.5V ICH_SMBCLK
A29 A30
PCIE_TXN3 GND SMB_CLK ICH_SMBDATA
22 PCIE_TXN3 A31 A32
PCIE_TXP3 PETn0 SMB_DATA
A33 GND
22 PCIE_TXP3 PETp0
CONN@ R11 10K_0402_5% A35
GND USB_D-
A36 USB20_N5 22 SI-1 For PR
JSIM UIM_CLK +3VS 1 2 CLKREQ#_6 A37 A38
GND USB_D+ USB20_P5 22 WL_LED# WW_LED#_R
1 1 A39 GND 1 2
UIM_VPP 1 C824 @ +3.3Vaux PR@ R1225 0_0402_5%
2 2 +3VS_WLAN A41 +3.3Vaux LED_WWAN# A42
UIM_RST 3 18P_0402_50V8J R10 10K_0402_5% A43 A44
UIM_CLK 3 CLKREQ#_10 GND LED_WLAN# WL_LED# 33 XMIT_OFF# 1 M_WXMIT_OFF#
4 4 +3VS 1 2 A45 Reserved LED_WPAN# A46 2
UIM_DATA 5 7 2 A47 A48 PR@ R1226 0_0402_5%
5 G1 Reserved +1.5V +1.5VS_WLAN
UIM_PWR 6 8 A49
6 G2 Reserved GND UIM_PWR_R LPC_FRAME#
A51 A52 +3VS_WLAN 1 2 PR@
ACES_87212-06G0 Reserved +3.3Vaux UIM_DATA_R R1227 0_0402_5% LPC_AD3 PR@
1 2
A53 A54 UIM_CLK_R R1228 1 2 0_0402_5% LPC_AD2 PR@
GND GND UIM_RST_R R1229 0_0402_5% LPC_AD1 PR@
1 2
QUASA_CA0416-092N21 UIM_VPP_R R1230 1 2 0_0402_5% LPC_AD0 PR@

/
@ R750 R1231 0_0402_5%
UIM_PWR 1 2 UIM_DATA
47K_0402_5% JMINIB UIM_PWR_R 1 2 UIM_PWR PA@
ICH_PCIE_WAKE# UIM_DATA_R R1232 0_0402_5% UIM_DATA PA@

/x
B1 WAKE# +3.3Vaux B2 +3VS_WWAN 1 2
CH_DATA B3 B4 UIM_CLK_R R1233 1 2 0_0402_5% UIM_CLK PA@
CH_CLK COEX1 GND UIM_RST_R R1234 0_0402_5% UIM_RST PA@
B5 COEX1 +1.5V B6 +1.5VS_WLAN 1 2
CLKREQ#_10 B7 B8 UIM_PWR_R UIM_VPP_R R1235 1 2 0_0402_5% UIM_VPP PA@
17 CLKREQ#_10 CLKREQ# UIM_PWR
B10 UIM_DATA_R R1236 0_0402_5%
+3VS_WWAN B11
GND UIM_DATA
B12 UIM_CLK_R
17 CLK_PCIE_MCARD0# REFCLK- UIM_CLK
B13 B14 UIM_RST_R

su
+3VS_WWAN 17 CLK_PCIE_MCARD0 REFCLK+ UIM_RESET UIM_VPP_R
@ R400 B16
2
1 2 B17
GND UIM_VPP
B18 PA@ D11 CH751H-40PT_SOD323-2 2
0.01U_0402_16V7K 4.7U_0805_10V4Z 0_0603_5% Reserved GND M_WXMIT_OFF# 2
B19 Reserved W_DISABLE# B20 1 WXMIT_OFF# 22
+3VS PA@ 0_0402_5% B22 PLT_RST#
R418 R419 1 2 PCIE_C_RXN1 B23
GND PERST#
B24 @ R420 1 2 0_0805_5% +3VALW
22 PCIE_RXN1 PERn0 +3.3Vaux
S

1 PA@ 1 PA@ 1 PA@ 3 1 1 2 1 2 PCIE_C_RXP1 B25 B26 R422 1 2 0_0805_5% +3VS_WWAN


D

+3VALW 22 PCIE_RXP1 PERp0 GND

p.
C573 C574 C575 0_1206_5% R421 0_0402_5% B28 +1.5VS_WLAN
GND +1.5V ICH_SMBCLK
1 @ PA@
GND SMB_CLK B30
@ C1499 PCIE_TXN1 ICH_SMBDATA
G

22 PCIE_TXN1 B31 B32


2

2 2 2 Q52 PCIE_TXP1 PETn0 SMB_DATA


B33 B34
32 WWAN_POWER_OFF 47P_0402_50V8J 22 PCIE_TXP1 PETp0 GND
B36 USB20_N8 22
GND USB_D-

om
0.1U_0402_16V4Z SI2301BDS-T1-E3_SOT23-3 2 B37 B38
GND USB_D+ USB20_P8 22
Reserve for WWAN +3VS_WWAN B39
B41
+3.3Vaux GND
B40
B42
+3.3Vaux LED_WWAN# WW_LED# 33
B43 B44 WW_LED#_R
GND LED_WLAN#
B45 B46
Reserved LED_WPAN#
B47 B48 +1.5VS_WLAN
Reserved +1.5V
B49 B50
Reserved GND
B51 B52 +3VS_WWAN
Reserved +3.3Vaux

yc
QUASA_CA0416-092N21

New Card
m
Near to Express Card slot.
// CONN@
JEXP
3
1 +3VS_PEC 3
R436 USB9- GND
1 2 0_0402_5% 2
Express Card Power Switch
22 USB20_N9 USB9+ USB_D-
R437 1 2 0_0402_5% 3
22 USB20_P9 EXP_CPPE# USB_D+
4
p:

+1.5VS CPUSB#
5 1 1
C576 RSV
6
ICH_SMBCLK RSV
1 2 0.1U_0402_16V4Z U16
17,22 ICH_SMBCLK 7 C577 C578
ICH_SMBDATA SMB_CLK 0.1U_0402_16V4Z 4.7U_0805_10V4Z
12 11 +1.5VS_PEC 17,22 ICH_SMBDATA 8
+3VS 1.5Vin 1.5Vout SMB_DATA 2 2
14 13 +1.5VS_PEC 9
tt

1.5Vin 1.5Vout R438 +1.5V


+1.5VS_PEC 10
PCIE_PME#_R +1.5V
22,25 ICH_PCIE_WAKE# 1 2 11
C579 1 WAKE#
2 0.1U_0402_16V4Z 2 3 +3VS_PEC 0_0402_5% 12
3.3Vin 3.3Vout +3V_PEC PERST# +3.3VAUX +1.5VS_PEC
4 5 13
3.3Vin 3.3Vout PERST#
h

C580 1 2 0.1U_0402_16V4Z 14
+3VS_PEC +3.3V
+3VALW 17 15 +3V_PEC 15
AUX_IN AUX_OUT CLKREQ#_4 +3.3V
17 CLKREQ#_4 16 1 1
PLT_RST# EXP_CPPE# CLKREQ#
9,20,25 PLT_RST# 6 19 17
SYSRST# OC# CPPE# C581 C582
17 CLK_PCIE_NCARD# 18
SYSON PERST# REFCLK- 0.1U_0402_16V4Z 4.7U_0805_10V4Z
32,35,40 SYSON 20 8 17 CLK_PCIE_NCARD 19
SHDN# PERST# REFCLK+ 2 2
20
SUSP# GND
32,35,37,39 SUSP# 1 16 22 PCIE_RXN4 21
STBY# NC PERn0
22 PCIE_RXP4 22
@ R439 1 PERp0
+3VALW 2 100K_0402_5% 10 7 23
CPPE# GND GND
22 PCIE_TXN4 24
EXP_CPPE# PETn0
22 EXP_CPPE# 9 22 PCIE_TXP4 25
CPUSB# PETp0
26
GND +3V_PEC
18
Close to
RCLKEN
27
GND
ENE P2231NL E2 QFN 20P 28
JEXP
GND

internal pull high to 3.3Vaux-in R12 SANTA_130801-5_RT C583


1 1
C584
4 CLKREQ#_4 0.1U_0402_16V4Z 4.7U_0805_10V4Z 4
1 2
EC need setting at Hi-Z & output Low +3VS
2 2
10K_0402_5%

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/08/28 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
WLAN, WWAN, New Card
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina UMA 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 18, 2009 Sheet 26 of 46
A B C D E
5 4 3 2 1

+3VS
D D

2 R1102 +VCC_4IN1
100K_0402_5%

R1103 0_0402_5% 1
1

2 1 RST# C1403 1 2
0.1U_0402_16V4Z 0.1U_0402_16V4Z R1104 0_0402_5%
2

1 C1404
C1405 R1105 2
1 2
499K_0402_1%~D +3VS
1U_0402_6.3V6K @ U47
2 0.1U_0402_16V4Z
1

C1406 1 1 1 1 C1409
1U_0603_16V6K C1407 C1408 AV_PLL 1U_0603_10V4Z
3 NC
7 NC 1 2
9

Card Reader Connector


2 2 2 CARD_3V3
11 D3V3
33 D3V3 VREG 10
+3VS 0.1U_0402_16V4Z 22 CONN@
MS_D4 JREAD1
NC 30
8 3V3_IN +VCC_4IN1 3 XD-VCC SD-VCC 21 +VCC_4IN1
RST# 44 28
C1410 RST# MS-VCC
1 C1411 R1115 MODE SEL XDD0_SDD5

/
1 45 MODE_SEL 32 XD-D0
4.7U_0603_6.3V6K 0_0402_5% 47 43 XD_CLE XDD1 10 7 IN 1 CONN 20 SDCLK
XTLI XTLO XD_CLE_SP19 XDCE# XDD2_SDD7_MSD2 XD-D1 SD_CLK XDD6_SDD0_MSD0
17 CLK_48M_CR 1 2 48 XTLI XD_CE#_SP18 42 9 XD-D2 SD-DAT0 14
2 41 XD_ALE XDD3_MSD1 8 12 XDD4_SDD1
XD_ALE_SP17 XD-D3 SD-DAT1

/x
2 2 USB20_N3 XD_RE#_SDD2 XDD4_SDD1 XD_RE#_SDD2
22 USB20_N3 4 DM SD_DAT2/XD_RE#_SP16 40 7 XD-D4 SD-DAT2 30
@ C1415 22 USB20_P3 USB20_P3 5 39 XDWE#_SDD3 XDD5_MSBS 6 29 XDWE#_SDD3
0.1U_0402_16V4Z 6P_0402_50V8J CR_LED# DP SD_DAT3/XD_WE#_SP15 XDRDY XDD6_SDD0_MSD0 XD-D5 SD-DAT3 XDWP#_SDD4
14 GPIO0 XD_RDY_SP14 38 5 XD-D6 SD-DAT4 27
1 XDWP#_SDD4 XDD7_SDD6_MSD3 XDD0_SDD5
SD_DAT4/XD_WP#/MS_D7_SP13 37 4 XD-D7 SD-DAT5 23
C 35 XDD0_SDD5 18 XDD7_SDD6_MSD3 C
SD_DAT5/XD_D0/MS_D6_SP12 SD-DAT6
SI-1 Delete Crystall layout location SD_CLK/XD_D1/MS_CLK_SP11 34 XDD1 1 2 MSCLK XDWE#_SDD3 34 XD-WE SD-DAT7 16 XDD2_SDD7_MSD2
31 XDD7_SDD6_MSD3 0_0402_5% R1106 XDWP#_SDD4 33 25 SDCMD
SD_DAT6/XD_D7/MS_D3_SP10 XD-WP SD-CMD

su
29 MSINS# 1 2 SDCLK XD_ALE 35 1 SDCD#
MS_INS#_SP9 XDD2_SDD7_MSD2 0_0402_5% R1109 XDCD# XD-ALE SD-CD-SW
SD_DAT7/XD_D2/MS_D2_SP8 28 40 XD-CD
27 XDD6_SDD0_MSD0 XDRDY 39 2 SDWP
SD_DAT0/XD_D6/MS_D0_SP7 XD-R/B SD-WP-SW
SI-1 Change LED type SD_DAT1/XD_D3/MS_D1_SP6 26 XDD3_MSD1 XD_RE#_SDD2 38 XD-RE
25 XDD5_MSBS XDCE# 37
PA@ XD_D5_SP5 XDD4_SDD1 XD_CLE XD-CE MSCLK
R1107 XD_D4/SD_DAT1_SP4 23 36 XD-CLE MS-SCLK 26
D54 21 SDCD# 17 XDD6_SDD0_MSD0

p.
CR_LED# SD_CD#_SP3 SDWP MS-DATA0 XDD3_MSD1
+5VS 1 2 2 1 SD_WP_SP2 20 11 7IN1 GND MS-DATA1 15
19 XDCD# 31 19 XDD2_SDD7_MSD2
1.2K_0402_5% HT-110TW_WHITE 6.19K_0402_1% XD_CD#_SP1 7IN1 GND MS-DATA2 XDD7_SDD6_MSD3
EEDI 18 MS-DATA3 24
R1112 0_0402_5% 22 MSINS#
White
R1111 MS-INS
MODE SEL 2 1 2 13 1 2 +3VS 13 XDD5_MSBS
RREF XTAL_CTR MS-BS

om
MS_D5 24 41 7IN1 GND
2

12 DGND 42 7IN1 GND


D64 1 32 15
@ C1412 @ R1110 DGND EEDO TAITW_R015-B10-LM
2 1 EECS 16
47P_0402_50V8J 10K_0402_5% 6 17
HT-110TW_WHITE AGND EESK SDCMD
46 36
1

PR@ 2 AGND SD_CMD

yc
RTS5159E-GR_LQFP48_7X7

MSCLK SDCLK

1
R1113 R1114

m
@ 10_0402_5% @ 10_0402_5%
B B

2
// 1 1
10P_0402_50V8J 10P_0402_50V8J
@ C1413 @ C1414
2 2
p:
tt
h

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/08/28 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB CardReader&CONN
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom Montevina UMA 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 18, 2009 Sheet 27 of 46
5 4 3 2 1
A B C D E

1
CODEC POWER 1

(4.75V(4.56~4.94V)) 300mA
+VDDA_CODEC R1116 R1117
SI-1 Delete CODEC POWER IC VREFOUT_B 2 1 C1418 1 2 VREFOUT_C 2 1 C1419 1 2
0_0402_5% 1K_0402_5%

1
1U_0603_10V4Z 1U_0603_10V4Z

2
R1118 R1119 R1120 R1121
R1122
0_0603_5% 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5%

2
+VDDA_CODEC_R MIC_EXT_R MIC_IN_R

1
R1123
BLM18BD601SN1D_0603 MIC_EXT_L MIC_IN_L
+3VS 2 1 +3VS_HDA C1424 C1425 C1426 C1422 C1423
1 2

1U_0603_10V4Z
10U_0805_10V4Z
0.1U_0402_16V7K

1U_0603_10V4Z

0.1U_0402_16V7K
1 1 2 2 1

/
2 2 1
U49 +VDDA_CODEC_R
PV-1 ESD request

/x
1 17 R1124 1 2 2.49K_0402_1%
DVDD_LV AVDD R1125 1 2 39.2K_0402_1% HP_DET# 29
6 10 SENSEA R1126 1 2 20K_0402_1%
+1.5VS DVDD_CORE SENSE_A EXTMIC_DET# 29
23 R1128 2 1 100K_0402_5% +VDDA_CODEC_R
SENSE_B @ C1428 1 1000P_0402_50V7K C1429
2 1 2 1000P_0402_50V7K

su
HDA_BITCLK_CODEC 3 26 HP_IN_L
21 HDA_BITCLK_CODEC HDA_BITCLK PORT_A_L HP_IN_L 29
1

2 33_0402_5% HP_IN_R 2
PORT_A_R 27 HP_IN_R 29 HP Jack
R1239
21 HDA_SDIN0
R1130 1 2 HDA_SDIN0_CODEC 5 HDA_SDI
C1430
4.7K_0402_5% 13 MIC_EXTL 1 2 2.2U_0603_6.3V6K MIC_EXT_L
HDA_SDOUT_CODEC PORT_B_L MIC_EXTR MIC_EXT_R MIC_EXT_L 29 MIC_IN_L
21 HDA_SDOUT_CODEC 2 HDA_SDO PORT_B_R 14 1 2 2.2U_0603_6.3V6K MIC_EXT_R 29 Jack MIC 1 2 MIC_IN_L 29
20 VREFOUT_B C1432 2.2U_0603_6.3V6K
2

VREFOUT_B

p.
HDA_SYNC_CODEC 7 C1431
21 HDA_SYNC_CODEC HDA_SYNC MIC_INL
PORT_C_L 15 Internal MIC
0.01U_0402_16V7K

HDA_RST#_CODEC HDA_RST#_CODEC 8 16 MIC_INR


21,32 HDA_RST#_CODEC HDA_RST# PORT_C_R VREFOUT_C
21
VREFOUT_C
1 SI-1 For EMI request

om
24 LINE_OUT_L 1 2 MIC_IN_R
PORT_D_L LINE_OUT_L 29 MIC_IN_R 29
C1516 25 LINE_OUT_R Internal SPKR. C1433 2.2U_0603_6.3V6K
PORT_D_R LINE_OUT_R 29
R1132 22_0603_1%
2 1 2 30 11
19 DMIC_CLK DMIC_CLK PORT_E_L
19 DMIC_DAT 1 2 29
DMIC0/GPIO1 PORT_E_R
12
R1178 0_0603_5% R1133 47K_0402_5%
9 MONO_INR 2 1 MONO_IN 2 1 R1134 10K_0402_5%
PC_BEEP/MONO
32
SPDIF_OUT_0
0.1U_0402_16V7K C1434 2 1 +VDDA_CODEC PV-1 For EMI

yc
28
EAPD_CODEC SPDIF_OUT_1/GPIO7 MIC_EXTL
32 EAPD_CODEC 31 22
EAPD/GPIO0/SPDIF_OUT 0 or 1 CAP2

0.1U_0402_16V7K
19
VREFFILT MIC_EXTR
2 2 1

2
10K_0402_5%
C1436 C1459

6
10U_0805_10V4Z
4 18 C1437 C1435 0.1U_0402_16V7K
DVSS AVSS

2
m
33 1 2 R1135 Q10A
TPAD 1

1U_0603_10V4Z
2N7002DW-7-F_SOT363-6 D58
92HD75B1X5NLGXYAX8 QFN 32P 1.5V CODEC 22 SB_SPKR 2 PSOT24C_SOT23-3

1
2 1

2N7002DW-7-F_SOT363-6
1
//

1
3
3 Q10B 3

5
p:

C1478

4
1 2
1000P_0402_50V7K
C1479
tt

1 2
1000P_0402_50V7K 090212 For PC Beep Noise
C1480
h

1 2
1000P_0402_50V7K
C1481
1 2
1000P_0402_50V7K

R1174
1 2
0_0402_5%

R1175
1 2
0_1206_5%

R1176
1 2 GNDA 29
0_1206_5%
4 4

GND GNDA

Security Classification Compal Secret Data


Issued Date 2007/08/28 Deciphered Date 2006/07/26 Title
Codec_IDT9275B
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Montevina UMA 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 18, 2009 Sheet 28 of 46
A B C D E
A B C D E

JSPK1
SPKR- R1136 1 2 0_0603_5% SPK_R- 1
AMP. FOR INTERNAL SPEAKER SPKR+ R1137 1 2 0_0603_5% SPK_R+ 2
1
2
SPEAKER
SPKL- R1138 1 2 0_0603_5% SPK_L- 3
SPKL+ R1139 1 0_0603_5% SPK_L+ 3
2 4 4

GAIN1 GAIN0 Av(inv) C1438


1
C1439
1
C1440
1
C1441
1 5
6
GND1
1 GND2 1
E&T_3806-F04N-02R
2 2 2 2
0 0 10dB CONN@
330P_0402_50V7K 330P_0402_50V7K

0 1 12dB +5VS TPA6047 LDO OUTPUT 4.7V 330P_0402_50V7K 330P_0402_50V7K


+5VS R1140 +VDDA_CODEC
0_0805_5% 9/20 SP02000CW00
1 0 V 15.6dB 2 1
Close to Pin29

2
1 2
@ R1141 100K_0402_5% 1 2 C1443 10U_0805_10V4Z
1 1 21.6dB 1 2
1 2 C1442 1U_0603_10V4Z C1444 1U_0603_10V4Z D55 D56
R1142 100K_0402_5% 1 2 PSOT24C_SOT23-3 PSOT24C_SOT23-3
R1144 C1445 0.1U_0402_16V7K

1
@ R1143 0_0402_5% 1 2 1 2

+VDDA_CODEC_IC
1 2 GAIN1 0_0603_5%
R1145 0_0402_5%
1 2 GAIN0 1 2 HP_IN_L
HP_IN_L 28
C1446 1 2 2.2U_0805_10V6K HP_IN_R
HP_IN_R 28
C1447 2.2U_0805_10V6K CONN@

HP_INR
HP_INL

/
GAIN1

GAIN0
JSPK2
SPK_L- 1
SLP_S3# 22,32 SPK_L+ 1
@ R1147 2 2

/x
1 2
100K_0402_5%

33

32

31

30

29

28

27

26

25
3 GND
4 GND
U50

TML

GAIN1

GAIN0

HP_INL
REG_OUT
VDD

SGND

HP_INR

REG_EN
TPA6047A4RHBR QFN 32P ACES_88231-02001
C1448 0.47U_0402_6.3V6K R1148 0_0402_5%
2 1 LINE_C_OUTR 2 1 LINE_R_OUTR 2 24 C1449 1 2 1U_0603_10V4Z SI-1 Add JSPK2 for PA

su
28 LINE_OUT_R C1450 0.47U_0402_6.3V6K SPKR_RIN+ BYPASS
2 2
2 1 1 SPKR_RIN- SPKR_EN# 23
C1451 0.47U_0402_6.3V6K R1150 0_0402_5% R1151 EC_MUTE# 32
2 1 LINE_C_OUTL 2 1 LINE_L_OUTR 3 22 1 2 +3VS
28 LINE_OUT_L C1452 0.47U_0402_6.3V6K SPKR_LIN+ HP_EN 100K_0402_5%
2 1 4 21
SPKR_LIN- SPGND

p.
1 2
5 20 SPKR+ MV-1 For ESD request, close to JMIC2
SPGND ROUT+ @ C1453 0.1U_0402_16V4Z
SPKL+ 6 19 SPKR-
LOUT+ ROUT-

om
R1152 SPKL- 7 18 R1153
LOUT- SPVDD

1
0_0805_5% 0_0805_5%
+5VS 2 1 8
SPVDD HPVDD
17 2 1 +5VS
D57
C1456

C1457

C1454

C1455
HP_OUTR
PSOT24C_SOT23-3

HP_OUTL
CPGND

INTMIC IN
CPVDD

CPVSS

HPVSS 1 1 28 MIC_IN_L
1 1

3
C1N
C1P

1
yc
R1211
2 2

1U_0603_10V4Z

10U_0805_10V4Z
0_0402_5%
9

10

11

12

13

14

15

16
2 2 CONN@
10U_0805_10V4Z

1U_0603_10V4Z

JMIC2

2
28 MIC_IN_R 1
1
2
2

m
3
GND
1 2 4
C1458 GND
1U_0603_10V4Z ACES_88231-02001
1
C1461
2
1U_0603_10V4Z
// HP_OUTL
HP_OUTR
3 3
p:
tt

SI-1 Add Audio board connector


h

Audio connector
JAUDIO
1
MIC_EXT_R 1
28 MIC_EXT_R 2
MIC_EXT_L 2
28 MIC_EXT_L 3
3
4
HP_OUTL 4
5
HP_OUTR 5
SI-1 Change IR1 to SCR00000E00 6
6
7
EXTMIC_DET# 7
28 EXTMIC_DET# 8
+5VL HP_DET# 8
9
Consumer IR 28 HP_DET#
10
9
10
1

R1158
100_0805_5% 11
IR1 GND1
12
GND2
1
2

4 Vout ACES_87213-1000G 4
2 CONN@
VCC

32 CIR_IN CIR_IN 3 GND


4 GND
C1466
IRM-V536/TR1_3P
4.7U_0805_10V4Z Security Classification Compal Secret Data
Issued Date 2007/08/28 Deciphered Date 2006/07/26 Title
AMP & Audio Jack
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Montevina UMA 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 18, 2009 Sheet 29 of 46
A B C D E
5 4 3 2 1

Right side USB Power Switch Right side ESATA/USB combination Connector
+5VALW

USB_VCCC
U41 USB_VCCC
1
GND OUT
8 W=100mils JESAT
2 7 1 USB
IN OUT VBUS

1000P_0402_50V7K
D D

0.1U_0402_16V4Z
3 6 1 R1080 1 2 0_0402_5% USB20_N0_R 2
IN OUT 22 USB20_N0 D-

150U_B_6.3VM_R40M
1 USB_EN# 4 5 1 1 R1081 1 2 0_0402_5% USB20_P0_R 3
EN# OC# 22 USB20_P0 D+

C1380

C1382

C1383
C1381 + 4
TPS2061IDGNR_MSOP8 GND
5
2 2 2 2 SATA_TXP5 GND
21 SATA_TXP5 6
SATA_TXN5 A+ ESATA
21 SATA_TXN5 7
A-
8
GND
4.7U_0805_10V4Z
21 SATA_RXN5_C
C1385 2 1 0.01U_0402_16V7K SATA_RXN5 9
B-
21 SATA_RXP5_C
C1384 2 1 0.01U_0402_16V7K SATA_RXP5 10
B+
11
R1083 GND
1 2 10K_0402_5% +5VALW
12 GND
13 GND
14 GND
15 GND
TYCO_1759576-1
@ CONN@
D45
@

/
4 2 USB20_N0_R
+5VALW VIN IO1 D46
USB20_P0_R 3 1 +5VALW 4 2 SATA_TXP5
IO2 GND VIN IO1

/x
PRTR5V0U2X_SOT143-4 SATA_TXN5 3 1
IO2 GND
PRTR5V0U2X_SOT143-4

su
C C

Finger printer BT Connector

p.
om
JBT
10 8 +3VAUX_BT
GND 8
7
7 USB20_P6_R R1084
6 2 1 0_0402_5% USB20_P6 22
6 USB20_N6_R R1085
5
5 2 1 0_0402_5% USB20_N6 22
4 BT_LED 33
+3VS 4 @ R1086 1 1K_0402_5%
3 2
3 @ R1087 1 1K_0402_5% CH_DATA 26
2 2 CH_CLK 26
2

yc
9 1
GND 1
2

ACES_87213-0800G @
D47
R628 CONN@
0_0805_5% CONN@ +5VALW 4 2 USB20_P6_R
JFPR VIN IO1

m
22 USB20_N7
R634 1 2 0_0402_5% USB20_N7_R 1 USB20_N6_R 3 1
1

1 IO2 GND
22 USB20_P7
R635 1 2 0_0402_5% USB20_P7_R 2
+3VS_FP 2 +3VS PRTR5V0U2X_SOT143-4
3
3 R235
1 4
4
5 1 2
GND
C756 0.1U_0402_16V4Z
D30
6
//
GND +3VALW 0_0603_5% +3VAUX_BT
2 USB20_P7_R P-TWO_161011-04021 Q105 SI2301BDS-T1-E3_SOT23-3
+5VALW 4 2
B VIN IO1 @ R236 B
0.1U_0402_16V4Z

S
USB20_N7_R

D
3 1 1 2 3 1
IO2 GND
PRTR5V0U2X_SOT143-4 0_0603_5%
p:

G
1 1 1 1

2
C1387 C1388 C1389
C1386 @ R1090
1U_0603_10V4Z 100K_0402_5%
2 2 2 2

2
tt

0.01U_0402_16V7K 4.7U_0805_10V4Z

USB cable connector for Right side


C1390
h

R1092 1 2 10K_0402_5% 1 2
22 BT_OFF
0.1U_0402_16V4Z

JUSB
+5VALW 1
1
2
2
3
USB_EN# 3
32 USB_EN# 4
4
5
22 USB20_N2 5
6
22 USB20_P2 6
7
7
8
22 USB20_N1 8
9
22 USB20_P1 9
10
10

11 GND1
A A
12 GND2
ACES_87213-1000G
CONN@

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/08/28 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB, BT, eSATA
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina UMA 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 18, 2009 Sheet 30 of 46
5 4 3 2 1
5 4 3 2 1

D
SPI ROM D

+3VL
U27
20mils 8 4
VCC VSS
1
C712 3
0.1U_0402_16V4Z W
7 HOLD
2
1 2 SPI_FSEL# 1
32 FSEL# S
R553 10_0402_5%
1 2 SPI_CLK_R 6
32 SPI_CLK C
R554 10_0402_5%
32 FWR# 1 2 SPI_FWR# 5 2 SPI_SO 1 2 FRD# FRD# 32
R556 10_0402_5% D Q R555 0_0402_5%
WIESON G6179 8P SPI

SP07000F500 S SOCKET WIESON G6179-100000 8P SPIFLASH


R230 C307 WIESO_G6179-100000_8P

/
SPI_FSEL# 2 1 2 1

33_0402_5% 22P_0402_50V8J

/x
R231 C308
SPI_CLK_R 2 1 2 1

33_0402_5% 22P_0402_50V8J

R232 C309

su
SPI_FWR# 2 1 2 1
C C
33_0402_5% 22P_0402_50V8J

EMI request

p.
om
yc
m
//
B B
p:
tt
h

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/08/28 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BIOS ROM
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina UMA 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 18, 2009 Sheet 31 of 46
5 4 3 2 1
+1.5VS C301
+3VL_EC
+3VS BATT_OVP 2 1
0.1U_0402_16V4Z 0.1U_0402_16V4Z 1000P_0402_50V7K
HDA level shift

1
1 1 1 1 1 100P_0402_50V8J

1
R250
C715 C716 C717 C718 C719 +3VL +3VL_EC +EC_AVCC 56_0402_5% R251
10K_0402_5%
EC recommend
2 2 2 2 2 R572

2 2
0.1U_0402_16V4Z 1000P_0402_50V7K 1 2

2
B
0_0805_5%
For EMI

E
3 1 HDA_RST#_EC
21,28 HDA_RST#_CODEC

111
125

C
+3VL +3VS

22
33
96

67
9
U30 Q21 KSO15 @ C792 1 2 100P_0402_50V8J
SMB_EC_DA1 R573 1 2 4.7K_0402_5% MMBT3904_NL_SOT23-3

VCC
VCC
VCC
VCC
VCC
VCC

AVCC
SMB_EC_CK1 R577 1 2 4.7K_0402_5% KSO10 @ C793 1 2 100P_0402_50V8J
SMB_EC_DA2 R574 1 2 4.7K_0402_5%
SMB_EC_CK2 R575 1 2 4.7K_0402_5% KSO11 @ C794 1 2 100P_0402_50V8J
GATEA20 1 21 INV_PWM
21 GATEA20 KB_RST# GA20/GPIO00 INVT_PWM/PWM1/GPIO0F INV_PWM 19 KSO14
2 23 @ C795 1 2 100P_0402_50V8J
21 KB_RST# SIRQ KBRST#/GPIO01 BEEP#/PWM2/GPIO10 DIM_LED
22 SIRQ 3 26 DIM_LED 35
LPC_FRAME# SERIRQ# FANPWM1/GPIO12 ACOFF KSO13 @ C796 1
21,26 LPC_FRAME# 4
LFRAME# ACOFF/FANPWM2/GPIO13
27 ACOFF 37 2 100P_0402_50V8J
@ C722 @ R576 21,26 LPC_AD3 LPC_AD3 5 0.01U_0402_16V7K
LPC_AD2 LAD3 ECAGND KSO12
1 2 1 2 21,26 LPC_AD2 7
LAD2 PWM Output C720 1 2 @ C797 1 2 100P_0402_50V8J
33_0402_5% 21,26 LPC_AD1 LPC_AD1 8 63 BATT_TEMP
LPC_AD0 LAD1 BATT_TEMP/AD0/GPIO38 BATT_OVP BATT_TEMP 36 KSO3
LAD0 LPC & MISC
15P_0402_50V8J 21,26 LPC_AD0 10 64 @ C798 1 2 100P_0402_50V8J
BATT_OVP/AD1/GPIO39 ADP_I BATT_OVP 36
ADP_I/AD2/GPIO3A 65 ADP_I 37
CLK_PCI_EC 12 AD Input 66 ADP_ID KSO6 @ C799 1 2 100P_0402_50V8J
17 CLK_PCI_EC PCI_RST# PCICLK AD3/GPIO3B TP_BTN# ADP_ID 36
20 PCI_RST# 13 PCIRST#/GPIO05 AD4/GPIO42 75 TP_BTN# 33
1 2 ECRST# 37 76 KSO8 @ C800 1 2 100P_0402_50V8J
+3VL ECRST# SELIO2#/AD5/GPIO43
R578 47K_0402_5% 20
22 EC_SCI# HDA_RST#_EC R403 1 SCI#/GPIO0E KSO7
2 0_0402_5% 38 CLKRUN#/GPIO1D
@ C801 1 2 100P_0402_50V8J
68 FAN_SET
DAC_BRIG/DA0/GPIO3C FAN_SET 6
1

2 1 J1 70 VCTRL KSO4 @ C802 1 2 100P_0402_50V8J


EN_DFAN1/DA1/GPIO3D IREF VCTRL 37
C721 0.1U_0402_16V4Z DA Output IREF/DA2/GPIO3E 71
IREF 37

/
JOPEN KSI0 55 72 AC_SET KSO2 @ C803 1 2 100P_0402_50V8J
2

KSI1 KSI0/GPIO30 DA3/GPIO3F AC_SET 37


56 KSI1/GPIO31
KSI2 57 +5V_TP KSI0 @ C804 1 2 100P_0402_50V8J
KSI3 KSI2/GPIO32 EC_MUTE#

/x
58 KSI3/GPIO33 PSCLK1/GPIO4A 83 EC_MUTE# 29
KSI4 59 84 USB_EN# R579 1 2 10K_0402_5% KSO1 @ C805 1 2 100P_0402_50V8J
KSI5 KSI4/GPIO34 PSDAT1/GPIO4B I2C_INT USB_EN# 30
60 85 R580 1 2 10K_0402_5%
KSI6 KSI5/GPIO35 PSCLK2/GPIO4C I2C_INT 33 KSO5
+3VALW +3VL
61 KSI6/GPIO36 PS2 Interface PSDAT2/GPIO4D 86 @ C806 1 2 100P_0402_50V8J
SYSON SUSP# PCI_RST# +3VS KSI7 62 87 TP_CLK
KSO0 KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E TP_DATA TP_CLK 33 KSI3 @ C807 1
39 88 2 100P_0402_50V8J
KSO1 KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F TP_DATA 33
40

su
KSO1/GPIO21
2

KSO2 41 KSI2 @ C808 1 2 100P_0402_50V8J


KSO2/GPIO22
1

R213 R581 R713 KSO3 42 97 R582 1 2 0_0402_5%


KSO3/GPIO23 SDICS#/GPXOA00 AC_LED# 36
1

8.2K_0402_5% 8.2K_0402_5% 100K_0402_5% KSO4 43 98 KSO0 @ C809 1 2 100P_0402_50V8J


KSO5 KSO4/GPIO24 SDICLK/GPXOA01
KSO5/GPIO25 Int. K/B
@ R124 R583 R721 44 99
10K_0402_5% 10K_0402_5% 10K_0402_5% KSO6 SDIDO/GPXOA02 KSI5 @ C810 1
45 KSO6/GPIO26 Matrix 109 2 100P_0402_50V8J
1

KSO7 SDIDI/GPXID0
46 SPI Device Interface
2

KSO7/GPIO27

p.
KSO8 47 KSI4 @ C811 1 2 100P_0402_50V8J
2

KSO9 KSO8/GPIO28 FRD#


48 KSO9/GPIO29 SPIDI/RD# 119 FRD# 31
KSO10 49 120 R227 1 2 33_0402_5% FWR# KSO9 @ C812 1 2 100P_0402_50V8J
LID_SW# TP_BTN# KSO11 KSO10/GPIO2A SPIDO/WR# SPI_CLK FWR# 31
50
KSO11/GPIO2B SPI Flash ROM SPICLK/GPIO58
126 R228 1 2 47_0402_5%
SPI_CLK 31
KSO12 51 128 R229 1 2 33_0402_5% FSEL# KSI6 @ C813 1 2 100P_0402_50V8J
KSO12/GPIO2C SPICS# FSEL# 31

om
KSO13 52

+3VALW
KSO14
KSO15
53
54
KSO13/GPIO2D
KSO14/GPIO2E
73 CIR_IN
R720 1 2 10K_0402_5% +5VL PV-1 For WWAN noise KSI7 @ C814 1 2 100P_0402_50V8J
KSO15/GPIO2F CIR_RX/GPIO40 VCC1_PWRGD CIR_IN 29 SPI_CLK KSI1
81 74 @ C815 1 2 100P_0402_50V8J
KSO16/GPIO48 CIR_RLC_TX/GPIO41 FSTCHG T84
82 89 FSTCHG 37
KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 STD_ADP
90 STD_ADP 37 1
BATT_CHGI_LED#/GPIO52
1

91 CAPS_LED#
SMB_EC_CK1 CAPS_LED#/GPIO53 BAT_LED# CAPS_LED# 33
R191
10K_0402_5% 33,36 SMB_EC_CK1 77
SCL1/GPIO44 GPIO BATT_LOW_LED#/GPIO54
92 BAT_LED# 33
C327
SMB_EC_DA1 ON/OFFBTN_LED#

yc
78 93 22P_0402_50V8J
33,36 SMB_EC_DA1 SMB_EC_CK2 SDA1/GPIO45 SUSP_LED#/GPIO55 SYSON ON/OFFBTN_LED# 33 2
6 SMB_EC_CK2 79
SCL2/GPIO46 SM Bus SYSON/GPIO56
95
SYSON 26,35,40
SMB_EC_DA2 80 121 VR_ON
6 SMB_EC_DA2 VR_ON 42
2

SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 AC_IN


127
@ R589 1 EC_PME# AC_IN/GPIO59
2 2 1
20 PCI_PME# 0_0402_5% R586 10K_0402_5%

m
SLP_S3# 6 100 EC_RSMRST#
22,29
SLP_S5# SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 EC_RSMRST# 22
22 SLP_S5# 14 101 R588 1 2 EC_LID_OUT# 22
R190 1 EC_SMI# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 EC_ON 0_0402_5%
2 22 EC_SMI# 15 102 EC_ON 38 R254
33 WL_BLUE_BTN OPP@ 0_0402_5% LID_SW# EC_SMI#/GPIO08 EC_ON/GPXO05 WL_BLUE_LED#
33 LID_SW# 16 103 WL_BLUE_LED# 33
ESB_CLK_R LID_SW#/GPIO0A EC_SWI#/GPXO06 PM_PWROK_R 14" INT_KBD
17 104 1 2
SUSP#/GPIO0B ICH_PWROK/GPXO06 PM_PWROK 9,22
ESB_DAT_R
EC_PME#
18
19
//
PBTN_OUT#/GPIO0C
EC_PME#/GPIO0D GPIO
GPO BKOFF#/GPXO08
WL_OFF#/GPXO09
105
106
BKOFF#
M_PWROK BKOFF# 19
M_PWROK 9,22
100_0402_5% CONN.( TYPE "D"
1 @ R591 2 0_0603_5% 25 107 TP_LED#
9 TSATN# EC_THERM#/GPIO11 GPXO10 TP_LED# 33
FAN_SPEED 28 108
6 FAN_SPEED WWAN_POWER_OFF 29
FAN_SPEED1/FANFB1/GPIO14 GPXO11 KB)
26 WWAN_POWER_OFF UTX FANFB2/GPIO15
30 CONN@
R5931 LAN_POWER_OFF_R EC_TX/GPIO16 SLP_S4# JKB
2 31 110
p:
+3VL EC_RX/GPIO17 PM_SLP_S4#/GPXID1 SLP_S4# 22
4.7K_0402_5% ON/OFFBTN 32 112 ENBKL KSO15 1
EC_PME# PCI_RST# 33 ON/OFFBTN ON_OFF/GPIO18 ENBKL/GPXID2 EAPD_CODEC ENBKL 11 KSO10 1
34 114 EAPD_CODEC 28 2
NUM_LED# PWR_LED#/GPIO19 GPXID3 THERM_SCI# KSO11 2
33 NUM_LED# 36
NUMLED#/GPIO1A GPI GPXID4
115 THERM_SCI# 22 3
3
1 1 116 SUSP# KSO14 4
C723 GPXID5 PWRBTN_OUT# SUSP# 26,35,37,39 KSO13 4
117 PWRBTN_OUT# 22 5
tt

C324 C325 15P_0402_50V8J GPXID6 NMI_DBG# +3VL KSO12 5


118 6
0.1U_0402_16V4Z 0.1U_0402_16V4Z CRY2 GPXID7 D16 KSO3 6
1 2 122 7
2 2 XCLK1 +3VL ADP_ID KSO6 7
123 124 2 1 8
XCLK0 V18R KSO8 8
1 9
9
1

AGND
h

Y5 CH751H-40PT_SOD323-2 KSO7 10
GND
GND
GND
GND
GND

10

1
3 4 @ C724 R714 KSO4 11
NC OSC R595 4.7U_0603_6.3V6K 10K_0402_5% KSO2 11
12
20M_0402_5% KB926QFD2_LQFP128_14X14 2 KSI0 12
2 1 13
EMI request
11
24
35
94
113

69

NC OSC KSO1 13
14
For C
2

32.768KHZ_12.5PF_9H03200413 D14 KSO5 14


15

2
NMI_DBG# 15
2 PCI_SERR# KSI3
Revision
1 PCI_SERR# 20 16
CRY1 KSI2 16
1 2 17
+3VL_EC +3VL CH751H-40PT_SOD323-2 KSO0 17
18
C725 KSI5 18
19
ECAGND

15P_0402_50V8J KSI4 19
20
20
1

1
R715 KSO9 21
EC DEBUG port +EC_AVCC L30 150K_0402_5% KSI6 21
22
0_0603_5% KSI7 22
23
UTX @ R233 2 KSI1 23
1 24
0_0805_5% L31 D13 24
25
2

2
R443 AC_IN ACIN G1
1 2 1 2 2 1 ACIN 37 26
G2
1 2 LAN_POWER_OFF_R C726 0.1U_0402_16V4Z 0_0603_5%
25 LAN_POWER_OFF
CH751H-40PT_SOD323-2 ACES_85202-24051
0_0402_5% 1 2 SI-1 Reverse KB connector
+3VL +3VL C791 100P_0402_50V8J
Vendor
Recommend
1

1
R1099 @
R1100 4.7K_0402_5% C315
4.7K_0402_5%
2
10P_0402_25V8K Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/28 Deciphered Date 2006/07/26 Title
2

R731 1 2 0_0402_5% ESB_CLK_R


33 ESB_CLK
33 ESB_DAT
R732 1 2 0_0402_5% ESB_DAT_R
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EC KB926/KB Conn.
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina UMA 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 18, 2009 Sheet 32 of 46
A B C D E

Power Button MV-1 For ESD request, close to JTPSW

SI-1 Delete SW2 for debug only TP_LED#

TP_BTN#
+5VS

2
D65 D66
SM05_SOT23 SM05_SOT23

1 1

1
System LED Conn CONN@
JLED Caps-Lock Conn Keyboard backlight Conn T/P Board (Inculde T/P_ON/OFF)
+5VALW 8 10 CONN@
8 GND CONN@ +5VS R205 JKBL CONN@
+5VS 7 7
6 JCAP 1 2 1 JTPSW

White
+3VS 6 +5VS_LED 1
32 BAT_LED# 5 5 1 1 2 2 1 1 +5VS
4 2 0_0805_5% 3 2 TP_LED# TP_LED# 32
AMBER 21 SATA_LED# 4 2 CAPS_LED# 32 3 2 TP_BTN#
22 HDDHALT_LED# 3 3 3 3 4 4 3 3 TP_BTN# 32
ON/OFFBTN_LED# 2 4 5 4
2 4 GND 4
1 1 GND 9 GND 5 6 GND GND 5
GND 6 GND 6
ACES_87213-0800G P-TWO_161011-04021
P-TWO_161011-04021 P-TWO_161011-04021

/
/x
su
T/P Board Conn
TP_DATA
2 TP_CLK 2

2
SI-1 Change Cap board power rail to +3VL +3VL +5VALW
D28
SM05_SOT23

p.
+5VALW +5V_TP

1
1

1
+5V_TP
ENE@ R51 R53

om
C326 0_0805_5% 0_0805_5% R691 1 2 0_0603_5%
33P_0402_50V8K Main@ OPP@ 1
ESB_CLK_CAP 2 1 C729

SWITCH BOARD.
2

2
0.1U_0402_16V4Z
CONN@
JTP 2
1 +5V_TP
Cypress@ 4.7U_0603_6.3V6K 1
R729 1 1 TP_CLK
32,36 SMB_EC_CK1 2 0_0402_5% 2 TP_CLK 32
2

2
yc
R730 1 2 0_0402_5% C313 3 TP_DATA TP_DATA 32
32,36 SMB_EC_DA1 2 3
Cypress@ D67 4
4
SM05_SOT23 5
OPP@ R151 +5VS GND
32 WL_BLUE_BTN 1 2 0_0402_5% GND
6
WL_BLUE_LED# OPP@ R1191 1 2 0_0402_5% JCSB CONN@ 1 1
1 P-TWO_161011-04021

1
1

m
2 @ C730 @ C731
ENE@ 2 100P_0402_50V8J 100P_0402_50V8J
32 ON/OFFBTN_LED# 3
R56 1 ESB_CLK_CAP 3 2 2
32 ESB_CLK 2 FBMA-11-100505-801T 0402 4
R149 1 ESB_DAT_CAP 4
32 ESB_DAT 2 FBMA-11-100505-801T 0402 5
5
32 I2C_INT
ENE@ Close to JP59 6
6 MV-1 For ESD request, close to JTP
+5VALW
32 LID_SW#
main@1
R169
2
1.8K_0402_5%
// 7
8
7
8
32 ON/OFFBTN 1 2 9
3 R238 1K_0402_1% 9 3

Mini card LED


10
10
11
GND
12
GND +3VS
p:
3

P-TWO_161021-10021

1
R1192 1 2 0_0402_5%
32 NUM_LED#
OPP@
C1518 0.1U_0402_16V4Z R193
1 2 10K_0402_5%
tt

@ D60 SM05_SOT23
1

2
MV-1 For ESD request, close to JCSB WL_BLUE_LED# 32
h

Q11
2N7002_SOT23-3

1
D

30 BT_LED 2
G

1
S

3
R716
100K_0402_5%

2
D24

26 WL_LED# 2
1 WL_BLUE_LED#
26 WW_LED# 3

PSOT24C_SOT23-3
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/08/28 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
KBD, ON/OFF, SW, CIR
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina UMA 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 18, 2009 Sheet 33 of 46
A B C D E
5 4 3 2 1

+3VS_LS +3VS_LS

R648
11 TMDS_B_DATA2# TMDS_B_DATA1 11
11 TMDS_B_DATA2 TMDS_B_DATA1# 11 +3VS 1 2 +3VS_LS

10U_0805_6.3V6M
0.01U_0402_16V7K

0.1U_0402_10V6K

0.1U_0402_10V6K
0_0603_5%
11 TMDS_B_CLK# TMDS_B_DATA0 11
11 TMDS_B_CLK TMDS_B_DATA0# 11
2 1 1 1
+3VS_LS

C321

C320

C319
EQUALIZATION SETTING:

C318
[PC1,PC0]=00,8dB +3VS_LS 1 2 2 2

48

47

46

45

44

43

42

41

40

39

38

37
[PC1,PC0]=01,4dB (Recommanded)

1
@ R1240 U43
D [PC1,PC0]=10,12dB +3VS_LS 4.7K_0402_5% D

IN_D4-

IN_D3-

IN_D2-

IN_D1-
IN_D4+

IN_D3+

IN_D2+

IN_D1+
VCC3V

VCC3V
GND

GND
[PC1,PC0]=11,0dB @ R1241 2 1 4.7K_0402_5% +3VS_LS

1
@ R1201 R1242 @ R1202 2 1 4.7K_0402_5% +3VS_LS

2
1
4.7K_0402_5% 1 2 1 36
+3VS_LS @ R1243 0_0402_5% GND GND
4.7K_0402_5% +3VS_LS 2 35 0_0402_5% 2 1 R1203

2
VCC3V FUNCTION4
1 2 3 PC0 34 0_0402_5% 2 1 R1205

2
R1204 4.7K_0402_5% FUNCTION1 FUNCTION3
1 2 4 PC1 33 R1245 2 1 0_0402_5% +3VS_LS
FUCNTION2 VCC3V
1

@ R1244 0_0402_5% @ R1246 2 1 0_0402_5%


R649 R650 5 32 R651 2 1 4.7K_0402_5% +3VS_LS
2.2K_0402_5% 2.2K_0402_5% R653 3.9K_0402_1% GND DDC_EN @ R652 0_0402_5%
2 1
2 1 6 ANALOG1(REXT) GND 31
2

TMDS_B_HPD 7 30 HDMI_DETECT
HPD_SOURCE HPD_SINK
8 29 HDMIDAT +3VS_LS
9 HDMIDAT_NB SDA_SOURCE SDA_SINK
9 28 HDMICLK
9 HDMICLK_NB SCL_SOURCE SCL_SINK

1
/
@ R1247 4.7K_0402_5%
1 2 10 27 2 1 +3VS_LS R654
R1206 0_0402_5% R1248 0_0402_5% ANALOG2 GND 10K_0402_5%

/x
+3VS_LS 1 2 11 VCC3V VCC3V 26 +3VS_LS 1 2
@ R1250 4.7K_0402_5% R1249 0_0402_5%

2
1 2 1 2 12 GND OE* 25 2 1
R655 0_0402_5%

OUT_D4+

OUT_D3+

OUT_D2+

OUT_D1+
OUT_D4-

OUT_D3-

OUT_D2-

OUT_D1-

1
@C1517 2.2U_0603_6.3V4Z D Q108
49

VCC3V

VCC3V
@ R1251 4.7K_0402_5% thm_pad HDMI_DETECT 2

GND

GND
+3VS_LS 1 2 G

su
S

3
C 2N7002_SOT23-3 C
1 2

13

14

15

16

17

18

19

20

21

22

23

24
+3VS_LS R1252 0_0402_5% S IC STHDLS101TQTR QFN 48P HDMI SHIFTER
1

p.
R1207 HDMI_TX_0-
20K_0402_5% @C769 @ R656 @ R657 @C770
HDMICLK+ 1 2 1 2 HDMI_TX_0+
68_0402_5% 68_0402_5%
2

R9 HDMICLK- 0.5P_0402_50V8B +3VS_LS +3VS_LS 0.5P_0402_50V8B

om
TMDS_B_HPD# 2 1 TMDS_B_HPD
11 TMDS_B_HPD#
HDMI_TX_1-
0_0402_5% @C771 @ R658 @ R659 @C772
HDMI_TX_2+ 1 2 1 2 HDMI_TX_1+
1

68_0402_5% 68_0402_5%
R1208 HDMI_TX_2- 0.5P_0402_50V8B 0.5P_0402_50V8B
7.5K_0402_1%

yc
SI-1 Use ST only
2

To option use ST or Parade

HDMI Connector

m
@ R1212 0_0402_5%
1 2 +5VS
C273
@
L38
Parade Parade
HDMICLK- HDMI_CLK-
ST 8101T 8171 1 2
1 2
1 2
R1240 X X X
// 2200P_0402_25V7K

2
WCM-2012-900T_0805
HDMICLK+ 4 3 HDMI_CLK+
B 4 3 R1242 0 ohm 0 ohm 4.7K ohm RB411D T146 _SOT23-3 B
D31
R1201 X 4.7K ohm X
1 2

1
@ R1213 0_0402_5% +5VS_HDMI
R1204 4.7K ohm X 4.7K ohm
p:

@ R1214 0_0402_5%
R1243 X X 4.7K ohm 1 1
1 2

3.9K_0402_1%

3.9K_0402_1%
0.1U_0402_16V4Z C314 @
R1244 X X X

1
L39 C773 2200P_0402_25V7K
tt

HDMI_TX_0- 1 2 HDMI_TX0- 2 2
1 2 R653 3.9K ohm 499 ohm 499 ohm

R49

R50
WCM-2012-900T_0805
HDMI_TX_0+ HDMI_TX0+
R1206 0 ohm X X
4 3

2
4 3
h

C1517 X X 2.2uF JHDMI1


1 2 R1248 0 ohm 0 ohm X 18
@ R1215 0_0402_5% HDMIDAT +5V
16 13
R665 L40 HDMICLK SDA CEC
R1250 X X 4.7K ohm 15 14
@ R1216 0_0402_5% HDMI_DETECT SCL Reserved
1 2 1 2 19
1K_0402_1% HP_DET
1 2 R1251 X X 4.7K ohm 2
GND
1

FBML10160808121LMT_0603 1 HDMI_CLK- 12 5
L41 HDMI_CLK+ CK- GND
HDMI_TX_1- HDMI_TX1-
R1252 0 ohm 0 ohm X D32 HDMI_TX0-
10
CK+ GND
8
1 2 9 11
1 2 SKS10-04AT_TSMA C774 HDMI_TX0+ D0- GND
WCM-2012-900T_0805
R1247 X X 4.7K ohm 330P_0402_50V7K 2 HDMI_TX1-
7
D0+ GND
20
6 21
2

HDMI_TX_1+ HDMI_TX1+ HDMI_TX1+ D1- GND


4 3 R1249 0 ohm 0 ohm X 4 22
4 3 HDMI_TX2- D1+ GND
3 23
HDMI_TX2+ D2- GND
R1245 0 ohm 0 ohm X 1 17
D2+ DDC/CEC_GND
1 2
@ R1217 0_0402_5%
R1246 X X 4.7K ohm SUYIN_100042MR019S153ZL
@ R1218 0_0402_5% CONN@
A R1203 0 ohm X 4.7K ohm A
1 2

L42
R1241 X X X
HDMI_TX_2- 1 2 HDMI_TX2-
1 2 R1205 0 ohm X X
WCM-2012-900T_0805
HDMI_TX_2+ HDMI_TX2+
R1202 X X 4.7K ohm
4 4 3 3
C773 0.1uF 1uF 1uF Security Classification Compal Secret Data Compal Electronics, Inc.
1 2 R1207 V X X Issued Date 2007/08/28 Deciphered Date 2006/03/10 Title
@ R1219 0_0402_5%
R1208 V X X THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDMI LS & Conn.
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Montevina UMA 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 18, 2009 Sheet 34 of 46
5 4 3 2 1
5 4 3 2 1

+5VALW to +5VS +3VALW to +3VS DIM LED +5VS


Q15
+5VS_LED

+5VALW Transfer SI7326DN-T1-E3_PAK1212-8


U32
+5VS
B+ Transfer +3VALW
SI7326DN-T1-E3_PAK1212-8 +3VS
U33
SI2301BDS-T1-E3_SOT23-3

D
1 1 3 1
B+ 2 2

10U_0805_10V4Z

10U_0805_10V4Z
0.1U_0402_16V4Z

0.1U_0402_16V4Z
5 3 5 3 1

1
10U_0805_10V4Z
C294

G
1 1 1 1 1

2
1
1 C761 C762 R636 C759 C763 C764 0.1U_0402_16V4Z
1

C760 R637

4
D R223 330K_0402_5% 10U_0805_10V4Z 10K_0402_5% 2 D
2 2 2 2 2

2
330K_0402_5% 2

2
DIM_LED#
2

RUNON_3VS

1
3

1
RUNON R638 D

1
DIM_LED 2 Q35
32 DIM_LED
6

470_0402_5% G 2N7002_SOT23-3
R224 SUSP 5 S

3
470_0402_5% 1
SUSP 2 C765

4
Q34B
1 0.01U_0402_16V7K
1

Q34A 2
C65 2N7002DW-7-F_SOT363-6
2N7002DW-7-F_SOT363-6 4700P_0402_25V7K
2

/
+1.8V to +1.8VS

/x
Transfer +1.8V
SI7326DN-T1-E3_PAK1212-8
+1.8VS
U34 @
+3VL +3VL
SI-1 For EMI DDR issue
1 SI-R 2 caps and change to GND

su
2 +1.8V
C C
10U_0805_10V4Z
0.1U_0402_16V4Z

5 3

1
1 1
10U_0805_10V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
@ C767 @ C768 R639 R640
1 1 1 1 1
4

@ C766 100K_0402_5% 100K_0402_5% C1512 C1513 C1514 C1515

p.
2 2

2N7002DW-7-F_SOT363-6

2N7002DW-7-F_SOT363-6
2

2
RUNON SYSON# SUSP
2 41 SYSON# SUSP 41 2 2 2 2

om
Q13A Q13B

SYSON 2 5 SUSP#
26,32,40 SYSON SUSP# 26,32,37,39

4
yc
m
H1 H2 H3 H4 H5 H6 H7 H8 H9

Discharge circuit
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
//

1
+5VS +3VS +1.5VS +VCCP +1.8V +0.9V +1.8VS
B B
H10 H11 H12 H13
1

1
HOLEA HOLEA HOLEA HOLEA
R641 R642 R644 R645 R643 R646 @ R647
p:

470_0402_5% 470_0402_5% 470_0402_5% 470_0402_5% 470_0402_5% 470_0402_5% 470_0402_5%

1
2

2
2N7002DW-7-F_SOT363-6

2N7002DW-7-F_SOT363-6

2N7002DW-7-F_SOT363-6

2N7002DW-7-F_SOT363-6

2N7002DW-7-F_SOT363-6

2N7002DW-7-F_SOT363-6
tt
6

3
FM1 FM2 FM3 FM4

1
Q6A Q6B Q9A Q9B Q12A Q12B D @ Q44 1 1 1 1
SUSP 2
h

SUSP 2 SUSP 5 SUSP 2 SUSP 5 SYSON# 2 SUSP 5 G


S

3
2N7002_SOT23-3 T21 T32
1

4
T33 T34
T45 T51
T52 T53
T60 T61 For ICT
T62 T63
T64 T72
T73 T74
T75 T76

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/08/28 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC/DC Interface
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina UMA 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 18, 2009 Sheet 35 of 46
5 4 3 2 1
A B C D

+3VALW
PQ3

3
TP0610K-T1-E3_SOT23-3
+3VL
1 PR9 2 BATT
100K_0402_5% connect to KBC pin97
2 AC_LED# 32

340K_0402_1%
PR1 1
1 +5VALW 1

<BOM Structure>

ADP_ID 32

0.01U_0402_25V7K
2 1

2
PC12

1
PC1
499K_0402_1%
1

PR4 1
PR8 PD4 @1000P_0402_50V7K
2K_0402_5% PR2

2
10K_0402_5%
JDC1 <BOM Structure> VIN

2
1

2
6 RLZ3.6B_LL34

2
GND

8
5 ADP_SIGNAL 1 2 PR5
GND PR3 10K_0402_5%
4 3

P
4 10K_0402_5% +
3 3 0 1 2 1 BATT_OVP 32
2 PL1 2
2 -

G
1 HCB2012KF-121T50_0805

105K_0402_1%
1

PR6 1
ADPIN 1 2

0.01U_0402_25V7K

4
1
PL2 PU1A
ACES_87302-0441

PC6
HCB2012KF-121T50_0805 LM358ADT_SO8

/
1 2

100P_0402_50V8J

2
1000P_0402_50V7K

2
2

PD1

100P_0402_50V8J

/x
1

1
PC5
PC4
PC3

2
PC2
1000P_0402_50V7K
PJSOT24C_SOT23-3
1

su
2 2

p.
om
VMB
PL3 BATT
JBATT HCB2012KF-121T50_0805
1 1 1 2

yc
PL4
2 2
3 EC_SMD HCB2012KF-121T50_0805
PH1 under CPU botten side :
3 EC_SMC
4 4
5
1 2 CPU thermal protection at 90 +-3 degree C
5
1

1
6 6

m
GND 7 PD2
8 PC8 PC9
2

2
GND 1000P_0402_50V7K 0.01U_0402_50V4Z PR7
3
1 +5VS 604K_0402_1%
PD3
2
CPU 1 2
SUYIN_200045MR006G101ZR 3
//
1 PJSOT24C_SOT23-3
3 2 3
1
1

1
PJSOT24C_SOT23-3
p:

PR14 PH1
PR13 100_0402_5% 10K_TH11-3H103FT_0603_1%
100_0402_5%
2

EN0 38
2

2
SMB_EC_DA1 SMB_EC_DA1 32,33 PR10

8
tt

200K_0402_1%
D

1
1 2 5

P
SMB_EC_CK1 + PQ1
SMB_EC_CK1 32,33 0 7 2
+5VALW 1 2 6 G SSM3K7002FU_SC70-3
-

G
h

BAT_ID 37 PR11 PU1B S

3
1
150K_0402_1%

4
1

1
LM358ADT_SO8

1
PC10 PR12
PR16 2.49K_0402_1%
6.49K_0402_1% +3VL 0.22U_0603_10V7K PR15
2

1 2 150K_0402_1% PC11
2

2
1000P_0402_50V7K

2
1

PR17
1K_0402_5%
BATT_TEMP 32
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/05/29 Deciphered Date 2008/05/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC Connector/CPU_OTP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina Consumer Discrete 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: W ednesday, February 18, 2009 Sheet 36 of 46
A B C D
A B C D

P4 B+

BATT
VIN P2
PQ102
AO4433 1P SO8
PR102
1 8
PQ101 PQ103 PL101
1 4 2 7
AO4433 AO4433 HCB2012KF-121T50_0805 3 6
8 1 1 8 2 3 1 2 CHG_B+ 5
7 2 2 7 PR103
6 3 3 6 47K_0402_5%

4
5 5 1 2 0.012_2512_1% 1 2

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
PR101 VIN

1
47K_0402_5% PR104 ACDET PC102
47P_0402_50V8J

1
1 1
0_0402_5%

PC103

PC104

PC105
1 2 1U_0603_6.3V6M

0.1U_0603_25V7K
32 AC_SET 1 2 ACSET

2
1

3
PR105
PC101

1
10K_0402_5%

2 Structure>

PC108
0.47U_0603_16V7K

1
2

2
1

ACN
PR140

ACP
2 PC107 ACOFF#

200K_0402_5%

2
1

@0.01U_0402_16V7K 100K_0402_5%

PC106

PR106

1
<BOM Structure>

2
<BOM
PR107 CHGEN# CHG_B+

2
47K_0402_1% PQ104 PR108
1 2 2 DTA144EUA_SC70-3 10_1206_5%
1

1
1 2 2 ACOFF 32

LPMD

ACN

CHGEN
LPREF

ACSET

ACDET

ACP
PQ105 29
TP

5
6
7
8
DTC115EUA_SC70-3 PR110 PC110 PQ108
3

PQ107 0_0402_5% 1U_0805_25V6K

3
1

SSM3K7002FU_SC70-3 D PR109 AO4466_SO8 PQ106


26,32,35,39 SUSP# 1 2 8 28 1 2
150K_0402_5% IADSLP PVCC PR142 DTC115EUA_SC70-3
2
G 0_0402_5% PC111

2
S 9 27 BST_CHG1 2 1 2 4
3

AGND BTST PR139


BQ24740VREF
PACIN_1 38
PC112 PU101
BQ24740RHDR_QFN28_5X5
0_0402_5%
DH_CHG
0.1U_0402_10V7K BATT
1 2 10 26 1 2
VREF HIDRV PL102 PR112

3
2
1
PR111 PQ109 1U_0603_6.3V6M +3VL 10U_LF919AS-100M-P3_4.5A_20% 0.015_1206_1%
1

/
3K_0402_1% D LX_CHG
11 25 1 2 1 2
PACIN SSM3K7002FU_SC70-3 VDAC PH
1 2 2

1
G PD102

5
6
7
8
S PR113 VADJ 12 24 REGN 2 1 PR141

/x
3

PD101 143K_0402_1% VADJ REGN @4.7_1206_5%


ACOFF# 1 2 PR114 1SS355_SOD323-2

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
@0_0402_5% 13 23 DL_CHG <BOM Structure>

2 2
EXTPWR LODRV

1
1SS355_SOD323-2 32 VCTRL 1 2

PC113

PC114

PC115

PC116

PC128
<BOM Structure> 4

1
14 22 S TR AO4468 1N SO8 PC135

2
ISYNSET PGND
1

@470P_0603_50V8J

DPMDET

1
1

su
PC117 PR115 PQ110

IADAPT
1 2

SRSET

CELLS

1
1U_0603_10V6K 100K_0402_1% PC119

SRN
2

SRP
2
2

3
2
1
BAT
PR116
2

15K_0402_1% 1U_0603_10V6K PC118

2
0.1U_0402_10V7K

15

16

17

18

19

20

21
PR117
100K_0402_5% BQ24740VREF

p.
IADAPT
PR118 1 2

1
10K_0402_5%
1 2
32 ADP_I 47K_0402_5%

1
D PR119

100P_0402_50V8J
0.22U_0603_10V7K
1

1
PQ111

om
2 BAT_ID 36

2
SSM3K7002FU_SC70-3
PC120

PC121
G
S

BATT
2

3
Charge Detector

0.1U_0603_25V7K
yc
VIN
PR120
2 1 IREF 32

1
133K_0402_1%

PC124
2

1
PC123
PD104 0.1U_0402_10V7K 1 PR122

2
1SS355_SOD323-2 PR121 681K_0402_1%
200K_0402_1% 1 2

m
2

PR123
1

2
1M_0402_5%
1 2
1VIN_1

+3VL
// VIN
PR124
1K_0402_5%
VIN
1 2
3
PR125 +3VL ACIN 32 3

1
47_1206_5%
PR126
1

100K_0402_1% PR127
10K_0402_5%
2

VIN
p:
PR130 10K_0402_1%
1

8
+3VL 2.15K_0402_1% PU102B
PR128
10K_0402_1%

2
1 2 5

P
+
1

PACIN
PR129

7
2

O
1

PR131 6
100K_0402_5%

G
133K_0402_1% PC125 CHGEN#
2

1
0.1U_0603_25V7K PC126 LM393DG_SO8
tt
PR132

PR133
2

1
0.047U_0402_16V7K 10K_0603_0.1%
2

PR134
2

2
1

D PD103
3 10K_0402_5%
P

2
+ PQ112 RLZ4.3B_LL34
1 2
O
1

SSM3K7002FU_SC70-3
h

2 G

2
-
G

PU102A S
PR135
3

LM393DG_SO8 FSTCHG#
4

10K_0603_0.1% PR136
60.4K_0402_1%
2

D
1
<BOM 2 VIN_1
Structure>
1.24VREF 32 FSTCHG 2 PQ113
G SSM3K7002FU_SC70-3
S
3

STD_ADP 32
PU104

4 3 1.24VREF
ACDET REF CATHODE
1 2

1
PC127 2
PR137 NC
22P_0402_50V8J
1

20K_0402_1% 5 1
100K_0402_1%

2
ANODE NC
PR138

LMV431ACM5X_SOT23-5
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/05/29 Deciphered Date 2008/05/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Charger
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4481P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 18, 2009 Sheet 37 of 46
A B C D
A B C D E

2VREF_51125

1
PC302
0.22U_0603_10V7K

2
1 1

PR301 PR302
13.7K_0402_1% 30.9K_0402_1%
1 2 1 2

PR303 PR304
B+ B++
20K_0402_1% 20K_0402_1%
B++
PL301 1 2 1 2
HCB2012KF-121T50_0805

1 2 +3VLP

ENTRIP2

ENTRIP1
PR305 PR306
2200P_0402_50V7K

2200P_0402_50V7K

10U_1206_25V6M

0.1U_0402_25V6
4.7U_0805_25V6-K

115K_0402_1% 90.9K_0402_1%
1

1
0.1U_0402_25V6

1 2 1 2
1

1
PC301

PC303

PC304

PC305

PC313
PC316

PQ301
2

S TR AON7408L 1N DFN
2

2
6

5
/
PQ302

1
PC306

ENTRIP2

VFB2

TONSEL

VFB1

ENTRIP1
VREF
4 10U_0805_6.3V6M 25 S TR AON7408L 1N DFN
P PAD

/x
2
UG1_3V
7 VO2 VO1 24 4

1
2
3
8 23 PR308 PC308
PR307 VREG3 PGOOD 2.2_0402_5% 0.1U_0402_10V7K
PR309 1 2 1 2 BST_3V 9 22 BST_5V 1 2 1 2 PR310

su

3
2
1
0_0402_5% 0_0402_5% VBST2 VBST1 0_0402_5%
2 PL302 PC307 UG_3V UG_5V PL303 2
1 2 10 DRVH2 DRVH1 21 1 2
4.7UH_SIQB74B-4R7PF_4A_20% 0.1U_0402_10V7K 4.7UH_PCMC063T-4R7MN_5.5A_20%
2 1 LX_3V 11 20 LX_5V 1 2 +5VALWP
+3VALWP LL2 LL1
5

5
LG_3V 12 19 LG_5V
DRVL2 DRVL1

1
p.

@4.7_1206_5%
PQ303

SKIPSEL
1
@4.7_1206_5%

PR316
S TR AON7406L

VREG5
1
PR315

VCLK
PC309 PR312 1

GND
EN0

VIN
+ 1M_0402_5%
150U 6.3V B2 R45M

@680P_0603_50V8J
4 1 <BOM Structure>
2 4 + PC310
B++

2
om
@680P_0603_50V8J

PU301 150U 6.3V B2 R45M


2

13

14

15

16

17

18
2 RT8205AGQW WQFN 24P

1
2

PC315
1

1
36 EN0
PC314

1
2
3

3
2
1
VL PR317

2
PR311
2

191K_0402_1% 1 2 R_EC_RSMRST# 22

1
yc
PC311 0_0402_5% PQ304
10U_0805_10V6K

2
S TR AON7702L 1N DFN

1
m
B++
PC312

2
0.1U_0603_25V7K
ENTRIP1

2VREF_51125
ENTRIP2

//
3 3
1

D D
PQ305 2 2 PQ306
p:

SSM3K7002FU_SC70-3 G G SSM3K7002FU_SC70-3
S S +3VLP +3VL
3

PJP301
PJP302 2 1
+5VALWP 1 2 +5VALW (4.5A,180mils ,Via NO.= 9)
tt

PR313 PAD-OPEN 2x2m


100K_0402_5%
PAD-OPEN 4x4m
1 2 VL PJP303
h

+3VALWP
1 2 +3VALW (3A,120mils ,Via NO.= 6) VL +5VL
PQ308 PQ307
1

@SSM3K7002FU_SC70-3 D D SSM3K7002FU_SC70-3 PJP304


PAD-OPEN 4x4m
1 2 2 2 2 1
37 PACIN_1 PR318 G G EC_ON 32
604K_0402_1% S S PAD-OPEN 2x2m
3

<BOM Structure>
1

PC318
0.047U_0603_16V7K PR314
2

100K_0402_5%
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
3.3VALWP/5VALWP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4481P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 18, 2009 Sheet 38 of 46
A B C D E
5 4 3 2 1

PR501 PR502
29.4K_0402_1% 75K_0402_1% PR503 PR504
10.2K_0603_0.1% 10.2K_0603_0.1%
+1.05V_VCCP 1 2 1 2 1 2 1 2 +1.5VSP
B+++
D D

2
PR505 B+++ B+
0_0402_5% PL502

2200P_0402_50V7K

0.1U_0402_25V6
HCB2012KF-121T50_0805
4.7U_0805_25V6-K

4.7U_0805_25V6-K 2 1

1
1

1
PC501

PC503

PC502

PC520
2

4.7U_0805_25V6-K

2200P_0402_50V7K

0.1U_0402_25V6
@4.7U_0805_25V6-K
1
8
7
6
5

5
6
7
8

1
PQ502 PU501

PC516

1
PQ501

PC504

PC505

PC521
VO2

VFB2

TONSEL

VFB1

VO1
GND

2
AO4466_SO8

/
25

2
P PAD

2
/x
4 7 PGOOD2 PGOOD1 24 4
PC507
PC506 PR506 8 23 PR507
EN2 EN1 0.1U_0402_10V7K
0.1U_0402_10V7K 0_0402_5% 0_0402_5%
+1.05V_VCCP 2 1 2 1 BST_1.05V 9 22 BST_1.5V 2 1 1 2 AO4466_SO8
1
2
3

3
2
1
VBST2 VBST1
+1.5VSP

su
PL503 UG1_1.05V 2 1 UG_1.05V 10 21 UG_1.5V 2 1 UG1_1.5V PL501
C 2.2UH_PCMC063T-2R2MN_8A_20% 0_0402_5% PR508 DR VH2 DR VH1 PR509 3.3UH 30% MSCDRI-7030AB-3R3N 4.1A C
2 1 LX_1.05V 11 20 LX_1.5V 0_0402_5% 1 2
LL2 LL1
LG_1.05V 12 19 LG_1.5V
DR VL2 DR VL1
8
7
6
5

p.
1

5
6
7
8
PQ504

PGND2

PGND1
1

V5FILT

1
TRIP2

TRIP1
PR515 PQ503 1

V5IN
1

+ 4.7_1206_5% PR516
PC517

220U_B2
<BOM Structure>
220U 2.5V B2

2
PC509 @4.7_1206_5% +

PC508
om
4.7U_0805_6.3V6K 4 TPS51124RGER_QFN24_4x4 PC510
2

1 2

13

14

15

16

17

18
2 4.7U_0805_6.3V6K
4

1 2

1
2

2
PC518
1
2
3

<BOM Structure> 820P_0603_50V7K PR510 PR511 PC519 AO4468_SO8

3
2
1
15.8K_0402_1% 9.53K_0402_1% @680P_0603_50V7K
1 2

yc 1
IRF8707TRPBF_SO8
PR513
0_0402_5% PR512
2 1 0_0402_5%
26,32,35,37 SUSP#

m
1 2
1 2 SUSP# 26,32,35,37
+5VALW
PR514
3.3_0402_5%
//
1

1
B PC514 PC515 PC512 B
1U_0603_10V6K 4.7U_0805_10V6K @0.1U_0402_16V7K
PC513
2

2
p:

@0.1U_0402_16V7K

PJP501
tt

+1.5VSP 1 2 +1.5VS (7A,280mils ,Via NO.=14)


PAD-OPEN 4x4m
h

PJP502
+1.05V_VCCP 1 2 +VCCP (6A,240mils ,Via NO.= 12)
PAD-OPEN 4x4m

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/05/29 Deciphered Date 2008/05/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.5VP/1.05V_VCCP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina Consumer Discrete 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: W ednesday, February 18, 2009 Sheet 39 of 46
5 4 3 2 1
A B C D

1 1

PR401
0_0402_5%
1 2 PL401
26,32,35 SYSON
HCB1608KF-121T30_0603
1.8V_B+ 1 2 B+

2200P_0402_50V7K
0.1U_0402_25V6

4.7U_0805_25V6-K

4.7U_0805_25V6-K
PC401
@1000P_0402_50V7K S TR AON7408L 1N DFN

1
+5VALW
PQ401 PC406

PC414

PC403

PC404

PC405
BST_1.8V1 2 BST1_1.8V 1 2 @680P_0402_50V7K

2
PR402 PC402

1
0_0402_5% 0.1U_0402_10V7K 4

/
PR403

15

14
1

DH1_1.8V
316_0402_1% PU401
PR404

EN_PSV

TP

VBST

/x
255K_0402_1%
PR411

3
2
1
1 2 2 13 DH_1.8V 1 2 PL402
TON DRVH 2.2UH_PCMC063T-2R2MN_8A_20%
PR405 0_0402_5%
+1.8VP 2 1 3 12 LX_1.8V 1 2 +1.8VP
VOUT LL

4.7U_0805_6.3V6K
0_0402_5%

1
4 11 1 2

su

220P_0603_50V8J
V5FILT TRIP

5
PR406 PQ402 PR407
1

220U_2.5V _B2
2 2

1
5 10 +5VALW 10K_0402_1% 4.7_1206_5%
VFB V5DRV S TR AON7702L +

PC408

PC407

PC410
1

PC409 6 9 PC415

2 2

2
PGOOD DRVL

1
PGND
1U_0603_10V6K 4.7U_0805_10V6K

GND
2

p.
4
2

PC412

2
+1.8VP TPS51117RGYR_QFN14_3.5x3.5 180P_0402_50V8J
PR408

1
1 2
14.3K_0603_0.1%

om

3
2
1
DL_1.8V
1

yc
PR409
10K_0603_0.1%
2

m
//
3 3
p:
tt

PJP401
+1.8VP 1 2 +1.8V (7A,280mils ,Via NO.=14)
h

PAD-OPEN 4x4m

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/05/29 Deciphered Date 2008/05/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.8VP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina Consumer Discrete 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: W ednesday, February 18, 2009 Sheet 40 of 46
A B C D
5 4 3 2 1

D D

+1.8V

PU601
1 VIN VCNTL 6 +5VALW

@10U_0805_10V4Z
2 GND NC 5

PC602

1
PC601 3 7
VREF NC

1
10U_0805_10V4Z

2
PR601 PC603

/
4 VOUT NC 8
1K_0402_1% 1U_0603_16V6K

2
9

2
TP

/x
S IC RT9173DPSP SO 8P

35 SYSON# 1 2
PR602 +0.9VP

0.1U_0402_16V7K
1
C C
@0_0402_5%
PQ601
SSM3K7002FU_SC70-3 PR603

su
1
D

1
1K_0402_1%
1 2 2 PC605
35 SUSP

2
G 10U_0805_6.3V6M

PC604
PR604

2
0_0402_5% S

3
1
PC606

p.
2
@0.1U_0402_16V7K

om
yc
PJP601

+0.9VP 1 2 +0.9V (2A,80mils ,Via NO.= 4)

m
B PAD-OPEN 3x3m B

//
p:
tt
h

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2006/11/23 Deciphered Date 2007/11/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
0.9VP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina Consumer Discrete 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 18, 2009 Sheet 41 of 46
5 4 3 2 1
5 4 3 2 1

+5VS

B+
CPU_B+

2
7

7
7

7
CPU_VID6

CPU_VID5

CPU_VID4

CPU_VID3

CPU_VID2

CPU_VID1

CPU_VID0
PR202 PL201
SMB3025500YA_2P

32
1_0603_5%

VR_ON
2 1

1
D D

100U_25V_M

@100U_25V_M
470P_0402_50V7K

2200P_0402_50V7K

@1000P_0402_50V7K

@2200P_0402_50V7K
@47P_0402_50V8J
4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K

1000P_0402_50V7K
1 1

1
PC233

PC234

PC205

PC206
PR201 499_0402_1%

1
+ +

PC242

PC207

PC204

PC239

PC208

PC240
9,22 DPRSLPVR 1 2 PC203

5
6
7
8

PC237

PC243
PC202 2.2U_0603_6.3V6K

2
PR203 0_0402_5% 0.022U_0402_16V7K

2
2 2

PR208

PR209

PR210

PR211

PR212

PR205

PR213
PR207
7,9,21 H_DPRSTP# 1 2 PQ201

PR204 0_0402_5% IRF8714TRPBF 1N SO8


17 CLK_ENABLE# 1 2 4

1
1

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%
0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%
PR206 0_0402_5%
+3VS 1 2

3
2
1
+3VS

1U_0603_6.3V6M

2
2
2.2_0603_5% 0.22U_0603_10V7KUGATE_CPU1-2 PL202

1.91K_0402_1%

1
PC201
PR214 PC209 0.36UH +-20% PCMC104T-R36MN1R17
1

BOOT_CPU1 1 2 1 2 2 1 +VCC_CORE
2

5
PR216

PR215

1
10K_0402_1%
2.2_1206_5%

PC210 @4.7_1206_5%

3.65K_0805_1%

47P_0402_50V8J

<BOM Structure>
1
/
PR218

PR245

PR219

PR220
@499_0402_1% PQ203

49

48

47

46

45

44

43

42

41

40

39

38

37
1 2
0_0603_5% PR223
2

1
PR217 TPCA8036-H 1N SOP-ADV 1_0402_5%

GND

3V3

CLK_EN#

DPRSTP#

DPRSLPVR

VR_ON

VID6

VID5

VID4

VID3

VID2

VID1

VID0
1

/x

PC244
4 PR224

1 2

680P_0603_50V7K 2

2
1 36 @0_0603_5%

2
17,22 VGATE PR247 PGOOD BOOT1
1 2
7 H_PSI# 2 1 PSI# 2 35 UGATE_CPU1-1 VSUM PC211
PSI# UGATE1
1 2

3
2
1

2
1 PR221 2 0_0402_5% 3 34 PHASE_CPU1 VCC_PRM
@0_0402_5% PR222 147K_0402_1% PMON PHASE1 ISEN1

su
1 2 4 33 0.22U_0603_10V7K CPU_B+
C RBIAS PGND1 C
VR_TT# 5 32 LGATE_CPU1
VR_TT# LGATE1

2200P_0402_50V7K

1000P_0402_50V7K
5
6
7
8

2200P_0402_50V7K
6 31

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
NTC PVCC

1
IRF8714TRPBF 1N SO8

p.

1
PC212

PC213

PC235

PC236
7 30 LGATE_CPU2
SOFT LGATE2

1
PC241

PC214
S IC ISL6266AHRZ-T QFN 48P PW M PQ204

PC238
8 29

2
0.022U_0603_25V7K PC215 OCSET PGND2
4

2
om
1 2 9 28 PHASE_CPU2
VW PHASE2 PR225
PR226 13K_0402_1% 10 27 UGATE_CPU2-1 1 2 UGATE_CPU2-2
COMP UGATE2 0_0603_5% 0.36UH +-20% PCMC104T-R36MN1R17
1 2

3
2
1
11 26 BOOT_CPU2
1 2 1 2 2 1
FB BOOT2 PR227 PL203
1 2

1
DROOP

1000P_0402_50V7K PC216 2.2_0603_5% PC217

2.2_1206_5%

PC219 @4.7_1206_5%

47P_0402_50V8J
12 25

<BOM Structure>
FB2 NC

1
VDIFF

VSUM

ISEN2

ISEN1
VSEN

PR229

PR246

10K_0402_1%
PR228 13K_0402_1% 0.22U_0603_10V7K

3.65K_0805_1%
GND

VDD
RTN

DFB

1
VIN

yc

PR231
VO

1 2 PR232

1
PR230

PC245
1 2 PU201
13

14

15

16

17

18

19

20

21

22

23

24

1 2

2
4 1_0402_5%

2
PC218 1000P_0402_50V7K

2
ISEN1 PR233 @0_0603_5%

680P_0603_50V7K
m
ISEN2 PQ206 1 2

2
PR235 97.6K_0402_1% PC220 1 2 +5VS

3
2
1
2 PR237 1

VSUM
1K_0402_1%

1 2 2 1 PC223
1

PR234 1_0603_5% TPCA8036-H 1N SOP-ADV 1 2


270P_0402_50V7K PC221
1 2 1U_0402_6.3V6K
//
2

0.22U_0603_10V7K
PC222 100P_0402_50V8J VCC_PRM
B PR239 ISEN2 B
100_0402_1% PC224 2200P_0402_50V7K 10_0603_5%
1 2 1 2 1 2 CPU_B+
p:
1

PR238 1 2 PC225
0.1U_0603_25V7K
PR240 1K_0402_1%
2

PC226 330P_0603_50V8
tt

7 VCCSENSE 1 2
VSUM
1

PC227 PC228
2.61K_0402_1%

330P_0603_50V8
h PR241

1000P_0603_50V7K
2

7 VSSSENSE
2
1

11K_0402_1%

PC229 180P_0402_50V8J
PR242

1 2
2

10KB_0603_5%_ERTJ1VR103J
1 2 1 2 PH201
2

PR243 1K_0402_1% PR244 3.57K_0402_1%


PC230 0.1U_0402_16V7K
1

VCC_PRM 1 2

PC232 0.22U_0402_6.3V6K
PC231 2 1 2 1
0.22U_0603_10V7K

A A

Compal Electronics, Inc.


Title
+CPU_CORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISIONCustom
OF R&D 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.Date: W ednesday, February 18, 2009 Sheet 42 of 46
5 4 3 2 1
A B C D E

Version Change List ( P. I. R. List ) for Power Circuit


Item Page# Title Date Request Issue Description Solution Description Rev.
Owner
1 1

/
/x
su
2 2

p.
om
yc
m
//
3 3
p:
tt
h

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power Changed-List History-1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4111P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 18, 2009 Sheet 43 of 46
A B C D E
5 4 3 2 1

Item Fixed Issue (Reason for change) PAGE Modify List Date Phase

1 CardReader clock issue 17 Using USB_0 for CLK_48M_CR 2008/10/08 SI-1

2 Debug Card issue 26 Connect PLT_RST# to JP7.A17 2008/10/08 SI-1

3 SMT issue 29 Change IR1 to SCR00000E00 2008/10/08 SI-1


D D

4 Add Audio board 29 Add JAUDIO for audio board 2008/10/08 SI-1

5 SW2 is for DB1 debug 33 Delete SW2 2008/10/08 SI-1

6 Cap board issue 33 Change Cap board power rail to +3VL 2008/10/08 SI-1

7 Support GM47 13 Add C1503 for GM47 2008/10/08 SI-1

8 Change FAN control circuit to voltage control 6 Add U51,D63 2008/10/08 SI-1

/
9 Delete HDA SSC 21 Remove U8 for layout spacing 2008/10/08 SI-1

/x
10 For PR mini card connector 26 Add R1225 -- R1236 2008/10/08 SI-1

11 PA/PR CardReader LED 27 D54 for PA, D64 for PR 2008/10/08 SI-1

su
C C

12 EMI request 28 Change R1132 to bead 2008/10/08 SI-1

p.
13 Use audio board 29 Add audio board connector, change MIC to 2pin and add SPK connector 2008/10/08 SI-1

14 Change JFPR to 6 pin connector 30 Add Q109, C1518, R1210 2008/10/08 SI-1

om
15 EMI request 35 Add C1512 -- C1517 2008/10/08 SI-1

16 Change JFPR to 4 pin connector 30 Delete Q109, C1518, R1210 2008/11/21 SI-R

yc
17 Delete resistor for Debug card 26 Delete R1220-R1224 2008/11/21 SI-R

m
18 EMI request 35 Delete C1516,C1517 and connect to GND 2008/11/21 SI-R

For Intel DPST 19


//
Add R1237,R1238 2008/11/25 SI-R
19
B B

17
20 EMI and WWAN request 21 Install C217, C218, C219, C435, C312, C316, C66, C67, C1478, C1479, C1480, C1481, D58, C1516, R1239, C327 2008/12/18 PV-1
28
p:

21 Audio board connector 29 Change pin define 2008/12/18 PV-1


tt

22 ST and Parade level shift 34 Add R for Parade 2008/12/18 PV-1


h

23 ESD request 33 Add C1518,D65,D66,D67 2008/1/19 MV-1

17 25
24 ESD/ EMI request 18 32 C217-C219, D5-D7, D45-D47, D20, C792-C815 no stuff 2008/2/13 MV-1
30

25 AUDIO issue 29 C1446, C1447 change to 0805 size 2008/2/13 MV-1

26 PC Beep issue 28 change to analog GND and add separate diode 2008/2/13 MV-1

27
A A

28

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/08/28 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PIR
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina UMA 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 18, 2009 Sheet 44 of 46
5 4 3 2 1
5 4 3 2 1

Item Fixed Issue (Reason for change) PAGE Modify List Date Phase

29

30

31
D D

32

33

34

35

36

/
37

/x
38

39

su
C C

40

p.
41

42

om
43

44

yc
45

m
46 //
47
B B

48
p:

49
tt

50
h

51

52

53

54

55
A A

56

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/08/28 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PIR 2
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina UMA 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 18, 2009 Sheet 45 of 46
5 4 3 2 1
5 4 3 2 1

Item Fixed Issue (Reason for change) PAGE Modify List Date Phase

57

58

59
D D

60

61

62

63

64

/
65

/x
66

67

su
C C

68

p.
69

70

om
71

72

yc
73

m
74 //
75
B B

76
p:

77
tt

78
h

79

80

81

82

83
A A

84

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/08/28 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW PIR 3
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina UMA 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 18, 2009 Sheet 46 of 46
5 4 3 2 1

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