DELL Inspiron 1420 ELSA LANAI UMA Laptop Schematics PDF

A B C D E
ASUS CONFIDENTIAL
MODEL NAME : Elsa
1
PCB NO : ??? 1
ASUS P/N : ???
2 2
Lanai UMA Schematics Document

uFCPGA Mobile Merom
Intel Crestline-GM + ICH8M
3 3
2007-03-19
REV :1.2(DELL: X02)
4 4
5 MB PCB 5
Part Number Description
BOM NO. ???
DA800004H0L PCB 00B LA-3071P REV0 M/B
PCB P/N: ???
REVISION DATE: Monday, March 19, 2007 DESCRIPTION: SCHEMATIC FILE NAME : DESIGN ENGINEER :
PROJECT: 1.2 SHEET 1 OF 68 Cover Page RELEASE DATE :
A B C D E
5 4 3 2 1
LANAI: UMA CLOCK

CK410M+LP
POWER POWER SEQUENCE PG 51 PG 21
LOGIC
D POWER POWER PG 57 Merom POWER D
CON. CHARGER POWER VCORE PG 53

XDP (478 Micro-FCPGA)
PG 59 POWER CONTROL PG 49 PG 52
POWER I/O PG 55
SWITCH PG 7,8
POWER SYSTEM
+1.5V_RUN/+1.05V_VCCP
PG 54
5V_ALW & 3.3V_ALW
DISCHARGE PATH PG 49 (Symbol Rev.09) REGULATOR PG 58
PG 56
+3.3V_SUS/+5V_SUS/+3.3V_RUN REGULATOR
+5V/+3.3V/+1.8V/+1.25_RUN +VCC_GFX_CORE/+1.25V_RUN +1.8V_SUS/+0.9V_DDR_VTT
Panel Connector LVDS 533/667 MHZ DDR II

PG 28 DDR2-SODIMM1
Crestline PG 19
1299 uFCBGA
PG 9,10,11,12,13,14 533/667 MHZ DDR II DDR2-SODIMM2
C
(Symbol Rev.09) PG 19 C
IO Board
CRT CONN. VGA VGA
USB2.0(P0,P1) USB CONN.
TVOUT DMI INTERFACE
TVOUT PG 39
TV CONN.
USB Board
USB2.0(P2,3) D.B
USB CONN.x2 CON PCIE (Lane6)
USB2.0(P2,3)
PCIEx1 (Lane2) PCIEx1 (Lane2) PCI
MINI-CARD
WLAN PG 50 ICH8-M
USB2.0(P9) PCIE (Lane4)
676 BGA
MINI-CARD USB2.0(P9)
WWAN PG 15,16,17,18 USB2.0(P6)
CARD READER
USB2.0(P7) 1394/R5C833 BCM5906KMLG
(Symbol Rev.09) PG 32,33,34 QFN-68 PG 47
IHDA
B
SIM USB2.0(P5) B
CARD CAMERA
PG 28
EXPRESS-CARD RJ45/Magnetic
SIM CARD Board R5538 PG 48
PG 35
SPI LPC SATA SATA-HDD
AUDIO/AMP MDC PG 31
PG 44,45,46 PG 36
IDE CD-ROM
PG 31
SIO SIO
S/PDIF DIGITAL Speaker WtoB MEC5025 ECE5011
TO TV MIC. CON CON 128KB Flash Expander
CONN. TMKBC BC USB 2.0 Hub(4) Bluetooth
PG 30 PG 46 PG 46 PG 41
PG 28 128 Pins VTQFP 128 Pins VTQFP
PG 37 PG 38
A
Audio RJ11 SPI PS/2
A
Jacks
*3 Touchpad FAN &THERMAL USER SNIFFER CAPBTN
CIR FLASH CON. EMC4001 INTERFACE CON.
PG 41 PG 40 PG 41 PG 43 PG 42 PG 42 PG 40
JACK Board RJ11 Board
PROJECT: 1.2 SHEET 2 OF 68 BLOCK DIAGRAM RELEASE DATE :
5 4 3 2 1
A B C D E
INDEX
Pg# Description DNI LIST Pg# Description DNI LIST
01 Cover Page 63 POWER CIRCUIT CHANGE LIST

1 1
02 Schematic Block Diagram 64 Modem board cover page

03 INDEX 65 RJ-11 CONN
04 Bus connection 66 Modem board change List
05 SMBUS BLOCK 67 USB board cover page
06 Power Rail 68 USB PORT ( SINGLE * 2 )
07-08 CPU ( Merom 、 Penryn )
09-14 Crestline
15-18 ICH8M
2 19-20 DDRII SO-DIMM( 533MHz 、 667MHz ) 2
21 Clock Generator ( CK410M+LP )

22-27 BLANK PAGE
28 LVDS CON & Camera & DMIC
29 RGB CON
30 TV OUT CON
31 SATA(HDD & CD_ROM)
32-34 MEDIA CARD READER / 1394 ( R5C833 )
35 PCI-Express Card
3 3
36 MDC CONN
37 EC ( MEC5025 )
38 SIO ( ECE5011 )
39 USB PORT x 2
40 FLASH & RTC & CAPBTN CONN
41 TOUCH PAD & BT & CIR & LID
42 SWITCH & LED
43 HARDWARE MONITOR ( EMC4001 )
4 44-46 AUDIO CODEC & AMP 4
47 LOM BCM5906
48 Magnetics and RJ-45
49 Power Control Switch
50 BtoB CON
51 Power Sequence Logic
52 XDP
53-59 Power Circuit
60 SCREW PAD
5 5
61 Change List 1
62 Change List 2
PROJECT: Lanai 1.2 SHEET 3 OF 68 INDEX RELEASE DATE :
A B C D E
A B C D E
Footprint Definition PCI TABLE

PCI
Resistor Footprint is 0402 if there is no description DEVICE IDSEL REQ#/GNT# PIRQ
Capacitor Footprint is 0402 if there is no description PCI_REQ1# PCI_PIRQC#
1 R5C833 PCI_AD17 PCI_GNT1# 1
PCI_PIRQD#
Ferrite Bead Footprint is 0603 if there is no description
Layout Note
For all of ESD diode, they should be placed as close as
possible to connectors and the signals from connectors PCI Express TABLE
should be routed to ESD diodes first. There is no branch
or via before diodes Lane 1 WWAN / Mini Card
Lane 2 WLAN / Mini Card
2 Lane 3 2
Lane 4 ExpressCard
Lane 5
Lane 6 LAN BCM5906KMLG
USB TABLE
3 ICH8-0 User1 3
(EHCI#1) (Single port , in USB BD)
ICH8-1 User2
(EHCI#1) (Single port , in USB BD)
ICH8-2 User3
(EHCI#1) (Dual port-bottom , in I/O BD)
ICH8-3 User4
(EHCI#1) (Dual port-top , in I/O BD)
ICH8-4
(EHCI#1)
4 4
ICH8-5 Camera
(EHCI#1)
ICH8-6
(EHCI#2) ExpressCard
ICH8-7
(EHCI#2) BT Module
ICH8-8
(EHCI#2)
ICH8-9 WWAN / Mini Card

5 5
(EHCI#2)
Note : No USB for WLAN

REVISION DATE: Monday, March 19, 2007 DESCRIPTION: SCHEMATIC FILE NAME : <OrgName> DESIGN ENGINEER :
PROJECT: Lanai 1.2 SHEET 4 OF 68 Bus Connection RELEASE DATE :
A B C D E
5 4 3 2 1
+3.3V_SUS +3.3V_SUS +3.3V_RUN

MEM_SCLK 197
2.2K 2.2K 2.2K 2.2K MEM_SDATA 195 DIMM 0
10K 10K
+3.3V_RUN
ICH8-M AJ26 ICH_SMBCLK
7002 MEM_SCLK 197
AD19 ICH_SMBDATA MEM_SDATA 195 DIMM 1
D
7002 D
AC17 AMT_SMBCLK
I/O Board
AE19 AMT_SMBDAT
+5V_MEDIA
7 30 30
8.2K 8.2K
8 Express Card 32 WWAN 32 WLAN
6 DOCK_SMBCLK
5 DOCK_SMBDAT CAPBTN Board
+3.3V_ALW +3.3V_RUN
2.2K 2.2K 2.2K 2.2K

C C
+3.3V_RUN
13 CKG_SMBCLK CLK_SCLK 16
7002
12 CKG_SMBDAT CLK_SDATA 17 CLK GEN.
+3.3V_ALW 7002
4.7K 4.7K
100 THRM_SMBCLK 12
99 THRM_SMBDAT +3.3V_ALW 11 ECE4001
SIO +3.3V_ALW
10
2.2K 2.2K 9 CHARGER
B
MEC5025 112 PBAT_SMBCLK
100
SMB_CLK 3
B
+3.3V_ALW Battery
111 PBAT_SMBDAT SMB_DAT 4 CONN.
100
+3.3V_ALW
8.2K 8.2K
8 LCD_SMBCLK 34
7 LCD_SMDDAT +3.3V_ALW 35
+3.3V_RUN 47pF 47pF
LVDS
Connector
2.2K 2.2K
A A
LCD_DDCCLK 43
VGA LCD_DDCDAT +3.3V_RUN 44
PROJECT: Lanai 1.2 SHEET 5 OF 68 SMBUS BLOCK RELEASE DATE :
5 4 3 2 1
A B C D E
ADAPTER
1 1
+RTC_CELL
+PWR_SRC
BATTERY
2 2
TPS51120 ISL6260C SN0508073 SN0508073

ISL6208
THERM_STP#
THERM_STP#
THERM_STP#
RUNPWROK
IMVP_VR_ON
1.25V_RUN_ON
1.5V_RUN_ON
1.05_RUN_ON
ALWON
ALWON
ALWON
DDR_ON
3 3
+5V_ +3.3V_RTC
ALW2 _LDO +5V_ALW +3.3V_ALW +VCC_CORE +1.5V_RUN +1.05V_VCCP +1.8V_SUS +1.25V_RUN
0.9V_DDR_VTT_ON
3.3V_SUS_ON
3.3V_RUN_ON
RUN_ON
SUS_ON
SI4800BDY BAT54S SI4800BDY FDS6612A SI4800BDY
DDR_ON
1.8V_RUN_ON
+5V_RUN +15V_ALW +5V_SUS +3.3V_RUN +3.3V_SUS TPS51100 FDS6612A
4 4
+0.9V_DDR_VTT +1.8V_RUN
EMC4001
EE
SIDE
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
5
+2.5V_RUN TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, 5
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
PROJECT: Lanai 1.2 SHEET 6 OF 68 Power Rail RELEASE DATE :
A B C D E
5 4 3 2 1
U25A U25B
H_A#[3..16] MOLEX/47387-4781 H_D#[0..63] MOLEX/47387-4781 H_D#[0..63]
9 H_A#[3..16] 9 H_D#[0..63] H_D#[0..63] 9
H_A#3 J4 H1 H_D#0 E22 Y22 H_D#32
A3# ADS# H_ADS# 9 D0# D32#
0
ADDR GROUP
H_A#4 L5 E2 H_D#1 F24 AB24 H_D#33
A4# BNR# H_BNR# 9 D1# D33#
H_A#5 L4 G5 H_D#2 E26 V24 H_D#34
A5# BPRI# H_BPRI# 9 D2# D34#
H_A#6 K5 H_D#3 G22 V26 H_D#35
A6# D3# D35#
DATA GRP 0
H_A#7 M3 H5 H_D#4 F23 V23 H_D#36
A7# DEFER# H_DEFER# 9 D4# D36#
H_A#8 N2 F21 H_D#5 G25 T22 H_D#37
A8# DRDY# H_DRDY# 9 D5# D37#
H_A#9 J1 E1 H_D#6 E25 U25 H_D#38
H_A#10 A9# DBSY# H_DBSY# 9 D6# D38#
N3 H_D#7 E23 U23 H_D#39
A10# H_BR0# 9 D7# D39#
H_A#11 P5 F1 H_D#8 K24 Y25 H_D#40
H_A#12 A11# BR0# H_D#9 D8# D40# H_D#41
DATA GRP 2
P2 A12# G24 D9# D41# W22
CONTROL
H_A#13 L2 D20 H_IERR# 1 2 H_D#10 J24 Y23 H_D#42
A13# IERR# +1.05V_VCCP D10# D42#
H_A#14 P4 B3 R159 56Ohm 5% H_D#11 J23 W24 H_D#43
H_A#15 A14# INIT# H_INIT# 15 D11# D43#
P1 H_D#12 H22 W25 H_D#44
D H_A#16 A15# H_D#13 D12# D44# H_D#45 D
R1 A16# LOCK# H4 H_LOCK# 9 F26 D13# D45# AA23
M1 H_D#14 K22 AA24 H_D#46
9 H_ADSTB#0 H_REQ#[0..4] ADSTB0# H_RESET# H_D#15 D14# D46# H_D#47
9 H_REQ#[0..4] RESET# C1 H_RESET# 9,52 H23 D15# D47# AB25
H_REQ#0 K3 F3 J26 Y26
H_REQ#1 REQ0# RS0# H_RS#0 9 9 H_DSTBN#0 DSTBN0# DSTBN2# H_DSTBN#2 9
H2 REQ1# RS1# F4 H_RS#1 9 9 H_DSTBP#0 H26 DSTBP0# DSTBP2# AA26 H_DSTBP#2 9
H_REQ#2 K2 G3 H25 U22
H_REQ#3 REQ2# RS2# H_RS#2 9 9 H_DINV#0 DINV0# DINV2# H_DINV#2 9
J3 REQ3# TRDY# G2 H_TRDY# 9
H_REQ#4 L1 H_D#[0..63] H_D#[0..63]
H_A#[17..35] REQ4# 9 H_D#[0..63] H_D#[0..63] 9
G6 H_D#16 N22 AE24 H_D#48
9 H_A#[17..35] HIT# H_HIT# 9 D16# D48#
H_A#17 Y2 E4 H_D#17 K25 AD24 H_D#49
A17# HITM# H_HITM# 9 D17# D49#
H_A#18 U5 H_D#18 P26 AA21 H_D#50
H_A#19 A18# XDP_BPM#0 Layout note: H_D#19 D18# D50# H_D#51
R3 A19# BPM0# AD4 XDP_BPM#0 52 R23 D19# D51# AB22
1
ADDR GROUP
H_A#20 W6 AD3 XDP_BPM#1 H_D#20 L23 AB21 H_D#52
A20# BPM1# XDP_BPM#1 52 Place voltage D20# D52#
DATA GRP 1
H_A#21 U4 AD1 XDP_BPM#2 H_D#21 M24 AC26 H_D#53
A21# BPM2# XDP_BPM#3 XDP_BPM#2 52 divider within D21# D53#
H_A#22 Y5 AC4 H_D#22 L22 AD20 H_D#54
XDP/ITP SIGNALS
A22# BPM3# XDP_BPM#4 XDP_BPM#3 52 D22# D54#
H_A#23 U1 AC2 0.5" of GTLREF H_D#23 M23 AE22 H_D#55
A23# PRDY# XDP_BPM#5 XDP_BPM#4 52 D23# D55#
H_A#24 R4 AC1 H_D#24 P25 AF23 H_D#56
A24# PREQ# XDP_TCK XDP_BPM#5 52 pin D24# D56#
H_A#25 T5 AC5 H_D#25 P23 AC25 H_D#57
A25# TCK XDP_TDI XDP_TCK 52 D25# D57#
H_A#26 T3 AA6 H_D#26 P22 AE21 H_D#58
A26# TDI XDP_TDO XDP_TDI 52 +1.05V_VCCP D26# D58#
H_A#27 H_D#27 H_D#59
DATA GRP 3
W2 A27# TDO AB3 XDP_TDO 52 T24 D27# D59# AD21
H_A#28 W5 AB5 XDP_TMS H_D#28 R24 AC22 H_D#60
A28# TMS XDP_TRST# XDP_TMS 52 D28# D60#
H_A#29 Y4 AB6 H_D#29 L25 AD23 H_D#61
A29# TRST# XDP_TRST# 52 D29# D61#
2
H_A#30 U2 C20 XDP_DBRESET# H_D#30 T25 AF22 H_D#62
A30# DBR# XDP_DBRESET# 17,38,52 D30# D62#
H_A#31 V4 R163 H_D#31 N25 AC23 H_D#63
H_A#32 A31# 1KOhm D31# D63#
W3 A32# 9 H_DSTBN#1 L26 DSTBN1# DSTBN3# AE25 H_DSTBN#3 9
H_A#33 AA4 THERMAL 1 2 1% M26 AF24
H_A#34 A33# +1.05V_VCCP 9 H_DSTBP#1 DSTBP1# DSTBP3# H_DSTBP#3 9
AB2 R160 56Ohm 5% N24 AC20
H_A#35 A34# 9 H_DINV#1 DINV1# DINV3# H_DINV#3 9
CPU_PROCHOT#
1
AA3 A35# PROCHOT# D21
V1 A24 H_THERMDA V_CPU_GTLREF AD26 R26 COMP0 Note:
9 H_ADSTB#1 ADSTB1# THERMDA H_THERMDC H_THERMDA 43 CPU_TEST1 GTLREF COMP0 COMP1
THERMDC B25 H_THERMDC 43 C23 TEST1 MISC COMP1 U26 H_DPRTSTP need to daisy chain
2
A6 CPU_TEST2 D25 AA1 COMP2
15 H_A20M# A20M# TEST2 COMP2
ICH
A5 C7 R164 CPU_TEST3 C24 Y1 COMP3 from ICH8 to IMVP6 to CPU.

C 15 H_FERR# FERR# THERMTRIP# H_THERMTRIP# 43 CPU_TEST4 TEST3 COMP3 C
C4 2KOhm AF26
15 H_IGNNE# IGNNE# CPU_TEST5 TEST4
1 2 1% AF1 E5
+1.05V_VCCP CPU_TEST6 TEST5 DPRSTP# H_DPRSTP# 10,15,53
D5 R368 56Ohm 5% A26 B5
15 H_STPCLK# STPCLK# TEST6 DPSLP# H_DPSLP# 15
H CLK
1
15 H_INTR C6 LINT0 DPWR# D24 H_DPWR# 9
15 H_NMI B4 LINT1 BCLK0 A22 CLK_CPU_BCLK 21 10,21 CPU_MCH_BSEL0 B22 BSEL0 PWRGOOD D6 H_PWRGOOD 15
15 H_SMI# A3 SMI# BCLK1 A21 CLK_CPU_BCLK# 21 10,21 CPU_MCH_BSEL1 B23 BSEL1 SLP# D7 H_CPUSLP# 9
10,21 CPU_MCH_BSEL2 C21 BSEL2 PSI# AE6 H_PSI# 53
M4 RSVD01
N5 SOCKET478 1 2
RSVD02 H_PWRGD_XDP 52
T2 R112 1KOhm 5%
RSVD03
V3 RSVD04
RESERVED
B2 RSVD05
C3 H_THERMDA 2 1 H_THERMDC 2 1 CPU_TEST1 T27
RSVD06 R395 1KOhm 1% /* CPU_TEST3
D2 RSVD07 1
D22 C410 2200PF/50V MLCC/+/-10% /* 2 1 CPU_TEST2
RSVD08 R396 1KOhm 1% /* T15
D3 RSVD09
F6 1 CPU_TEST5
RSVD10 CPU_TEST4
1 2
C409 0.1UF/10V MLCC/+/-10% /*
1 2 CPU_TEST6 For the purpose of testability, route these signals
SOCKET478 R399 0Ohm 5% /*
Place C close to the through a ground referenced Zo= 55 ohm trace that
CPU_TEST4 pin. Make sure ends in a via that is near a GND via and is
CPU_TEST4 routing is accessible through an oscilloscope connection.
reference to GND and away
from other noisy signal.
FSB BCLK BSEL2 BSEL1 BSEL0 COMP0

COMP1
B COMP2 B
COMP3
533 133 0 0 1
2
R120 R118 R398 R397
667 166 0 1 1
54.9Ohm 27.4Ohm 54.9Ohm 27.4Ohm
Voltage Level Shift 1% 1% 1% 1%
+1.05V_VCCP +3.3V_ALW 800 200 0 1 0
1
2
R161 Comp0,2 connect with Zo=27.4ohm, Comp1,3

+1.05V_VCCP 2.2KOhm
/* connect with Zo=55 ohm, make those traces
1
length shorter than 0.5". Trace should be

G
XDP_TMS
1
2 1
R122 54.9Ohm 1% CPU_PROCHOT# at least 25 mils away from any other
2 S
XDP_TDI EC_CPU_PROCHOT# 37
D
2 1 toggling signal.
R119 54.9Ohm 1%
XDP_BPM#5 2 1 Q54
R121 54.9Ohm 1%
XDP_TCK 2 1 2N7002
R114 54.9Ohm 1% Id=280mA/Pd=300mW
XDP_TRST# 2 1 /*
R117 649Ohm 1%
A A
PROJECT: Lanai 1.2 SHEET 7 OF 68 MEROM CPU (1) RELEASE DATE :
5 4 3 2 1
5 4 3 2 1
+VCC_CORE +VCC_CORE
+VCC_CORE
All use 10U 4V (+-20% , X6S , 0805)Pb-Free.
U25D
U25C MOLEX/47387-4781
MOLEX/47387-4781 A4 P6
VSS001 VSS082
A7 VCC001 VCC068 AB20 A8 VSS002 VSS083 P21
A9 VCC002 AB7 A11 P24
VCC069 VSS003 VSS084
1
A10 VCC003 VCC070 AC7 A14 VSS004 VSS085 R2
C403 C385 C132 C140 C390 A12 AC9 A16 R5
VCC004 VCC071 VSS005 VSS086
10UF/4V 10UF/4V 10UF/4V 10UF/4V 10UF/4V A13 VCC005 AC12 A19 R22
2
2
MLCC/+/-20% MLCC/+/-20% MLCC/+/-20% MLCC/+/-20% MLCC/+/-20% A15 VCC006 VCC073 AC13 A23 VSS007 VSS088 R25
pt_c0805 pt_c0805 pt_c0805 pt_c0805 pt_c0805 A17 VCC007 VCC074 AC15 AF2 VSS008 VSS089 T1
A18 VCC008 AC17 B6 T4
A20 VCC009 VCC076 AC18 B8 VSS010 VSS091 T23
D B7 AD7 B11 T26 D
+VCC_CORE VCC010 VCC077 VSS011 VSS092
B9 VCC011 AD9 B13 U3
B10 VCC012 VCC079 AD10 B16 VSS013 VSS094 U6
B12 VCC013 VCC080 AD12 B19 VSS014 VSS095 U21
B14 VCC014 AD14 B21 U24
B15 VCC015 VCC082 AD15 B24 VSS016 VSS097 V2
B17 VCC016 VCC083 AD17 C5 VSS017 VSS098 V5
1
1
B18 VCC017 VCC084 AD18 C8 VSS018 VSS099 V22
C183 C166 C400 C392 C176 B20 AE9 C11 V25
10UF/4V 10UF/4V 10UF/4V 10UF/4V 10UF/4V C9 VCC019 VCC086 AE10 C14 VSS020 VSS101 W1
2
2
MLCC/+/-20% MLCC/+/-20% MLCC/+/-20% MLCC/+/-20% MLCC/+/-20% C10 VCC020 AE12 C16 W4
pt_c0805 pt_c0805 pt_c0805 pt_c0805 pt_c0805 C12 VCC021 VCC088 AE13 C19 VSS022 VSS103 W23
C13 VCC022 VCC089 AE15 C2 VSS023 VSS104 W26
C15 VCC023 AE17 C22 Y3
C17 VCC024 VCC091 AE18 C25 VSS025 VSS106 Y6
8 inside cavity, north side, secondary layer. C18 VCC025 VCC092 AE20 D1 VSS026 VSS107 Y21
D9 VCC026 AF9 D4 Y24
D10 VCC027 VCC094 AF10 D8 VSS028 VSS109 AA2
+VCC_CORE D12 AF12 D11 AA5
D14 VCC029 AF14 D13 AA8
D17 AF17 +1.05V_VCCP D19 AA14
E7 VCC033 VCC100 AF20 D26 VSS034 VSS115 AA19
1
1
E9 VCC034 E3 VSS035 VSS116 AA22
C180 C157 C159 C383 C187 E10 G21 E6 AA25
VCC035 VCCP01 VSS036 VSS117
10UF/4V 10UF/4V 10UF/4V 10UF/4V 10UF/4V E12 VCC036 VCCP02 V6 E8 VSS037 VSS118 AB1
2
2
MLCC/+/-20% MLCC/+/-20% MLCC/+/-20% MLCC/+/-20% MLCC/+/-20% E13 VCC037 VCCP03 J6 E11 VSS038 VSS119 AB4
pt_c0805 pt_c0805 pt_c0805 pt_c0805 pt_c0805 E15 VCC038 VCCP04 K6 E14 VSS039 VSS120 AB8
E17 VCC039 VCCP05 M6 E16 VSS040 VSS121 AB11
E18 VCC040 VCCP06 J21 E19 VSS041 VSS122 AB13
1
E20 VCC041 VCCP07 K21 + CE20 E21 VSS042 VSS123 AB16
C +VCC_CORE F7 M21 220UF/4V E24 AB19 C
VCC042 VCCP08 pt_c7343d_h79 VSS043 VSS124
F9 VCC043 VCCP09 N21 F5 VSS044 VSS125 AB23
F10 N6 TAN/Lf_T=2000hrs_105C/+/-20% F8 AB26
2
F12 VCC045 VCCP11 R21 F11 VSS046 VSS127 AC3
F14 VCC046 VCCP12 R6 F13 VSS047 VSS128 AC6
F15 VCC047 VCCP13 T21 F16 VSS048 VSS129 AC8
1
1
F17 VCC048 VCCP14 T6 F19 VSS049 VSS130 AC11
C131 C386 C152 C391 C402 F18 V21 +1.5V_RUN F2 AC14
10UF/4V 10UF/4V 10UF/4V 10UF/4V 10UF/4V F20 VCC050 VCCP16 W21 F22 VSS051 VSS132 AC16
2
2
MLCC/+/-20% MLCC/+/-20% MLCC/+/-20% MLCC/+/-20% MLCC/+/-20% AA7 VCC051 F25 VSS052 VSS133 AC19
pt_c0805 pt_c0805 pt_c0805 pt_c0805 pt_c0805 AA9 VCC052 VCCA01 B26 G4 VSS053 VSS134 AC21
AA10 VCC053 VCCA02 C26 G1 VSS054 VSS135 AC24
AA12 VCC054 G23 VSS055 VSS136 AD2
1
AA13 VCC055 VID0 AD6 VID0 53 G26 VSS056 VSS137 AD5
8 inside cavity, south side, secondary layer. AA15 AF5 C414 C418 H3 AD8
VCC056 VID1 VID1 53 VSS057 VSS138
AA17 VCC057 VID2 AE5 VID2 53 0.01UF/25V H6 VSS058 VSS139 AD11
10UF/4V
2
AA18 VCC058 VID3 AF4 VID3 53 MLCC/+/-10% H21 VSS059 VSS140 AD13
AA20 AE3 pt_c0603 pt_c0805 H24 AD16
+VCC_CORE VCC059 VID4 VID4 53 VSS060 VSS141
AB9 AF3 MLCC/+/-20% J2 AD19
VCC060 VID5 VID5 53 VSS061 VSS142
AC10 VCC061 VID6 AE2 VID6 53 J5 VSS062 VSS143 AD22
AB10 VCC062 J22 VSS063 VSS144 AD25
AB12 VCC063 J25 VSS064 VSS145 AE1
AB14 VCC064 VCCSENSE AF7 VCCSENSE VCCSENSE 53 K1 VSS065 VSS146 AE4
AB15 VCC065 Layout Note: K4 VSS066 VSS147 AE8
1
AB17 K23 AE11

C126 C181 C399 C398 C397 C145 AB18
VCC066
AE7 VSSSENSE Place 0.01U/25V near PIN K26
VSS067 VSS148
AE14
VCC067 VSSSENSE VSSSENSE 53 VSS068 VSS149
10UF/4V 10UF/4V 10UF/4V 10UF/4V 10UF/4V 10UF/4V B26. L3 VSS069 VSS150 AE16
SOCKET478
2
MLCC/+/-20% MLCC/+/-20% MLCC/+/-20% MLCC/+/-20% MLCC/+/-20% MLCC/+/-20% L6 VSS070 VSS151 AE19

pt_c0805 pt_c0805 pt_c0805 pt_c0805 pt_c0805 pt_c0805 L21 AE23
VSS071 VSS152
L24 VSS072 VSS153 AE26
M2 VSS073 VSS154 A2
M5 VSS074 VSS155 AF6
B +VCC_CORE B
6 inside cavity, north side, primary layer. M22 VSS075 VSS156 AF8
M25 VSS076 VSS157 AF11
N1 VSS077 VSS158 AF13
2
+VCC_CORE N4 AF16
R128 VSS078 VSS159
N23 VSS079 VSS160 AF19
100Ohm N26 AF21
1% VSS080 VSS161
100U/25V *4 Remove to POWER CIRCUIT . P3 VSS081 VSS162 A25
VSS163 AF25
VCCSENSE
1
1
VSSSENSE SOCKET478
C179 C133 C396 C172 C134 C158
2
10UF/4V 10UF/4V 10UF/4V 10UF/4V 10UF/4V 10UF/4V
R127
2
MLCC/+/-20% MLCC/+/-20% MLCC/+/-20% MLCC/+/-20% MLCC/+/-20% MLCC/+/-20%

pt_c0805 pt_c0805 pt_c0805 pt_c0805 pt_c0805 pt_c0805 100Ohm
1%
1
6 inside cavity, south side, primary layer.
+VCC_CORE Route VCCSENSE and VSSSENSE

+1.05V_VCCP
traces at 27.4ohms with 50
mils spacing and length
No.43 matched to within 25 mil.
Place PU and PD within
1
C381 C380 C404 C193 C405 C124

1
1
0.1UF/10V 0.1UF/10V 0.1UF/10V 0.1UF/10V 0.1UF/10V 0.1UF/10V + + + + + + 1 inch of CPU.
MLCC/+/-10% MLCC/+/-10% MLCC/+/-10% MLCC/+/-10% MLCC/+/-10% MLCC/+/-10% CE6 CE5 CE19 CE16 CE18 CE7
2
A 220UF/2V 220UF/2V 220UF/2V 220UF/2V 220UF/2V 220UF/2V A

pt_c7343d_h75 pt_c7343d_h75 pt_c7343d_h75 pt_c7343d_h75 pt_c7343d_h75 pt_c7343d_h75
2
2
SANYO/2TPF220M7 SANYO/2TPF220M7 SANYO/2TPF220M7 SANYO/2TPF220M7 SANYO/2TPF220M7 SANYO/2TPF220M7
/* /*
Layout out:
Place these inside socket cavity on North side secondary.
PROJECT: Lanai 1.2 SHEET 8 OF 68 Merom CPU (2) RELEASE DATE :
5 4 3 2 1
5 4 3 2 1
U10A H_A#[3..35]
H_D#[0..63] H_A#[3..35] 7
J13 H_A#3
7 H_D#[0..63] H_D#0 H_A#_3
E2 B11 H_A#4
H_D#1 H_D#_0 H_A#_4 H_A#5
G2 H_D#_1 H_A#_5 C11
H_D#2 G7 M11 H_A#6
D H_D#3 H_D#_2 H_A#_6 H_A#7 D
M6 H_D#_3 H_A#_7 C15
H_D#4 H7 F16 H_A#8
H_D#5 H_D#_4 H_A#_8 H_A#9
H3 H_D#_5 H_A#_9 L13
H_D#6 G4 G17 H_A#10
H_D#7 H_D#_6 H_A#_10 H_A#11
F3 H_A#_11 C14
H_D#8 H_D#_7 H_A#12
N8 H_D#_8 H_A#_12 K16
H_D#9 H2 B13 H_A#13
H_D#10 H_D#_9 H_A#_13 H_A#14
M10 H_D#_10 H_A#_14 L16
H_D#11 N12 J17 H_A#15
H_D#12 H_D#_11 H_A#_15 H_A#16
N9 H_D#_12 H_A#_16 B14
+1.05V_VCCP H_D#13 H5 K19 H_A#17
H_D#14 H_D#_13 H_A#_17 H_A#18
P13 H_D#_14 H_A#_18 P15
H_D#15 K9 R17 H_A#19
H_D#16 H_D#_15 H_A#_19 H_A#20
M2 H_D#_16 H_A#_20 B16
1
H_D#17 W10 H20 H_A#21

R367 H_D#18 H_D#_17 H_A#_21 H_A#22
Y8 H_D#_18 H_A#_22 L19
221Ohm H_D#19 V4 D17 H_A#23
1% H_D#20 H_D#_19 H_A#_23 H_A#24
M3 H_D#_20 H_A#_24 M17
H_D#21 J1 N16 H_A#25
H_SWING H_D#22 H_D#_21 H_A#_25 H_A#26
2
N5 H_D#_22 H_A#_26 J19

H_D#23 N3 B18 H_A#27
H_D#_23 H_A#_27
1
H_D#24 W6 E19 H_A#28

H_D#_24 H_A#_28
1
R366 C371 H_D#25 W9 B17 H_A#29

100Ohm 0.1UF/10V H_D#26 H_D#_25 H_A#_29 H_A#30
N2 H_D#_26 H_A#_30 B15
1% MLCC/+/-10% H_D#27 Y7 E17 H_A#31
H_D#28 H_D#_27 H_A#_31 H_A#32
2
Y9 H_D#_28 H_A#_32 C18

H_D#29 H_A#33
2
P4 H_D#_29 H_A#_33 A19

H_D#30 W3 B19 H_A#34
H_D#31 H_D#_30 H_A#_34 H_A#35
N1 H_D#_31 H_A#_35 N19
H_D#32 AD12
H_D#33 H_D#_32
AE3 H_D#_33 H_ADS# G12 H_ADS# 7
HOST
H_D#34 AD9 H17
C H_D#35 H_D#_34 H_ADSTB#_0 H_ADSTB#0 7 C
AC9 H_D#_35 H_ADSTB#_1 G20 H_ADSTB#1 7
H_D#36 AC7 C8
H_D#37 H_D#_36 H_BNR# H_BNR# 7
AC14 H_D#_37 H_BPRI# E8 H_BPRI# 7
+1.05V_VCCP H_D#38 AD11 F12
H_D#39 H_D#_38 H_BREQ# H_BR0# 7
AC11 H_D#_39 H_DEFER# D6 H_DEFER# 7
H_D#40 AB2 C10
H_D#41 H_D#_40 H_DBSY# H_DBSY# 7
AD7 H_D#_41 HPLL_CLK AM5 CLK_MCH_BCLK 21
H_D#42 AB1 AM7
H_D#_42 HPLL_CLK# CLK_MCH_BCLK# 21
1
H_D#43 Y3 H8
H_D#_43 H_DPWR# H_DPWR# 7
1
R129 R130 H_D#44 AC6 K7

H_D#45 H_D#_44 H_DRDY# H_DRDY# 7
54.9Ohm 54.9Ohm AE2 E4
H_D#46 H_D#_45 H_HIT# H_HIT# 7
1% 1% AC5 C6
H_D#47 H_D#_46 H_HITM# H_HITM# 7
AG3 H_D#_47 H_LOCK# G10 H_LOCK# 7
H_D#48
2
AJ9 H_D#_48 H_TRDY# B7 H_TRDY# 7

H_SCOMP H_D#49
2
AH8 H_D#_49
H_SCOMP# H_D#50 AJ14
H_D#51 H_D#_50
AE9 H_D#_51
H_RCOMP H_D#52 AE11
H_D#53 H_D#_52
AH12 H_D#_53 H_DINV#_0 K5 H_DINV#0 7
1
H_D#54 AJ5 L2
H_D#55 H_D#_54 H_DINV#_1 H_DINV#1 7
R132 AH5 AD13
24.9Ohm AJ6 AE13
1% AE7
Layout Note: H_D#58 H_D#_57
AJ7 H_D#_58 H_DSTBN#_0 M7 H_DSTBN#0 7
H_D#59
2
H_RCOMP trace should be AJ2 H_D#_59 H_DSTBN#_1 K3 H_DSTBN#1 7

H_D#60 AE5 AD2
10-mil wide with 20-mil H_D#61 H_D#_60 H_DSTBN#_2 H_DSTBN#2 7
AJ3 H_D#_61 H_DSTBN#_3 AH11 H_DSTBN#3 7
spacing H_D#62 AH2
H_D#63 H_D#_62
AH13 H_D#_63 H_DSTBP#_0 L7 H_DSTBP#0 7
H_DSTBP#_1 K2 H_DSTBP#1 7
H_DSTBP#_2 AC2 H_DSTBP#2 7
H_SWING B3 AJ10
B H_SWING H_DSTBP#_3 H_DSTBP#3 7 B
+1.05V_VCCP H_RCOMP C2 H_RCOMP
H_REQ#_0 M14 H_REQ#0 7
H_SCOMP W1 E13
H_SCOMP H_REQ#_1 H_REQ#1 7
H_SCOMP# W2 A11
H_SCOMP# H_REQ#_2 H_REQ#2 7
1
H_REQ#_3 H13 H_REQ#3 7

R364 B6 B12
7,52 H_RESET# H_CPURST# H_REQ#_4 H_REQ#4 7
1KOhm E5
1% 7 H_CPUSLP# H_CPUSLP#
H_RS#_0 E12 H_RS#0 7
H_RS#_1 D7 H_RS#1 7
2
H_RS#_2 D8 H_RS#2 7
H_REF B9 H_AVREF
A9 H_DVREF
1
CRESTLINE_965GM
1
R365 C367
2KOhm 0.1UF/10V
1% MLCC/+/-10%
2
2
Layout Note:
Place the 0.1uF
decoupling capacitor
within 100 mils from
GMCH pins.
A A
PROJECT: Lanai 1.2 SHEET 9 OF 68 Crestline(HOST) RELEASE DATE :
5 4 3 2 1
5 4 3 2 1
+1.8V_SUS
U10C +VCC_PEG
U10B R90
1
J40 24.9Ohm 1%
L_IBG 28 BIA_PWM L_BKLT_CTRL
R351 P36 RSVD1 38 PANEL_BKEN H39 L_BKLT_EN PEG_COMPI N43 VCC3G_PCIE_R 1 2
1KOhm P37 AV29 LCTLA_CLK E39 M43
RSVD2 SM_CK_0 M_CLK_DDR0 19 52 LCTLA_CLK L_CTRL_CLK PEG_COMPO
2
0.1% R35 BB23 LCTLB_DATA E40
RSVD3 SM_CK_1 M_CLK_DDR1 19 52 LCTLB_DATA LCD_DDCCLK L_CTRL_DATA
N35 BA25 R325 C37
RSVD4 SM_CK_3 M_CLK_DDR2 19 28 LCD_DDCCLK LCD_DDCDATA L_DDC_CLK
SM_RCOMP_VOH 2.4KOhm
2
AR12 RSVD5 SM_CK_4 AV23 M_CLK_DDR3 19 28 LCD_DDCDAT D35 L_DDC_DATA PEG_RX#_0 J51
AR13 1% K40 L51
RSVD6 28 ENVDD L_VDD_EN PEG_RX#_1
1
AM12 RSVD7 SM_CK#_0 AW30 M_CLK_DDR#0 19 PEG_RX#_2 N47
1
1
C351 C353 R348 L_IBG
1
AN13 RSVD8 SM_CK#_1 BA23 M_CLK_DDR#1 19 L41 LVDS_IBG PEG_RX#_3 T45
0.01UF/25V 2.2UF/10V 3.01KOhm J12 AW25 T86 1 L43 T50
RSVD9 SM_CK#_3 M_CLK_DDR#2 19 UMA LVDS_VBG PEG_RX#_4
RSVD
MLCC/+/-10% MLCC/+/-10% 1% AR37 AW23 N41 U40
D RSVD10 SM_CK#_4 M_CLK_DDR#3 19 LVDS_VREFH PEG_RX#_5 D
c0603,pt_c0603
2
2
AM36 RSVD11 N40 LVDS_VREFL PEG_RX#_6 Y44
2
AL36 BE29 DDR_CKE0_DIMMA 19,20 28 LCD_ACLK- D46 PEG_RX#_7 Y40
RSVD12 SM_CKE_0 LVDSA_CLK#
AM37 RSVD13 SM_CKE_1 AY32 DDR_CKE1_DIMMA 19,20 28 LCD_ACLK+ C45 LVDSA_CLK PEG_RX#_8 AB51
D20 BD39 +1.8V_SUS D44 W49
RSVD14 SM_CKE_3 DDR_CKE2_DIMMB 19,20 28 LCD_BCLK- LVDSB_CLK# PEG_RX#_9
SM_RCOMP_VOL BG37 E42 AD44
SM_CKE_4 DDR_CKE3_DIMMB 19,20 28 LCD_BCLK+ LVDSB_CLK PEG_RX#_10
PEG_RX#_11 AD40
1
LVDS
SM_CS#_0 BG20 DDR_CS0_DIMMA# 19,20 28 LCD_A0- G51 LVDSA_DATA#_0 PEG_RX#_12 AG46
1
C108 C109 R352 BK16 R110 E51 AH49

SM_CS#_1 DDR_CS1_DIMMA# 19,20 28 LCD_A1- LVDSA_DATA#_1 PEG_RX#_13
0.01UF/25V 2.2UF/10V 1KOhm BG16 20Ohm F49 AG45
SM_CS#_2 DDR_CS2_DIMMB# 19,20 28 LCD_A2- LVDSA_DATA#_2 PEG_RX#_14
MLCC/+/-10% MLCC/+/-10% 0.1% H10 BE13 1% AG41
GRAPHICS
RSVD20 SM_CS#_3 DDR_CS3_DIMMB# 19,20 PEG_RX#_15
c0603,pt_c0603
2
B51
MUXING
RSVD21
2
2
BJ20 RSVD22 SM_ODT_0 BH18 M_ODT0 19,20 28 LCD_A0+ G50 LVDSA_DATA_0 PEG_RX_0 J50
BK22 BJ15 SMRCOMPP E50 L50
RSVD23 SM_ODT_1 M_ODT1 19,20 SMRCOMPN 28 LCD_A1+ LVDSA_DATA_1 PEG_RX_1
BF19 BJ14 M_ODT2 19,20 28 LCD_A2+ F48 PEG_RX_2 M47
RSVD24 SM_ODT_2 LVDSA_DATA_2
BH20 RSVD25 SM_ODT_3 BE16 M_ODT3 19,20 PEG_RX_3 U44
1
BK18 RSVD26 PEG_RX_4 T49
+3.3V_RUN BJ18 BL15 SMRCOMPP R363
28 LCD_B0- G44 PEG_RX_5 T41
RSVD27 SM_RCOMP LVDSB_DATA#_0
BF23 RSVD28 SM_RCOMP# BK14 SMRCOMPN 20Ohm
28 LCD_B1- B47 LVDSB_DATA#_1 PEG_RX_6 W45
R335 1 2 10KOhm 5% PM_EXTTS#0 BG23 RSVD29
1%
28 LCD_B2- B45 LVDSB_DATA#_2 PEG_RX_7 W41
R337 1 2 10KOhm 5% PM_EXTTS#1 BC23 BK31 SM_RCOMP_VOH PEG_RX_8 AB50
RSVD30 SM_RCOMP_VOH
BL31 SM_RCOMP_VOL
2
BD24 RSVD31 SM_RCOMP_VOL PEG_RX_9 Y48
DDR_A_MA14 BJ29
DDR
19,20 DDR_A_MA14 RSVD32 28 LCD_B0+ E44 LVDSB_DATA_0 PEG_RX_10 AC45
DDR_B_MA14 BE24 AR49 A47 AC41
19,20 DDR_B_MA14 RSVD33 SM_VREF_0 V_DDR_MCH_REF 28 LCD_B1+ LVDSB_DATA_1 PEG_RX_11
BH39 AW4 28 LCD_B2+ A45 AH47
PCI-EXPRESS
RSVD34 SM_VREF_1 LVDSB_DATA_2 PEG_RX_12
AW20 RSVD35 PEG_RX_13 AG49
BK20 RSVD36 PEG_RX_14 AH45
C48 RSVD37 PEG_RX_15 AG42
D47 RSVD38 DPLL_REF_CLK B42 MCH_DREFCLK 21
B44 RSVD39 DPLL_REF_CLK# C42 MCH_DREFCLK# 21 50 TV_CVBS E27 TVA_DAC PEG_TX#_0 N45
C44 RSVD40 DPLL_REF_SSCLK H48 DREF_SSCLK 21 50 TV_Y G27 TVB_DAC PEG_TX#_1 U39
+1.05V_VCCP
CLK
A35 RSVD41 DPLL_REF_SSCLK# H47 DREF_SSCLK# 21 50 TV_C K27 TVC_DAC PEG_TX#_2 U47
TV
C
No.10 B37 RSVD42 PEG_TX#_3 N51
C
B36 RSVD43 PEG_CLK K44 CLK_MCH_3GPLL 21 F27 TVA_RTN PEG_TX#_4 R50
2
R354 1 2 THERMTRIP_MCH# B34 K45 J27 T42
RSVD44 PEG_CLK# CLK_MCH_3GPLL# 21 TVB_RTN PEG_TX#_5
56Ohm 5% C34 R345 R350 R344 L27 Y43
RSVD45 150Ohm 150Ohm 150Ohm TVC_RTN PEG_TX#_6
PEG_TX#_7 W46
1% 1% 1% M35 W38
Layout Note: TV_DCONSEL_0 PEG_TX#_8
DMI_RXN_0 AN47 DMI_MRX_ITX_N0 16 P33 TV_DCONSEL_1 PEG_TX#_9 AD39
1
Location of all MCH_CFG strap DMI_RXN_1 AJ38 DMI_MRX_ITX_N1 16 PEG_TX#_10 AC46
DMI_RXN_2 AN42 DMI_MRX_ITX_N2 16 PEG_TX#_11 AC49
resistors needs to be close to AN46 AC42
DMI_RXN_3 DMI_MRX_ITX_N3 16 PEG_TX#_12
minmize stub. PEG_TX#_13 AH39
DMI_RXP_0 AM47 DMI_MRX_ITX_P0 16 PEG_TX#_14 AE49
7,21 CPU_MCH_BSEL0 P27 CFG_0 DMI_RXP_1 AJ39 DMI_MRX_ITX_P1 16 PEG_TX#_15 AH44
7,21 CPU_MCH_BSEL1 N27 CFG_1 DMI_RXP_2 AN41 DMI_MRX_ITX_P2 16
N24 AN45 VGA_BLU H32 M45
7,21 CPU_MCH_BSEL2 CFG3 CFG_2 DMI_RXP_3 DMI_MRX_ITX_P3 16 50 VGA_BLU CRT_BLUE PEG_TX_0
T111 1 C21 G32 T38
T14 CFG4 CFG_3 VGA_GRN CRT_BLUE# PEG_TX_1
1 C23 CFG_4 DMI_TXN_0 AJ46 DMI_MTX_IRX_N0 16 50 VGA_GRN K29 CRT_GREEN PEG_TX_2 T46
R356 2 1 4.02KOhm 1% /* CFG5 F23 AJ41 J29 N50
CFG6 CFG_5 DMI_TXN_1 DMI_MTX_IRX_N1 16 VGA_RED CRT_GREEN# PEG_TX_3
T110 1 N23 AM40 F29 R51
CFG_6 DMI_TXN_2 DMI_MTX_IRX_N2 16 50 VGA_RED CRT_RED PEG_TX_4
VGA
T93 1 CFG7 G23 AM44 E29 U43
CFG8 CFG_7 DMI_TXN_3 DMI_MTX_IRX_N3 16 CRT_RED# PEG_TX_5
T113 1 J20 W42
CFG_8 PEG_TX_6
CFG
R355 4.02KOhm 1% /* CFG9

DMI
2 1 C20 CFG_9 DMI_TXP_0 AJ47 DMI_MTX_IRX_P0 16 PEG_TX_7 Y47

T105 1 CFG10 R24 AJ42 K33 Y39
CFG11 CFG_10 DMI_TXP_1 DMI_MTX_IRX_P1 16 50 G_CLK_DDC2 CRT_DDC_CLK PEG_TX_8
T107 1 L23 AM39 G35 AC38
CFG12 CFG_11 DMI_TXP_2 DMI_MTX_IRX_P2 16 50 G_DAT_DDC2 CRT_DDC_DATA PEG_TX_9
T109 1 J23 AM43 R341 1 2 30Ohm pt_r0603 1% F33 AD47
CFG13 CFG_12 DMI_TXP_3 DMI_MTX_IRX_P3 16 50 VGAHSYNC CRT_HSYNC PEG_TX_10
T100 1 E23 R330 1 2 1.3KOhm pt_r0603 0.5% C32 AC50
T112 CFG14 CFG_13 R338 30Ohm pt_r0603 1% CRT_TVO_IREF PEG_TX_11
1 E20 50 VGAVSYNC 1 2 E33 PEG_TX_12 AD43
T98 CFG15 CFG_14 +1.25V_RUN CRT_VSYNC
1 K23 CFG_15 PEG_TX_13 AG39
GRAPHICS VID
R359 2 1 4.02KOhm 1% /* CFG16 M20 R0933,R0937 AE50

CFG_16 PEG_TX_14
1
+3.3V_RUN T99 1 CFG17 M24 AH43
T91 1 CFG18 L32
CFG_17 Non-iAMT R82
Intel 30.1 PEG_TX_15
R333 4.02KOhm 1% /* CFG19 CFG_18 1KOhm ohm 1%
2 1 N33 CFG_19
R336 2 1 4.02KOhm 1% /* CFG20 L35 1% CRESTLINE_965GM
B CFG_20 B
LCTLA_CLK, LCTLB_DATA
MCH_CLVREF
2
connect to XDP CONN.
GFX_VID_0 E35 1
1
G41 A39 1 T90 +3.3V_RUN R327,R324 Stuff. VGA_BLU
17 PM_BMBUSY# PM_BM_BUSY# GFX_VID_1 UMA UMA
1
L39 C38 1 T13 C86 R84 VGA_GRN
7,15,53 H_DPRSTP# PM_DPRSTP# GFX_VID_2 VGA_RED
PM_EXTTS#0 L36 B39 1 T12 0.1UF/10V 392Ohm
19 PM_EXTTS#0 PM_EXT_TS#_0 GFX_VID_3
PM
PM_EXTTS#1 J36 E36 1 T11 MLCC/+/-10% 1% R327 1 2 10KOhm 5% /* LCTLA_CLK No.2

19 PM_EXTTS#1 PM_EXT_TS#_1 GFX_VR_EN
2
T89 pt_r0603 R324 10KOhm 5% /* LCTLB_DATA
2
17,51 ICH_PWRGD AW49 PWROK 1 2

PLTRST#_R R329 2.2KOhm 5% LCD_DDCCLK R340 R343 R342
2
AV20 1 2
RSTIN#
2
THERMTRIP_MCH# N20 R334 1 2 2.2KOhm 5% LCD_DDCDATA 150Ohm 150Ohm 150Ohm Layout Note:
43 THERMTRIP_MCH# THERMTRIP# R536 R537 1% 1% 1%
17,53 DPRSLPVR 1 2 G36 DPRSLPVR Place 150 ohm
R332 0Ohm 5% 0Ohm 0Ohm
5% 5% termination resistors
1
CL_CLK AM49 CL_CLK0 17
CL_DATA AK50 CL_DATA0 17 close to GMCH
T2
1
1 BJ51 AT43
ME
NC_1 CL_PWROK ICH_CL_PWROK 17,37

T4 1 BK51 AN49
NC_2 CL_RST# ICH_CL_RST0# 17
T8 1 BK50 AM50
T7 NC_3 CL_VREF MCH_CLVREF
1 BL50
T10 NC_4
T16
1 BL49 NC_5 Low=DMIx2
1 BL3 NC_6 CFG5 DMI X2 Select High=DMIx4 (Default)
T17 1 BL2 NC_7
NC
T22 1 BK1 PCI Express Low=Reveise Lane

T21 NC_8
1 BJ1 H35 CFG9
MISC
T20 1 E1
NC_9 SDVO_CTRL_CLK
K36 Graphic Lane High=Normal operation
T19 NC_10 SDVO_CTRL_DATA
1 A5 NC_11 CLK_REQ# G39 CLK_3GPLLREQ# 21 FSB Dynamic Low=Dynamic ODT Disable
T3 1 C51 G40 CFG16
NC_12 ICH_SYNC# MCH_ICH_SYNC# 17 ODT High=Dynamic ODT Enable (default)
T5 1 B50
T6 NC_13
1 A50 NC_14 DMI Lane Low=Normal (default)
T9 1 A49 A37 CFG19
T18 1 BK2
NC_15 TEST_1
R32 Reversal High=Lane Reversed
NC_16 TEST_2
Low=Only SDVO or PCIEx1 is
2
CRESTLINE_965GM SDVO/PCIE
A R339 R326 CFG20 operational (defaults) A
20KOhm 0Ohm Concurrent High=SDVO and PCIEx1 are operating
5% 5%
Operation sumultaneously via PEG port
16 SB_NB_PCIE_RST# 1 2
R357 0Ohm 5% /*
1
R358 100Ohm 5% Low=No SDVO Device Present

1 2 2 1 PLTRST#_R
16,35,37 PLTRST# (defaults)
R360 0Ohm 5% SDVO_CRTL_DATA SDVO Present.
High=SDVO Device Prsent
PROJECT: Lanai 1.2 SHEET 10 OF 68 Crestline(VGA,DMI) RELEASE DATE :
5 4 3 2 1
5 4 3 2 1
D D
U10D U10E
19 DDR_A_D[0..63] DDR_A_D0 DDR_A_BS0 19 DDR_B_D[0..63] DDR_B_D0 DDR_B_BS0
AR43 SA_DQ_0 BB19 DDR_A_BS0 19,20 AP49 SB_DQ_0 AY17 DDR_B_BS0 19,20
DDR_A_D1 SA_BS_0 DDR_A_BS1 DDR_B_D1 SB_BS_0 DDR_B_BS1
AW44 SA_DQ_1 SA_BS_1 BK19 DDR_A_BS1 19,20 AR51 SB_DQ_1 SB_BS_1 BG18 DDR_B_BS1 19,20
DDR_A_D2 BA45 BF29 DDR_A_BS2 DDR_B_D2 AW50 BG36 DDR_B_BS2
DDR_A_D3 SA_DQ_2 SA_BS_2 DDR_A_BS2 19,20 DDR_B_D3 SB_DQ_2 SB_BS_2 DDR_B_BS2 19,20
AY46 SA_DQ_3 AW51 SB_DQ_3
DDR_A_D4 AR41 BL17 DDR_A_CAS# DDR_B_D4 AN51 BE17 DDR_B_CAS#
DDR_A_D5 SA_DQ_4 SA_CAS# DDR_A_CAS# 19,20 DDR_B_D5 SB_DQ_4 SB_CAS# DDR_B_CAS# 19,20
AR45 SA_DQ_5 DDR_A_DM[0..7] 19 AN50 SB_DQ_5 DDR_B_DM[0..7] 19
DDR_A_D6 AT42 AT45 DDR_A_DM0 DDR_B_D6 AV50 AR50 DDR_B_DM0
DDR_A_D7 SA_DQ_6 SA_DM_0 DDR_A_DM1 DDR_B_D7 SB_DQ_6 SB_DM_0 DDR_B_DM1
AW47 SA_DQ_7 SA_DM_1 BD44 AV49 SB_DQ_7 SB_DM_1 BD49
DDR_A_D8 BB45 BD42 DDR_A_DM2 DDR_B_D8 BA50 BK45 DDR_B_DM2
BF48 SA_DQ_9 SA_DM_3 AW38 BB50 SB_DQ_9 SB_DM_3 BL39
DDR_A_D10 BG47 AW13 DDR_A_DM4 DDR_B_D10 BA49 BH12 DDR_B_DM4
BJ45 SA_DQ_11 SA_DM_5 BG8 BE50 SB_DQ_11 SB_DM_5 BJ7
DDR_A_D12 BB47 AY5 DDR_A_DM6 DDR_B_D12 BA51 BF3 DDR_B_DM6
BG50 SA_DQ_13 SA_DM_7 AN6 AY49 SB_DQ_13 SB_DM_7 AW2
DDR_A_D14 BH49 DDR_B_D14 BF50
A
DDR_A_D15 SA_DQ_14 DDR_A_DQS[0..7] 19 SB_DQ_14 DDR_B_DQS[0..7] 19
BE45 AT46 DDR_A_DQS0 DDR_B_D15 BF49 AT50 DDR_B_DQS0
B
DDR_A_D16 SA_DQ_15 SA_DQS_0 DDR_B_D16 SB_DQ_15 SB_DQS_0 DDR_B_DQS1
AW43 SA_DQ_16 SA_DQS_1 BE48 DDR_A_DQS1 BJ50 SB_DQ_16 SB_DQS_1 BD50
DDR_A_D17 BE44 BB43 DDR_A_DQS2 DDR_B_D17 BJ44 BK46 DDR_B_DQS2
DDR_A_D18 SA_DQ_17 SA_DQS_2 SB_DQ_17 SB_DQS_2 DDR_B_DQS3
BG42 SA_DQ_18 SA_DQS_3 BC37 DDR_A_DQS3 DDR_B_D18 BJ43 SB_DQ_18 SB_DQS_3 BK39
C DDR_A_D19 BE40 BB16 DDR_A_DQS4 DDR_B_D19 BL43 BJ12 DDR_B_DQS4 C
MEMORY
DDR_A_D20 SA_DQ_19 SA_DQS_4 DDR_B_D20 SB_DQ_19 SB_DQS_4 DDR_B_DQS5
BF44 BH6 DDR_A_DQS5 BK47 BL7
MEMORY
SA_DQ_20 SA_DQS_5 SB_DQ_20 SB_DQS_5
DDR_A_D21 BH45 SA_DQ_21 SA_DQS_6 BB2 DDR_A_DQS6 DDR_B_D21 BK49 SB_DQ_21 SB_DQS_6 BE2 DDR_B_DQS6
DDR_B_DQS#[0..7] 19
DDR_A_D22 BG40 AP3 DDR_A_DQS7 DDR_B_D22 BK43 AV2 DDR_B_DQS7
SA_DQ_22 SA_DQS_7 DDR_A_DQS#[0..7] 19 SB_DQ_22 SB_DQS_7
DDR_A_D23 BF40 SA_DQ_23 SA_DQS#_0 AT47 DDR_A_DQS#0 DDR_B_D23 BK42 SB_DQ_23 SB_DQS#_0 AU50 DDR_B_DQS#0
DDR_A_D24 AR40 BD47 DDR_A_DQS#1 DDR_B_D24 BJ41 BC50 DDR_B_DQS#1
DDR_A_D25 SA_DQ_24 SA_DQS#_1 DDR_B_D25 SB_DQ_24 SB_DQS#_1
AW40 SA_DQ_25 SA_DQS#_2 BC41 DDR_A_DQS#2 BL41 SB_DQ_25 SB_DQS#_2 BL45 DDR_B_DQS#2
DDR_A_D26 AT39 BA37 DDR_A_DQS#3 DDR_B_D26 BJ37 BK38 DDR_B_DQS#3
DDR_A_D27 SA_DQ_26 SA_DQS#_3 DDR_B_D27 SB_DQ_26 SB_DQS#_3 DDR_B_DQS#4
AW36 SA_DQ_27 SA_DQS#_4 BA16 DDR_A_DQS#4 BJ36 SB_DQ_27 SB_DQS#_4 BK12
DDR_A_D28 AW41 BH7 DDR_A_DQS#5 DDR_B_D28 BK41 BK7 DDR_B_DQS#5
DDR_A_D29 SA_DQ_28 SA_DQS#_5 DDR_B_D29 SB_DQ_28 SB_DQS#_5 DDR_B_DQS#6
AY41 SA_DQ_29 SA_DQS#_6 BC1 DDR_A_DQS#6 BJ40 SB_DQ_29 SB_DQS#_6 BF2
DDR_A_D30 AV38 AP2 DDR_A_DQS#7 DDR_B_D30 BL35 AV3 DDR_B_DQS#7
DDR_A_D31 SA_DQ_30 SA_DQS#_7 DDR_B_D31 SB_DQ_30 SB_DQS#_7
AT38 SA_DQ_31 DDR_A_MA[0..13] 19,20 BK37 SB_DQ_31 DDR_B_MA[0..13] 19,20
DDR_A_D32 DDR_A_MA0 DDR_B_D32 DDR_B_MA0
SYSTEM
AV13 SA_DQ_32 SA_MA_0 BJ19 BK13 SB_DQ_32 SB_MA_0 BC18

DDR_A_D33 DDR_A_MA1 DDR_B_D33 DDR_B_MA1
SYSTEM
AT13 SA_DQ_33 SA_MA_1 BD20 BE11 SB_DQ_33 SB_MA_1 BG28
DDR_A_D34 AW11 BK27 DDR_A_MA2 DDR_B_D34 BK11 BG25 DDR_B_MA2
DDR_A_D35 SA_DQ_34 SA_MA_2 DDR_A_MA3 DDR_B_D35 SB_DQ_34 SB_MA_2 DDR_B_MA3
AV11 SA_DQ_35 SA_MA_3 BH28 BC11 SB_DQ_35 SB_MA_3 AW17
DDR_A_D36 AU15 BL24 DDR_A_MA4 DDR_B_D36 BC13 BF25 DDR_B_MA4
AT11 SA_DQ_37 SA_MA_5 BK28 BE12 SB_DQ_37 SB_MA_5 BE25
DDR_A_D38 BA13 BJ27 DDR_A_MA6 DDR_B_D38 BC12 BA29 DDR_B_MA6
BA11 SA_DQ_39 SA_MA_7 BJ25 BG12 SB_DQ_39 SB_MA_7 BC28
DDR_A_D40 BE10 BL28 DDR_A_MA8 DDR_B_D40 BJ10 AY28 DDR_B_MA8
BD10 SA_DQ_41 SA_MA_9 BA28 BL9 SB_DQ_41 SB_MA_9 BD37
DDR_A_D42 BD8 BC19 DDR_A_MA10 DDR_B_D42 BK5 BG17 DDR_B_MA10
AY9 SA_DQ_43 SA_MA_11 BE28 BL5 SB_DQ_43 SB_MA_11 BE37
DDR_A_D44 BG10 BG30 DDR_A_MA12 DDR_B_D44 BK9 BA39 DDR_B_MA12
SA_DQ_44 SA_MA_12 SB_DQ_44 SB_MA_12
DDR
DDR_A_D45 AW9 BJ16 DDR_A_MA13 DDR_B_D45 BK10 BG13 DDR_B_MA13

SA_DQ_45 SA_MA_13 SB_DQ_45 SB_MA_13
DDR
DDR_A_D46 BD7 DDR_B_D46 BJ8
DDR_A_D47 SA_DQ_46 DDR_B_D47 SB_DQ_46 DDR_B_RAS#
BB9 SA_DQ_47 BJ6 SB_DQ_47 AV16 DDR_B_RAS# 19,20
DDR_A_D48 DDR_A_RAS# DDR_B_D48 SB_RAS# T108
BB5 SA_DQ_48 SA_RAS# BE18 DDR_A_RAS# 19,20 BF4 SB_DQ_48 SB_RCVEN# AY18 1
DDR_A_D49 AY7 AY20 1 T114 DDR_B_D49 BH5
DDR_A_D50 SA_DQ_49 SA_RCVEN# DDR_B_D50 SB_DQ_49 DDR_B_WE#
AT5 SA_DQ_50 BG1 SB_DQ_50 SB_WE# BC17 DDR_B_WE# 19,20
B DDR_A_D51 AT7 BA19 DDR_A_WE# DDR_B_D51 BC2 B
DDR_A_D52 SA_DQ_51 SA_WE# DDR_A_WE# 19,20 DDR_B_D52 SB_DQ_51
AY6 SA_DQ_52 BK3 SB_DQ_52
DDR_A_D53 BB7 DDR_B_D53 BE4
DDR_A_D54 SA_DQ_53 DDR_B_D54 SB_DQ_53
AR5 SA_DQ_54 BD3 SB_DQ_54
DDR_A_D55 AR8 DDR_B_D55 BJ2
AR9 SA_DQ_56 BA3 SB_DQ_56
DDR_A_D57 AN3 DDR_B_D57 BB3
AM8 SA_DQ_58 AR1 SB_DQ_58
DDR_A_D59 AN10 DDR_B_D59 AT3
AT9 SA_DQ_60 AY2 SB_DQ_60
DDR_A_D61 AN9 DDR_B_D61 AY3
AM9 SA_DQ_62 AU2 SB_DQ_62
DDR_A_D63 AN11 DDR_B_D63 AT2
SA_DQ_63 SB_DQ_63
CRESTLINE_965GM CRESTLINE_965GM
A A
PROJECT: Lanai 1.2 SHEET 11 OF 68 Crestline(DDR2) RELEASE DATE :
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN U10F
R143 10Ohm 5% D11
U10G 1 2 +VCC_GMCH_L 2 1 AB33 VCC_NCTF_1
AB36 VCC_NCTF_2
+VCC_GMCH AT35 RB751V_40 AB37
VCC_1 VCC_NCTF_3
AT34 VCC_2 VCC_AXG_NCTF_1 T17 AC33 VCC_NCTF_4 VSS_NCTF_1 T27
AH28 VCC_3 VCC_AXG_NCTF_2 T18 AC35 VCC_NCTF_5 VSS_NCTF_2 T37
AC32 VCC_5 T19 AC36 VCC_NCTF_6 VSS_NCTF_3 U24
VCC_AXG_NCTF_3
AC31 VCC_4 VCC_AXG_NCTF_4 T21 AD35 VCC_NCTF_7 VSS_NCTF_4 U28
AK32 VCC_6 VCC_AXG_NCTF_5 T22 AD36 VCC_NCTF_8 VSS_NCTF_5 V31
AJ31 T23 +1.05V_VCCP AF33 V35
VCC_7 VCC_AXG_NCTF_6 VCC_NCTF_9 VSS_NCTF_6
AJ28 VCC_8 VCC_AXG_NCTF_7 T25 AF36 VCC_NCTF_10 VSS_NCTF_7 AA19
D AH32 +VCC_GMCH AH33 AB17 D
U15
VCC CORE
VSS NCTF
VCC_9 VCC_AXG_NCTF_8 VCC_NCTF_11 VSS_NCTF_8
AH31 AH35
TAN/Lf_T=2000hrs_105C/+/-20%
VCC_10 U16 VCC_NCTF_12 VSS_NCTF_9 AB35
VCC_AXG_NCTF_9
AH29 VCC_11 VCC_AXG_NCTF_10 U17 AH36 VCC_NCTF_13 VSS_NCTF_10 AD19
1
AF32 U19 + C366 C343 C341 C346 AH37 AD37
VCC_12 VCC_AXG_NCTF_11 CE15 22UF/4V 0.22UF/10V 0.22UF/10V 0.1UF/10V VCC_NCTF_14 VSS_NCTF_11
U20 AJ33 VCC_NCTF_15 VSS_NCTF_12 AF17
VCC_AXG_NCTF_12 MLCC/+/-20% MLCC/+/-10% MLCC/+/-10% MLCC/+/-10%
VCC_AXG_NCTF_13 U21 220UF/4V AJ35 VCC_NCTF_16 VSS_NCTF_13 AF35
Layout Note: pt_c0805_h53 pt_c0603 pt_c0603
2
VCC_AXG_NCTF_14 U23 AK33 VCC_NCTF_17 VSS_NCTF_14 AK17
pt_c7343d_h79
2
R30 VCC_13 VCC_AXG_NCTF_15 U26 370 mils form edge. AK35 VCC_NCTF_18 VSS_NCTF_15 AM17
VCC_AXG_NCTF_16 V16 AK36 VCC_NCTF_19 VSS_NCTF_16 AM24
VCC_AXG_NCTF_17 V17 AK37 VCC_NCTF_20 VSS_NCTF_17 AP26
V19 Layout Note: AD33 AP28
VCC_AXG_NCTF_18 VCC_NCTF_21 VSS_NCTF_18
V20 AJ36 AR15
VCC NCTF
VCC_AXG_NCTF_19 Inside GMCH VCC_NCTF_22 VSS_NCTF_19
VCC_AXG_NCTF_20 V21 AM35 VCC_NCTF_23 VSS_NCTF_20 AR19
V23 cavity AL33 AR28
VCC_AXG_NCTF_21 VCC_NCTF_24 VSS_NCTF_21
VCC_AXG_NCTF_22 V24 AL35 VCC_NCTF_25
+1.8V_SUS Y15 Layout Note: AA33
POWER VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
Y16
Y17
370mils form edge. +1.05V_VCCP AA35
AA36
VCC_NCTF_26
VCC_NCTF_27
VCC_NCTF_28
AU32 Y19 +VCC_AXG AP35
VCC_SM_1 VCC_AXG_NCTF_26 VCC_NCTF_29
AU33 VCC_SM_2 Y20 AP36 VCC_NCTF_30
VCC_AXG_NCTF_27
AU35 VCC_SM_3 VCC_AXG_NCTF_28 Y21 AR35 VCC_NCTF_31
1
AV33 VCC_SM_4 VCC_AXG_NCTF_29 Y23 + + + + AR36 VCC_NCTF_32
AW33 Y24 CE4 CE9 CE10 CE8 Y32
VCC_SM_5 VCC_AXG_NCTF_30 220UF/2.5V 220UF/2.5V 220UF/2.5V 220UF/2.5V VCC_NCTF_33
AW35 Y26 Y33
AY35
VCC_SM_6
VCC_SM_7
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32 Y28 pt_c7343d_h75
+/-20%
pt_c7343d_h75
+/-20%
+/-20%
pt_c7343d_h75
+/-20%
pt_c7343d_h75
Y35
VCC_NCTF_34
VCC_NCTF_35 POWER
2
BA32 VCC_SM_8 VCC_AXG_NCTF_33 Y29 Y36 VCC_NCTF_36
BA33 AA16 /* /* Y37 A3
VCC_SM_9 VCC_AXG_NCTF_34 VCC_NCTF_37 VSS_SCB1
BA35 AA17 T30 B2
VSS SCB
VCC_SM_10 VCC_AXG_NCTF_35 VCC_NCTF_38 VSS_SCB2
BB33 VCC_SM_11 VCC_AXG_NCTF_36 AB16 T34 VCC_NCTF_39 VSS_SCB3 C1
BC32 VCC_SM_12 VCC_AXG_NCTF_37 AB19 T35 VCC_NCTF_40 VSS_SCB4 BL1
BC33 VCC_SM_13 VCC_AXG_NCTF_38 AC16 U29 VCC_NCTF_41 VSS_SCB5 BL51
BC35 AC17 U31 A51
VCC SM
C VCC_SM_14 VCC_AXG_NCTF_39 Layout Note: VCC_NCTF_42 VSS_SCB6 C

BD32 VCC_SM_15 VCC_AXG_NCTF_40 AC19 U32 VCC_NCTF_43
BD35 VCC_SM_16 VCC_AXG_NCTF_41 AD15 Inside GMCH cavity for VCC_AXG. U33 VCC_NCTF_44
BE32 VCC_SM_17 VCC_AXG_NCTF_42 AD16 U35 VCC_NCTF_45
BE33 AD17 +VCC_AXG U36
VCC GFX NCTF
VCC_SM_18 VCC_AXG_NCTF_43 VCC_NCTF_46

BE35 VCC_SM_19 VCC_AXG_NCTF_44 AF16 V32 VCC_NCTF_47
BF33 VCC_SM_20 VCC_AXG_NCTF_45 AF19 V33 VCC_NCTF_48
1
BF34 AH15 C332 C334 C368 C340 C342 C326 V36
VCC_SM_21 VCC_AXG_NCTF_46 0.1UF/10V 0.1UF/10V 0.47UF/10V 1UF/10V 10UF/6.3V 22UF/4V VCC_NCTF_49
BG32 VCC_SM_22 VCC_AXG_NCTF_47 AH16 V37 VCC_NCTF_50
BG33 AH17 MLCC/+/-10% MLCC/+/-10% MLCC/+/-10% MLCC/+/-10% MLCC/+/-20% MLCC/+/-20%
VCC_SM_23 VCC_AXG_NCTF_48 pt_c0603 pt_c0603 pt_c0805_h53 pt_c0805_h53 AT33 +VCC_AXM
2
2
BG35 VCC_SM_24 VCC_AXG_NCTF_49 AH19 VCC_AXM_1
BH32 AJ16 Layout Note: AT31
VCC AXM
VCC_SM_25 VCC_AXG_NCTF_50 VCC_AXM_2
BH34 VCC_SM_26 VCC_AXG_NCTF_51 AJ17 Inside GMCH cavity VCC_AXM_3 AK29
BH35 AJ19 +1.05V_VCCP AK24
VCC_SM_27 VCC_AXG_NCTF_52 VCC_AXM_4
BJ32 VCC_SM_28 VCC_AXG_NCTF_53 AK16 VCC_AXM_5 AK23
BJ33 AK19 +VCC_AXM AL24 AJ26
VCC_SM_29 VCC_AXG_NCTF_54 VCC_AXM_NCTF_1 VCC_AXM_6
BJ34 VCC_SM_30 VCC_AXG_NCTF_55 AL16 AL26 VCC_AXM_NCTF_2 VCC_AXM_7 AJ23
1
BK32 AL17 C348 C349 C347 AL28
VCC_SM_31 VCC_AXG_NCTF_56 0.1UF/10V 0.1UF/10V 0.1UF/10V VCC_AXM_NCTF_3
BK33 AL19 AM26
VCC AXM NCTF

VCC_SM_32 VCC_AXG_NCTF_57 MLCC/+/-10% MLCC/+/-10% MLCC/+/-10% VCC_AXM_NCTF_4
BK34 VCC_SM_33 VCC_AXG_NCTF_58 AL20 AM28 VCC_AXM_NCTF_5
2
BK35 VCC_SM_34 VCC_AXG_NCTF_59 AL21 AM29 VCC_AXM_NCTF_6
BL33 VCC_SM_35 VCC_AXG_NCTF_60 AL23 AM31 VCC_AXM_NCTF_7
AU30 VCC_SM_36 VCC_AXG_NCTF_61 AM15 Non-iAMT AM32 VCC_AXM_NCTF_8
VCC_AXG_NCTF_62 AM16 AM33 VCC_AXM_NCTF_9
VCC_AXG_NCTF_63 AM19 AP29 VCC_AXM_NCTF_10
VCC_AXG_NCTF_64 AM20 AP31 VCC_AXM_NCTF_11
AM21 AP32 VCC_AXM_NCTF_12
+VCC_AXG VCC_AXG_NCTF_65
R20 VCC_AXG_1 VCC_AXG_NCTF_66 AM23 AP33 VCC_AXM_NCTF_13
T14 VCC_AXG_2 VCC_AXG_NCTF_67 AP15 AL29 VCC_AXM_NCTF_14
1
W13 AP16 C321 C350 C337 AL31
VCC_AXG_3 VCC_AXG_NCTF_68 22UF/4V 0.22UF/10V 0.22UF/10V VCC_AXM_NCTF_15
W14 VCC_AXG_4 VCC_AXG_NCTF_69 AP17 AL32 VCC_AXM_NCTF_16
Y12 AP19 MLCC/+/-20% MLCC/+/-10% MLCC/+/-10% AR31
VCC_AXG_5 VCC_AXG_NCTF_70 pt_c0805_h53 pt_c0603 pt_c0603 VCC_AXM_NCTF_17
2
AA20 VCC_AXG_6 VCC_AXG_NCTF_71 AP20 AR32 VCC_AXM_NCTF_18
B B
AA23 VCC_AXG_7 VCC_AXG_NCTF_72 AP21 AR33 VCC_AXM_NCTF_19
AA26 VCC_AXG_8 VCC_AXG_NCTF_73 AP23
AA28 VCC_AXG_9 VCC_AXG_NCTF_74 AP24
AB21 AR20 Layout Note:
VCC_AXG_10 VCC_AXG_NCTF_75
AB24 VCC_AXG_11 VCC_AXG_NCTF_76 AR21 Place close to GMCH edge.
AB29 AR23 CRESTLINE_965GM
AC20 AR24
VCC GFX
AC21 VCC_AXG_14 VCC_AXG_NCTF_79 AR26
AC23 VCC_AXG_15 VCC_AXG_NCTF_80 V26
AC28 Y31 +1.8V_SUS
AC29 VCC_AXG_19
1
AD20 VCC_AXG_20 +
1
AD23 C95 CE11 C92 C91
VCC_AXG_21 VCCSM_LF1 0.1UF/10V 330UF/6.3V 22UF/4V 22UF/4V
AD24 VCC_AXG_22 VCC_SM_LF1 AW45
AD28 BC39 VCCSM_LF2 MLCC/+/-10% pt_c7343d_h110 MLCC/+/-20% MLCC/+/-20%
VCC SM LF
VCC_AXG_23 VCC_SM_LF2 VCCSM_LF3 +/-20% pt_c0805_h53 pt_c0805_h53
2
AF21 VCC_AXG_24 VCC_SM_LF3 BE39
AF26 BD17 VCCSM_LF4
VCC_AXG_25 VCC_SM_LF4 VCCSM_LF5
AA31 VCC_AXG_26 VCC_SM_LF5 BD4
AH20 AW8 VCCSM_LF6 Layout Note:
VCC_AXG_27 VCC_SM_LF6 VCCSM_LF7
AH21 VCC_AXG_28 VCC_SM_LF7 AT6 Place C1117 where LVDS
AH23 Layout Note:
VCC_AXG_29 andDDR2 taps
AH24 VCC_AXG_30 Place on the edge
AH26 VCC_AXG_31
1
1
AD31 C370 C369 C376 C360 C333 C344 C328
VCC_AXG_32 0.1UF/10V 0.1UF/10V 0.22UF/10V 0.22UF/10V 0.47UF/10V 1UF/10V 1UF/10V
AJ20 VCC_AXG_33
AN14 MLCC/+/-10% MLCC/+/-10% MLCC/+/-10% MLCC/+/-10% MLCC/+/-10% MLCC/+/-10% MLCC/+/-10%
VCC_AXG_34 pt_c0603 pt_c0603 pt_c0603 pt_c0603 pt_c0603
2
A A
CRESTLINE_965GM
PROJECT: Lanai 1.2 SHEET 12 OF 68 Crestline(VCC,NCTF) RELEASE DATE :
5 4 3 2 1
5 4 3 2 1
FB_180ohm+-25_100mHz_1500mA_0.09ohm DC
L11 180Ohm R102 0Ohm 5% pt_r0603

1 2 +VCCA_CRTDAC 1 2 +VCCA_CRTDAC_R +3.3V_RUN U10H +1.05V_VCCP
+3.3V_RUN
U7
BLM18PG181SN1 C100 IN1 3OUT J32 U13
VCCSYNC VTT_1
1
0.1UF/10V U12
VTT_2
1
MLCC/+/-10% GND 22NF/16V /* C345 +VCCA_CRTDAC_R A33 U11 C374 C373
VCCA_CRT_DAC_1 VTT_3
1
0.1UF/10V 2.2UF/6.3V 4.7UF/10V D12
2
B33 VCCA_CRT_DAC_2 VTT_4 U9
MLCC/+/-10% MLCC/+/-10% MLCC/+/-10% RB751V_40
2
U8
CRT
VTT_5 pt_c0603 pt_c0805_h37 /*
2
VTT_6 U7
+VCC_TVBG_R +VCC_HV_L
12
A30 VCCA_DAC_BG VTT_7 U5
VTT_8 U3
B32 U2 R142
D VSSA_DAC_BG VTT_9 Place on the edge 10Ohm 5% D
45mA MAX. VTT_10 U1
+1.05V_VCCP /*
Non-iAMT T13
VTT
FB_120ohm+-25%_100mHz +1.25V_RUN +VCCA_DPLLA VTT_11
40mA MAx. B49 VCCA_DPLLA VTT_12 T11
_200mA_0.2ohm DC
2
10uH+-20%_100mA VTT_13 T10
L23 +VCCA_DPLLB H49 T9
VCCA_DPLLB VTT_14
1
+1.25V_RUN 1 2 +VCCA_DPLLA T7 C363 C377 +
PLL
+VCCA_HPLL VTT_15 0.47UF/6.3V 4.7UF/10V CE17 +3.3V_RUN
AL2 VCCA_HPLL VTT_16 T6
1
L30 10uH + CE13 C327 T5 MLCC/+/-10% MLCC/+/-10%
VTT_17 220UF/4V
1
120Ohm/100Mhz pt_l0805 470UF/4V 0.1UF/10V +VCCA_MPLL pt_c0805_h37
2
+VCCA_HPLL
AM2 VCCA_MPLL VTT_18 T3 Non-
pt_c7343d_h157 MLCC/+/-10% C336 pt_c7343d_h79
2
1 2 T2
+/-20% 1000PF/50V VTT_19
R3 TAN/Lf_T=2000hrs_105C/+/-20% iAMT
A LVDS
VTT_20
1
1
BLM18AG121SN1D C378 C375 1 +VCC_TX_LVDS A41 +1.25V_RUN +1.25V_RUN
2
2 VCCA_LVDS VTT_21 R2
22UF/10V 0.1UF/10V R1 Place on the edge JUMP
MLCC/+80%-20% MLCC/+/-10% MLCC/+/-10% VTT_22
B41 VSSA_LVDS
pt_c1206_h71 L26 L29 JP8
2
+VCCA_DPLL 1 2 +VCCA_DPLLB +3.3V_RUN AT23 +VCC_AXD_L 1 2 +VCC_AXD_R 1 2

VCC_AXD_1 0Ohm 0Ohm
VCC_AXD_2 AU28
1
10uH + CE12 C324 K50 AU24 C354 C355 pt_r0603 Reserved L1202 pad for +VCC_AXF
AXD
VCCA_PEG_BG VCC_AXD_3
1
L16 pt_l0805 470UF/4V 0.1UF/10V C85 AT29 1UF/10V 22UF/10V 5%
VCC_AXD_4 inductor
1
120Ohm/100Mhz pt_c7343d_h157 MLCC/+/-10% 0.1UF/10V K49 AT25 MLCC/+/-10% MLCC/+80%-20% C116 C117
A PEG
+VCCA_MPLL 0.1Caps should be +/-20% MLCC/+/-10% VSSA_PEG_BG VCC_AXD_5 pt_c0603 pt_c1206_h71 1UF/10V 10UF/6.3V
2
1 2 VCC_AXD_6 AT30
Place caps MLCC/+/-10% MLCC/+/-20%
2
BLM18AG121SN1D
placed 200 mils +VCCA_PEG_PLL pt_c0603 pt_c0805_h53
2
U51 VCCA_PEG_PLL VCC_AXD_NCTF AR29 close to
R136 with in its pins.
1 2 VCC_AXD
0.5Ohm 1% AW18 B23 +VCC_AXF
pt_r0603 VCCA_SM_1 VCC_AXF_1
AV19 B21 Place caps close to
AXF
AU19
VCCA_SM_2
VCCA_SM_3 POWER VCC_AXF_2
VCC_AXF_3 A21 VCC_AXF
1
+VCC_MPLL_L C121 JUMP AU18

0.1UF/10V VCCA_SM_4
AU17 VCCA_SM_5 VCC_DMI AJ50 +1.25V_RUN
1
C382 MLCC/+/-10% JP7
A SM
1
22UF/10V +VCCA_SM C320
2
+1.25V_RUN 1 2 AT22 VCCA_SM_7

C MLCC/+80%-20% 0Ohm AT21 BK24 +VCC_SM_CK 0.1UF/10V C
SM CK
VCCA_SM_8 VCC_SM_CK_1
1
1
pt_c1206_h71 + CE14 C361 C357 C358 C362 MLCC/+/-10%
2
AT19 VCCA_SM_9 VCC_SM_CK_2 BK23

100UF/6.3V 4.7UF/6.3V 22UF/4V 22UF/4V 1UF/10V
2
AT18 VCCA_SM_10 VCC_SM_CK_3 BJ24
pt_c3528_h79 MLCC/+/-10% MLCC/+/-20% MLCC/+/-20% MLCC/+/-10% AT17 BJ23 Place JP1206 for +1.8V_SUS
+/-20% pt_c0603 pt_c0805_h53 pt_c0805_h53 pt_c0603 VCCA_SM_11 VCC_SM_CK_4
2
Non-iAMT AR17 VCCA_SM_NCTF_1
1uH+-20%_300mA
2
AR16 VCCA_SM_NCTF_2 L8 JP2 +1.8V_SUS

A43 +VCC_TX_LVDS 2 1 +VCC_TX_LVDS_R 1 2
A CK
JP4 VCC_TX_LVDS 0Ohm
BC29 VCCA_SM_CK_1
1
+VCCA_SM_CK +3.3V_RUN 1UH/300mA pt_l0805_h53 JP3 +1.8V_RUN
+1.25V_RUN 1 2 BB29 VCCA_SM_CK_2 +
1
0Ohm C40 C330 CE3 1 2
VCC_HV_1 1000PF/50V 220UF/4V 0Ohm /*
C25 B40
HV
VCCA_TVA_DAC_1 VCC_HV_2
1
1
C103 C105 C106 C104 +VCC_TVDACA_R B25 C90 MLCC/+/-10% pt_c7343d_h79 JUMP
VCCA_TVA_DAC_2
1
JUMP 22UF/4V 1UF/10V 1UF/10V 0.1UF/10V 0.1UF/10V TAN/Lf_T=2000hrs_105C/+/-20%
2
C27 VCCA_TVB_DAC_1
MLCC/+/-20% MLCC/+/-10% MLCC/+/-10% MLCC/+/-10% +VCC_TVDACB_R B27 AD51 MLCC/+/-10%
TV
pt_c0805_h53 pt_c0603 pt_c0603 VCCA_TVB_DAC_2 VCC_PEG_1 +VCC_PEG +1.05V_VCCP
2
2
B28 W50
PEG
+VCC_TVDACC_R VCCA_TVC_DAC_1 VCC_PEG_2
2
A28 VCCA_TVC_DAC_2 VCC_PEG_3 W51
V49 L25
L27 VCC_PEG_4
V50 1 2
D TV/CRT
+1.25V_RUN BLM21PG221SN1D +VCCD_TVDAC_R VCC_PEG_5
M32 VCCD_CRT
220Ohm/100Mhz L29 91NH/1.5A 91nH+-20%_1.5A
VCCD_TVDAC
1
1 2 +VCCA_PEG_PLL Place JP1204 for AH50 +VCC_RXR_DMI + C83
DMI
+1.25V_RUN +VCCQ_TVDAC_R VCC_RXR_DMI_1 CE1 10UF/6.3V
Non-iAMT +1.8V_SUS N28 VCCD_QDAC VCC_RXR_DMI_2 AH51
1
pt_l0805_h41 MLCC/+/-20% M08 CKT: 91uH+-20%_1.5A

R318 220UF/4V pt_c0805_h53
2
AN2 VCCD_HPLL need to be confirm
FB_220ohm+-25_100MHz 1Ohm 1% A7 +VTTLF1 pt_c7343d_h79
2
VTTLF
VTTLF1
1
_2A_0.1ohm DC pt_r0603 C325 +VCCA_PEG_PLL U48 VCCD_PEG_PLL VTTLF2 F2 +VTTLF2 TAN/Lf_T=2000hrs_105C/+/-20%

0.1UF/10V JP5 AH1 +VTTLF3 +1.05V_VCCP
VTTLF3
1
MLCC/+/-10% C122 C322 +VCCD_LVDS

2
1 2 J41
LVDS
+1.8V_SUS VCCD_LVDS_1
0.1UF/10V 0.1UF/10V 0Ohm L24
2
H42 VCCD_LVDS_2
1
C323 MLCC/+/-10% MLCC/+/-10% 1 2

1
1
10UF/6.3V C338 C329
2
B MLCC/+/-20% 1UF/10V 10UF/6.3V 91NH/1.5A B
1
pt_c0805_h53 JP6 MLCC/+/-10% MLCC/+/-20% CRESTLINE_965GM 91nH+-20%_1.5A
2
+
pt_c0603 pt_c0805_h53 CE2 C84
2
2
+1.8V_RUN 1 2
0Ohm /* 10UF/6.3V
220UF/4V MLCC/+/-20%
JUMP
2
+VTTLF1 pt_c7343d_h79 pt_c0805_h53
2
+VTTLF2 TAN/Lf_T=2000hrs_105C/+/-20%
+VTTLF3
FB_180ohm+-25_100mHz_1500mA_0.09ohm DC
L14 180Ohm R349 0Ohm 5% pt_r0603
1
1 2 +VCC_TVDACA 1 2 +VCC_TVDACA_R C127 C372 C129
+3.3V_RUN
U21 0.47UF/10V 0.47UF/10V 0.47UF/10V
1
BLM18PG181SN1 C115 C356 IN1 3OUT MLCC/+/-10% MLCC/+/-10% MLCC/+/-10%

1
22nF & 0.1uF for 10UF/6.3V 0.1UF/10V pt_c0603 pt_c0603 pt_c0603
2
No.45 MLCC/+/-20% MLCC/+/-10% GND 22NF/16V /*
VCC_TVDACA:C_R should
pt_c0805_h53
2
be placed with in 250

2
mils from Crestline. +1.8V_SUS

L13
R362 0Ohm 5% pt_r0603 R111 30mOhm 1% R361 0Ohm 5% pt_r0603 1UH/300mA
+VCC_TVBG_R 1 2 +VCC_TVBG 1 2 +VCC_TVDACB 1 2 +VCC_TVDACB_R +1.5V_RUN +VCC_SM_CK 1 2
U23 pt_r0603 U24 R331 0Ohm 5% pt_r0603
1
IN1 3OUT C365 C364 IN1 3OUT 1 2 +VCCD_TVDAC_R pt_l0805_h53 1uH+-20%_300mA
1
0.1UF/10V 0.1UF/10V U19 R109

1
1
GND MLCC/+/-10% MLCC/+/-10% GND 22NF/16V /* C339 IN1 3OUT C111 C113 1Ohm
22NF/16V 0.1UF/10V 22UF/10V 0.1UF/10V 1%
2
/* MLCC/+/-10% GND 22NF/16V /* MLCC/+80%-20%MLCC/+/-10% pt_r0603

2
pt_c1206_h71
2
2
+VCC_SM_CK_L
R353 0Ohm 5% pt_r0603 No.7
1
A +VCC_TVDACC 1 2 +VCC_TVDACC_R C110 A
U22 R538 R328 0Ohm 5% pt_r0603 10UF/6.3V
C359 IN1 3OUT 1 2 +VCCQ_TVDAC 1 2 +VCCQ_TVDAC_R No.7 MLCC/+/-20%
1
+1.5V_RUN +3.3V_RUN 0.1UF/10V 100Ohm pt_r0603 U18 pt_c0805_h53
2
1
D10 R113 10Ohm MLCC/+/-10% GND 22NF/16V /* C335 IN1 3OUT
1
2+VCC_TVDAC_L 1 0.1UF/10V
2
1 2
5% /* FB_180ohm+-25_ MLCC/+/-10% GND 22NF/16V /* C538
2
RB751V_40 /*
2
100mHz_1500mA_ 1UF/10V
TV DAC Voltage Follower Circuit -700mV.
2
0.09ohm DC MLCC/+/-10%
PROJECT: Lanai 1.2 SHEET 13 OF 68 Crestline(POWER) RELEASE DATE :
5 4 3 2 1
5 4 3 2 1
U10I
A13 VSS_1 VSS_100 AW24

AA21 AW7 U10J
VSS_5 VSS_104
AA24 VSS_6 VSS_105 AY10 C46 VSS_199 VSS_287 W11
AA29 VSS_7 VSS_106 AY24 C50 VSS_200 VSS_288 W39
AB20 VSS_8 VSS_107 AY37 C7 VSS_201 VSS_289 W43
D AB23 VSS_9 VSS_108 AY42 D13 VSS_202 VSS_290 W47 D
AB26 VSS_10 VSS_109 AY43 D24 VSS_203 VSS_291 W5
AB28 VSS_11 VSS_110 AY45 D3 VSS_204 VSS_292 W7
AB31 VSS_12 VSS_111 AY47 D32 VSS_205 VSS_293 Y13
AC10 VSS_13 VSS_112 AY50 D39 VSS_206 VSS_294 Y2
AC13 VSS_14 VSS_113 B10 D45 VSS_207 VSS_295 Y41
AC3 VSS_15 VSS_114 B20 D49 VSS_208 VSS_296 Y45
AC39 VSS_16 VSS_115 B24 E10 VSS_209 VSS_297 Y49
AD1 VSS_19 VSS_118 B35 E28 VSS_212 VSS_300 Y11
AD21 VSS_20 VSS_119 B38 E32 VSS_213 VSS_301 P29
AD26 VSS_21 VSS_120 B43 E47 VSS_214 VSS_302 T29
AD29 VSS_22 VSS_121 B46 F19 VSS_215 VSS_303 T31
AD3 VSS_23 VSS_122 B5 F36 VSS_216 VSS_304 T33
AD41 VSS_24 VSS_123 B8 F4 VSS_217 VSS_305 R28
AD45 VSS_25 VSS_124 BA1 F40 VSS_218
AD49 VSS_26 VSS_125 BA17 F50 VSS_219
AD5 VSS_27 VSS_126 BA18 G1 VSS_220
AD50 VSS_28 VSS_127 BA2 G13 VSS_221 VSS_306 AA32
AD8 VSS_29 VSS_128 BA24 G16 VSS_222 VSS_307 AB32
AE10 VSS_30 VSS_129 BB12 G19 VSS_223 VSS_308 AD32
AE14 VSS_31 VSS_130 BB25 G24 VSS_224 VSS_309 AF28
AE6 VSS_32 VSS_131 BB40 G28 VSS_225 VSS_310 AF29
AF20 BB44 G29 AT27
AF23
AF24
VSS_33
VSS_34
VSS_35
VSS VSS_132
VSS_133
VSS_134
BB49
BB8
G33
G42
VSS_226
VSS_227
VSS_228
VSS_311
VSS_312
VSS_313
AV25
H50
AF31 VSS_36 VSS_135 BC16 G45 VSS_229
AG2 VSS_37 VSS_136 BC24 G48 VSS_230
C AG38 BC25 G8 C
VSS_38 VSS_137 VSS_231
AG43 VSS_39 VSS_138 BC36 H24 VSS_232
AG47 VSS_40 VSS_139 BC40 H28 VSS_233
AG50 VSS_41 VSS_140 BC51 H4 VSS_234
AH3 VSS_42 VSS_141 BD13 H45 VSS_235
AH40 VSS_43 VSS_142 BD2 J11 VSS_236
AH41 VSS_44 VSS_143 BD28 J16 VSS_237
AJ11 VSS_47 VSS_146 BD5 J28 VSS_240
AJ13 BE1 J33
AJ21
AJ24
VSS_48
VSS_49
VSS_50
VSS_147
VSS_148
VSS_149
BE19
BE23
J35
J39
VSS_241
VSS_242
VSS_243
VSS
AJ29 VSS_51 VSS_150 BE30
AJ32 VSS_52 VSS_151 BE42 K12 VSS_245
AJ43 VSS_53 VSS_152 BE51 K47 VSS_246
AJ45 VSS_54 VSS_153 BE8 K8 VSS_247
AJ49 VSS_55 VSS_154 BF12 L1 VSS_248
AK20 VSS_56 VSS_155 BF16 L17 VSS_249
AK21 VSS_57 VSS_156 BF36 L20 VSS_250
AK26 VSS_58 VSS_157 BG19 L24 VSS_251
AK28 VSS_59 VSS_158 BG2 L28 VSS_252
AK31 VSS_60 VSS_159 BG24 L3 VSS_253
AK51 VSS_61 VSS_160 BG29 L33 VSS_254
AL1 VSS_62 VSS_161 BG39 L49 VSS_255
AM11 VSS_63 VSS_162 BG48 M28 VSS_256
AM13 VSS_64 VSS_163 BG5 M42 VSS_257
AM3 VSS_65 VSS_164 BG51 M46 VSS_258
AM4 VSS_66 VSS_165 BH17 M49 VSS_259
B B
AM41 VSS_67 VSS_166 BH30 M5 VSS_260
AM45 VSS_68 VSS_167 BH44 M50 VSS_261
AN1 VSS_69 VSS_168 BH46 M9 VSS_262
AN38 VSS_70 VSS_169 BH8 N11 VSS_263
AN39 VSS_71 VSS_170 BJ11 N14 VSS_264
AN43 VSS_72 VSS_171 BJ13 N17 VSS_265
AN5 VSS_73 VSS_172 BJ38 N29 VSS_266
AN7 VSS_74 VSS_173 BJ4 N32 VSS_267
AP4 VSS_75 VSS_174 BJ42 N36 VSS_268
AP48 VSS_76 VSS_175 BJ46 N39 VSS_269
AP50 VSS_77 VSS_176 BK15 N44 VSS_270
AR11 VSS_78 VSS_177 BK17 N49 VSS_271
AR2 VSS_79 VSS_178 BK25 N7 VSS_272
AR39 VSS_80 VSS_179 BK29 P19 VSS_273
AR44 VSS_81 VSS_180 BK36 P2 VSS_274
AR47 VSS_82 VSS_181 BK40 P23 VSS_275
AR7 VSS_83 VSS_182 BK44 P3 VSS_276
AT10 VSS_84 VSS_183 BK6 P50 VSS_277
AT14 VSS_85 VSS_184 BK8 R49 VSS_278
AT41 VSS_86 VSS_185 BL11 T39 VSS_279
AT49 VSS_87 VSS_186 BL13 T43 VSS_280
AU1 VSS_88 VSS_187 BL19 T47 VSS_281
AU23 VSS_89 VSS_188 BL22 U41 VSS_282
AU29 VSS_90 VSS_189 BL37 U45 VSS_283
AU3 VSS_91 VSS_190 BL47 U50 VSS_284
AU36 VSS_92 VSS_191 C12 V2 VSS_285
AU49 VSS_93 VSS_192 C16 V3 VSS_286
AU51 VSS_94 VSS_193 C19
A AV39 VSS_95 VSS_194 C28 A
AV48 C29 CRESTLINE_965GM
VSS_96 VSS_195
AW1 VSS_97 VSS_196 C33
AW12 VSS_98 VSS_197 C36
AW16 VSS_99 VSS_198 C41
CRESTLINE_965GM
PROJECT: Lanai 1.2 SHEET 14 OF 68 Crestline(VSS) RELEASE DATE :
5 4 3 2 1
5 4 3 2 1
+RTC_CELL +RTC_CELL
2
1 2
R400 10MOhm 5% R187 R231
332KOhm 332KOhm
1% 1%
X3
No.25 +/-10ppm/6PF ICH_INTVRMEN ICH_LAN100_SLP
1
32.768KHZ
2
ICH_RTCX2 1 4 1 2 ICH_RTCX1
R384 0Ohm 5% R190 R230
0Ohm 5% 0Ohm 5%
/* /*
1
D D
3
C424 C412 +1.05V_VCCP
1
15PF/50V 15PF/50V
2
MLCC/+/-5% MLCC/+/-5%
/* /*
1
ICH8M Internal VR Enable Strap ICH8M LAN100SLP Strap
(Internal VR for VccSus1.05, VccSus1.5 and VccCL1.5) (Internal VR for VccLAN1.05 and VccCL1.05) R186 R203 R210
56Ohm 56Ohm 56Ohm
ICH_INTVRMEN Low = Internal VR Disabled ICH_LAN100_SLP Low = Internal VR Disabled 5% 5% 5%
+RTC_CELL High = Internal VR Enable(Default) High = Internal VR Enable(Default) /* /*
2
H_DPRSTP#
U32A H_DPSLP#
2
ICH_RTCX1 AG25 E5
ICH_RTCX2 RTCX1 FWH0/LAD0 LPC_LAD0 37 H_FERR#
R229 R183 AF24 F5
RTCX2 FWH1/LAD1 LPC_LAD1 37
1MOhm G8
20KOhm ICH_RTCRST# FWH2/LAD2 LPC_LAD2 37
5% AF23 F6
5% RTCRST# FWH3/LAD3 LPC_LAD3 37
ICH_RTCRST# ICH_INTRUDER# AD22 +3.3V_RUN
1
1
INTRUDER# FWH4/LFRAME# C4 LPC_LFRAME# 37
RTC
LPC
ICH_INTRUDER# ICH_INTVRMEN AF25 G9 LPC_LDRQ0# 1 T65
ICH_LAN100_SLP AD21 INTVRMEN LDRQ0# LPC_LDRQ1# T73
1
LAN100_SLP LDRQ1#/GPIO23 E6 1
1
C202
1UF/10V/X7R T133 1 GLAN_CLK B24 GLAN_CLK A20GATE AF13 SIO_A20GATE
SIO_A20GATE 37
R192 R167
MLCC/+/-10% AG26 10KOhm 10KOhm
A20M# H_A20M# 7
pt_c0603 5% 5%
2
D22 LAN_RSTSYNC
AF26 H_DPRSTP#
DPRSTP# H_DPRSTP# 7,10,53
T81 1 LAN_RXD0 H_DPSLP#
2
C21 LAN_RXD0 DPSLP# AE26 H_DPSLP# 7
T131 1 LAN_RXD1 B21 LAN_RXD1
SIO_A20GATE
T80 1 LAN_RXD2 C22 AD24 H_FERR#
LAN / GLAN
LAN_RXD2 FERR# H_FERR# 7 SIO_RCIN#
C R208 2 1 33Ohm 5% ACZ_BIT_CLK T71 1 LAN_TXD0 D21 AG29 C
36 ICH_AZ_MDC_BITCLK LAN_TXD0 CPUPWRGD/GPIO49 H_PWRGOOD 7
T59 1 LAN_TXD1 E20 LAN_TXD1
44 ICH_AZ_CODEC_BITCLK
R219 2 1 33Ohm 5% T75 1 LAN_TXD2 C20 LAN_TXD2 IGNNE# AF27 H_IGNNE# 7
T122 1 AH21 AE24 +1.05V_VCCP
GLAN_DOCK#/GPIO13 INIT# H_INIT# 7
1
C215 C226 AC20
CPU
INTR H_INTR 7
27PF/50V 27PF/50V
+1.5V_PCIE_ICH 1 2 GLAN_COMP D25 GLAN_COMPI RCIN# AH14 SIO_RCIN#
SIO_RCIN# 37
1
No.57 MLCC/+/-5% MLCC/+/-5% C25
/* R268 24.9Ohm 1% GLAN_COMPO R194
2
NMI AD23 H_NMI 7

ACZ_BIT_CLK AJ16 AG28 56Ohm
ACZ_SYNC HDA_BIT_CLK SMI# H_SMI# 7
AJ15 5%
HDA_SYNC
STPCLK# AA24 H_STPCLK# 7
R201 1 33Ohm 5% ACZ_SYNC ACZ_RST# THERMTRIP#_ICH
2
36 ICH_AZ_MDC_SYNC 2 AE14 HDA_RST#
R202 2 1 33Ohm 5% AE27 THERMTRIP#_ICH
44 ICH_AZ_CODEC_SYNC THRMTRIP#
44 ICH_AZ_CODEC_SDIN0 AJ17 HDA_SDIN0
R205 2 1 33Ohm 5% ACZ_RST# AH17 AA23 1 T42
36 ICH_AZ_MDC_RST# 36 ICH_AZ_MDC_SDIN1 HDA_SDIN1 TP8 IDE_DD[0..15]
R199 2 1 33Ohm 5% T121 1 AH15
IHDA
44 ICH_AZ_CODEC_RST# HDA_SDIN2 IDE_DD0 IDE_DD[0..15] 31
T43 1 AD13 V1
R213 ACZ_SDOUT HDA_SDIN3 DD0 IDE_DD1
36 ICH_AZ_MDC_SDOUT 2 1 33Ohm 5%
DD1 U2
R220 2 1 33Ohm 5% ACZ_SDOUT AE13 V3 IDE_DD2
44 ICH_AZ_CODEC_SDOUT HDA_SDOUT DD2 IDE_DD3
DD3 T1
SPEAKER_DET# AE10 V4 IDE_DD4
46 SPEAKER_DET# RTC_BAT_DET# HDA_DOCK_EN#/GPIO33 DD4 IDE_DD5
Place all series terms close to ICH8 except for SDIN input lines, which 40 RTC_BAT_DET# AG14 HDA_DOCK_RST#/GPIO34 DD5 T5
AB2 IDE_DD6
should be close to source. Placement of R208, R201, R205, R213 should SATA_ACT# DD6 IDE_DD7
AF10 SATALED# DD7 T6
equal distance to the T split trace point as R219, R202, R199, R220 T3 IDE_DD8
DD8 IDE_DD9
31 SATA_RX0- AF6 SATA0RXN DD9 R2
respective. Basically, keep the same distance from T for all series 31 SATA_RX0+ AF5 T4 IDE_DD10
SATA_TX0-_C SATA0RXP DD10 IDE_DD11
termination resistors. AH5 SATA0TXN DD11 V6
SATA_TX0+_C AH6 V5 IDE_DD12
SATA0TXP DD12 IDE_DD13
DD13 U1
AG3 V2 IDE_DD14
B SATA1RXN DD14 IDE_DD15 B
AG4 U6
IDE
SATA1RXP DD15
AJ4 SATA1TXN
C427 MLCC/+/-10% 2 1 3900PF/50V SATA_TX0-_C AJ3 AA4 IDE_DA0
31 SATA_TX0- SATA_TX0+_C SATA1TXP DA0 IDE_DA1 IDE_DA0 31
C428 MLCC/+/-10% 2 1 3900PF/50V AA1
SATA
31 SATA_TX0+ DA1 IDE_DA2 IDE_DA1 31
AF2 SATA2RXN DA2 AB3 IDE_DA2 31
AF1 SATA2RXP
AE4 Y6 IDE_DCS1#
SATA2TXN DCS1# IDE_DCS3# IDE_DCS1# 31
Distance between the ICH-8 M and cap on the "P" signal AE3 SATA2TXP DCS3# Y5 IDE_DCS3# 31
should be identical distance between the ICH-8 M and cap on AB7 W4
21 CLK_PCIE_SATA# SATA_CLKN DIOR# IDE_DIOR# 31
the "N" signal for same pair. 21 CLK_PCIE_SATA AC6 SATA_CLKP DIOW# W3 IDE_DIOW# 31
DDACK# Y2 IDE_DDACK# 31
Place within 500 mils 1 2 SATABIAS AG1 Y3
SATARBIAS# IDEIRQ IDE_IRQ 31
AG2 Y1
of ICH8 ball R198 24.9Ohm 1% SATARBIAS IORDY
W5
IDE_DIORDY 31
+3.3V_RUN DDREQ IDE_DDREQ 31
The circuit is only
ICH8-M
needed if the
+3.3V_RUN
platform has the
SNIFFER.
Pull up for each detect line
2
R197 XOR Chain Entrance strap R223

10KOhm 1KOhm
38,41 LED_MASK# +3.3V_RUN +3.3V_RUN
5% 5%
ICH _RSVD ACZ_SDOUT Description /*
1
ACZ_SDOUT
2
0 0 RSVD
1
R196 R209
G
SATA_ACT# ICH_RSVD 17
100KOhm 100KOhm
3
S 2
42 SATA_ACT#_R
0
D
1 Enter XOR chain 5% 5%

1
A A
Q37 2N7002 R181
1
1
Id=180mA/Pd=300mW 1 0 Normal operation (Default) 1KOhm SPEAKER_DET# RTC_BAT_DET#
5%
2 1 /*
1 1 Set PCIE port config bit 1
2
R182 0Ohm 5% /*
PROJECT: Lanai 1.2 SHEET 15 OF 68 ICH8: IDE/AC97/LPC/RTCRELEASE DATE :
5 4 3 2 1
5 4 3 2 1
Place TX DC blocking caps close ICH8. U32D BIOS should not enable the internal GPIO pull up
50 PCIE_RX1- P27 PERN1 DMI0RXN V27 DMI_MTX_IRX_N0 10 resistor
P26 V26 +3.3V_RUN
PCIE_TXN1_C 50 PCIE_RX1+ PCIE_TXN1_C PERP1 DMI0RXP DMI_MTX_IRX_P0 10
C465 2 1 0.1UF/10V MLCC/+/-10% N29 U29
50 PCIE_TX1- PETN1 DMI0TXN DMI_MRX_ITX_N0 10
Direct Media Interface

MiniWWAN PCIE_TXP1_C N28 U28
PCIE_TXP1_C PETP1 DMI0TXP DMI_MRX_ITX_P0 10 SB_NB_PCIE_RST#
C469 2 1 0.1UF/10V MLCC/+/-10% R519 1 2 10KOhm 5%
50 PCIE_TX1+ SB_WLAN_PCIE_RST# R253 10KOhm 5%
50 PCIE_RX2- M27 PERN2 DMI1RXN Y27 DMI_MTX_IRX_N1 10 1 2
50 PCIE_RX2+ M26 PERP2 DMI1RXP Y26 DMI_MTX_IRX_P1 10
C475 2 1 0.1UF/10V MLCC/+/-10% PCIE_TXN2_C PCIE_TXN2_C L29 W29 SB_NB_PCIE_RST# R520 1 2 100KOhm 5%
50 PCIE_TX2- PCIE_TXP2_C PETN2 DMI1TXN DMI_MRX_ITX_N1 10 SB_WLAN_PCIE_RST#
MiniWLAN L28 W28 R250 1 2 100KOhm 5%
PCIE_TXP2_C PETP2 DMI1TXP DMI_MRX_ITX_P1 10 SB_LOM_PCIE_RST#
C473 2 1 0.1UF/10V MLCC/+/-10% R280 1 2 20KOhm 5%
PCI-Express
50 PCIE_TX2+ SB_WWAN_PCIE_RST# R274 20KOhm 5%
K27 PERN3 DMI2RXN AB26 DMI_MTX_IRX_N2 10 1 2
K26 PERP3 DMI2RXP AB25 DMI_MTX_IRX_P2 10
C483 2 1 0.1UF/10V MLCC/+/-10% PCIE_TXN4_C J29 AA29
35 PCIE_TX4- PETN3 DMI2TXN DMI_MRX_ITX_N2 10
J28 PETP3 DMI2TXP AA28 DMI_MRX_ITX_P2 10
D C485 2 1 0.1UF/10V MLCC/+/-10% PCIE_TXP4_C D
35 PCIE_TX4+
35 PCIE_RX4- H27 PERN4 DMI3RXN AD27 DMI_MTX_IRX_N3 10
35 PCIE_RX4+ H26 PERP4 DMI3RXP AD26 DMI_MTX_IRX_P3 10
C494 2 1 0.1UF/10V MLCC/+/-10% GLAN_TXN_C PCIE_TXN4_C G29 AC29
47 PCIE_TX6-/GLAN_TX- PCIE_TXP4_C PETN4 DMI3TXN DMI_MRX_ITX_N3 10
ExpressCard G28 PETP4 DMI3TXP AC28 DMI_MRX_ITX_P3 10
C496 2 1 0.1UF/10V MLCC/+/-10% GLAN_TXP_C
47 PCIE_TX6+/GLAN_TX+
F27 PERN5 DMI_CLKN T26 CLK_PCIE_ICH# 21
F26 PERP5 DMI_CLKP T25 CLK_PCIE_ICH 21
E29 PETN5
E28 PETP5 DMI_ZCOMP Y23
Y24 DMI_COMP 2 1 Place within 500 mils of ICH8
DMI_IRCOMP +1.5V_PCIE_ICH
D27 R221 24.9Ohm 1%
47 PCIE_RX6-/GLAN_RX- PERN6/GLAN_RXN
47 PCIE_RX6+/GLAN_RX+ D26 PERP6/GLAN_RXP USBP0N G3 ICH_USBP0- 39
GLAN_TXN_C C29 G2 USER1 Left side pair top/left
GLAN_TXP_C PETN6/GLAN_TXN USBP0P ICH_USBP0+ 39
C28 PETP6/GLAN_TXP USBP1N H5
H4
ICH_USBP1- 39
USER2 Left side pair bottom/right
PCI Pullups
ICH_EC_SPI_CLK_R USBP1P ICH_USBP1+ 39
R275 1 2 15Ohm 5% C23 H2
37 ICH_EC_SPI_CLK ICH_SPI_CS# SPI_CLK USBP2N ICH_USBP2- 50 PCI_STOP#
Layout Note: B23 H1 USER3 Right side pair top/left R276 1 2 8.2KOhm 5%
ICH_SPI_CS1#_R SPI_CS0# USBP2P ICH_USBP2+ 50 +3.3V_RUN
T55 1 E22 J3
SPI
Place 15 ohm within SPI_CS1# USBP3N ICH_USBP3- 50
USBP3P J2 ICH_USBP3+ 50 USER3 Right side pair bottom/right
500 mils from ICH. R267 1 2 15Ohm 5% ICH_EC_SPI_DO_R D23 K5 ICH_USBP4- 1 T60 PCIE_MCARD2_DET# R548 1 2 100KOhm 5%
37 ICH_EC_SPI_DO SPI_MOSI USBP4N ICH_USBP4+ +3.3V_RUN
F21 K4 1 T56 RP4E 10 No.14
37 ICH_EC_SPI_DIN SPI_MISO USBP4P +3.3V_RUN
K2 PCI_DEVSEL# 6 5
USB_OC0_1# USBP5N ICH_USBP5- 28
AJ19 K1 CCD 8.2KOhm 5%
39 USB_OC0_1# OC0# USBP5P ICH_USBP5+ 28
AG16 OC1#/GPIO40 USBP6N L3 ICH_USBP6- 35
RP4F 10 10 RP4D
+3.3V_ALW USB_OC2_3# Express Card PCI_FRAME# PCI_REQ1#
50 USB_OC2_3# AG15
AE15
OC2#/GPIO41 USB USBP6P L2
M5
ICH_USBP6+ 35
8.2KOhm
7
5%
5 5 4
8.2KOhm 5%
OC4# OC3#/GPIO42 USBP7N ICH_USBP7- 41
AF15 OC4#/GPIO43 USBP7P M4 ICH_USBP7+ 41 BlueTooth RP4G 10 10 RP4C
OC5# AG17 M2 ICH_USBP8- 1 T48 No.5 ICH_GPIO2_PIRQE# 8 5 5 3 PCI_PIRQD#
U36 OC6# OC5#/GPIO29 USBP8N ICH_USBP8+ T49 8.2KOhm 5% 8.2KOhm 5%
AD12 OC6#/GPIO30 USBP8P M1 1
5
VCC
R518 15Ohm 5% OC7# AJ18 N3 RP4H 10 10 RP4B
ICH_SPI_CS#_R OC7#/GPIO31 USBP9N ICH_USBP9- 50
40 SPI_CS0# 1 2 4 A 2 1 2 ICH_SPI_CS# OC8# AD14 OC8# USBP9P N2 ICH_USBP9+ 50 WWAN PCI_SERR# 9 5 5 2
OC9#
C
Y C
1 AH18 8.2KOhm 5% 8.2KOhm 5%
B SIO_SPI_CS# 37 OC9#
R517 15Ohm5% /*
USBRBIAS# F2 10 RP4A
GND
F3 USBRBIAS 5 1 PCI_TRDY#
74AHC1G08GW USBRBIAS 8.2KOhm 5%
3
/* ICH8-M
1
R492 RP3E 10 +3.3V_RUN
1 2 22.6Ohm 6 5
Short F2 and F3 at the package 8.2KOhm 5%
R521 0Ohm 5% 1% RP3F
and keep length to less than pt_r0603 10 10 RP3D
PCI_REQ0# PCI_PIRQC#
2
7 5 5 4
500mils. Trace Impedance 8.2KOhm 5% 8.2KOhm 5%
should be 60ohms +/- 15%. RP3G 10 10 RP3C
PCI_PLOCK# 8 5 5 3 PCI_PIRQB#
Non-iAMT +3.3V_SUS 8.2KOhm 5% 8.2KOhm 5%
RP1E 10 RP3H 10 10 RP3B
USB_OC0_1# 6 5 PCI_PERR# 9 5 5 2 PCI_PIRQA#
10KOhm 5% ICH_SPI_CS1#_R 8.2KOhm 5% 8.2KOhm 5%
RP1D
RP1F 10 10 Boot BIOS Strap 10 RP3A
OC9# 7 5 5 4 OC5# PCI_GNT0# 5 1 PCI_IRDY#
10KOhm 5% 10KOhm 5% GNT0# SPI_CS1# 8.2KOhm 5%
RP1G RP1C
10 10
2
OC6# 8 5 5 3 OC8# LPC 11 No stuff No stuff
10KOhm 5% 10KOhm 5% R272 R260
RP1H RP1B 1KOhm 1KOhm Add Buffers as needed for
OC7# 9
10 10
5 5 2 USB_OC2_3# 5% 5% PCI 10 No stuff Stuff Non-iAMT
10KOhm 5% 10KOhm 5% /*
Loading and fanout
RP1A concerns.
1
10
5 1 OC4# SPI 01 Stuff No stuff
10KOhm 5% +3.3V_SUS
C279 0.047UF/10V
2 1
B U32B B
32 PCI_AD[0..31] PCI_AD0 PCI_REQ0# PCI_GNT3# MLCC/+/-10%
D20 AD0 REQ0# A4 PCI_REQ0#
PCI_AD1 PCI_GNT0#
E19 AD1 PCI GNT0# D7 PCI_GNT0#
2
PCI_AD2 D19 E18 PCI_REQ1# U14
PCI_AD3 AD2 REQ1#/GPIO50 PCI_GNT1# PCI_REQ1# 32
A20 C18 R266 1 5
PCI_AD4 AD3 GNT1#/GPIO51 SB_WWAN_PCIE_RST# PCI_GNT1# 32 PCI_RST#_G A VCC
D17 B19 1KOhm 5% 2
PCI_AD5 AD4 REQ2#/GPIO52 PCI_GNT2# SB_WWAN_PCIE_RST# 50 B
A21 F18 1 T72 /* 3 4
PCI_AD6 AD5 GNT2#/GPIO53 SB_LOM_PCIE_RST# GND Y PCI_RST# 32
A19 AD6 REQ3#/GPIO54 A11 SB_LOM_PCIE_RST# 47
PCI_AD7 PCI_GNT3# T78 SN74AHC1G32DBVR
1
C19 AD7 GNT3#/GPIO55 C10 1
PCI_AD8 A18 No.37
PCI_AD9 AD8
B16 AD9 C/BE0# C17 PCI_C_BE0# 32
PCI_AD10 A12 E15 A16 away override strap.
PCI_AD11 AD10 C/BE1# PCI_C_BE1# 32 +3.3V_SUS
E16 AD11 C/BE2# F16 PCI_C_BE2# 32
PCI_AD12 A14 E17
PCI_AD13 AD12 C/BE3# PCI_C_BE3# 32
G16 PCI_GNT3# Low = A16 swap override enabled. C199 0.047UF/10V
PCI_AD14 AD13 PCI_IRDY#
A15 AD14 IRDY# C8 PCI_IRDY# 32 High = Default. 2 1
PCI_AD15 B6 D9
PCI_AD16 AD15 PAR PCI_RST#_G PCI_PAR 32
C11 G6 MLCC/+/-10%
PCI_AD17 AD16 PCIRST# PCI_DEVSEL#
A9 AD17 DEVSEL# D16 PCI_DEVSEL# 32
PCI_AD18 D11 A7 PCI_PERR# U12
PCI_AD19 AD18 PERR# PCI_PLOCK# PCI_PERR# 32 CLK_PCI_ICH
B12 AD19 PLOCK# B7 1 A VCC 5
PCI_AD20 C12 F10 PCI_SERR# PCI_PLTRST# 2
AD20 SERR# PCI_SERR# 32 B
2
PCI_AD21 D10 C16 PCI_STOP# 3 4
PCI_AD22 AD21 STOP# PCI_TRDY# PCI_STOP# 32 GND Y PLTRST# 10,35,37
C7 C9 R281
PCI_AD23 AD22 TRDY# PCI_FRAME# PCI_TRDY# 32
F13 A17 R5C833 REQ1 GNT1 PIRQC 10Ohm SN74AHC1G32DBVR
PCI_AD24 AD23 FRAME# PCI_FRAME# 32 +3.3V_SUS
E11 5%
PCI_AD25 E13
AD24
AG24 PCI_PLTRST# PIRQD /*
PCI_AD26 AD25 PLTRST# CLK_PCI_ICH C542 0.047UF/10V
1
E12 AD26 PCICLK B10 CLK_PCI_ICH 21
PCI_AD27 D8 G7 2 1
PCI_AD28 AD27 PME# ICH_PME# 38
A6 AD28
PCI_AD29 E8 MLCC/+/-10%
AD29
1
PCI_AD30 D6 U40
A PCI_AD31 AD30 C284 A
A3 AD31 1 A VCC 5
8.2PF/50V PCI_PLTRST# 2 B
2
T79 1 PCI_PIRQA# F9
Interrupt I/F F8 ICH_GPIO2_PIRQE#
MLCC/+/-0.25PF
/*
3 GND Y 4 PLTRST_LAN_MINICARD# 47,50
PCI_PIRQB# PIRQA# PIRQE#/GPIO2 SB_WLAN_PCIE_RST# SN74AHC1G32DBVR
PCI_PIRQB# B5 PIRQB# PIRQF#/GPIO3 G11 SB_WLAN_PCIE_RST# 50
1
PCI_PIRQC# C5 F12 SB_NB_PCIE_RST# C553 No.54
32 PCI_PIRQC# PCI_PIRQD# PIRQC# PIRQG#/GPIO4 PCIE_MCARD2_DET# SB_NB_PCIE_RST# 10
32 PCI_PIRQD# A10 B3 PCIE_MCARD2_DET# 50
Reserved for EMI. 47PF/50V
PIRQD# PIRQH#/GPIO5 MLCC/+/-5%
ICH8-M
Place resister and cap /*
No.14
2
close to ICH.
PROJECT: Lanai 1.2 SHEET 16 OF 68 ICH8: PCI/INT/DMI/USB RELEASE DATE :
5 4 3 2 1
5 4 3 2 1
Place these close to ICH8

+3.3V_SUS
Non-iAMT CLK_ICH_48M
1
R191 1 2 10KOhm 5% /* RSV_ICH_CL_RST1# No.26
+3.3V_SUS R216 10KOhm 5% AMT_SMBCLK +3.3V_RUN R261
Non-iAMT 1 2
AMT_SMBDAT
R217 1 2 10KOhm 5% 10Ohm
R224 1 2 10KOhm 5% ICH_RI#
2
RN37A 1 2.2KOhm 2 5% ICH_SMBDATA R215 1 2 10KOhm 5% LOM_ICH_SMBALERT# 5%
RN37B 3 2.2KOhm 4 5% ICH_SMBCLK R214 1KOhm 5% ICH_PCIE_WAKE# R422
12
1 2
8.2KOhm C270
5% 4.7PF/50V
U32C
ICH_SMBCLK MLCC/+/-0.25PF
2
35,50 ICH_SMBCLK AJ26 SMBCLK SATA0GP/GPIO21 AJ12
D ICH_SMBDATA AD19 AJ10 D
35,50 ICH_SMBDATA RSV_ICH_CL_RST1# SMBDATA SATA1GP/GPIO19 CLK_ICH_14M
T35
SATA
GPIO
1 AG21 AF11
SMB
AMT_SMBCLK LINKALERT# SATA2GP/GPIO36
AC17 SMLINK0 SATA3GP/GPIO37 AG11
1
AMT_SMBDAT AE19 SMLINK1 CLK_ICH_14M R204
CLK14 AG9 CLK_ICH_14M 21
ICH_RI# CLK_ICH_48M 10Ohm
Clocks
AF17 RI# CLK48 G5 CLK_ICH_48M 21
/*
T69 1 F4 D3 ICH_SUSCLK 1 T76 5%
SUS_STAT#/LPCPD# SUSCLK
12
7,38,52 XDP_DBRESET# AD15 SYS_RESET#
+3.3V_RUN AG23 C212
SLP_S3# SIO_SLP_S4# SIO_SLP_S3# 37
AG12 AF21 1 T36 4.7PF/50V
10 PM_BMBUSY# BMBUSY#/GPIO0 SLP_S4#
AD18 /*
LOM_ICH_SMBALERT# AG22 SLP_S5# SIO_SLP_S5# 37
MLCC/+/-0.25PF
2
37 LOM_SMB_ALERT# 1 2 SMBALERT#/GPIO11
2
R173 0Ohm 5% /* AH27 SIO_S4_STATE# 1 T124
GPIO
R185 S4_STATE#/GPIO26
AE20
SYS
21 H_STP_PCI# STP_PCI#/GPIO15 ICH_PWRGD
8.2KOhm AG18 AE23
21 H_STP_CPU# STP_CPU#/GPIO25 PWROK ICH_PWRGD 10,51 ICH_PWRGD
5% R200 1 2 10KOhm 5%
CLKRUN# AH11 AJ14 DPRSLPVR
Power MGT
CLKRUN# 32,37 CLKRUN# CLKRUN#/GPIO32 DPRSLPVR/GPIO16 DPRSLPVR 10,53 DPRSLPVR R420 1 2 100KOhm 5%
1
ICH_PCIE_WAKE# AE17 AE21 ICH_BATLOW# 1 2

38 ICH_PCIE_WAKE# WAKE# BATLOW# +3.3V_SUS
2
IRQ_SERIRQ AF12 R228 8.2KOhm 5% WOL_EN R193 1 2 100KOhm 5%

32,37 IRQ_SERIRQ RSV_THRM# SERIRQ
R184 1 AC13 C2
THRM# PWRBTN# SIO_PWRBTN# 37 SUSPWROK
10Ohm T46 R176 1 2 10KOhm 5% /*
5% IMVP_PWRGD AJ20 AH20 ICH_LAN_RST#
37,51,53 IMVP_PWRGD VRMPWRGD LAN_RST# ICH_LAN_RST#
/* 1 2 R174 1 2 1MOhm 5%
ICH_RSMRST# 37
T33 R189 1 2 0Ohm 5%
1
1 AJ22 TP7 RSMRST# AG27 SUSPWROK 43,51

R188 0Ohm 5% /* ICH_CL_PWROK R262 1 2 1MOhm 5%
USB_IDE# AJ8 E1
RSVD_GPIO6 TACH1/GPIO1 CK_PWRGD CLK_PWRGD 21
T120 1
SIO_EXT_WAKE#
AJ9
AH9
TACH2/GPIO6
E3 ICH_CL_PWROK Non-iAMT
38 SIO_EXT_WAKE# SIO_EXT_SMI# TACH3/GPIO7 CLPWROK ICH_CL_PWROK 10,37
Option to "Disable " 37 SIO_EXT_SMI# AE16 GPIO8
SIO_EXT_SCI# AC19 AJ25 RSV_SIO_SLP_M# 1 T123
C clkrun. Pulling it down 37 SIO_EXT_SCI# PCIE_MCARD1_DET# AG8 GPIO12 SLP_M# C
50 PCIE_MCARD1_DET# TACH0/GPIO17
will keep the clks No.15 50 USB_MCARD1_DET# R543 1 2 4.7KOhm AH12 F23
GPIO18 CL_CLK0 CL_CLK0 10
Controller Link
No.14 1 T134 RSVD_GPIO20 AE11 AE18 RSV_ICH_CL_CLK1 1 T39
GPIO
running. USB_MCARD2_DET# AG10 GPIO20 CL_CLK1 +3.3V_SUS
50 USB_MCARD2_DET# USB_MCARD3_DET# AH25 SCLOCK/GPIO22
1 T31 QRT_STATE0/GPIO27 CL_DATA0 F22 CL_DATA0 10
AD16 AF19 RSV_ICH_CL_DATA1 1 T38
31 IDE_RST_MOD QRT_STATE1/GPIO28 CL_DATA1 EC_ME_ALERT R237
AG13 1 2 8.2KOhm 5%
21 SATA_CLKREQ# PLTRST_DELAY# SATACLKREQ#/GPIO35 CL_VREF0
PLTRST_DELAY# AF9 SLOAD/GPIO38 CL_VREF0 D24
1 T117 RSVD_GPIO39 AJ11 AH23 CL_VREF1 1 T32
CCD_VDD_ON SDATAOUT0/GPIO39 CL_VREF1
No.9 28 CCD_VDD_ON AD10 SDATAOUT1/GPIO48
CL_RST# AJ23 ICH_CL_RST0# 10
SPKR AD9
44 SPKR SPKR PCIE_MCARD3_DET# 1
AJ27 T30
MISC
USB_IDE# R419 1 MCH_ICH_SYNC#_R CLGPIO0/GPIO24
2 8.2KOhm 5% +3.3V_RUN 10 MCH_ICH_SYNC# 1 2 AJ13 MCH_SYNC# CLGPIO1/GPIO10 AJ24 ME_EC_ALERT 1 T119
R169 0Ohm 5% AF22 EC_ME_ALERT 1 T45
SIO_EXT_SCI# R227 1 CLGPIO2/GPIO14 WOL_EN
2 10KOhm 5% +3.3V_SUS 15 ICH_RSVD AJ21 TP3 WOL_EN/GPIO9 AG19
ICH8-M
Pull up for each detect line

Non-iAMT
+3.3V_RUN +3.3V_RUN +3.3V_RUN
RP2E 10
6 5
100KOhm 5%
SMBus address D2 RP2F 10 10 RP2D
2
7 5 5 4 USB_MCARD1_DET#
2
4
B R212 100KOhm 5% 100KOhm 5% B
1KOhm 5% These are for RP2G 10 10 RP2C
/* RN36A RN36B USB_MCARD3_DET# 8 5 5 3 PCIE_MCARD3_DET#
backdrive issue 2.2KOhm 2.2KOhm 100KOhm 5% 100KOhm 5%
5% 5% RP2H 10 10 RP2B
1
+3.3V_RUN SPKR USB_MCARD2_DET# 9 5 5 2

No.14 100KOhm 5% 100KOhm 5%
1
3
1
10 RP2A
G
R555 1 2 100KOhm 5% RSVD_GPIO20 5 1 PCIE_MCARD1_DET#
S 2
35,50 ICH_SMBDATA MEM_SDATA 19
100KOhm 5%
D
R235 1 2 10KOhm 5% RSV_THRM#
R168 1 2 10KOhm 5% /* MCH_ICH_SYNC#_R No Reboot strap. Q36 2N7002
R206 1 2 10KOhm 5% IRQ_SERIRQ Id=180mA/Pd=300mW
R424 1 2 10KOhm 5% RSVD_GPIO6 SPKR Low=Default
R423 1 2 10KOhm 5% RSVD_GPIO39
High=No Reboot
+3.3V_RUN
R195 1 2 10KOhm 5% PLTRST_DELAY#
R544 1 2 100KOhm 5% CCD_VDD_ON

Non-iAMT
No.9
1
+3.3V_RUN +3.3V_SUS
G
3
S 2
35,50 ICH_SMBCLK MEM_SCLK 19

D
1
Q35 2N7002 R277 R180
Id=180mA/Pd=300mW 3.24KOhm 3.24KOhm
1% 1%
/*
+3.3V_SUS CL_VREF0 CL_VREF1
2
1
1
A A
1
C278 R278 C201 R179
R226 1 2 10KOhm 5% SIO_EXT_SMI# 0.1UF/10V 453Ohm 0.1UF/10V 453Ohm
MLCC/+80-20% 1% MLCC/+80-20% 1%
/* /*
2
2
2
PROJECT: Lanai 1.2 SHEET 17 OF 68 ICH8: SMB/PWR/CLK/GPIO RELEASE DATE :
5 4 3 2 1
5 4 3 2 1
+RTC_CELL
1
C224 C218 C219
1UF/10V 0.1UF/10V 0.1UF/10V
MLCC/+/-10% MLCC/+/-10% MLCC/+/-10%
pt_c0603
2
+1.05V_VCCP +1.5V_RUN U32E
A23 VSS[001] VSS[099] K7
R284 100Ohm 5% U32F D13 A5 L1
VSS[002] VSS[100]
+5V_RUN 1 2 AD25 VCC1_05[01] A13 +1.05V_VCCP 1 AA2 L13
VCCRTC VSS[003] VSS[101]
VCC1_05[02] B13 3 1 2 AA7 VSS[004] VSS[102] L15
D15 A16 C13 2 R252 10Ohm 5% A25 L26
V5REF[1] VCC1_05[03] VSS[005] VSS[103]
1
1 2 +ICH_V5REF_RUN T7 C14 C253 C277 pt_r0805_h24 AB1 L27
+3.3V_RUN V5REF[2] VCC1_05[04] VSS[006] VSS[104]
D14 0.1UF/10V 0.1UF/10V BAT54C AB24 L4
D RB751V_40 VCC1_05[05] MLCC/+/-10% MLCC/+/-10% VSS[007] VSS[105] D
G4 V5REF_SUS VCC1_05[06] E14 AC11 VSS[008] VSS[106] L5
1
C285
2
VCC1_05[07] F14 AC14 M12
0.1UF/10V VSS[009] VSS[107]
AA25 VCC1_5_B[01] VCC1_05[08] G14 AC25 VSS[010] VSS[108] M13
MLCC/+/-10% AA26 L11 AC26 M14
VCC1_5_B[02] VCC1_05[09] VSS[011] VSS[109]
2
AA27 VCC1_5_B[03] VCC1_05[10] L12 AC27 M15
VSS[012] VSS[110]
Non-iAMT AB27 VCC1_5_B[04] VCC1_05[11] L14 AD17 VSS[013] VSS[111] M16
+5V_SUS 1 2 AB28 VCC1_5_B[05] VCC1_05[12] L16 AD20 VSS[014] VSS[112] M17
R255 10Ohm5% AB29 L17 AD28 M23
VCC1_5_B[06] VCC1_05[13] L39 0.1Ohm/100Mhz +1.5V_RUN VSS[015] VSS[113]
D28 VCC1_5_B[07] VCC1_05[14] L18 AD29 VSS[016] VSS[114] M28
D14 D29 M11 pt_inductor_2p_126x98_tdk AD3 M29
VCC1_5_B[08] VCC1_05[15] VSS[017]
CORE
+ICH_V5REF_SUS VSS[115]
+3.3V_SUS 1 2 E25 VCC1_5_B[09] M18 +1.5V_DMIPLL 2 1 +1.5V_DMIPLL_R 1 2 AD4 M3
VCC1_05[16] R497 1Ohm 5% VSS[018] VSS[116]
E26 VCC1_5_B[10] VCC1_05[17] P11 AD6 VSS[019] VSS[117] N1
1
RB751V_40 E27 P18 C250 C249 pt_r0603 AE1 N11
VCC1_5_B[11] VCC1_05[18] VSS[020] VSS[118]
1
C261 F24 T11 0.01UF/25V 10UF/6.3V AE12 N12
0.1UF/10V VCC1_5_B[12] VCC1_05[19] MLCC/+/-10% MLCC/+/-20% VSS[021] VSS[119]
F25 VCC1_5_B[13] VCC1_05[20] T18 AE2 VSS[022] VSS[120] N13
MLCC/+/-10% pt_c0805_h53
2
G24 VCC1_5_B[14] VCC1_05[21] U11 AE22 VSS[023] VSS[121] N14
2
H23 VCC1_5_B[15] U18 AD1 N15
VCC1_05[22] VSS[024] VSS[122]
H24 VCC1_5_B[16] VCC1_05[23] V11 AE25 VSS[025] VSS[123] N16
J23 VCC1_5_B[17] VCC1_05[24] V12 AE5 VSS[026] VSS[124] N17
J24 VCC1_5_B[18] V14 AE6 N18
VCC1_05[25] VSS[027] VSS[125]
K24 VCC1_5_B[19] VCC1_05[26] V16 AE9 VSS[028] VSS[126] N26
K25 VCC1_5_B[20] VCC1_05[27] V17 +1.25V_RUN AF14 VSS[029] VSS[127] N27
L23 VCC1_5_B[21] VCC1_05[28] V18 AF16 VSS[030] VSS[128] N4
1
L24 C209 C220 AF18 N5
VCC1_5_B[22] VSS[031] VSS[129]
VCCA3GP
L25 R29 0.1UF/10V 22UF/10V AF3 N6
+1.5V_RUN VCC1_5_B[23] VCCDMIPLL MLCC/+/-10% MLCC/+/-20% VSS[032] VSS[130]
M24 VCC1_5_B[24] AF4 VSS[033] VSS[131] P12
FB_330ohm+-25%_100mHz_ +VCC_DMI Intel 20% pt_c1206_h75
2
M25 VCC1_5_B[25] VCC_DMI[1] AE28 AG5 VSS[034] VSS[132] P13
1.5A_0.09_ohm DC N23 VCC1_5_B[26] VCC_DMI[2] AE29 AG6 VSS[035] VSS[133] P14
1
L17
TAN/Lf_T=2000hrs_105C/+/-20%
N24 VCC1_5_B[27] AH10 VSS[036] VSS[134] P15

330Ohm/100Mhz N25 AC23 +V_CPU_IO AH13 P16
+1.5V_PCIE_ICH VCC1_5_B[28] V_CPU_IO[1] +1.05V_VCCP VSS[037] VSS[135]
MURATA/BLM21PG331SN1D P24 AC24 AH16 P17
VCC1_5_B[29] V_CPU_IO[2] VSS[038] VSS[136]
1
pt_l0805_h41 P25 C228 C227 C515 AH19 P23
C VCC1_5_B[30] 0.1UF/10V 0.1UF/10V 4.7UF/10V VSS[039] VSS[137] C
1 2
R24 VCC1_5_B[31] VCC3_3[01] AF29 +3.3V_RUN AH2 VSS[040] VSS[138] P28

R25 MLCC/+/-10% MLCC/+/-10% MLCC/+/-10% AF28 P29
VCC1_5_B[32] VSS[041] VSS[139]
1
1
+ CE21 C517 C234 C264 C210 pt_c1206_h71
2
R26 VCC1_5_B[33] VCC3_3[02] AD2 AH22 VSS[042] VSS[140] R11
220UF/4V 22UF/10V 22UF/10V 2.2UF/10V R27 0.1UF/10V AH24 R12
VCC1_5_B[34] VSS[043] VSS[141]
1
pt_c7343d_h79 MLCC/+/-20% MLCC/+/-20% MLCC/+/-10% T23 AC8 C232 MLCC/+/-10% AH26 R13
pt_c1206_h75 pt_c1206_h75 pt_c0805_h53 VCC1_5_B[35] VCC3_3[03] 0.1UF/10V VSS[044] VSS[142]
2
2
T24 VCC1_5_B[36] VCC3_3[04] AD8 AH3 VSS[045] VSS[143] R14
VCCP_CORE
MLCC/+/-10%
2
T27 VCC1_5_B[37] VCC3_3[05] AE8 AH4 VSS[046] VSS[144] R15
2
T28 VCC1_5_B[38] VCC3_3[06] AF8 AH8 VSS[047] VSS[145] R16
T29 VCC1_5_B[39] AJ5 VSS[048] VSS[146] R17
U24 VCC1_5_B[40] VCC3_3[07] AA3 B11 VSS[049] VSS[147] R18
U25 VCC1_5_B[41] VCC3_3[08] U7 B14 VSS[050] VSS[148] R28
1
V23 V7 C269 B17 R4
VCC1_5_B[42] VCC3_3[09] 0.1UF/10V VSS[051] VSS[149]
V24 VCC1_5_B[43] VCC3_3[10] W1 B2 VSS[052] VSS[150] T12
+1.5V_RUN V25 W6 MLCC/+/-10% B20 T13
VCC1_5_B[44] VCC3_3[11] VSS[053] VSS[151]
IDE
2
W25 VCC1_5_B[45] VCC3_3[12] W7 B22 VSS[054] VSS[152] T14
Y25 VCC1_5_B[46] VCC3_3[13] Y7 B8 VSS[055] VSS[153] T15
1
C24 VSS[056] VSS[154] T16

R414 +VCCSATPLL AJ6 A8 C26 T17
0Ohm 5% VCCSATAPLL VCC3_3[14] VSS[057] VSS[155]
VCC3_3[15] B15 C27 VSS[058] VSS[156] T2
1
AE7 B18 C280 C274 C236 C6 U12
+1.5V_RUN VCC1_5_A[01] VCC3_3[16] VSS[059] VSS[157]
AF7 B4 0.1UF/10V 0.1UF/10V 0.1UF/10V D12 U13
VCC1_5_A[02] VCC3_3[17] VSS[060] VSS[158]
1
ARX
+VCCSATPLL_L C252 MLCC/+/-10% MLCC/+/-10% MLCC/+/-10%
12
AG7 VCC1_5_A[03] VCC3_3[18] B9 D15 VSS[061] VSS[159] U14

0.1UF/10V +3.3V_RUN
2
AH7 VCC1_5_A[04] VCC3_3[19] C15 D18 VSS[062] VSS[160] U15
L34 MLCC/+/-10% AJ7 D13 D2 U16
VCC1_5_A[05] VCC3_3[20] VSS[063] VSS[161]
PCI
2
10uH VCC3_3[21] D5 D4 VSS[064] VSS[162] U17
2
Irat=100mA AC1 E10 Non-iAMT E21 U23
pt_l0805 VCC1_5_A[06] VCC3_3[22] R218 VSS[065] VSS[163]
AC2 VCC1_5_A[07] VCC3_3[23] E7 E24 VSS[066] VSS[164] U26
+3.3V_SUS
ATX
AC3 VCC1_5_A[08] VCC3_3[24] F11 0Ohm E4 VSS[067] VSS[165] U27
AC4 VCC1_5_A[09] 5% E9 U3
VSS[068] VSS[166]
2
+1.5V_RUN AC5 VCC1_5_A[10] VCCHDA AC12 VCCHDA F15 VSS[069] VSS[167] U5

+VCCSATPLL
1
E23 VSS[070] VSS[168] V13
1
C229 AC10 AD11 F28 V15

VCC1_5_A[11] VCCSUSHDA VSS[071] VSS[169]
1
B C426 C420 0.1UF/10V B

AC9 VCC1_5_A[12] F29 VSS[072] VSS[170] V28
1
1UF/10V 10UF/6.3V MLCC/+/-10% J6 +TP_VCCSUS1.05_1 1 T54 C213 C225 F7 V29
MLCC/+/-10% MLCC/+/-20% VCCSUS1_05[1] +TP_VCCSUS1.05_2 T37 0.1UF/10V 0.1UF/10V VSS[073] VSS[171]
2
AA5 VCC1_5_A[13] VCCSUS1_05[2] AF20 1 G1 VSS[074] W2

pt_c0603 pt_c0805_h53 MLCC/+/-10% MLCC/+/-10% VSS[172]
2
AA6 VCC1_5_A[14] E2 VSS[075] VSS[173] W26

+TP_VCCSUS1.5_1 T44
2
VCCSUS1_5[1] AC16 1 G10 VSS[076] W27
VSS[174]
G12 VCC1_5_A[15] G13 VSS[077] VSS[175] Y28
+TP_VCCSUS1.5_2 T64 +3.3V_SUS
G17 VCC1_5_A[16] VCCSUS1_5[2] J7 1 Non-iAMT G19 VSS[078] VSS[176] Y29
H7 VCC1_5_A[17] G23 VSS[079] VSS[177] Y4
C3 +VCCSUS3_3[0~6] G25 AB4
VCCSUS3_3[01] VSS[080] VSS[178]
AC7 VCC1_5_A[18] G26 VSS[081] VSS[179] AB23
1
+1.5V_RUN AD7 AC18 G27 AB5
VCC1_5_A[19] VCCSUS3_3[02] C246 C242 VSS[082] VSS[180]
VCCSUS3_3[03] AC21 H25 AB6
0.022UF/16V 0.022UF/16V VSS[083] VSS[181]
D1 VCCUSBPLL VCCSUS3_3[04] AC22 H28 VSS[084] AD5
VSS[182]
VCCPSUS
MLCC/+/-10% MLCC/+/-10%
2
VCCSUS3_3[05] AG20 H29 VSS[085] VSS[183] U4
1
C272 F1 AH28 H3 W24

+1.5V_RUN VCC1_5_A[20] VCCSUS3_3[06] VSS[086] VSS[184]
USB CORE
0.1UF/10V L6 H6
VCC1_5_A[21] VSS[087]
1
MLCC/+/-10% C217 L7 P6 J1 A1
0.1UF/10V VCC1_5_A[22] VCCSUS3_3[07] VSS[088] VSS_NCTF[01]
2
M6 VCC1_5_A[23] VCCSUS3_3[08] P7 J25 A2

MLCC/+/-10% VSS[089] VSS_NCTF[02]
M7 VCC1_5_A[24] VCCSUS3_3[09] C1 J26 VSS[090] VSS_NCTF[03] A28
+VCCSUS3_3[7~19]
2
VCCSUS3_3[10] N7 J27 VSS[091] VSS_NCTF[04] A29

W23 VCC1_5_A[25] VCCSUS3_3[11] P1 J4 AH1
1
C241 VSS[092] VSS_NCTF[05]
VCCSUS3_3[12] P2 J5 VSS[093] VSS_NCTF[06] AH29
T57 1 TP_VCCSUSLAN1 F17 VCCLAN1_05[1] VCCSUS3_3[13] P3 0.1UF/10V K23 VSS[094] AJ1
VSS_NCTF[07]
VCCPUSB
T61 1 TP_VCCSUSLAN2 G18 VCCLAN1_05[2] P4 MLCC/+/-10% K28 AJ2

VCCSUS3_3[14] VSS[095] VSS_NCTF[08]
2
+3.3V_RUN VCCSUS3_3[15] P5 K29 VSS[096] VSS_NCTF[09] AJ28
Non-iAMT F19 VCCLAN3_3[1] VCCSUS3_3[16] R1 K3 VSS[097] AJ29
1
C265 VSS_NCTF[10]
Place CAP
Non-iAMT G20 VCCLAN3_3[2] VCCSUS3_3[17] R3 K6
VSS[098] VSS_NCTF[11]
B1
0.1UF/10V R5 B29
MLCC/+/-10% +VCCGLANPLL VCCSUS3_3[18] VSS_NCTF[12]
close to A24 A24 VCCGLANPLL VCCSUS3_3[19] R6
ICH8-M
2
+1.5V_RUN
GLAN POWER
A26 G22 TP_VCCCL1.05 1 T66

VCCGLAN1_5[1] VCCCL1_05
A27 VCCGLAN1_5[2]
A +VCCGLANPLL B26 A22 VCCCL1_5 A
+1.5V_PCIE_ICH VCCGLAN1_5[3] VCCCL1_5
B27 VCCGLAN1_5[4]
1
1
C214 C281 B28 F20 C282 C283
1UF/10V 4.7UF/6.3V VCCGLAN1_5[5] VCCCL3_3[1] 0.1UF/10V 1UF/10V
VCCCL3_3[2] G21 +3.3V_RUN
MLCC/+/-10% MLCC/+/-10% B25 MLCC/+/-10% MLCC/+/-10%
+3.3V_RUN VCCGLAN3_3
pt_c0603 pt_c0603 /* pt_c0603
2
2
Non-iAMT
ICH8-M /*
PROJECT: Lanai 1.2 SHEET 18 OF 68 ICH8-M(POWER,GND) RELEASE DATE :
5 4 3 2 1
5 4 3 2 1
+1.8V_SUS +1.8V_SUS +1.8V_SUS +1.8V_SUS

A is required to route to Top DDR_A_DM[0..7] 11 DDR_B_DM[0..7] 11
DDR_A_D[0..63] 11 DDR_B_D[0..63] 11
S0DIMM for AMT to function DDR_A_DQS[0..7] 11 DDR_B_DQS[0..7] 11
V_DDR_MCH_REF
Ch.A SODIMM needs to be
populated for Intel AMT support.
TOP DDR_A_DQS#[0..7] 11
DDR_A_MA[0..14] 10,11,20
V_DDR_MCH_REF BOT DDR_B_DQS#[0..7] 11
DDR_B_MA[0..14] 10,11,20
V_DDR_MCH_REF
CON14 CON15
1 2 1 2 V_DDR_MCH_REF
VREF VSS46 DDR_A_D13 VREF VSS46 DDR_B_D5
3 VSS47 4 3 VSS47 4
DDR_A_D12 DQ4 DDR_A_D14 DDR_B_D0 DQ4 DDR_B_D4
5 DQ0 6 5 DQ0 6
DDR_A_D8 DQ5 DDR_B_D1 DQ5
7 8 7 8
DQ1 VSS15 DQ1 VSS15
1
MLCC/+80-20%
MLCC/+/-10%
9 10 DDR_A_DM1 9 10 DDR_B_DM0
VSS37 DM0 VSS37 DM0
1
MLCC/+80-20%
MLCC/+/-10%
D DDR_A_DQS#1 11 12 DDR_B_DQS#0 11 12 D
DDR_A_DQS1 DQS#0 VSS5 DDR_A_D11 C102 C99 DDR_B_DQS0 DQS#0 VSS5 DDR_B_D6
13 14 13 14
DQS0 DQ6 DDR_A_D10 DQS0 DQ6 DDR_B_D7 C101 C97
2
15 VSS48 16 15 VSS48 16
DDR_A_D15 DQ7 0.1UF/10V 2.2UF/6.3V DDR_B_D3 DQ7
2
17 DQ2 18 17 DQ2 18
DDR_A_D9 VSS16 DDR_A_D3 DDR_B_D2 VSS16 DDR_B_D8 0.1UF/10V 2.2UF/6.3V
19 20 19 20
DQ3 DQ12 DDR_A_D1 pt_c0805_h53 DQ3 DQ12 DDR_B_D12
21 VSS38 22 21 VSS38 22
DDR_A_D7 DQ13 DDR_B_D9 DQ13 pt_c0805_h53
23 DQ8 24 23 DQ8 24
DDR_A_D2 VSS17 DDR_A_DM0 DDR_B_D13 VSS17 DDR_B_DM1
25 DQ9 26 25 DQ9 26
DM1 DM1
27 VSS49 28 27 VSS49 28
DDR_A_DQS#0 VSS53 DDR_B_DQS#1 VSS53 +1.8V_SUS
29 DQS#1 30 M_CLK_DDR0 10 29 DQS#1 30 M_CLK_DDR2 10
DDR_A_DQS0 CK0 DDR_B_DQS1 CK0 Please these Caps near So-Dimm1.
31 32 M_CLK_DDR#0 10 31 32 M_CLK_DDR#2 10
DQS1 CK0# DQS1 CK0#
33 VSS39 34 33 VSS39 34
DDR_A_D4 VSS41 DDR_A_D5 DDR_B_D10 VSS41 DDR_B_D11
35 DQ10 36 35 DQ10 36
37 38 37 38
DQ11 DQ15 DQ11 DQ15
1
39 40 39 40 C154 C119 C163 C147 C168
VSS50 VSS54 VSS50 VSS54
41 42 41 42 2.2UF/6.3V 2.2UF/6.3V 2.2UF/6.3V 2.2UF/6.3V 2.2UF/6.3V
DDR_A_D16 VSS18 VSS20 DDR_A_D17 DDR_B_D20 VSS18 VSS20 DDR_B_D21 MLCC/+/-10% MLCC/+/-10% MLCC/+/-10% MLCC/+/-10% MLCC/+/-10%
2
43 DQ16 44 43 DQ16 44
DDR_A_D21 DQ20 DDR_A_D20 DDR_B_D16 DQ20 DDR_B_D23 pt_c0603 pt_c0603 pt_c0603 pt_c0603 pt_c0603
45 DQ17 46 45 DQ17 46
DQ21 DQ21
47 48 47 48
DDR_A_DQS#2 VSS1 VSS6 PM_EXTTS#0 DDR_B_DQS#2 VSS1 VSS6 PM_EXTTS#1
49 DQS#2 50 PM_EXTTS#0 10 49 DQS#2 50 PM_EXTTS#1 10
DDR_A_DQS2 NC3 DDR_A_DM2 DDR_B_DQS2 NC3 DDR_B_DM2
51 DQS2 52 51 DQS2 52
DM2 DM2 +1.8V_SUS
53 VSS19 54 53 VSS19 54
DDR_A_D19 VSS21 DDR_A_D18 DDR_B_D18 VSS21 DDR_B_D22 Please these Caps near So-Dimm2.
55 DQ18 56 55 DQ18 56
57 DQ19 58 57 DQ19 58
DQ23 DQ23
59 VSS22 60 59 VSS22 60
61 DQ24 62 61 DQ24 62
DQ28 DQ28
1
DDR_A_D27 63 64 DDR_A_D29 DDR_B_D28 63 64 DDR_B_D31 C138 C395 C379 C151 C142
DQ25 DQ29 DQ25 DQ29
65 VSS23 66 65 VSS23 66
DDR_A_DM3 VSS25 DDR_A_DQS#3 DDR_B_DM3 VSS25 DDR_B_DQS#3 2.2UF/6.3V 2.2UF/6.3V 2.2UF/6.3V 2.2UF/6.3V 2.2UF/6.3V
67 DM3 68 67 DM3 68
DQS#3 DDR_A_DQS3 DQS#3 DDR_B_DQS3 MLCC/+/-10% MLCC/+/-10% MLCC/+/-10% MLCC/+/-10% MLCC/+/-10%
2
69 NC4 70 69 NC4 70
DQS3 DQS3 pt_c0603 pt_c0603 pt_c0603 pt_c0603 pt_c0603
71 VSS9 72 71 VSS9 72
C DDR_A_D31 VSS10 DDR_A_D30 DDR_B_D27 VSS10 DDR_B_D24 C
73 DQ26 74 73 DQ26 74
75 DQ27 76 75 DQ27 76
DQ31 DQ31 +1.8V_SUS
77 VSS4 78 77 VSS4 78
VSS8 VSS8 Please these Caps near So-Dimm1.
10,20 DDR_CKE0_DIMMA 79 CKE0 80 DDR_CKE1_DIMMA 10,20 10,20 DDR_CKE2_DIMMB 79 CKE0 80 DDR_CKE3_DIMMB 10,20
CKE1 CKE1
81 VDD7 82 81 VDD7 82
VDD8 VDD8
83 NC1 84 83 NC1 84
DDR_A_BS2 A15 DDR_A_MA14 DDR_B_BS2 A15 DDR_B_MA14
11,20 DDR_A_BS2 85 A16_BA2 86 11,20 DDR_B_BS2 85 A16_BA2 86
A14 A14
1
87 88 87 88 C128 C136 C153 C125
DDR_A_MA12 VDD9 VDD11 DDR_A_MA11 DDR_B_MA12 VDD9 VDD11 DDR_B_MA11
89 A12 90 89 A12 90
DDR_A_MA9 A11 DDR_A_MA7 DDR_B_MA9 A11 DDR_B_MA7 0.1UF/10V 0.1UF/10V 0.1UF/10V 0.1UF/10V
91 A9 92 91 A9 92
DDR_A_MA8 A7 DDR_A_MA6 DDR_B_MA8 A7 DDR_B_MA6 MLCC/+80-20%MLCC/+80-20%MLCC/+80-20%MLCC/+80-20%
2
93 A8 94 93 A8 94
A6 A6
95 VDD5 96 95 VDD5 96
DDR_A_MA5 VDD4 DDR_A_MA4 DDR_B_MA5 VDD4 DDR_B_MA4
97 A5 98 97 A5 98
DDR_A_MA3 A4 DDR_A_MA2 DDR_B_MA3 A4 DDR_B_MA2
99 A3 100 99 A3 100
DDR_A_MA1 A2 DDR_A_MA0 DDR_B_MA1 A2 DDR_B_MA0
101 A1 102 101 A1 102
A0 A0 +1.8V_SUS
103 VDD10 VDD12 104 103 VDD10 VDD12 104
DDR_A_MA10 105 106 DDR_A_BS1 DDR_B_MA10 105 106 DDR_B_BS1 Please these Caps near So-Dimm2.
DDR_A_BS0 A10/AP BA1 DDR_A_RAS# DDR_A_BS1 11,20 DDR_B_BS0 A10/AP BA1 DDR_B_RAS# DDR_B_BS1 11,20
11,20 DDR_A_BS0 107 BA0 108 DDR_A_RAS# 11,20 11,20 DDR_B_BS0 107 BA0 108 DDR_B_RAS# 11,20
DDR_A_WE# RAS# DDR_B_WE# RAS#
11,20 DDR_A_WE# 109 WE# 110 DDR_CS0_DIMMA# 10,20 11,20 DDR_B_WE# 109 WE# 110 DDR_CS2_DIMMB# 10,20
S0# S0#
111 VDD2 112 111 VDD2 112
VDD1 VDD1
1
DDR_A_CAS# 113 114 M_ODT0 DDR_B_CAS# 113 114 M_ODT2 C167 C384 C388 C393
11,20 DDR_A_CAS# CAS# ODT0 DDR_A_MA13 M_ODT0 10,20 11,20 DDR_B_CAS# CAS# ODT0 DDR_B_MA13 M_ODT2 10,20
10,20 DDR_CS1_DIMMA# 115 S1# 116 10,20 DDR_CS3_DIMMB# 115 S1# 116
A13 A13 0.1UF/10V 0.1UF/10V 0.1UF/10V 0.1UF/10V
117 VDD3 118 117 VDD3 118
M_ODT1 VDD6 M_ODT3 VDD6 MLCC/+80-20%MLCC/+80-20%MLCC/+80-20%MLCC/+80-20%
2
10,20 M_ODT1 119 ODT1 120 10,20 M_ODT3 119 ODT1 120
NC2 NC2
121 VSS11 122 121 VSS11 122
123 124 123 124
DDR_A_D33 DQ32 DQ36 DDR_A_D38 DDR_B_D36 DQ32 DQ36 DDR_B_D32
125 DQ33 126 125 DQ33 126
DQ37 DQ37
127 VSS26 128 127 VSS26 128
DDR_A_DQS#4 VSS28 DDR_A_DM4 +3.3V_RUN DDR_B_DQS#4 VSS28 DDR_B_DM4
129 130 129 130
DDR_A_DQS4 DQS#4 DM4 Non-iAMT DDR_B_DQS4 DQS#4 DM4
131 DQS4 132 131 DQS4 132
VSS42 DDR_A_D37 VSS42 DDR_B_D39
133 VSS2 134 133 VSS2 134
135 DQ34 136 135 DQ34 136
DQ39 DQ39
MLCC/+/-10%
MLCC/+80-20%
B DDR_A_D34 137 138 DDR_B_D33 137 138 B

DQ35 VSS55 DQ35
1
DDR_A_D45 VSS55 DDR_B_D40

139 VSS27 140 139 VSS27 140
141 DQ40 142 141 DQ40 142
DDR_A_D47 DQ45 C445 C200 DDR_B_D46 DQ45
143 DQ41 144 143 DQ41 144
VSS43 DDR_A_DQS#5 VSS43 DDR_B_DQS#5
2
145 VSS29 DQS#5 146 145 VSS29 DQS#5 146

DDR_A_DM5 147 148 DDR_A_DQS5 2.2UF/6.3V 0.1UF/10V DDR_B_DM5 147 148 DDR_B_DQS5
DM5 DQS5 DM5 DQS5 +3.3V_RUN
149 150 149 150
DDR_A_D42 151
VSS51 VSS56
152 DDR_A_D41 pt_c0805_h53 DDR_B_D44 151
VSS51 VSS56
152 DDR_B_D47 Non-iAMT
DDR_A_D43 DQ42 DQ46 DDR_A_D46 DDR_B_D42 DQ42 DQ46 DDR_B_D43
153 154 153 154
DQ43 DQ47 DQ43 DQ47
155 VSS40 156 155 VSS40 156
VSS44 VSS44
MLCC/+/-10%
MLCC/+80-20%
DDR_A_D48 157 158 DDR_A_D53 DDR_B_D53 157 158 DDR_B_D52
DQ48 DQ52 DQ48 DQ52
1
DDR_A_D49 159 160 DDR_A_D52 DDR_B_D48 159 160 DDR_B_D49
DQ49 DQ53 DQ49 DQ53
161 VSS52 162 161 VSS52 162
VSS57 VSS57 C435 C429
163 NCTEST 164 M_CLK_DDR1 10 163 NCTEST 164 M_CLK_DDR3 10
CK1 CK1
2
165 166 M_CLK_DDR#1 10 165 166 M_CLK_DDR#3 10
DDR_A_DQS#6 VSS30 CK1# DDR_B_DQS#6 VSS30 CK1# 2.2UF/6.3V 0.1UF/10V
167 DQS#6 VSS45 168 167 DQS#6 VSS45 168
DDR_A_DQS6 169 170 DDR_A_DM6 DDR_B_DQS6 169 170 DDR_B_DM6
DQS6 DM6 DQS6 DM6 pt_c0805_h53
171 172 171 172
DDR_A_D50 VSS31 VSS32 DDR_A_D51 DDR_B_D51 VSS31 VSS32 DDR_B_D55
173 DQ50 174 173 DQ50 174
175 DQ51 176 175 DQ51 176
DQ55 DQ55
177 178 177 178
DDR_A_D56 VSS33 VSS35 DDR_A_D58 DDR_B_D56 VSS33 VSS35 DDR_B_D57
179 DQ56 180 179 DQ56 180
181 DQ57 182 181 DQ57 182
DQ61 DQ61
183 184 183 184 Non-iAMT
DDR_A_DM7 VSS3 VSS7 DDR_A_DQS#7 DDR_B_DM7 VSS3 VSS7 DDR_B_DQS#7
185 DM7 186 185 DM7 186
DQS#7 DDR_A_DQS7 DQS#7 DDR_B_DQS7
187 VSS34 188 187 VSS34 188
DDR_A_D61 DQS7 DDR_B_D63 DQS7
189 190 189 190
DDR_A_D59 DQ58 VSS36 DDR_A_D63 DDR_B_D60 DQ58 VSS36 DDR_B_D58 +3.3V_RUN
191 DQ59 192 191 DQ59 192
DQ62 DDR_A_D62 Non-iAMT DQ62 DDR_B_D59
193 VSS14 194 193 VSS14 194
MEM_SDATA DQ63 MEM_SDATA DQ63
17 MEM_SDATA 195 196 195 196
MEM_SCLK SDA VSS13 MEM_SCLK SDA VSS13 R172
17 MEM_SCLK 197 SCL 198 197 SCL 198
SA0 SA0
+3.3V_RUN 199 VDDSPD 200 199 VDDSPD 200 2 1
SA1 SA1
2
A +3.3V_RUN A
201 202 201 202
2
GND0 GND1 R178 R171 GND0 GND1
203 NP_NC1NP_NC2 204 203 NP_NC1NP_NC2 204
SMbus address A0 SMbus address A4 R170 10KOhm
Non-iAMT STD 10KOhm 10KOhm STD 5%
FOXCONN/AS0A426-N2SN-7F 5% 5% FOXCONN/AS0A426-NASN-7F 10KOhm
5%
CLOCK 0 , 1
1
CLOCK 2 , 3
1
CKE 0 , 1
CKE 2 , 3
PROJECT: Lanai 1.2 SHEET 19 OF 68 DDR2 SO-DIMM (0) RELEASE DATE :
5 4 3 2 1
5 4 3 2 1
D D
TOP
+0.9V_DDR_VTT Layout note : Place 1 cap close to every 1 R-pack terminated to SMDDR_VTERM.
1
C148 C192 C118 C170 C190 C137 C189 C175 C135 C144 C149 C139 C169
0.1UF/10V 0.1UF/10V 0.1UF/10V 0.1UF/10V 0.1UF/10V 0.1UF/10V 0.1UF/10V 0.1UF/10V 0.1UF/10V 0.1UF/10V 0.1UF/10V 0.1UF/10V 0.1UF/10V
MLCC/+80-20% MLCC/+80-20% MLCC/+80-20% MLCC/+80-20% MLCC/+80-20% MLCC/+80-20% MLCC/+80-20% MLCC/+80-20% MLCC/+80-20% MLCC/+80-20% MLCC/+80-20% MLCC/+80-20% MLCC/+80-20%
2
+0.9V_DDR_VTT
BOT
1
C155 C186 C146 C165 C130 C123 C150 C120 C191 C143 C164 C156 C185
0.1UF/10V 0.1UF/10V 0.1UF/10V 0.1UF/10V 0.1UF/10V 0.1UF/10V 0.1UF/10V 0.1UF/10V 0.1UF/10V 0.1UF/10V 0.1UF/10V 0.1UF/10V 0.1UF/10V
MLCC/+80-20% MLCC/+80-20% MLCC/+80-20% MLCC/+80-20% MLCC/+80-20% MLCC/+80-20% MLCC/+80-20% MLCC/+80-20% MLCC/+80-20% MLCC/+80-20% MLCC/+80-20% MLCC/+80-20% MLCC/+80-20%
2
C C
10,11,19 DDR_A_MA[0..14] DDR_B_MA[0..14] 10,11,19

+0.9V_DDR_VTT
DDR_A_MA6 RN19A 1 RN21A DDR_B_MA14

DDR_A_MA7 56Ohm 2 1 56Ohm 2 DDR_B_MA7
RN19B 3 5% RN21B 4 5%
56Ohm 4
5% 3 56Ohm
5%

DDR_A_BS1 56Ohm 2 1 56Ohm 2 DDR_B_MA11
RN26B 3 5% RN18B 5%
11,19 DDR_A_BS1 56Ohm 4
5% 3 56Ohm 4
5%
DDR_A_RAS# RN29A 1 RN34A DDR_B_BS1

11,19 DDR_A_RAS# DDR_A_MA13 56Ohm 2 1 56Ohm 2 DDR_B_MA0 DDR_B_BS1 11,19
RN29B 3 5% RN34B 4 5%
56Ohm 4
5% 3 5%
56Ohm

B DDR_A_MA2 56Ohm 2 1 56Ohm 2 DDR_B_RAS# B
RN23B 3 5% RN30B 4 5%
56Ohm 4
5% 3 5%
56Ohm DDR_B_RAS# 11,19
DDR_A_MA8 RN24A RN17A 1 DDR_A_MA11

DDR_A_MA5
1 56Ohm 2 56Ohm 2 DDR_A_MA14
RN24B 3 5% RN17B 4 5%
56Ohm 4
5% 3 5%
56Ohm
Please these resistor RN16B 3 5% RN28B 5% Please these resistor
11,19 DDR_A_BS2 56Ohm 4
5% 3 56Ohm 4
5%
closely DIMMA, all closely DIMMB, all
trace length<750 mil. DDR_A_MA9 RN27A 1 RN31A DDR_B_WE# trace length<750 mil.
DDR_A_MA3 56Ohm 2 1 56Ohm 2 DDR_B_BS0 DDR_B_WE# 11,19
RN27B 3 4 5% RN31B 3 5%
56Ohm
5% 56Ohm 4
5% DDR_B_BS0 11,19

RN33B 3 4 5% RN20B 3 4 5%
11,19 DDR_A_BS0 5%
56Ohm 56Ohm
5%
DDR_A_WE# RN32A 1 RN35A DDR_B_MA10

11,19 DDR_A_WE# DDR_A_CAS# 56Ohm 2 1 56Ohm 2 DDR_B_CAS#
RN32B 3 4 5% RN35B 3 5%
11,19 DDR_A_CAS# 56Ohm
5% 56Ohm 4
5% DDR_B_CAS# 11,19
DDR_B_MA4 RN25A 1 RN22A DDR_B_MA2

DDR_B_MA5 56Ohm 2 1 56Ohm 2 DDR_B_MA8
RN25B 3 5% RN22B 5%
56Ohm 4
5% 3 56Ohm 4
5%
M_ODT0 5% R147 1 2 56Ohm R153 1 2 5% 56Ohm M_ODT2
10,19 M_ODT0 M_ODT2 10,19
5% R157 1 2 56Ohm R154 1 2 5% 56Ohm
10,19 M_ODT1 DDR_A_MA1 M_ODT3 10,19
5% R152 1 2 56Ohm R133 1 2 5% 56Ohm
DDR_B_BS2 11,19
5% R149 1 2 56Ohm R155 1 2 5% 56Ohm
10,19 DDR_CS0_DIMMA# DDR_CS2_DIMMB# 10,19
5% R158 1 2 56Ohm R156 1 2 5% 56Ohm
10,19 DDR_CS1_DIMMA# DDR_CS3_DIMMB# 10,19
5% R124 1 2 56Ohm R125 1 2 5% 56Ohm
10,19 DDR_CKE0_DIMMA DDR_CKE2_DIMMB 10,19
5% R126 1 2 56Ohm R131 1 2 5% 56Ohm
A 10,19 DDR_CKE1_DIMMA DDR_CKE3_DIMMB 10,19 A
PROJECT: Lanai 1.2 SHEET 20 OF 68 DDR2 SO-DIMM (1) RELEASE DATE :
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN
X2 R52
CLK_XTAL_IN 1 2 CLK_XTAL_OUT PCIE_LOM_CLKREQ# R79 10KOhm 5%
Non-iAMT +3.3V_RUN
Non-iAMT 1 2
CLK_3GPLLREQ# R70
1 2
10KOhm 5%
1 2
+3.3V_RUN +3.3V_RUN 14.31818Mhz 0Ohm SATA_CLKREQ# R80 1 2 10KOhm 5%
1
5% CARD_CLK_REQ# R76 1 2 10KOhm 5%
R61 C69 MINI1CLK_REQ# R42 10KOhm 5%
1 2
1
1 2 10KOhm PCI_PCCARD No.25 MINI2CLK_REQ# R45 1 2 10KOhm 5%
27PF/50V C66
2
MLCC/+/-5%
2
2
5%
R78 R85 27PF/50V
2
MLCC/+/-5% 14.318MHz
10KOhm 10KOhm /*
5% 5% PGMODE R43
/* /* 1 2 10KOhm
1
1
D 5% D
FSA PCI_LOM
Populate for Napa platforms only

2
R77 R83
10KOhm 10KOhm
5% 5%
/*
1
U5
1 7 +CK_VDD_A
VDDSRC1 VDDA
49 VDDSRC2 GNDA 8
0=UMA 54 VDDSRC3
1=Disc. GRFX down 65 VDDSRC4 PCI_SRC_STOP# 25 H_STP_PCI# 17
CPU_STOP# 24 H_STP_CPU# 17
+CK_VDD_MAIN2 30 VDDPCI1 MCH_BCLK 5% 1 RN3A
36 VDDPCI2 CPUT1_MCH 11 33Ohm 2 CLK_MCH_BCLK 9
10 MCH_BCLK# 5% 3 RN3B
+CK_VDD_MAIN CPUC1_MCH 33Ohm 4 CLK_MCH_BCLK# 9
12 VDDCPU
14 CPU_BCLK 5% 1 RN2A
+CK_VDD_48 CPUT0 CPU_BCLK# 33Ohm 2 CLK_CPU_BCLK 7
40 13 5% 3 RN2B
VDD48 CPUC0 33Ohm 4 CLK_CPU_BCLK# 7
+CK_VDD_REF 18 6 CPU_XTP 5% 1 RN4A
VDDREF CPUT2_ITP/SRCT10 CPU_XTP# 33Ohm 2 CLK_XDP 52
Non-iAMT 5 5% 3 RN4B
CLK_XTAL_IN CPUC2_ITP/SRCC10 33Ohm 4 CLK_XDP# 52
20 X1
+3.3V_RUN No.6 CLK_XTAL_OUT 19 9 PGMODE 5% 2 10KOhm 1 R75 /* Non-iAMT
X2 *PG_MODE +3.3V_RUN
R67 1 2 33Ohm 5%
17 CLK_ICH_48M PCIE_MINI1
Enable ITP R68 1 2 2.2KOhm 5% FSA 41 3 5% 1 RN5A
7,10 CPU_MCH_BSEL0 USB_48MHz/FSLA SRCT9 PCIE_MINI1# 33Ohm 2 CLK_PCIE_MINI1 50
FSB 45 2 5% 3 RN5B
7,10 CPU_MCH_BSEL1 FSLB/TEST_MODE SRCC9 33Ohm 4 CLK_PCIE_MINI1# 50
2
R69 1 2 2.2KOhm 5% FSC 23 72

C 7,10 CPU_MCH_BSEL2 REF0/FSLC/TEST_SEL CLKREQ9# PCIE_MINI2 MINI1CLK_REQ# 50 C
R72 No.44 5% 1 RN1A
SRCT8 70
PCIE_MINI2# 33Ohm 2 CLK_PCIE_MINI2 50
R53 1 2 33Ohm 5% CLKREF 22 69 5% 3 RN1B
10KOhm 17 CLK_ICH_14M REF1 SRCC8 33Ohm 4 CLK_PCIE_MINI2# 50
5% CLKREQ8# 71 MINI2CLK_REQ# 50
R55 1 2 33Ohm 5% PCI_SIO 27 66 PCIE_ICH 5% 3 RN7B
37 CLK_PCI_5025 PCI1 SRCT7 PCIE_ICH# 33Ohm 4 CLK_PCIE_ICH 16
R59 2 33Ohm 5% PCI_PCCARD 5% 1 RN7A
1
32 CLK_PCI_PCCARD 1 32 *PCI2/TME SRCC7 67 33Ohm 2 CLK_PCIE_ICH# 16

33 PCI3 CLKREQ7# 38
PCI_LOM 34 63
PCI_ICH PCI4/FCTSEL1 SRCT6
SRCC6 64
43 DOTT_96/27MHz_NS CLKREQ6# 62
5% 1 RN11A 27M_NSS PCIE_EXPCARD 5% 3 RN8B
10 MCH_DREFCLK 33Ohm 2 27M_SS
44 DOTC_96/27MHz_SS SRCT5 60
PCIE_EXPCARD# 33Ohm 4 CLK_PCIE_EXPCARD 35
5% 3 RN11B 5% 1 RN8A
10 MCH_DREFCLK# 33Ohm 4 SRCC5 61 33Ohm 2 CLK_PCIE_EXPCARD# 35
37 PCI_F0/ITP_EN CLKREQ5# 29 CARD_CLK_REQ# 35
33Ohm5% 1 2 R62 PCI_ICH 58 PCIE_LOM 5% 3 RN9B
16 CLK_PCI_ICH SRCT4 PCIE_LOM# 33Ohm 4 CLK_PCIE_LOM 47
39 59 5% 1 RN9A
CK_PWRGD/PD# SRCC4 33Ohm 2 CLK_PCIE_LOM# 47
CLKREQ4# 57 PCIE_LOM_CLKREQ# 47
CLK_SCLK 16 55 MCH_3GPLL 5% 3 4 RN10B
CLK_SDATA SMBCLK SRCT3 MCH_3GPLL# 33Ohm CLK_MCH_3GPLL 10
17 56 5% 1 2 RN10A
SMBDAT SRCC3 33Ohm CLK_MCH_3GPLL# 10
+3.3V_RUN UMA without iAMT 28 1% 475Ohm 1 2 R57
CLKREQ3# XDP_3GPLL CLK_3GPLLREQ# 10
15 52 5% 3 4 RN14B
17 CLK_PWRGD GNDCPU SRCT2 XDP_3GPLL# 33Ohm CLK_PCIE_XDP_3GPLL 52
L9 31 53 5% 1 2 RN14A
+CK_VDD_MAIN GNDPCI1 SRCC2 33Ohm CLK_PCIE_XDP_3GPLL# 52
1 2 35 GNDPCI2 CLKREQ2# 26
21 50 PCIE_SATA 5% 3 RN13B
GNDREF SRCT1/SATAT 22Ohm 4 CLK_PCIE_SATA 15
1
PCIE_SATA# 5% 1
330Ohm/100Mhz 4 GNDSRC1 SRCC1/SATAC 51 22Ohm 2 RN13A CLK_PCIE_SATA# 15
pt_l0805_h41 C75 C71 C54 C56 C63 C81 42 46
GND48 CLKREQ1# SATA_CLKREQ# 17
0.1UF/10V 0.1UF/10V 0.1UF/10V 0.1UF/10V 0.1UF/10V
MURATA/BLM21PG331SN1D 10UF/10V 68 No.40
MLCC/+80-20% MLCC/+80-20% MLCC/+80-20% Place close to Clock Gen. GNDSRC2 DOT96_SSC 5% 3 RN12B
120 OHM@100MHz
2
LCD100/SRCT0 47 33Ohm 4 DREF_SSCLK 10

MLCC/+80-20% MLCC/+80-20%
MLCC/+80-20% pt_c0805_h53 73 48 DOT96_SSC# 5% 1 RN12A
GND LCD100/SRCC0 33Ohm 2 DREF_SSCLK# 10
R54 2.2Ohm CLK_ICH_48M ICS9LPR333CKLFT
1 5%2 +CK_VDD_A CLK_PCI_ICH No.28
pt_r0603 CLK_ICH_14M
CLK_PCI_5025
1
B B
C55 C62 +3.3V_ALW +3.3V_RUN
0.047UF/10V 4.7UF/6.3V
SMBus address D2 Non-iAMT
1
MLCC/+/-10% MLCC/+/-10%
2
pt_c0603 C76 C72 C70 C64

10PF/50V 10PF/50V 10PF/50V 10PF/50V
L10
2
1 2 +CK_VDD_MAIN2 MLCC/+/-0.5PF MLCC/+/-0.5PF MLCC/+/-0.5PF MLCC/+/-0.5PF No.57
2
4
330Ohm/100Mhz FSC FSB FSA CPU SRC PCI
1
pt_l0805_h41
MURATA/BLM21PG331SN1D C67 C73 C80 RN6A 2.2KOhm 1 0 1 100 100 33
2
120 OHM@100MHz 0.1UF/10V 0.1UF/10V 10UF/10V RN6B 5%
2.2KOhm 0 0 1 133 100 33
MLCC/+80-20% MLCC/+80-20% R88 5%
2
MLCC/+80-20% pt_c0805_h53 0 1 1 166 100 33
1
3
2.2KOhm
1
CLK_PCI_PCCARD 5% 0 1 0 200 100 33
G
R81 2.2Ohm Q19 CLK_SDATA 0 0 0 266 100 33
S 2
+CK_VDD_48 37 CKG_SMBDAT
5%
D
1 2
pt_r0603 1 0 0 333 100 33
2N7002 1 1 0 400 100 33
1
No.57 R89 0Ohm

C74 C77 1 2 /* 1 1 1 RSVD 100 33
1
0.047UF/10V 4.7UF/6.3V 5%
MLCC/+/-10% MLCC/+/-10% C78 +3.3V_ALW +3.3V_RUN
2
pt_c0603
10PF/50V
2
MLCC/+/-0.5PF
2
R87
R47
1
+CK_VDD_REF 2.2KOhm
G
1 2 5% CLK_SCLK
PCI_LOM=FCTSEL1
Q18
S 2
37 CKG_SMBCLK
1
A 1Ohm A
1
D
5% C60 FCTSEL1(PIN 34) Pin43 Pin44 Pin47 Pin48
pt_r0603 0.047UF/10V 2N7002
MLCC/+/-10% R86 0 = UMA DOT96T DOT96C 96/100M_T 96/100M_C
2
1 2 1 = Disc. 27Mout 27M_SSout SRCT0 SRCC0

0Ohm /* GRFX down
5%
PROJECT: Lanai 1.2 SHEET 21 OF 68 CLK GEN. CY28547 RELEASE DATE :
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
PROJECT: Lanai 1.2 SHEET 23 OF 68 RELEASE DATE :
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
5 4 3 2 1
A B C D E
1 1
2 2
3 3
4 4
5 5
A B C D E
5 4 3 2 1
D D
C C
B B
A A
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
PROJECT: Lanai 1.2 SHEET 27 OF 68 RELEASE DATE : Sean Kuo
5 4 3 2 1
5 4 3 2 1
CON1 Q1
+15V_ALW +3.3V_RUN +LCDVCC
56 USBP5_D-
56 USBP5_D+
55 55
54 54 6
53 53 5 4
52 AUX_LCD_CBL_DET# 2
52 +5V_CCD AUX_LCD_CBL_DET# 37
68 NP_NC2 51 51 1
50 +3V_DMIC
50
49 49 AUD_DMIC_IN0 44
2
66 SIDE_10 48 48
2
47 AUD_DMIC_CLK_L R24 FDC653N_NL
47
1
R17
3
46 46
64 45 LCD_CBL_DET_R 150Ohm C10 C6
D SIDE_8 45 INVERTER_CBL_DET# LCD_CBL_DET_R 37 D
44 330KOhm pt_r0603_h22
44 LAMP_STAT# INVERTER_CBL_DET# 37 22UF/10V 0.1UF/16V
T135 Adress: A9H --Contrast 5% 5%
2
43 43 1 MLCC/+80%-20% MLCC/+/-10%
No.9 LCDVCC_ON
1
63 SIDE_7 42 42 +5V_ALW AAH --Backlight pt_c1206_h71
41 41
2
40 40 LCD_SMBCLK 37 No.56
1
39 R23 /* C15
39 LCD_SMBDAT 37
62 SIDE_6 38 38
1
37 BACKLITEON C4 C3
37 100KOhm 0.01UF/25V GND
2
36 36
47PF/50V 47PF/50V 5% MLCC/+/-10%
1
35 35 GFX_PWR_SRC
MLCC/+/-5% MLCC/+/-5% +3.3V_RUN +3.3V_ALW
2
61 SIDE_5 34 34
33 /* /* 3 GND GND 3
33 D D
32 GND GND Q3
32 2N7002 Q4
31 31 LCD_TST 38
60 30 1 1
SIDE_4 30 +LCDVCC
2
29 G G 2N7002
29 R20 /* R35
S 2 2 S
28 28 +3.3V_RUN
27 LCD_A2+ LCD_B2+
27 LCD_DDCDAT 10
59 SIDE_3 26 26 LCD_DDCCLK 10
25 47KOhm 47KOhm
25
1
LCD_B2- C316 /* C315 /* 5% 5% GND GND
1
24 24 LCD_B2- 10
23 LCD_B2+ R26 /* 1 2 0Ohm 5%
23 LCD_B2+ 10
22 22
LCD_B1- 3.3PF/50V 3.3PF/50V Q2 3
2
58 SIDE_2 21 21 LCD_B1- 10
20 LCD_B1+ LCD_A2- LCD_B2- D2 C
20 LCD_B1+ 10 R1 B
19 1 2 2
19 LCD_B0- LCD_A1+ LCD_B1+ 10 ENVDD
18 18 LCD_B0- 10
57 17 LCD_B0+ RB751S40T1G E
SIDE_1 17 LCD_B0+ 10 R2
16 16
1
15 LCD_BCLK-_C C311 /* C314 /* D1
15 LCD_BCLK+_C
14 14 37 LCDVCC_TST_EN 1 2
13 DDTC124EUA-7-F 1
C 13 LCD_ACLK-_C 3.3PF/50V 3.3PF/50V RB751S40T1G C
2
65 SIDE_9 12 12
11 LCD_ACLK+_C LCD_A1- LCD_B1-
11
10 10
9 LCD_A2- LCD_A0+ LCD_B0+
9 LCD_A2+ LCD_A2- 10
67 NP_NC1 8 8 LCD_A2+ 10
7 7
1
6 LCD_A1- C308 /* C307 /* GND
6 LCD_A1+ LCD_A1- 10
5 5 LCD_A1+ 10
4 4
LCD_A0- 3.3PF/50V 3.3PF/50V
2
3 3 LCD_A0- 10
2 LCD_A0+ LCD_A0- LCD_B0- +3.3V_RUN +LCDVCC
2 LCD_A0+ 10
1 1
R16 0Ohm 5% R8 0Ohm 5%
LCD_ACLK+_C 1 2 LCD_BCLK+_C 1 2
LCD_ACLK+ 10 LCD_BCLK+ 10
1
C7
2
2
WTOB_CON_56P C1 C2
1
JAE/FI-M56SB1 R4 No.23 R5 No.23 0.1UF/10V 0.047UF/10V
0Ohm C16 0Ohm C11 L2 0.1UF/10V MLCC/+80-20%MLCC/+/-10%
2
5% /* 5% /* +3V_DMIC MLCC/+80-20%
8.2PF/50V 8.2PF/50V 1 2
R15 0Ohm 5% R7 0Ohm 5% +3.3V_RUN
2
GND LCD_ACLK-_C /* LCD_BCLK-_C /* 600Ohm Irat=200mA GND GND
1
1
1 2 LCD_ACLK- 10 1 2 LCD_BCLK- 10
No.9
1
C5 +5V_ALW
No.9 No.48 +3.3V_RUN 10UF/10V

Populate R1 for MLCC/+/-20%
1
0Ohm R539 pt_c0805_h57
pt_r0603
DPST implementation C312
1 2
+5V_RUN 1 only.
R6 /* 0.1UF/10V
2
Q70 MLCC/+/-10%
B 10KOhm B
SI2301BDS 5%
/*
+5V_CCD GND
2
2 3
S
3 D
BACKLITEON
2
10 BIA_PWM 1 2
R1 0Ohm 5% Populate R6 for
G
2
+PWR_SRC GFX_PWR_SRC
11
platform without DPST

R540
1
C539 support. No Stuff for 40mils 40mils

10KOhm
1
1UF/10V/X7R C306 Discrete DSPT support

pt_c0603 /* 10UF/10V
MLCC/+/-10% C540 MLCC/+80-20% due to back up plan.
1
1
/* pt_c0805_h53 C309
2
1 2
+3.3V_RUN C310
6
1UF/10V/X7R
2.2UF/25V
2
pt_c0603 MLCC/+/-10% No.27 Q49 0.1UF/50V
2
pt_c0805_h53
1
DTC114EKA Q71 R312 C305 MLCC/+/-10%
/* /* FDC658P_NL pt_c0603
1
3
C
R551 1 2 0Ohm 5% No.52

R2
100KOhm 0.1UF/50V
2
5% MLCC/+/-10%
1
B
U1 pt_c0603
No.19
1
1 OE# Vcc 5
R1
2 GND
44 AUD_DMIC_CLK A
2 1 3 4 1 2 1 2 AUD_DMIC_CLK_L
R314 GND Y
2
10KOhm SN74LVC1G125DBVR L44 R552 C543

17 CCD_VDD_ON
1
5% /* 80Ohm 47Ohm 33PF/50V
/* pt_l0603 5% MLCC/+/-5% R313
/*
2
R2 1 2 0Ohm 5% 100KOhm
5%
2
A
V_DMIC IS DEPENDENT ON MIC SELECTION (1.8V - 3.3V TYP) 3 A
16 ICH_USBP5- Verify to ensure operability with chosen mic supplier. D
4
USBP5_D-
L1 USBP5_D+ Q48
Note1: If only 1 digital mic, use AUD_DMIC_IN0. 1
90OHM/100MHz 37,49,51,54 RUN_ON 2N7002
G
16 ICH_USBP5+ /* 2 S
1
MURATA/DLW21SN900SQ2L Note2: If using 2 dig mics, also use AUD_DMIC_IN0.

R3 1 2 0Ohm 5% This input supports 2 digimics. AUD_DMIC_IN1 is only
used to support 4 dig mics.
GND
PROJECT: Lanai 1.2 SHEET 28 OF 68 LVDS CON RELEASE DATE :
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
5 4 3 2 1
D D
C C
B B
A A
A B C D E
1 1
CON12
SATA Connector 25 NP_NC3 1
2
1
2 SATA_TX0+ 15
ODD Connector
23 NP_NC1 3 3 SATA_TX0- 15
4 4
5 SATA_RXN0_C
5 SATA_RXP0_C
6 6
7 +5V_MOD
+5V_HDD 7
2
8 R254
8 +3.3V_RUN
C58 /* C46 /* 9
9 100KOhm
1
1
10 +5V_MOD
0.1UF/10V/Y5V 1000PF/50V 10 5%
11 11 /* CON19
1
12 12
MLCC/+80-20% MLCC/+/-10% +5V_MOD +5V_MOD
2
13 13
C254
C260
C268
14 BtoB_CON_50P
14 +5V_HDD
54
52
15 15
1
16 16
17 1 2
NP_NC4
NP_NC2
17 R285 1 2
pt_c0805_h57
MLCC/+80-20%
MLCC/+80-20%
MLCC/+/-20%
18 3 4
10UF/10V/X5R
0.1UF/10V/Y5V
0.1UF/10V/Y5V
2 2
18 3 4 IDE_DD8
Place caps close to 2 56Ohm 15%
2
19 19 17 IDE_RST_MOD 5 5 6 6
24 20 IDE_DD7 7 8 IDE_DD9
connector. NP_NC2 20
21 IDE_DD6 9
7 8
10 IDE_DD10
21 IDE_DD5 9 10 IDE_DD11
26 NP_NC4 22 22 11 11 12 12
IDE_DD4 13 14 IDE_DD12
IDE_DD3 13 14 IDE_DD13
15 15 16 16
SATA_CON_22P IDE_DD2 17 18 IDE_DD14
FOXCONN/LD2822H-SA3L6 IDE_DD1 17 18 IDE_DD15
19 19 20 20
Place caps close to IDE_DD0 21 22 IDE_DDREQ
21 22 IDE_DIOR#
23 24
connector. 4.7KOhm 5% IDE_DIOW# 25
23 24
26 22Ohm
IDE_DIORDY 25 26
+3.3V_RUN
R270 2 1 27 27 28 28 1 R269 2 IDE_DDACK#
R263 2 1 IDE_IRQ 29 30
+3.3V_RUN IDE_DA1 29 30 PDIAG#
31 31 32 32
8.2KOhm 5% IDE_DA0 33 34 IDE_DA2
IDE_DCS1# 33 34 IDE_DCS3#
35 35 36 36
DASP# 37 38
37 38
39 39 40 40
IDE_DD[0:15] 41 42
SATA_RXN0_C 15 IDE_DD[0:15] 41 42
MLCC/+/-10% 2 1 3900PF/50V/X7R C319 43 44
SATA_RX0- 15 43 44
NP_NC3
NP_NC1
SATA_RXP0_C MLCC/+/-10% 2 1 3900PF/50V/X7R C318 IDE_DDREQ R244 45 46
SATA_RX0+ 15 15 IDE_DDREQ IDE_DIOW# CSEL2 45 46
15 IDE_DIOW# 2 1 47 47 48 48
IDE_DIOR# 49 50
15 IDE_DIOR# IDE_DIORDY 470Ohm 5% 49 50
15 IDE_DIORDY IDE_DDACK#
53
51
3 15 IDE_DDACK# IDE_IRQ 3
15 IDE_IRQ IDE_DA1
15 IDE_DA1 IDE_DA0
15 IDE_DA0 IDE_DCS1# SUYIN/800194MR050S520ZL
15 IDE_DCS1# IDE_DA2
15 IDE_DA2 IDE_DCS3#
15 IDE_DCS3#
+5V_ALW
+5V_MOD +5V_RUN
+5V_ALW
+5V_HDD
Q9 +5V_RUN Q41 R256

1 6 8 D S 1 1 2
2 D 5 R50 /* 7 2 0Ohm
C231
C266
3 S 4 1 2 6 3 pt_r0805_h24
MLCC/+/-10% C267
G 0Ohm 5 4 /*
0.01UF/25V/X7R
G
1
+5V_ALW2
pt_c0805_h57
pt_r0805_h24
10UF/10V/X5R
SI3456BDV-T1-E3
2
C57
1
pt_c0805_h57
R48 SI4800BDY
MLCC+/-10%
MLCC/+/-20%
10UF/10V/X5R
pt_c0603
100KOhm
1UF/16V/X5R
2
5%
MLCC/+/-20%
4 4
2
2
+5V_ALW2 +15V_ALW R249

1
100KOhm
5%
R241
1
+15V_ALW 2 1
2
R46
C240
R51 2 1 HDD_EN_5V 100KOhm 5%
pt_c0603
C45
100KOhm 100KOhm 5% 3
0.1UF/25V
D
1
5%
pt_c0603
3 Q44
0.1UF/25V
MLCC/+/-10%
D
1
1
1
Q11 G 2N7002
2
MLCC/+/-10%
1 2 S
G 2N7002 3
2
D
3 2 S
D
Q43
Q12 1
1 38 MODC_EN 2N7002
G
38 HDDC_EN 2 S
2
G 2N7002
2 S
2
R248
R58 100KOhm
100KOhm 5%
5%
1
1
5 5
PROJECT: Lanai 1.2 SHEET 31 OF 68 SATA(HDD & CD_ROM) RELEASE DATE :
A B C D E
A B C D E
+3.3V_R5C832
1
C258 C205 C206 C207 C208 C223 +3.3V_RUN +3.3V_R5C832
10UF/10V 0.01UF/16V 0.01UF/16V 0.01UF/16V 0.01UF/16V 0.01UF/16V
MLCC/+80-20% MLCC/+/-10% MLCC/+/-10% MLCC/+/-10% MLCC/+/-10% MLCC/+/-10%
2
Place these caps as close as pt_c0805_h53 1 2
1 1
R247 0Ohm 5% pt_r0603
possible to the device pins.
U31B +3.3V_R5C832
10 VCC_PCI3V_1 VCC_3V 67
20 VCC_PCI3V_2
1
27 VCC_PCI3V_3
32 C245 C255
VCC_PCI3V_4 0.01UF/16V 10UF/10V
41 VCC_PCI3V_5 MLCC/+/-10% MLCC/+80-20%
2
128 VCC_PCI3V_6 pt_c0805_h53
+3.3V_R5C832 61 VCC_RIN
1
1
16 VCC_ROUT1
C203 C244 C259 C211 34 VCC_ROUT2
1
10UF/10V 0.01UF/16V 0.01UF/16V 64
MLCC/+80-20% 0.1UF/10V MLCC/+/-10% MLCC/+/-10% C222 C216 C239 C204 VCC_ROUT3
2
2
MLCC/+80-20% 114 VCC_ROUT4
pt_c0805_h53 0.01UF/16V 0.01UF/16V 120
0.47UF/10V MLCC/+/-10% 0.47UF/10V MLCC/+/-10% VCC_ROUT5
2
MLCC/+/-10% MLCC/+/-10%
pt_c0603 pt_c0603 VCC_MD 86
2 2
GND1 4
GND2 13
PCI_AD31 125 22
PCI_AD30 AD31 GND3
126 AD30 GND4 28
PCI_AD29 127 54
PCI_AD28 AD29 GND5
1 AD28 GND6 62
PCI_AD27 2 63
PCI_AD26 AD27 GND7
3 AD26 GND8 68
PCI_AD25 5 118
PCI_AD24 AD25 GND9
6 AD24 GND10 122
PCI_AD23 9
PCI_AD22 AD23
11 AD22
PCI_AD21 12 99 +3.3V_R5C832
PCI_AD20 AD21 AGND1
14 AD20 AGND3 102
PCI_AD19 15 103
AD19 AGND2
2
PCI_AD18 17 107
PCI_AD17 AD18 AGND4 R488
16 PCI_AD[0..31] 18 AD17 AGND5 111
+3.3V_R5C832 PCI_AD16 19 10KOhm
PCI_AD15 AD16 5%
36 AD15
PCI_AD14 37 AD14
2
PCI_AD13
1
38 AD13
R238 PCI_AD12 39
PCI_AD11 AD12
100KOhm 40 AD11
PCI / OTHER
PCI_AD10 42 69
3 5% PCI_AD9 AD10 HWSPND# 3
43 AD9
PCI_AD8
1
44 AD8
PCI_AD7 46
PCI_AD6 AD7
47 AD6 MSEN 58 1 2 +3.3V_R5C832
Memory Stick Enable
PCI_AD5 48 R239 10KOhm 5%
PCI_AD4 AD5
49 AD4 XDEN 55
1
C238 PCI_AD3 50 XD Card Enable

1UF/10V/X7R PCI_AD2 AD3
51 AD2
MLCC/+/-10% PCI_AD1 52 57 2 1
PCI_AD0 AD1 UDIO5 +3.3V_R5C832 Serial ROM disable
pt_c0603 R236 100KOhm 5%
2
53 AD0
16 PCI_PAR 33 PAR
16 PCI_C_BE3# 7 C/BE3# UDIO3 65 SD Card Enable
16 PCI_C_BE2# 21 C/BE2# UDIO4 59
35 MMC Card Enable
16 PCI_C_BE1# C/BE1#
16 PCI_C_BE0# 45 C/BE0# UDIO2 56
PCI_AD17 1 2 R5C832_IDSEL 8
16 PCI_AD17 IDSEL
R207 100Ohm 5% 60
UDIO1
Pull-up 16 PCI_REQ1# 124 REQ#
16 PCI_GNT1# 123 72 IRQ_SERIRQ 17,37
resistors to 23
GNT# UDIO0/SRIRQ#
16 PCI_FRAME# FRAME#
+3.3V_RUN are 16 PCI_IRDY# 24 IRDY#
Pull-up resistors
16 PCI_TRDY# 25 to +3.3V_RUN are
required on 26
TRDY#
16 PCI_DEVSEL# DEVSEL# required on the ICH
the ICH 16 PCI_STOP# 29 STOP# INTA# 115 PCI_PIRQD# 16 1394 : INTA#
16 PCI_PERR# 30 schematics.
schematics. 31
PERR#
116
4 16 PCI_SERR# SERR# INTB# PCI_PIRQC# 16 4in1 : INTB# 4
Route to CLK GEN . 71 GBRST#

16 PCI_RST# 119 PCIRST#
21 CLK_PCI_PCCARD 121 PCICLK

Pull-up to R486 1 2 0Ohm 5% /* 70 66 1 T129
38 SYS_PME# PME# TEST
+3.3V_ALW R222
17,37 CLKRUN# 1 2 0Ohm 5% 117 CLKRUN#
is required on
2
SYS_PME# The ICH schematics need to
include a pull-up resistor R487
on SIO
2
100KOhm
1
R211 schematics. to implement CLKRUN#, and R5C833_TQFP128 5%

10Ohm the ICH schematics must R225 C.S R5C833 TQFP128
(From SIO).
1
5% 10KOhm
0 ohm of PME# have a pull-down, or
/* 5% No.24
constantly drive the
1
is no-stuff /*
Reserve for EMI
2
to prevent signal low, in order to

1
backdrive disable CLKRUN#.

C221 Ricoh R5C832 Package Type : TQFP-128-P1 (1414)
from this
10PF/50V
MLCC/+/-0.5PF signal
2
/* since the
5 5
controller
is powered of
the
RUN rail
PROJECT: Lanai 1.2 SHEET 32 OF 68 R5C833 - PCI INTERFACE RELEASE DATE :
A B C D E
A B C D E
For SD/MS Card Power

No.24 +3.3V_R5C832 +3.3V_RUN_CARD
U33
1
2 GND IN 5 1
3 OC#
MC_PWR_CTRL_0 4 1
+3.3V_RUN_CARD EN OUT
1
TPS2051BDBVR
C481 C472
0.1UF/10V 1UF/10V
Recommended Crystal Specs from Data Sheet:
2
+3.3V_RUN_PHY MLCC/+80-20% MLCC/+80%-20%
pt_c0603
2
1
1
Normal Frequency : 24.576 MHz U31A R456
C461 C459 C458 150KOhm
Frequency Tolerance : +/- 50ppm @ 25C 0.01UF/16V 0.01UF/16V 0.01UF/16V 5%
Driver Level : .1 mW MLCC/+/-10% MLCC/+/-10% MLCC/+/-10%
1
Load capacitance : 10pF AVCC_PHY3V_1 98
106 +3.3V_RUN_CARD
AVCC_PHY3V_2
Equ. Resistance : 50 Ohm Max AVCC_PHY3V_3 110 Place these components close to
Shunt Capacitance : 7.0pF Max No.25 AVCC_PHY3V_4 112 the flash memory card connector
CON20
TAISOL/144-2420000900
C478 2 1 1394_XI 113 TPBIAS0 41 18 SD/XD/MS_DATA1
TPBIAS0 TPBIAS0 34 XD_CDSW# XD_0(GND) MS_3(DATA1) SD/XD/MS_DATA0
40 XD_1(CD) MS_4(DATA0) 20
SD_WP#(XDR/B#) 39 22 SD/XD/MS_DATA2
15PF/50V SD/XD/MS_CLK XD_2(R/-B) MS_5(DATA2) MS_INS#
38 XD_3(-RE) MS_6(INS) 24
MLCC/+/-5% XD_CE# SD/XD/MS_DATA3
1
94 XI 37 XD_4(-CE) MS_7(DATA3) 26
2 X5 XD_CLE 36 28 SD/XD/MS_CLK 2
XD_ALE XD_5(CLE) MS_8(SCLK)
24.576Mhz 34 XD_6(ALE) MS_9(VCC) 30
SD/XD/MS_CMD
2
+/-50ppm/10PF 31 XD_7(-WE) MS_10(VSS) 32

104 TPB0N XD_WP# 27 33 SD/XD/MS_DATA3
TPBN0 TPB0N 34 XD_8(-WP) SD_1(DAT3) SD/XD/MS_CMD
23 XD_9(GND) SD_2(CMD) 29
C477 2 1 1394_XO 1 2 95 105 TPB0P SD/XD/MS_DATA0 19 25
XO TPBP0 TPB0P 34 SD/XD/MS_DATA1 XD_10(D0) SD_3(VSS)
R483 0Ohm 5% 15 21
SD/XD/MS_DATA2 XD_11(D1) SD_4(VDD) SD/XD/MS_CLK
No.24 12 XD_12(D2) SD_5(CLK) 17
15PF/50V SD/XD/MS_DATA3 11 13
MLCC/+/-5% XD_DATA4 XD_13(D3) SD_6(VSS) SD/XD/MS_DATA0
R5C832 : 0.01uF => stuff 9 XD_14(D4) SD_7(DAT0) 10
IEEE1394/SD
108 TPA0N +3.3V_RUN_CARD XD_DATA5 7 8 SD/XD/MS_DATA1
R5C833 : 0.01uF => No stuff TPAN0 TPA0N 34 XD_DATA6 XD_15(D5) SD_8(DAT1) SD/XD/MS_DATA2
6 XD_16(D6) SD_9(DAT2) 35
2 1 RICHO_FILO 96 109 TPA0P XD_DATA7 5 1
FIL0 TPAP0 TPA0P 34 XD_17(D7) SD(CD2/WP2/GND) SD_CD#
4 XD_18(VCC) SD(CD1) 2
P_GND1
P_GND2
NP_NC1
NP_NC2
C256 0.01UF/16V MLCC/+/-10% /* SD_WP# SD_WP#(XDR/B#)
S 2
D
14 MS_1(VSS) SD(WP1) 3
SD/XD/MS_CMD
3
16 MS_2(BS)
1
1 2 RICHO_REXT 101
G
REXT
1
C457 Q72
R474 10KOhm 1% 2.2UF/16V CARD_READER_41P 2N7002
42
43
44
45
2
MLCC/+/-10%
2 1 RICHO_VREF 100 pt_c0603 XD_CDSW#
VREF
C243 0.01UF/16V MLCC/+/-10%
No.47
Place as close to
3 R5C832 as possible. 3
87 XD_DATA7
MDIO17
92 XD_DATA6
MDIO16
89 XD_DATA5
MDIO15
91 XD_DATA4
MDIO14
90 SD/XD/MS_DATA3
MDIO13
93 SD/XD/MS_DATA2
MDIO12
81 SD/XD/MS_DATA1
MDIO11
82 SD/XD/MS_DATA0
MDIO10
75 XD_WP#
MDIO05
88 SD/XD/MS_CMD
MDIO08
83 XD_ALE
MDIO19
85 XD_CLE
MDIO18
4 4
78 XD_CE#
MDIO02
SD_CD#
77 SD_WP#(XDR/B#)
MDIO03 D20 1N4148W-7-F
MDIO00 80 1 2
D21 1N4148W-7-F XD_CDSW#

MDIO01 79 1 2
MS_INS#
MDIO09 84 1 2 SD/XD/MS_CLK
R484 0Ohm 5%
No.51
1
76 MC_PWR_CTRL_0
MDIO04 C552
74 MS_LED# TPC26T 1 T130
MDIO06 10PF/50V
2
MLCC/+/-0.5PF
97 RSV
MDIO07 73
R5C833_TQFP128
C.S R5C833 TQFP128
5 No.24 5
PROJECT: Lanai 1.2 SHEET 33 OF 68 R5C833 - FLASH MEMORY PART RELEASE DATE :
A B C D E
A B C D E
1 1
Place these caps as close to the R5C832 as possible.

L18
+3.3V_RUN_PHY 1 2 +3.3V_R5C832
MURATA/BLM15HD601SN1D
600Ohm/100MHz Irat=0.3A
1
C230 C257 C233 C235
1000PF/50V 10UF/10V 0.01UF/16V
MLCC/+80-20% 0.1UF/10V MLCC/+/-10%
2
MLCC/+/-10% MLCC/+80-20%
pt_c0603 pt_c0805_h53
2 2
Place as close as possible to 1394 connector.

Also, place 0 ohm close to the
chokes to minimize stubs
3 3
Common mode chokes should Place as close as possible to R5C832

be 110- ohms impedance.They 1 2
R375 0Ohm 5%
are reserved for EMI
LTPA0+
1
1
L31
2
C456 C453
LTPA0- 120OHM R454 R455
/* 0.01UF/16V 0.33UF/25V
56Ohm 56Ohm
4
2
MURATA/DLW21HN121SQ2L MLCC/+/-10% MLCC/+80%-20%
CON13 pt_c0603 1% 1%
FOXCONN/UV31413-WR56P-7F 1 2
6
R371 0Ohm 5% TPBIAS0
1
SIDE_G2
TPA0P TPBIAS0 33
TPXA1+ 4 TPA0P 33
3 TPA0N
TPXA1-
TPB0P TPA0N 33
TPXB1+ 2 TPB0P 33
1 TPB0N
SIDE_G1
TPXB1- TPB0N 33
1 2 2 1 1 2
IEEE_1394_CON_4P R377 0Ohm 5% R470 56Ohm 1% R458 5.1kOhm 1%
5
2 1 1394_TPB1_R 2 1
LTPB0+ R459 56Ohm 1% C464
4
270PF/50V MLCC/+/-10%
4
L32 4
LTPB0- 120OHM
/*
1
MURATA/DLW21HN121SQ2L
1394 pairs should be
routed as 110-ohm 1 2
R378 0Ohm 5%
differential
5 5
PROJECT: Lanai 1.2 SHEET 34 OF 68 R5C833 - IEEE1394 PART RELEASE DATE :
A B C D E
5 4 3 2 1
16 ICH_USBP6-
USBP6_D- +1.5V_CARD Express Card
3
L33
90OHM/100MHz USBP6_D+
16 ICH_USBP6+ /* +1.5V_CARD Max. 650mA, Average 500mA.
1
1
2
1 2
MURATA/DLW21SN900SQ2L C438 C440 +3V_CARD Max. 1300mA, Average 1000mA.
R404 0Ohm 5% 0.1UF/10V 0.1UF/10V
2
1 2 MLCC/+80-20% MLCC/+80-20%
R412 0Ohm 5%
+1.5V_RUN +3.3V_RUN +3.3V_SUS +3.3V_CARDAUX +3.3V_CARD +1.5V_CARD
D D
U28
17 AUX_IN AUX_OUT 15
2 3.3VIN_1 3.3VOUT_1 3
+3.3V_CARD Please the cap 4 5
3.3VIN_2 3.3VOUT_2 +3.3V_SUS
12 11
near connector. 14
1.5VIN_2 1.5VOUT_1
13
+3.3V_SUS R438 1.5VIN_1 1.5VOUT_2 CARD_RESET#
1 2 100KOhm 5%
1
1
20 SHDN# PERST# 8
C449 C446 C448 R433 1 2 0Ohm 5% /* 1 10 EXPRCRD_PWREN# R417 2 1 100KOhm 5%
10UF/10V CON8 38 EXPRCRD_STDBY# STBY# CPPE# CPUSB# R418
0.1UF/10V 0.1UF/10V 10,16,37 PLTRST# 6 SYSRST# CPUSB# 9 2 1 100KOhm 5%
MLCC/+80-20% JAE/PX10ABSB00G-1
2
2
MLCC/+80-20% MLCC/+80-20% OC# 19
pt_c0805_h53 1 1 P_GND1 29
USBP6_D- 2 2 NP_NC1 27 16 21
USBP6_D+ NC GND2
3 3 7 GND1 RCLKEN 18
CPUSB# 4 4
Please the cap 5 5 R5538D001_TR_F
6 6
near connector. 7 7
17,50 ICH_SMBCLK
17,50 ICH_SMBDATA 8 8
9 9
+1.5V_CARD 10 10
38,47,50 PCIE_WAKE# 11 11
+3.3V_CARDAUX 12 12
CARD_RESET# 13 13
+3.3V_CARD 14 14
15 15
21 CARD_CLK_REQ# 16 16
EXPRCRD_PWREN# 17 17
38 EXPRCRD_PWREN# +1.5V_RUN +3.3V_RUN +3.3V_SUS +3.3V_CARDAUX +3.3V_CARD +1.5V_CARD
21 CLK_PCIE_EXPCARD# 18 18
21 CLK_PCIE_EXPCARD 19 19
C C
20 20
16 PCIE_RX4- 21 21
1
16 PCIE_RX4+ 22 22
23 23 C437 C436 C444 C441 C432 C431
16 PCIE_TX4- 24 24 0.1UF/10V 0.1UF/10V 0.1UF/10V 0.1UF/10V 0.1UF/10V 0.1UF/10V
2
16 PCIE_TX4+ 25 25 NP_NC2 28 MLCC/+80-20% MLCC/+80-20% MLCC/+80-20% MLCC/+80-20% MLCC/+80-20% MLCC/+80-20%
26 26 P_GND2 30
EXPRESS_CARD_26P
PCI-Express TX and RX direct to connector .
Please the cap Please the cap Please the cap Please the cap Please the cap Please the cap
near pin 12 & near pin 2 & 4 near pin 17 near pin 15 near pin 3 & 5 near pin 11 &
14 (1.5VIN). (3.3VIN). (AUXIN). (AUXOUT). (3.3VOUT). 13 (1.5VOUT).
B B
A A
PROJECT: Lanai 1.2 SHEET 35 OF 68 PCI-Express Card RELEASE DATE : Terry_Lin
5 4 3 2 1
A B C D E
1 1
ICH_AZ_MDC_SDOUT
2
R243 /*
10Ohm
5%
1
1
C247
10PF/50V
2
MLCC/+/-0.5PF
/*
2
MDC 1
R245
2
2
0Ohm 5%
Q42
13
15
17
19
CON18 BSS138
/*
ICH_AZ_MDC_RST1#
2 S
D
GND1
GND3
GND5
NP_NC1
15 ICH_AZ_MDC_RST#
3
1 1 2 2
ICH_AZ_MDC_SDOUT 3 4 +5V_SUS
G
15 ICH_AZ_MDC_SDOUT 3 4
1
5 5 6 6 +3.3V_SUS
ICH_AZ_MDC_SYNC 7 8
15 ICH_AZ_MDC_SYNC 7 8
NP_NC2
MDC_SDIN 9 10
9 10
2
GND2
GND4
GND6
ICH_AZ_MDC_RST1# 11 12 ICH_AZ_MDC_BITCLK
11 12 ICH_AZ_MDC_BITCLK 15
2
R232
R240
14 10KOhm
16
18
20
MDC_CONN_12P 5% 100KOhm
TYCO/1-1775844-2 /* 5%
1
/*
1
43 MDC_RST_DIS#
Note: MDC DISABLE.
3 3
If platform requires MDC disable, populate this circuit.
If MDC disable isn't required, connect ICH_A2_MDC_RST# directly to JMDC connector.
ICH_AZ_MDC_BITCLK +3.3V_SUS
1 R246 MDC_SDIN
MLCC/+80-20%
15 ICH_AZ_MDC_SDIN1 2
33Ohm 5%
C248
C237
MLCC/+80-20%
2
1
R251 /*
0.1UF/10V
4.7UF/10V
10Ohm
pt_c0805_h53
2
2
5%
1
4 4
1
C251
10PF/50V
2
MLCC/+/-0.5PF
/*
Place these caps near

MDC module.
5 5
PROJECT: Lanai 1.2 SHEET 36 OF 68 MDC CONN RELEASE DATE :
A B C D E
5 4 3 2 1
(GPIO4) (GPIO5) CHIPSET
CHIPSET_ID1 CHIPSET_ID0 Common Boot block sequence
-------------------------------------------------------
R409 2.7KOhm 0 0 Intel-SR
1 2 5% SUS_ON Place cap close to pin 121. +3.3V_ALW
0 1 ATI-RR
R393 2.7KOhm 1 0 TBD +RTC_CELL
1 2 5% RUN_ON +RTC_CELL
1 1 Parker(Intel/ATI) U29 R430 0Ohm
1
R427 2.7KOhm /* 12 121 MEC5025_VCC0 1 2 C463 C423 C442 C443 C462
AC_OFF 21 CKG_SMBDAT KSO17/GPIOA1/AB1H_DATA VCC0
1 2 5% 21 CKG_SMBCLK 13 KSO16/GPIOA0/AB1H_CLK
5% pt_r0603 0.1UF/10V 0.1UF/10V 0.1UF/10V 0.1UF/10V
2
CHIPSET_ID0 14 21 C439 10UF/6.3V MLCC/+/-10% MLCC/+/-10% MLCC/+/-10% MLCC/+/-10%
CHIPSET_ID1 GPIO5/KSO15 VCC1_1 +3.3V_ALW
R428 MLCC/+/-20%
2
15 GPIO4/KSO14 VCC1_2 44
16 POWER PLANES 65 0.1UF/10V pt_c0805_h53
58 1.8V_SUS_PWRGD KSO13/GPIO18 VCC1_3 100KOhm
MLCC/+/-10%
2
7 EC_CPU_PROCHOT# 17 KSO12/OUT8 VCC1_4 83 5%
18 KSO11/GPIOC7 116
VCC1_5
Place these caps close to MEC5025
1
19
Non 10,17 ICH_CL_PWROK
TPC26T T28 1 20
KSO10/GPIOC6
KSO9/GPIOC5
ICH_RSMRST# ALWON
D
iAMT 17 ICH_RSMRST# 23 KSO8/GPIOC4 ALWON 120 ALWON 54 D
1
24 119 C422
+5V_RUN KSO7/GPIO3 POWER_SW_IN2#/GPIO23 SNIFFER_PWR_SW# 42
25 KSO6/GPIO2 POWER_SW_IN1#/GPIO22 126 INSTANT_ON_SW# R431 1 2 INSTANT_POWER_SW# 41
1UF/10V
27 KEYBOARD/MOUSE 127 10KOhm 5% MLCC/+/-10%
CLK_KBD 58 DDR_ON KSO5/GPIO1 POWER_SW_IN0# MAIN_PWR_SW# 42
RN39A pt_c0603
2
1 4.7KOhm2 41 TP_DET# 28 KSO4/GPIO0 ACAV_IN 128 ACAV_IN 43,57
3 RN39B DAT_KBD POWER SWITCH +5V_ALW
4.7KOhm4 CLK_DOCK 54 ALW_PWRGD_3V_5V 29 KSO3/GPIOC3 BGPO0/GPIOA5
118
SNIFFER_RTC_GPO
5 RN39C T34 TPC26T
4.7KOhm6 DAT_DOCK 17 SIO_SLP_S3# 30 KSO2/GPIOC2 1
7 RN39D R402 8.2KOhm
4.7KOhm8 17 SIO_SLP_S5# 31 KSO1/GPIOC1 LCD_SMBCLK DOCK_SMBCLK
49 3.3V_RUN_ON 32 KSO0/GPIOC0 AB1B_CLK/GPIOA4 8 LCD_SMBCLK 28 2 1
TPC26T T118 1 AUX_ON 7 LCD_SMBDAT 5%
SUS_ON ACCESS BUS AB1B_DATA/GPIOA2 DOCK_SMBCLK LCD_SMBDAT 28
33 6 1 T29 TPC26T R387 8.2KOhm
49,51 SUS_ON KSI7/GPIO19 AB1A_CLK DOCK_SMBDAT DOCK_SMBDAT
RUN_ON 34 5 1 T116 TPC26T 2 1
28,49,51,54 RUN_ON KSI6/GPIO17 AB1A_DATA
35 5%
+3.3V_ALW 59 AC_OFF KSI5/GPIO10
36 93
Non 37
KSI4/GPIO9
KSI3/GPIO8
GPIO11/AB2_DATA
GPIO12/AB2_CLK 94 LCDVCC_TST_EN 1.8V_RUN_ON 49
LCDVCC_TST_EN 28
+3.3V_ALW
iAMT 41
41 BC_A_INT#
BC_A_DAT
38
39
KSI2/GPIO7/BC_A_INT#
KSI1/GPIO6/BC_A_DAT
GPIO13/AB1G_DATA
GPIO14/AB1G_CLK
95
96
1
1
T41 TPC26T
T40 TPC26T R406 8.2KOhm
40 111 PBAT_SMBDAT LCD_SMBCLK 2 1
41 BC_A_CLK KSI0/SGPIO30/BC_A_CLK GPIO87/AB1C_DATA PBAT_SMBCLK PBAT_SMBDAT 57,59
112 5%
GPIO86/AB1C_CLK PBAT_SMBCLK 57,59
1
R444 R441 R465 R466 92 9 SBAT_DH_SMBDAT R388 8.2KOhm

15 SIO_A20GATE SNIFFER_GREEN# SGPIO34/A20M GPIO85/AB1D_DATA SBAT_DH_SMBCLK
50 10 LCD_SMBDAT 2 1
42 SNIFFER_GREEN# OUT5/KBRST GPIO84/AB1D_CLK
97 5%
GPIO93/AB1F_DATA 1.5V_RUN_ON 55
75 98 R440 2.2KOhm
41 CLK_TP_SIO GPIO94/IMCLK GPIO92/AB1F_CLK THRM_SMBDAT 1.25V_RUN_ON 58 PBAT_SMBDAT
41 DAT_TP_SIO 76 GPIO95/IMDAT 99 THRM_SMBDAT 43 2 1
100KOhm100KOhm100KOhm100KOhm TPC26T T128 CLK_KBD GPIO91/AB1E_DATA THRM_SMBCLK 5%
2
1 77 KCLK GPIO90/AB1E_CLK 100 THRM_SMBCLK 43

5% 5% 5% 5% TPC26T T126 1 DAT_KBD 78 R435 2.2KOhm
/* /* CLK_DOCK KDAT PBAT_SMBCLK
79 GPIOA6/EMCLK GPIO82/FAN_TACH3 43 IMVP_PWRGD 17,51,53 2 1
AUX_LCD_CBL_DET# DAT_DOCK 80 42 R432 2 1 5%
8051_RX GPIOA7/EMDAT GPIO16/FAN_TACH2 +3.3V_RUN
INVERTER_CBL_DET# 81 41 2.2KOhm 5% /*
SNIFFER_GREEN# 50 8051_RX 8051_TX GPIO20/PS2CLK/8051RX GPIO15/FAN_TACH1 FAN1_TACH 43
50 8051_TX 82 GPIO21/PS2DAT/8051TX
SNIFFER_YELLOW# 48 Pin 1
OUT2/PWM3 AUX_EN_WOWL_1 IMVP_VR_ON 53
47 R445 2 1 0Ohm 5%
OUT9/PWM2 3.3V_SUS_ON AUX_EN_WOWL 50
10,16,35 PLTRST# 57 LRESET# OUT11/PWM1 46 3.3V_SUS_ON 49 Pin 3
CLK_PCI_5025 58 45
21 CLK_PCI_5025 PCICLK OUT10/PWM0 BREATH_LED# 42
15 LPC_LFRAME# 59 LFRAME# SIO_EXT_SCI#
CLK_PCI_5025 15 LPC_LAD0 60 LAD0 PCI POWER/LPC BUS nEC_SCI/SPDIN2 66 SIO_EXT_SCI# 17 MLX_53398-0371
15 LPC_LAD1 61 LAD1 SGPIO45/MSDATA/SPDOUT2 55 PS_ID 59
15 LPC_LAD2 62 LAD2 54 SIO_RCIN# 15
SGPIO44/MSCLK/SPCLK2 +3.3V_ALW
15 LPC_LAD3 63 LAD3 SGPIO46/SPDIN1 69 BEEP 44
2
C
Place close to 64 68 1 T125 TPC26T C
17,32 CLKRUN#
5
R450 CLKRUN# SGPIO47/SPDOUT1 DEBUG_ENABLE#
17,32 IRQ_SERIRQ 56 67
pin 58 SER_IRQ SGPIO31/TIN1/SPCLK1 HOLD2
3 CON2
GPIO HOST_DEBUG_TX 50
10Ohm 70 2
5% /* SYSOPT0/SGPIO32/LPC_TX WTOB_CON_3P
16 ICH_EC_SPI_CLK 102 71 1
HSTCLK SYSOPT1/SGPIO33/LPC_RX R464 /*
1 1MOhm
1
HOLD1
16 ICH_EC_SPI_DIN 105 HSTDATAIN 2 +3.3V_ALW HOST_DEBUG_RX 50
4
107 91 LCD_CBL_DET 5%
16 ICH_EC_SPI_DO
1
C447 HSTDATAOUT SGPIO40 INVERTER_CBL_DET# RN38A RN38B
4
SGPIO41 90 INVERTER_CBL_DET# 28
103 89 AUX_LCD_CBL_DET#
40 EC_FLASH_SPI_CLK FLCLK HOST/8051 SPI SGPIO42 SIO_SPI_CS# AUX_LCD_CBL_DET# 28
4.7PF/50V 106 4 4.7KOhm 4.7KOhm
40 EC_FLASH_SPI_DIN FLDATAIN SGPIO43 SIO_SPI_CS# 16
/* 5% 5%
2
40 EC_FLASH_SPI_DO 108 FLDATAOUT

MLCC/+/-0.25PF 1 LOM_SMB_ALERT# pt_2r4p0402_h18 pt_2r4p0402_h18
SGPIO35 SFPI_EN LOM_SMB_ALERT# 17
3
17 SIO_PWRBTN# 109 GPIO80 SGPIO36(SFPI_EN) 2
SNIFFER_YELLOW# 110 3 DOCK_SMB_ALERT#
42 SNIFFER_YELLOW# GPIO81 SGPIO37
GPIO96/TOUT1 52 0.9V_DDR_VTT_ON 58
87 11 THRM_SMBCLK
38 BC_CLK BC_CLK OUT7/nSMI SIO_EXT_SMI# 17
86 THRM_SMBDAT
38 BC_DAT BC_DAT BC
38 BC_INT# 85 BC_INT#
nPWR_LED 115 BAT2_LED# 42
MISCELLANEOUS No.33
32KHz Clock MEC5025_XTAL1 nBAT_LED 114
FWP# BAT1_LED# 42
R549 0Ohm 5%
122 XTAL1 nFWP 84
MEC5025_XTAL2 MEC5025_XTAL2 124 CLOCK 73 1 T136 TPC26T 2 1
MEC5025_XOSEL XTAL2 GPIOA3/WINDMON EC_PWM_2 54
R429 1 2 10KOhm 123 117 2 1 EC_32KHZ 38
2
5% XOSEL GPIO83/32KHZ_OUT R550 0Ohm 5% +3.3V_ALW

PWRGD 49 RUNPWROK 51,53
R426 53
nRESET_OUT/OUT6 RESET_OUT# 51
C419 2 1 4.7UF/10V VR_CAP 22 VR_CAP TEST_PIN 72 MEC_TEST_PIN 1 T127 TPC26T 1 = Enabled.
0Ohm X4 No.25 pt_c0805_h37 MLCC/+/-10%
0 = Disabled
1
5% 2 1 MEC_AGND 125 AGND
1
32.768KHZ L35 Populate R391
1
VSS1 113
+/-10ppm/6PF 120Ohm/100Mhz 104 88 R467
MEC5025_XTAL2_R 4 MEC_VCC_PLL VCC_PLL POWER PLANES VSS2 for flash
1 MEC5025_XTAL1 +3.3V_ALW 1 2 74 0Ohm 1KOhm
L36 VSS3 5% corruption 5% /*
51
1
120Ohm/100Mhz C455 VSS4
2
101 26 issue.
1
VSS_PLL VSS5 SFPI_EN
2
C434 C433 0.1UF/10V
3
MEC5025-NU
MLCC/+/-10%
2
1
12PF/50V 15PF/50V
2
1 2
MLCC/+/-5% MLCC/+/-5% L37 R386
Flash Recovery
120Ohm/100Mhz
B 1KOhm B
5%
2
For MEC5025 Rev. C : C4519= 22uF and
External Work Around populate workaround circuit.
Circuit. For MEC5025 Rev. D : C4519= 4.7uF and
+3.3V_ALW
depopulate workaround circuit. +3.3V_ALW
1
Low=
2
R452
R413 R416
Write Protected.
100KOhm
100KOhm 10KOhm 5%
5% /* 5% /* C425
2
4.7UF/6.3V /* FWP#
1
2 1
pt_c0603 MLCC/+/-10%
1
Flash Write
D18 Q56 2 R453
R410 E Protect bottom
ALWON 2 1 2 1 R390 0Ohm 4K of internal 100KOhm
B 1
2 1 VR_CAP Debug Serial Port bootblock flash 5% /*
10KOhm
C
5% /* Pin 1 +3.3V_ALW
2
RB500V-40 5% /* PMBS3906
3 Flash Recovery
/* /* 3
D
Port.
Q55
Pin 5 +3.3V_ALW
1
28 LCD_CBL_DET_R
2
1
G
2 S 2N7002 R64 R73 R65 LOM_SMB_ALERT# R405 100KOhm 5% R461
MLX_53398-0571 DOCK_SMB_ALERT#R403
1 2
1 2 10KOhm 5%
R439 /* 1MOhm 10KOhm 10KOhm SIO_SPI_CS# R392 10KOhm 5% /* 100KOhm
A 1 2 5% A
2 1 CON4 5% 5% 5% SBAT_DH_SMBDAT R389 1 2 10KOhm 5%
SBAT_DH_SMBCLK R407 10KOhm 5%
1
2
7 SIDE2 5 5 1 2
100KOhm 4 8051_RX TP_DET# R408 1 2 100KOhm5% LCD_CBL_DET
5% /* 4 8051_TX BC_DAT R471 100KOhm5%
3 3 1 2
2 BC_A_DAT R434 1 2 100KOhm5% /*
2
2
6 SIDE1 1 1
R66 0Ohm No.18 DDR_ON R553 1 2 100KOhm 5% R460
1 2 DEBUG_ENABLE# ICH_RSMRST# R394 2 1 100KOhm 5%
WTOB_CON_5P /* 5% CHIPSET_ID0 R411 200KOhm
1 2 0Ohm 5%
/* CHIPSET_ID1 R554 5%
No.36 1 2 0Ohm 5% /*
Not Stuff 0 ohm when doing
1
Flash recovery.
PROJECT: Lanai 1.2 SHEET 37 OF 68 MEC5025 RELEASE DATE : STANLY_HSU
5 4 3 2 1
5 4 3 2 1
2 10kOhm 1 RN40A
+3.3V_ALW SYS_PME#
4 10kOhm 3 RN40B
6 10kOhm 5 RN40C PCIE_WAKE#
8 7 RN40D
10kOhm +3.3V_ALW
No.16
+5V_ALW
R545 1 2 10KOhm 5% DOCK_SMB_PME#
U34
D
VSS7 37 D
59 PBAT_PRES# 97 GPIOA[0] VSS8 56
SBAT_PRES# 98 39
T82 GPIOA[1] VSS9
Discrete 1 99 GPIOA[2]
+3.3V_ALW
Board ID Straps 100 GPIOA[3]
101 GPIOA[4] VSS10 54
SYS_PME# 102 52
32 SYS_PME# PCIE_WAKE# GPIOA[5] VSS11
35,47,50 PCIE_WAKE# 103 GPIOA[6] VSS12 49
50 USB_BACK_EN# 104 GPIOA[7] VSS13 47
No.30 42
1
1
VCC1_6
VSS14 41
R478 R476 R473 R469 BID2 112 46
VGA_IDENTIFY GPIOF[4] NC
111 GPIOF[5] VSS15 44
110 GPIOF[6]
10KOhm 10KOhm 10KOhm 10KOhm 109
5% 5% /* 5% 5% GPIOF[7]
2
2
VSS16 55
/* /* BID0 53
BID1 LOM_LOW_PWR VSS17
47 LOM_LOW_PWR 88 GPIOG[0] VSS18 50
BID2 SC_DET# 89 48
VGA_IDENTIFY GPIOG[1] VSS19
15,41 LED_MASK# 90 GPIOG[2] VCC1_7 43
T83 1 91 38
R516 2 GPIOG[3] VSS20
17 SIO_EXT_WAKE# 1 0Ohm 92 GPIOG[4] VSS21 45
1
5% 93 40
16 ICH_PME# GPIOG[5] VSS22
R477 R475 R472 R468 94
17 ICH_PCIE_WAKE# GPIOG[6]
50 WLAN_RADIO_DIS# 95 GPIOG[7]
BC_CLK 60 BC_CLK 37
10KOhm 10KOhm 10KOhm 10KOhm 59
BC_DAT BC_DAT 37
5% 5% 5% 5%
2
35 EXPRCRD_PWREN# 26 GPIOH[4] BC_INT# 58 BC_INT# 37

35 EXPRCRD_STDBY# 27 GPIOH[5]
UMA IMVP6_PROCHOT# 32
53 IMVP6_PROCHOT# GPIOH[6]
VGA_IDENTIFY 51 5V_3V_1.8V_1.25V_RUN_PWRGD 33 GPIOH[7] GPIOB[0] 65 USB_SIDE_EN# 39
66 PWRUSB_OC#
1 = Discrete Gfx. GPIOB[1]
82
GPIOB[2] HP_NB_SENSE
0 = UMA R514 R479 , ECE5011 is suff , 28 LCD_TST 105 OUT65 GPIOB[3] 81
GPIOB[4] 80
BID2 BID1 BID0 M08 M08B ECE5021 is not stuff GPIOB[5] 79
R479 2 1 10KOhm 5% RBIAS 127 78
0 0 0 ENG1(X00) ENG1(X00) R514 GPIOJ[0] GPIOB[6]
+3.3V_ALW 2 1 10KOhm 5% 126 GPIOI[7] GPIOB[7] 77 NB_MUTE# 45,46
0 0 1 ENG2(X01) ENG2(X01) /*
C /* C
0 1 0 ENG3(X02) ENG3(X02) ECE5011_XTAL2 122 76 DOCK_SMB_PME#
GPIOI[3] GPIOC[0]
0 1 1 ENG4(X03) ENG4(X03) Note : for ECE5011 only 1 R481 2 10KOhm ECE5011_XTAL1 123 GPIOI[4] GPIOC[1] 75 DOCKED
5% 67
ECE5021 will be non_stuff GPIOC[2]
1 0 0 QT(X04) QT(X04) GPIOC[3] 68
T58 1 9 69
1 0 1 RAMP(A00) RAMP(A00) T53 1 10
GPIOJ[2] GPIOC[4]
70
ADAPT_OC 57
GPIOJ[3] GPIOC[5] ADAPT_TRIP_SEL 57
1 1 0 T50 1 13 71
GPIOJ[6] GPIOC[6] XDP_DBRESET# 7,17,52
T67 1 12 73
GPIOJ[5] GPIOC[7] PS_ID_DISABLE# 59
T70 1 15
T62 GPIOK[0]
1 16 GPIOK[1] PANEL_BKEN 10
T52 1 19 74 R522 100KOhm
T47 GPIOK[3] GPIOD[0] 5%
1 18 GPIOK[2] 2 1
T63 1 21 GPIOK[5]
24MHz Clock T51 1 22 GPIOK[6] GPIOE[0] 1 M_LED_BK# 42
ECE5011_XTAL1 GPIOE[1] 2 No.13
GPIOE[2] 3
T74 1 63 4
R482 R485 MODPRES# GPIOD[3] GPIOE[3]
28 GPIOD[4] GPIOE[4] 5
1 2 /* 2 1 ECE5011_XTAL2 DBAY_MODPRES# 29 84
GPIOD[5] GPIOE[5]
31 HDDC_EN 30 GPIOD[6] GPIOE[6] 83
1MOhm 5% 0Ohm 5% R462 R489 R480 , ECE5011 is 31 6
/* 31 MODC_EN GPIOD[7] GPIOE[7]
X6
suff , ECE5021 is not stuff
ECE5011_XTAL1_R 1 2 ECE5011_XTAL2_R EC_VDDA R462 2 1 5% 125 113
GPIOI[6] CIRTX
0Ohm 8 114 FREE_CIRRX 41
VCC1_1 CIRRX
1
C470 R489 2 1 5% 14 61
GPIOJ[7] GPIOD[1]/CIRTX LID_CL_SIO# 42
24Mhz C474 C471 R480 2 /*
0Ohm 1 5% 20 62
1
C476 C495 GPIOK[4] GPIOD[2]/CIRRX 1.05V_RUN_ON 55

/* 0.1UF/10V R504 2 0Ohm 1 5% 11 118
4.7UF/6.3V MLCC/+80-20% 4.7UF/6.3V GPIOJ[4] GPIOF[0]
2
/*
0Ohm 17 117 ATF_INT# 43
30PF/50V 30PF/50V pt_c0603 pt_c0603 VSS1 GPIOF[1] BID0
R505 2 /* 1 5% 23 116
MLCC/+/-5% MLCC/+/-5% MLCC/+/-10% MLCC/+/-10% GPIOK[7] GPIOF[2] BID1
2
/*
0Ohm 36 115
/* /* /* VSS2 GPIOF[3]
51 VSS3
/* 72 VSS4
Crystal and surrounding 87 VSS5 GPIOH[0] 24 WIRELESS_ON/OFF# 42
EC_32KHZ 96 25
components not needed unless R504 R505 R463 , ECE5011 is 37 EC_32KHZ
121
KHz_32 GPIOH[1]
106
BT_RADIO_DIS# 41
VSS6 GPIOH[2] LOM_CABLE_DETECT WWAN_RADIO_DIS# 50
SIO USB Hub is utilized suff , ECE5021 is not stuff R463 2 1 5% 128 GPIOJ[1] GPIOH[3] 107 1
0Ohm 34 T77
B +3.3V_ALW VCC1_2 B
57 VCC1_3
/* 85 64
VCC1_4 VSS23
108 VCC1_5
+3.3V_ALW R498 R493 R506, ECE5011 is R498 2 1 5% 119 GPIOI[1]
suff , ECE5021 is not stuff 0Ohm Reserved for Broadcom
L38
LOM solution
R493 2 /* 1 5% 120
EC_VDDA GPIOI[2]
1 2 180Ohm 0Ohm 86 CAP_LDO
R506 2 1 5% 124 35 RSV_TEST_PIN 1
GPIOI[5] TEST_PIN
1
BLM18PG181SN1 C468 C466 C467 /*

0Ohm 7 T68
pt_l0603 PWRGD_PS
1
1
0.1UF/10V 0.1UF/10V 0.1UF/10V C482 C486 C509 /* ECE5021-NU
MLCC/+/-10% MLCC/+/-10% MLCC/+/-10% C525 C505
2
4.7UF/6.3V 0.1UF/10V 4.7UF/6.3V 4.7UF/6.3V 0.1UF/10V

MLCC/+/-10% MLCC/+80-20% MLCC/+/-10% MLCC/+/-10% MLCC/+80-20% No.46
2
2
pt_c0603 /* pt_c0603 pt_c0603 /*
/* /*
1
C487 C484 C524 C492 C497 C479 C501

+3.3V_ALW
0.1UF/10V 0.1UF/10V 0.1UF/10V 0.1UF/10V 0.1UF/10V 0.1UF/10V 0.1UF/10V
MLCC/+/-10% MLCC/+/-10% MLCC/+/-10% MLCC/+/-10% MLCC/+/-10% MLCC/+/-10% MLCC/+/-10%
2
SBAT_PRES# R513 1 2 10KOhm 5%

Place these caps near ECE5011 PWRUSB_OC# R515 1 2 10KOhm 5%
MODPRES# R500 1 2 100KOhm5%
SC_DET# R523 1 2 10KOhm 5% /*
DBAY_MODPRES# R501 1 2 10KOhm 5%
+3.3V_RUN
LOM_CABLE_DETECT R499 1 2 10KOhm 5%

IMVP6_PROCHOT# R494 1 2 100KOhm 5%
DOCKED R524 1 2 100KOhm 5%
HP_NB_SENSE R512 1 2 100KOhm 5%
A A
LCD_TST R503 1 2 100KOhm 5%
PROJECT: Lanai 1.2 SHEET 38 OF 68 SUPER IO ECE5011 RELEASE DATE :
STANLY_HSU
5 4 3 2 1
A B C D E
1 1
No.55
+5V_ALW
USB daughter board connector
2 F1 2
1 2 Place one 150uF cap by each
/* USB connector CON17
1.6A/6V
POLYSWITCH SMD1812P160TF SUYIN/127153MA010G521ZR
J1 11
U27 ICH_USBP1- NP_NC1 +USB_SIDE_PWR
16 ICH_USBP1- 1 1 2 2
1 1 2 2 2 IN 1 ICH_USBP1+ 3 4
GND 16 ICH_USBP1+ 3 4
5 5 6 6
2MM_OPEN_5mil ICH_USBP0- 7 8
+USB_SIDE_PWR 16 ICH_USBP0- ICH_USBP0+ 7 8
38 USB_SIDE_EN# 3 EN1# OUT1 7 16 ICH_USBP0+ 9 9 10 10
OC1# 8 USB_OC0_1# 16 NP_NC2 12
1
C417 C416 4 6 +USB_SIDE_PWR BTOB_CON_10P
EN2# OUT2
0.1UF/10V 10UF/10V OC2# 5
2
MLCC/+/-10% MLCC/+/-10%
/* TPS2062DR
pt_c1206_h75
3 3
Each channel is 1A
4 4
5 5
PROJECT: Lanai 1.2 SHEET 39 OF 68 USB PORT x 2 RELEASE DATE : Terry_Lin
A B C D E
A B C D E
1 1
RTC BATTERY
Layout Note: +3.3V_SUS
Place R449 within 500 mils from +RTC_CELL +3.3V_RTC_LDO +PWR_SRC
SPI flash. Place R449 & R451 U26
D17
C411 /*
within 500 mils of the MEC5025. 1 IN SHDN# 5
2 GND
pt_c0805_h57
1UF/25V
MLCC/+/-10%
2 1 3 OUT 5/3# 4
1
1
C408
MAX1615EUK
2.2UF/6.3V/X5R
R457 RB751V_40 /*
MLCC/+/-10%
1
1
pt_c0603
2
R437 10KOhm
5%
10KOhm
2
5% U30
2
16 SPI_CS0# 1 CE# VDD 8
D19
2 SO HOLD# 7
3 6 SPI_CLK R449 1 2 15Ohm
WP# SCK EC_FLASH_SPI_CLK 37
1
4 5 SPI_SI R451 1 2 15Ohm C460 2 1 +RTC_1 2 1 +RTC
VSS SI EC_FLASH_SPI_DO 37
C421
2 R447 15Ohm5% CON16 2
4
SPI_DO
pt_c0805_h57
0.1UF/10V R421
MLCC/+/-10%
37 EC_FLASH_SPI_DIN 1 2 SST25VF016B
1
MLCC/+80-20% RB751V_40 1KOhm HOLD1
1UF/25V
2
1
5% 2 WTOB_CON_3P
15 RTC_BAT_DET# 3
MOLEX/53398-0371(P6497)
2
HOLD2
5
3 3
Pin 1
Pin 3
MLX_53398-0371
4 4
5 5
PROJECT: Lanai 1.2 SHEET 40 OF 68 FLASH & RTC RELEASE DATE : C.L. Ho
A B C D E
5 4 3 2 1
+3.3V_ALW
RN15B
RN15A
Touch Pad
4
2
4.7KOhm
4.7KOhm
CON5
MOLEX/48227-1511
D WTOB_CON_15P D
3
1
16
1
SIDE1
L15 600Ohm Irat=200mA 37 TP_DET#
pt_l0603 1
37 DAT_TP_SIO 2 1 2 2
L12 2 1 600Ohm Irat=200mA pt_l0603 3
37 CLK_TP_SIO 3
4 4
42 MEDIA_LED_R 5 5
42,43 POWER_SW# 6 6
pt_c_array_8p_79x49_h39
37 INSTANT_POWER_SW# 7 7
Lid Switch(Hall) BIO No.17 +3.3V_ALW 8 8
+5V_ALW 9 9
8
6
4
2
37 BC_A_DAT 10 10
+3.3V_ALW +5V_ALW
7 10PF/50V
5 10PF/50V
3 10PF/50V
1 10PF/50V
No.17 11 11
37 BC_A_CLK 12 12
37 BC_A_INT# 13 13
SIDE2
/*
/*
/*
/*
/*
14 14
15 15 Please refer to item 191 of issue_list_0517_TDC ,
CN2D
CN2C
CN2B
CN2A
22PF/50V MLCC/+/-5%
22PF/50V MLCC/+/-5%
22PF/50V MLCC/+/-5%
MLCC/+/-5%
MLCC/+/-5%
MLCC/+/-5%
MLCC/+/-5%
MLCC/+/-5%
"Lanai plan to use 3V TP controller. No need
1
1
C114 C112
17
0.1UF/10V TP_VCC " . So we delete this circuit which
0.1UF/10V MLCC/+80-20%
MLCC/+/-10% supply TP_VCC power.
2
2
No.20
22PF/50V
22PF/50V
22PF/50V
22PF/50V
22PF/50V
1
1
2
2
C544
C545
C546
C547
C548
C549
C550
C551
C C
This circuit is only needed if

the platform has the SNIFFER. BT_ACTIVE#_R 42
No.22 No.42 3
D
Q62
2 1 BT_ACTIVE 1
R528 10KOhm 5% G BSS138N
2 S
Q63
Bluetooth 2
E
MMBT3906LT1G
+3.3V_RUN
1 B LED_MASK# 15,38
C
3
CON21
MOLEX/48226-1011
11
WTOB_CON_10P
1 1 2
SIDE2 SIDE1
2
3 3 4 4 COEX2_WLAN_ACTIVE 50
38 BT_RADIO_DIS# 5 5 6 6 COEX1_BT_ACTIVE 50
T132 1 7 7 8
8 ICH_USBP7- 16
16 ICH_USBP7+ 9 9 10 10
12
1
1
C512 C523 R527 R526
B C518 B
0.1UF/10V 100PF/50V 10KOhm 10KOhm
2
MLCC/+80-20% MLCC/+/-5% 5% 5% 33PF/50V
2
MLCC/+/-5%
1
Vendor suggest : +3.3V_RUN
Pin 7 of RC-Rxd is
open collector
HALL SENSOR
CIR
2
+3.3V_RUN +3.3V_ALW output.it should be +3.3V_ALW

add external pullup R534
10KOhm
2
resister 5%
CON6
R296 R300 MOLEX/48227-0311
/*
1
0Ohm 0Ohm 1 1 SIDE1 4

5% 5%
/* U39 2
42 LID_CL# 2
1
38 FREE_CIRRX 4 OUT
+3.3V_CIR 1 2 3 3 5
R301 100Ohm 5% VS 3 SIDE2
2 GND2
A WTOB_CON_3P A
1 GND1
1
C536 C302
0.1UF/16V 4.7UF/10V TSOP36136TR
MLCC/+/-10% MLCC/+/-10%
pt_c1206_h71
2
PROJECT: Lanai 1.2 SHEET 41 OF 68 TOUCH PAD & BT & CIR & LID
RELEASE DATE :
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN HDD_LED#
HDD activity LED Sniffer Switch
Q39 3 Battery status CON22
1
Q38 C SNIFFER1
R1 1 1 GND1 5
R166 1 2 B +3.3V_ALW 2 7
100KOhm 5% GND BAT1_LED_BLUE# 2 NP_NC1
3 3 NP_NC2 8
/* E SNIFFER2 4 6
R2 R2 Q46 4 GND2
R175 0Ohm 5% SLIDE_SWITCH_4P
2
1
FOXCONN/1BS008-13130-042-7F
GND
15 SATA_ACT#_R 2 1 2
pt_r0603 IN
R1 3 HDD_LED DTC114EKA 1 Q68 3
OUT R2
R1 C
D DDTA114YUA_7_F 2 B +3.3V_RUN D
37 BAT1_LED# 2
1
IN
R1 3 BAT1_LED E
OUT R2 R533
+3.3V_RUN BT_LED# DDTA114YUA_7_F 100KOhm 5%
BT activity LED pt_r0603
DTC114EKA 1
Q65 R531 0Ohm 5%
2
1 Q64 3 2 1 SNIFFER1
GND 38 WIRELESS_ON/OFF#
R1 C
2 B
1
R2 +3.3V_ALW C534
E 1UF/10V
2 R2 MLCC/+/-10%
41 BT_ACTIVE#_R BT_LED pt_c0603
IN
2
R1 3 OUT Q47
/*
DDTA114YUA_7_F DTC114EKA 1 1 GND
R2
BREATH_PWRLED# 2 +RTC_CELL
37 BAT2_LED# IN BAT2_LED
Power&Suspend R1 3 OUT
1
Q69 3 DDTA114YUA_7_F
C R425
+3.3V_SUS 1 B 100KOhm 5%
U17 E
PMBS3904 2 R415 0Ohm 5%
2
1 NC VCC 5 2 1 SNIFFER2
37 SNIFFER_PWR_SW#
2 A R297 10KOhm
C 37 BREATH_LED# Y 4 BREATH_PWRLED 1 C
3 GND 5% 2
1
C430
1UF/10V
1
74AHC1G04GW C537 MLCC/+/-10%
1UF/10V pt_c0603
2
MLCC/+/-10% /*
pt_c0603
2
No.8
+3.3V_WLAN +3.3V_RUN
Hall Switch
WLAN
LED_WLAN_OUT_R# +3.3V_ALW
Sniffer LED driver circuit
2
R541
1
R134
+3.3V_SUS +3.3V_SUS 10KOhm 100KOhm
5% 2 Q29 3 5%
R542 Q27
1
E
R1 C
Q67 Q66 2 B
50 LED_WLAN_OUT# 2 1 MMBT3906LT1G R135 10Ohm
2
B 1
1 1 C
10KOhm 5% 5% 2
GND GND
3 E 38 LID_CL_SIO# 1 LID_CL# 41
R2
R2 R2 LED_WLAN_OUT_R
1
C141
2 2 DTC114EKA 1 0.047UF/10V
SNIFFER_YELLOW# 37 SNIFFER_GREEN# 37
3 R1
IN
3 R1
IN MLCC/+/-10%
OUT OUT
2
DDTA114YUA_7_F DDTA114YUA_7_F
B B
SNIFFER_Y_R SNIFFER_G_R
SNIFFER_Y_R SNIFFER_G_R
Layout Note: C pad is used
+RTC_CELL
No.53
as a Provision For External Media Bottom Board LED drive circuit
LED4 LITE-ON/LTST-C192TBKT-5A BLUE Power Cycling, Must place C
1
on top to be accessed when +5V_RUN
LED_WLAN_OUT_R# 2 1 2 1 R401
+5V_RUN +5V_ALW Keyboard is removed.
+ R305 750Ohm 5% 100KOhm 5%
BAT2_LED
LED2 LITE-ON/LTST-C192TBKT-5A BLUE R546
No.53 R385 10KOhm MEDIA_LED_O 2
2
1 MEDIA_LED_R 41
OUT
BREATH_PWRLED# POWER_SW#
GND
2 1 2 1 1 5% 2
+5V_SUS 37 MAIN_PWR_SW# POWER_SW# 41,43
1
+ R302 750Ohm 5% 0Ohm
3
R304 R298 pt_r0805_h24
1
1
LED3 LITE-ON/LTST-C192TBKT-5A BLUE 220Ohm C415 C413 Q57
750Ohm 1UF/10V 1UF/10V 5%
5% DDTA114YUA_7_F
R2
HDD_LED# 2 1 2 1 5% MLCC/+/-10% MLCC/+/-10%
+5V_RUN
R303 750Ohm 5% pt_c0603 pt_c0603 /*
2
2
+
Package 0603
LED5 LITE-ON/LTST-C192TBKT-5A BLUE
2
R1
Orange
Blue
BT_LED# 2 1 2 1 LED1
+5V_RUN
+
+ R299 750Ohm 5%
BLUE&ORANGE
2
IN
M_LED_BK#
38 M_LED_BK#
R529 220Ohm 5% No.39
SNIFFER_Y_R LED6
SNIFFER_Y_R 1 2 Y
pt_r0603 2 No.13 No.35
A A
4
1
3 SG
R532 220Ohm 5%
SNIFFER_G_R 1 2
SNIFFER_G_R
pt_r0603 G&Y
BAT1_LED_BLUE#
PROJECT: Lanai 1.2 SHEET 42 OF 68 SWITCH & LED RELEASE DATE : C
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN
2
REM_DIODE4_N
R316 REM_DIODE1_N
1
1
10KOhm 5% C198 Q52
1
Pin 1
E
1
C195 E Q51 REM_DIODE3_N
1
2200PF/50V C394
B 2
Pin 3
1
FAN1_TACH 37
2200PF/50V C389 MLCC/+/-10% MMST3904 2200PF/50V
B 2 1 C
2
2
1
MLCC/+/-10% MMST3904 2200PF/50V C197 MMST3904_7_F Q50 /*
C 3
2
E
1
R315 /* REM_DIODE4_P MLCC/+/-10%
3
2
MLX_53398-0371 REM_DIODE1_P MLCC/+/-10% 2200PF/50V
B 2
C387
0Ohm MLCC/+/-10%
C 2200PF/50V
2
pt_r0805_h24 CON11
3
/* Put C198 close to Guardian.
2
D 5% REM_DIODE3_P MLCC/+/-10% D
Put C195 close to Guardian.
1
Put C394 close Diode
4
FAN1_VOUT 1 HOLD1 Put C389 close Diode
FAN1_VOUT_FB 2 Put C197 close to Guardian.
WTOB_CON_3P Place under Skin.
3 Put C387 close Diode
2
HOLD2
MOLEX/53398-0371(P6497) Place under CPU.
1
D16 C317 Place near the bottom

22UF/10V
5
SODIMM.
MLCC/+/-20% UMA
RB751S40T1G pt_c1206_h75
2
/*
1
Layout Note:
R177 is put on BOT DIMM
sockett
+5V_SUS +3.3V_SUS
Guardian Note:
150K input impedance on VCP1 (Pin 43)
VCP2
Put C196 close to
2
49
Guardian. U11 R383
11 43
GND
7 H_THERMDA 37 THRM_SMBDAT SMDATA VCP1 PWR_MON 53 2.2KOhm
12 46 VCP2
37 THRM_SMBCLK SMCLK VCP2 +RTC_CELL +3.3V_SUS 1%
2
C196 REM_DIODE1_P REM_DIODE3_P
1
38 DP1 DP3 45
REM_DIODE1_N 37 44 REM_DIODE3_N R380
470PF/50V DN1 DN3
10KOhm
2
MLCC/+/-10% H_THERMDA REM_DIODE4_P
2
41 DP2 DP4 48 1%
1
H_THERMDC 40 47 REM_DIODE4_N R144 R372
7 H_THERMDC DN2 DN4
1
C406
1
C +3VSUS_THRM 35 2 T24 1 10KOhm 10KOhm R177 C
3V_SUS DP5 T25 5% 5% 0.1UF/10V
2
DN5 1 1 10KOHM MLCC/+/-10%
/*
1
+RTC_CELL 21 RTC_PWR3V 5%
ATF_INT# 20 ATF_INT# 38 THERMISTOR 10K OHM
R370 1 2 1KOhm 5% THERM_PWRGO
2
17,51 SUSPWROK 23 VSUS_PWRGD POWER_SW# 3 POWER_SW# 41,42
R141 1 2 1KOhm 5% +3V_PWROK# 16 4
51 ICH_PWRGD# 3V_PWROK# ACAVAIL_CLR ACAV_IN 37,57
3
25 1 Q53
THERMTRIP_SIO
THERMATRIP1# 17 24 T23
THERM_STP# 54 D3
THERMATRIP2# THERMTRIP1# SYS_SHDN#
18 THERMTRIP2#
R162 +RTC_CELL THERMATRIP3# LDO_SHDN#_ADDR R376
19 THERMTRIP3# LDO_SHDN#/ADDR 27 2 1 7.5KOhm +3.3V_SUS
+3.3V_SUS 2 1 +3VSUS_THRM 1% 2 2 5V_CAL_SIO1#
THERM_VEST 42 33 G
VSET LDO_POK 2.5V_RUN_PWRGD 51
1 2 26 XEN
1
49.9Ohm C188 R374 1KOhm 5% 34 28 THERM_LDO_SET

VSS LDO_SET S 1
1% C162 RHU002N06
0.1UF/10V 7 32
0.1UF/10V FAN1_VOUT FAN_OUT1 LDO_OUT2 +2.5V_RUN
MLCC/+80-20%
2
1
pt_c0402 8 FAN_OUT2 LDO_OUT1 31
MLCC/+/-10% R148 1
+3.3V_SUS 2 10KOhm /* T115 1 39 FAN_DAC1 LDO_IN2 30 THERM_LDO_IN
R146 1 2 10KOhm /* 29
LDO_IN1
36 MDC_RST_DIS# 10 GPIO1
13 +3.3V_SUS
SIO_GFX_PWR 5V_CAL_SIO1# GPIO2
14 GPIO3 VDD_3V 9 +3.3V_RUN
5V_CAL_SIO2# 15 5V_CAL_SIO2# R140 1 2 10KOhm 5% /*
GPIO4
45 AUDIO_AVDD_ON 22 GPIO5 VDD_5V_1 5 +5V_RUN
T26 1 36 6
GPIO6/FAN_DAC2 VDD_5V_2
+3.3V_SUS EMC4001_HZH
+2.5V_RUN
C161 needs to be placed near
2
Guardian IC. Voltage margining

B R137 +3.3V_SUS B
circuit for LDO output.
1
8.2KOhm For Vmargin stuff R379 R379
2
5% and R373=30K. R373=1K

THERMATRIP1# R369 31.6KOhm
1
for production. 1%
Q32 3 8.2KOhm
2
C 5% THERM_LDO_SET /*
1
THERM_B1 2 B C161 THERMATRIP3#

1
+1.05V_VCCP 1 2
R145 2.2KOhm 5%
2
E 0.1UF/10V
MMST3904_7_F 1 MLCC/+80-20% R373
2
+3.3V_RUN 0603
1KOhm
7 H_THERMTRIP# Package. 5%
Layout Note:
/*
1
Place those capacitors close to pt_r0603
1
C174 EMC4001.
C184
0.1UF/10V 10UF/10V
MLCC/+80-20% MLCC/+80-20%
2
+3.3V_SUS pt_c0805_h53
+3.3V_SUS R150
THERM_LDO_IN 2 1 +3.3V_RUN
2
C160 needs to be placed near R382 0Ohm pt_r1210_h24 /*
1
R138 1 2 THERM_VEST C171
Guardian IC. +5V_RUN C173
2
8.2KOhm 332KOhm +2.5V_RUN 1UF/10V pt_c0603

0.1UF/10V
1
5% C401 1% R381 C407 Note: MLCC/+80%-20%
2
THERMATRIP2# /* This Value of R150 can
1
No.10 0.1UF/10V 118KOhm 2200PF/50V VSET = (Tp-70)/21, where Tp = 70 MLCC/+80-20% /*

be 0.27 or 0 ohm and the
1
1
A Q31 3 MLCC/+80-20% 1% MLCC/+/-10% to 101 degree C. C177 C194 A
2
1
C C178 package is 1210
1
Tp set at 88 degrees C.
1
1 2 THERM_B2 2 B C160 0.1UF/10V 10UF/10V C182 /*

+1.05V_VCCP Guardian temp tolerance = +-3
R139 2.2KOhm 5% MLCC/+80-20% MLCC/+/-20% 0.1UF/10V
2
E 0.1UF/10V degrees C. pt_c0805_h57 MLCC/+80-20% 10UF/4V
2
1
MMST3904_7_F MLCC/+80-20% pt_c0805
2
/* MLCC/+/-20%
10 THERMTRIP_MCH#
PROJECT: Lanai 1.2 SHEET 43 OF 68 EMC4001 RELEASE DATE : N
5 4 3 2 1
A B C D E
VDDA
+3.3V_RUN
PORT C : LEAVE NC
IF NO INTERNAL MICS.
2
FROM ICH U13 C275 0.1UF/16V/X7R L40
1 A 2 MLCC/+/-10%
Port A---> HP1
17 SPKR VCC 5 1 600Ohm/100Mhz VDDA
pt_c0402
2 B
Irat=500mA Port D---> Speaker
1
37 BEEP DVDD_CORE MURATA/BLM18EG601SN1D
10KOhm 5% C273 0.1UF/16V/X7R
Port E---> ext Mic
C488
MLCC/+/-10% C489
C490
R264 AUD_PC_BEEP
10UF/10V/X5R /*
FROM EC
1UF/10V/X7R
0.1UF/16V/X7R
3 GND 4 1 2 1 2
1
1 1
pt_c0805_h57
pt_c0603
Y
SN74AHCT1G86DCKR MLCC/+/-10% L41
Port F---> HP2
pt_c0402
MLCC/+/-20%
MLCC/+/-10%
600Ohm/100Mhz
2
R265 Irat=500mA
2
MURATA/BLM18EG601SN1D
2.2KOhm
5%
C519
MLCC/+/-10% C514
C516
1UF/10V/X7R
0.1UF/16V/X7R
1
1
pt_c0805_h57
pt_c0603
10UF/10V
1
pt_c0805_h57
1000PF/50V
MLCC/+/-10%
MLCC/+/-20%
10UF/10V/X5R
1
C480
MLCC/+/-20%
MLCC/+/-10%
C541
2
2
2
U15
5% 1 0Ohm 2 R490 DVDD_CORE1 1 25 AVDD_CODEC
DVDD_CORE1 AVDD1
No.4 9 DVDD_CORE2 AVDD2 38
5% 1 2 R509 DVDD_CORE3 40
100KOhm DVDD_CORE3
5% 1 0Ohm /* 2 R510 13 AUD_SENSE_A
45 AUD_EAPD# SENSE_A AUD_SENSE_B
SENSE_B 34
AUD_HP1_OUT_L 45
15 ICH_AZ_CODEC_BITCLK 6 BITCLK AUD_HP1_OUT_R 45
1000PF/50V
1000PF/50V
MLCC/+/-10%
MLCC/+/-10%
PORTA_L 39
1
5% 1 33Ohm 2 R257 HDA_SDI
C503 /*
8 41
C507 /*
2 2
15 ICH_AZ_CODEC_SDIN0 SDI PORTA_R
VREFOUT_A 37
15 ICH_AZ_CODEC_SDOUT 5 SDO
2
PORTB_L 21
15 ICH_AZ_CODEC_SYNC 10 SYNC PORTB_R 22
VREFOUT_B 28
15 ICH_AZ_CODEC_RST# 11 RESET#
PORTC_L 23
PORTC_R 24
VREFOUT_C 29
PORTD_L 35 AUD_LINE_OUT_L 45
PORTD_R 36 AUD_LINE_OUT_R 45
32 MLCC/+/-10% 1UF/10V/X7R
VREFOUT_D
+3.3V_RUN
28 AUD_DMIC_IN0 2 VOLUME_UP/DMIC_0/GPIO1
pt_r0603 1 R511 2 AUD_EXT_MIC_L41 2 AUD_EXT_MIC_L 46
5% 1 0Ohm 2 R507 EAPD#_CODEC 3 14 AUD_EXT_MIC_L3 5.1Ohm 1% pt_c0603 C506
45 AUD_EAPD# VOLUME_DOWN/DMIC_1/GPIO2 PORTE_L AUD_EXT_MIC_R3
PORTE_R 15 1 R508 2 AUD_EXT_MIC_R41 2 AUD_EXT_MIC_R 46
5% 1 0Ohm /* 2 R502 31 5.1Ohm 1% pt_c0603 C502
VREFOUT_E AUD_VREFOUT_E 46 pt_r0603
MLCC/+/-10% 1UF/10V/X7R
PORTF_L 16 AUD_HP2_OUT_L 46
PORTF_R 17 AUD_HP2_OUT_R 46
VREFOUT_F 30
1000PF/50V
C493 /*
1000PF/50V
MLCC/+/-10%
MLCC/+/-10%
47 43
C499 /*
28 AUD_DMIC_CLK SPDIF_IN/GPIO0/EAPD/DMIC_CLK PORTG_L
1
50 AUD_SPDIF_OUT 48 SPDIF_OUT/ADAT_OUT PORTG_R 44
3 3
For TV port PORTH_L 45
2
PORTH_R 46
AVDD_CODEC
PLACE CLOSE TO U15 PIN13 CD_L 18
No.41 CD_GND 19
If SENSE_A total length >6" CD_R 20
2
change C276 to 0.1uF R271 12 AUD_PC_BEEP

PCBEEP
5.1kOhm
1% 4 DVSS1 CAP2 33
7 DVSS2 VREFFILT 27
C522
C513
AUD_SENSE_A
1
1
pt_c0805_h57
pt_c0805_h57
10UF/10V/X5R
10UF/10V/X5R
2
AVSS1 26
R279
MLCC/+/-20%
MLCC/+/-20%
AVSS2 42
No.41
2
39.2KOhm
1
PLACE CLOSE TO U15 PIN34 STAC9228

1% C276
If SENSE_B total length >6" AVDD_CODEC
1
1000PF/50V
2
3 MLCC/+/-10% change C510 to 0.1uF

D
2
Q45 R495
1
45,46 AUD_HP1_NB_SENSE 2N7002 5.1kOhm
G
2 S 1%
4 4
1
AUD_SENSE_B
PLACE BETWEEN U15 and

U16
2
PLACE CLOSE TO U15 PIN6 PLACE CLOSE TO U15 PIN5 R491

39.2KOhm
1%
1
ICH_AZ_CODEC_BITCLK ICH_AZ_CODEC_SDOUT
3
D
No.50
Q58
2
1
46 AUD_MIC_SWITCH
2
G 2N7002 R496 5% 1 0Ohm 2 R273

R258 /* R259 /* 2 S C510
20KOhm
47Ohm 47Ohm 1% 1000PF/50V 5% 1 0Ohm /* 2 R535
2
5% 5% MLCC/+/-10% JP9
1
1
1 2
3 5% 1 0Ohm /* 2 R287
D
SHORTPIN
Q59 /*
1
5 1 5
46 AUD_HP2_NB_SENSE 2N7002
C263 /* C262 /* G
0.1UF/16V/X5R 0.1UF/16V/X5R 2 S
MLCC/+/-10% MLCC/+/-10%
2
PROJECT: Lanai 1.2 SHEET 44 OF 68 STAC9228 RELEASE DATE : Yihao Yeh
A B C D E
A B C D E
Signal Inveter for Speaker Shutdown

Allow speakers to work while class driver is
+5V_SPK_AMP
installed VDDA
MURATA/BLM18AG601SN1(J5535)<G>
+5V_SPK_AMP
C533
C535
Irat=200mA L20
1UF/10V/X7R
1UF/10V/X7R
MLCC/+/-10%
MLCC/+/-10%
2
1
+5V_SPK_AMP
600Ohm
2
1 1
pt_c0603
pt_c0603
R288 Place C295 close
2
100KOhm to Pin 30
1
5%
2
+5V_AMP1
AUD_SPK_ENABLE# R525
C295
pt_c0603 C300
pt_c0603 C296
1UF/10V/X7R
1UF/10V/X7R
0.1UF/16V/X7R
MLCC/+/-10%
MLCC/+/-10%
MLCC/+/-10%
100KOhm
1
3
D 5%
Q61 MLCC/+/-10%
1
1 1UF/25V/X7R
2
44 AUD_EAPD# 2N7002 HP1_INL_AMP1
G 2 1
2 S AUD_HP1_OUT_L 44
pt_c1206_h49 C301
pt_c1206_h49 C297
HP1_INR_AMP1 2 1 AUD_HP1_OUT_R 44
3 1UF/25V/X7R
C294 /*
/*
MLCC/+/-5%
MLCC/+/-5%
D
1
MLCC/+/-10%
47PF/50V
47PF/50V
+5V_SPK_AMP
C293
FROM EC Q60 NOTE:For TPA6040A, pop
1 Note: For TPA6040A,
38,46 NB_MUTE# 2N7002 C292 and C291(0402
G
2
2 S X5R) and no pop R530 No.49 pop R291 and no pop
2
and R292. C292 and AUD_AMP_GAIN1 R294
R294
C291 value should AUD_AMP_GAIN2 100KOhm 5%
match C299 and C298
2 No.49 /* 2
R291 FROM EC
1
MUTE#_AMP1 0Ohm 1
0Ohm 5% /*
0.033UF/16V/X7R
2 AUDIO_AVDD_ON 43
R530 2
5%
MLCC/+/-10%
C292
+3.3V_CPVDD_HPVDD
MLCC/+/-5%
MLCC/+/-5%
PLACE JUST BEFORE
32
31
30
29
28
27
26
25
34
35
36
37
1
2
C526
U16
47PF/50V
C532 /*
47PF/50V
C531 /*
0.1UF/16V
MLCC/+/-10%
+5V_MAX9789 CROSSES TEMPORARY VALUES. FINAL
GAIN1
GAIN0
VDD
SGND
HP_INR
HP_INL
REG_EN
GND2
GND3
GND4
GND5
REG_OUT
MOAT VALUES CHOSEN IN PT MLCC/+/-10%
1UF/10V/X7R
1
PHASE.
1 SPKR_RIN- BYPASS 24 1 2
+5V_RUN +5V_SPK_AMP pt_c1206_h59 2 1 C299 pt_c0603 C289
44 AUD_LINE_OUT_R U38
MLCC/+/-10% 0.033UF/100V SPKR_INR_AMP1 2 23 AUD_SPK_ENABLE#
SPKR_RIN+ SPKR_EN#
5
L42
VCC
74AHC1G08GW
1 2 SPKR_INL_AMP1 3 22 4 2
SPKR_LIN+ HP_EN Y A AUD_HP1_NB_SENSE 44,46
60Ohm Irat=3A pt_c1206_h59 2 1 C298 1
44 AUD_LINE_OUT_L B NB_MUTE# 38,46
C520
pt_l0805_h41 MLCC/+/-10% 0.033UF/100V 4 21

SPKR_LIN- SPGND2
1
pt_c0805_h57
MURATA/BLM21PG600SN1(Y8220)<G> R292 /*
GND
10UF/10V/X5R
3
43 AUDIO_AVDD_ON 1 2 5 SPGND1 ROUT+ 20 AUD_SPK_R1 46
5% 0Ohm
MLCC/+/-20%
FROM EC
2
46 AUD_SPK_L1 6 LOUT+ ROUT- 19 AUD_SPK_R2 46

0.033UF/16V/X7R
MLCC/+/-10%
46 AUD_SPK_L2 7 LOUT- SPVDD2 18 +5V_SPK_AMP

1
C291
NOTE:For TPA6040A,
C530
C290
HP_OUTR
8 17
HP_OUTL
+5V_SPK_AMP SPVDD1 HPVDD
CPGND2
CPVDD1
pop C291 and no pop
pt_c0805_h57 C286
3 3
1UF/10V/X7R
1UF/10V/X7R
MLCC/+/-10%
MLCC/+/-20%
MLCC/+/-10%
10UF/10V/X5R
CPVSS
HPVSS
1
pt_c0603 C288
2
R292
MLCC/+/-20%
10UF/10V/X5R
C1N
C1P
1
1
GND1 33
pt_c0805_h57
pt_c0603
No.49
TPA6040A4RHBR
2
10
11
12
13
14
15
16
No.49
9
AUD_HP1_JACK_L 46
ROUTE VIA TRACE BACK TO TIE POINT. +3.3V_RUN
L43 AUD_HP1_JACK_R 46
+3.3V_CPVDD_HPVDD
ROUTE VIA TRACE BACK TO TIE POINT.
2 1
C527
600Ohm Irat=200mA
C529
C528
MURATA/BLM18AG601SN1(J5535)<G>
MLCC/+/-20%
10UF/10V/X5R
1
Recommend a star
1UF/10V/X7R
1UF/10V/X7R
MLCC/+/-10%
MLCC/+/-10%
1
1
GAIN SETTING RESISTORS connection for PVSS
pt_c0805_h57
+5V_SPK_AMP and CPVSS at capacitor
pt_c0603
pt_c0603
+5V_SPK_AMP
2
2
2
C6613 of MAX9789A
4 4
Gain1 Gain2 Gain

2
C287
R293 R289 /* 1 2
100KOhm 5% 100KOhm 5%
0 0 6 dB 1UF/10V/X7R
MLCC/+/-10%
AUD_AMP_GAIN1 pt_c0603
1
AUD_AMP_GAIN2
0 1 10 dB
2
R295 /* R290 ROUTE VIA TRACE BACK TO TIE POINT.

100KOhm 5% 100KOhm 5% 1 0 15.6 dB
1 1 21.6 dB
1
5 5
PROJECT: Lanai 1.2 SHEET 45 OF 68 AMP MAX9789 RELEASE DATE : Yihao Yeh
A B C D E
A B C D E
L19
Maxim:1.8V ~ 3.6V NOTE: MAKE SURE THERMAL PAD +3.3V_AMP2 2 1 Speaker CON
+3.3V_RUN
C271
1UF/10V/X7R
TI:1.8V ~ 4.5V
MLCC/+/-10%
(Pin21)UNDER MAX4411 IS NOT
1
600Ohm Irat=200mA
CONNECTED TO GND MURATA/BLM18AG601SN1(J5535)<G>
CON7
pt_c0603
1 1
2
7 SIDE1 1 1 AUD_SPK_L1 45
2 2 AUD_SPK_L2 45
3 3 AUD_SPK_R1 45
4 4 AUD_SPK_R2 45
5 5
8 SIDE2 6 6 SPEAKER_DET# 15
0.1UF/16V/X7R
MLCC/+/-10%
2
C508
WTOB_CON_6P
MOLEX/48227-0611
MLCC/+/-5%
MLCC/+/-5%
MLCC/+/-5%
MLCC/+/-5%
1
U37
19
10
21
5
U35
VCC
74AHC1G08GW
/*
/*
/*
/*
2 4 14 11
PVDD
SVDD
GND
44 AUD_HP2_NB_SENSE A Y SHDNR# OUTR AUD_HP2_JACK_R
38,45 NB_MUTE# 1
1
B
C450
C454
C451
C452
GND 18 SHDNL# OUTL 9 AUD_HP2_JACK_L
No.31
100PF/50V/NPO
100PF/50V/NPO
100PF/50V/NPO
100PF/50V/NPO
3
2
pt_c1206_h75 C511 4
HP2_INR_AMP2 NC1
44 AUD_HP2_OUT_R 2 1 15 INR
MLCC/+/-10% 2.2UF/16V 6
HP2_INL_AMP2 NC2
44 AUD_HP2_OUT_L 2 1 13 INL
2 MLCC/+/-10% 2.2UF/16V 8 2
pt_c1206_h75 NC3
Need to adjust EMI cap values as necessary.
C504
C498
C521
MLCC/+/-5%
MLCC/+/-5%
NC4 12
47PF/50V
47PF/50V
1
1
C1P 1 16
C1P NC5
PGND
SGND
C500
PVSS
SVSS
2.2UF/10V/X5R
MLCC/+/-10%
3 C1N NC6 20
1
2
17
pt_c0603
No.49
2
C1N
2 TPA4411MRTJR
PVSS
C491
2.2UF/10V/X5R
MLCC/+/-10%
1
pt_c0603
2
3 3
No.50
4 4
16
+3.3V_RUN
1 CON9
SIDE1
1
44 AUD_MIC_SWITCH 2 2 WTOB_CON_15P
AUD_MIC_SWITCH 1 2 3
44 AUD_VREFOUT_E 3 MOLEX/48227-1511
R282 100KOhm 5% 4
AUD_HP2_NB_SENSE 44 AUD_EXT_MIC_L 4
1 2 44 AUD_EXT_MIC_R 5 5
R283 100KOhm 5% 6
AUD_HP1_NB_SENSE 6
1 2 44 AUD_HP2_NB_SENSE 7 7
R286 100KOhm 5% 8
AUD_HP2_JACK_L 8
AUD_HP2_JACK_R 9 9
10 10
44,45 AUD_HP1_NB_SENSE 11 11
45 AUD_HP1_JACK_L 12 12
45 AUD_HP1_JACK_R 13 13
SIDE2
14 14
15 15
17
5 5
PROJECT: Lanai 1.2 SHEET 46 OF 68 AMP MAX4411 & AUDIO JACK
RELEASE DATE : Yihao Yeh
A B C D E
5 4 3 2 1
VDDP Power Decoupling VDDIO Power Decoupling

Core Power Decoupling
+1.2V_LOM +2.5V_LOM +3.3V_LAN
pt_c0805_h37
pt_c0805_h37
MLCC/+80-20%
MLCC/+80-20%
MLCC/+80-20%
MLCC/+80-20%
MLCC/+80-20%
MLCC/+80-20%
MLCC/+80-20%
MLCC/+80-20%
MLCC/+80-20%
MLCC/+80-20%
MLCC/+80-20%
MLCC/+80-20%
MLCC/+80-20%
4.7UF/10V
0.1UF/10V
0.1UF/10V
0.1UF/10V
0.1UF/10V
0.1UF/10V
0.1UF/10V
0.1UF/10V
0.1UF/10V
0.1UF/10V
0.1UF/10V
4.7UF/10V
0.1UF/10V
0.1UF/10V
0.1UF/10V
MLCC/+/-10%
MLCC/+/-10%
1
1
1
1
1
1
1
C23
C30
C48
C50
C47
C39
C17
C20
C26
C43
C35
C52
C49
C31
C51
2
2
2
2
2
D D
+3.3V_LAN +2.5V_LOM
15
19
56
61
17
68
6
+1.2V_LOM U3
+2.5V_LOM
VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDP1
VDDP2
L4 600Ohm
5 MURATA/BLM18AG601SN1
VDDC1 LAN_BIASVDD +3.3V_LAN
13 VDDC2 BIASVDD 36 1 2
20 VDDC3
34 +3.3V_LAN
VDDC4 L7 600Ohm
55 VDDC5 MURATA/BLM18AG601SN1
MLCC/+80-20%
0.1UF/10V
60 VDDC6
1
23 LAN_XTALVDD 2 1
XTALVDD
C59
+1.2V_LOM L3 600Ohm
MLCC/+80-20%
0.1UF/10V
1
MURATA/BLM18AG601SN1 R21 R19
MLCC/+80-20%
0.1UF/10V
1
LAN_AVDDL
C32
2
1 2 39 AVDDL 4.7KOhm
C13
44 4.7KOhm
DC3 U2
pt_c0805_h37
MLCC/+80-20%
2
4.7UF/10V
0.1UF/10V
MLCC/+/-10%
46 DC5
1
C8
2
51 DC10 DC2 38 8 VCC A0 1
EEPROM_WP
C12
7 WP A1 2
45 LAN_SCLK 6 3
DC4 LAN_SO SCL A2
2
5 SDA GND 4
35 DC1 DC11 52
1
C +1.2V_LOM L5 600Ohm C
MURATA/BLM18AG601SN1 R18 AT24C02BN
1 2 LAN_PCIE_PLLVDD
4.7KOhm
30 PCIE_PLLVDD DC8 49
L6 1 2 600Ohm LAN_PCIE_VDD 50
DC9
2
pt_c0805_h37
pt_c0805_h37
MURATA/BLM18AG601SN1
MLCC/+80-20%
MLCC/+80-20%
MLCC/+80-20%
4.7UF/10V
0.1UF/10V
4.7UF/10V
0.1UF/10V
0.1UF/10V
MLCC/+/-10%
MLCC/+/-10%
1
1
C19
C24
27 PCIE_VDD1
C21
C18
C22
33 PCIE_VDD2 DC7 48
DC6 47
No.3
2
2
24 VSS2
TDN 42 LOM_RX- 48
TDP 43 LOM_RX+ 48
C25 1 2 0.1UF/10V MLCC/+/-10% LAN_PCIETXDP 26
16 PCIE_RX6+/GLAN_RX+ LAN_PCIETXDN PCIE_TXD_P
C28 1 2 0.1UF/10V MLCC/+/-10% 25 41
16 PCIE_RX6-/GLAN_RX- PCIE_TXD_N RDN LOM_TX- 48
16 PCIE_TX6+/GLAN_TX+ 31 PCIE_RXD_P RDP 40 LOM_TX+ 48
No.53 16 PCIE_TX6-/GLAN_TX- 32
49.9Ohm 1%
49.9Ohm 1%
PCIE_RXD_N
1
1
12 2 LINK_LED10#
35,38,50 PCIE_WAKE# LOM_PERST# WAKE LINK_LED# LINK_LED100# LINK_LED10# 48
R12
R11
16,50 PLTRST_LAN_MINICARD# 1 2 10 PERST# SPD100_LED# 1 LINK_LED100# 48
R32 47Ohm 5% 29 66 ACTLED#
21 CLK_PCIE_LOM ACTLED# 48
49.9Ohm 1%
PCIE_REFCLK_P TRAFFIC_LED#
1
49.9Ohm 1%
16 SB_LOM_PCIE_RST# 1 2 21 CLK_PCIE_LOM# 28 PCIE_REFCLK_N
R13
R14
R25 0Ohm 5% /*
2
2
SERIAL_DI 67
+3.3V_RUN +3.3V_LAN
2
MLCC/+/-10%
SERIAL_DO 62
0.1UF/10V
1% VAUX_PRSNT
C14
R22 1 2 1KOhm 54 VAUX_PRSNT
1
R10 2 1KOhm 1% VMAIN_PRSNT
0.1UF/10V
MLCC/+/-10%
1 53 VMAIN_PRSNT
C9
LOM_LOW_PWR 3 8
B 38 LOM_LOW_PWR LOW_PWR GPIO_2 B
GPIO_0 4
2
58 NC2
57 7 EEPROM_WP
NC1 GPIO_1
No.25 Layout note:
LOM_XOUT 65 LAN_SCLK +3.3V_LAN
X1
22
SCLK Place Close to LOM
2 1 XTALO
1 2 LOM_XOUT_R LOM_XIN 21 XTALI SO 64 LAN_SO
R37 200Ohm 1% +3.3V_LAN
R41
pt_c0805_h37
MLCC/+80-20%
No.12
4.7UF/10V
0.1UF/10V
MLCC/+/-10%
1
LAN_UART_MODE
C79
25Mhz R9 1%
27PF/50V
27PF/50V
MLCC/+/-5%
MLCC/+/-5%
UART_MODE 9 1 2
1
1 LAN_RDAC
C33
C37
C82
+/-30ppm/18PF 2 37 0Ohm
RDAC
4
1KOhm 63 5% /*
NC3 Q15
2
E
LAN_REGCTL25
2
Layout note: REGCTL25 18 3 B MBT35200MT1G

Place Close to LOM +3.3V_LAN
C
R44 R49 1.5Ohm
2 PCIE_LOM_CLKREQ#_R LAN_REGCTL12
1
2
5
6
21 PCIE_LOM_CLKREQ# 1 11 CLKREQ# REGCTL12 14 1 2
59 pt_r2512_h26 5% +2.5V_LOM
ENERGY_DET
pt_c0805_h37
0Ohm 5%
MLCC/+80-20%
4.7UF/10V
0.1UF/10V
MLCC/+/-10%
1
1
C61
R93 No.12
C53
10KOhm 16
GND
5% VSS1
MLCC/+80-20%
0.1UF/10V
3
1
/* Q10
2
E
C68
BCM5906MKMLG C65
69
C.S BCM5906MKMLG A2 QFN68 MMJT9435T1G 10UF/10V

2
B 1
C
MLCC/+80-20%
2
pt_c0805_h53
4 2
No.27
+1.2V_LOM
A A
MLCC/+80-20%
0.1UF/10V
1
C44
C38
10UF/10V
MLCC/+80-20%
2
pt_c0805_h53
PROJECT: Lanai 1.2 SHEET 47 OF 68 LAN BCM5906MKMLG(QFN-68) RELEASE DATE : Ivan_Chou
5 4 3 2 1
5 4 3 2 1
D D
+3.3V_LAN
Reserve Pull-up
1
R308
No Stuff 10KOhm
5% /* CON10
2
14 YELLOW+
R311 150Ohm 1%
ACTLED# 1 2 ACTLED#_R 13
47 ACTLED# YELLOW-
LOM_TX+ 11
47 LOM_TX+ TRD1+
12 TRCT1
LOM_TX- 10
47 LOM_TX- TRD1-
LOM_RX+ 4
47 LOM_RX+ TRD2+
6 TRDCT
LOM_RX- 5
47 LOM_RX- TRD2-
3
NP_NC1 20
21
+3.3V_LAN Source Guideline:
NC_1 NP_NC2 1. Use +3.3V_SUS if Wake-on-LAN is
1 NC_2
+2.5V_LOM L21 600Ohm 2
MURATA/BLM18AG601SN1 NC_3 NOT required out of S4, S5
1 2 LOM_CT 8 2. Use +3.3V_SRC if Wake-on_LAN is
NC_4
7 NC_5 required out of S4, S5
9 NC_6
C LINK_LED100# R309 1 2 150Ohm 1% LINK_LED100#_R 15 C
47 LINK_LED100# LINK_LED10# R310 1 ORANGE-
47 LINK_LED10# 2 150Ohm 1% LINK_LED10#_R 17
SHIELD1
SHIELD2
GREEN-
16 COMMON+
0.1UF/16V
0.1UF/16V
MLCC/+/-10%
MLCC/+/-10%
1
1
C303
C304
LAN_JACK_17P +3.3V_SUS +3.3V_LAN
18
19
TYCO/1840427-2,TAB DOWN JP1
No Stuff
2
1 2
R307 1 2 10KOhm 5% /* 0Ohm
pt_r0603
+3.3V_LAN
R306 1 2 10KOhm 5% /* JUMP
Layout note:
No Stuff C303 should be close to pin12
Reserve Pull-up C304 should be close to pin6
B B
A A
PROJECT: Lanai 1.2 SHEET 48 OF 68 Magnetics and RJ-45 RELEASE DATE : Ivan_Chou
5 4 3 2 1
5 4 3 2 1
+5V_ALW +5V_RUN
+3.3V_ALW +3.3V_SUS
+15V_ALW
+15V_ALW PQ42
8 D S 1
7 2
1
PQ39
6 3
5 G 4 PR101 8 D S 1
1
100KOhm 7 2
1
PR156 PC170 PR155 +5V_ALW2 5% 6 3 PR154
+5V_ALW2 100KOhm SI4800BDY 10UF/16V 20KOhm 5 G 4 PC168 20KOhm
5% MLCC/+/-10% 5% 5%
2
pt_c1206_h71 10UF/10V
2
MLCC/+/-20%
1
SUS_3.3V_ENABLE SI4800BDY
2
pt_c0805_h57
1
RUN_ENABLE PR99
D PR157 100KOhm D
1
100KOhm 5% 3
D
1
5% 3 PC92 PR100
D
1
PC167 PQ27 4700PF/50V 100KOhm
2
PQ40 4700PF/50V SUS_ON_3.3V# 1 pt_c0603 5%
2
RUN_ON_5V# 1 2N7002 MLCC/+/-10% 2N7002 MLCC/+/-10% /*
2
G
pt_sot23_philips pt_c0603 2 S pt_sot23_philips /*
2
G
2 S 3
D
3
D
PQ28
PQ49 3.3V_SUS_ON 1
RUN_ON 1 37 3.3V_SUS_ON 2N7002
2N7002 G
28,37,51,54 RUN_ON
G pt_sot23_philips For iAMT Support 2 S pt_sot23_philips
2 S
+15V_ALW
+5V_ALW +5V_SUS
1
PQ41
PR95 8 D S 1
1
100KOhm 7 2
1
+5V_ALW2 5% 6 3 PR153
5 G 4 PC169 20KOhm
+1.8V_SUS +1.8V_RUN 5%
2
10UF/10V
No.29
2
MLCC/+/-20%
1
+15V_ALW SUS_5V_ENABLE SI4800BDY
2
+5V_ALW2 PR97 pt_c0805_h57
PQ16 100KOhm
1
1
8 D S 1 5% 3
D
1
PR39 7 2 PC166 PR152
1
100KOhm PR40 PQ24 4700PF/50V 100KOhm
2
6 3
5% 5 4 PC53 20KOhm SUS_ON_5V# 1 pt_c0603 5%
G
1
5% 2N7002 MLCC/+/-10% /*
2
G
PR37 PD9 10UF/10V 2 S pt_sot23_philips /*
2
2
100KOhm FDS8884 MLCC/+/-20% 3
2
2 1 pt_c0805_h57 D
C 5% C
RB751V_40 /* PQ26
3 pt_sod323_h35 SUS_ON 1
2
D 37,51 SUS_ON
1
/* PC52 G 2N7002
PQ14 0.047UF/25V 2 S pt_sot23_philips
1 1 2 MLCC/+/-10% No.34
2N7002 /*
2
G
2 S pt_sot23_philips PR42
3 0Ohm
D
5%
PQ15
1 2N7002
37 1.8V_RUN_ON
G pt_sot23_philips
2 S
+3.3V_RUN
+3.3V_ALW No.29
+15V_ALW
PQ38
1
+5V_ALW2 8 D S 1
1
PR98 7 2 PR151 +1.8V_SUS +5V_SUS +3.3V_SUS

100KOhm 6 3 PC162 20KOhm
5% 5 G 4 5% Reserve discharge path
10UF/10V
1
MLCC/+/-20%
1
PR96 PD11
2
100KOhm FDS8884 pt_c0805_h57 R96 R60 R242

2 1
5%
B RB751V_40 30Ohm 1KOhm 1KOhm B
1
3 pt_sod323_h35 PC164 No.11 1% 5% /* 5% /*

2
D
/* 4700PF/50V pt_r0603 pt_r0603 pt_r0603
2
PQ25 MLCC/+/-10% /*
1 pt_c0603 3 3 3
2
1 2 D D D
G 2N7002 Q21 Q13 Q40
2 S pt_sot23_philips PR102
3 0Ohm SUS_ON_5V# 1 1 1
D 2N7002 2N7002 2N7002
5% G G G
PQ29 2 S /* 2 S 2 S
1 /* /*
37 3.3V_RUN_ON 2N7002
G
2 S pt_sot23_philips
Reserve discharge path +5V_RUN +3.3V_RUN +1.8V_RUN +1.5V_RUN +0.9V_DDR_VTT +1.25V_RUN
For iAMT Support

1
R151 R165 R71 R63 R94 R74
1KOhm 10Ohm 1KOhm 1KOhm 1KOhm

5% /* 5% /* 5% /* 5% /* 5% /* 1KOhm
pt_r0603 pt_r0603 pt_r0603 pt_r0603 pt_r0603 5% /*
2
pt_r0603
3 3 3 3 3 3
D D D D D D
Q33 Q34 Q16 Q14 Q22 Q17
A A
RUN_ON_5V# 1 1 1 1 1 1
G 2N7002 G 2N7002 G 2N7002 G 2N7002 G 2N7002 G 2N7002
2 S 2 S 2 S 2 S 2 S 2 S
/* /* /* /* /* /*
PROJECT: Lanai 1.2 SHEET 49 OF 68 Power Control Switch RELEASE DATE : Eric Ko
5 4 3 2 1
5 4 3 2 1
D D
No.21
+PWR_SRC
+3.3V_ALW
5
6
7
8
2
2
U9
D
R108 R106
SI4800BDY
G
100KOhm 100KOhm
S
/*
5% 5%
/* /*
4
3
2
1
3 3
D D
Q30 Q28
1 1
37 AUX_EN_WOWL 2N7002 2N7002
G G
2 S 2 S
2
/* /*
+3.3V_WLAN
1
R115 R107 C107
1
100KOhm R116 470KOhm 4700PF/50V
5% 200KOhm 5% MLCC/+/-10% R104
5% pt_c0603 0Ohm
2
/* /*
/* /* 5%
1
pt_r1206_h26
2
+3.3V_RUN
C C
CON3B
CON3A
76 NP_NC2 NP_NC1 75
21 CLK_PCIE_MINI2# 1 1 2 2 CLK_PCIE_MINI1# 21 114 NP_NC40 NP_NC3 77
21 CLK_PCIE_MINI2 3 3 4 4 CLK_PCIE_MINI1 21 115 NP_NC41 NP_NC4 78
5 5 6 6 116 NP_NC42 NP_NC5 79
10 G_DAT_DDC2 7 7 8 8 MINI2CLK_REQ# 21 117 NP_NC43 NP_NC6 80
10 G_CLK_DDC2 9 9 10 10 VGAVSYNC 10 118 NP_NC44 NP_NC7 81
11 11 12 12 VGAHSYNC 10 119 NP_NC45 NP_NC8 82
10 VGA_RED 13 13 14 14 +5V_ALW 120 NP_NC46 NP_NC9 83
10 VGA_BLU 15 15 16 16 121 NP_NC47 NP_NC10 84
10 VGA_GRN 17 17 18 18 +5V_RUN 122 NP_NC48 NP_NC11 85
10 TV_CVBS 19 19 20 20 +1.5V_RUN 123 NP_NC49 NP_NC12 86
B B
10 TV_Y 21 21 22 22 USB_MCARD1_DET# 17 124 NP_NC50 NP_NC13 87
10 TV_C 23 23 24 24 USB_BACK_EN# 38 125 NP_NC51 NP_NC14 88
25 25 26 26 USB_OC2_3# 16 126 NP_NC52 NP_NC15 89
+3.3V_RUN 27 27 28 28 PLTRST_LAN_MINICARD# 16,47 127 NP_NC53 NP_NC16 90
29 29 30 30 PCIE_WAKE# 35,38,47 128 NP_NC54 NP_NC17 91
31 31 32 32 COEX2_WLAN_ACTIVE 41 129 NP_NC55 NP_NC18 92
+3.3V_RUN 33 33 34 34 COEX1_BT_ACTIVE 41 130 NP_NC56 NP_NC19 93
17 USB_MCARD2_DET# 35 35 36 36 ICH_SMBCLK 17,35 131 NP_NC57 NP_NC20 94
16 PCIE_MCARD2_DET# 37 37 38 38 ICH_SMBDATA 17,35 132 NP_NC58 NP_NC21 95
17 PCIE_MCARD1_DET# 39 39 40 40 WLAN_RADIO_DIS# 38 133 NP_NC59 NP_NC22 96
38 WWAN_RADIO_DIS# 41 41 42 42 SB_WWAN_PCIE_RST# 16 134 NP_NC60 NP_NC23 97
43 44 135 98
T1 1 YPRPB_DET# 44 AUD_SPDIF_OUT 45
43 44
46
LED_WLAN_OUT# 42
136
NP_NC61 NP_NC24
99
45 46 SB_WLAN_PCIE_RST# 16 NP_NC62 NP_NC25
47 47 48 48 MINI1CLK_REQ# 21 137 NP_NC63 NP_NC26 100
16 PCIE_TX1- 49 49 50 50 +3.3V_WLAN 138 NP_NC64 NP_NC27 101
16 PCIE_TX1+ 51 51 52 52 139 NP_NC65 NP_NC28 102
53 53 54 54 140 NP_NC66 NP_NC29 103
16 PCIE_RX1- 55 55 56 56 ICH_USBP9- 16 141 NP_NC67 NP_NC30 104
16 PCIE_RX1+ 57 57 58 58 ICH_USBP9+ 16 142 NP_NC68 NP_NC31 105
59 59 60 60 143 NP_NC69 NP_NC32 106
16 ICH_USBP3- 61 61 62 62 PCIE_TX2- 16 144 NP_NC70 NP_NC33 107
16 ICH_USBP3+ 63 63 64 64 PCIE_TX2+ 16 145 NP_NC71 NP_NC34 108
65 65 66 66 146 NP_NC72 NP_NC35 109
16 ICH_USBP2- 67 67 68 68 PCIE_RX2- 16 147 NP_NC73 NP_NC36 110
16 ICH_USBP2+ 69 69 70 70 PCIE_RX2+ 16 148 NP_NC74 NP_NC37 111
37 HOST_DEBUG_RX 71 71 72 72 8051_RX 37 149 NP_NC75 NP_NC38 112
37 HOST_DEBUG_TX 73 73 74 74 8051_TX 37 150 NP_NC76 NP_NC39 113
PCB_SCK_2X37P PCB_SCK_2X37P
SUYIN/127216FA074G500ZR SUYIN/127216FA074G500ZR
A A
PROJECT: Lanai 1.2 SHEET 50 OF 68 BtoB CON RELEASE DATE : STANLY_HSU
5 4 3 2 1
5 4 3 2 1
Discrete +3.3V_SUS
R40 1 2 0Ohm 5%
58 1.25V_RUN_PWRGD
1
R105
R56 1 2 0Ohm 5%
55 1.5V_RUN_PWRGD
R317 1 2 0Ohm 5% 100KOhm
55 1.05V_RUN_PWRGD
R99 1 2 0Ohm 5% /* 5%
43 2.5V_RUN_PWRGD
2
ICH_PWRGD#
+5V_RUN +5V_ALW ICH_PWRGD# 43
3
D
D D7 2
D
R28 10KOhm E Q26
1 2 1 2 Q6 1
5% B 1 PMBS3906 +3.3V_ALW G 2N7002
2 S
1
C
1
1
3
C36 RB751V_40 3
R33 C27 R27 4.7KOhm C Q5
0.1UF/10V 200KOhm 1 B PMBS3904
14
1 2
MLCC/+80-20% 5% 2200PF/50V 5% U8D
2
2
MLCC/+/-10% E IMVP_PWRGD VCC
2
17,37,53 IMVP_PWRGD 12
2 11 ICH_PWRGD
RESET_OUT# ICH_PWRGD 10,17
37 RESET_OUT# 13
GND
74AHC08PW
+1.8V_RUN +1.8V_SUS
7
D9 2
R97 10KOhm E
1 2 1 2 Q25
5% B 1 PMBS3906
1
C
Keep Away from high speed buses
1
3
C98 RB751V_40 3
R98 C93 R103 4.7KOhm C Q24
0.1UF/10V 200KOhm 1 2 1 B PMBS3904
MLCC/+80-20% 5% 2200PF/50V 5% +3.3V_ALW +3.3V_ALW
2
MLCC/+/-10% E +3.3V_SUS
2
2 C88 0.1UF/10V
1 2
MLCC/+80-20%
2
+3.3V_RUN +3.3V_ALW R100
20KOhm
5
D8 2 5% U6A U6B
R91 10KOhm
1
E
1 2 1 2 Q20 1 6 3 4
5% B 1 PMBS3906
1
C +3.3V_ALW
1
1
3
C C89 RB751V_40 3 C94 NC7WZ14P6X_NL NC7WZ14P6X_NL C
R92 C87 R95 4.7KOhm C Q23
2
0.1UF/10V 200KOhm 1 2 1 B PMBS3904 0.01UF/25V C96 0.1UF/10V
MLCC/+80-20% 5% 2200PF/50V 5% MLCC/+/-10%
2
2
MLCC/+/-10% 1 2
E MLCC/+80-20%
2
14
U8A
1 VCC
R101 0Ohm 3
28,37,49,54 RUN_ON 1 2 2
5% GND
74AHC08PW
+3.3V_ALW
7
5V_3V_1.8V_1.25V_RUN_PWRGD 38
14
U8B
4 VCC
6 RUNPWROK 37,53
5
GND
74AHC08PW
7
+3.3V_ALW
14
U8C
9 VCC
37,49 SUS_ON
8 SUSPWROK 17,43
3V_5V_SUS_PWRGD 10
+3.3V_SUS +3.3V_ALW +3.3V_ALW GND
C41 0.1UF/10V 74AHC08PW
7
1 2
D4 2 MLCC/+80-20%
R31 10KOhm E
1 2 1 2 Q8
B 5% B 1 PMBS3906 B
1
C
1
3
C42 RB751V_40
R36 C29 U4
0.1UF/10V 200KOhm D6 1 5
MLCC/+80-20% 5% 2200PF/50V NC VCC
2
MLCC/+/-10%
2
1 2 2 A
1
3 GND Y 4
RB751V_40
R39
200KOhm NC7SZ14P5X_NL
5%
2
+5V_SUS +5V_ALW
D3 2
R34 10KOhm E
1 2 1 2 Q7
5% B 1 PMBS3906
1
C
1
3
C40 RB751V_40
R38 C34
0.1UF/10V 200KOhm D5
MLCC/+80-20% 5% 2200PF/50V
2
MLCC/+/-10%
2
1 2
1
RB751V_40
R29 R30
200KOhm 200KOhm
5% 5%
2
A A
PROJECT: Lanai 1.2 SHEET 51 OF 68 Power Sequence Logic RELEASE DATE : C.L. Ho
5 4 3 2 1
5 4 3 2 1
D D
C C
XDP
U20
SAMTEC/BSH-030-01-L-D-A-TR Layout note:R123 should
1 GND0 GND1 2 connect to H_RESET# with
XDP_BPM#5 3 4 XDP_OBS8 1 T92
7 XDP_BPM#5 XDP_BPM#4 OBSFN_A0 OBSFN_C0 XDP_OBS9 T101 no stub
7 XDP_BPM#4 5 OBSFN_A1 OBSFN_C1 6 1
7 GND2 GND3 8
1 2 XDP_OBS0 9 10 XDP_OBS16 1 T97
7 XDP_BPM#3 R319 XDP_OBS1 OBSDATA_A0 OBSDATA_C0 XDP_OBS17 1
7 XDP_BPM#2 1 2 0Ohm 5% 11 OBSDATA_A1 OBSDATA_C1 12 T106
R320 0Ohm 5% 13 14
XDP_OBS2 GND4 GND5 XDP_OBS10 1 +1.05V_VCCP +3.3V_RUN
7 XDP_BPM#1 1 2 /* 15 OBSDATA_A2 OBSDATA_C2 16 T94
XDP_BPM#0 R321 1 /*
2 0Ohm 5% XDP_OBS3_R 17 18 XDP_OBS11 1 T102
7 XDP_BPM#0 R322 0Ohm 5% OBSDATA_A3 OBSDATA_C3
19 GND6 GND7 20
/* 21 22
/* OBSFN_B0 OBSFN_D0
23 OBSFN_B1 OBSFN_D1 24
2
+1.05V_VCCP 25 26
GND8 GND9
T88 1 XDP_OBS4 27 OBSDATA_B0 OBSDATA_D0 28 XDP_OBS12 1 T95 C352
2
T85 1 XDP_OBS5 29 OBSDATA_B1 OBSDATA_D1 30 XDP_OBS13 1 T104 0.1UF/10V
2
MLCC/+/-10% R347 R346
1
31 GND10 GND11 32
R323 T84 1 XDP_OBS6 33 OBSDATA_B2 OBSDATA_D2 34 XDP_OBS14 1 T96 /* 54.9Ohm 1KOhm
54.9Ohm T87 1 XDP_OBS7 35 OBSDATA_B3 OBSDATA_D3 36 XDP_OBS15 1 T103 1% 5%
1% 37 GND12 GND13 38 /*
H_PWRGD_XDP
1
/* 7 H_PWRGD_XDP 39 PWRGOOD/HOOK0 ITPCLK/HOOK4 40 CLK_XDP 21
XDP_OBS20
1
41 HOOK1 ITPCLK#/HOOK5 42 CLK_XDP# 21

43 VCC_OBS_AB VCC_OBS_CD 44
45 46 RST_SNS1 1 2
21 CLK_PCIE_XDP_3GPLL HOOK2 RESET#/HOOK6 H_RESET# 7,9
2
47 48 R123 100Ohm 5%
B 21 CLK_PCIE_XDP_3GPLL# HOOK3 DBR#/HOOK7 XDP_DBRESET# 7,17,38 B
C331 49 50
0.1UF/10V GND14 GND15 /*
10 LCTLB_DATA 51 SDA TDO 52 XDP_TDO 7
MLCC/+/-10% XDP_TRST#
1
10 LCTLA_CLK 53 SCL TRSTN 54 XDP_TRST# 7

/* 55 56 XDP_TDI
XDP_TCK TCK1 TDI XDP_TMS XDP_TDI 7
7 XDP_TCK 57 TCK0 TMS 58 XDP_TMS 7
59 GND16 GND17 60
61 NP_NC1 NP_NC2 62
BtoB_CON_60P
/*
CAD NOTE:
Place the XDP connector on the
primary side of the CRB and place
all components near the connector.
A A
PROJECT: Lanai 1.2 SHEET 52 OF 68 XDP RELEASE DATE : Terry_Lin
5 4 3 2 1
5 4 3 2 1
+CPU_PWR_SRC
EL/Lf_T=3000hrs_105c/+/-20%
EL/Lf_T=3000hrs_105c/+/-20%
EL/Lf_T=3000hrs_105c/+/-20%
EL/Lf_T=3000hrs_105c/+/-20%
Design Current:35.2A
pt_c1206_h71 MLCC/+/-10%
pt_c1206_h71 MLCC/+/-10%
MLCC/+/-10%
MLCC/+/-10%
1
/*
Maximum current:44A
10UF/25V
10UF/25V
PR88
2200PF/50V
MLCC/+/-10%
1
1
PC146
PC147
pt_c0603
10UF/25V
10UF/25V
PC79
PC80
PC76
PC77
2.2Ohm
100uF/25V
100uF/25V
0.1UF/50V
MLCC/+/-10%
OCP point min.50A + + + +
PCE1
PCE3
PCE4
PCE2
pt_r1206_h26
100uF/25V
100uF/25V
5%
5
6
7
8
PR61
2
pt_c1206_h71
pt_c1206_h71
0Ohm
2
D
pt_c0603
1500PF/50V
1 5% /*
MLCC/+/-5%
37,51 RUNPWROK 2
1
PC81
S
PQ17
PR64 PC149 SI4386DY_T1_E3
4
3
2
1
2
D 0Ohm 0.22UF/10V GND +VCC_CORE D
37 IMVP_VR_ON 1 5% 2 pt_c0603
MLCC/+/-10% CORE_HG1
+VCC_CORE_L1
1
1 2
1
PR63 PR148
4
9
0Ohm 0Ohm PL12
9
8
7
1
PMON 1 5% /* 2 pt_r0603 GND PU7 D 5 PC78 0.45UH
5% 4 G 6 1500PF/50V Irat=25A
GND2
UGATE
PHASE
1
+5V_ALW pt_c0603 pt_inductor_4p_453x394_spe
2
3 7
+3.3V_RUN MLCC/+/-5% PR83
2
2 8
1 6 1 PR79 10Ohm
BOOT FCCM 10KOhm pt_r0603
17,37,51 IMVP_PWRGD 2 PWM VCC 5 S
1
1% 1%
LGATE
PQ18
GND1
PR87
2
1 2 2 1
1
PC148 FDS7088SN3 2.2Ohm
7 H_PSI#
1
1UF/10V pt_r1206_h26 PR71 PC75
PWR_MON PR59 pt_c0603 5% 7.68KOhm 0.22UF/10V PR80
7,10,15
H_DPRSTP#
43 PWR_MON
DPRSLPVR
10,17
1.91KOhm ISL6208CRZ MLCC/+/-10% pt_r0805_h24 pt_c0603 0Ohm
3
4
2
pt_r0603 GND 1% MLCC/+/-10% pt_r0603+PWR_SRC
1% +CPU_PWR_SRC 5%
VO_CORE
PT1
PC60 VSUM ISEN1
TPC32T
2
2
GND GND
1
1UF/10V CORE_LG1 PJP16
8
8
8
8
8
8
8
pt_c0603 +CPU_PWR_SRC
VID6
VID5
VID4
VID3
VID2
VID1
VID0
1 1 2 2
MLCC/+/-10%
1
4MM_OPEN_5MIL
2
pt_c1206_h71 MLCC/+/-10%
pt_c1206_h71 MLCC/+/-10%
pt_c1206_h71 MLCC/+/-10%
pt_c1206_h71 MLCC/+/-10%
1
1
1%
GND /*
38 CLK_ENABLE#
2
2200PF/50V
PR89 PJP15
MLCC/+/-10%
MLCC/+/-10%
1
1
PC152
PC151
pt_c0603
10UF/25V
10UF/25V
10UF/25V
10UF/25V
PR62
PC83
PC82
PC84
PC85
PR146 2.2Ohm
0.1UF/50V
2
PC62 PC59 0Ohm CGND PR58 pt_r1206_h26 1 2

1 2
1
5
6
7
8
C C
35 499Ohm
2200PF/50V 0.015UF/16V 5% 0Ohm 5%
2
MLCC/+/-10% MLCC/+/-10% /* PR52 pt_r0603 4MM_OPEN_5MIL
2
CGND GND
D
pt_c0603
1500PF/50V
/* PR57 10KOhm 5% /*
MLCC/+/-5%
1
147KOhm 5% 2
S
2
1
5% pt_r0603
PC86
/* 1% PU4
45
41
40
39
37
36
34
33
32
31
PR145
ISL6260CCRZ_T PC154 PQ19

470KOHM
Close to Phase 1
2
0.22UF/10V SI4386DY_T1_E3
1
4
3
2
1
+VCC_CORE
GND4
GND
PGOOD
3V3
CLK_EN#
DPRSTP#
VID3
DPRSLPVR
VR_ON
VID6
VID5
VID4
Inductor pt_c0603 CORE_HG2
2
38 IMVP6_PROCHOT# PSI# MLCC/+/-10%
1 PSI# VID2 30 GND
PR49 PMON
1
1
2 PMON VID1 29
13KOhm 3 28 +VCC_CORE_L2 1 2
1% /* RBIAS VID0
4 VR_TT# PWM1 27
1
VDD_CORE 1 2 5 26
NTC PWM2 PR149
4
6 SOFT PWM3 25
9
VO_CORE 2 1 7 24 0Ohm PL13
OCSET FCCM
9
8
7
1
PC55 8 23 pt_r0603 GND PU8 D 5 PC153 0.45UH
PR46 220PF/50V VW ISEN1 5% 1500PF/50V Irat=25A
9 22 4 G 6
GND2
UGATE
PHASE
COMP ISEN2
1
DROOP
11.5KOhm 1 PR55 pt_c0603 pt_inductor_4p_453x394_spe
2
2 1 2 10 FB ISEN3 21 3 7
VDIFF
VSUM
+5V_ALW
GND1
VSEN
1% 0Ohm 5% MLCC/+/-5% PR84
2
44 2 8
VDD
RTN
DFB
VSS
ISEN2
ISEN1
GND3
ISEN3
2
VIN
MLCC/+/-10% PR77 10Ohm
VO
5% /*
MLCC/+/-10%
GND2 43 1 BOOT FCCM 6 1

2
pt_r0603
PR144 10KOHM
PR48
PC61
1000PF/50V
10KOhm pt_r0603
6.34kOhm
MLCC/+/-10%
2 PWM VCC 5 S
1
1
1.69KOhm
PC56
332Ohm
PR47
PR45
1500PF/50V
PR56 1% 1%
LGATE
PQ20
42
11
12
13
14
15
16
17
18
19
20
GND1
1 1%
1%
226KOhm PR90
2
GND GND 1 2 2 1
1
1
1% PR43 PC150 FDS7088SN3 2.2Ohm
1
1
1 1%
/* 82.5KOhm PR81 +5V_ALW 1UF/10V pt_r1206_h26 PR75 PC74

2
1% 10Ohm ISL6208CRZ pt_c0603 5% 7.68KOhm 0.22UF/10V PR86

1
GND
2 PR51 pt_r0603 MLCC/+/-10% pt_r0805_h24 pt_c0603 0Ohm
3
4
2
1 2 1
4.99KOhm 1% /* VDD_CORE 1 1% 2 1% MLCC/+/-10% pt_r0603
PR50 PC57 1 PR54 5%
2
2 1 2
1
1KOhm 0.01UF/16V 0Ohm 5% PC72 PR76 Intersil request to VSUM ISEN2 VO_CORE
2
GND GND
B 1 2 2 1 PC58 1UF/10V 0Ohm CORE_LG2 B
1% 680PF/50V pt_c0603 pt_r0603 change. +CPU_PWR_SRC
MLCC/+/-10% MLCC/+/-10% MLCC/+/-10% 5%
2
1000PF/50V
MLCC/+/-10%
MLCC/+/-10%
MLCC/+/-10%
MLCC/+/-10%
MLCC/+/-10%
pt_c1206_h71 MLCC/+/-10%
1 2 1 2 GND
2
1
PC189
PC63
1000PF/50V
10UF/25V
10UF/25V
10UF/25V
2200PF/50V
PR44 /* PR91
MLCC/+/-10%
MLCC/+/-10%
0.1UF/50V
8 VCCSENSE 1 2
1
PC157
PC156
pt_c0603
10UF/25V
PC88
PC87
PC90
PC89
0Ohm PR74 GND 2.2Ohm
1
5% PR53 CGND 10Ohm +CPU_PWR_SRC pt_r1206_h26
1
5
6
7
8
/* 0Ohm pt_r0603 5%
pt_r0603 CGND VIN 1 1%
12
2
CGND 2
pt_c1206_h71
pt_c1206_h71
pt_c1206_h71
pt_c0603
PC91
1500PF/50V
1 5%
MLCC/+/-5%
2
CGND 8 VSSSENSE 2
PC158
MLCC/+/-10%
MLCC/+/-10%
S
1
2
PC71
1000PF/50V
1000PF/50V
0.01UF/50V
PR60 0.22UF/10V
MLCC/+/-10%
2
PC190
PC65
0Ohm pt_c0603 PQ21
2
+VCC_CORE
2
pt_r0603 /* MLCC/+/-10% SI4386DY_T1_E3
4
3
2
1
5% CORE_HG3
2
GND
1
PC64 +VCC_CORE_L3
1
1 2
1
330PF/50V CGND CGND

CGND MLCC/+/-10% PR150
0Ohm
4
MLCC/+/-10%
2 1
1
9
8
7
1
pt_r0603 GND PU9 PC159 PL14
0.1UF/16V
1
10.5KOhm
PC67
5% UGATE D 5 1500PF/50V 0.45UH

PHASE
GND2
PR68
pt_c0603 Irat=25A
2
4 G 6
+5V_ALW
1%
PR67 MLCC/+/-5% pt_inductor_4p_453x394_spe

2
2
Close to Phase 1 3 7
1
1KOhm PR66 1 6 2 8
Inductor 1% 15KOhm 2
BOOT FCCM
5 1 PR82
PWM VCC
1
1% PR78 10Ohm
2
1 2 S
LGATE
GND1
PR70 CGND /* PR92 10KOhm pt_r0603

PQ22
1
VO_CORE 15KOhm 1 2 PC155 2.2Ohm 1% 1%
PWR_MON 43
1% 1UF/10V FDS7088SN3 pt_r1206_h26
2
1 2 2 1
2
A A
pt_c0603 5%
0.033UF/16V
MLCC/+/-10%
MLCC/+/-10%
MLCC/+/-10%
MLCC/+/-10%
1 2
2
1
30KOhm
PR65
0.01UF/25V
0.33UF/16V
PR72 ISL6208CRZ MLCC/+/-10% PR73 PC73 PR85

3
4
2
0.1UF/10V
GND
1
1
4.53KOhm
pt_c0603
5%
PC69
PC70
PC68
PR69
PC66
PR147 2.43KOhm 7.68KOhm 0.22UF/10V 0Ohm

/*
1%
1% pt_r0805_h24 pt_c0603 pt_r0603

/*
2 1 1 2 GND
CORE_LG3 GND 1% MLCC/+/-10% 5%
6.8KOHM
2
VSUM 5% pt_r0603 VSUM ISEN3 VO_CORE

1
2
CGND GND
PROJECT: Lanai 1.2 SHEET 53 OF 68 POWER_VCORE RELEASE DATE : JEFF
5 4 3 2 1
5 4 3 2 1
+5V_ALW2 +15V_ALWP
+VCC_TPS51120 PU10B TPS51120RHBR
PR183
3.3 Volt +/-5%
5 Volt +/-5% 47Ohm
pt_r0603
GND10
GND11
3
GND3
GND4
GND5
GND6
GND7
GND8
GND9
pt_c1206_h71
5%
MLCC/+/-10%
MLCC/+/-10%
Maximum current:8.78A
Maximum current:8.72A 2 1
1
PC186
pt_c0603
RB717F
10UF/16V
PD12
PC99
PC185
pt_sot323
1UF/10V
OCP point min. 13.14A 1UF/25V
/*
OCP point min. : 8.82A
34
35
36
37
38
39
40
41
42
pt_c0603
MLCC/+/-10%
2
1
1
D PLACE THESE CAPS CLOSE TO FETS GND GND +DC1_PWR_SRC PC188 D
+PWR_SRC +3.3V_BS 1UF/25V GND
+5V_BS
+DC1_PWR_SRC +3.3V_RTC_LDO PLACE THESE CAPS CLOSE TO FETS pt_c0603
PJP8 MLCC/+/-10%
2
+5V_ALWP
MLCC/+/-10%
pt_c1206_h71
+10V_ALWP
MLCC/+/-10%
1 1 2 2
PC183
pt_c0603
10UF/16V
PC98
1UF/10V
MLCC/+/-10%
MLCC/+/-10%
1
2
pt_c1206_h71
pt_c1206_h71
pt_c0603
10UF/25V
10UF/25V
2200PF/50V
4MM_OPEN_5MIL
0.1UF/50V
MLCC/+/-10%
MLCC/+/-10%
MLCC/+/-10%
MLCC/+/-10%
1
1
PC182
PC175
PC176
PC174
pt_c0603
PC95
/* PR185
0.1UF/50V
1
PC179
pt_c0603
0Ohm
0.1UF/25V
MLCC/+/-10%
pt_c1206_h71
pt_c1206_h71
10UF/25V
10UF/25V
2200PF/50V
5%
CS1
CS2
2
0.1UF/50V
MLCC/+/-10%
MLCC/+/-10%
MLCC/+/-10%
MLCC/+/-10%
1
1
PC171
PC177
PC172
pt_c0603
pt_c0603
PC93
PD18
2
0.1UF/25V
1
PC178
PR177
pt_r0603
0Ohm
BAT54S
21
2
1
PR178
pt_r0603
5%
0Ohm
pt_sot23_philips
5%
2
24
23
22
21
20
19
18
17
1
SI4392DY-T1-E3
PU10A PD19
2
GND GND
8
7
6
5
5
6
7
8
BAT54S
V5FILT
PGND1
CS1
VREG5
VREG3
VIN
CS2
PGND2
3
SI4800BDY
PQ46
PQ44
pt_sot23_philips
D
D
+5V_DL
3
G
25 GND
S
DRVL1
S
+3.3V_DL
+5V_ALWP +5V_DH
26 LL1 DRVL2 16
GND 27 DRVH1 LL2 15 +3.3V_ALWP
1
+5V_VBST +3.3V_DH PC181 PC180
1
2
3
4
4
3
2
1
28 VBST1 TPS51120RHBR DRVH2 14
29 13 +3.3V_VBST PL15 1UF/25V 1UF/25V
PL3 3V_5V_POK 30 EN1 VBST2 +3.3V_ALWP_L pt_c0603 pt_c0603
PGOOD1 EN2 12 1 2
+5V_ALWP_L TONSEL 31 3V_5V_POK MLCC/+/-10% MLCC/+/-10%
2
1 2 TONSEL PGOOD2 11
32 10 3.3UH
SKIPSEL EN3
5
6
7
8
3.3UH 33 9 Irat=8.8A +5V_PMP
GND2 EN5
8
7
6
5
PQ48
FDS6690AS
FDS6676AS
Irat=8.8A pt_inductor_2p_453x394
COMP1
COMP2
TAN/Lf_T=2000hrs_105C/+/-20%
D
VREF2
GND1
PQ43
pt_inductor_2p_453x394
VFB1
VFB2
TAN/Lf_T=2000hrs_105C/+/-20%
D
VO1
VO2
3
pt_c7343d_h118
S
C C
330UF/6.3V
G
1
S
+VCC_TPS51120
PC94
PD20
MLCC/+/-10%
+
1
pt_c0603
PC96
PC173 BAT54
1
2
3
4
5
6
7
8
4
3
2
1
0.1UF/25V
pt_c7343d_h118
1000PF/50V
1
2
3
4
MLCC/+/-10%
1
PC165
pt_c0603
pt_c0603
330UF/6.3V
1
2
0.1UF/25V
+
1
PC163
MLCC/+/-10%
2
PR160
40.2KOhm
/*
GND
1 2
PR159
pt_r0603
1%
2
GND GND GND
5%
0Ohm
2
GND
2
+VCC_TPS51120
1
+5V_VFB
1
/* PR174
MLCC/+/-10%
10KOhm
PR158
pt_r0603
pt_c0603
1KOhm
0.1UF/25V
GND
1
2
PC191
1%
1%
1000PF/50V
PR161
MLCC/+/-10%
MLCC/+/-10%
37 ALWON 1 2
9.76KOhm
1
1% 1
1
PR103
PR182
PC184
12.4KOhm
pt_c0603
pt_c0603
PC97
1000PF/50V
0Ohm GND
1%
pt_r0603
2
2 1 +VCC_TPS51120 5%
43 THERM_STP#
1
PR173
200KOhm
/*
1
+15V_ALWP +15V_ALW
5%
GND PR172
2
GND
PJP18 0Ohm +5V_ALW2 +5V_ALWP
2
2
5% PR163
2
1
1 2 CS1 CS2 23.2KOhm
/* 5%
1 2
PR169
PR167
PR168
5%
0Ohm
0Ohm
1%
5% /*
For debug
2
1
+3.3V_VFB
0Ohm
2MM_OPEN_5mil 1 2
/* PR180 PR181
0Ohm 0Ohm
1
B B
1
PR164 /* +5V_ALWP 5% 5%
1
2
+5V_ALWP +5V_ALW
MLCC/+/-10%
PR162
10KOhm
pt_r0603
pt_c0603
GND 0Ohm /*
0.1UF/25V
1
PC192
1%
PJP7 5% /*
2
2 1
1 1 2 2
+VCC_TPS51120
2
4MM_OPEN_5MIL PR165
MLCC/+/-10%
1
PC187
pt_c0603
/* 0Ohm
1UF/25V
2
47KOhm
PR187
5%
+3.3V_ALWP +3.3V_ALW 5% /*
PR175
/* 5%
0Ohm
2 1 GND GND
PJP17
2
+VCC_TPS51120
1
1 1 2 2
PQ45
1
2
4MM_OPEN_5MIL BSS84LT1G GND

/* TONSEL /*
PR171
5%
0Ohm
2 S 3 PQ50 3
3 D
D
2N7002
2
2
PR188
G
PR170
/* 5%
0Ohm
PQ37 1 PU11
1
2 1
11
37 EC_PWM_2
+3.3V_RTC_LDO FDN340P_NL +3.3V_ALW G 1 A 5
/* PR166 0Ohm 2 S VCC
+3.3V_ALWP
200KOhm 5% 2 B
5% PR186
1
2 3
S
3 D
/*
2
3 GND 4 2 1
2 1 Y
G
PC161
pt_c1206_h71
SN74LVC1G00DCKR 120Ohm
MLCC/+/-10%
11
1
5%
4.7UF/10V
1 2
1
PC160
GND PR176
0.01UF/25V /* 3 100KOhm
D
1
A A
pt_c0603 5% GND GND
THERM_STP# PR94 MLCC/+/-10% PR93 PD10 PQ47
2
4.7KOhm /* 2.2MOhm BAT54 1 2N7002 2

28,37,49,51 RUN_ON
5% 5% /* G /*
PQ23 /* /* 2 S PR179
1
G
2N7002 3V_5V_POK +5V_DL

2
1
2
ALW_PWRGD_3V_5V 37 2 1
/*
2 S
GND
D
0Ohm
pt_r0603
GND GND 5% /*
PROJECT: Lanai 1.2 SHEET 54 OF 68 POWER_SYSTEM 5V_ALW&3.3V_ALW RELEASE DATE : JEFF
5 4 3 2 1
5 4 3 2 1
PR134
200KOhm
1%
D
1 2 D
PR140
210KOhm
1.5 Volt +/-5% 1%
1 2
Design Current: 3.02A PC129 PC35
0.1UF/25V 0.1UF/25V
Maximum current:4.31A pt_c0805_h53 pt_c0805_h53
OCP point min. : 9.37A MLCC/+/-10% MLCC/+/-10%
1 2 +1.5V_BS +1.05V_BS 1 2
1
PD17
2 1 BAT54A 2 1
+PWR_SRC PJP9 pt_sot23_philips
PR31 +5V_SUS /* PR30 1.05 Volt +/-5%
1 2 +DC2_PWR_SRC 0Ohm 0Ohm
1 2 5% 5%
3
4MM_OPEN_5MIL
+1.5V_VBST
pt_c1206_h71
/* MLCC/+/-10%
MLCC/+/-10%
MLCC/+/-10%
pt_c1206_h71
pt_c0603
10UF/25V
10UF/25V
2200PF/50V
0.1UF/50V
MLCC/+/-10%
1 2
1
1
PC122
PC29
PC30
PC26
PC40 PR142 +DC2_PWR_SRC
OCP point min. 11.91A
+1.05V_VBST
MLCC/+/-10%
8
7
6
5
1
PC120
pt_c0603
1UF/10V 9.53KOhm
1UF/10V
(OCP point typ.: 15.71A)
PQ7
pt_c1206_h71
pt_c1206_h71
FDS8880
pt_c0805_h33 1%
2
MLCC/+/-10%
MLCC/+/-10%
D
10UF/25V
2200PF/50V
MLCC/+/-10%
MLCC/+/-10%
MLCC/+/-10%
GND
5
6
7
8
1
pt_c0603
10UF/25V
PC33
PC28
PC32
1
0.1UF/50V
G
S
PC127
PU2
D
1 PGND1 GND1 28
+1.5V_RUN +1.5V_RUN_P +1.5V_PG1
1
2
3
4
2
TI request to change.
G
2 27
S
DRVL1 PGOOD1
3 V5DRV1 VFB1 26 GND
PJP12 PL9 GND 4 25
+1.5V_RUN_P_L TRIP1 V5FILT1 PQ8
4
3
2
1
1 1 2 2 1 2 5 LL1 VOUT1 24
+1.5V_HG 6 23 FDS8880 +1.05V_VCCP_P +1.05V_VCCP
4MM_OPEN_5MIL 1UH DRVH1 TON1 RUN_1.5VO
7 VBST1 EN_PSV1 22
C /* Irat=14.3A RUN_1.05VO 8 21 PJP10 C
pt_inductor_2p_453x394 EN_PSV2 VBST2 +1.05V_HG PL8
9 TON2 DRVH2 20
+1.05V_VCCP_P_L
TAN/Lf_T=2000hrs_105C/+/-20%
10 VOUT2 LL2 19 1 2 1 1 2 2
8
7
6
5
FDS6670AS
11 V5FILT2 TRIP2 18
PQ9
12 17 1UH 4MM_OPEN_5MIL
D
+1.05V_PG2 13 VFB2 V5DRV2 +1.05V_LG

pt_c7343d_h79
+1.5V_RUN_P 16 Irat=14.3A /*
1
PGOOD2 DRVL2
pt_c1206_h35
330UF/2.5V
pt_inductor_2p_453x394
TAN/Lf_T=2000hrs_105C/+/-20%
TAN/Lf_T=2000hrs_105C/+/-20%
0.1UF/10V
MLCC/+/-10%
MLCC/+/-10%
+ G 14 GND2 PGND2 15
1
9
S
PC133
PC136
PC137
PJP11
10UF/6.3V
pt_c0805_h33
pt_c7343d_h79
SN0508073PWR
MLCC/+/-10%
D 5
1
PC118
pt_c1206_h35
pt_c7343d_h79
330UF/2.5V
330UF/2.5V
1UF/10V
1
2
3
4
MLCC/+/-10%
MLCC/+/-10%
4 G 6 + + 1 1 2 2
1
PC125
PC135
PC128
PC124
+1.5V_LG
2
10UF/6.3V
0.1UF/10V
3 7
2 8 +1.05V_VCCP_P 4MM_OPEN_5MIL
+1.5V_V5FILT2_L
/*
1
1
+1.05V_V5FILT2_L
2
S
PQ10
+5V_SUS
GND FDS7088SN3
+1.05V_VCCP_P
+1.5V_V5FILT
+5V_SUS
GND
+1.5V_RUN_P
1
PR130
+1.05V_V5FILT
10Ohm
pt_r0603
MLCC/+/-5%
GND GND
2
2
5%
PC31
39PF/50V
pt_r0603
10Ohm
pt_r0603
11.8KOhm
5%
PR25
PR34
100PF/50V
PC41
MLCC/+/-5%
GND
1
pt_r0603
15KOhm
1%
PR35
0.1UF/10V
MLCC/+/-10%
2
1
PC36
PR131
1%
5.6KOhm
/*
MLCC/+/-10%
0.1UF/10V
1
PC37
1%
/*
2
2
2
2
MLCC/+/-10%
1
PC126
pt_c0603
1UF/10V
2
pt_r0603
29.4KOhm
PR23
1%
1
2
MLCC/+/-10%
1
pt_r0603
15KOhm
pt_c0603
PC39
PR36
1UF/10V
B B
1%
1
2
GND
+1.5V_PG1
51 1.5V_RUN_PWRGD
GND
+1.05V_PG2
51 1.05V_RUN_PWRGD
For debug
PR141
0Ohm
5%
2 1 RUN_1.5VO
37 1.5V_RUN_ON
PR133
0Ohm
5%
2 1 RUN_1.05VO
38 1.05V_RUN_ON
A A
PROJECT: Lanai 1.2 SHEET 55 OF 68 POWER_I/O_1.5VS & 1.05VS RELEASE DATE : JEFF
5 4 3 2 1
5 4 3 2 1
TOTAL POWER=65W
-->3.34A
TABLE3
PIN NAME DIFFERENCES
PIN MAXIM INTERSIL
+VCHGR +PBATT
CHRG_IN
1 GND NC
+DC_IN_SS PR109 +PWR_SRC
10mOhm
3 REF VREF
pt_r2512_4p_h33 PJP1
PQ33 1% PQ3 4 CCS ICOMP
8 D S 1 +DC_IN_SS_X 1 2 1 2 1 S D 8
1 2 5 CCI NC
7 2 4 3 2 7
6 3 4MM_OPEN_5MIL 3 6
/*
6 CCV VCOMP
5 G 4 4 G 5
7 DAC NC
1
D D
PC3 PC2 SI4835BDY-T1-E3
1
SI4835BDY-T1-E3 2200PF/50V 0.1UF/50V +DC_IN_SS
PR21 MLCC/+/-10% pt_c0603
8 IINP ICM
PR110 0Ohm /* MLCC/+/-10%
2
100KOhm 5% /*
11 VDD VDDSMB
PR111 5% PC19
10KOhm 0.22UF/10V
14 BATSEL NC
1
5% pt_c0603
MLCC/+/-10%
15 FBSA VFB
1 2
/* PR112
470KOhm
16 FBSB NC
1 2
3
5%
17 CSIN CSON
D3
2
CHG_CSSN_L
18 CSIP CSOP
2 2 ACAV_IN GND
20 DLO LGATE
G PR116
CHG_CSSP_L 0Ohm
PQ34 pt_r0603
21 LDO VDDP
S 1
RHU002N06 5% GND
23 LX PHASE
2 1
1
24 DHI UGATE
2
25 BST BOOT
RB751V_40
PD16
GND PC15
PR19 0.1UF/25V
1Ohm pt_c0603
"NC" means no-connect
CHG_BST_L
pt_r0603 MLCC/+/-10%
2
PC16 1%
1
1UF/10V 2 1
pt_c0603
MLCC/+/-10%
1 2 CHG_VCC_L
2
MLCC/+/-10%
MLCC/+/-10%
2
pt_c1206_h71
pt_c1206_h71
10UF/25V
10UF/25V
2200PF/50V
PR108
0.1UF/50V
MLCC/+/-10%
MLCC/+/-10%
CHG_LX_L
C C
PC109
PC7
PC6
pt_c0603
PC11
365KOhm PR114
CHG_DHI_L
1% PC8 PC5 33Ohm +5V_ALW
220PF/50V 1UF/25V pt_r0603
MLCC/+/-10% pt_c0805_h57 5%
1
2
MLCC/+/-10%
1
PC1
29
28
27
26
25
24
23
22
1
PU1 1UF/10V Charge Current:4.68A
5
6
7
8
5
6
7
8
pt_c0603 PD3
CSSP
LX
GND3
CSSN
VCC
BST
DCIN
DHI
PQ5
PQ6
SI4800BDY
SI4800BDY
MLCC/+/-10% 1SS355
Discharge current:6.6A
D
GND_CHA 1 21 GND LDO 1 2 /*
GND1 LDO
G
2 20
S
BAT_REF ACIN DLO GND
2
3 REF PGND 19
4 CCS CSIP 18
2
2
4
3
2
1
4
3
2
1
5 CCI CSIN 17
1
PC20 PR120 6 16 +VCHGR +VCHGR PR12

CCV FBSB
BATSEL
0.01UF/25V 49.9KOhm 7 15 LDO GND PR119 1KOhm
DAC FBSA
ACOK
GND2
MLCC/+/-10% 1% 1 2 10mOhm 5%
VDD
SDA
SCL
IINP pt_r2512_4p_h33 pt_r0603
2
MAX8731AETI PR9 PL7 1% /*

1
1
MLCC/+/-10%
1
+VCHGR_L 2 +VCHGR_LX
3300PF/50V
100Ohm 1 1 2
10
11
12
13
14
1
1
PC13
5% PR11
8
9
4 3
10KOhm 5.2UH
PR22 INP 1% Irat=5.5A
1
1
10KOhm PC18 pt_inductor_2p_398x394
5
6
7
8
GND_CHA 5% 0.1UF/10V PR8
MLCC/+/-10%
1
pt_c1206_h71
pt_c1206_h71
pt_c1206_h71
10UF/25V
10UF/25V
PC24 PC21 PC22 MLCC/+/-10% 0Ohm
2
0.1UF/25V
MLCC/+/-10%
MLCC/+/-10%
MLCC/+/-10%
pt_c0603
2 1 ACAV_IN 37,43
1
PC110
PC117
PC111
SI4810BDY-T1-E3
10UF/25V
PC14
1UF/10V 0.01UF/25V 0.01UF/25V 5%
2
PQ4
pt_c0603 MLCC/+/-10% MLCC/+/-10% +5V_ALW PR13 CHG_DLO_L 4 G PC4
MLCC/+/-10% 0Ohm 0.22UF/10V
2
2
S
2
2
5% pt_c0603
2
1
1
PC23 PR125 MLCC/+/-10% PR189
1
0.01UF/25V 8.45KOhm PR10 /* 1.8KOhm
1
2
3
1
MLCC/+/-10% PC17 1% PC10 15.8KOhm 1 2 5%

0.1UF/10V 0.1UF/10V 1% pt_r1206_h26
2
CHG_CSIN_L
TABLE2 MLCC/+/-10% MLCC/+/-10% /*
2
1
MAXIM & INTERSIL BOM DIFFERENCES
2
2
B B
REF DES MAXIM INTERSIL
GND GND
3
PR125 8.45K, 0402, 1% 16.0K, 0402, 1%
CHG_CSIP_L PQ51 3D
PC115 0.01uF No Stuff RHU002N06
GND /*
PC17 0.1uF, 0402, 10V No Stuff 37,59 PBAT_SMBDAT
ACAV_IN 2 2
G
PC24 1.0uF, 0603, 10V No Stuff GND_CHA PR113
0Ohm
37,59 PBAT_SMBCLK 1 S
PR108 365K, 0402, 1% 215K, 0402, 1% pt_r0603
5%
PR8 0, 0402, 5% 10, 0402, 5%
1
2 1
+5V_ALW
PR21 0, 0402, 5% 10, 0402, 5% Maxim request +3.3V_ALW
FOR GPRS IMMUNITY GND
PC4 No Stuff 0.22uF to add PLACE AS CLOSE TO THE
TABLE1
1
PR124 IC AS POSSIBLE
PC19 No Stuff 0.22uF BAT_REF 2 1 PR128 GND_CHA
INP 1 2 PC108 100KOhm GND ADAPTOR (W) TRIP CURRENT (A) PR121 PR123 PR126 PR122
1
PC22 0.01uF No Stuff PR121 100PF/50V 1%

57.6KOhm 0Ohm MLCC/+/-5% PC107 65 3.17 57.6K 13.0K 105 N/A
1
PC18 0.1uF, 0402, 10V No Stuff 1% 5% 0.01UF/16V

2
PC115 MLCC/+/-10% PR117 OC TRIP 90 4.43 51.1K 17.8K 348 33.2K

2
ADAPT_OC 38
PC8 220pF, 0402, 50V No Stuff 0.01UF/16V 100KOhm
MLCC/+/-10% 1% 130 6.43 32.4K 20.5K 100 27.4K
2
PD16 RB751V-40 No Stuff 38 ADAPT_TRIP_SEL 1 2

7.43
GND_CHA GND_CHA 3 150 30.9K 24.9K 432 88.7K
2
D
PC13 3.3nF No Stuff PR122 GND_CHA
33.2KOhm PQ35 200 9.75 19.1K 28K 301 36.5K
PR19 1, 0603, 1% 0, 0603, 5% 1% PR118 1
230 11.28 32.4K 6.49K 115 N/A
1
/* 1MOhm G 2N7002
PU5 2 S
1
MLCC/+/-5%
PR9 100, 0402, 5% 0, 0402, 5% 1%

PR127
100PF/50V
1KOhm
PR123 1 2 1 VOUT1 VCC 8 Note 1: PR122 is populated if ADAPT_TRIP_SET is

1
PC116
1%
13KOhm
/*
PR22 4.7K, 0402, 5% 4.7K, 0402, 5% 2 7

1% V=0.975V,I=3.25A 3
VIN1- VOUT2
6 used to program for the next lower adaptor
/*
VIN1+ VIN2-
PC23 0.01uF 0.01uF
2
4 GND VIN2+ 5 ADAPT_TRIP_SET is floating for the higher

2
A A
PC21 0.01uF 0.01uF LM393DR
adaptor, grounded for the lower adaptor
1
PR126 PC112 PC114

Note 2: 24.9K at PR122 allows the 65W adaptor
PD3 1SS355 No stuff
105Ohm PC113 100PF/50V 100PF/50V setting to switch down to 45W. (now is N/A)
1% 0.01UF/16V MLCC/+/-5% MLCC/+/-5%
2
MLCC/+/-10%
Note 3: PR109 must be 5m ohm instead of 10m ohm
PR12 1K, 0603, 5% No stuff for the 230W adaptor
2
FOR GPRS IMMUNITY PLACE

AS CLOSE TO THE IC AS
GND_CHA POSSIBLE
GND_CHA
GND_CHA
PROJECT: Lanai 1.2 SHEET 57 OF 68 POWER_CHARGER RELEASE DATE : JEFF
5 4 3 2 1
5 4 3 2 1
D 1.25Volt +/-5% PR27 D

200KOhm
Maximum current:1.33A 5%
1 2
OCP point min. : 6.54A PR32
150KOhm
1%
1 2
PC131 PC34
+PWR_SRC 0.1UF/25V 0.1UF/25V
PJP3 pt_c0805_h53 pt_c0805_h53
MLCC/+/-10% MLCC/+/-10%
1 2 +DC3_PWR_SRC 1 2 VGA_1.25V_BS VGA_1.8V_BS 1 2
1.8Volt +/-5%
1 2
Design Current: 6.59A
1
4MM_OPEN_5MIL
pt_c1206_h71
pt_c1206_h71
/* PD8 PR29
MLCC/+/-10%
MLCC/+/-10%
MLCC/+/-10%
PC139
10UF/25V
Maximum current: 9.42A
10UF/25V
PC43
2200PF/50V
BAT54A 0Ohm
0.1UF/50V
MLCC/+/-10%
1
1
pt_c0603
PC47
PC46
+5V_SUS pt_sot23_philips 5% OCP point min. : 16.93A
2 1
2
3
2 1
MLCC/+/-10%
VGA_1.25V_VBST
PC123
pt_c0603
PR135 +DC3_PWR_SRC
1UF/10V
1
0Ohm
+1.8V_VBST
5%
MLCC/+/-10%
5
6
7
8
pt_c1206_h71
pt_c1206_h71
VGA_1.25V_DH
10UF/25V
10UF/25V
2200PF/50V
TI request to change.
MLCC/+/-10%
MLCC/+/-10%
MLCC/+/-10%
1
1
PC138
pt_c0603
PC45
PC44
PC42
+1.25V_SRC_MP PU6 GND PQ13
0.1UF/50V
D
PQ11 FDS8880
1 PGND1 GND1 28
+1.25V_PG1
G
4 5 2 27
S
DRVL1 PGOOD1
G1 Q2 D1
PL10
2
2 1 3 V5DRV1 VFB1 26
1 2 3 6 4 25 +1.25V_V5FILT GND
S1 D1
PC134 TRIP1 V5FILT1
4
3
2
1
5 LL1 VOUT1 24
1UH 2 7 1UF/10V 6 23 +1.8V_SUS
DRVH1 TON1
G2 Q1 D2
VGA_1.25V_L
Irat=14.3A GND pt_c0805_h33 2 PR136 1 +1.8V_SUSP

TAN/Lf_T=2000hrs_105C/+/-20%
C 7 VBST1 EN_PSV1 22 1.25V_RUN_ON 37 C

pt_inductor_2p_453x394 1 8 MLCC/+/-10% 8 21 0Ohm 5% PJP14
S2 D2 EN_PSV2 VBST2 +1.8V_DH PL11
9 TON2 DRVH2 20
+1.8V_SUS_L
pt_c7343d_h75
10 VOUT2 LL2 19 For debug 1 2 1 1 2 2

1
pt_c1206_h35
220UF/2.5V
VGA_1.25V_DL
MLCC/+/-10%
MLCC/+/-10%
+ 11 V5FILT2 TRIP2 18
1
1
PC143
PC140
PC145
FDS6982AS 0.88UH 4MM_OPEN_5MIL

0.1UF/10V
10UF/6.3V
12 VFB2 V5DRV2 17
5
6
7
8
+1.8V_PG2 13 +1.8V_DL PQ12 Irat=17A /*
TAN/Lf_T=2000hrs_105C/+/-20%
TAN/Lf_T=2000hrs_105C/+/-20%
PGOOD2 DRVL2 16
FDS6676AS pt_inductor_2p_453x394
MLCC/+/-10%
14 15
D
GND2 PGND2
pt_c0805_h33
DDR_ON_P PJP13
2
2
PC119
+1.25V_SRC_MP SN0508073PWR
1UF/10V
pt_c7343d_h79
pt_c7343d_h79
+5V_SUS 1 2
1 2
1
+1.8V_V5FILT
330UF/2.5V
330UF/2.5V
+5V_SUS
MLCC/+/-10%
+ +
1
PC144
PC141
PC142
4MM_OPEN_5MIL
0.1UF/10V
1
4
3
2
1
GND
For debug /*
2
+1.8V_SUSP
10Ohm 5%
2
PR137
10Ohm
+1.25V_SRC_MP +1.8V_SUSP
PR28
GND
2
5%
1
14KOhm
pt_r0603
PR132
PC121
39PF/50V
MLCC/+/-5%
GND
1
1
12.4KOhm
1%
PR26
GND
1%
1
pt_r0603
PR143
15KOhm
PC132
100PF/50V
1%
MLCC/+/-5%
1
MLCC/+/-10% /*
MLCC/+/-10%
0.1UF/10V
1
PC25
PC38
Change to low profile
/*
0.1UF/10V
PR138
9.53KOhm
+1.25V_RUN +1.25V_SRC_MP
2
MLCC/+/-10%
MLCC/+/-10%
FOR LAYOUT ISSUE
2
pt_c0603
pt_c0603
1%
PC27
1UF/10V
2
2
pt_r0603
PR129
10KOhm
PC130
GND
1UF/10V
2
PR139
pt_r0603
22.6KOhm
1%
PJP5
1%
2
2
1
1 1 2 2
1
4MM_OPEN_5MIL
/*
GND
GND
B B
0.9Volt +/-5%
Design Current:1.05A No.32
+1.8V_SUSP +5V_ALW +0.9V_P +0.9V_DDR_VTT +3.3V_ALW +3.3V_SUS
PJP6
PJP4 PU3
10 VIN VTT 3 1 1 2 2
1 2 +1.8V_SUSP_VLDOIN&VDDQSNS 2 5
1 2 VLDOIN VTTSNS 2MM_OPEN_5mil
1 VDDQSNS VTTREF 6 No.38
For debug 2MM_OPEN_5mil V_DDR_MCH_REF /*
/* 4
PGND
1
100KOhm
2 1 7 /*
37 0.9V_DDR_VTT_ON S3
PR33
GND1 8
1%
PR41 DDR_ON_P 9
0Ohm 5% S5
GND2 11
1
PC48 PC49 TPS51100DGQ PC51 PC54 PC50
2
37 DDR_ON 2 1
10UF/6.3V 0.1UF/10V 1UF/10V 10UF/6.3V 10UF/6.3V
1
PR38 pt_c0805_h53 MLCC/+/-10% pt_c0603 pt_c0805_h53 pt_c0805_h53
100KOhm
PR24
0Ohm 5% MLCC/+/-10% MLCC/+/-10% MLCC/+/-10% MLCC/+/-10%
2
/*
1%
+1.25V_PG1
For debug 51 1.25V_RUN_PWRGD
2
GND
GND
A +1.8V_PG2 A
37 1.8V_SUS_PWRGD
PROJECT: Lanai 1.2 SHEET 58 OF 68 POWER_VGA_1.25V & DDR & VTT RELEASE DATE : Jeff
5 4 3 2 1
5 4 3 2 1
+3.3V_ALW
ESD DIODES
2
D D
PD7 PD6 PD5 PD4 GND
TDC REQUSET TO CHANGE
DA204U DA204U DA204U DA204U
pt_sot323_rohm pt_sot323_rohm pt_sot323_rohm pt_sot323_rohm
/*
3
+3.3V_ALW +3.3V_ALW
PCON2 +PBATT
P_GND1 10
100KOhm
PR18 /*
2
10KOhm
PC12
PR15
PR20
2200PF/50V
100Ohm
MLCC/+/-10%
MLCC/+/-10%
1 1
1
1
PC9
BATT+_IN
pt_c0603
5%
5%
5%
0.1UF/50V
2 2
3 Z4304 SMB_CLK 1 2
3 Z4305 SMB_DAT PBAT_SMBCLK 37,57
4 4 1 2 PBAT_SMBDAT 37,57
Z4306 BATT_PRES# PR16
2
5 5
SYSPRES# PR17 100Ohm
1
6 6
7 BATT_VOLT 100Ohm 5%
7 BATT1- 5%
8 8 1 2 PBAT_PRES# 38
9 BATT2-
9
1 2 PBAT_ALARM#
P_GND2 11
PR14
BATT_CON_9P 100Ohm
PS_ID_DISABLE# 38
5%
+5V_ALW
2
C C
+5V_ALW
pt_r0603
15KOhm
PR4
+3.3V_ALW
5%
GND
PQ30 2
2
PMBS3904 E
PR5 PD1 GND
1
B 1 10KOhm PR2 DA204U GND
PR7
PD15 5% 10KOhm pt_sot323_rohm
2.2KOhm
C
5%
MBRS2040LT3G 3 5% /* PD2
2
pt_smb_h101 /* DA204U
1
/* PR104 pt_sot323_rohm
3
1 2
100KOhm
1 1
pt_r0603
2
1
5% PQ31
3
G
pt_sot23
1
1 2 PS_ID 37
FDV301N_NL
PR3
3 2 33Ohm
S 2
D3
PL4 5%
1 2
1000Ohm/100MHz
1 2 +DC_IN_SS
pt_l0603 PR1 +DC_IN
FERRITE BEAD(0603)1000OHM/0.1A 33Ohm 1 S D 8
5% 2 7
PL6 /* 3 6
+DCIN_JACK 2 1 4 5
G
2
pt_r0805_h24
pt_c1206_h71
0.1UF/50V
MLCC/+/-10%
MLCC/+/-10%
MLCC/+/-10%
MLCC/+/-10%
1
1
PR106
PC103
PC104
PC100
pt_c0603
pt_c0603
10UF/25V
0.01UF/25V
PQ32
4.7KOhm
60Ohm/100Mhz
0.1UF/50V
1
PC102
5%
PCON1 pt_l1806 FDS6679_NL
B 10 1 MURATA/BLM41PG600SN1L B
P_NC3 1
2
6 P_NC1 2 2
1
7 NP_NC1 3 3
pt_c0805_h53
0.47UF/25V
MLCC/+/-10%
8 NP_NC2 4 4
2
PC101
9 P_NC2 5 5
1
PR107
240KOhm
11 PC105
P_NC4
2
1%
0.1UF/25V
DC_PWR_JACK_5P pt_c0603 PR6
pt_dc_pwr_jack_5p_6hold_lf2 MLCC/+/-10% 0Ohm PQ2 GND
2
2
/* 5% SI2301BDS
1
/* /*
1
2 3
S
3 D
GND
2
G
11
2
PR105
GND 47KOhm
2
5%
PD14
1
VZ0603M260APT CONFIRM JAY EE REQUEST TO
pt_varistor_0603
/* DE-POP
3
1
R1 C
2 B PQ1 GND
37 AC_OFF
DTC115EUA
E pt_umt3_rohm_h39
GND R2 /*
A A
1
GND
PROJECT: Lanai 1.2 SHEET 59 OF 68 POWER_CONNECTOR RELEASE DATE : JEFF
5 4 3 2 1
5 4 3 2 1
GM screw pad
D D
13G021049200DE 13G021049200DE H8
H6 C98D98N
H1 H2 H3 H4
H5 O118X98DO118X98N H7
C256I138D118 CT315B295I158D118 CRT354X315B394D138 CRT337X413B394D138
1
1
ESA1-1A_NUT_M2_H2.5_1 ESA1-1A_NUT_M2_H2.5_2
1
13G021052020DE 13G021052020DE CPU
H10 H12 H13 H14 H15 H30 H31 H32
H9 H11
O47X31DO47X31N RT197X413D91 CT315B394I158D138 CT315B394I158D138 CT295B276I158D138 CT295B276I162D142 CT295B276I162D142 CT295B276DO138X154
ESA1-1A_NUT_M2_H7 ESA1-1A_NUT_M2_H7_2
1
C C
13G021049200DE 13G021052010DE
H17 H18 H20 H33 H21
CT236B217D102 CT236B217D102 CT138B295D118
ESA1-1A_NUT_M2_H2.5_3 ESA1-1A_NUT_M2_H8
SATA
1
Header2 13G021052030DE
B B
H24 H25 H34 H26 H35 H27 H28 H36 H29

CRT335X386B276D138 ESA1-1A_NUT_H0.4 ESA1-1A_NUT_H0.4 CRT394X413B394D138 CRT394X413B394D138 O43X98DO20X75 CT315B394I158D138 CT315B394I158D138 crt413x394b394d138
1
1
H37
SPRING1 O43X98DO20X75
/* EMI_SPRING_PAD
1
11
A A
PROJECT: Lanai 1.2 SHEET 60 OF 68 SCREW PAD RELEASE DATE : Sean Kuo
5 4 3 2 1
5 4 3 2 1
ASUS CONFIDENTIAL
MODEL NAME : Elsa
D D
Lanai:Modem Board
C C
RJ11 BOARD
control signals WtoB Jack

2P 2P
B B
REV : 1.1(DELL: X01)
A A
PROJECT: Lanai 1.2 SHEET 64 OF 68 BLOCK DIAGRAM RELEASE DATE : Stanly_Hsu
5 4 3 2 1
A B C D E
1 1
Irat=0.2A ML1 470Ohm MCON1

MCON2 RJ_TIP 1 2 P_GND1 5
3 1 RJ_TIP 3
SIDE1 1 MURATA/BLM18RK471SN1D RJ_TIP_R NP_NC1
1 1
2 4 2 RJ_RING 2
SIDE2 2 RJ_RING_R 2 2
Irat=0.2A ML2 470Ohm 4
RJ_RING NP_NC2
MC1
MC2
WTOB_CON_2P 1 2 6
P_GND2
pt_c1808_h65
pt_c1808_h65
MOLEX/53398-0271
MLCC/+/-10%
MLCC/+/-10%
1
1
MURATA/BLM18RK471SN1D
MODULAR_JACK_2P
330PF/3KV
330PF/3KV
2
2
JOHANSON is
MGND MGND
MH2 MH1
not in the QVL
C276D165 CT217BDO91X106 No. 1.
1
1
3 3
MGND MGND
4 4
5 5
PROJECT: Lanai 1.2 SHEET 65 OF 68 RJ-11 CONN RELEASE DATE : Stanly_Hsu
A B C D E
A B C D E
ASUS CONFIDENTIAL
MODEL NAME : Elsa
1
PCB NO : ??? 1
ASUS P/N : ???
2 2
Lanai PP2 USB Board
3 3
REV : 1.1(DELL: X01)
4 4
5 MB PCB 5
Part Number Description
BOM NO. ???
DA800004H0L PCB 00B LA-3071P REV0 M/B
PCB P/N: ???
PROJECT: Lanai 1.2 SHEET 67 OF 68 Cover Page RELEASE DATE : Terry_Lin
A B C D E
A B C D E
External USB PORT hookup reference. Your design may

need more or less external ports and may be mapped
differently .
UICH_USBP0- USBP0_D-
3
1 1
UL2 MURATA/DLW21SN900SQ2L USB daughter board connector
Screw hole
90OHM/100MHz
UICH_USBP0+ USBP0_D+ UCON2 UH2 C244DO134X150
/*
SUYIN/127150FA010G509ZR
2
1
1 2 11 NP_NC1 UGND
UR3 0Ohm 5% UICH_USBP1- 1 2 U+USB_SIDE_PWR
UICH_USBP1+ 1 2
1 2 3 3 4 4
UR4 0Ohm 5% UH1 C244D134
5 5 6 6
UICH_USBP1- USBP1_D- UICH_USBP0- 7 8 1
7 8
3
UICH_USBP0+ 9 10 UGND
UL1 MURATA/DLW21SN900SQ2L 9 10
12 NP_NC2
90OHM/100MHz
UICH_USBP1+ /* USBP1_D+ BTOB_CON_10P
1
2
1 2
UR1 0Ohm 5%
1 2 UGND UGND
UR2 0Ohm 5%
2 2
UCON1
Place one 150uF cap by each TYCO/1759528-1
USB connector U+USB_SIDE_PWR 1
USBP0_D- V1+
2 DATA1_L
USBP0_D+ 3 DATA1_H
P_GND1
P_GND2
4 GND1
U+USB_SIDE_PWR
1
UC2 USB_CON_1X4P
0.1UF/10V
5
6
Platforms should put in PADS for the USB chokes if they
1
MLCC/+/-10%
2
have the room. Chokes should be NOPOP. + +
UCE1 UCE2
150UF/6.3V 150UF/6.3V
pt_c7343d_h79 pt_c7343d_h79 UGND
/*
2
UU1 UGND
USBP0_D+ 1 6 USBP1_D+ UGND UGND
3 UCON3 3
2 5 U+USB_SIDE_PWR TYCO/1759528-1
U+USB_SIDE_PWR 1
USBP1_D- V1+
2 DATA1_L
USBP1_D+ 3 DATA1_H
P_GND1
P_GND2
USBP0_D- 3 4 USBP1_D- 4 GND1
1
SRV05-4
/* UC1
0.1UF/10V USB_CON_1X4P
MLCC/+/-10%
5
6
UGND
UGND
UGND
Each channel is 1A
4 4
Place ESD diodes as close as USB connector. Semtech Consult you ESD Engineer if you think you may need to
SRV05-4 can also be used but the Philips IP42220CZ6 have add ESD Supression Components to your USB lines.
a lower input C ( 1pf vs 3pf ). Add PADS ONLY until proven diodes are really needed.
5 5
PROJECT: Lanai 1.2 SHEET 68 OF 68 USB PORT ( SINGLE * 2 ) RELEASE DATE : Terry_Lin
A B C D E

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ASUS P/N : ???

Lanai UMA Schematics Document

LANAI: UMA CLOCK

D POWER POWER PG 57 Merom POWER D

CON. CHARGER POWER VCORE PG 53

Panel Connector LVDS 533/667 MHZ DDR II

Pg# Description DNI LIST Pg# Description DNI LIST

01 Cover Page 63 POWER CIRCUIT CHANGE LIST

02 Schematic Block Diagram 64 Modem board cover page

21 Clock Generator ( CK410M+LP )

Footprint Definition PCI TABLE

(EHCI#1) (Single port , in USB BD)

ICH8-9 WWAN / Mini Card

Note : No USB for WLAN

+3.3V_SUS +3.3V_SUS +3.3V_RUN

2.2K 2.2K 2.2K 2.2K

TPS51120 ISL6260C SN0508073 SN0508073

SI4800BDY BAT54S SI4800BDY FDS6612A SI4800BDY

A5 C7 R164 CPU_TEST3 C24 Y1 COMP3 from ICH8 to IMVP6 to CPU.

FSB BCLK BSEL2 BSEL1 BSEL0 COMP0

R161 Comp0,2 connect with Zo=27.4ohm, Comp1,3

length shorter than 0.5". Trace should be

AB17 K23 AE11

MLCC/+/-20% MLCC/+/-20% MLCC/+/-20% MLCC/+/-20% MLCC/+/-20% MLCC/+/-20% L6 VSS070 VSS151 AE19

MLCC/+/-20% MLCC/+/-20% MLCC/+/-20% MLCC/+/-20% MLCC/+/-20% MLCC/+/-20%

+VCC_CORE Route VCCSENSE and VSSSENSE

C381 C380 C404 C193 C405 C124

A 220UF/2V 220UF/2V 220UF/2V 220UF/2V 220UF/2V 220UF/2V A

H_D#17 W10 H20 H_A#21

N5 H_D#_22 H_A#_26 J19

H_D#24 W6 E19 H_A#28

R366 C371 H_D#25 W9 B17 H_A#29

Y9 H_D#_28 H_A#_32 C18

P4 H_D#_29 H_A#_33 A19

R129 R130 H_D#44 AC6 K7

AJ9 H_D#_48 H_TRDY# B7 H_TRDY# 7

H_RCOMP trace should be AJ2 H_D#_59 H_DSTBN#_1 K3 H_DSTBN#1 7

H_REQ#_3 H13 H_REQ#3 7

C108 C109 R352 BK16 R110 E51 AH49

R355 4.02KOhm 1% /* CFG9

2 1 C20 CFG_9 DMI_TXP_0 AJ47 DMI_MTX_IRX_P0 16 PEG_TX_7 Y47

R359 2 1 4.02KOhm 1% /* CFG16 M20 R0933,R0937 AE50

PM_EXTTS#1 J36 E36 1 T11 MLCC/+/-10% 1% R327 1 2 10KOhm 5% /* LCTLA_CLK No.2

17,51 ICH_PWRGD AW49 PWROK 1 2

NC_1 CL_PWROK ICH_CL_PWROK 17,37

T22 1 BK1 PCI Express Low=Reveise Lane

R358 100Ohm 5% Low=No SDVO Device Present

AV13 SA_DQ_32 SA_MA_0 BJ19 BK13 SB_DQ_32 SB_MA_0 BC18

DDR_A_D45 AW9 BJ16 DDR_A_MA13 DDR_B_D45 BK10 BG13 DDR_B_MA13

C VCC_SM_14 VCC_AXG_NCTF_39 Layout Note: VCC_NCTF_42 VSS_SCB6 C

VCC_SM_18 VCC_AXG_NCTF_43 VCC_NCTF_46

VCC AXM NCTF

VCC_AXG_23 VCC_SM_LF2 VCCSM_LF3 +/-20% pt_c0805_h53 pt_c0805_h53

L11 180Ohm R102 0Ohm 5% pt_r0603

+VCCA_DPLL 1 2 +VCCA_DPLLB +3.3V_RUN AT23 +VCC_AXD_L 1 2 +VCC_AXD_R 1 2

+VCC_MPLL_L C121 JUMP AU18

C382 MLCC/+/-10% JP7