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STM32L4串行音频接口模块 (SAI) 介绍
STM32L4串行音频接口模块 (SAI) 介绍
SAIx
APB Interface
SYNC OUT
Sync Out
Sub-Block A
SAI_CK_A
Clock generator Sub-Block A FIFO Serial Interface FS_A
8 x 32b SCK_A
IO Line Management
PLL_P SD_A
MCLK_A
PLLSAI1_P
PLLSAI2_P
Sub-Block B FS_B
SAIxEXTCLK
SCK_B
Clock generator Sub-Block B FIFO Serial Interface
8 x 32b SD_B
SAI_CK_B MCLK_B
SYNC IN
Sync In
APB Interface
S
S
T
AI
M
32
L4
In
76
Te
ch
Th
ni
ca
l
Tr
e
ai
Sy
st
SYNCIO LineSYNC SYNCIO LineSYNC
INManagementOUT INManagementOUT
47
SAI: Internal Synchronization examples (1/3)
• Synchronization of 2 sub-blocks Interrupt Request TX or RX - MASTER DMA
Request
SAIx
APB Interface
Sync Out
Sub-Block A
SAI_CK_A
Clock generator Sub-Block A FIFO Serial FS_A (O) SCK_A (O) SD_A (I/O)
8 x 32b Interface MCLK_A (O)
Sync In
APB Interface
SYNC OUT
IO Line Management
• SLAVE full-duplex or dual lane
SYNC IN
48
SAI: External Synchronization examples (2/3)
• Synchronization of 2 SAIs
Interrupt TX or RX - SLAVE DMA
Request Request
SAI2
APB Interface
Sync Out
Sub-Block A
8 x 32b
• Up to four data lanes can work FS2_B SCK2_B SD2_B (IO) MCLK2_B
simultaneously Sub-Block B
TX or RX - SLAVE DMA
Request Request
STM32L476/486
Interrupt
Request
TX or RX - MASTER DMA
Request
Synchro !!!
SAI1
APB Interface
Sub-Block A
Sync In
APB Interface
F
FF = MCLK FSCK
256 FFS =
FRL + 1
FSÆI_CK (1)
SF =
MCLK 2 × MCKDIV FSC = FSÆI_CK
K
(1)
When MCKDIV = 0 FMCLK = FSAI_CK
• Data format:
• The data register must contain CS,U and V bits, plus the data
X Y Z Y X Y X Y Z Y
M Ch A W Ch B B Ch A W Ch B M Ch A W Ch B M Ch A W Ch B B Ch A W Ch B
Sub-frame Sub-frame
• Preambles
• The preambles are ‘violating’ the biphase-mark code rules
0 1 2 3
1 UI 2 UI 3 UI 4 UI 5 UI 6 UI 7 UI 8 UI
Previous half-bit = 0
Preamble “B”
Previous half-bit =
Missing Transitions !!!
1 Previous half-bit
=0 Preamble “M”
Previous half-bit = 1
Previous half-bit = 0
02/07/2015
Previous half-bit = 1
STM32F7xx Preamble “W”
Technical Training
66
AC’97 protocol(1/2)
• The SAI is able to work as an AC’97 link controller.
– To select the AC 97 protocol, set bit PRTCFG[1:0] in the
SAI_xCR1 register to 10.
• The number of slot is fixed to 13 slots:
– Tag slot :slot 0 (16-bit),
– Data slots: slot 1 to slot 12 (20-bit)
€Bit FBOFF[5:0] in the SAI_xSLOTR register is ignored
• The frame length is fixed to 256-bit
€ The SAI_xFRCR register is ignored
FS (SYNC)
€This detection and flag assertion can detect glitches on the SCK
Clock/FS due to a noisy environment
02/07/2015 STM32L476 Technical Training 69
Overrun/Underrun handling
• The FIFO overrun or underrun errors occupy the same
bit: OVRUDR
• The SAI guarantees the data alignment even if underrun
overrun occurs
• Example : FIFO Overrun on Slot 1
MSb
MSb
LSb
LSb
72