Beyond UVM Registers

Better, Faster, Smarter

Rich Edelman, Bhushan Safi
Mentor Graphics, US, India

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What are UVM Registers good for?
• Standard
– Runs on all the simulators
• High level abstraction
– Test can be “almost C code” or device driver-like
– Test doesn’t have to change
• If register address changes
• If register bit arrangements change
• If registers move into different “blocks”

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Does the UVM Register have issues?
Lines of Register Register
Code Size Files
• Complexity
Code Files LOC
UVM 1.2 26/158 22k/78k 16% 28%
– It’s a lot of the UVM UVM 1.1d 26/138 22k/69k 19% 32%

• Doc size (about 26% of the user guide)

• Code size (about 30% of the code base)
– VPI
– Generator – XML/CSV input
• RAM Size – modeling a 32 bit register with classes is
expensive
• Modeling Quirky Registers
• Transparency – what you see is what you get
• Monitoring DUT value changes can be hard

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 Possible solutions
• Make classes more efficient - hard
• Make code base less complex and more transparent
- hard
• Don’t use UVM Registers – non-starter
• Think about registers again – takes time

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Why do UVM Register Verification?
• Registers are an abstraction
– Register tests
– Register constraints
– DUT operation modes controlled by registers
– Register tests are “portable”
– “Automatic” register function scoreboarding
– Built-in register tests
• Others ….

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 Register Model
• typedef struct packed {
– logic [2:0] a;
– logic [3:0] b;
• } REGA_t;

• interface REGA;
– register_types::REGA_t value;
• endinterface

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 Register Tests
class read_registers extends uvm_sequence#(bus_transaction);
virtual REGA rega;
task body();
bus_transaction t;
rega.value.a = 12;
rega.value.b = 17;
t = new(“item”);
t.data = rega.value;
t.addr = rega.get_address();
t.rw = 1;
start_item(t);
finish_item(t);
endtask
endclass

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 Register Monitor
• Each register in the DUT has a “shadow” or model in
the testbench.
• The model is bound to the actual register values in
the DUT using SystemVerilog ‘bind’.
• All updates to the DUT register are immediately
reflected in the model.
• Backdoor loads are accomplished using this bound
model and do not require VPI.

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 Register Scoreboard – Is my register
working?
• Scoreboard – is the functionality correct?
– Actual DUT register value always immediately available
– Model desired behavior using SystemVerilog
– Compare desired behavior against observed
• write()
• read()
• Causes a new value to be predicted.
• Implement any access routine
– peek()/poke()/set()/get()
• Use raw struct field access

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 Modeling Quirky Registers
• Quirky registers have special behavior.
– Clear on Read, Write Once
– ID Registers, FIFO Registers, Coherent Registers, Broadcast
Registers.
• Implement using SystemVerilog. Just write the code.
– It is NOT hard code to write.
– Creating a generic framework for a library that supports all
kinds of Quirky Registers IS hard.
• Callbacks, pre_ and post_ routines, complex Boolean equations.

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 Register Functional Coverage
• Write the covergroup
• Sample the register
• Sample the register fields
• Sample other registers and other register fields

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 Conclusions
• UVM Register tests and models are useful and
powerful
– They should be used as widely as possible
– They should be simplified and optimized for speed and
space
• The model
• The test
• The underlying modeling infrastructure
• The proposed ideas are a good start to thinking
differently about UVM Register tests and models.
– But are not yet complete.

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 Questions?

rich_edelman@mentor.com
bhushan_safi@mentor.com

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