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Conversores Adc PDF
Conversores Adc PDF
D I G I TA L E L E C T R O N I C S I I C O U R S E
U P T C S O G AM O S O FAC U LT Y
1
1. Analog-to-Digital Conversion
Fourier
Frequency
Domain
Time
Domain
0 1 0 0 0 1 01 1 1 0 0 1 0 10
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ADC
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Many ICs can perform both functions on a single chip and include two or
more channels. For audio applications, the AD1871 is an example of a stereo
audio ADC.
1011..01
1011..01
vi(t) C vc(t)
𝑣𝑖(𝑡)
Charge 𝑖𝑡 = 𝑒−𝑡 𝑅𝐶 V I
𝑅 vi i0
𝑞 𝑡 = 𝑣𝑖 𝑡 𝐶 1 − 𝑒 −𝑡 𝑅𝐶
vc ic
𝑞(𝑡)
∆𝑣𝑐 = = 𝑣𝑖 𝑡 1 − 𝑒 −𝑡 𝑅𝐶
𝐶 t t
𝑣𝑖 (𝑡 ) v I
Discharge 𝑖 𝑡 =
𝑅
𝑒 −𝑡 𝑅𝐶 vi i0
vc
𝑞 𝑡 = 𝑣𝑖 𝑡 𝐶 𝑒 −𝑡 𝑅𝐶 ic
∆𝑣𝑐 = 𝑞(𝑡) = 𝑣𝑖 𝑡 𝑒 −𝑡 𝑅𝐶
𝐶 t t
AD/DA Converters. School of Electronic Engineering, UPTC Wilson Javier Perez H. 9
2. Sample & Hold
Tm R
vi(t) C vc(t)
P-Channel JFET
IN OUT
Tm t
v H
s s H
s H
H
s
s H
Tm t
V
vi
v H vc
s s H
t
v
s H vi
vc
H
s
s H
t
Tm t
101100
110101
011001
101110
…
Analog Sampled Sampled &Hold Encoded
Signal Signal Signal Digital
(Digital Signal) Values
Tm
Sampling Pulses
AD/DA Converters. School of Electronic Engineering, UPTC Wilson Javier Perez H. 19
3. Quantization
Tm
Sampling Pulses
AD/DA Converters. School of Electronic Engineering, UPTC Wilson Javier Perez H. 2
0
3. Quantization
V
1-bit resolution with two
levels of Quantization
Quantized
Signal
Quantization
Threshold
0
t
Tm
Sampling Pulses
AD/DA Converters. School of Electronic Engineering, UPTC Wilson Javier Perez H. 21
3. Quantization
V
1-bit resolution with two
levels of Quantization
Quantized
Signal
Quantization
Threshold
0
t
Tm
Sampling Pulses
AD/DA Converters. School of Electronic Engineering, UPTC Wilson Javier Perez H. 2
2
3. Quantization
V
2-bit resolution with four
levels of Quantization
11
Quantized
Signal
10
01
00
t
Tm
Sampling Pulses
AD/DA Converters. School of Electronic Engineering, UPTC Wilson Javier Perez H. 2
3
3. Quantization
V
3-bit resolution with eight
levels of Quantization
111
110
Quantized
101
Signal
100
011
010
001
000
t
Tm
Sampling Pulses
AD/DA Converters. School of Electronic Engineering, UPTC Wilson Javier Perez H. 24
3. Quantization
V
4-bit resolution with sixteen
1111 levels of Quantization
1110
1101
1100
1011
1010
1001
1000 Quantized
0111 Signal
0110
0101
0100
0011
0010
0001
0000
t
Tm
Sampling Pulses
AD/DA Converters. School of Electronic Engineering, UPTC Wilson Javier Perez H. 2
5
3. Quantization
V
4-bit resolution with sixteen
1111 levels of Quantization
1110
1101
1100
1011
1010
1001 Quantized
1000 Signal
0111
0110
0101
0100
0011
0010
0001
0000
t
Tm
Sampling Pulses
AD/DA Converters. School of Electronic Engineering, UPTC Wilson Javier Perez H. 26
3. Quantization
True
Signal
Alias
Signal
To understand the need for an anti-aliasing filter, you need to understand the
sampling theorem which essentially states:
If the signal is sampled less than this, the recovery process will produce
frequencies that are entirely different than in the original signal.
These “masquerading” signals are called aliases.
Most signals have higher frequency harmonic and noise. For most ADCs, the
sampling and filter cutoff frequencies are selected to be able to reconstruct the
desired signal without including unnecessary harmonics and noise.
+VREF
Op-amp
a) The flash ADC: R comparators
Input from +
sample- –
and-hold
R + Priority
– encoder
R 7
+
6
–
The flash ADC uses a series high-speed R
5
4
1 D0 Parallel
+
comparators that compare the input – 3
2
4
D1 binary
D output
2
binary number. R
+
Enable
– pulses
Answer 1023
AD/DA Converters. School of Electronic Engineering, UPTC Wilson Javier Perez H. 3
3
5. Analog-to-Digital Conversion Methods
CLK
+
V
−
C
Comparator
Counter
En
t
Clear
Slope Control
Generator Reset Logic
En Latches
Tm
(Sampling Pulses)
D7 D6 D5 D4 D3 D2 D1 D0
Binary Output
V
The single-slope ADC (Analog Slope)
Vmax
Tm
V
The single-slope ADC (Analog Slope)
Vmax
Tm
V
The single-slope ADC (Analog Slope)
Vmax
Tm
V
The single-slope ADC (Analog Slope)
Vmax
Tm
CLK
+
V
−
C
Comparator
Counter
En
t
Clear
DAC Control
Logic
En Latches
Tm
(Sampling Pulses)
D7 D6 D5 D4 D3 D2 D1 D0
Binary Output
C
+ -
𝑣𝐶(t)
R
𝑖𝐶 (t)
+ - + -
𝑣𝑖 (t) +
C Vx=0 𝑣𝑜(t)
𝑖𝑅 (t)
-
𝑖𝐶 (t)
𝒕
0
𝑑𝑣𝐶(𝑡) 𝑣 − 𝑉𝑥 𝑣 𝒗𝒊
𝑖𝐶 𝑡 = 𝐶 𝑖𝑅 = 𝑖 = 𝑖 𝒎=−
𝑹𝑪
𝑑𝑡 𝑅 𝑅 𝒗
1 𝑉𝑥 = 0, por lo tanto 𝑖𝑅 = 𝑖𝐶
𝑣𝐶 𝑡 = 𝑖𝐶 𝑡 𝑑𝑡 Constante
𝐶 a trozos
1 1 𝑣𝑖 𝑣𝑖
𝑣 = −𝑣 = − 𝑖 𝑑𝑡 = − 𝑑𝑡 = − 𝑡
𝑂 𝐶
𝐶 𝐶 𝐶𝑅 𝑅𝐶
AD/DA Converters.
Electronics School
Engineering of –
School Electronic Engineering,
Eng. Wilson Javier PerezUPTC
H. Wilson Javier Perez H. 45
AD/DA Converters. School of Electronic Engineering, UPTC Wilson Javier Perez H. 46
AD/DA Converters. School of Electronic Engineering, UPTC Wilson Javier Perez H. 47
1 0 0 0
(20)
(1) (5)
CS ADC0804 INTR
(2) (19)
RD CLK R (out)
(3) (18)
WR D0
CLK IN
(4) (17)
D1
The completion is signaled by the
Analog Vin+
(6) (16)
D2 INTR line going LOW.
(7) (15) Digital
input Vin– D3
(9) (14) data
REF/2 D4
(13) output
D5
(12)
D6
(11)
D7
(8) (10)
ANLG DGTL
GND GND
Summing
point
Analog + ∆ Quantized output
1-bit
input Σ Integrator
quantizer
is a single bit
signal – data stream.
DAC
One option for the sigma-delta method is to count the one-bit quantized output
for a set interval. The output of the counter is latched with the parallel binary
code.
Summing
point
Analog + ∆ 1-bit n-bit Binary code
Σ Integrator Latch
output
input quantizer counter
signal – . .
. .
. .
. .
. .
1-bit
DAC
Sigma-delta ADCs can have high resolution and have advantages for rejecting
noise signals (such as 60 Hz power line interference).
They are available in ICs with internal programmable amplifiers. For these
reasons, they are widely used in instrumentation applications.
AD/DA Converters. School of Electronic Engineering, UPTC Wilson Javier Perez H. 58
5. Analog-to-Digital Conversion Methods
Sigma-Delta Converter
If the wave amplitude, accumulated over a given sample period is greater than
the previous sample period, the converter generates “1”.
This generates a type of high density pulse modulation with positive half-waves
represented by many consecutive “1s”, while the negative half-waves produce
many “0s” in the sequence.