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AD – DA Converters

D I G I TA L E L E C T R O N I C S I I C O U R S E

SCHOOL OF ELECTRONIC ENGINEERING

U P T C S O G AM O S O FAC U LT Y

1
1. Analog-to-Digital Conversion

Fourier

Frequency
Domain

Time
Domain

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2. Sampling

Most input signals to an electronic system start out as analog signals.


For processing, the signal is normally converted to a digital signal by sampling
the input.

Before sampling, the analog


input must be filtered with
Analog
a low-pass anti-aliasing input Sampling
signal circuit
filter.
The filter eliminates Sampling
pulses

frequencies that exceed a


certain limit that is SAMPLE
determined by the sampling
rate.
Sampled
version of
input signal

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2. Sample & Hold and ADC

Following the anti-aliasing filter, is the sample-and-hold circuit and the


analog-to-digital converter. At this point, the original analog signal has been
converted to a digital signal.

HOLD (Ideal Representation)


Samples held
for one clock
pulse

0 1 0 0 0 1 01 1 1 0 0 1 0 10

.
.
.
.
ADC

.
.
.
.
.
.
.
.
.
.
.
Many ICs can perform both functions on a single chip and include two or
more channels. For audio applications, the AD1871 is an example of a stereo
audio ADC.

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1. Analog-to-Digital Conversion

Sample Hold Quantize Codification

1011..01

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1. Analog-to-Digital Conversion

Sample Hold Quantize Codification

1011..01

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2. Sample & Hold
Tm
R

vi(t) C vc(t)

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2. Sample & Hold
Tm
Sample R

vi(t) Hold C vc(t)

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2. Sample & Hold
Tm
R
Let´s Assuming
vi(t) C vc(t) 𝑞 0 =0

𝑣𝑖(𝑡)
Charge 𝑖𝑡 = 𝑒−𝑡 𝑅𝐶 V I
𝑅 vi i0
𝑞 𝑡 = 𝑣𝑖 𝑡 𝐶 1 − 𝑒 −𝑡 𝑅𝐶
vc ic
𝑞(𝑡)
∆𝑣𝑐 = = 𝑣𝑖 𝑡 1 − 𝑒 −𝑡 𝑅𝐶
𝐶 t t
𝑣𝑖 (𝑡 ) v I
Discharge 𝑖 𝑡 =
𝑅
𝑒 −𝑡 𝑅𝐶 vi i0
vc
𝑞 𝑡 = 𝑣𝑖 𝑡 𝐶 𝑒 −𝑡 𝑅𝐶 ic

∆𝑣𝑐 = 𝑞(𝑡) = 𝑣𝑖 𝑡 𝑒 −𝑡 𝑅𝐶
𝐶 t t
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2. Sample & Hold

Tm R

vi(t) C vc(t)

P-Channel JFET

Transmission Gate (CMOS Switch)


A

IN OUT

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2. Sample & Hold

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2. Sample & Hold

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2. Sample & Hold

Tm t

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2. Sample & Hold

v H
s s H

s H
H
s
s H

Tm t

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2. Sample & Hold

V
vi

v H vc
s s H
t
v
s H vi
vc
H
s
s H
t

Tm t

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1. Analog-to-Digital Conversion

X(t) Sample & X(n) Xq(n) 101100…


Quantifier Encoder
Hold

Analog Discrete-Time Quantized Digital


World Signal Signal World

101100
110101
011001
101110

Analog Sampled Sampled &Hold Encoded
Signal Signal Signal Digital
(Digital Signal) Values

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1. Analog-to-Digital Conversion

Digital Signal Processing System

Analog Digital Signal Analog


ADC DAC
Signal Processing Signal

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3. Quantization

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3. Quantization

Tm
Sampling Pulses
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3. Quantization

Tm
Sampling Pulses
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0
3. Quantization

V
1-bit resolution with two
levels of Quantization

Quantized
Signal

Quantization
Threshold

0
t

Tm
Sampling Pulses
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3. Quantization

V
1-bit resolution with two
levels of Quantization

Quantized
Signal

Quantization
Threshold

0
t

Tm
Sampling Pulses
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2
3. Quantization

V
2-bit resolution with four
levels of Quantization

11

Quantized
Signal
10

01

00
t

Tm
Sampling Pulses
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3
3. Quantization

V
3-bit resolution with eight
levels of Quantization

111

110
Quantized
101
Signal
100
011
010
001
000
t

Tm
Sampling Pulses
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3. Quantization

V
4-bit resolution with sixteen
1111 levels of Quantization
1110
1101
1100
1011
1010
1001
1000 Quantized
0111 Signal
0110
0101
0100
0011
0010
0001
0000
t

Tm
Sampling Pulses
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3. Quantization

V
4-bit resolution with sixteen
1111 levels of Quantization
1110
1101
1100
1011
1010
1001 Quantized
1000 Signal
0111
0110
0101
0100
0011
0010
0001
0000
t

Tm
Sampling Pulses
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3. Quantization

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4. Aliasing Problem

True
Signal

Alias
Signal

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4. Anti-Aliasing Filter

To understand the need for an anti-aliasing filter, you need to understand the
sampling theorem which essentially states:

In order to recover a signal, the sampling rate must be greater


than twice the highest frequency in the signal.

Stated as an equation, fsample > 2fa(max)


where fsample = sampling frequency
fa(max) = highest harmonic in the analog signal

If the signal is sampled less than this, the recovery process will produce
frequencies that are entirely different than in the original signal.
These “masquerading” signals are called aliases.

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4. Anti-Aliasing Filter

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0
4. Anti-Aliasing Filter

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1
4. Anti-Aliasing Filter

Most signals have higher frequency harmonic and noise. For most ADCs, the
sampling and filter cutoff frequencies are selected to be able to reconstruct the
desired signal without including unnecessary harmonics and noise.

An example of a reasonable sampling rate is in a digital audio CD. For audio


CDs, sampling is done at 44.1 kHz because audio frequencies above 20 kHz
are not detectable by the ear.

Question What cutoff frequency should


an anti-aliasing filter have for a
digital audio CD?

Answer Less than 22.05 kHz.

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2
5. Analog-to-Digital Conversion Methods

+VREF
Op-amp
a) The flash ADC: R comparators

Input from +
sample- –
and-hold
R + Priority
– encoder

R 7
+
6

The flash ADC uses a series high-speed R
5
4
1 D0 Parallel
+
comparators that compare the input – 3
2
4
D1 binary
D output
2

with reference voltages. Flash ADCs


2
R + 1

are fast but require 2n – 1 comparators – 0 EN


R
to convert an analog input to an n-bit +

binary number. R
+
Enable
– pulses

Question How many comparators are needed by a 10-bit flash ADC?

Answer 1023
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3
5. Analog-to-Digital Conversion Methods

a) The single-slope ADC (Analog Slope):


Analog
Input

CLK
+
V

C
Comparator
Counter
En
t
Clear

Slope Control
Generator Reset Logic

En Latches

Tm
(Sampling Pulses)
D7 D6 D5 D4 D3 D2 D1 D0
Binary Output

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5. Analog-to-Digital Conversion Methods

V
The single-slope ADC (Analog Slope)
Vmax

Tm

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5
5. Analog-to-Digital Conversion Methods

V
The single-slope ADC (Analog Slope)
Vmax

Tm

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5. Analog-to-Digital Conversion Methods

V
The single-slope ADC (Analog Slope)
Vmax

Tm

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5. Analog-to-Digital Conversion Methods

V
The single-slope ADC (Analog Slope)
Vmax

Tm

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5. Analog-to-Digital Conversion Methods

a) The single-slope ADC (Digital Slope):


Analog
Input

CLK
+
V

C
Comparator
Counter
En
t
Clear

DAC Control
Logic

En Latches
Tm
(Sampling Pulses)

D7 D6 D5 D4 D3 D2 D1 D0
Binary Output

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5. Analog-to-Digital Conversion Methods

C
+ -
𝑣𝐶(t)
R
𝑖𝐶 (t)
+ - + -
𝑣𝑖 (t) +
C Vx=0 𝑣𝑜(t)
𝑖𝑅 (t)
-
𝑖𝐶 (t)

𝒕
0
𝑑𝑣𝐶(𝑡) 𝑣 − 𝑉𝑥 𝑣 𝒗𝒊
𝑖𝐶 𝑡 = 𝐶 𝑖𝑅 = 𝑖 = 𝑖 𝒎=−
𝑹𝑪
𝑑𝑡 𝑅 𝑅 𝒗

1 𝑉𝑥 = 0, por lo tanto 𝑖𝑅 = 𝑖𝐶
𝑣𝐶 𝑡 = 𝑖𝐶 𝑡 𝑑𝑡 Constante
𝐶 a trozos
1 1 𝑣𝑖 𝑣𝑖
𝑣 = −𝑣 = − 𝑖 𝑑𝑡 = − 𝑑𝑡 = − 𝑡
𝑂 𝐶
𝐶 𝐶 𝐶𝑅 𝑅𝐶

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5. Analog-to-Digital Conversion Methods

b) The dual-slope ADC:

AD/DA Converters.
Electronics School
Engineering of –
School Electronic Engineering,
Eng. Wilson Javier PerezUPTC
H. Wilson Javier Perez H. 45
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1 0 0 0

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0 1 0 0

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0 0 1 0

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0
0 0 0 1

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2
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3
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5. Analog-to-Digital Conversion Methods

c) The successive approximation ADC:

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5
5. Analog-to-Digital Conversion Methods

An integrated circuit successive approximation ADC is the ADC0804. This


popular ADC is an 8-bit converter that completes a conversion in 64 clock
periods (100 s).
VCC

(20)
(1) (5)
CS ADC0804 INTR
(2) (19)
RD CLK R (out)
(3) (18)
WR D0
CLK IN
(4) (17)
D1
The completion is signaled by the
Analog Vin+
(6) (16)
D2 INTR line going LOW.
(7) (15) Digital
input Vin– D3
(9) (14) data
REF/2 D4
(13) output
D5
(12)
D6
(11)
D7

(8) (10)

ANLG DGTL
GND GND

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5. Analog-to-Digital Conversion Methods

d) The sigma-delta ADC:


With sigma-delta conversion, the difference between two samples of the
analog input signal is integrated and quantized. The density of 1s at the
output is proportional to the input signal.

Summing
point
Analog + ∆ Quantized output
1-bit
input Σ Integrator
quantizer
is a single bit
signal – data stream.

DAC

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5. Analog-to-Digital Conversion Methods

One option for the sigma-delta method is to count the one-bit quantized output
for a set interval. The output of the counter is latched with the parallel binary
code.
Summing
point
Analog + ∆ 1-bit n-bit Binary code
Σ Integrator Latch
output
input quantizer counter
signal – . .
. .
. .
. .
. .
1-bit
DAC

Sigma-delta ADCs can have high resolution and have advantages for rejecting
noise signals (such as 60 Hz power line interference).
They are available in ICs with internal programmable amplifiers. For these
reasons, they are widely used in instrumentation applications.
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5. Analog-to-Digital Conversion Methods

Sigma-Delta Converter

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5. Analog-to-Digital Conversion Methods

If the wave amplitude, accumulated over a given sample period is greater than
the previous sample period, the converter generates “1”.

If the accumulated wave amplitude is lower, the converter generates “0”.

This generates a type of high density pulse modulation with positive half-waves
represented by many consecutive “1s”, while the negative half-waves produce
many “0s” in the sequence.

The D/A Delta-Sigma decoder performs the inverse operation.

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Sigma-Delta Converter

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References

• Fundamentos de sistemas digitales, Floyd. 9 ed. Capitulo 13

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