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5 4 3 2 1

53 +1P1V_CORE 01 Block Diagram


54 SPI 4Mb 02 Power Sequence

IPM41-D3 Revision:1.00
55 RTC / CMOS / SPKR/SCREW HOLE 03
04
05
06
Power Flow
Clock Distribution
Clock
PROCESSOR LGA775 1 - 3
07 PROCESSOR LGA775 2 - 3
D 08 PROCESSOR LGA775 3 - 3 D
09 ITP_31P DEBUG CONNECTOR
Intel Pentium processor 10 INTEL EAGLELAKE 1 - 7
Conroe-L/Conroe/Wolfdate 11 INTEL EAGLELAKE 2 - 7
LGA775 12 INTEL EAGLELAKE 3 - 7
13 INTEL EAGLELAKE 4 - 7
14 INTEL EAGLELAKE 5 - 7
15 INTEL EAGLELAKE 6 - 7
HOST BUS 16 INTEL EAGLELAKE 7 - 7

DDR3 DIMM A1

DDR3 DIMM B1
17 DDR2 CHANNEL A
18 DDR2 CHANNEL B
19 DDR2 TERMINATION A&B
On board
VGA
INTEL Channel A 20 ICH7-1
21 ICH7-2
C
GMCH 22 ICH7-3 C
23 ICH7-4
EagleLake Channel B
PCI Express PCI-E X16 24 PCI EXPRESS X16 SLOT
X16 SLOT 25 PCI EXPRESS X1 SLOT
26 INTEGRATED VGA PORT
27 SATA CONNECTORS
DMI Link 28 PCI SLOT INTERFACE - PCI1
29 PCI SLOT INTERFACE - PCI2
30 DOUBLE STACK PORT CONNECTOR
31 USB HEADER CONNECTOR
PCI Express PCI-E X1 SATA1 32 REALTEK RTL8111C CONTROLLER
SATA
X1 SLOT SATA2 33 RJ-45+USB CONNECTOR
34 ALC662/883
INTEL SATA3 35 AUDIO Connector
Audio Azalia Link SATA4 36 FRONT AUDIO CONNECTOR
B
ALC662/ALC888S 24MHz ICH7 37 TPM HEADER INTERFACE B
38 SUPER I/O W83627DHG - 1 OF 2
39 SUPER I/O W83627DHG - 2 OF 2
40 PARALLEL PORT - CPC
41 SERIAL PORT CONNECTOR- SI
USB2.0 480Mb/s LPC SUPER I/O 42 PS2 KB &MS CONNECTOR FOR CPC
8 ports Winbond83627DHG-A 43 FAN CIRCUIT FOR 4 - PIN
44 FRONT PANEL CIRCUIT FOR CPC
45 ATX POWER_24P CONNECTOR
SPI

PCI Slot1 46 VCORE CONTROLLER - RT8857


47 VCORE DRIVER - RT9619_1
PCI Slot2 PCI Bus
48 VCORE DRIVER - RT9619_2
Parallel Port 49 +0P9V_VTT_DDR_LDO
SPI TPM Serial Port 50 +1P1V_FSB_VTT&+5V_DUAL
PS2 KB/MS 51 PSI CIRCUIT
A LAN FAN Control 52 +1P8V_DUAL A
RealTek PCI-E X <Variant Name>

RTL8111D(L) H/W Monitor


Title : Block Diagram
PEGATRON CORP. Engineer: Wayne Hsieh
Size Project Name Rev
A3 IPM41-D3 1.00G
Date: Thursday, July 09, 2009 Sheet 1 of 55
5 4 3 2 1

8 PLTRST#

GMCH

D Power D
User press Supply PWROK_PS /X
8 PWROK
Ctrl+Alt+Del
7
PSON#
6
5V Level 9
Buffer Out 5V RST#_IDE
User press 3 IDE
Power PWRBTN#
button Default Super IO
PCI Express X16
7
3.3V 3.3V 4
5 5
PLTRST#_PCIEX16 9

3.3V
RST_KB

RSMRST#

SLP_S3#

SLP_S4#

IO_PWRBTN#

PWROK
PCI Express X1
2
C PLTRST#_PCIEX1 9
C

3.3V
PCI slots
3.3V 3.3V 3.3V 3.3V 3.3V 3.3V
User press 8 3.3V PCIRST#
3.3V ICH7
Reset RSTCON#
button Default
3.3V

3.3V
RTCRST#
User 1
PLTRST#
Clear
CMOS 3.3V 8

10
B CPURST# Vcore B
RTL8111C
8
3.3V
CPUPWRGD

CPU
HINIT# Vcore

FWHHINIT# FWH 8
3.3V
3.3V

8
3.3V

A A
<Variant Name>

8
3.3V Title : Power Sequence
PEGATRON CORP. Engineer: Wayne Hsieh
Size Project Name Rev
A3 IPM41-D3 1.00G
Date: Thursday, July 09, 2009 Sheet 2 of 55
5 4 3 2 1

ATX12V
ISL6312
3.5Phases VCORE
I max.=125A.
TDC: 100A.
D S0 TDP:65W.(05A) D
VCORE_EN
ATXPWR

+3VSB Io: 2A LAN_1.5V Io: 380mA


+5VSB L1085DG L1117LG
S0/S3/S5 S0/S3/S5

LAN_2.5V Io: 260mA


L1117LG Io
S0/S3/S5 S0: 500mA
+3VDUAL S3: 12mA
AME1117ACGTZ
S0/S3/S5
APM9932CKC
C + C
AP2306GN +5V_DUAL Io: >10.4A
S3/S5:+5VSB
+1.8V_DUAL LM324DR+ +1.5V
Switch
+5V S0:+5V
AP60T03H*2
APW7120KE_TRL Io S0
S0/S1/S3 S0/S1: 14A
S3: 425mA
LM324DR Io: 6A
+VTT_CPU
+P3055LDG
S0

+3.3V +2.5V_DAC Io: 70mA


LM324DR+7002
S0 LM324DR Io: 1.31A
+1.05V
+P3055LDG
VR_ProtHot S0
LM324DR+7002
B S0 B

CM8562PGISTR VTT_DDR
S0/S3 Io
S0: 1.2A
S3: 420mA

NOTE:
Linear REG
A A
<Variant Name>
Switch REG
Title : Power Flow
PEGATRON CORP. Engineer: Wayne Hsieh
Size Project Name Rev
A3 IPM41-D3 1.00G
Date: Thursday, July 09, 2009 Sheet 3 of 55
5 4 3 2 1

133/200/266 MHz CK_FSB_CPU/#


CPU
ICS
9LPRS552AGLF_T
133/200/266 MHz CK_FSB_NB/#
D D
MCH
100 MHz CK_100M_MCH/#

96 MHz CK_96M_DREF/# Lakeport

100 MHz CK_100M_PCIEX16/#


PCIEX16

100 MHz CK_100M_ICH/#


14.318 MHz
XTAL

100 MHz CK_100M_SATA/#

C 48 MHz CK_48M_USB ICH7 C

33 MHz CK_33M_ICH

14.318 MHz CK_14M_ICH

48 MHz CK_48M_SIO
Super I/O
33 MHz CK_33M_SIO

33 MHz

B 33 MHz CK_PCI_TPM TCM B

33 MHz CK_33M_SL1
PCI SLOT 1
33 MHz CK_33M_SL2
PCI SLOT 2

A 100 MHz CK_PCIE_SLOT1/# A


PCIEX1_1 <Variant Name>

Title : Clock Distribution


PEGATRON CORP. Engineer:
Wayne Hsieh
100 MHz CK_100M_LAN/# Size Project Name Rev

LAN A3 IPM41-D3 1.00G


Date: Thursday, July 09, 2009 Sheet 4 of 55
5 4 3 2 1

I
I CRITICAL
+3P3VSB CKL1
600Ohm/100Mhz/0.5A +CLKVCC3 CKU2
mx_l0603
1 2 VDDPCI 2 46
VDD_PCI CPU_0 CPUHCLK [6]
CPU_0# 45 CPUHCLK# [6]
VDD_PLL3 16 43
VDD_PLL3 CPU_1_AMT CK_FSB_NB [10]
VDD_SRC 31 42
VDD_SRC CPU_1_AMT# CK_FSB_NB# [10]
VDDCPU 47 39
VDD_CPU SRC_8/CPU_ITP CK_ITP [9]
SRC_8#/CPU_ITP# 38 CK_ITP# [9]
D +3P3V D
NI VDDREF 53
NOTE:
CKL2 VDD_REF
600Ohm/100Mhz/0.5A SRC_7 36 CK_100M_ICH [20] SRC[3 4 6 and 7] are
35 CK_100M_ICH# [20]
mx_l0603 SRC_7# designated for PCIe GEN2,

1
1 2 I
CKCB2
I
CKCB3
I
CKCB4
I
CKCB5
I
CKCB6 SRC_6 33 CK_100M_PCIEX16 [24] must be used for GMCH and
32 CK_100M_PCIEX16# [24]
0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V SRC_6# PCIe Gen2 slot

2
X7R 10% X7R 10% X7R 10% X7R 10% X7R 10% 8 30
VSS_PCI PCI_STOP#/SRC_5 CK_100M_PCIEX1 [25]
23 VSS_SRC1 CPU_STOP#SRC_5# 29 CK_100M_PCIEX1# [25] NOTE:
34 VSS_SRC2
+CLKVCC3 44 27 PIN [29 30] tie to ICH
VSS_CPU SRC_4 CK_100M_MCH [10]
GND GND GND GND GND 50 28
VSS_REF SRC_4# CK_100M_MCH# [10] through 1K ohm if iAMT support

1
SRC_3 24 CK_100M_LAN [32] (PCI_STOP#, CPU_STOP#),
NOTE: I 25 CK_100M_LAN# [32]
CKR2 GND SRC_3# Strap SRC5 disable
CKR2 CKR10 PIN17 PIN18 10K 21
SRC_2 CK_100M_SATA [20]
VOUT_VDDIO 40 22 CK_100M_SATA# [20]

2
SEL_24.576MHz SRC_2#
I NI 25MHz 24.576MHz I CKR1
25MHz_0_F 17 1 2 33 CK_25M_LAN [32]
25MHz_1/24.576MHz 18
8/19 modify
SRC_0/DOT_96 13 CK_96M_DREF [13]
SRC_0#/DOT_96# 14 CK_96M_DREF# [13]

VDD_IO_96 12 PCIF5/ITP_EN(Pin7):
C VDD_I/O_3.3
1: CPU_ITP
NOTE: C

PCIF_5 is dedicated for ICH


PCI4/SRC5_EN(Pin6):
PCI4 is for the shortest route

1
I 1: SRC5 Output
CKCB9 I CKRN2A 5% PCI0 is for the longest route
0.1UF/16V 7 RCK_33M_ICH 1 33 Ohm 2 CK_33M_ICH [20]
2 X7R 10% ITP_EN/PCI_5 CK_33M_PCI4 I CKRN2B 5%
PCI_4/SRC_5_EN 6
5 RCK_33M_TPM I CKRN2C 3 5%
PCI_3 33 Ohm 4 CK_33M_TPM [37]
4 RCK_33M_SL2 I CKRN2D 5 5%
PCI_2 33 Ohm 6 CK_33M_SL2 [29]
3 RCK_33M_SL1 7
GND PCI_1 33 Ohm 8 CK_33M_SL1 [28]
1 RCK_33M_SIO 1 2 33
PCI_0 CK_33M_SIO [39]
20 VDD_PLL3_I/O
+VDD_IO 26 PCI3/CFG0(Pin5): I CKR34 8/27 modify
VDD_SRC_I/O1
37 VDD_SRC_I/O2 Strap for SATA PLL

1
41 VDD_CPU_I/O 1: PLL2, SS OFF NI NI NI I NI
1

8
NI I I I I I I I I I CKC3 CKC4 CKC5 CKC6 CKC7
CKCB11 CKCB12 CKCB13 CKCB14 CKCB15 CKCB16 19 PCI2/TME(Pin4): CKRN1A CKRN1B CKRN1C CKRN1D 10PF/50V 10PF/50V 10PF/50V 10PF/50V 10PF/50V

2
10UF/6.3V 10UF/6.3V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V VSS_PLL3 4.7KOHM NPO 5% NPO 5% NPO 5% NPO 5% NPO 5%
15 1: SR enable 4.7KOHM 4.7KOHM 4.7KOHM
2

2
X5R 10% X5R 10% X7R 10% X7R 10% X7R 10% X7R 10% VSS_I/O
5% 5% 5% 5%
mx_c0805 mx_c0805
GND GND GND GND GND

7
PCB40 GND GND GND GND GND GND GND

PCB
PCB_BOARD +CLKVCC3 +CLKVCC3 5%
I CKRN3A 1
I 1KOHM 2 M_HBSEL0 [7,13]
B VDD48_BW B
9 VDD_48 I CKR42 1 2 22 CK_48M_SIO [39]
10 RCK_48M_USB I CKR40 1 2 22
FS_A/48MHz_0 5% CK_48M_USB [20]
11 VSS_48
49 FSLB I CKRN3C 5
FS_B/TEST_MODE 1KOHM 6 M_HBSEL1 [7,13]
1

I
CKCB18 54 RCK_14M_ICH I CKR39 1 2 33
0.1UF/16V REF/FS_C/TEST_SEL CK_14M_ICH [21]
2

X7R 10% 5%
I CKRN3B 3 1KOHM 4 M_HBSEL2 [7,13]
GND GND
VRMPWRGD_ICH 48
NOTE:
[21,51] VRMPWRGD_ICH CKPWRGD/PD#
OSC_CK14M_XTALIN
Single End damping resistor
52
OSC_CK14M_XTALOUT 51
XTAL_IN Single Load => 33 OHM
XTAL_OUT
Double Load => 22 OHM
I
Y1
14.318Mhz
1 2
GND
3
1

I I
CKC8 CKC9
33PF/50V 33PF/50V
2

NPO 5% NPO 5%

GND GND GND 56


A [9,17,18,21,24,25,28,29] SMB_CLK_R SCL A

[9,17,18,21,24,25,28,29] SMB_DATA_R 55 SDA

SLG8XP548T PEGATRON DT-MB RESTRICTED SECRET


1

NI NI
CKC10
33PF/50V
CKC11
33PF/50V
Title : CLOCK CK505
2

NPO 5% NPO 5% PEGATRON CORP. Engineer: Wayne Hsieh


Size Project Name Rev
GND GND A3
IPM41-D3 1.00G
Date: Thursday, July 09, 2009 Sheet 5 of 55
5 4 3 2 1
5 4 3 2 1

+1P1V_FSB_VTT RMA1
NOBOM I
SMD4X25_NP XU1B

1
I
SOCKET775/ATX
XU1A I RMA1 is soldermask on trace for RMA

1
HR1
SOCKET775/ATX 62 purpose. Place on suitable location where

1
[10] HA#[3..35] [10] HD#[0..63] HD#[0..63] [10]
can be easily reached by Probe

2
HD#0 B4 G16 HD#32
HA#3 HD#1 D00# D32# HD#33
L5 A03# ADS# D2 HADS# [10] C5 D01# D33# E15
HA#4 P6 C2 HD#2 A4 E16 HD#34
A04# BNR# HBNR# [10] D02# D34#
HA#5 M5 D4 HD#3 C6 G18 HD#35
A05# HIT# HIT# [10] D03# D35#
HA#6 L4 H4 HD#4 A5 G17 HD#36
HA#7 A06# RSP# HD#5 D04# D36# HD#37
D M4 A07# BPRI# G8 HBPRI# [10] B6 D05# D37# F17 D
HA#8 R4 B2 HD#6 B7 F18 HD#38
A08# DBSY# HDBSY# [10] D06# D38#
HA#9 T5 C1 HD#7 A7 E18 HD#39
A09# DRDY# HDRDY# [10] D07# D39#
HA#10 U6 E4 HD#8 A10 E19 HD#40
A10# HITM# HITM# [10] D08# D40#
HA#11 T4 AB2 HIERR# HD#9 A11 F20 HD#41
HA#12 A11# IERR# HD#10 D09# D41# HD#42
U5 A12# INIT# P3 HINIT# [20] B10 D10# D42# E21
HA#13 U4 C3 HD#11 C11 F21 HD#43
A13# LOCK# HLOCK# [10] D11# D43#
HA#14 V5 E3 HD#12 D8 G21 HD#44
A14# TRDY# HTRDY# [10] D12# D44#
HA#15 V4 AD3 HD#13 B12 E22 HD#45
HA#16 A15# BINIT# HD#14 D13# D45# HD#46
W5 A16# DEFER# G7 HDEFER# [10] C12 D14# D46# D22
HD#15 D11 G22 HD#47
D15# D47#
MCERR# AB3

[10] HREQ#[0..4] HREQ#0 K4 REQ0#


HREQ#1 J5 U2 +VTT_OUT_L A8 D19
REQ1# AP0# [10] HDBI0# DBI0# DBI2# HDBI2# [10]
HREQ#2 M6 U3
HREQ#3 REQ2# AP1#
K6 REQ3#

1
HREQ#4 J6 J16
REQ4# DP0#
DP1# H15 I
R6 H16 HR2
[10] HADSTB0# ADSTB0# DP2# 62
DP3# J17 [10] HDSTBN0# C8 DSTBN0# DSTBN2# G20 HDSTBN2# [10]
B9 G19 HDSTBP2# [10]

2
[10] HDSTBP0# DSTBP0# DSTBP2#
N4 RSVD1
P5 RSVD2
BR0# F3 HBREQ0# [10]
+VTT_OUT_L +VTT_OUT_L

C C

[10] HA#[3..35]

1
I I
HR4 HR3
HA#17 AB6 57.6 57.6
HA#18 A17# 1% 1%
W6 A18# I
HA#19 Y6 HR5

2
HA#20 A19# 10
Y4 A20# [10] HD#[0..63] HD#[0..63] [10]
HA#21 AA4 H2 CPU_GTLREF1 2 1 CPU_GTLREF1_R
HA#22 A21# GTLREF1
AD6 A22#
HA#23 AA5 H1 CPU_GTLREF0 2 1 CPU_GTLREF0_R HD#16 G9 D20 HD#48
HA#24 A23# GTLREF0 HD#17 D16# D48# HD#49
AB5 A24# F8 D17# D49# D17
HA#25 AC5 I HD#18 F9 A14 HD#50
A25# D18# D50#

1
HA#26 AB4 HR6 I I HD#19 E9 C15 HD#51
A26# D19# D51#
1

1
HA#27 AF5 NI NI 10 I I HR8 HR7 HD#20 D7 C14 HD#52
HA#28 A27# HCB1 HCB2 HCB3 HCB4 100 100 HD#21 D20# D52# HD#53
AF4 A28# E10 D21# D53# B15
HA#29 AG6 220PF/50V 220PF/50V 1UF/10V 1UF/10V 1% 1% HD#22 D10 C18 HD#54
2

2
HA#30 A29# X7R 10% X7R 10% mx_c0603 mx_c0603 HD#23 D22# D54# HD#55
AG4 F11 B16

2
HA#31 A30# HD#24 D23# D55# HD#56
AG5 A31# F12 D24# D56# A17
HD#25 D13 B18 HD#57
HD#26 D25# D57# HD#58
E13 D26# D58# C21
GND GND GND GND GND GND HD#27 G13 B21 HD#59
D27# D59#
2

HA#32 AH4 HD#28 F14 B19 HD#60


HA#33 A32# NJP4 HD#29 D28# D60# HD#61
AH5 A33# NOTE: G14 D29# D61# A19
HA#34 AJ5 SHORTPIN_RECT HD#30 F15 A22 HD#62
A34# D30# D62#
HA#35 AJ6 A35# NOBOM Place near CPU HD#31 G15 D31# D63# B22 HD#63
2

AD5 NJP5
1

[10] HADSTB1# ADSTB1#


SHORTPIN_RECT
B B
NOBOM DBI3# C20 HDBI3# [10]
AC4 RSVD3 [10] HDBI1# G11 DBI1#
AE4
1

RSVD4

GTLREF2 F2
[10] HRS#[0..2]
GTLREF3 G10
HRS#2 A3
HRS#1 RS2#
F5 RS1# [10] HDSTBN1# G12 DSTBN1# DSTBN3# A16 HDSTBN3# [10]
HRS#0 B3 E12 C17
RS0# [10] HDSTBP1# DSTBP1# DSTBP3# HDSTBP3# [10]

[5] CPUHCLK F28 BCLK0


G28 REV=1.3
[5] CPUHCLK# BCLK1

+VTT_OUT_R
NOTE: Default is 0.63*VTT
1

E24
I
FC10 ICH_GPIOA ICH_GPIOB GTLREF COMMENTS
HR13 H29 HQ1 off, HQ2 on
62 FC15 0 0 0.615*VTT HQ3 off, HQ4 on
HQ1 off, HQ2 on
0 1 0.65*VTT
2

HQ3 on, HQ4 off


G23 HQ1 on, HQ2 off
[9,10,51] CPURESET# RESET# 1 0 0.63*VTT HQ3 off, HQ4 on
A A
HQ1 on, HQ2 off
1 1 0.67*VTT
1

NI HQ3 on, HQ4 off


HC1
22PF/50V
ASUS OEM-DT MB RESTRICTED SECRET
2

NPO 5%

REV=1.3 Title : INTEL LGA-775 1 - 3


GND PEGATRON CORP. Engineer: Wayne Hsieh
Size Project Name Rev
A3 IPM41-D3 1.00G
Date: Thursday, July 09, 2009 Sheet 6 of 55
5 4 3 2 1
5 4 3 2 1

PLACE NEAR SB
+1P1V_FSB_VTT

NOTE:

1
I I +1P1V_FSB_VTT +VTT_OUT_L +VTT_OUT_R FSB_VTT Net Name changed
HR17 I
62 XU1C
SOCKET775/ATX 0.05 1 2 HRN4A I XU1D
51OHM

2
0.05 3 4 HRN4B I SOCKET775/ATX +1P1V_FSB_VTT
51OHM
F26 TESTHI0 0.05 1 2 HRN3A I 0.05 5 6 HRN4C I
TESTHI00 51OHM 51OHM
P2 W3 TESTHI1 0.05 3 4 HRN3B I 0.05 7 8 HRN4D I
[20] SMI# SMI# TESTHI01 51OHM 51OHM
D K3 H5 TESTHI10 0.05 5 6 HRN3C I AE1 A29 D
[20] A20M# A20M# TESTHI10 51OHM [9] TCK TCK VTT1
R3 P1 TESTHI11 0.05 7 8 HRN3D I AD1 B25
[20] HFERR# FERR#/PBE# TESTHI11 51OHM [9] TDI TDI VTT2
[20] INTR K1 LINT0 [9] TDO AF1 TDO VTT3 B29
L1 L2 TESTHI13 I HR24 2 1 51 AC1 B30
[20] NMI LINT1 TESTHI13 [9] TMS TMS VTT4
N2 F25 TESTHI2_7 I HR23 2 1 51 AG1 C29
[20] IGNNE# IGNNE# TESTHI02 [9] TRST# TRST# VTT5
[20] STPCLK# M3 STPCLK# TESTHI03 G25 VTT6 A26
TESTHI04 G27 PM_SLP# [13,20] VTT7 B27

1
TESTHI05 G26 DPSLP# [21] I I VTT8 C28
G24 HR26 HR27 A25
TESTHI06 49.9 49.9 VTT9
TESTHI07 F24 VTT10 A28
A23 G3 TESTHI8 0.05 1 HRN6A I 1% 1%
VCCA TESTHI08 51OHM 2 VTT11 A27
G4 TESTHI9 0.05 3 HRN6B I
51OHM 4 C30

2
TESTHI09 VTT12
VTT13 A30
H_BPM2_2 [9] VTT14 C25
H_BPM3_2 [9] VTT15 C26
CPU_PSI [51] GND GND VTT16 C27
+VTT_OUT_R B26
DPRSTP# [13] VTT17
VTT18 D27
B23 A13 HCOMP0 I HR49 1 2 49.9 1% 0.05 1 2 HRN5A I D28
VSSA COMP0 51OHM VTT19
T1 HCOMP1 I HR46 1 2 49.9 1% +VTT_OUT_L 0.05 3 4 HRN5B I D25
COMP1 51OHM VTT20
G2 HCOMP2 I HR28 1 2 49.9 1% 0.05 5 6 HRN5C I D26
COMP2 51OHM VTT21
R1 HCOMP3 I HR33 1 2 49.9 1% +VTT_OUT_R 0.05 7 8 HRN5D I B28
COMP3 51OHM VTT22
J2 HCOMP4 NI HR32 2 1 49.9 1% I HR35 1 2 51 D29
COMP4 DPRSTP# HR37 49.9 1% VTT23
COMP5 T2 I 2 1 I HR38 1 2 51
VTT24 D30
Y3 CPU_PSI I HR36 2 1 49.9 1%
COMP6 HCOMP7 HR47 49.9 1%
COMP7 AE3 NI 2 1 [9] BPM0# AJ2 BPM0#
C23 B13 HCOMP8 I HR39 1 2 24.9 1% AJ1
VCCIOPLL COMP8 TESTHI12 HR21 51 [9] BPM1# BPM1#
TESTHI12 W2 I 2 1 [9] BPM2# AD2 BPM2#
2 0 1 AG2
C NOTE: NI HR48
[9] BPM3#
AF2
BPM3# C
0.05 5 HRN6C I GND [9] BPM4# BPM4# +VTT_OUT_R +VTT_OUT_L
The VCCIO PLL Filter Circuit is no longer 51OHM 6 [9] BPM5# AG3 BPM5#
G1 H_BPM0_2 [9]
needed since Conroe CPU RSVD33
U1
RSVD34
RSVD35 A24 [9,21,38,44] SYS_RESET# AC2 DBR# VTT_OUT1 AA1
RSVD36 E29
+VTT_OUT_R AH2 AK3 J1
RSVD12 ITPCLK<0> VTT_OUT2
RSVD21 G6 AJ3 ITPCLK<1>
F29 +VTT_OUT_L
RSVD9

1
I 7 8 HRN1D NI NI
680
5 6 HRN1C 0.05 7 HRN6D I HCB13 HCB12
I 680 51OHM 8 N5 RSVD17
I 3 4 HRN1B C9 0.1UF/16V 0.1UF/16V
680

2
HRN1A MSID0 [9] H_BPM1_2 RSVD18
I 1 680 2 MSID0 W1 E7 RSVD19
AE6 RSVD20
V1 MSID1 D16
HRN2D MSID1 RSVD22
I 7 680 8 A20 RSVD23

1
I 5 6 HRN2C +VTT_OUT_L NI NI E23 GND GND
680 RSVD31
I 3 4 HRN2B HR50 HR51
680
I 1 2 HRN2A 51 51
680

1
+VTT_OUT_R +CPU_VCCPLL
NI

2
[46] RCVID[0..7] HR53

1
62 D23
+VTT_OUT_R VCC_PLL
I
RCVID0 AM2 VID0 2 GND GND HR52

1
RCVID1 AL5 680 I NI
VID1
1

RCVID2 AM3 AA2 CPU_LL_ID1 Check PWM controller HCB14 HCB15

2
RCVID3 VID2 LL_ID1 0.01UF/25V 10UF/6.3V
I AL6

2
HR65 RCVID4 VID3 X7R 10% X5R 10%
AK4 VID4 LL_ID0 V2 [46,51] VRMPWRGD AM6 VTTPWRGD
B 680 RCVID5 mx_c0805 B
AL4 VID5
RCVID6 AM5 Y1 CPU_BOOT
2

RCVID7 VID6 BOOTSELECT


AM7 VID7 BOOTSELECT:

1
VID_SELECT AN7 I NI GND GND
[46] VID_SELECT VID_SECECT
AL3 HR55 Install PD resistor to HC2
NC 51 prevent PSC SMF CDM PSL 100PF/50V

2
AE8 G5 PECI_CPU NPO 5%
SKTOCC# PECI PECI_CPU [38] CPU from booting

2
F6 IMPSEL_F6
IMPSEL
[38] TRD_CPU_P GND AL1 THERMDA VTT_SEL F27 VTT_SELECT [50]
AK1 GND GND
[38] TRD_CPU_N THERMDC +1P1V_FSB_VTT
1

AJ7 VSS_AJ7 I
AH7 HR56 +VTT_OUT_R +VTT_OUT_L +VTT_OUT_R I 5%HR500
1 470 OHMHRN7A
5% I
VSS_AH7 470 OHM2
51 I 5% 1 2
5 HRN7C
470 OHM6
2

GND [5,13] M_HBSEL0 G29 BSEL0


[46] VCC_SENSE AN5 VCC_MB_REGULATION I NI I [5,13] M_HBSEL1 H30 BSEL1
HR61 HR62 HR63 G30
GND 130 100 130 [5,13] M_HBSEL2 BSEL2
[46] VSS_SENSE AN6 VSS_MB_REGULATION 1% 1%
REV=1.3
2

AN3 AK6 HFORCEPH#


VCC_SENSE FORCEPR# 06/20 modify
+VCORE AN4 N1 CPUPWRGD
VSS_SENSE PWRGOOD CPUPWRGD [9,21]
I 5% 7 HRN7D
470 OHM8
AL8 AL2 PROCHOT# I 5% 3 HRN7B
VCC_D_SENSE PROCHOT# 470 OHM4
A A
AL7 M2 H_THMTRIP#
VSS_D_SENSE THERMTRIP# H_THMTRIP# [20]
THERMALTRIP# NEED A PULL UP RESISTOR NEAR SB

GND 9/8 modify ASUS OEM-DT MB RESTRICTED SECRET


REV=1.3
Title : INTEL LGA-775 2 - 3
PEGATRON CORP. Engineer: Wayne Hsieh
Size Project Name Rev
A3 IPM41-D3 1.00G
Date: Thursday, July 09, 2009 Sheet 7 of 55
5 4 3 2 1
5 4 3 2 1

+VCORE
I I I
XU1G XU1H XU1I
SOCKET775/ATX SOCKET775/ATX SOCKET775/ATX

D D
AF28 VSS1 VSS61 AF3 B11 VSS141 VSS201 Y7 1 RM_POST_NC1
AF27 VSS2 VSS62 AF30 B14 VSS142 VSS202 Y5 2 RM_POST_NC2
I I AF26 VSS3 VSS63 AF6 B17 VSS143 VSS203 Y2 3 RM_POST_NC3
XU1E XU1F AF25 VSS4 VSS64 AF7 B20 VSS144 VSS204 W7 4 RM_POST_NC4
AF24 VSS5 VSS65 AG10 B24 VSS145 VSS205 W4
SOCKET775/ATX SOCKET775/ATX AF23 AG13 B5 V7
VSS6 VSS66 VSS146 VSS206
AF20 VSS7 VSS67 AG16 B8 VSS147 VSS207 V6
VCC225 L8 AF17 VSS8 VSS68 AG17 C10 VSS148 VSS208 V30 REV=1.3
AA8 VCC1 VCC112 AM14 AM15 VCC113 VCC224 M23 AF16 VSS9 VSS69 AG20 C13 VSS149 VSS209 V3
AB8 VCC2 VCC111 AM12 AM18 VCC114 VCC223 M24 AF13 VSS10 VSS70 AG23 C16 VSS150 VSS210 V29
AC23 VCC3 VCC110 AM11 AM19 VCC115 VCC222 M25 AF10 VSS11 VSS71 AG24 C19 VSS151 VSS211 V28
AC24 VCC4 VCC109 AL9 AM21 VCC116 VCC221 M26 AE7 VSS12 VSS72 AG7 C22 VSS152 VSS212 V27
AC25 VCC5 VCC108 AL30 AM22 VCC117 VCC220 M27 AE5 VSS13 VSS73 AH1 C24 VSS153 VSS213 V26
AC26 VCC6 VCC107 AL29 AM25 VCC118 VCC219 M28 AE30 VSS14 VSS74 AH10 C4 VSS154 VSS214 V25
AC27 VCC7 VCC106 AL26 AM26 VCC119 VCC218 M29 AE29 VSS15 VSS75 AH13 C7 VSS155 VSS215 V24
AC28 VCC8 VCC105 AL25 AM29 VCC120 VCC217 M30 AE28 VSS16 VSS76 AH16 D12 VSS156 VSS216 V23
AC29 VCC9 VCC104 AL22 AM30 VCC121 VCC216 M8 AE27 VSS17 VSS77 AH17 D15 VSS157 VSS217 U7
AC30 VCC10 VCC103 AL21 AM8 VCC122 VCC215 N23 AE26 VSS18 VSS78 AH20 D18 VSS158 VSS218 T7
AC8 VCC11 VCC102 AL19 AM9 VCC123 VCC214 N24 AE25 VSS19 VSS79 AH23 D21 VSS159 VSS219 T6
AD23 VCC12 VCC101 AL18 AN11 VCC124 VCC213 N25 AE24 VSS20 VSS80 AH24 D24 VSS160 VSS220 T3
AD24 VCC13 VCC100 AL15 AN12 VCC125 VCC212 N26 AE20 VSS21 VSS81 AH3 D3 VSS161 VSS221 R7
AD25 VCC14 VCC99 AL14 AN14 VCC126 VCC211 N27 AE2 VSS22 VSS82 AH6 D5 VSS162 VSS222 R5
AD26 VCC15 VCC98 AL12 AN15 VCC127 VCC210 N28 AE17 VSS23 VSS83 AJ10 D6 VSS163 VSS223 R30
AD27 VCC16 VCC97 AL11 AN18 VCC128 VCC209 N29 AE16 VSS24 VSS84 AJ13 D9 VSS164 VSS224 R29
AD28 VCC17 VCC96 AK9 AN19 VCC129 VCC208 N30 AE13 VSS25 VSS85 AJ16 E11 VSS165 VSS225 R28
AD29 VCC18 VCC95 AK8 AN21 VCC130 VCC207 N8 AE10 VSS26 VSS86 AJ17 E14 VSS166 VSS226 R27
AD30 VCC19 VCC94 AK26 AN22 VCC131 VCC206 P8 AD7 VSS27 VSS87 AJ20 E17 VSS167 VSS227 R26
AD8 VCC20 VCC93 AK25 AN25 VCC132 VCC205 R8 AD4 VSS28 VSS88 AJ23 E2 VSS168 VSS228 R25
C AE11 AK22 AN26 T23 AC7 AJ24 E20 R24 C
VCC21 VCC92 VCC133 VCC204 VSS29 VSS89 VSS169 VSS229
AE12 VCC22 VCC91 AK21 AN29 VCC134 VCC203 T24 AC3 VSS30 VSS90 AJ27 E25 VSS170 VSS230 R23
AE14 VCC23 VCC90 AK19 AN30 VCC135 VCC202 T25 AC6 VSS31 VSS91 AJ28 E26 VSS171 VSS231 R2
AE15 VCC24 VCC89 AK18 AN8 VCC136 VCC201 T26 AB7 VSS32 VSS92 AJ29 E27 VSS172 VSS232 P7
AE18 VCC25 VCC88 AK15 AN9 VCC137 VCC200 T27 AB30 VSS33 VSS93 AJ30 E28 VSS173 VSS233 P4
AE19 VCC26 VCC87 AK14 J10 VCC138 VCC199 T28 AB29 VSS34 VSS94 AJ4 E8 VSS174 VSS234 P30
AE21 VCC27 VCC86 AK12 J11 VCC139 VCC198 T29 AB28 VSS35 VSS95 AK10 F10 VSS175 VSS235 P29
AE22 VCC28 VCC85 AK11 J12 VCC140 VCC197 T30 AB27 VSS36 VSS96 AK13 F13 VSS176 VSS236 P28
AE23 VCC29 VCC84 AJ9 J13 VCC141 VCC196 T8 AB26 VSS37 VSS97 AK16 F16 VSS177 VSS237 P27
AE9 VCC30 VCC83 AJ8 J14 VCC142 VCC195 U23 AB25 VSS38 VSS98 AK17 F19 VSS178 VSS238 P26
AF11 VCC31 VCC82 AJ26 J15 VCC143 VCC194 U24 AB24 VSS39 VSS99 AK2 F22 VSS179 VSS239 P25
AF12 VCC32 VCC81 AJ25 J18 VCC144 VCC193 U25 AB23 VSS40 VSS100 AK20 F4 VSS180 VSS240 P24
AF14 VCC33 VCC80 AJ22 J19 VCC145 VCC192 U26 AB1 VSS41 VSS101 AK23 F7 VSS181 VSS241 P23
AF15 VCC34 VCC79 AJ21 J20 VCC146 VCC191 U27 AA7 VSS42 VSS102 AK24 H10 VSS182 VSS242 N7
AF18 VCC35 VCC78 AJ19 J21 VCC147 VCC190 U28 AA6 VSS43 VSS103 AK27 H11 VSS183 VSS243 N6
AF19 VCC36 VCC77 AJ18 J22 VCC148 VCC189 U29 AA30 VSS44 VSS104 AK28 H12 VSS184 VSS244 N3
AF21 VCC37 VCC76 AJ15 J23 VCC149 VCC188 U30 AA3 VSS45 VSS105 AK29 H13 VSS185 VSS245 M7
AF22 VCC38 VCC75 AJ14 J24 VCC150 VCC187 U8 AA29 VSS46 VSS106 AK30 H14 VSS186 VSS246 M1
AF8 VCC39 VCC74 AJ12 J25 VCC151 VCC186 V8 AA28 VSS47 VSS107 AK5 H17 VSS187 VSS247 L7
AF9 VCC40 VCC73 AJ11 J26 VCC152 VCC185 W23 AA27 VSS48 VSS108 AK7 H18 VSS188 VSS248 L6
AG11 VCC41 VCC72 AH9 J27 VCC153 VCC184 W24 AA26 VSS49 VSS109 AL10 H19 VSS189 VSS249 L30
AG12 VCC42 VCC71 AH8 J28 VCC154 VCC183 W25 AA25 VSS50 VSS110 AL13 H20 VSS190 VSS250 L3
AG14 VCC43 VCC70 AH30 J29 VCC155 VCC182 W26 A12 VSS51 VSS111 AL16 H21 VSS191 VSS251 L29
AG15 VCC44 VCC69 AH29 J30 VCC156 VCC181 W27 A15 VSS52 VSS112 AL17 H22 VSS192 VSS252 L28
AG18 VCC45 VCC68 AH28 J8 VCC157 VCC180 W28 A18 VSS53 VSS113 AL20 H23 VSS193 VSS253 L27
AG19 VCC46 VCC67 AH27 J9 VCC158 VCC179 W29 A2 VSS54 VSS114 AL23 H24 VSS194 VSS254 L26
AG21 VCC47 VCC66 AH26 K30 VCC159 VCC178 W30 A21 VSS55 VSS115 AL24 H25 VSS195 VSS255 L25
AG22 VCC48 VCC65 AH25 K29 VCC160 VCC177 W8 A6 VSS56 VSS116 AL27 H26 VSS196 VSS256 L24
AG25 VCC49 VCC64 AH22 K28 VCC161 VCC176 Y23 A9 VSS57 VSS117 AL28 H27 VSS197 VSS257 L23
B B
AG26 VCC50 VCC63 AH21 K27 VCC162 VCC175 Y24 AA23 VSS58 VSS118 AM1 H28 VSS198 VSS258 K7
AG27 VCC51 VCC62 AH19 K26 VCC163 VCC174 Y25 AA24 VSS59 VSS119 AM10 H3 VSS199 VSS259 K5
AG28 VCC52 VCC61 AH18 K25 VCC164 VCC173 Y26 AF29 VSS60 VSS120 AM13 H6 VSS200 VSS260 K2
AG29 VCC53 VCC60 AH15 K24 VCC165 VCC172 Y27 VSS121 AM16 VSS261 J7
AG30 VCC54 VCC59 AH14 K23 VCC166 VCC171 Y28 VSS122 AM17 VSS262 J4
AG8 VCC55 VCC58 AH12 K8 VCC167 VCC170 Y29 VSS123 AM20 VSS263 H9
AG9 VCC56 VCC57 AH11 Y8 VCC168 VCC169 Y30 VSS124 AM23 VSS264 H8
REV=1.3 GND AM24 GND H7
REV=1.3 VSS125 VSS265
VSS126 AM27
VSS127 AM28
VSS128 AM4
VSS129 AN1
VSS130 AN10 GND
VSS131 AN13
VSS132 AN16
VSS133 AN17
VSS134 AN2
D1 RSVD27 VSS135 AN20
D14 RSVD28 VSS136 AN23
E5 RSVD29 VSS137 AN24
E6 RSVD30 VSS138 AN27
F23 RSVD37 VSS139 AN28
J3 RSVD32 VSS140 B1
REV=1.3 REV=1.3
1

A NI NI GND A
HR66 HR67
1K 1K
NOTE:
2

Intel ENG Feature ASUS OEM-DT MB RESTRICTED SECRET


Title : INTEL LGA-775 3 - 3
GND GND
PEGATRON CORP. Engineer: Wayne Hsieh
Size Project Name Rev
A3 IPM41-D3 1.00G
Date: Thursday, July 09, 2009 Sheet 8 of 55
5 4 3 2 1
5 4 3 2 1

INTEL LGA-775 PROCESSOR ITP DEBUG PORT

[7] BPM0#
[7] BPM1#
[7] BPM2#
D [7] BPM3# D

XDP

[7] H_BPM0_2 NI 5% 1 2 GRN1A 9 23


0 Ohm BPM0# TDO TDO [7]
[7] H_BPM1_2 NI 5% 3 4 GRN1B 7 29
0 Ohm BPM1# TDI TDI [7]
[7] H_BPM2_2 NI 5% 5 6 GRN1C 6 31
0 Ohm BPM2# TMS TMS [7]
[7] H_BPM3_2 NI 5% 7 8 GRN1D 4 30
0 Ohm BPM3# TCK TCK [7]
[7] BPM4# 3 BPM4# TRST# 25 TRST# [7]
[7] BPM5# 1 BPM5#

13 10 CPUPWRGD
[5] CK_ITP BCLK0 PWRGOOD CPUPWRGD [7,21]
[5] CK_ITP# 15 BCKL1

C C

16 19 CPURST_ITP#
GCLKp RESET# CPURESET# [6,10,51]
18 GCLKn

ITP_SMBCLK 22 21 MR_R#
[5,17,18,21,24,25,28,29] SMB_CLK_R SCL DBR# SYS_RESET# [7,21,38,44]
[5,17,18,21,24,25,28,29] SMB_DATA_R ITP_SMBDATA 24 SDA

28 NC RESERVED 12

+VTT_OUT_R

14 VTT GND1 2
GND5 5
GND2 8
GND6 11
1

NI/PROTO/ITP GND7 17
GCB1 20
B 0.1UF/16V GND3 B
26
2

GND4
GND8 27

GND
BtoB_CON_31P
NI/PROTO GND

PEGATRON P/N: 12X64A531W00

A A

ASUS OEM-DT MB RESTRICTED SECRET


Title : ITP_31P CONN.
PEGATRON CORP. Engineer: Wayne Hsieh
Size Project Name Rev
A3 IPM41-D3 1.00G
Date: Thursday, April 29, 2010 Sheet 9 of 55
5 4 3 2 1
5 4 3 2 1

I
+1P1V_CORE
NU1A
[6] HA#[3..35] HD#[0..63] [6]
I
HA#3 L36 F44 HD#0
HA3# HD0 NU1B

1
HA#4 L37 C44 HD#1 I
HA#5 HA4# HD1 HD#2 NR1
J38 HA5# HD2 D44
HA#6 HD#3 49.9
D HA#7
F40
H39
HA6# HD3 C41
E43 HD#4 D9
SDVO 1% D
HA7# HD4 [5] CK_100M_MCH EXP_CLKINP
HA#8 L38 B43 HD#5 E9
[5] CK_100M_MCH#

2
HA#9 HA8# HD5 HD#6 EXP_CLKINN
HA#10
L43
N39
HA9#
HA10#
FSB HD6
HD7
D40
B42 HD#7
SDVO_CTRL_DATA NOTE:
HA#11 N35 B38 HD#8 J13 Y7 EXP_RCOMP
HA11# HD8 [24] SDVO_CTRL_DATA SDVO_CTRLDATA EXP_RCOMPO
HA#12 N37 HA12# HD9 F38 HD#9 1 SDVO CARD PRESENT, PEG DISABLE [24] SDVO_CTRL_CLK G13 SDVO_CTRLCLK EXP_COMPI Y8 Breakout W/S:10/6
HA#13 J41 A38 HD#10 Y6
HA#14 N40
HA13# HD10
B37 HD#11 EXP_ICOMPO W/S:10/10
HA#15 HA14# HD11 HD#12
0 SDVO DISABLE(DEFAULT)
M45 HA15# HD12 D38 AB13 RESERVED3 EXP_RBIAS AG1 EXP_RBIAS
HA#16 R35 C37 HD#13 AD13
HA16# HD13 RESERVED4

1
HA#17 T36 D37 HD#14 I
HA#18 HA17# HD14 HD#15 NR2
R36 HA18# HD15 B36
HA#19 R34 E37 HD#16 750
HA#20 HA19# HD16 HD#17
R37 HA20# HD17 J35 1%
HA#21 HD#18
R39 H35
02G010024100 PCIE

2
HA#22 HA21# HD18 HD#19
U38 HA22# HD19 F37 GND
HA#23 T37 G37 HD#20 F6 C11
[24] EXP_RXP0 EXP_TXP0 [24]
HA#24
HA#25
U34
U40
HA23#
HA24#
HD20
HD21 J33
L33
HD#21
HD#22
C.S EAGLELAKE 82G41 A-3 G41 [24] EXP_RXN0 G7
H6
PEG_RXP_0
PEG_RXN_0
PEG_TXP0
PEG_TXN0 B11
A10
EXP_TXN0 [24]
HA25# HD22 [24] EXP_RXP1 PEG_RXP_1 PEG_TXP1 EXP_TXP1 [24]
HA#26 T34 G33 HD#23 G4 B9
HA26# HD23 [24] EXP_RXN1 PEG_RXN_1 PEG_TXN1 EXP_TXN1 [24]
HA#27 Y36 L31 HD#24 J6 C9
HA27# HD24 [24] EXP_RXP2 PEG_RXP_2 PEG_TXP2 EXP_TXP2 [24]
HA#28 U35 M31 HD#25 J7 D8
HA28# HD25 [24] EXP_RXN2 PEG_RXN_2 PEG_TXN2 EXP_TXN2 [24]
HA#29 AA35 M30 HD#26 L6 B8
HA29# HD26 [24] EXP_RXP3 PEG_RXP_3 PEG_TXP3 EXP_TXP3 [24]
HA#30 U37 J30 HD#27 L7 C7
HA30# HD27 [24] EXP_RXN3 PEG_RXN_3 PEG_TXN3 EXP_TXN3 [24]
HA#31 Y37 G31 HD#28 N9 B7
HA31# HD28 [24] EXP_RXP4 PEG_RXP_4 PEG_TXP4 EXP_TXP4 [24]
HA#32 Y34 K30 HD#29 N10 B6
HA32# HD29 [24] EXP_RXN4 PEG_RXN_4 PEG_TXN4 EXP_TXN4 [24]
HA#33 Y38 M29 HD#30 N7 B3
HA33# HD30 [24] EXP_RXP5 PEG_RXP_5 PEG_TXP5 EXP_TXP5 [24]
HA#34 AA37 G30 HD#31 N6 B4
HA34# HD31 [24] EXP_RXN5 PEG_RXN_5 PEG_TXN5 EXP_TXN5 [24]
HA#35 AA36 J29 HD#32 R7 D2
HA35# HD32 [24] EXP_RXP6 PEG_RXP_6 PEG_TXP6 EXP_TXP6 [24]
C F29 HD#33 R6 C2 C
[6] HREQ#[0..4] HD33 [24] EXP_RXN6 PEG_RXN_6 PEG_TXN6 EXP_TXN6 [24]
H29 HD#34 R9 H2
HD34 [24] EXP_RXP7 PEG_RXP_7 PEG_TXP7 EXP_TXP7 [24]
HREQ#0 G38 L25 HD#35 R10 G2
HREQ0# HD35 [24] EXP_RXN7 PEG_RXN_7 PEG_TXN7 EXP_TXN7 [24]
HREQ#1 K35 K26 HD#36 U10 J2
HREQ1# HD36 [24] EXP_RXP8 PEG_RXP_8 PEG_TXP8 EXP_TXP8 [24]
HREQ#2 J39 L29 HD#37 U9 K2
HREQ2# HD37 [24] EXP_RXN8 PEG_RXN_8 PEG_TXN8 EXP_TXN8 [24]
HREQ#3 C43 J26 HD#38 U6 K1
HREQ3# HD38 [24] EXP_RXP9 PEG_RXP_9 PEG_TXP9 EXP_TXP9 [24]
HREQ#4 G39 M26 HD#39 U7 L2
HREQ4# HD39 [24] EXP_RXN9 PEG_RXN_9 PEG_TXN9 EXP_TXN9 [24]
H26 HD#40 AA9 P2
HD40 [24] EXP_RXP10 PEG_RXP_10 PEG_TXP10 EXP_TXP10 [24]
F25 HD#41 AA10 M2
HD41 [24] EXP_RXN10 PEG_RXN_10 PEG_TXN10 EXP_TXN10 [24]
J40 F24 HD#42 R4 T2
[6] HADSTB0# HADSTB0# HD42 [24] EXP_RXP11 PEG_RXP_11 PEG_TXP11 EXP_TXP11 [24]
T39 G25 HD#43 P4 R1
[6] HADSTB1# HADSTB1# HD43 [24] EXP_RXN11 PEG_RXN_11 PEG_TXN11 EXP_TXN11 [24]
H24 HD#44 AA7 U2
HD44 [24] EXP_RXP12 PEG_RXP_12 PEG_TXP12 EXP_TXP12 [24]
C39 L24 HD#45 AA6 V2
[6] HDSTBP0# HDSTBP0# HD45 [24] EXP_RXN12 PEG_RXN_12 PEG_TXN12 EXP_TXN12 [24]
B39 J24 HD#46 AB10 W4
[6] HDSTBN0# HDSTBN0# HD46 [24] EXP_RXP13 PEG_RXP_13 PEG_TXP13 EXP_TXP13 [24]
B40 N24 HD#47 AB9 V3
[6] HDBI0# HDINV#0 HD47 [24] EXP_RXN13 PEG_RXN_13 PEG_TXN13 EXP_TXN13 [24]
C28 HD#48 AB3 AA4
HD48 [24] EXP_RXP14 PEG_RXP_14 PEG_TXP14 EXP_TXP14 [24]
K31 B31 HD#49 AA2 Y4
[6] HDSTBP1# HDSTBP1# HD49 [24] EXP_RXN14 PEG_RXN_14 PEG_TXN14 EXP_TXN14 [24]
J31 F35 HD#50 AD10 AC1
[6] HDSTBN1# HDSTBN1# HD50 [24] EXP_RXP15 PEG_RXP_15 PEG_TXP15 EXP_TXP15 [24]
F33 C35 HD#51 AD11 AB2
[6] HDBI1# HDINV#1 HD51 [24] EXP_RXN15 PEG_RXN_15 PEG_TXN15 EXP_TXN15 [24]
B35 HD#52
HD52 HD#53
[6] HDSTBP2# J25 HDSTBP2# HD53 D35
K25 D31 HD#54 NOTE:
[6] HDSTBN2# HDSTBN2# HD54
F26 A34 HD#55
[6] HDBI2# HDINV#2 HD55
HD56 B32 HD#56 Check Eaglelake PDG for detai if wanna
HD#57 +1P1V_FSB_VTT
[6] HDSTBP3# C32 HDSTBP3# HD57 F31
HD#58
support Integrated HDMI/DVI/DP
[6] HDSTBN3# D32
D30
HDSTBN3# HD58 D28
A29 HD#59 HXSWING W/S=10/10
DMI NCB26
[6] HDBI3# HDINV#3 HD59 NCB66
C30 HD#60 AD7 AC2 1 NCB67
2
HD60 [20] DMI_RXP0 DMI_RXP0 DMI_TXP0 DMI_TXP0 [20]

1
B HD61 B30 HD#61 HXRCOMP W/S=10/7 I [20] DMI_RXN0 AD8 DMI_RXN0 DMI_TXN0 AD2 1 NCB68
2 DMI_TXN0 [20] B
E27 HD#62 NR3 AE9 AD4 1 0.1UF/16V
2
HD62 [20] DMI_RXP1 DMI_RXP1 DMI_TXP1 NCB77 DMI_TXP1 [20]
J42 B28 HD#63 301 AE10 AE4 1 NCB78
2
[6] HADS# HADS# HD63 [20] DMI_RXN1 DMI_RXN1 DMI_TXN1 0.1UF/16V DMI_TXN1 [20]
[6] HTRDY# L40 HTRDY# I 1%
[20] DMI_RXP2 AE6 DMI_RXP2 DMI_TXP2 AE2 1 X7R 210%
NCB79
0.1UF/16V DMI_TXP2 [20]
J43 NR4 AE7 AF2 X7R
1 NCB80
210% I
[20] DMI_RXN2 DMI_TXN2 [20]

2
[6] HDRDY# HDRDY# DMI_RXN2 DMI_TXN2 0.1UF/16V
[6] HDEFER# G44 HDEFER#
49.9 1%
[20] DMI_RXP3 AF9 DMI_RXP3 DMI_TXP3 AF4 I 1 X7R 210%
0.1UF/16V DMI_TXP3 [20]
[6] HITM# K44 HITM# HSWING B24 HXSWING 2 1 HXSWING_R
[20] DMI_RXN3 AF8 DMI_RXN3 DMI_TXN3 AG4 1 X7R 210%
0.1UF/16V I DMI_TXN3 [20]
H45 I X7R 10%
[6] HIT# HIT# HXRCOMP X7R 10% 0.1UF/16V
[6] HLOCK# H40 HLOCK# HRCOMP A23 0.1UF/16V I
1

1
L42 10/07 modify I I I X7R 10%
[6] HBREQ0# HBREQ0# NCB1 NR6 +1P1V_FSB_VTT REV=1.4 X7R 10%
[6] HBNR# J44 HBNR# I
1

H37 I 0.1UF/16V 100 EAGLELAKE I


2

[6] HBPRI# HBPRI# NR5 X7R 10% 1%


[6] HDBSY# H42 HDBSY# 16.5
2

1
1% I
NR7
[6] HRS#[0..2]
2

GND 49.9
HRS#0 G43 GND 1%
HRS#1 HRS0# 9/9 modify
L44 I

2
HRS#2 HRS1# NR8
G42 HRS2# GND
49.9 1%
D27 C22 MCH_GTLREF0 2 1 R_MCH_GTLREF0
[6,9,51] CPURESET# HCPURST# HDVREF
HACCVREF B23
1

10/07 modify I
1

NI I NR9
P30 NCB2 NCB3 100
[5] CK_FSB_NB# HCLKN
P29 220PF/50V 1UF/16V 1%
[5] CK_FSB_NB
2

HCLKP X7R 10% X7R 10%


2

A
mx_c0603 A

N25 RESERVED
GND GND GND
REV=1.4 ASUS OEM-DT MB RESTRICTED SECRET
EAGLELAKE MCH_GTLREF0 W/S=10/7
Title :EAGLELAKE 1- 7
PEGATRON CORP. Engineer: Wayne Hsieh
Size Project Name Rev
A3 IPM41-D3 1.00G
Date: Thursday, July 09, 2009 Sheet 10 of 55
5 4 3 2 1
5 4 3 2 1

I
[17] M_CHA_MAA[1..14] NU1C
BC41 SMA_A0 SDQS_A0 BC5 M_CHA_DQS0 [17]
M_CHA_MAA1 BC35 BD4
SMA_A1 SDQS_A0# M_CHA_DQS0# [17]
M_CHA_MAA2 BB32 BC3
SMA_A2 SDM_A0 M_CHA_DM0 [17]
M_CHA_MAA3 BC32 SMA_A3 M_CHA_DQ[0..63] [17]
M_CHA_MAA4 BD32 BC2 M_CHA_DQ0
M_CHA_MAA5 SMA_A4 SDQ_A0 M_CHA_DQ1
BB31 SMA_A5 SDQ_A1 BD3
M_CHA_MAA6 AY31 BD7 M_CHA_DQ2
M_CHA_MAA7 SMA_A6 SDQ_A2 M_CHA_DQ3
D BA31 SMA_A7 SDQ_A3 BB7 D
M_CHA_MAA8 BD31 BB2 M_CHA_DQ4
M_CHA_MAA9 SMA_A8 SDQ_A4 M_CHA_DQ5
BD30 SMA_A9 SDQ_A5 BA3
M_CHA_MAA10 AW43 BE6 M_CHA_DQ6
M_CHA_MAA11 SMA_A10 SDQ_A6 M_CHA_DQ7
BC30 SMA_A11 SDQ_A7 BD6
M_CHA_MAA12 BB30
M_CHA_MAA13 SMA_A12
AM42 SMA_A13 SDQS_A1 BB9 M_CHA_DQS1 [17]
M_CHA_MAA14 BD28 BC9
SMA_A14 SDQS_A1# M_CHA_DQS1# [17]
SDM_A1 BD9 M_CHA_DM1 [17]
AW42 SWE_A#
AU42 BB8 M_CHA_DQ8
[17] M_CHA_CAS# SCAS_A# SDQ_A8
AV42 AY8 M_CHA_DQ9
[17] M_CHA_RAS# SRAS_A# SDQ_A9
BD11 M_CHA_DQ10
SDQ_A10 M_CHA_DQ11
[17] M_CHA_BA0 AV45 SBS_A0 SDQ_A11 BB11
AY44 BC7 M_CHA_DQ12
[17] M_CHA_BA1 SBS_A1 SDQ_A12 M_CHA_DQ13
[17] M_CHA_BA2 BC28 SBS_A2 SDQ_A13 BE8
BD10 M_CHA_DQ14
SDQ_A14 M_CHA_DQ15
[17] M_CHA_CS#0 AU43 SCS_A0# SDQ_A15 AY11
AR40 SCS_A1#
AU44 SCS_A2# SDQS_A2 BD15 M_CHA_DQS2 [17]
NOBOM 1 HT8 N27146510 AM43 BB15
SCS_A3# SDQS_A2# M_CHA_DQS2# [17]
SDM_A2 BD14 M_CHA_DM2 [17]
[17] M_CHA_CKE0 BB27 SCKE_A0
BD27 BB14 M_CHA_DQ16
[17] M_CHA_CKE1 SCKE_A1 SDQ_A16 M_CHA_DQ17
BA27 SCKE_A2 SDQ_A17 BC14
AY26 BC16 M_CHA_DQ18
SCKE_A3 SDQ_A18 M_CHA_DQ19
SDQ_A19 BB16
AR42 BC11 M_CHA_DQ20
[17] M_CHA_ODT0 SODT_A0 SDQ_A20 M_CHA_DQ21
[17] M_CHA_ODT1 AM44 SODT_A1 SDQ_A21 BE12
C NOBOM 1 HT11 N27146424 AR44 BA15 M_CHA_DQ22 C
SODT_A2 SDQ_A22 M_CHA_DQ23
AL40 SODT_A3 SDQ_A23 BD16

SDQS_A3 AR22 M_CHA_DQS3 [17]


SDQS_A3# AT22 M_CHA_DQS3# [17]
[17] M_CHA_CLK0 AY37 SCLK_A0 SDM_A3 AV22 M_CHA_DM3 [17]
[17] M_CHA_CLK0# BA37 SCLK_A0#
AW29 AW21 M_CHA_DQ24
SCLK_A1 SDQ_A24 M_CHA_DQ25
AY29 SCLK_A1# SDQ_A25 AY22
AU37 AV24 M_CHA_DQ26
[17] M_CHA_CLK2 SCLK_A2 SDQ_A26 M_CHA_DQ27
[17] M_CHA_CLK2# AV37 SCLK_A2# SDQ_A27 AY24
NOBOM 1 HT15 N27146426 AU33 AU21 M_CHA_DQ28
HT16 N27146514 SCLK_A3 SDQ_A28 M_CHA_DQ29
NOBOM 1 AT33 SCLK_A3# SDQ_A29 AT21
AT30 AR24 M_CHA_DQ30
HT18 N27146515 SCLK_A4 SDQ_A30 M_CHA_DQ31
NOBOM 1 AR30 SCLK_A4# SDQ_A31 AU24
NOBOM 1 HT19 N27146428 AW38
HT20 N27146516 SCLK_A5
NOBOM 1 AY38 SCLK_A5# SDQS_A4 AH43 M_CHA_DQS4 [17]
SDQS_A4# AH42 M_CHA_DQS4# [17]
SDM_A4 AK42 M_CHA_DM4 [17]
AL41 M_CHA_DQ32
SDQ_A32 M_CHA_DQ33
SDQ_A33 AK43
AG42 M_CHA_DQ34
SDQ_A34 M_CHA_DQ35
SDQ_A35 AG44
M_CHA_DQ36
DDR_A SDQ_A36
SDQ_A37
AL42
AK44 M_CHA_DQ37
M_CHA_DQ38
SDQ_A38 AH44
AG41 M_CHA_DQ39
SDQ_A39
B B
SDQS_A5 AD43 M_CHA_DQS5 [17]
SDQS_A5# AE42 M_CHA_DQS5# [17]
SDM_A5 AE45 M_CHA_DM5 [17]
AF43 M_CHA_DQ40
SDQ_A40 M_CHA_DQ41
SDQ_A41 AF42
AC44 M_CHA_DQ42
SDQ_A42 M_CHA_DQ43
SDQ_A43 AC42
AF40 M_CHA_DQ44
SDQ_A44 M_CHA_DQ45
SDQ_A45 AF44
AD44 M_CHA_DQ46
SDQ_A46 M_CHA_DQ47
SDQ_A47 AC41

SDQS_A6 Y43 M_CHA_DQS6 [17]


SDQS_A6# Y42 M_CHA_DQS6# [17]
SDM_A6 AA45 M_CHA_DM6 [17]
AB43 M_CHA_DQ48
SDQ_A48 M_CHA_DQ49
SDQ_A49 AA42
W42 M_CHA_DQ50
SDQ_A50 M_CHA_DQ51
SDQ_A51 W41
AB42 M_CHA_DQ52
SDQ_A52 M_CHA_DQ53
SDQ_A53 AB44
Y44 M_CHA_DQ54
SDQ_A54 M_CHA_DQ55
SDQ_A55 Y40

SDQS_A7 T44 M_CHA_DQS7 [17]


SDQS_A7# T43 M_CHA_DQS7# [17]
A SDM_A7 T42 M_CHA_DM7 [17] A

V42 M_CHA_DQ56
SDQ_A56 M_CHA_DQ57
SDQ_A57 U45
R40 M_CHA_DQ58
SDQ_A58 M_CHA_DQ59
SDQ_A59 P44
SDQ_A60 V44
V43
M_CHA_DQ60
M_CHA_DQ61
Title :EAGELLAKE 2 - 7
SDQ_A61 M_CHA_DQ62
SDQ_A62 R41
M_CHA_DQ63 PEGATRON CORP. Engineer: Wayne Hsieh
SDQ_A63 R44
Size Project Name Rev
REV=1.4
A3 IPM41-D3 1.00
EAGLELAKE
Date: Thursday, July 09, 2009 Sheet 11 of 55

5 4 3 2 1
5 4 3 2 1

[18] M_CHB_MAA[0..14]
NU1D
False
M_CHB_MAA0 BD24 AW8
SMA_B0 SDQS_B0 M_CHB_DQS0 [18]
M_CHB_MAA1 BB23 AW9
SMA_B1 SDQS_B0# M_CHB_DQS0# [18]
M_CHB_MAA2 BB24 AY6
SMA_B2 SDM_B0 M_CHB_DM0 [18]
M_CHB_MAA3 BD23 SMA_B3 M_CHB_DQ[0..63] [18]
M_CHB_MAA4 BB22 AV7 M_CHB_DQ0
M_CHB_MAA5 SMA_B4 SDQ_B0 M_CHB_DQ1
BD22 SMA_B5 SDQ_B1 AW4
M_CHB_MAA6 BC22 BA9 M_CHB_DQ2
M_CHB_MAA7 SMA_B6 SDQ_B2 M_CHB_DQ3
BC20 SMA_B7 SDQ_B3 AU11
D M_CHB_MAA8 BB20 AU7 M_CHB_DQ4 D
M_CHB_MAA9 SMA_B8 SDQ_B4 M_CHB_DQ5
BD20 SMA_B9 SDQ_B5 AU8
M_CHB_MAA10 BC26 AW7 M_CHB_DQ6
M_CHB_MAA11 SMA_B10 SDQ_B6 M_CHB_DQ7
BD19 SMA_B11 SDQ_B7 AY9
M_CHB_MAA12 BB19
M_CHB_MAA13 SMA_B12
BE38 SMA_B13 SDQS_B1 AT15 M_CHB_DQS1 [18]
M_CHB_MAA14 BA19 AU15
SMA_B14 SDQS_B1# M_CHB_DQS1# [18]
SDM_B1 AR15 M_CHB_DM1 [18]
BD36 AY13 M_CHB_DQ8
[18] M_CHB_WE# SWE_B# SDQ_B8
BC37 AP15 M_CHB_DQ9
[18] M_CHB_CAS# SCAS_B# SDQ_B9
BD35 AW15 M_CHB_DQ10
[18] M_CHB_RAS# SRAS_B# SDQ_B10
AT16 M_CHB_DQ11
SDQ_B11 M_CHB_DQ12
[18] M_CHB_BA0 BD26 SBS_B0 SDQ_B12 AU13
BB26 AW13 M_CHB_DQ13
[18] M_CHB_BA1 SBS_B1 SDQ_B13 M_CHB_DQ14
[18] M_CHB_BA2 BD18 SBS_B2 SDQ_B14 AP16
AU16 M_CHB_DQ15
SDQ_B15

[18] M_CHB_CS#0 BB35 SCS_B0# SDQS_B2 AR20 M_CHB_DQS2 [18]


[18] M_CHB_CS#1 BD39 SCS_B1# SDQS_B2# AR17 M_CHB_DQS2# [18]
BB37 SCS_B2# SDM_B2 AU17 M_CHB_DM2 [18]
NOBOM 1 HT25 N27146430 BD40 SCS_B3# M_CHB_DQ16
SDQ_B16 AY17
BC18 AV17 M_CHB_DQ17
[18] M_CHB_CKE0 SCKE_B0 SDQ_B17 M_CHB_DQ18
[18] M_CHB_CKE1 AY20 SCKE_B1 SDQ_B18 AR21
NOBOM 1 HT26 N27146431 BE17 AV20 M_CHB_DQ19
HT27 N27146432 SCKE_B2 SDQ_B19 M_CHB_DQ20
NOBOM 1 BB18 SCKE_B3 SDQ_B20 AP17
AW16 M_CHB_DQ21
SDQ_B21 M_CHB_DQ22
[18] M_CHB_ODT0 BD37 SODT_B0 SDQ_B22 AT20
C BC39 AN20 M_CHB_DQ23 C
[18] M_CHB_ODT1 SODT_B1 SDQ_B23
BB38 SODT_B2
NOBOM 1 HT29 N27146434 BD42 AU26
SODT_B3 SDQS_B3 M_CHB_DQS3 [18]
SDQS_B3# AT26 M_CHB_DQS3# [18]
SDM_B3 AV25 M_CHB_DM3 [18]
[18] M_CHB_CLK0 AY33 SCLK_B0
AW33 AT25 M_CHB_DQ24
[18] M_CHB_CLK0# HT30 N27146435 SCLK_B0# SDQ_B24 M_CHB_DQ25
NOBOM 1 AV31 SCLK_B1 SDQ_B25 AV26
NOBOM 1 HT31 N27146436 AW31 AU29 M_CHB_DQ26
SCLK_B1# SDQ_B26 M_CHB_DQ27
[18] M_CHB_CLK2 AW35 SCLK_B2 SDQ_B27 AV29
AY35 AW25 M_CHB_DQ28
[18] M_CHB_CLK2# HT32 N27146437 SCLK_B2# SDQ_B28 M_CHB_DQ29
NOBOM 1 AT31 SCLK_B3 SDQ_B29 AR25
NOBOM 1 HT33 N27146438 AU31 AP26 M_CHB_DQ30
HT34 N27146439 SCLK_B3# SDQ_B30 M_CHB_DQ31
NOBOM 1 AP31 SCLK_B4 SDQ_B31 AR29
DDR_REF NEED ROUTING NOBOM 1 HT35 N27146440 AP30 SCLK_B4#
AW37 AR38 M_CHB_DQS4 [18]
Width/Spacing: 12/12 mils NOBOM 1 HT37 N27146442 AV35
SCLK_B5 SDQS_B4
AR37
SCLK_B5# SDQS_B4# M_CHB_DQS4# [18]
SDM_B4 AU39 M_CHB_DM4 [18]
+1P5V_DUAL
AR43 AR36 M_CHB_DQ32
[17] M_CHA_CS#1 DDR3_A_CSB1 SDQ_B32 M_CHB_DQ33
[17] M_CHA_MAA0 BB40 DDR3_A_MA0 SDQ_B33 AU38
AT44 AN35 M_CHB_DQ34
[17] M_CHA_WE# DDR3_A_WEB SDQ_B34
AV40 AN37 M_CHB_DQ35
DDR3_B_ODT3 SDQ_B35 M_CHB_DQ36
[19] DDR3_DRAM_PWROK AR6 DDR3_DRAM_PWROK SDQ_B36 AV39
BC24 AW39 M_CHB_DQ37
[17,18] DDR3_DRAMRST# DDR3_DRAMRSTB SDQ_B37
1

AU40 M_CHB_DQ38
SDQ_B38
1

NI I AU41 M_CHB_DQ39
NCB4 NR11 SDQ_B39
AN29 RESERVED5
0.1UF/16V 1K NOBOM 1 HT39 N27146445 AN30 AK34 M_CHB_DQS5 [18]
2

B 1% HT40 N27146446 RESERVED6 SDQS_B5 B


NOBOM 1 AJ33 AL34 M_CHB_DQS5# [18]
2

RESERVED7 SDQS_B5#
AK33 RESERVED8 SDM_B5 AL37 M_CHB_DM5 [18]
DDR_VREF BB44 AL35 M_CHB_DQ40
DDR_VREF SDQ_B40 M_CHB_DQ41
SDQ_B41 AL36
GND AK36 M_CHB_DQ42
+1P5V_DUAL SDQ_B42 M_CHB_DQ43
SDQ_B43 AJ34
1

I I I AN39 M_CHB_DQ44
NR12 NCB115 NCB5 SDQ_B44 M_CHB_DQ45
I SDQ_B45 AN40
1K 1UF/10V 0.1UF/16V NR13 AK37 M_CHB_DQ46
2

1% mx_c0603 MCH_DDR_RPU SDQ_B46 M_CHB_DQ47


1 2 BA43 DDR_RPU SDQ_B47 AL39
MCH_DDR_RPD AY42
2

80.6 DDR_RPD
SDQS_B6 AF37 M_CHB_DQS6 [18]
1

1% I SDQS_B6# AF36 M_CHB_DQS6# [18]


1

I NR14 AJ35
SDM_B6 M_CHB_DM6 [18]
GND GND GND NCB6 80.6
0.1UF/16V 1% AJ38 M_CHB_DQ48
2

090420 add by TSL SDQ_B48 M_CHB_DQ49


AJ37
2

SDQ_B49 M_CHB_DQ50
SDQ_B50 AF38
AE37 M_CHB_DQ51
SDQ_B51 M_CHB_DQ52
MCH_DDR_RPU, MCH_DDR_RPD, MCH_DDR_SPU, MCH_DDR_SPD SDQ_B52 AK40
GND GND AJ40 M_CHB_DQ53
SDQ_B53 M_CHB_DQ54
NEED ROUTING LESS THEN 1000MIL LENGTH. SDQ_B54 AF34
AE35 M_CHB_DQ55
+1P5V_DUAL I SDQ_B55
WIDTH/SPACING = 10/10 MIL
NR15 AB35
SDQS_B7 M_CHB_DQS7 [18]
1 2 MCH_DDR_SPU BC44 AD35
DDR_SPU SDQS_B7# M_CHB_DQS7# [18]
MCH_DDR_SPD BC43 AD37
DDR_SPD SDM_B7 M_CHB_DM7 [18]
A
80.6 A
1

1% I AD40 M_CHB_DQ56
SDQ_B56
1

I NR16 AD38 M_CHB_DQ57


NCB7 SDQ_B57 M_CHB_DQ58
249 SDQ_B58 AB40
0.1UF/16V 1% AA39 M_CHB_DQ59
2

SDQ_B59 M_CHB_DQ60
AE36
2

SDQ_B60
SDQ_B61 AE39 M_CHB_DQ61
M_CHB_DQ62
Title :EAGLELAKE 3 - 7
DDR_B SDQ_B62
SDQ_B63
AB37
AB38 M_CHB_DQ63
PEGATRON CORP. Engineer: Wayne Hsieh
GND GND
REV=1.4 Size Project Name Rev
EAGLELAKE A3 IPM41-D3 1.00
Date: Thursday, July 09, 2009 Sheet 12 of 55

5 4 3 2 1
5 4 3 2 1

I NOTE:
NU1E
Install NR67 NR68 and NOT Install NR18 NR21 for non-Graphics SKU

I 5% 1 NRN1A D14 VGA_HSYNC_3P3V I NR18 33


[5,7] M_HBSEL0 1KOHM 2 F17 BSEL0 CRT_HSYNC 1 2 VGA_HSYNC [26]
I 5% 3 NRN1B C14 VGA_VSYNC_3P3V I NR21 33
[5,7] M_HBSEL1 1KOHM 4 G16 BSEL1 CRT_VSYNC 1 2 VGA_VSYNC [26]
I 5% 5 NRN1C
[5,7] M_HBSEL2 1KOHM 6 P15 BSEL2

EXP_EN G15
DUALX8_EN RESERVED9
D F20 DUALX8_ENABLE D
M20 ALLZTEST CRT_RED B18 VGA_RED [26]
N17 XORTEST CRT_GREEN D18 VGA_GREEN [26]
1K 2 1 NI NR66 X16_OCC K16 C18
[24] PCIE_B7 RSVD CRT_BLUE VGA_BLUE [26]
0 1 2 NR76 EXP_SM H17 F13
[24] EXP_EN_HDR EXP_SM CRT_IRTN
NOBOM EXP_SLR F15
ITPM_EN# EXP_SLR
L17 ITPM_EN#

1
TCEN J17 I I I
CEN

1
NI NI NI NR25 NR26 NR27
NC1 NC2 NC3 150 150 150
22PF/50V 22PF/50V 22PF/50V 1% 1% 1%

2
1

2
NI NI NI NI NI NI NI
NR30 NR75 NR32 NR22 NR23 NR24 NR28 AN17
1K 1K 1K 1K 1K 1K 1K NC1
A44 NC2 GND GND GND GND
BD1 GND GND GND
2

2
NC3
BD45
BE2
NC4
NC5
VGA PLACED CAPACITOR CLOSE TO PLACED RESISTOR CLOSE TO
BE44
GND GND GND GND GND GND GND B14
NC6 GMCH FOR EMI GMCH WITHIN 250 MIL LENGTH
NC7
B45 NC8
AK15 NC9
AD42 NC10 CRT_DDC_DATA L15 DDCA_DATA [26]
AN16 NC11 CRT_DDC_CLK M15 DDCA_CLK [26]
W30 NC12
NOTE: AW44 NC13
R42 NC14 NOTE:
PIN HIGH LOW DESCRIPTION U32 B15 DACREFSET
NC15 DAC_IREF
Change NR33 and NR25~NR27 to 0 OHM for non-Graphics SKU,
C
EXP_SM CONCURRENT NOT PCI-E/SDVO KEEP PU resistor VR14~15 for DDCDATA/CLK
C

1
CONCURRENT PLACED RESISTOR I
NR33
DUALX8 1x16 PCIe 2x8 PCIe DUALX8 ENABLE CLOSE TO THE GMCH 1K
M17 RESERVED10 WITHIN 500 MIL 1%
X16_OCC NOT PRESENCE PCIe CARD IN G20
LENGTH

2
BSCANTEST
J16
PRESENCE PRIMARY SLOT M16
RESERVED12
RESERVED13
EXP_SLR NORMAL RESERVE PCI-E LANE RESERVAL J15 RESERVED14
J20 GND
ATX BTX AR7
RESERVED16
JTAG_TDI
ITPM_EN# DISABLE ENABLE iTPM Enable AN10 JTAG_TDO
AN11 JTAG_TCK
TCEN ENABLE DISABLE TLS CONFIDENTALITY AN9 JTAG_TMS
R31 RESERVED22 DREFCLKINP E15 CK_96M_DREF [5]
R32 RESERVED23 DREFCLKINN D15 CK_96M_DREF# [5]
U30 RESERVED24
U31 RESERVED25 DPL_REFSSCLKP G8
R15 RESERVED26 DPL_REFSSCLKN G9
R14 RESERVED27
T15 RESERVED28
+1P1V_CORE T14 RESERVED29
AB15 RESERVED30
L13 RESERVED32
1

I L11 RESERVED33
NR35 AN6
RSTIN# LRESET# [21,37,39]
1K CLINK VREF TARGET=0.349V
1% AR4
PWROK PWROK [21,38]
2

B CL_VREF B
AN13 CL_VREF ICH_SYNC# K15 ICH_SYNC# [21]
AY4 CL_DATA
AY2 CL_CLK
2

I I 1 3K 2 NR80 AW2 CL_RST#


1

NR38 I [21,37,39] LRESET# AN8


NCB8 CL_PWROK
464OHM HDA_BCLK AU4
1

1% 0.1UF/16V I AV4
2

NR81 HDA_RST#
AU2
1

1.5K HDA_SDI
HDA_SDO AV1
HDA_SYNC AU3
2

GND GND
GND
GND

NOTE:
[21,38] PWROK
HDMI PORTC DDC Control CLK
NOTE: MISC HDMI PORTC DDC Control DATA
Install NR45 for non-iAMT support DDPC_CTRLCLK J11
DDPC_CTRLDATA F11

A45 TEST0
B2 TEST1
A BE1 TEST2 DPRSTP# P43 R_RESERVED_F1# DPRSTP# [7] A
BE45 TEST3 SLP# P42 R_PM_SLP# PM_SLP# [7,20]

NOTE:
REV=1.4
NR69 NR46 place near CPU side
ASUS OEM-DT MB RESTRICTED SECRET
EAGLELAKE
Title :EAGLELAKE 4 - 7
PEGATRON CORP. Engineer: Wayne Hsieh
Size Project Name Rev
A3 IPM41-D3 1.00G
Date: Thursday, July 09, 2009 Sheet 13 of 55
5 4 3 2 1
5 4 3 2 1

I
+1P1V_CORE NL1
1UH/300mA
mx_l0805 0 +1P1V_CORE I
+1P1V_GPLLD_R NR47 +1P1V_GPLLD +1P1V_CORE
1 2 1 2 NU1F
NOBOM 0
AA19 VCC_3 VCC_73 R26

1
NR48
1 2 NI NI AA21 VCC_4 VCC_74 R27
NCB9 NCB10 AA23 R29
VCC_5 VCC_75

1
NOBOM 10UF/6.3V 0.1UF/16V AA25 T21 I I I

2
X5R 10% X7R 10% VCC_6 VCC_81 NCB24 NCB11 NCB12
AA27 VCC_7 VCC_82 T24
mx_c0805 AA29 T25 22UF/6.3V 22UF/6.3V 22UF/6.3V

2
VCC_8 VCC_83 X5R 20% X5R 20% X5R 20%
D I AA30 VCC_9 VCC_84 T26 D
+1P1V_CORE NL2 AB20 T27 mx_c1206 mx_c1206 mx_c1206
1UH/300mA GND VCC_12 VCC_85
GND AB22 VCC_13 VCC_86 T29 Y Y Y
mx_l0805 0 AB24 U21
+1P1V_GPLL_R NR49 +1P1V_GPLL VCC_14 VCC_92 GND GND
1 2 1 2 AB26 VCC_15 VCC_93 U22 GND
AB29 VCC_16 VCC_94 U23
NOBOM 0
AB30 VCC_17 VCC_95 U24

1
NR50
1 2 NI NI AC16 VCC_18 VCC_96 U25
NCB13 NCB14 AC17 U26
VCC_19 VCC_97

1
NOBOM 10UF/6.3V 0.1UF/16V AC19 U27 I NI I NI

2
X5R 10% X7R 10% VCC_20 VCC_98 NCB25 NCB15 NCB16 NCB17
AC21 VCC_21 VCC_99 U29
+1P1V_CORE I mx_c0805 AC23 W19 10UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V

2
NL7 VCC_22 VCC_102 X5R 10% X5R 10% X5R 10% X5R 10%
AC25 VCC_23 VCC_103 W21
2.2UH/250mA GND GND AC27 W23 mx_c0805 mx_c0805 mx_c0805 mx_c0805
mx_l0805 VCC_24 VCC_104
AC29 VCC_25 VCC_105 W25
1 2 +1P1V_MPLL AD16 W27
VCC_26 VCC_106 GND GND GND GND
AD17 VCC_27 VCC_107 W29
0 AD20 Y20 10/2 modify
NR51 +1P1V_MPLL_R VCC_28 VCC_110
1 2 AD22 VCC_29 VCC_111 Y22
AD24 VCC_30 VCC_112 Y24
NOBOM 0
AD26 VCC_31 VCC_113 Y26

1
NR52
1 2 NOTE: AD29 VCC_32 VCC_114 T22 I I NI NI

1
I AE16 T23 NCB19 NCB20 NCB21 NCB22
NOBOM VCC_33 VCC_115
NCB18 Install NCB18 for EA issue AE17 AC4 1UF/16V 1UF/16V 1UF/16V 1UF/16V

2
10UF/6.3V VCC_34 VCC_116 X7R 10% X7R 10% X7R 10% X7R 10%
AE19 AF3

2
X5R 10% VCC_35 VCC_117 mx_c0603 mx_c0603 mx_c0603 mx_c0603
AE21 VCC_36 VCC_118 F9
mx_c0805 AE23 H4
NOTE: AE25
VCC_37 VCC_119
L3 GND GND GND GND
VCC_38 VCC_120 10/2 modify
+1P1V_CORE
Install NL3 NL4 for iAMT support GND AE27 VCC_39 VCC_121 P3
C AE29 V4 Core edge CAP decoupling, Place in C

POWER
I NL5 Install NL5 NL7 for non-iAMT support AF16
VCC_40 VCC_122
0.27UH/170mA mx_l0603 AF17
VCC_41 PCI-E breakout
+1P1V_HPLL VCC_42
1 2 AF19 VCC_43
AF20 VCC_44
AF21 VCC_45

1
NI AF22 VCC_46
NCB23 AF23
2.2UF/6.3V VCC_47
AF24

2
X5R 10% VCC_48
I AF25 VCC_49
+1P1V_CORE NL6 mx_c0603 AF26 AA14
10UH/125mA VCC_50 VCC_EXP_1
GND AF27 VCC_51 VCC_EXP_2 AA15
mx_l0805 AF29 AB14
+1P1V_DPLLB VCC_52 VCC_EXP_3
1 2 AG16 VCC_53 VCC_EXP_4 AC15
AG17 AD14 +1P1V_PCIEXPRESS +1P1V_CORE
VCC_54 VCC_EXP_6
AG20 VCC_55 VCC_EXP_7 AD15 NOBOM
1

1
I NI AG22 AE14 NJP1
NCE1 NCB27 VCC_56 VCC_EXP_8
AG24 VCC_57 VCC_EXP_9 AE15 2 SHORTPIN_RECT
1
10UF/6.3V 0.1UF/16V AG26 AF14
2

X5R 10% X7R 10% VCC_58 VCC_EXP_10


AG29 VCC_59 VCC_EXP_11 AF15 NOBOM
I mx_c0805 AJ16 AG15 NJP2
+1P1V_CORE NL8 VCC_60 VCC_EXP_13
AJ17 VCC_61 VCC_EXP_14 AJ10 2 SHORTPIN_RECT
1
10UH/125mA GND GND AJ19 AJ11
mx_l0805 VCC_62 VCC_EXP_15
AJ21 VCC_63 VCC_EXP_16 AJ12 NOBOM
1 2 +1P1V_DPLLA AJ23 AJ13 NJP3
VCC_64 VCC_EXP_17
AJ25 VCC_65 VCC_EXP_18 AJ14 2 SHORTPIN_RECT
1
R25 VCC_72 VCC_EXP_19 AJ6
1

I NI VCC_EXP_20 AJ7

1
NCE2 NCB30 AJ8 I I I
B 10UF/6.3V 0.1UF/16V VCC_EXP_21 NCB65 NCB28 NCB29 B
AJ9
2

X5R 10% X7R 10% VCC_EXP_22 2.2UF/6.3V 2.2UF/6.3V 2.2UF/6.3V


AK10

2
mx_c0805 VCC_EXP_23 X5R 10% X5R 10% X5R 10%
VCC_EXP_24 AK11
AK12 mx_c0805 mx_c0805 mx_c0805
VCC_EXP_25
VCC_EXP_26 AK13
GND GND VCC_EXP_27 AK6
AK7 GND GND GND
VCC_EXP_28
VCC_EXP_29 AK8
+1P1V_CORE AK9
VCC_EXP_30
VCC_EXP_35 U14
B12 VCCD_PLL_EXP VCC_EXP_36 U15
VCC_EXP_38 W15
1

B16 VCCA_PLL_EXP VCC_EXP_39 Y14


NR53 Y15
0 VCC_EXP_40
VCC_EXP_41 AJ1
NOBOM A21 VCCA_MPLL VCC_EXP_42 AJ2
AK2
2

VCC_EXP_43
B22 VCCA_HPLL VCC_EXP_44 AK3
VCC_EXP_45 AK4
+1P1V_HPLL_D U33 NOBOM +1P1V_CORE
VCCD_HPLL NR79
C20 0
VCCA_DPLLB
1 2
+3P3V D20 VCCA_DPLLA
+1P5V_ICH
E19 NI
VCC_3P3
NR78
A AR2 AG2 VCCAVRM_EXP_R 2 1 A
VCC_HDA VCCAVRM_EXP
0
1

1
REV=1.4
NI
NCB38
I
NCB39 GND EAGLELAKE
NI
NCB76 ASUS OEM-DT MB RESTRICTED SECRET
4.7UF/6.3V 0.1UF/16V 4.7UF/6.3V
2

2
X5R 10% X7R 10% X5R 10% Title :EAGLELAKE 5 - 7
mx_c0805 mx_c0805
PEGATRON CORP. Engineer: Wayne Hsieh
GND GND GND Size Project Name Rev
A3 IPM41-D3 1.00G
Date: Thursday, July 09, 2009 Sheet 14 of 55
5 4 3 2 1
5 4 3 2 1

Place near GMCH +1P1V_FSB_VTT I


+1P5V_DUAL
NU1G
A25 VTT1 0 NL9 BOTTOM
B25 AK32 VCCCK_DDR 2 1
VTT2 VCC_SMCLK1
B26 VTT3 VCC_SMCLK2 AL31

1
I I I C24 AL32 NOBOM
VTT4 VCC_SMCLK3

1
NCB40 NCB45 NCB46 mx_r1206_short
D C26 VTT5 VCC_SMCLK4 AM31 NI D
2.2UF/6.3V 2.2UF/6.3V 2.2UF/6.3V D22 NCB47

2
X5R 10% X5R 10% X5R 10% VTT6 0.1UF/16V
D23

2
mx_c0603 mx_c0603 mx_c0603 VTT7 X7R 10%
D24 VTT8 NINR57 1 2 1 V_CKDDR_R
E23 VTT9 BOTTOM BOTTOM
GND GND GND F21 VTT10
F22 VTT11 NINR56 1 2 1
G21 VTT12 GND BOTTOM
G22 AA32 10/2 modify
VTT13 VCC_CL1

1
H21 VTT14 VCC_CL2 AA33 NI
H22 AB32 NCB48
VTT15 VCC_CL3 10UF/6.3V
J21 AB33

2
VTT16 VCC_CL4

1
NI NI I J22 AD32 X5R 10%
NCB49 NCB41 NCB42 VTT17 VCC_CL5 mx_c0805
K21 VTT18 VCC_CL6 AD33
0.1UF/16V 0.1UF/16V 0.1UF/16V K22 AE32 BOTTOM

2
X7R 10% X7R 10% X7R 10% VTT19 VCC_CL7 +1P1V_CL +1P1V_CORE
L21 VTT20 VCC_CL8 AE33
L22 VTT21 VCC_CL9 AF32 GND
M21 VTT22 VCC_CL10 AJ32 NOBOM
M22 AK31 NJP10
VTT23 VCC_CL11
GND GND GND N20 VTT24 VCC_CL12 AL30 2 SHORTPIN_RECT
1
N21 VTT25 VCC_CL13 AM15
N22 VTT26 VCC_CL14 AM16 NOBOM
P20 AM17 NJP9
VTT27 VCC_CL15
P21 VTT28 VCC_CL16 AM20 2 SHORTPIN_RECT
1
P22 VTT29 VCC_CL17 AM21
P24 VTT30 VCC_CL18 AM22 NOBOM
R20 AM24 NJP8
VTT31 VCC_CL19
R21 VTT32 VCC_CL20 AM25 2 SHORTPIN_RECT
1
R22 VTT33 VCC_CL21 AM26
C
Place a via in between cap and GMCH on R23 VTT34 VCC_CL22 AM29 C
R24 Y32
GND trace.It means that the GND for cap VTT35 VCC_CL23

1
+1P5V_DUAL Y33 NI I I
VCC_CL24
has to be independent VCC_CL25 AP1 NCB50 NCB51 NCB52
AP2 0.1UF/16V 10UF/6.3V 10UF/6.3V

2
VCC_CL26 X7R 10% X5R 10% X5R 10%
AP44 VCCSM1 VCC_CL27 Y31
AT45 AA31 mx_c0805 mx_c0805
VCCSM2 VCC_CL28
AV44 VCCSM3 VCC_CL29 AB31
AY40 VCCSM4 VCC_CL30 AC31
1

NI I I I I I I BA41 VCCSM5 VCC_CL31 AD31 GND GND GND


NCB43 NCB53 NCB54 NCB44 NCB55 NCB56 NCB57 BB39 AE31
2.2UF/6.3V 2.2UF/6.3V 2.2UF/6.3V 2.2UF/6.3V 2.2UF/6.3V 2.2UF/6.3V 2.2UF/6.3V VCCSM6 VCC_CL32
BD21 AF31
2

X5R 10% X5R 10% X5R 10% X5R 10% X5R 10% X5R 10% X5R 10% VCCSM7 VCC_CL33
BD25 VCCSM8 VCC_CL34 AG30
mx_c0603 mx_c0603 mx_c0603 mx_c0603 mx_c0603 mx_c0603 mx_c0603 BD29 AG31
VCCSM9 VCC_CL35 +1P1V_CORE
BD34 VCCSM10 VCC_CL36 AJ30 BACKSIDE CAPS FOR SPECIFIC +1P1V_CORE GMCH
BD38 VCCSM11 VCC_CL37 AJ31
GND GND GND GND GND GND GND BE23 VCCSM12 VCC_CL38 AK16
BE27 VCCSM13 VCC_CL39 AK17
BE31 VCCSM14 VCC_CL40 AK19
BE36 VCCSM15 VCC_CL41 AK20

1
+3P3V +3P3V_DAC_FB AK21 NI NI NI NI
VCC_CL42 NCB58 NCB59 NCB60 NCB61
VCC_CL43 AK22
NL10 0 AK23 10UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V

2
+3P3V_DAC_VCCA VCC_CL44 X5R 10% X5R 10% X5R 10% X5R 10%
1 2 B19 VCCA_DAC1 VCC_CL45 AK24
D19 AK25 mx_c0805 mx_c0805 mx_c0805 mx_c0805
NOBOM VCCA_DAC2 VCC_CL46
VCC_CL47 AK26 BOTTOM BOTTOM BOTTOM BOTTOM
1

mx_r0603_short
+ NI I VCC_CL48 AK27
NCE3 NCB62 AK29 GND GND GND GND
220UF/16V 1UF/16V VCC_CL49
AK30
2

B X7R 10% VCC_CL50 B


AL1
2

VCC_CL51
2

mx_c0603 I AL10
NR60 VCC_CL52
VCC_CL53 AL11
40.2 OHM VCC_CL55 AL26

1
GND GND 1% VCC_CL56 AL12 NI NI NI NI
AL15 NCB63 NCB64 NCB69 NCB70
1

0 VCC_CL57 1UF/16V 1UF/16V 1UF/16V 1UF/16V


AL17

2
+1P5V_EXP_FB NR61 VCCABG_EXP VCC_CL58 X7R 10% X7R 10% X7R 10% X7R 10%
1 2 A17 VCCA_EXP VCC_CL59 AL19
AL2 mx_c0603 mx_c0603 mx_c0603 mx_c0603
NOBOM VCC_CL60
VCC_CL61 AL20 BOTTOM BOTTOM BOTTOM BOTTOM
2

I AL21
NR62 VCC_CL62 GND GND
VCC_CL63 AL22 GND GND
39.2 OHM VCC_CL64 AL23
1% VCC_CL65 AL16
AL24
1

VCC_CL66
VCC_CL67 AL25
VCC_CL68 AL27
+1P5V_ICH +CPU_VCCPLL AL29
VCC_CL69

1
NJP7 GND VCC_CL70 AL4 NI NI NI NI
NL11 0 AL5 NCB71 NCB72 NCB73 NCB74
VCC_CL71
2 1 1 2VCCDQ_CRT_R VCCDQ_CRT B20 AL6 1UF/16V 1UF/16V 1UF/16V 1UF/16V

2
VCCDQ_CRT VCC_CL72 X7R 10% X7R 10% X7R 10% X7R 10%
VCC_CL73 AL7
NOBOM B17 AL8 mx_c0603 mx_c0603 mx_c0603 mx_c0603
SHORTPIN_RECT VSS0 VCC_CL74
1

mx_r0603_short
NI VCC_CL75 AL9 BOTTOM BOTTOM BOTTOM BOTTOM
NOBOM NCB75 AM2
1UF/16V VCC_CL76
AM3 GND GND GND GND
2

X7R 10% VCC_CL77


GND VCC_CL78 AM4
mx_c0603 AL14
VCC_CL79
A VCC_CL80 AJ15 A
+1P1V_CORE AK14
VCC_CL81
I GND VCC_CL82 AJ27
NL12
1 2 VCCCML_DDR AM30
VCC_CL83 AJ29
W31
ASUS OEM-DT MB RESTRICTED SECRET
VCCCML_DDR VCC_CL84
VCC_CL85 Y30
0.1UH/300mA
mx_l0603 REV=1.4 VCC_CL86
Y29 Title :EAGLELAKE 6 - 7
EAGLELAKE Engineer:
PEGATRON CORP. Wayne Hsieh
Size Project Name Rev
A3 IPM41-D3 1.00G
Date: Thursday, July 09, 2009 Sheet 15 of 55

5 4 3 2 1
5 4 3 2 1

I
NU1H
A12 VSS1 VSS170 AP20
A15 VSS2 VSS169 AP22 I
A19
A27
VSS3 VSS168 AP24
AP29 NU1I EAGLELAKE-P/Q/G (25.2W/23.4W/25.5W)
VSS4 VSS167
A31 VSS5 VSS166 AP45
A36 VSS6 VSS165 AR10 AK35 VSS171 VSS345 AV6 13G070432001 HEATSINK 55.2*37.6*30MM SILVER
A40 VSS7 VSS164 AR11 AK38 VSS172 VSS344 AU6
D AA1 VSS8 VSS163 AR13 AK39 VSS173 VSS343 AU5 13G070432000 HEATSINK 55.2*37.6*30MM SILVER D
AA11 VSS9 VSS162 AR16 AL38 VSS174 VSS342 AP25
AA12 VSS10 VSS161 AR26 AL44 VSS175 VSS341 AP21 13G070432002 HEATSINK 55.2*37.6*30MM SILVER
AA13 VSS11 VSS160 AR3 AL45 VSS176 VSS340 AN26
AA20 VSS12 VSS159 AR31 AN33 VSS177 VSS339 C16
AA22 VSS13 VSS158 AR33 AN36 VSS178 VSS338 N38
AA24 VSS14 VSS157 AR35 AN38 VSS179 VSS337 N8
AA26 VSS15 VSS156 AR39 AN7 VSS180 VSS336 P25
AA34 VSS16 VSS155 AR8 A8 VSS181 VSS335 P26 I
AA38 VSS17 VSS154 AR9 D11 VSS182 VSS334 P31 HEATSINK1
AA40 VSS18 VSS153 AT1 D16 VSS183 VSS333 R11
AA44 VSS19 VSS152 AT11 D21 VSS184 VSS332 R12 8 1
AA8 VSS20 VSS151 AT13 D25 VSS185 VSS331 R2 7 2
AB11 VSS21 VSS150 AT17 D26 VSS186 VSS330 R38
AB12 VSS22 VSS149 AT2 D39 VSS187 VSS329 R45
AB19 VSS23 VSS148 AT24 D6 VSS188 VSS328 R5 6 3
AB21 VSS24 VSS147 AT29 D7 VSS189 VSS327 R8 5 4
AB23 VSS25 VSS146 AY15 B10 VSS190 VSS326 T10
AB25 AT35 E3 T11 HEATSINK_4ANCHOR
VSS26 VSS145 VSS191 VSS325
AB27 VSS27 VSS144 AU22 E31 VSS192 VSS324 T12 T725
AB34 VSS28 VSS143 AU25 E41 VSS193 VSS323 T13 GND GND
AB36 AU30 E5 T3 8/11 change to 13X070401000
VSS29 VSS142 VSS194 VSS322
AB39 VSS30 VSS141 AU9 F16 VSS195 VSS321 T31
AB4 VSS31 VSS140 AV11 F2 VSS196 VSS320 T32
AB6 VSS32 VSS139 AV13 F30 VSS197 VSS319 T33
AB7 VSS33 VSS138 AV15 F4 VSS198 VSS318 T35
AB8 VSS34 VSS137 AV16 F42 VSS199 VSS317 T38
AC20 VSS35 VSS136 AV2 F45 VSS200 VSS316 T4
AC22 VSS36 VSS135 AV21 F8 VSS201 VSS315 T40
C AC24 AV30 G11 T6 I I I I C
VSS37 VSS134 VSS202 VSS314
AC26 AV38 G17 T7
AC45
AC5
VSS38
VSS39
VSS40
GND VSS133
VSS132
VSS131
AV8
AV9
G24
G26
VSS203
VSS204
VSS205
VSS313
VSS312
VSS311
T8
T9
CLIP1
ANCHOR_CLIP
CLIP2
ANCHOR_CLIP
CLIP3
ANCHOR_CLIP
CLIP4
ANCHOR_CLIP
AD12 AW11 G29 U1 ANGLE_45 ANGLE_45 ANGLE_45 ANGLE_45
VSS41 VSS130 VSS206 VSS310
AD19 AW17 G3 U11
AD21
AD23
VSS42
VSS43
VSS44
VSS129
VSS128
VSS127
AW20
AW22
G35
H1
VSS207
VSS208
VSS209
GND VSS309
VSS308
VSS307
U12
U13
AD25 VSS45 VSS126 AW24 H11 VSS210 VSS306 U36
AD27 VSS46 VSS125 AW26 H13 VSS211 VSS305 U39
AD3 VSS47 VSS124 AW3 H15 VSS212 VSS304 U44
AD34 VSS48 VSS123 AW30 H16 VSS213 VSS303 U8
AD36 VSS49 VSS122 AY1 H20 VSS214 VSS302 W1
AD39 VSS50 VSS121 AY16 H25 VSS215 VSS301 W2
AD6 VSS51 VSS120 AY21 H30 VSS216 VSS300 W20
AD9 VSS52 VSS119 AY25 H31 VSS217 VSS299 W22
AE1 VSS53 VSS118 AY30 H33 VSS218 VSS298 W24
AE11 VSS54 VSS117 AY45 H44 VSS219 VSS297 W26
AE20 VSS55 VSS116 B21 H7 VSS220 VSS296 W44
AE22 VSS56 VSS115 B27 H8 VSS221 VSS295 W45
AE24 VSS57 VSS114 B29 H9 VSS222 VSS294 W5
AE26 VSS58 VSS113 B34 J3 VSS223 VSS293 Y10
AE34 VSS59 VSS112 BA23 J37 VSS224 VSS292 Y11
AE38 VSS60 VSS111 BA5 J4 VSS225 VSS291 Y12
AE40 VSS61 VSS110 BB21 J5 VSS226 VSS290 Y13
AE44 VSS62 VSS109 BB25 J8 VSS227 VSS289 Y19
AE8 VSS63 VSS108 BB28 J9 VSS228 VSS288 Y2
AF10 VSS64 VSS107 BB6 K11 VSS229 VSS287 Y21
AF11 VSS65 VSS106 BD12 K13 VSS230 VSS286 Y23
B B
AF12 VSS66 VSS105 BD17 K17 VSS231 VSS285 Y25
AF13 VSS67 VSS104 BD43 K20 VSS232 VSS284 Y27
AF33 VSS68 VSS103 BD8 K24 VSS233 VSS283 Y3
AF35 VSS69 VSS102 BE10 K29 VSS234 VSS282 Y35
AF39 VSS70 VSS101 BE15 K33 VSS235 VSS281 Y39
AF6 VSS71 VSS100 BE19 K45 VSS236 VSS280 Y9
AF7 VSS72 VSS99 BE21 L10 VSS237 VSS279 AN22
AG19 VSS73 VSS98 BE25 L16 VSS238 VSS277 AE13
AG21 VSS74 VSS97 BE29 L20 VSS239 VSS276 AN24
AG23 VSS75 VSS96 BE34 L26 VSS240 VSS275 AU35
AG25 VSS76 VSS95 BE40 L30 VSS241 VSS274 AN25
AG27 VSS77 VSS94 AV33 L35 VSS242 VSS273 AE12
AG45 VSS78 VSS93 C3 L39 VSS243 VSS271 AN21
AG5 VSS79 VSS92 C5 L4 VSS244 VSS270 A3
AH2 VSS80 VSS91 H38 L8 VSS245 VSS269 A43
AH3 VSS81 VSS90 AJ45 L9 VSS246 VSS268 A6
AH4 VSS82 VSS89 AJ44 M1 VSS247 VSS267 B44
AJ20 VSS83 VSS88 AJ39 M24 VSS248 VSS266 BC1
AJ22 VSS84 VSS87 AJ36 M25 VSS249 VSS265 BC45
AJ24 VSS85 VSS86 AJ26 M44 VSS250 VSS264 BD2
N11 VSS251 VSS263 BD44
VSS370 Y17 N13 VSS252 VSS262 BE3
AU20 VSS346 VSS369 Y16 N26 VSS253 VSS261 BE43
AA16 VSS347 VSS368 W17 N29 VSS254
AA17 VSS348 VSS367 W16 N30 VSS255
AB16 VSS349 VSS366 U20 N33 VSS256
AB17 VSS350 VSS365 U19 N36 VSS257 VSS371 AD30
N16 VSS351 VSS364 U17 F1 VSS258 VSS372 AC30
A P16 VSS352 VSS363 U16 C45 VSS259 VSS373 AF30 A
P17 VSS353 VSS362 T30 C1 VSS260 VSS374 AE30
R16 VSS354 VSS361 T20
R17 T19 REV=1.4
VSS355 VSS360 EAGLELAKE
R19
R30
VSS356 VSS359 T17
T16
ASUS OEM-DT MB RESTRICTED SECRET
VSS357 REV=1.4 VSS358
EAGLELAKE GND GND Title :EAGLELAKE 7 - 7
PEGATRON CORP. Engineer: Wayne Hsieh
GND GND
Size Project Name Rev
A3 IPM41-D3 1.00G
Date: Thursday, July 09, 2009 Sheet 16 of 55
5 4 3 2 1
5 4 3 2 1

NOTE: +1P5V_DUAL DIMMA0B +1P5V_DUAL


Below 4 signals are different connection in Eaglelake platform 78 VDD10 VDD21 197
75 194
Channel A : CS1/WE/MA0 72
VDD9 VDD20
191
VDD8 VDD19
Channel B : ODT3 (G41 No ODT3) 69 VDD7 VDD18 189
M_CHA_DQ[0..63] [11] 66 VDD6 VDD17 186
M_CHA_MAA[1..14] [11] 65 VDD5 VDD16 183
62 VDD4 VDD15 182
M_CHA_MAA0 [12] 60 VDD3 VDD14 179
57 VDD2 VDD13 176
XMM1 COLOR: BLUE +0P75V_VTT_DDR 54 173
VDD1 VDD12
51 VDD0 VDD11 170
GND59 239
D 240 VTT2 GND58 235 D
DIMMA0A 120 VTT1 GND57 232
GND56 229

1
M_CHA_MAA0 188 234 M_CHA_DQ63 I I 113 226
M_CHA_MAA1 181 A0 DQ63 M_CHA_DQ62 D3CB17 D3CB18 GND27 GND55
A1 DQ62 233 110 GND26 GND54 223
M_CHA_MAA2 61 228 M_CHA_DQ61 4.7UF/6.3V 0.1UF/16V 107 220

2
M_CHA_MAA3 180 A2 DQ61 M_CHA_DQ60 X5R 10% X7R 10% GND25 GND53
A3 DQ60 227 104 GND24 GND52 217
M_CHA_MAA4 59 115 M_CHA_DQ59 mx_c0805 101 214
M_CHA_MAA5 58 A4 DQ59 M_CHA_DQ58 GND23 GND51
A5 DQ58 114 98 GND22 GND50 211
M_CHA_MAA6 178 109 M_CHA_DQ57 95 208
M_CHA_MAA7 56 A6 DQ57 M_CHA_DQ56 GND21 GND49
A7 DQ56 108 GND GND 92 GND20 GND48 205
M_CHA_MAA8 177 225 M_CHA_DQ55 89 202
M_CHA_MAA9 175 A8 DQ55 M_CHA_DQ54 GND19 GND47
A9 DQ54 224 86 GND18 GND46 199
M_CHA_MAA10 70 219 M_CHA_DQ53 83 166
M_CHA_MAA11 55 A10/AP DQ53 M_CHA_DQ52 GND17 GND45
A11 DQ52 218 80 GND16 GND44 163
M_CHA_MAA12 174 106 M_CHA_DQ51 47 160
M_CHA_MAA13 196 A12 DQ51 M_CHA_DQ50 GND15 GND43
A13 DQ50 105 44 GND14 GND42 157
M_CHA_MAA14 172 100 M_CHA_DQ49 41 154
NOTE: 171
A14 DQ49
99 M_CHA_DQ48 GND 38
GND13 GND41
151
A15 DQ48 M_CHA_DQ47 GND12 GND40
Check clock source if Eaglelake DQ47 216
M_CHA_DQ46
35 GND11 GND39 148
215 32 145
implemented DQ46
210 M_CHA_DQ45 29
GND10 GND38
142
DQ45 M_CHA_DQ44 GND9 GND37
[11] M_CHA_CLK0 63 CK1P/NU DQ44 209 26 GND8 GND36 139
64 97 M_CHA_DQ43 +1P5V_DUAL +1P5V_DUAL 23 136
[11] M_CHA_CLK0# CK1N/NU DQ43 GND7 GND35
184 96 M_CHA_DQ42 20 133
[11] M_CHA_CLK2 CK0P DQ42 GND6 GND34
185 91 M_CHA_DQ41 17 130
[11] M_CHA_CLK2# CK0N DQ41 GND5 GND33
90 M_CHA_DQ40 14 127
DQ40 GND4 GND32

1
06/03 Important! follow Intel MRC code, 207 M_CHA_DQ39 11 124
only DIMMA need. DQ39 M_CHA_DQ38 GND3 GND31
DQ38 206 I I 8 GND2 GND30 121
C 76 201 M_CHA_DQ37 D3R17 D3R15 5 119 C
[12] M_CHA_CS#1 CS1# DQ37 GND1 GND29
193 200 M_CHA_DQ36 1K 1K 2 116 +3P3V
[11] M_CHA_CS#0 CS0# DQ36 GND0 GND28
88 M_CHA_DQ35 1% 1% 241

2
DQ35 M_CHA_DQ34 DIMM_CA_VREF_A NP_NC1
[11] M_CHA_CKE1 169 CKE1 DQ34 87 67 VREFCA NP_NC2 242
50 82 M_CHA_DQ33 243 GND
[11] M_CHA_CKE0 CKE0 DQ33 M_CHA_DQ32 DIMM_VREF_A NP_NC3
DQ32 81 1 VREFDQ VDDSPD 236
52 156 M_CHA_DQ31
[11] M_CHA_BA2 BA2 DQ31 M_CHA_DQ30
[11] M_CHA_BA1 190 BA1 DQ30 155 DDR3_DIMM_240P

1
71 150 M_CHA_DQ29
[11] M_CHA_BA0 BA0 DQ29

1
149 M_CHA_DQ28 I I I I I
DQ28 M_CHA_DQ27 D3R18 D3R16 D3CB6 D3CB5
[5,9,18,21,24,25,28,29] SMB_DATA_R 238 SDA DQ27 37
118 36 M_CHA_DQ26 1K 1K 0.1UF/16V 0.1UF/16V

2
[5,9,18,21,24,25,28,29] SMB_CLK_R SCL DQ26 M_CHA_DQ25 1% 1% X7R 10% X7R 10%
31

2
DQ25 M_CHA_DQ24
165 CB7 DQ24 30
164 147 M_CHA_DQ23
CB6 DQ23 M_CHA_DQ22
159 CB5 DQ22 146
158 141 M_CHA_DQ21 GND GND GND GND
CB4 DQ21 M_CHA_DQ20
46 CB3 DQ20 140
45 28 M_CHA_DQ19
CB2 DQ19 M_CHA_DQ18
40 CB1 DQ18 27
39 22 M_CHA_DQ17
CB0 DQ17 M_CHA_DQ16
DQ16 21
138 M_CHA_DQ15
DQ15 M_CHA_DQ14
237 SA1 DQ14 137
117 132 M_CHA_DQ13
SA0 DQ13 M_CHA_DQ12
DQ12 131
19 M_CHA_DQ11
DQ11 M_CHA_DQ10
GND DQ10 18
13 M_CHA_DQ9
B DQ9 M_CHA_DQ8 B
[12] M_CHA_WE# 73 WE# DQ8 12
192 129 M_CHA_DQ7
[11] M_CHA_RAS# RAS# DQ7
74 128 M_CHA_DQ6
[11] M_CHA_CAS# CAS# DQ6
123 M_CHA_DQ5
DQ5 M_CHA_DQ4
[11] M_CHA_ODT1 77 ODT1 DQ4 122
195 10 M_CHA_DQ3
[11] M_CHA_ODT0 ODT0 DQ3
9 M_CHA_DQ2
DQ2 M_CHA_DQ1
DQ1 4
168 3 M_CHA_DQ0
[12,18] DDR3_DRAMRST# RESET# DQ0

161 DM8/DQS17P DQS7P 112 M_CHA_DQS7 [11]


162 NC/DQS17N DQS7N 111 M_CHA_DQS7# [11]
[11] M_CHA_DM7 230 DM7/DQS16P DQS6P 103 M_CHA_DQS6 [11]
231 NC/DQS16N DQS6N 102 M_CHA_DQS6# [11]
[11] M_CHA_DM6 221 DM6/DQS15P DQS5P 94 M_CHA_DQS5 [11]
222 NC/DQS15N DQS5N 93 M_CHA_DQS5# [11]
[11] M_CHA_DM5 212 DM5/DQS14P DQS4P 85 M_CHA_DQS4 [11]
213 NC/DQS14N DQS4N 84 M_CHA_DQS4# [11]
[11] M_CHA_DM4 203 DM4/DQS13P DQS3P 34 M_CHA_DQS3 [11]
204 NC/DQS13N DQS3N 33 M_CHA_DQS3# [11]
[11] M_CHA_DM3 152 DM3/DQS12P DQS2P 25 M_CHA_DQS2 [11]
153 NC/DQS12N DQS2N 24 M_CHA_DQS2# [11]
[11] M_CHA_DM2 143 DM2/DQS11P DQS1P 16 M_CHA_DQS1 [11]
144 NC/DQS11N DQS1N 15 M_CHA_DQS1# [11]
[11] M_CHA_DM1 134 DM1/DQS10P DQS0P 7 M_CHA_DQS0 [11]
135 NC/DQS10N DQS0N 6 M_CHA_DQS0# [11]
[11] M_CHA_DM0 125 DM0/DQS9P
A 126 NC/DQS9N A
43 NC/DQS8P
42 NC/DQS8N RESERVED 79

198 FREE1
187 FREE2 NC/PAR_IN 68
49
48
FREE3 NC/ERR_OUT 53
167
Title : DDR3 CHANNEL A
FREE4 NC/TEST4
PEGATRON CORP. Engineer: York Chang
DDR3_DIMM_240P Size Project Name Rev
GND
I A3 IPM41-D3 1.00
Date: Thursday, July 09, 2009 Sheet 17 of 55

5 4 3 2 1
5 4 3 2 1

+1P5V_DUAL DIMMB0B +1P5V_DUAL


78 VDD10 VDD21 197
75 VDD9 VDD20 194
M_CHB_DQ[0..63] [12] 72 VDD8 VDD19 191
M_CHB_MAA[0..14] [12] 69 VDD7 VDD18 189
66 VDD6 VDD17 186
65 VDD5 VDD16 183
62 VDD4 VDD15 182
60 VDD3 VDD14 179
57 VDD2 VDD13 176
XMM3 COLOR: BLUE +0P75V_VTT_DDR 54 173
VDD1 VDD12
51 VDD0 VDD11 170
GND59 239
D 240 VTT2 GND58 235 D
DIMMB0A 120 VTT1 GND57 232
GND56 229

1
M_CHB_MAA0 188 234 M_CHB_DQ63 I I 113 226
M_CHB_MAA1 181 A0 DQ63 M_CHB_DQ62 D3CB25 D3CB26 GND27 GND55
A1 DQ62 233 110 GND26 GND54 223
M_CHB_MAA2 61 228 M_CHB_DQ61 4.7UF/6.3V 0.1UF/16V 107 220

2
M_CHB_MAA3 180 A2 DQ61 M_CHB_DQ60 X5R 10% X7R 10% GND25 GND53
A3 DQ60 227 104 GND24 GND52 217
M_CHB_MAA4 59 115 M_CHB_DQ59 mx_c0805 101 214
M_CHB_MAA5 58 A4 DQ59 M_CHB_DQ58 GND23 GND51
A5 DQ58 114 98 GND22 GND50 211
M_CHB_MAA6 178 109 M_CHB_DQ57 95 208
M_CHB_MAA7 56 A6 DQ57 M_CHB_DQ56 GND21 GND49
A7 DQ56 108 GND GND 92 GND20 GND48 205
M_CHB_MAA8 177 225 M_CHB_DQ55 89 202
M_CHB_MAA9 175 A8 DQ55 M_CHB_DQ54 GND19 GND47
A9 DQ54 224 86 GND18 GND46 199
M_CHB_MAA10 70 219 M_CHB_DQ53 83 166
M_CHB_MAA11 55 A10/AP DQ53 M_CHB_DQ52 GND17 GND45
A11 DQ52 218 80 GND16 GND44 163
M_CHB_MAA12 174 106 M_CHB_DQ51 47 160
M_CHB_MAA13 196 A12 DQ51 M_CHB_DQ50 GND15 GND43
A13 DQ50 105 44 GND14 GND42 157
M_CHB_MAA14 172 100 M_CHB_DQ49 41 154
NOTE: 171
A14 DQ49
99 M_CHB_DQ48 GND 38
GND13 GND41
151
A15 DQ48 M_CHB_DQ47 GND12 GND40
Check clock source if Eaglelake DQ47 216
M_CHB_DQ46
35 GND11 GND39 148
215 32 145
implemented DQ46
210 M_CHB_DQ45 +1P5V_DUAL 29
GND10 GND38
142
DQ45 M_CHB_DQ44 GND9 GND37
[12] M_CHB_CLK2 63 CK1P/NU DQ44 209 26 GND8 GND36 139
64 97 M_CHB_DQ43 +1P5V_DUAL 23 136
[12] M_CHB_CLK2# CK1N/NU DQ43 GND7 GND35
184 96 M_CHB_DQ42 20 133
[12] M_CHB_CLK0 CK0P DQ42 GND6 GND34
185 91 M_CHB_DQ41 17 130
[12] M_CHB_CLK0# CK0N DQ41 GND5 GND33
90 M_CHB_DQ40 14 127
DQ40 GND4 GND32

1
207 M_CHB_DQ39 11 124
DQ39 M_CHB_DQ38 GND3 GND31
DQ38 206 I I 8 GND2 GND30 121
C 76 201 M_CHB_DQ37 D3R28 D3R25 5 119 C
[12] M_CHB_CS#1 CS1# DQ37 GND1 GND29
193 200 M_CHB_DQ36 1K 1K 2 116 +3P3V
[12] M_CHB_CS#0 CS0# DQ36 GND0 GND28
88 M_CHB_DQ35 1% 1% 241

2
DQ35 M_CHB_DQ34 DIMM_CA_VREF_B NP_NC1
[12] M_CHB_CKE1 169 CKE1 DQ34 87 67 VREFCA NP_NC2 242
50 82 M_CHB_DQ33 243 GND
[12] M_CHB_CKE0 CKE0 DQ33 M_CHB_DQ32 DIMM_VREF_B NP_NC3
DQ32 81 1 VREFDQ VDDSPD 236
52 156 M_CHB_DQ31
[12] M_CHB_BA2 BA2 DQ31 M_CHB_DQ30
[12] M_CHB_BA1 190 BA1 DQ30 155 DDR3_DIMM_240P

1
71 150 M_CHB_DQ29
[12] M_CHB_BA0 BA0 DQ29

1
149 M_CHB_DQ28 I I
DQ28

1
238 37 M_CHB_DQ27 D3R26 I I I
[5,9,17,21,24,25,28,29] SMB_DATA_R SDA DQ27 M_CHB_DQ26 1K D3R27 D3CB12 D3CB11
[5,9,17,21,24,25,28,29] SMB_CLK_R 118 SCL DQ26 36
31 M_CHB_DQ25 1% 1K 0.1UF/16V 0.1UF/16V

2
DQ25 M_CHB_DQ24 1% X7R 10% X7R 10%
165 30

2
CB7 DQ24 M_CHB_DQ23
164 CB6 DQ23 147
159 146 M_CHB_DQ22
CB5 DQ22 M_CHB_DQ21
158 CB4 DQ21 141 GND GND GND
46 140 M_CHB_DQ20 GND
CB3 DQ20 M_CHB_DQ19
45 CB2 DQ19 28
40 27 M_CHB_DQ18
CB1 DQ18 M_CHB_DQ17
39 CB0 DQ17 22
+3P3V 21 M_CHB_DQ16
DQ16 M_CHB_DQ15
DQ15 138
237 137 M_CHB_DQ14
SA1 DQ14 M_CHB_DQ13
117 SA0 DQ13 132
131 M_CHB_DQ12
DQ12 M_CHB_DQ11
DQ11 19
18 M_CHB_DQ10
DQ10 M_CHB_DQ9
GND DQ9 13
B M_CHB_DQ8 B
[12] M_CHB_WE# 73 WE# DQ8 12
192 129 M_CHB_DQ7
[12] M_CHB_RAS# RAS# DQ7
74 128 M_CHB_DQ6
[12] M_CHB_CAS# CAS# DQ6
123 M_CHB_DQ5
DQ5 M_CHB_DQ4
[12] M_CHB_ODT1 77 ODT1 DQ4 122
195 10 M_CHB_DQ3
[12] M_CHB_ODT0 ODT0 DQ3
9 M_CHB_DQ2
DQ2 M_CHB_DQ1
DQ1 4
168 3 M_CHB_DQ0
[12,17] DDR3_DRAMRST# RESET# DQ0
1

I
D3C02
0.1UF/16V 161 112 M_CHB_DQS7 [12]
2

X7R 10% DM8/DQS17P DQS7P


162 NC/DQS17N DQS7N 111 M_CHB_DQS7# [12]
[12] M_CHB_DM7 GND 230 DM7/DQS16P DQS6P 103 M_CHB_DQS6 [12]
231 NC/DQS16N DQS6N 102 M_CHB_DQS6# [12]
[12] M_CHB_DM6 221 DM6/DQS15P DQS5P 94 M_CHB_DQS5 [12]
222 NC/DQS15N DQS5N 93 M_CHB_DQS5# [12]
[12] M_CHB_DM5 212 DM5/DQS14P DQS4P 85 M_CHB_DQS4 [12]
213 NC/DQS14N DQS4N 84 M_CHB_DQS4# [12]
[12] M_CHB_DM4 203 DM4/DQS13P DQS3P 34 M_CHB_DQS3 [12]
204 NC/DQS13N DQS3N 33 M_CHB_DQS3# [12]
[12] M_CHB_DM3 152 DM3/DQS12P DQS2P 25 M_CHB_DQS2 [12]
153 NC/DQS12N DQS2N 24 M_CHB_DQS2# [12]
[12] M_CHB_DM2 143 DM2/DQS11P DQS1P 16 M_CHB_DQS1 [12]
144 NC/DQS11N DQS1N 15 M_CHB_DQS1# [12]
[12] M_CHB_DM1 134 DM1/DQS10P DQS0P 7 M_CHB_DQS0 [12]
135 NC/DQS10N DQS0N 6 M_CHB_DQS0# [12]
[12] M_CHB_DM0 125 DM0/DQS9P
A 126 NC/DQS9N A
43 NC/DQS8P
42 NC/DQS8N RESERVED 79

198
PEGATRON DT-MB RESTRICTED SECRET
FREE1
187 FREE2 NC/PAR_IN 68
49
48
FREE3 NC/ERR_OUT 53
167
Title : DDR3 CHANNEL B
FREE4 NC/TEST4
PEGATRON CORP. Engineer: York Chang
DDR3_DIMM_240P Size Project Name Rev
GND
I A3 IPM41-D3 1.00
Date: Thursday, July 09, 2009 Sheet 18 of 55

5 4 3 2 1
5 4 3 2 1

+1P5V_DUAL +1P5V_DUAL

2
D D3R01 D3R02 D
10K 10K
I I

1
1 B
[21,38] SLP_S5# DDR3_DRAM_PWROK [12]

2
I

C
2
E

3
PMBS3904 D3R03
D3Q1 100KOHM

1
5% I
D3C01

1
NI 0.1UF/16V

2
GND GND

C C

+1P5V_DUAL

+0P75V_VTT_DDR
1

1
I I I I I I I I
D3CB33 D3CB34 D3CB35 D3CB36 D3CB37 D3CB38 D3CB39 D3CB40
1UF/10V 1UF/10V 1UF/10V 1UF/10V 1UF/10V 1UF/10V 1UF/10V 1UF/10V
2

mx_c0603 mx_c0603 mx_c0603 mx_c0603 mx_c0603 mx_c0603 mx_c0603 2 mx_c0603

1
I I
DCB5 DCB6
0.1UF/16V 0.1UF/16V

2
GND GND GND GND GND GND GND GND

GND GND

B B
1

I I I I

1
D3CB41 D3CB42 D3CB43 D3CB44 I I
4.7UF/6.3V 4.7UF/6.3V 4.7UF/6.3V 4.7UF/6.3V DCB20 DCB21
2

X5R 10% X5R 10% X5R 10% X5R 10% 1UF/10V 1UF/10V

2
mx_c0805 mx_c0805 mx_c0805 mx_c0805 mx_c0603 mx_c0603

GND GND GND GND


GND GND

1
I I 09511 modify by TSL
1

+ + DCB25 DCB26
I I 10UF/6.3V 10UF/6.3V

2
D3CE1 D3CE2 X5R 10% X5R 10%
470uF/6.3V 470uF/6.3V mx_c0805 mx_c0805
2

GND GND

GND GND
09511 modify by TSL

A A

PEGATRON DT-MB RESTRICTED SECRET

Title : DECOUPLING
PEGATRON CORP. Engineer: York Chang
Size Project Name Rev
A3 IPM41-D3 1.00
Date: Thursday, July 09, 2009 Sheet 19 of 55

5 4 3 2 1
5 4 3 2 1
SU1B
ICH7 will not driver PME# high,but it will be pull up to +3VSB by an DMI_TXN0 V26 F1 USBN2 [30]
internal pull-up resistor SC7 0.1UF/16V [10] DMI_TXN0 DMI_TXP0 V25
DMI0RXN USBP0N
F2
[10] DMI_TXP0 DMI0RXP USBP0P USBP2 [30]
[10] DMI_RXN0 2 1SC8 0.1UF/16V U28 DMI0TXN USBP1N G4 USBN3 [30]
[10] DMI_RXP0 2 1 U27 DMI0TXP USBP1P G3 USBP3 [30]
DMI_TXN1 Y26 H1
SU1A A_D[31..0] [28,29] USBN0 [33]
SC9 I 0.1UF/16V [10] DMI_TXN1 DMI_TXP1 Y25
DMI1RXN USBP2N
H2
[10] DMI_TXP1 DMI1RXP USBP2P USBP0 [33]
E10 E18 A_D0 1SC10I 0.1UF/16V
[28,29] PPAR PAR AD0 A_D1 [10] DMI_RXN1 2 W28 DMI1TXN USBP3N J4 USBN1 [33]
[28,29] PDEVSEL# A12 DEVSEL# AD1 C18 [10] DMI_RXP1 2 1 W27 DMI1TXP USBP3P J3 USBP1 [33]
A9 A16 A_D2 DMI_TXN2 AB26 K1
[5] CK_33M_ICH PCICLK AD2 [10] DMI_TXN2 DMI2RXN USBP4N USBN4 [31]
B18 F18 A_D3 I SC11I 0.1UF/16V [10] DMI_TXP2 DMI_TXP2 AB25 K2

DMI
USBP4 [31]
SC74 [28,29] ICH_PCIRST# PCIRST# AD3 DMI2RXP USBP4P
2

A7 E16 A_D4 2 1SC12I 0.1UF/16V AA28 L4


[28,29] PIRDY# IRDY# AD4 [10] DMI_RXN2 DMI2TXN USBP5N USBN5 [31]
D NI 5PF/50V
/X
[28,29] PPME# B19
B10
PME# AD5 A18
E17
A_D5
A_D6 [10] DMI_RXP2
I
2 1
DMI_TXN3
AA27
AD25
DMI2TXP USBP5P L5
M1
USBP5 [31] D
[28,29] PSERR# USBN6 [31]
1

SERR# AD6 A_D7 [10] DMI_TXN3 DMI3RXN USBP6N


[28,29] PSTOP# F15 STOP# AD7 A17 I SC13 0.1UF/16V [10] DMI_TXP3 DMI_TXP3 AD24 DMI3RXP USBP6P M2 USBP6 [31]
E11 A15 A_D8 2 SC14 0.1UF/16V
1 AC28 N4
[28,29] PPLOCK# PLOCK# AD8 [10] DMI_RXN3 DMI3TXN USBP7N USBN7 [31]
GND F14 C14 A_D9 2 1 AC27 N3
[28,29] PTRDY# TRDY# AD9 [10] DMI_RXP3 DMI3TXP USBP7P USBP7 [31]
C9 E14 A_D10 I
[28,29] PPERR# PERR# AD10
F16 D14 A_D11 I +3P3VSB

USB
[28,29] PFRAME# FRAME# AD11 6/30 modify del 2cap
PCI B12 A_D12 D3 USB_OC0# SR132
AD12 A_D13 OC0# USB_OC0#
AD13 C13 [25] N_X1_RX#0 F26 PERN_0 OC1# C4 1 2
E7 G15 A_D14 F25 D5 USB_OC0#
[28] GNT0# GNT0# AD14 [25] N_X1_RX0 PERP_0 OC2#
D16 G13 A_D15 E28 D4 USB_OC0# 8.2KOHM1%
+3P3VSB [29] GNT1# GNT1# AD15 [25] N_X1_TX#0 PETN_0 OC3#
SR85 D17 E12 A_D16 E27 E5 USB_OC0#
GNT2# AD16 [25] N_X1_TX0 PETP_0 OC4#
8.2KOhm PGNT#3 F13 C11 A_D17 H26 C3 USB_OC0#
1 /X 2 PPME# PGNT#4 A14
GNT3# AD17
D11 A_D18 I SC5 0.1UF/16V[32] LAN_RXN
H25
PERN_1 OC5#/GPIO29
A2 USB_OC0#
PGNT#5 GNT4#/GPIO48 AD18 A_D19 [32] LAN_RXP PERP_1 OC6#/GPIO30 USB_OC0#
D8 GNT5#/GPIO17 AD19 A11 [32] LAN_TXN 2 1 G28 PETN_1 OC7#/GPIO31 B3
NI A10 A_D20 2 1 G27
AD20 [32] LAN_TXP PETP_1
F11 A_D21 SC6 0.1UF/16V K26 I of ICH7,avoid routing next to clock
Place it within 500mils
AD21 A_D22 PERN_2 SR88
[28] PREQ#0 D7 F10 I K25
REQ0# AD22 A_D23 PERP_2 pins
[28,29] PREQ#1 C16 REQ1# AD23 E9 J28 PETN_2 USBRBIAS D1 1 2
C17 D9 A_D24 J27 D2
[28] PREQ#2 REQ2# AD24 PETP_2 USBRBIAS#
E13 B9 A_D25 M26 20 OHM 1%
[28] PREQ#3 REQ3# AD25 PERN_3
PREQ#4 A13 A8 A_D26 M25 GND

PCI-E
PREQ#5 REQ4#/GPIO22 AD26 A_D27 PERP_3
C8 GPIO1/REQ5# AD27 A6 L28 PETN_3
C7 A_D28 L27
AD28 A_D29 PETP_3
[28] PINTA# A3 PIRQA# AD29 B6 P26 PERN_4 CLK48 B2 CK_48M_USB [5]
B4 E6 A_D30 ICH7_PCIE_CORE P25
[28] PINTB# PIRQB# AD30 PERP_4
C5 D6 A_D31 N28
[28] PINTC# PIRQC# AD31 PETN_4
[28] PINTD# B5 PIRQD# N27 PETP_4

2
[28,29] PINTE# G8 GPIO2/PIRQE# Close to ICH7 T25 PERN_5
C [28,29]
[28,29]
PINTF#
PINTG#
F7
F8
GPIO3/PIRQF#
B15 C/BE0#
C/BE0# [28,29] <500mil
SR89
24.9Ohm
T24
R28
PERP_5 C
GPIO4/PIRQG# C/BE0# C/BE1# 1% PETN_5 SC21
[28,29] PINTH# G7 GPIO5/PIRQH# C/BE1# C12 C/BE1# [28,29] R27 PETP_5
D12 C/BE2# 2 1
C/BE2# [28,29]

1
C/BE2# C/BE3# DMI_ZCOMP
C/BE3# C15 C/BE3# [28,29] C25 DMI_ZCOMP
DMI_IRCOMP D25 5PF/50V /X
+3P3V DMI_IRCOMP
I
[5] CK_100M_ICH# AE28 DMI_CLKN NI
ICH7 [5] CK_100M_ICH AE27 DMI_CLKP
R_Measure GND
I 1 2 RN8A PGNT#4 I
1KOHM
I 5 65%
RN8C PGNT#3
1KOHM

2
I 3 45%
RN8B PREQ#4 SC71 SC72
1KOHM
I 7 85%
RN8D PREQ#5 5PF/50V 5PF/50V ICH7
1KOHM
5% NI /X NI /X I

1
ICH_PCIRST#

SU1C GND GND

1
AB15 AF3 SC18
DD0 SATA0RXN SATA_RXN0 [27]
AE14 AE3 NI 1000PF/50V R_Measure
SATA_RXP0 [27]

2
DD1 SATA0RXP /X
AG13 DD2 SATA0TXN AG2 SATA_TXN0 [27] SC18 is used
AF13 AH2 for tuning CK_100M_SATA#
DD3 SATA0TXP SATA_TXP0 [27]
AD14 AE5 signal CK_100M_SATA Boot BIOS Destination Selection
DD4 SATA1RXN SATA_RXN1 [27]
AC13 DD5 SATA1RXP AD5 SATA_RXP1 [27] GND integrity.
AD12 DD6 SATA1TXN AG4 SATA_TXN1 [27] Sampled at Rising edge of PWROK
AC12 DD7 SATA1TXP AH4 SATA_TXP1 [27] (GNT5# is MSB)
AE12 AF7 SATA_RXN2 [27]
AF12
DD8 SATA2RXN
AE7
0 : SPI
DD9 SATA2RXP SATA_RXP2 [27]

2
AB13 AG6 SC20 SC19 1 : LPC (Weak internal pull-up)
B +3P3V AC14
DD10
DD11
SATA2TXN
SATA2TXP AH6
SATA_TXN2
SATA_TXP2
[27]
[27]
5PF/50V 5PF/50V B
AF14 AD9 /X /X
SATA_RXN3 [27]

1
DD12 SATA3RXN
IDE

AH13 AE9
SATA

DD13 SATA3RXP SATA_RXP3 [27]


1

AH14 DD14 SATA3TXN AG8 SATA_TXN3 [27]


R1036 AC15 AH8 NI NI
DD15 SATA3TXP SATA_TXP3 [27]
4.7K SATA_CLKN AF1 CK_100M_SATA# [5]
AF16 DDACK# SATA_CLKP AE1 CK_100M_SATA [5] GND GND LF FootPrint
I AE15
2

DDREQ SATA_BIASSR102
AF15 DIOR# SATARBIASN AH10 1 2 24.9Ohm 1%
AH15 AG10 +3P3V
DIOW# SATARBIASP
AG16 IORDY SATALED# AF18 ICH_SATALED# I [27]
GND
+3P3V AH17 AF19 I 3 SRN3B
DA0 GPIO21/SATA0GP 8.2KOHM4
AE17 AH18 I 7 SRN3D
DA1 GPIO19/SATA1GP 8.2KOHM8
AF17 AH19 I 5 SRN3C PGNT#5
DA2 GPIO36/SATA2GP 8.2KOHM6
1

AE19 I 1 SRN3A
GPIO37/SATA3GP 8.2KOHM2
R1037
4.7K AE16 DCS1# A20GATE AE22 A20GATE [39]

2
AD16 DCS3# A20M# AH28 A20M# [7]
I AG27 SR87
PM_SLP# [7,13]
2

CPUSLP# +3P3V 1KOhm


AH16 IDEIRQ IGNNE# AG22 IGNNE# [7]
INIT3_3V# AG21 I
AF22 +1P1V_FSB_VTT SR129
HINIT# [6]

1
INIT# A20GATE
INTR AF25 INTR [7] 1 2
AG26 I SR300 62 Ohm 5%
FERR# HFERR# [7]
AH24 HFERR# 1 2 8.2KOhm
HOST

NMI NMI [7]


AG23 /X GND
RCIN# RST_KB [39]
SERIRQ AH21 SERIRQ [37,39]
AF23
A SMI#
STPCLK# AH22
SMI#
STPCLK#
[7]
[7]
I SR301 62 Ohm 5% NI A
AF26 H_THMTRIP# 1 2
THERMTRIP# H_THMTRIP# [7] <Variant Name>
1

SC24
150PF/50V
Close to ICH7 modify 6/20
Title : ICH7-1
NI /X L<3''
ICH7 Engineer:
2

PEGATRON CORP.
Wayne Hsieh
I Size Project Name Rev
GND A3 IPM41-D3 1.00G
Date: Thursday, July 09, 2009 Sheet 20 of 55
1.00
5 4 3 2 Intel recommend Dual power for different SMBus Devices
1
SU1D Add MFG header 7/30 But only implement Main power here

[37,39] LAD0
AA5
AA6
LDRQ1#/GPIO23
LAD0
GPIO0/BM_BUSY#
GPIO6
AB18
AC21 MFG_NET
SMBus Switch SMBus connect to two kind of devices, one use Main power,
another use Standby power, so use this switch circuit to isolate

LPC
[37,39] LAD1 AB5 LAD1 GPIO7 AC18 F_AUDIO_DET# [36]
[37,39] LAD2 AC4 LAD2 GPIO8 E21 those two device.
SB_GPIO9 9/1 modify
[37,39] LAD3 Y6 LAD3 GPIO9 E20 SMB_CLK and SMB_DATA for Standby device.
AC3 A20 SB_GPIO10
[39] LDRQ# LDRQ0# GPIO10 SMB_CLK_MAIN and SMB_DATA_MAIN for Main power device.
AB3 F19 SB_GPIO12
[37,39] LFRAME# LFRAME# GPIO12 IO_PME#
GPIO13 E19 LPC_PME# [38]
ACZ_BITCLK_R U1 R4 +3P3VSB
ACZ_RST#_R ACZ_BIT_CLK GPIO14
R5 ACZ_RST# GPIO15 E22

AUDIO
T2 AC22 SMB_CLK_R I 5 SRN2C
[34] AZ_SDATA_IN0 ACZ_SDIN0 GPIO16/DPRSLPVR 2.7KOHM6
D T3
T1
ACZ_SDIN1 GPIO18/STPPCI# AC20
AF21
SMB_DATA_R I 7 2.7KOHM8
SRN2D D
ACZ_SDOUT_R ACZ_SDIN2 GPIO20/STPCPU# +3P3VSB SMB_CLK_R
T4 ACZ_SDOUT GPIO24 R3 PLED_N [44] SMB_CLK_R [5,9,17,18,24,25,28,29]
ACZ_SYNC_R R6 D20
ACZ_SYNC GPIO25
[5] CK_14M_ICH AC1 CLK14 GPIO26 A21

2
B21 I SMB_DATA_R
GPIO27 SMB_DATA_R [5,9,17,18,24,25,28,29]

EPROM
NI SC73 W1 E23 SR109 IO_PME# I 1 SRN2A
EE_CS GPIO28 2.7KOHM2
5PF/50V W3 AG18 CLKRUN# WAKE# I 3 SRN2B
EE_DIN GPIO32/CLKRUN# CLKRUN# [37] 5.1KOHM 2.7KOHM4
add SR1818 & SR7878 modify 7/31 /X Y2 AC19 1%

1
EE_DOUT GPIO33/AZ_DOCK_EN#
Y1 U2

1
EE_SHCLK GPIO34/AZ_DOCK_RST# SMB_CLK_R
GND GPIO35 AD21
V3 AD20 SBGPI38 SMB_DATA_R
LAN_CLK GPIO38

1
NI U3 AE20 GND SC25 SC26
SR1818 1 0 LAN_RSTSYNC GPIO39 10PF/50V 10PF/50V
2 C19 LAN_RST# GPIO49/CPUPWRGD AG24 CPUPWRGD [7,9]
1

[38] RSMRST# I U5 NI /X /X NI

2
LAN_RXD0

LAN
SR7878 V4 AF20 ICH_THRM#
LAN_RXD1 THRM# LPC_SMI# [38]
8.2KOHM T5 AD22 VRMPWRGD_ICH

MISC
LAN_RXD2 VRMPWRGD VRMPWRGD_ICH [5,51]
U7 AH20 ICH_SYNC#
LAN_TXD0 MCH_SYNC# ICH_SYNC# [13]
V6 C23 IO_PWRBTN# GND
SB_PWRBTN# [38]
2

LAN_TXD1 PWRBTN# RING#


V7 LAN_TXD2 RI# A28 RING# [41]
A27 LPCPD#
SUS_STAT# LPCPD# [37]
GND ICH_RTCX1 AB1 C20
RTXC1 SUSCLK

RTC
ICH_RTCX2 AB2 A22 SYS_RESET#
RTCX2 SYS_RST# SYS_RESET# [7,9,38,44]
RTCRST# AA3 C26
[55] RTCRST# RTCRST# PLTRST# LRESET# [13,37,39]
F20 WAKE#
WAKE# WAKE# [24,25,32]
SMBALERT# B23 Y5 ICH_INTRUDER#
SMB_CLK_R SMBALERT#/GPIO11 INTRUDER# PWROK +3P3VSB
[5,9,17,18,24,25,28,29] SMB_CLK_R C22 SMBCLK PWROK AA4 NI NI PWROK [13,38]

2
SMB_DATA_R B22 Y4 RSMRST# SC67 SC66 +3P3V
[5,9,17,18,24,25,28,29] SMB_DATA_R SMBDATA RSMRST# RSMRST# [38]

SMB
LINKALERT# A26 W4 ICH_INTVRMEN 0.1UF/16V 0.1UF/16V I SR5 1K 1% SMBALERT# I 1 SRN4A
LINKALERT# INTVRMEN 2.7KOHM2
C SMBLINK0 B25 A19 SPKR [55]
X7R 10% X7R 10% SBGPI38 1 2 LINKALERT# I 7 2.7KOHM8
SRN4D
C

1
I 5% 5 SRN15C SMBLINK1 SMLINK0 SPKR mx_c0603 mx_c0603 SMBLINK0 SRN4B
47 OHM 6 A25 SMLINK1 I 3 2.7KOHM4
B24 6/23 modify SMBLINK1 I 5 SRN4C
SLP_S3# SLP_S3# [38] 2.7KOHM6
I 5% 3 SRN15B ICH_SPI_MOSI SR6 +3P3V +3P3VSB
[54] SPI_MOSI 47 OHM 4 P5 SPI_MOSI SLP_S4# D23 SLP_S5# [19,38] 9/3 modify
[54] SPI_MISO P2 SPI_MISO SLP_S5# F22 1 2
SPI
I 5% 1 SRN15A ICH_SPI_CS#
[54] SPI_CS# 47 OHM 2 P6 SPI_CS# GND GND
I 5% 7 SRN15D ICH_SPI_CLK ICH_TP0 NI 0Ohm /X ICH_THRM# I SRN5B
[54] SPI_CLK 47 OHM 8 R2 SPI_CLK TP0/BATLOW# C21 3 8.2KOHM4
P1 SPI_ARB AF24 SBGPI38: IO_PWRBTN# I 7 SRN5D
TP1/DPRSTP# 8.2KOHM8
AH25 SYS_RESET# I 5 SRN5C
TP2/DPSLP# DPSLP# [7] Deafult High for new board, GND 8.2KOHM6
F21 ICH_TP0 I 1 SRN5A
SPI_+3VSB TP3 Low for forward compibility(P5LD2-TVM) 8.2KOHM2

ICH7 BATT_DUAL1.00
RN14A 1 5% I I
8.2KOHM2
RN14D 7 5% I ICH_INTVRMEN
8.2KOHM8 1 2
SR32 Intel
RN14B 3 5% I
8.2KOHM4
RN14C 5 5% I I SR116 390KOHM 5% recommend 330K
8.2KOHM6
+3P3VSB

SB_GPIO9 I 3 4 FRN1B
7/9 modify to 0603 1KOHM
SB_GPIO10 I 7 8 FRN1D
1KOHM
SB_GPIO12 I 5 6 FRN1C
1KOHM
+3P3V I 1 2 FRN1A
1KOHM 6/23 modify

1
RTC I 7 SRN9D ACZ_BITCLK_R
I [34] AZ_BITCLK 33OHM 8
SR78 Power-well
4.7K I I 1 SRN9A ACZ_RST#_R
Isolation [34] AZ_RST# 33OHM 2

2
SC70
B B
2
Control 22PF/50V I 5 SRN9C ACZ_SDOUT_R
RTC NPO 5% [34] AZ_SDATA_OUT 33OHM 6

1
I 3 SRN9B ACZ_SYNC_R
ICH_RTCX2 ICH_RTCX1 [34] AZ_SYNC 33OHM 4
BATT_DUAL MFG_NET
SX1 I
32.768Khz
1

I 11 22 SMD (07X901232760) GND


SR123 GND GND
10MOhm 3 4
3

4
2

5% I
INTRUDER mx_r0402 NOBOM
2

1 ICH_INTRUDER# SR71 IGND SP78


I 2 0 SR124 3 1
10MOhm 5% GPI1 NP_NC1
4 2
1 1

HEADER_1X2P GPI2 NP_NC2


1 2 6 GND NP_NC3 5
1

I I
GND SC27 SC28 PEGATRON_MFG
12PF/50V 12PF/50V
2

NPO 5% NPO 5% GND


10/2 modify 12X602012B00

GND GND

I Add MFG header 7/30


XSX1
A A
<Variant Name>

Crystal Holder
Title : ICH7-2
PEGATRON CORP. Engineer:
Wayne Hsieh
Size Project Name Rev
A3 IPM41-D3 1.00G
Date: Thursday, July 09, 2009 Sheet 21 of 55
5 4 3 2 1
+1P5V_ICH +1P5V_ICH +5V
SU1E I SR125
1KOhm 1%
A1 AD17 V5REF 2 1
VCC1_5_A_1 V5REF_1
AB10 VCC1_5_A_2 V5REF_2 G10
AB17 +5VSB r0603_h24
VCC1_5_A_3
AB7 VCC1_5_A_4 I SR126 10Ohm SD2
1

1
SC29 SC30 SC31 SC32 SC33 NI AB8 F6 V5REF_AUA 1 2 2 +3P3V
0.1UF/25V 0.1UF/25V 0.1UF/25V 0.1UF/25V 1UF/10V SC34 VCC1_5_A_5 V5REF_SUS r0603_h24
AB9 VCC1_5_A_6 3
c0603 c0603 c0603 c0603 c0603 1UF/10V AC10 W5 1
2

2
VCC1_5_A_7 VCCRTC

1
NI /X NI /X I I NI /X mx_c0603 AC17 SC35
VCC1_5_A_8

1
D 10/2 modify
AC6
AC7
VCC1_5_A_9 VCCUSBPLL C1 VCCUSBPLL 0.1UF/25V
c0603
SC36
0.1UF/25V BAT54CW
D

2
VCC1_5_A_10 VCCSATAPLL /X c0603 I
AC8 AD2 NI

2
VCC1_5_A_11 VCCSATAPLL
AD10 VCC1_5_A_12
AD6 AG28 VCCDMPLL I
VCC1_5_A_13 VCCDMIPLL
AE10 VCC1_5_A_14
GND AE6 VCC1_5_A_15 VCC1_05_1 L11 GND GND
AF10 VCC1_5_A_16 VCC1_05_2 L12
AF5 L14 +1P1V_CORE BATT_DUAL
VCC1_5_A_17 VCC1_05_3
AF6 VCC1_5_A_18 VCC1_05_4 L16
AF9 VCC1_5_A_19 VCC1_05_5 L17
AG5 VCC1_5_A_20 VCC1_05_6 L18
AG9 VCC1_5_A_21 VCC1_05_7 M11
AH5 VCC1_5_A_22 VCC1_05_8 M18

1
AH9 P11 SC37 SC38 SC39
VCC1_5_A_23 VCC1_05_9

1
F17 P18 0.1UF/16V 0.1UF/25V 0.1UF/25V SC40 SC41
VCC1_5_A_24 VCC1_05_10 c0603 c0603 c0603 0.1UF/16V 0.1UF/25V
G17 T11

2
VCC1_5_A_25 VCC1_05_11 /X /X /X c0603 c0603
H6 T18 NI NI NI I

2
VCC1_5_A_26 VCC1_05_12
H7 VCC1_5_A_27 VCC1_05_13 U11 NI /X
J6 VCC1_5_A_28 VCC1_05_14 U18
J7 VCC1_5_A_29 VCC1_05_15 V11
T7 VCC1_5_A_30 VCC1_05_16 V12
VCC1_05_17 V14 GND GND
D26 V16 +1P5V_ICH
VCC1_5_B_1 VCC1_05_18
D27 VCC1_5_B_2 VCC1_05_19 V17
D28 V18 +1P1V_FSB_VTT
VCC1_5_B_3 VCC1_05_20
E24 VCC1_5_B_4
+1P5V_ICH ICH7_PCIE_CORE E25 AE23
VCC1_5_B_5 V_CPU_IO_1

1
E26 AE26 SC42
VCC1_5_B_6 V_CPU_IO_2
C F23 VCC1_5_B_7 V_CPU_IO_3 AH26 0.1UF/25V
C

1
POWER
SL1 F24 SC43 SC44 I c0603

2
VCC1_5_B_8 0.1UF/25V 0.1UF/25V
1 2 G22 VCC1_5_B_9 VCC3_3_1 A5
G23 AA7 c0603 c0603

2
VCC1_5_B_10 VCC3_3_2 /X /X
70Ohm/100Mhz H22 VCC1_5_B_11 VCC3_3_3 AB12 NI NI
H23 VCC1_5_B_12 VCC3_3_4 AB20 GND
1

SC45 I J22 AC16 +3P3V +1P5V_ICH


+ VCC1_5_B_13 VCC3_3_5
1UF/10V SCE1 J23 AD13 NOBOM
c0603 100uF/16V VCC1_5_B_14 VCC3_3_6 NJP11
NI NI K22 AD18 GND
2

/X /X VCC1_5_B_15 VCC3_3_7
K23 AG12 2 SHORTPIN_RECT
1
2

VCC1_5_B_16 VCC3_3_8
L22 VCC1_5_B_17 VCC3_3_9 AG15

1
L23 AG19 SC46 SC47 SC48 SC49 SC50 SC51 SC52
VCC1_5_B_18 VCC3_3_10 0.1UF/25V 0.1UF/25V 0.1UF/25V 0.1UF/25V 10UF/6.3V 0.1UF/25V 0.1UF/25V
M22 VCC1_5_B_19 VCC3_3_11 AH11
GND GND M23 B13 c0603 c0603 c0603 c0603 c1206_h55 c0603 I c0603

2
VCC1_5_B_20 VCC3_3_12 /X /X /X /X /X
N22 VCC1_5_B_21 VCC3_3_13 B16 NI NI
N23 VCC1_5_B_22 VCC3_3_14 B27 NI NI I NI
P22 VCC1_5_B_23 VCC3_3_15 B7
P23 VCC1_5_B_24 VCC3_3_16 C10 GND GND GND
R22 VCC1_5_B_25 VCC3_3_17 D15
R23 VCC1_5_B_26 VCC3_3_18 F9
R24 G11 GND +1P5V_ICH
VCC1_5_B_27 VCC3_3_19
R25 VCC1_5_B_28 VCC3_3_20 G12 NOBOM

1
R26 G16 SC53 SC54 NJP12
VCC1_5_B_29 VCC3_3_21 0.1UF/25V 0.1UF/25V
T22 VCC1_5_B_30 Vcc3_3/VccHDA U6 2 SHORTPIN_RECT
1
T23 A24 c0603 c0603

2
VCC1_5_B_31 VCCSUS3_3_1

1
T26 C24 I NI /X SC55
VCC1_5_B_32 VCCSUS3_3_2 0.1UF/25V
T27 VCC1_5_B_33 VCCSUS3_3_3 D19 I
T28 D22

2
VCC1_5_B_34 VCCSUS3_3_4
U22 VCC1_5_B_35 VCCSUS3_3_5 E3
U23 G19
B V22
VCC1_5_B_36
VCC1_5_B_37
VCCSUS3_3_6
VCCSUS3_3_7 K3 GND B
1

SC56 SC57 SC58 V23 K4 GND


0.1UF/25V 0.1UF/25V 0.1UF/25V VCC1_5_B_38 VCCSUS3_3_8
W22 VCC1_5_B_39 VCCSUS3_3_9 K5
NI c0603 c0603 c0603 W23 K6
2

/X /X VCC1_5_B_40 VCCSUS3_3_10 +3P3VSB


I NI Y22 VCC1_5_B_41 VCCSUS3_3_11 L1
Y23 VCC1_5_B_42 VCCSUS3_3_12 L2
AA22 VCC1_5_B_43 VCCSUS3_3_13 L3
GND GND GND AA23 VCC1_5_B_44 VCCSUS3_3_14 L6

1
AB22 L7 SC59 SC60 SC61 SC62
VCC1_5_B_45 VCCSUS3_3_15 0.1UF/25V 0.1UF/25V 0.1UF/25V 0.1UF/16V
AB23 VCC1_5_B_46 VCCSUS3_3_16 M6
AC23 M7 c0603 c0603 c0603 c0603

2
VCC1_5_B_47 VCCSUS3_3_17 /X /X /X /X
AC24 VCC1_5_B_48 VCCSUS3_3_18 N7
AC25 VCC1_5_B_49 VCCSUS3_3_19 P7 NI NI NI NI
AC26 VCC1_5_B_50 VccSus3_3/VccSusHDA R7
1

SC63 SC64 AD26 V1


0.1UF/25V 0.1UF/25V VCC1_5_B_51 VccSus3_3/VccLAN3_3_0
AD27 VCC1_5_B_52 VccSus3_3/VccLAN3_3_1 V5
NI c0603 c0603 AD28 W2 GND
2

/X /X VCC1_5_B_53 VccSus3_3/VccLAN3_3_2
NI VccSus3_3/VccLAN3_3_3 W7

VccSus1_05/VccLAN1_05_1 AA2
GND GND VCCSUS1_05_2 C28
VCCSUS1_05_3 G20
K7 SB_K7
VCCSUS1_05_4
VccSus1_05/VccLAN1_05_0 Y7 1

HEATSINK2 SC65
1 0.1UF/25V
ICH7 I c0603
A A
2

2 GND <Variant Name>

HEATSINK
/X Title : ICH7-3
NI
PEGATRON CORP. Engineer:
Wayne Hsieh
Size Project Name Rev
A3 IPM41-D3 1.00G
Date: Thursday, July 09, 2009 Sheet 22 of 55
5 4 3 2 1

SU1F
E4 VSS1 VSS95 A4
AG11 VSS2 VSS96 A23
C27 VSS3 VSS97 B1
R14 VSS4 VSS98 B8
R15 VSS5 VSS99 B11
R16 VSS6 VSS100 B14
R17 VSS7 VSS101 B17
R18 VSS8 VSS102 B20
T6 VSS9 VSS103 B26
T12 VSS10 VSS104 B28
D T13 VSS11 VSS105 C2 D
T14 VSS12 VSS106 C6
T15 VSS13 VSS107 D10
T16 VSS14 VSS108 D13
T17 VSS15 VSS109 D18
U4 VSS16 VSS110 D21
U12 VSS17 VSS111 D24
U13 VSS18 VSS112 E1
U14 VSS19 VSS113 E2
U15 VSS20 VSS114 E8
U16 VSS21 VSS115 E15
U17 VSS22 VSS116 F3
U24 VSS23 VSS117 F4
U25 VSS24 VSS118 F5
U26 VSS25 VSS119 F12
V2 VSS26 VSS120 F27
V13 VSS27 VSS121 F28
V15 VSS28 VSS122 G1
V24 VSS29 VSS123 G2
V27 VSS30 VSS124 G5
V28 VSS31 VSS125 G6
W6 VSS32 VSS126 G9
W24 VSS33 VSS127 G14
W25 VSS34 VSS128 G18
W26 VSS35 VSS129 G21
Y3 VSS36 VSS130 G24
Y24 VSS37 VSS131 G25
Y27 VSS38 VSS132 G26
Y28 VSS39 VSS133 H3
C AA1 H4 C
VSS40 VSS134
AA24 VSS41 VSS135 H5
AA25 VSS42 VSS136 H24
AA26 VSS43 VSS137 H27
AB4 VSS44 VSS138 H28
AB6 VSS45 VSS139 J1
AB11 VSS46 VSS140 J2
AB14 VSS47 VSS141 J5
AB16 VSS48 VSS142 J24
AB19 VSS49 VSS143 J25
AB21 VSS50 VSS144 J26
AB24 VSS51 VSS145 K24
AB27 VSS52 VSS146 K27
AB28 VSS53 VSS147 K28
AC2 VSS54 VSS148 L13
AC5 VSS55 VSS149 L15
AC9 VSS56 VSS150 L24
AC11 VSS57 VSS151 L25
AD1 VSS58 VSS152 L26
AD3 VSS59 VSS153 M3
AD4 VSS60 VSS154 M4
AD7 VSS61 VSS155 M5
AD8 VSS62 VSS156 M12
AD11 VSS63 VSS157 M13
AD15 VSS64 VSS158 M14
AD19 VSS65 VSS159 M15
AD23 VSS66 VSS160 M16
AE2 VSS67 VSS161 M17
AE4 VSS68 VSS162 M24
B B
AE8 VSS69 VSS163 M27
AE11 VSS70 VSS164 M28
AE13 VSS71 VSS165 N1
AE18 VSS72 VSS166 N2
AE21 VSS73 VSS167 N5
AE24 VSS74 VSS168 N6
AE25 VSS75 VSS169 N11
AF2 VSS76 VSS170 N12
AF4 VSS77 VSS171 N13
AF8 VSS78 VSS172 N14
AF11 VSS79 VSS173 N15
AF27 VSS80 VSS174 N16
AF28 VSS81 VSS175 N17
AG1 VSS82 VSS176 N18
AG3 VSS83 VSS177 N24
AG7 VSS84 VSS178 N25
AG14 VSS85 VSS179 N26
AG17 VSS86 VSS180 P3
AG20 VSS87 VSS181 P4
AG25 VSS88 VSS182 P12
AH1 VSS89 VSS183 P13
AH3 VSS90 VSS184 P14
VSS185 P15
AH7 VSS91 VSS186 P16
AH23 VSS92 VSS187 P17
AH27 VSS93 VSS188 P24
VSS189 P27
VSS190 P28
A VSS191 R1 A
VSS192 R11
VSS193 R12
AH12 VSS94 VSS194 R13
<Variant Name>

GND
ICH7
GND Title : ICH7-4
PEGATRON CORP. Engineer:
I Wayne Hsieh
Size Project Name Rev
A3 IPM41-D3 1.00G
Date: Thursday, July 09, 2009 Sheet 23 of 55
5 4 3 2 1
5 4 3 2 1

PCI EXPRESS X16 Graphics Card Slot


I +12V
+3P3V +12V
+3P3VSB J41

1
2
SLOT 164P,PCI-E X16

NP_NC1
NP_NC2
B1 +12V_1 PRSNT1# A1
B2 +12V_2 +12V_3 A2
D B3 RSVD1 +12V_4 A3 D
B4 GND1 GND35 A4
1

+ [5,9,17,18,21,25,28,29] SMB_CLK_R B5 SMCLK JTAG2 A5


1

1
I I I B6 A6
XCE1 XCB1 XCB2 [5,9,17,18,21,25,28,29] SMB_DATA_R SMDAT JTAG3 +3P3V
[13] PCIE_B7 B7 GND2 JTAG4 A7
470uF/16V 0.1UF/16V 0.1UF/16V B8 A8
2

2
+3.3V_1 JTAG5
B9 JTAG1 +3.3V_2 A9
B10 3.3Vaux +3.3V_3 A10
[21,25,32] WAKE# B11 WAKE# PWRGD A11 PCIES_RST# [25,32,38]

GND GND GND

1
I NI
B12 A12 XCB3 XC1
RSVD2 GND36
I XC2 1 2 0.1UF/16V X7R 10% B13 A13 CK_100M_PCIEX16 [5]
0.1UF/16V 1000PF/50V

2
[10] EXP_TXP0 EXP_TXP0_C GND3 REFCLK+
[10] EXP_TXN0 B14 HSOP0 REFCLK- A14 CK_100M_PCIEX16# [5] X7R 10%
I XC3 1 2 0.1UF/16V X7R 10% EXP_TXN0_C B15 A15
HSON0 GND37
B16 GND4 HSIP0 A16 EXP_RXP0 [10]
[10] SDVO_CTRL_CLK B17 PRSNT2_1# HSIN0 A17 EXP_RXN0 [10]
B18 GND5 GND38 A18
GND GND
I XC4 1 2 0.1UF/16V X7R 10%
[10] EXP_TXP1 EXP_TXP1_C
[10] EXP_TXN1 B19 HSOP1 RSVD6 A19
I XC5 1 2 0.1UF/16V X7R 10% EXP_TXN1_C B20 A20
HSON1 GND39
B21 GND6 HSIP1 A21 EXP_RXP1 [10]
I XC6 1 2 0.1UF/16V X7R 10% B22 A22 EXP_RXN1 [10]
[10] EXP_TXP2 EXP_TXP2_C GND7 HSIN1
[10] EXP_TXN2 B23 HSOP2 GND40 A23
I XC7 1 2 0.1UF/16V X7R 10% EXP_TXN2_C B24 A24
HSON2 GND41
B25 GND8 HSIP2 A25 EXP_RXP2 [10]
C I XC8 1 2 0.1UF/16V X7R 10% B26 A26 EXP_RXN2 [10]
C
[10] EXP_TXP3 EXP_TXP3_C GND9 HSIN2
[10] EXP_TXN3 B27 HSOP3 GND42 A27
I XC9 1 2 0.1UF/16V X7R 10% EXP_TXN3_C B28 A28
HSON3 GND43
B29 GND10 HSIP3 A29 EXP_RXP3 [10]
B30 RSVD3 HSIN3 A30 EXP_RXN3 [10]
[10] SDVO_CTRL_DATA B31 PRSNT2_2# GND44 A31
B32 GND11 RSVD7 A32

I XC10 1 2 0.1UF/16V X7R 10%


[10] EXP_TXP4 EXP_TXP4_C
[10] EXP_TXN4 B33 HSOP4 RSVD8 A33
I XC11 1 2 0.1UF/16V X7R 10% EXP_TXN4_C B34 A34
HSON4 GND45
B35 GND12 HSIP4 A35 EXP_RXP4 [10]
I XC12 1 2 0.1UF/16V X7R 10% B36 A36 EXP_RXN4 [10]
[10] EXP_TXP5 EXP_TXP5_C GND13 HSIN4
[10] EXP_TXN5 B37 HSOP5 GND46 A37
I XC13 1 2 0.1UF/16V X7R 10% EXP_TXN5_C B38 A38
HSON5 GND47
B39 GND14 HSIP5 A39 EXP_RXP5 [10]
I XC14 1 2 0.1UF/16V X7R 10% B40 A40 EXP_RXN5 [10]
[10] EXP_TXP6 EXP_TXP6_C GND15 HSIN5
[10] EXP_TXN6 B41 HSOP6 GND48 A41
I XC15 1 2 0.1UF/16V X7R 10% EXP_TXN6_C B42 A42
HSON6 GND49
B43 GND16 HSIP6 A43 EXP_RXP6 [10]
I XC16 1 2 0.1UF/16V X7R 10% B44 A44 EXP_RXN6 [10]
[10] EXP_TXP7 EXP_TXP7_C GND17 HSIN6
[10] EXP_TXN7 B45 HSOP7 GND50 A45
I XC17 1 2 0.1UF/16V X7R 10% EXP_TXN7_C B46 A46
HSON7 GND51
B47 GND18 HSIP7 A47 EXP_RXP7 [10]
[13] EXP_EN_HDR B48 PRSNT2_3# HSIN7 A48 EXP_RXN7 [10]
B49 GND19 GND52 A49
I XC18 1 2 0.1UF/16V X7R 10% EXP_TXP8_C B50 A50
EXP_TXN8_C HSOP8 RSVD9
[10] EXP_TXP8 B51 HSON8 GND53 A51
I XC19 1 2 0.1UF/16V X7R 10% B52 A52 EXP_RXP8 [10]
B [10] EXP_TXN8 GND20 HSIP8 B
B53 GND21 HSIN8 A53 EXP_RXN8 [10]
I XC20 1 2 0.1UF/16V X7R 10% EXP_TXP9_C B54 A54
EXP_TXN9_C HSOP9 GND54
[10] EXP_TXP9 B55 HSON9 GND55 A55
I XC21 1 2 0.1UF/16V X7R 10% B56 A56 EXP_RXP9 [10]
[10] EXP_TXN9 GND22 HSIP9
B57 GND23 HSIN9 A57 EXP_RXN9 [10]
I XC22 1 2 0.1UF/16V X7R 10% EXP_TXP10_C B58 A58
EXP_TXN10_C HSOP10 GND56
[10] EXP_TXP10 B59 HSON10 GND57 A59
I XC23 1 2 0.1UF/16V X7R 10% B60 A60 EXP_RXP10 [10]
[10] EXP_TXN10 GND24 HSIP10
B61 GND25 HSIN10 A61 EXP_RXN10 [10]
I XC24 1 2 0.1UF/16V X7R 10% EXP_TXP11_C B62 A62
EXP_TXN11_C HSOP11 GND58
[10] EXP_TXP11 B63 HSON11 GND59 A63
I XC25 1 2 0.1UF/16V X7R 10% B64 A64 EXP_RXP11 [10]
[10] EXP_TXN11 GND26 HSIP11
B65 GND27 HSIN11 A65 EXP_RXN11 [10]
I XC26 1 2 0.1UF/16V X7R 10% EXP_TXP12_C B66 A66
EXP_TXN12_C HSOP12 GND60
[10] EXP_TXP12 B67 HSON12 GND61 A67
I XC27 1 2 0.1UF/16V X7R 10% B68 A68 EXP_RXP12 [10]
[10] EXP_TXN12 GND28 HSIP12
B69 GND29 HSIN12 A69 EXP_RXN12 [10]
I XC28 1 2 0.1UF/16V X7R 10% EXP_TXP13_C B70 A70
EXP_TXN13_C HSOP13 GND62
[10] EXP_TXP13 B71 HSON13 GND63 A71
I XC29 1 2 0.1UF/16V X7R 10%
[10] EXP_TXN13
B72 GND30 HSIP13 A72 EXP_RXP13 [10]
B73 GND31 HSIN13 A73 EXP_RXN13 [10]
I XC30 1 2 0.1UF/16V X7R 10% EXP_TXP14_C B74 A74
[10] EXP_TXP14 EXP_TXN14_C HSOP14 GND64
[10] EXP_TXN14 B75 HSON14 GND65 A75
I XC31 1 2 0.1UF/16V X7R 10% B76 A76 EXP_RXP14 [10]
GND32 HSIP14
B77 GND33 HSIN14 A77 EXP_RXN14 [10]
I XC32 1 2 0.1UF/16V X7R 10% EXP_TXP15_C B78 A78
[10] EXP_TXP15 EXP_TXN15_C HSOP15 GND66
[10] EXP_TXN15 B79 HSON15 GND67 A79
A I XC33 1 2 0.1UF/16V X7R 10% B80 A80 EXP_RXP15 [10] A
GND34 HSIP15
B81 PRSNT2_4# HSIN15 A81 EXP_RXN15 [10]
B82 RSVD4 GND68 A82

ASUS OEM-DT MB RESTRICTED SECRET


GND GND Title : PCI EXPRESS X16
PEGATRON CORP. Engineer: Wayne Hsieh
Size Project Name Rev
A3 IPM41-D3 1.00G
Date: Thursday, July 09, 2009 Sheet 24 of 55
5 4 3 2 1
5 4 3 2 1

D
PCI Express x1 SLOT D

+3P3VSB +12V J36 +12V


SLOT 36P,PCI-E X1

+3P3V B1 A1
+12V_1 PRSNT1#
B2 +12V_2 +12V_3 A2
B3 +12V_5 +12V_4 A3
B4 GND1 GND6 A4
[5,9,17,18,21,24,28,29] SMB_CLK_R B5 SMCLK JTAG2 A5
B6 A6 +3P3V
[5,9,17,18,21,24,28,29] SMB_DATA_R SMDAT JTAG3
B7 GND2 JTAG4 A7
B8 +3.3V_1 JTAG5 A8
B9 JTAG1 +3.3V_2 A9
B10 3.3Vaux +3.3V_3 A10
[21,24,32] WAKE# B11 WAKE# PWRGD A11 PCIES_RST# [24,32,38]
1

1
+ I

1
I X1CB3 I GND I I
X1CE1 0.1UF/16V X1CB4 X1CB5 X1CB6

2
C 820UF/6.3V 0.1UF/16V 0.1UF/16V 0.1UF/16V C
2

2
GND GND GND GND
GND B12 RSVD2 GND7 A12
B13 GND3 REFCLK+ A13 CK_100M_PCIEX1 [5]
I X1C1 1 2 0.1UF/16V X7R 10% PE1_TXP1_C B14 A14
[20] N_X1_TX0 HSOP0 REFCLK- CK_100M_PCIEX1# [5]
I X1C2 1 2 0.1UF/16V X7R 10% PE1_TXN1_C B15 A15
[20] N_X1_TX#0 HSON0 GND8
B16 GND4 HSIP0 A16 N_X1_RX0 [20]
1.Place Near to slot B17 PRSNT2_1# HSIN0 A17 N_X1_RX#0 [20]
B18 A18
2.Please check if another side already GND5 GND9
have installed serial capacitor
NP_NC1 1
NP_NC2 2

GND GND

B B

A A

ASUS MBRD2_CET RESTRICTED SECRET


Title : PCI EXPRESS X1
PEGATRON CORP. Engineer: Wayne Hsieh
Size Project Name Rev
A3 IPM41-D3 1.00G
Date: Thursday, July 09, 2009 Sheet 25 of 55
5 4 3 2 1
5 4 3 2 1

+5V
+5V_DAC_CLAMP

1
I NOTE:
VCB1

1
0.1UF/16V
Install the VD1/VD2/VD3/VD4/VD5 diode

1
I I I
VD1 VD2 VD3 8/27 modify to prevent from ESD issue I I
BAV99W-L BAV99W-L BAV99W-L VD4 VD5
BAV99W-L BAV99W-L
D GND GND D

3
GND

3
VP I
VL2 VL3
1 2 RA 1 2
[13] VGA_RED
0

1
mx_r0603 0.068UH/300mA

1
I NI I mx_l0603 I
VR1 VC1 VC2 VC3
150 3.3PF/50V 5.6PF/50V 3.3PF/50V

2
1% NPO 0.25PF NPO 0.25PF NPO 0.25PF

2
GND GND GND GND
RED
VP I
VL4 VL5
1 2 GA 1 2 GREEN
[13] VGA_GREEN
0

1
mx_r0603 0.068UH/300mA I

1
I NI I mx_l0603 I BLUE
VR2 VC4 VC5 VC6 J69
150 3.3PF/50V 5.6PF/50V 3.3PF/50V DDC_CONN_15P3R

2
1% NPO 0.25PF NPO 0.25PF NPO 0.25PF 16

2
SIDE_G16
6 GND2
1 RED
I 11 NC2
C GND GND GND GND VR3 7 GND3 C
100 2 GREEN
I 1 2 VGADATA 12 DATA
VP
VL6 VL7 8 GND4
1 2 BA 1 2 3 BLUE
[13] VGA_BLUE
0 VHSYNC 13 HSYNC
1

mx_r0603 0.068UH/300mA 9 VCC


1

1
I NI I mx_l0603 I 4 NC1
VR4 VC7 VC8 VC9 VVSYNC 14 VSYNC
NOTE: 150 3.3PF/50V 5.6PF/50V 3.3PF/50V 10 GND5
2

2
1% NPO 0.25PF NPO 0.25PF NPO 0.25PF GND1
Place there VGA filter components 5
2

1 2 VGACLK 15 DCLK
within 500 mils of the VGA connector SIDE_G17
17
I
GND GND GND GND VR5

1
100 I NI NI NI
VC10 VC11 VC12 VC13
0 1 2 VR6 NOBOM 470PF/50V 3.3PF/50V 3.3PF/50V 470PF/50V

2
X7R 10% NPO 0.25PF NPO 0.25PF X7R 10%
0 1 2 VR7 NOBOM

NI
VU1 GND GND GND GND GND
+5V
74AHCT1G125 NI
1 OE# Vcc 5 VR8
2 A 30
[13] VGA_HSYNC
3 GND VHSYNC_OB
Y 4 1 2
B B

NI
GND VU2
74AHCT1G125 NI
1 VR9
OE# Vcc 5 30
[13] VGA_VSYNC 2 A
3 4 VVSYNC_OB 1 2
GND Y
1

I
VCB2
GND 0.1UF/16V
2

8/27 modify

NI
GND +5V I +5V_VGA NI VL8
VD6 VF1 80Ohm/100Mhz/2A
SS14 1.1A/6V mx_l0805
+3P3V 1 2 1 2 +5V_VGA_L 1 2 +5V_VGA_CONN

1
I 5% 1 VRN1A 6/21 modify
2.2kOhm2 NI
1

I 5% 3 VRN1B 6/21 modify VCB3


2.2kOhm4
DDCA_CLK_G I 5% 5 VRN1C 0.1UF/16V
2.2kOhm6 I I

2
DDCA_DATA_G I 5% 7 VRN1D VR18 VR19
2.2kOhm8 6/21 modify
A
2.2K 2.2K A
2

I modify 6/20 GND


VQ1
1
G

2N7002
RDDCA_DATA PEGATRON DT-MB RESTRICTED SECRET
2 S

[13] DDCA_DATA
D

I
VQ2
Title : VGA PORT
1
G

2N7002 Pegatron Corp. Engineer: York Chang


RDDCA_CLK
2 S

[13] DDCA_CLK Size Project Name Rev


D

A3 IPM41-D3 1.00G
Date: Thursday, July 09, 2009 Sheet 26 of 55
5 4 3 2 1
5 4 3 2 1

SATA CONNECTOR FOR BPC


D D

I I
P60 P61
SATA_CON_7P SATA_CON_7P
[20] SATA_TXP0 I TC1 1 2 0.01UF/25V X7R 10% 1 1 P_GND1 8 [20] SATA_TXP1 I TC5 1 2 0.01UF/25V X7R 10% 1 1 P_GND1 8
SATA_TXP0_C 2 SATA_TXP1_C 2
2 2
[20] SATA_TXN0 I TC2 1 2 0.01UF/25V X7R 10% SATA_TXN0_C 3 3 [20] SATA_TXN1 I TC6 1 2 0.01UF/25V X7R 10% SATA_TXN1_C 3 3
4 4 4 4
[20] SATA_RXN0 I TC3 1 2 0.01UF/25V X7R 10% SATA_RXN0_C 5 5 COLOR = ORANGE [20] SATA_RXN1 I TC7 1 2 0.01UF/25V X7R 10% SATA_RXN1_C 5 5 COLOR = ORANGE
SATA_RXP0_C 6 SATA_RXP1_C 6
6 6
[20] SATA_RXP0 I TC4 1 2 0.01UF/25V X7R 10% 7 7 P_GND2 9 [20] SATA_RXP1 I TC8 1 2 0.01UF/25V X7R 10% 7 7 P_GND2 9

GND GND

7/15 modify 12X702200Y00


7/15 modify 12X702200Y00

C C

I I
P62 P63
SATA_CON_7P SATA_CON_7P
[20] SATA_TXP2 I TC9 1 2 0.01UF/25V X7R 10% 1 1 P_GND1 8 [20] SATA_TXP3 I TC13 1 2 0.01UF/25V X7R 10% 1 1 P_GND1 8
SATA_TXP4_C 2 SATA_TXP5_C 2
2 2
[20] SATA_TXN2 I TC10 1 2 0.01UF/25V X7R 10% SATA_TXN4_C 3 3 [20] SATA_TXN3 I TC14 1 2 0.01UF/25V X7R 10% SATA_TXN5_C 3 3
4 4 4 4
[20] SATA_RXN2 I TC11 1 2 0.01UF/25V X7R 10% SATA_RXN4_C 5 5 COLOR = ORANGE [20] SATA_RXN3 I TC15 1 2 0.01UF/25V X7R 10% SATA_RXN5_C 5 5 COLOR = ORANGE
SATA_RXP4_C 6 SATA_RXP5_C 6
6 6
[20] SATA_RXP2 I TC12 1 2 0.01UF/25V X7R 10% 7 7 P_GND2 9 [20] SATA_RXP3 I TC16 1 2 0.01UF/25V X7R 10% 7 7 P_GND2 9

GND GND

7/15 modify 12X702200Y00


7/15 modify 12X702200Y00

+3P3V
1

B I B
F3R1 I
8.2K TD1
BAT54AW
2

1
3 HD_LED# [44]
[20] ICH_SATALED# 2

A A

ASUS OEM-DT MB RESTRICTED SECRET


Title : SATA2 FOR BPC
PEGATRON CORP. Engineer: Wayne Hsieh
Size Project Name Rev
A3 IPM41-D3 1.00G
Date: Thursday, July 09, 2009 Sheet 27 of 55
5 4 3 2 1
5 4 3 2 1

+5V +3P3V -12V +5V +3P3V

+5V +5V
A_D[31..0] [20,29]

1
+ I +

1
I I KCB1 I
D KCE1 KCB2 0.1UF/16V KCE2 D

2
820UF/6.3V 0.1UF/16V 820UF/6.3V

2
I
+12V
GND GND
J20 GND GND
SLOT 120P, PCI
B1 -12V TRST A1
B2 TCK +12V A2
B3 A3 PCI1_TMS
GND11 TMS PCI1_TDI
B4 TDO TDI A4
B5 +5V22 +5V1 A5
B6 +5V23 INTA A6 PINTE# [20,29]
[20,29] PINTF# B7 INTB INTC A7 PINTG# [20,29]
[20,29] PINTH# B8 INTD +5V2 A8
B9 PRSNT1 RESERVED1 A9
7/8 modify net name B10 A10 7/8 modify net name
RESERVED5 +5V3 +3P3VSB
B11 PRSNT2 RESERVED2 A11
B12 GND12 GND1 A12
B13 GND13 GND2 A13
B14 RESERVED6 RESERVED3 A14
B15 GND14 RST A15 ICH_PCIRST# [20,29]
[5] CK_33M_SL1 B16 CLK +5V4 A16
B17 GND15 GNT A17 GNT0# [20]

1
B18 A18 I
[20] PREQ#0 REQ GND3 KCB5
B19 +5V8 RESERVED4 A19 PPME# [20,29]
A_D31 B20 A20 A_D30 0.1UF/16V

2
A_D29 AD31 AD30
B21 AD29 +3.3V1 A21
B22 A22 A_D28
C A_D27 GND16 AD28 A_D26 C
B23 AD27 AD26 A23
A_D25 B24 A24
AD25 GND4 A_D24
B25 +3.3V7 AD24 A25 GND
B26 A26 A_D19
[20,29] C/BE3# A_D23 C/BE3 IDSEL
B27 AD23 +3.3V2 A27
B28 A28 A_D22
A_D21 GND17 AD22 A_D20
B29 AD21 AD20 A29
A_D19 B30 A30
AD19 GND5 A_D18
B31 +3.3V8 AD18 A31
A_D17 B32 A32 A_D16
AD17 AD16
[20,29] C/BE2# B33 C/BE2 +3.3V3 A33
B34 GND18 FRAME A34 PFRAME# [20,29]
[20,29] PIRDY# B35 IRDY GND6 A35
B36 +3.3V9 TRDY A36 PTRDY# [20,29]
[20,29] PDEVSEL# B37 DEVSEL GND7 A37
B38 GND19 STOP A38 PSTOP# [20,29]
[20,29] PPLOCK# B39 LOCK +3.3V4 A39
[20,29] PPERR# B40 PERR SDONE A40 SMB_CLK_R [5,9,17,18,21,24,25,29]
B41 +3.3V10 SBO A41 SMB_DATA_R [5,9,17,18,21,24,25,29]
[20,29] PSERR# B42 SERR GND8 A42
B43 +3.3V11 PAR A43 PPAR [20,29]
B44 A44 A_D15
[20,29] C/BE1# A_D14 C/BE1 AD15
B45 AD14 +3.3V5 A45
B46 A46 A_D13
A_D12 GND20 AD13 A_D11
B47 AD12 AD11 A47
A_D10 B48 A48
AD10 GND9 A_D9
B49 GND21 AD9 A49

B A_D8 B
B52 AD8 C/BE0 A52 C/BE0# [20,29]
A_D7 B53 A53
AD7 +3.3V6 A_D6
B54 +3.3V12 AD6 A54
A_D5 B55 A55 A_D4
A_D3 AD5 AD4
B56 AD3 GND10 A56
B57 A57 A_D2 +5V
A_D1 GND22 AD2 A_D0
B58 AD1 AD0 A58
B59 A59
hold_NC1

hold_NC2

ACK64#_1 +5V9 +5V5 REQ64#_1 KRN1D 7


B60 ACK64 REQ64 A60 I 2.7K 8
B61 A61 I KRN1C 5 6
+5V10 +5V6 2.7K
B62 +5V11 +5V7 A62
1

GND GND

+3P3V +5V

A A
I KRN4A 1 2 I KRN6A 1 2
[20] PINTA# 8.2K [20,29] PPERR# 2.7K
I KRN4C 5 6 I KRN6B 3 4
[20] PINTC# 8.2K [20,29] PSERR# 2.7K
+3P3V I KRN2A 1 2 I KRN6C 5 6
[20,29]
[20,29]
PINTF#
PINTG# I KRN2D 7
8.2K
8.2K 8
[20,29] PPLOCK#
[20,29] PDEVSEL# I KRN6D 7
2.7K
2.7K 8 ASUS OEM-DT MB RESTRICTED SECRET
[20] PREQ#0 I
I
KRN3A
KRN3C
1
5
8.2K 2
6
[20] PINTB# I
I
KRN4B
KRN4D
3
7
8.2K 4
8
[20,29] PIRDY# I
I
KRN7A
KRN7B
1
3
2.7K 2
4
Title : PCI1 SLOT
[20,29] PREQ#1 8.2K [20] PINTD# 8.2K [20,29] PSTOP# 2.7K
I KRN3B 3 4 I KRN2C 5 6 I KRN7C 5 6 Engineer:
[20] PREQ#3
I KRN3D 7
8.2K
8
[20,29] PINTE#
I KRN2B 3
8.2K
4
[20,29] PFRAME#
I KRN7D 7
2.7K
8
PEGATRON CORP. Wayne Hsieh
[20] PREQ#2 8.2K [20,29] PINTH# 8.2K [20,29] PTRDY# 2.7K
Size Project Name Rev
A3 IPM41-D3 1.00G
Date: Thursday, July 09, 2009 Sheet 28 of 55

5 4 3 2 1
5 4 3 2 1

D D
+5V +3P3V -12V +5V +3P3V

A_D[31..0] [20,28]
+12V +5V +5V

1
NI NI
KCB6 KCB7
0.1UF/16V 0.1UF/16V

2
I

GND
J21 GND
SLOT 120P, PCI
B1 -12V TRST A1
B2 TCK +12V A2
B3 A3 PCI2_TMS
GND11 TMS PCI2_TDI
B4 TDO TDI A4
B5 +5V22 +5V1 A5
B6 +5V23 INTA A6 PINTF# [20,28]
[20,28] PINTG# B7 INTB INTC A7 PINTH# [20,28]
[20,28] PINTE# B8 INTD +5V2 A8
B9 A9 7/8 modify net name
7/8 modify net name PRSNT1 RESERVED1
B10 RESERVED5 +5V3 A10
B11 A11 +3P3VSB
PRSNT2 RESERVED2
B12 GND12 GND1 A12
C B13 A13 C
GND13 GND2
B14 RESERVED6 RESERVED3 A14
B15 GND14 RST A15 ICH_PCIRST# [20,28]
[5] CK_33M_SL2 B16 CLK +5V4 A16
B17 GND15 GNT A17 GNT1# [20]

1
B18 A18 NI
[20,28] PREQ#1 REQ GND3 KCB10
B19 +5V8 RESERVED4 A19 PPME# [20,28]
A_D31 B20 A20 A_D30 0.1UF/16V

2
A_D29 AD31 AD30
B21 AD29 +3.3V1 A21
B22 A22 A_D28
A_D27 GND16 AD28 A_D26
B23 AD27 AD26 A23
A_D25 B24 A24
AD25 GND4 A_D24
B25 +3.3V7 AD24 A25 GND
B26 A26 A_D20
[20,28] C/BE3# A_D23 C/BE3 IDSEL
B27 AD23 +3.3V2 A27
B28 A28 A_D22
A_D21 GND17 AD22 A_D20
B29 AD21 AD20 A29
A_D19 B30 A30
AD19 GND5 A_D18
B31 +3.3V8 AD18 A31
A_D17 B32 A32 A_D16
AD17 AD16
[20,28] C/BE2# B33 C/BE2 +3.3V3 A33
B34 GND18 FRAME A34 PFRAME# [20,28]
[20,28] PIRDY# B35 IRDY GND6 A35
B36 +3.3V9 TRDY A36 PTRDY# [20,28]
[20,28] PDEVSEL# B37 DEVSEL GND7 A37
B38 GND19 STOP A38 PSTOP# [20,28]
[20,28] PPLOCK# B39 LOCK +3.3V4 A39
[20,28] PPERR# B40 PERR SDONE A40 SMB_CLK_R [5,9,17,18,21,24,25,28]
B41 +3.3V10 SBO A41 SMB_DATA_R [5,9,17,18,21,24,25,28]
B B
[20,28] PSERR# B42 SERR GND8 A42
B43 +3.3V11 PAR A43 PPAR [20,28]
B44 A44 A_D15
[20,28] C/BE1# A_D14 C/BE1 AD15
B45 AD14 +3.3V5 A45
B46 A46 A_D13
A_D12 GND20 AD13 A_D11
B47 AD12 AD11 A47
A_D10 B48 A48
AD10 GND9 A_D9
B49 GND21 AD9 A49

A_D8 B52 A52


AD8 C/BE0 C/BE0# [20,28]
A_D7 B53 A53
AD7 +3.3V6 A_D6
B54 +3.3V12 AD6 A54
A_D5 B55 A55 A_D4
A_D3 AD5 AD4
B56 AD3 GND10 A56
B57 A57 A_D2 +5V
A_D1 GND22 AD2 A_D0
B58 AD1 AD0 A58
B59 A59
hold_NC1

hold_NC2

ACK64#_2 +5V9 +5V5 REQ64#_2 KRN1A 1


B60 ACK64 REQ64 A60 I 2.7K 2
B61 A61 I KRN1B 3 4
+5V10 +5V6 2.7K
B62 +5V11 +5V7 A62
1

GND GND

A A

ASUS OEM-DT MB RESTRICTED SECRET


Title : PCI2 SLOT
PEGATRON CORP. Engineer: Wayne Hsieh
Size Project Name Rev
A3 IPM41-D3 1.00G
Date: Thursday, July 09, 2009 Sheet 29 of 55
5 4 3 2 1
5 4 3 2 1

D D

DOUBLE STACK PORT CONNECTOR FOR CPC

I I
URN5B
3 4
J16
0
USB_CON_2X4P

LP4- 1P- VCC1


[20] USBN2 2 1
1

1P+ GND1
NI 3 4
UL5
90OHM/100MHz/300mA LP4+
4

[20] USBP2
NI GND +SBV45 I +5V_DUAL_USB
1 2 UF3
0 UU3 1.6A/6V
CM1213_04SO +5VSB LP5- 2P- VCC2
I 6 5 2 1
URN5A
CH1 1 2P+ GND2
6CH4 LP5+ 7 8 I
UF4

1
C VN 2 5 VP I 1.6A/6V C
+
I UC3 I 2 1
URN6B CH2 3 4 CH3 0.1UF/16V UCE3

2
3 4 GND GND 330UF/6.3V
0

2
SIDE_G9 SIDE_G11
9 11
SIDE_G10 SIDE_G12
[20] USBN3 10 12
1

NI GND GND
UL6
90OHM/100MHz/300mA modify 8/1
4

[20] USBP3 470uF/6.3V=11X040477140 change to 330uF/6.3V=11X040337140

1 0 2 GND GND

I
URN6A

B B

A A

ASUS OEM-DT MB RESTRICTED SECRET


DOUBLE USB CON.
Title :
PEGATRON CORP. Engineer: Wayne Hsieh
Size Project Name Rev
A3 IPM41-D3 1.00G
Date: Thursday, July 09, 2009 Sheet 30 of 55

5 4 3 2 1
5 4 3 2 1

+SBV89 NOTE: Check USB cable internal whether had capacity I USB_F
NI:BPC UF5
I: CPC 1.6A/6V
2 1

1
I + UF6
UCB3 I 1.6A/6V
D 0.1UF/16V UCE5 2 1 D

2
I 330UF/6.3V

2
I P154
URN9B modify 8/1
3 4 HEADER_2X5P_K9 470uF/6.3V=11X040477140 change to 330uF/6.3V=11X040337140
0
1 2 GND GND
LP8- 3 4 LP9-
[20] USBN4 LP8+ LP9+
5 6
1

2
NI 7 8
UL9 10
90OHM/100MHz/300mA
4

[20] USBP4 3

1 0 2 NI GND GND

I
UU5
URN9A CM1213_04SO 12X602025Y92 (15U)
+5VSB
CH1 1 6CH4
VN 2 5 VP
CH2 3 4 CH3

GND +5V_DUAL
I
URN10B USB_F

C
3 0 4 USBPW C

[20] USBN5 1
I 2
1

NI 3 +5VSB
UL10
90OHM/100MHz/300mA HEADER_1X3P
Default as short pin 1-2
4

[20] USBP5
1 2
USBPW5-8:
0 NOTE:
+SBV89
1-2: +5V_DUAL
I Check USB cable internal whether had capacity
URN10A NI: BPC 2-3: +5VSB
I: CPC USBPW:12

1
I MINI_JUMPER
UCB4 I
0.1UF/16V

2
I
I P153
URN11B
3 4 HEADER_2X5P_K9
0
1 2 GND
LP10- 3 4 LP11-
[20] USBN6 LP10+ LP11+
5 6
1

NI 7 8
UL11 10
B 90OHM/100MHz/300mA B
4

[20] USBP6
1 0 2 NI GND GND

I
UU6
URN11A CM1213_04SO
+5VSB 12X602025Y92 (15U)
CH1 1 6CH4
VN 2 5 VP
CH2 3 4 CH3

GND
I
URN12B
3 0 4

[20] USBN7
1

NI
UL12
90OHM/100MHz/300mA
4

[20] USBP7

A 1 0 2 A

I
URN12A
ASUS OEM-DT MB RESTRICTED SECRET
Title : USB HEADER CON.
PEGATRON CORP. Engineer: Wayne Hsieh
Size Project Name Rev
A3 IPM41-D3 1.00G

Date: Thursday, July 09, 2009 Sheet 31 of 55


5 4 3 2 1
5 4 3 2 1
I
+1P2V_VDD +3P3VSB
LU2

RTL8111DL Switching regulator I LR1 1 0 2 /8103_NI mx_r0603 +SWREG/+1P2VOUT 44


LR2 0 mx_r0603 VDDSR2
NI 1 2 /8103_I 45 VDDSR1
PIN PIN NAME I/O Function

1
I I
48 Layout Guide: +3P3VSB wider than 40mil LCB17 LCB1 3
REG_OUT O Regulator output 22UF/6.3V 0.1UF/16V MDIN0 LAN_MDI0_N [33]
2 LAN_MDI0_P [33]

2
LC2~LC5 place near 200mil to LAN X5R 10% X7R 10% MDIP0
4 FB12 I Feedback pin mx_c1206 6
MDIN1 LAN_MDI1_N [33]
43 3.3V : Enable ; 0V : disable +3P3VSB /8103_NI 5
ENSWREG I MDIP1 LAN_MDI1_P [33]
GND GND
D 44,45 VDDREG P 3.3V power pin MDIN2 9 LAN_MDI2_N [33] D
29 VDD33_1 MDIP2 8 LAN_MDI2_P [33]
37 VDD33_2
Layout Guide: MDIN3 12 LAN_MDI3_N [33]

1
I I I I 1 AVDD33_1 MDIP3 11 LAN_MDI3_P [33]
+1P2V_OUT & +1P2OUT wider than 60mil LCB2 LCB3 LCB4 LCB5 40
0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V AVDD33_2
LL1&LR18 place near 200mil to LAN

2
X7R 10% X7R 10% X7R 10% X7R 10%
LCB6&LCB7 place near 300mil to LAN
GND GND GND GND +3P3VSB
+1P2V_OUT

1
LL1 /8103NI
1 2 +1P2OUT 48 NI
SROUT12 LR24
8103EL Pin 8111DL Pin I I 4.7UH/1.7A 4.7K

1
LCB6 LCB7 I

2
DVDD3.3V 29,37 DVDD3.3V 29,37 22UF/6.3V 0.1UF/16V
X5R 10% X7R 10% 1 0 2 32 LAN_EECS

2
AVDD3.3V 1 AVDD3.3V 1,40 mx_c1206 EECS
LED0 38 REALTEK_ACTLED# [33]
+1P2V_VDD /8103_NI NI LR18 35
DVDD1.2V 10,13,30,36 DVDD1.2V 13,36 LED1/EESK LAN_EEDI REALTEK_LINK100# [33]
/8103_I LED2/EEDI/AUX 34
GND GND 33 LAN_EEDO
+1.2V_OUT 19,45,48 AVDD1.2V 10,30,39 0 LED3/EEDO REALTEK_LINK1G# [33]
I 1 2 13 DVDD12_1
36 +3P3VSB
EVDD1.2V 19 LR4 /8103_NI DVDD12_2
I I I I I 30 DVDD12_3

1
LCB8 LCB9 LCB10 LCB11 LCB12 10 AVDD12_1

1
+1.0V_OUT 48 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 39
C X7R 10% X7R 10% X7R 10% X7R 10% X7R 10% AVDD12_2 C
I NI

2
LR5
3.6K LU5 +3P3VSB
EEPROM 1Kb 93C46

2
GND GND GND GND GND 1 CS VCC 8
2 SK NC 7
1 0 2 +1P2V_EVDD 19 3
I EVDD12 DI ORG 6

1
4 DO GND 5 NI
LR6 /8103_NI I I LCB14

1
LCB18 LCB13 NI 0.1UF/16V
NOTE:

2
2
1UF/16V 1UF/16V X7R 10%
X7R 10% X7R 10% LR7 If using eFuse funtion,

2
mx_c0603 mx_c0603 10KOhm GND GND
/8103_I NI LU2 directly

1
GND GND NOTE: LED MODE
LJP1 NOBOM
1 2 FB12 4 GND (LEDS1, LEDS0) = (1, 1) DEFAULT
FB12
SHORTPIN (LEDS1, LEDS0) = (0, 1) ==> For this schematic

CLKREQB 25 O/D

[20] LAN_RXN I LC2 1 2 0.1UF/16V X7R 10% LAN_RXN_C 21


HSON
[20] LAN_RXP I LC1 1 2 0.1UF/16V X7R 10% LAN_RXP_C 20
HSOP
+3P3VSB
+3P3V
[20] LAN_TXN 16 HSIN

1
[20] LAN_TXP 15 HSIP I NOTE: 8111DL[PIN43]
1

LR9
B 0 B
I
LR8
3.3V enable internal regulator
[5] CK_100M_LAN 17 /8103_NI
1K
[5] CK_100M_LAN# 18
REFCLK_P 0V disable internal regulator

2
REFCLK_N
2

LAN_ISOLATEB 28 43 ENSWREG
ISOLATEB ENSR

[21,24,25] WAKE# 26 LANWAKEB

1
NI
1

27 LR11
[24,25,38] PCIES_RST# PERSTB
I 0
LR10 LANRSET 46 RSET
1

15K NI

2
1

LC3
2

10PF/50V I
2

NPO 5% LR12
2.49K GND
1%
2

GND GND GND


VP
LR13 23
0 LAN_XIN NC1
[5] CK_25M_LAN 1 2 41 CKTAL1 NC2 24
NI
NOBOM Y10 25Mhz
1 2 Y10 1 2 LAN__XOUT 42
GND
CKTAL2
NI LR14 0 Ohm 3 NI
1

A
LC4 LC5 22 A
33PF/50V EGND
30PF/50V
NPO 5% NPO 5% 7
2

GND2
GND1 14
GND3 31
GND4 47
GND GND GND Title : 8111DL co-lay 8102EL
PEGATRON CORP. Engineer: York Chang
RTL8111DL_GR GND Size Project Name Rev
A3 IPM41-D3 1.00
Date: Thursday, July 09, 2009 Sheet 32 of 55

5 4 3 2 1
5 4 3 2 1

I
UU7
CM1213_04SO +5VSB

LAN_MDI1_P CH1 1 6CH4 LAN_MDI1_N

VN 2 5 VP

LAN_MDI0_P CH2 3 4 CH3 LAN_MDI0_N 09/11 modify


LAN + Dual USB CONNECTOR

1
GND I +3P3VSB
LCB25
0.1UF/16V
12G14203322X

2
D D

1
I giga LAN connector
I GND LR20 /Change to 12XA070YG040 for 10/100
200 I
UU8 mx_r0603
J9

2
CM1213_04SO
+5VSB JACK_USB/LAN_GIGA
LAN_MDI3_P CH1 1 6CH4 LAN_MDI3_N
ICH_ACT_CTRL 19 21 LINKLED#_Q
VN 2 ACTLEDP LILEDP REALTEK_LINK1G# [32]
5 VP

1
I I
LAN_MDI2_P CH2 3 4 CH3 LAN_MDI2_N LC15 LC11

1
GND I 1000PF/50V Y G 1000PF/50V

2
LCB26 X7R 10% X7R 10%
0.1UF/16V

2
8/19 modify GND GND 8/19 modify
[32] REALTEK_ACTLED# 20 ACTLEDN LILEDN 22 REALTEK_LINK100# [32]

1
GND I I
LC12 LC16
1000PF/50V 1000PF/50V

2
X7R 10% X7R 10%

GND GND
8/19 modify
8/19 modify
10/2 modify 10/3 modify

C 10 9 VCC_CTR C
[32] LAN_MDI0_P TD1+ VCC_CTR

[32] LAN_MDI0_N 11 TD1-

1
18 GND_CTR NI
GND_CTR LCB22

1
12 I I 0.01UF/25V

2
[32] LAN_MDI1_P TD2+

1
LR22 LCB23 X7R 10%
13 0 0.1UF/16V /8102E_I
[32] LAN_MDI1_N TD2-
/8102E_NI /8102E_I GND

2
2
[32] LAN_MDI2_P 14 TD3+ LANGND30 30
29 8/29 modify
LANGND29
[32] LAN_MDI2_N 15 TD3- LANGND26 26
LANGND25 25 GND GND

[32] LAN_MDI3_P 16 TD4+

[32] LAN_MDI3_N 17 TD4-


GND

I
URN16A
1 2 +SBV45
0

LP0- 6 5
[20] USBN0 1P- VCC1
4

90OHM/100MHz/300mA
UL7
B NI B
7 1P+ GND1 8
LP0+
1

[20] USBP0
NI GND
3 0 4 UU4
I CM1213_04SO +5VSB
URN16B
CH1 1 6CH4
+SBV45
VN 2 5 VP
I
URN17A CH2 3 4 CH3 LP1- 2 1
2P- VCC2
1 0 2 GND

LP1+ 3 4
2P+ GND2
[20] USBN1 NI
4

90OHM/100MHz/300mA
UL8 GND
1

[20] USBP1
USBGND28 28
USBGND27 27
3 0 4 USBGND24 24
USBGND23 23
I
URN17B

A A
GND

ASUS OEM-DT MB RESTRICTED SECRET


Title : RJ45+USB CONN.
PEGATRON CORP. Engineer: Wayne Hsieh
Size Project Name Rev
A3 IPM41-D3 1.00G
Date: Thursday, July 09, 2009 Sheet 33 of 55
5 4 3 2 1
5 4 3 2 1

ALC888S-B1 ALC888S-VC2 +3P3VSB +3P3V C.S ALC662-GR LQFP-48:02G611003200

1
C.S ALC888S-GR(B1) LQFP-48:02G611003510 If pin 23/24 and pin 21/22 support retasking function,
AR26 AR25
Pin 4 DVSS GPIO1/DMIC-DATA 0 Ohm 0 Ohm C.S ALC888S-VC2-GR
AU22 LQFP-48:02G611003521 please changed AR34/AR35/AR30/AR31 to 75 ohm
NI/VIA I I/VIA NI I
I AR34 1K

2
1 24 F_LIN1_RC I AC17 1 2 4.7UF/6.3V X5R 10% I_F_LIN1_RC 1 2
DVDD1 LINE1_R LIN1_R_C [35]
9 mx_c0805 I AR35 1K
DVDD2 F_LIN1_LC
LINE1_L 23 I AC16 1 2 4.7UF/6.3V X5R 10% I_F_LIN1_LC 1 2 LIN1_L_C [35]

ALC888S Rev. A
mx_c0805
Please noite:

1
NI/VIA I I
D ACB1 ACB2 4 D
DVSS1

1
10UF/10V 0.1UF/16V 7
AZ_BITCLK need add

2
Y5V +80-20% DVSS2
Y5V +80-20% AR24 I AR15 75
0 Ohm 36 FRONT_RC I ACE4 1 2 10UF/25V I_FRONT_R_C 1 2 FRONT_R_C [35]
FRONT_OUT_R
a serial res(22 ohm) I AR32 75

+
I FRONT_LC
35 I ACE5 1 2 10UF/25V I_FRONT_L_C 1 2 FRONT_L_C [35]

2
FRONT_OUT_L

+
I
near SB side AR1
33 GND GND GND GND
1 2 RSDATA_IN0 8
[21] AZ_SDATA_IN0 SDATA_IN AR30 1K
[21] AZ_SDATA_OUT 5 SDATA_OUT I
10 22 MIC1_RC I AC19 1 2 4.7UF/6.3V X5R 10% I_MIC1_R_C 1 2
[21] AZ_SYNC SYNC MIC1_R MIC1_R_C [35]
11 mx_c0805
[21] AZ_RST# RESET#
6 21 MIC1_LC I AC18 1 2 4.7UF/6.3V X5R 10% I_MIC1_L_C 1 2
[21] AZ_BITCLK BIT_CLK MIC1_L MIC1_L_C [35]
mx_c0805
I AR31 1K

1
NI NI
AC3 AC4
10PF/50V 22PF/50V 12 13 SENSE_A [35]

2
PCBEEP SENSE_A
NPO 5% NPO 5%

I AR2 75
GND GND 15 LIN2_RC I ACE6 1 2 100uF/16V R_LIN2_RC 1 2
LINE2_R LIN2_R_C [36]

+
14 LIN2_LC I ACE7 1 2 100uF/16V R_LIN2_LC 1 2
LINE2_L LIN2_L_C [36]
I AR5 75

+
C
Provision AR23 for I AR4 75 C
2 17 MIC2_RC I ACE8 1 2 100uF/16V I_MIC2_R_C 1 2
ALC888S-VC codec GPIO0/DMIC-CLK/SPDIFO2 MIC2_R MIC2_R_C [36]

+
3 GPIO1/DMIC-DATA
16 MIC2_LC I ACE9 1 2 100uF/16V I_MIC2_L_C 1 2
MIC2_L MIC2_L_C [36]
I AR6 75

+
NI 1 0 2 AR37
The Gate Pin of AQ3 should
+5VSB I +5VA 34
be placed in degital area SENSE_B ACB9 SENSE_B [35,36]
AQ1 10UF/6.3V
for better Audio Quality NI/VIA I X5R 10% 1 2 AGND
25
S

3 D

AVDD1 ACB8
NI/VIA I 0.1UF/16V
2

+12V I 38 AVDD2
AR7 NTR4502PT1G X7R 10% 1 2 ALC662 → NI
G

AGND
100K R_CD_IN_JD 39.2K 2 AR70 1%
1

AGPIO 33 I 1 ALC888 → I LIN1_JD [35]


5% 888S(B1) 0 ohm
1

1
1 2 AZ_AVDD_GATE + I I I 32
MIC1_VREFO_R MIC1_VREF_R [35]
ACE10 ACB4 ACB5 26 AVSS1
1

NI 100uF/16V 0.1UF/16V 0.1UF/16V 42 28 MIC1_VREF_L [35]


2

2
ACB3 AVSS2 MIC1_VREFO_L
X7R 10% X7R 10% If front Microphone is not support retasking function,
2
1

I I 10UF/6.3V 37
2

PIN37_VREFO
1

AC26 AR8 X5R 10%


0.22UF/16V 100K mx_c0805
1.ACE8/ACE9 can be changed to SMD 4.7uF(11X234475150)
LINE1_VREFO 29
X7R 10% 5% AGND AGND AGND AGND 2.please change AR4/AR6 to 1K for better ESD immunity
2

mx_c0603 30 MIC2_VREF [36]


2

MIC2_VREFO
3 I 31
D LINE2_VREFO LIN2_VREF [36]
AQ3
AP2306GN 27 ALC_VREF
1 AQ3_G VREF
GND GND AGND Pin33 : rear side detected function as line-in used
B B

Digital Region S 2
G 20 CD_R

1
I
ACB6
AR70 : for ALC888S-B1:use 0 ohm
I
18 10UF/6.3V for ALC888S-VC2:use 39.2K ohm
AU2

2
+12V CD_L
X5R 10%

8 1 +5VA_AZ 19 ALC662 → NI
Vin Vout CD_GND
AGND ALC888 → I
7 GND4 GND1 2
1

+ NI
1

6 3 ACE11 I I AR27 75
GND3 GND2 AC2 SURB_RC
100uF/16V SIDESURR_OUT_R 46 I ACE868 1 2 10UF/25V I_SURB_R_C 1 2 SURB_R_C [35]
0.1UF/16V I AR38 75

+
5 4
2

NC2 NC1 SURB_LC


SIDESURR_OUT_L 45 I ACE869 1 2 10UF/25V I_SURB_L_C 1 2 SURB_L_C [35]

+
78L05
I AR36 75
44 LEFC I ACE870 1 2 10UF/25V I_LEF_C 1 2
LFE_OUT LEF_C [35]
I AR28 75

+
AGND AGND AGND GND
1 1M 2 43 CENC I ACE871 1 2 10UF/25V I_CEN_C 1 2
CEN_OUT CEN_C [35]
AR10

+
I
I AR33 75
I 47 41 SUR_RC I ACE872 1 2 10UF/25V I_SUR_R_C 1 2
SPDIFI/EAPD SURR_OUT_R SUR_R_C [35]
1

ACB7 I AR29 75

+
10UF/16V NI 48 39 SUR_LC I ACE873 1 2 10UF/25V I_SUR_L_C 1 2
[36] SPDIF_OUT SPDIFO SURR_OUT_L SUR_L_C [35]
X5R 10% AC47

+
2

mx_c0805 100PF/50V
A 1 2 40 AUD_JD_REF A
JDREF

1
I I /VIA 5.1K I
AR69 AR11
PEGATRON DT-MB RESTRICTED SECRET
1

GND 0 NI/ VIA I 20KOhm


1 2 ALC888S_GR AC36 1%
Change ACE864/ACE865/AC6 220PF/50V
Title : ALC888S AUDIO CODEC
2

X7R 10% 2
to 4.7uF/X5R/0805/10V Engineer: XXXXX_XX
PEGATRON CORP.
because CD-IN are
AGND GND Size Project Name Rev
dedicated Input port , AGND AGND
PLACE NEAR front audio CODEC FOR EMI and for better noise immunity
A3 IPM41-D3 1.00
Date: Thursday, July 09, 2009 Sheet 34 of 55

5 4 3 2 1
5 4 3 2 1

[34] MIC1_VREF_R

[34] MIC1_VREF_L AL87/AL89/AL91/AL93/AL95/AL97;Please use AL88/AL90/AL92/AL94/AL96/AL98;Please use


09X131216000 instead of 0 ohm if you found have Azalia Rear Audio Connector 09X131216000 instead of 0 ohm if you found have

1
I I EMI issue Note: EMI issue ALC662 → NI
AR13 AR12
ALC888 → I
4.7K 4.7K AR61&AR63 I
J86

2
Place near to codec
AUDIO_6IN1_AZA_26P
for avoid JD malfunction
D [34] LIN1_L_C VP AL87 1 2 0 LIN1_L 10 L L 23 CEN I AL88 1 0 2 CEN_C [34] D
11 B O 24 CEN_JD I 1 10K 2 AR60 1%
[34] LIN1_JD
12 PORT3 PORT6 25
[34] LIN1_R_C VP AL89 1 2 0 LIN1_R 13 R R 26 LEF I AL90 1 0 2 LEF_C [34]

[34] FRONT_L_C VP AL91 1 2 0 FRONT_L 6 L L 19 SUR_L I AL92 1 0 2 SUR_L_C [34]


I 1 5.1K 2 AR61 1% FRONT_JD 7 L B 20 SUR_JD I 1 39.2K 2 AR62 1%
[34] SENSE_A SENSE_A [34]
8 PORT2 PORT5 21
[34] FRONT_R_C VP AL93 1 2 0 FRONT_R 9 R R 22 SUR_R I AL94 1 0 2 SUR_R_C [34]

[34] MIC1_L_C VP AL95 1 2 0 MIC1_L 2 L L 15 SURB_L I AL96 1 0 2 SURB_L_C [34]


I 1 20K 2 AR63 1% MIC1_JD 3 16 SURB_JD I 1 5.1K 2 AR64 1%
P G SENSE_B [34,36]
4 PORT1 PORT4 17
[34] MIC1_R_C VP AL97 1 2 0 MIC1_R 5 18 SURB_R I AL98 1 0 2 SURB_R_C [34]
1 R R 14
I I I I I I
AC21 AC28 AC20 AC22 AC24 AC25 31 NC1 GND3 27 Note:
32 NC2 GND4 28 AR60&AR62&AR64
1

1
100PF/50V

100PF/50V

100PF/50V

100PF/50V

100PF/50V

100PF/50V
33 GND1 GND5 29 I I I I I I
Place near to codec

NPO 5%

NPO 5%

NPO 5%

NPO 5%

NPO 5%

NPO 5%
34 GND2 GND6 30 AC27 AC29 AC32 AC30 AC31 AC33
2

1
for avoid JD malfunction

100PF/50V

100PF/50V

100PF/50V

100PF/50V

100PF/50V

100PF/50V
AUD_GND

NPO 5%

NPO 5%

NPO 5%

NPO 5%

NPO 5%

NPO 5%
2

2
2
AGND AGND AGND AGND AGND AGND
JP19
SHORTPIN
ALC888S_NI NOBOM
C I 1 10KOhm 2 AR66 1% LIN1_JD C

1
AGND AGND AGND AGND AGND AGND AGND
AGND AGND

Azalia Rear Audio Connector


Note:
Rear Side Audio Header Just Only Function Dedicated
NIALC888S_NI
J83
AUDIO_3IN1_AZA_13P
LIN1_L 32 L
LIN1_JD 33
34 PORT3 B
LIN1_R 35 R
B B
FRONT_L 22 L
FRONT_JD 23
24 PORT2 L
FRONT_R 25 R

MIC1_L 2 L
MIC1_JD 3
PORT1
MIC1_R
4
R
P
5
1
AR24&AR25&AR26 G1 P_GND1 NP_NC1 P1
Place near to codec G2 P_GND2
G3 P_GND3
G4 P_GND4

AGND
NI
AC34
100PF/50V
NPO 5% AUD_GND 1 2
1 2
NOBOM
I JP1
A
AR65 SHORTPIN AGND A
0
1 2
PEGATRON DT-MB RESTRICTED SECRET

AGND GND
Title : HP AUDIO CONNECTOR
PEGATRON CORP. Engineer: XXXXX_XX
PLACE NEAR AUDIO Connector FOR EMI Size Project Name Rev
A3 IPM41-D3 1.00
Date: Thursday, July 09, 2009 Sheet 35 of 55

5 4 3 2 1
5 4 3 2 1

Note: Azalia Front Audio Header


D Front Side Support MIC&Headphone&Re-tasking Function D

I
AD2
BAW56WPT mx_4r8p0603
2 MIC2_VREF_R I 1 4.7K 2 ARN1A Note:
[34] MIC2_VREF 3
1 MIC2_VREF_L I 3 4.7K 4 ARN1B Follow Intel Front Audio Pin Definition
mx_4r8p0603

I
AD3
BAW56WPT mx_4r8p0603
2 LIN2_VREF_R I 5 6 ARN1C
4.7K
[34] LIN2_VREF 3
1 LIN2_VREF_L I 7 8 ARN1D +3P3V
This connection type of SENSE_B
4.7K
mx_4r8p0603 Color = GREEN just only for HDA front panel,

1
I I
not suit for AC97 Type
AR16
P23 4.7K
I AL1 1 2 120Ohm/100Mhz/0.6A MIC2_L 1 2

2
[34] MIC2_L_C
[34] MIC2_R_C I AL2 1 2 120Ohm/100Mhz/0.6A MIC2_R 3 4 F_AUDIO_DET# [21]
C
[34] LIN2_R_C I AL3 1 2 120Ohm/100Mhz/0.6A LIN2_R 5 6 MIC_JD I 1 20K 2 AR22 1% C
7
[34] LIN2_L_C I AL4 1 2 120Ohm/100Mhz/0.6A LIN2_L 9 10 LIN_JD I 1 39.2K 2 AR21 1% SENSE_B [34,35]
HEADER_2X5P_K8
AR21&AR22 Place near to codec

1
NI

1
I I I I AC23
AC5 AC6 AC7 AC8 0.1UF/16V

2
1

I I I I 100PF/50V 100PF/50V 100PF/50V 100PF/50V Y5V +80-20%

2
AR17 AR18 AR19 AR20 NPO 5% NPO 5% NPO 5% NPO 5%
22K 22K 22K 22K
2

AGND AGND AGND AGND AGND AGND GND

AGND AGND AGND AGND

B B

NI +5V
AC9 SPDIF_OUT
100PF/50V 1
NPO 5%
1 2 I 3 SPDIFO
SPDIF_OUT [34]
4
1

NI HEADER_1X4P_K2
NI AC41
AR23 AC35 150PF/50V
0 Ohm 0.1UF/16V
NI /X/EMI
2

1 2 Y5V +80-20%

8/27 modify
GND
AGND GND

PLACE NEAR FRONT AUDIO HEADER FOR EMI

A A

PEGATRON DT-MB RESTRICTED SECRET


Title : AUDIO CONNECTOR
PEGATRON CORP. Engineer: Wayne Hsieh
Size Project Name Rev
A3 IPM41-D3 1.00G
Date: Thursday, July 09, 2009 Sheet 36 of 55
5 4 3 2 1
5 4 3 2 1

D D

NI
JLPC
+3P3V HEADER_2X10P_K4

CK_33M_TPM 1 2
[5] CK_33M_TPM
LFRAMEn 3
[21,39] LFRAME# PLTRST#
[13,21,39] LRESET# 5 6
LAD3 7 8
[21,39] LAD3 LAD2 [21,39]
9 10 LAD1 [21,39]
LAD0 11 12
+3P3VSB [21,39] LAD0
13 14
15 16 SERIRQ [20,39]
17 18 TPM_CLKRUN#
CLKRUN# [21]
19 20
[21] LPCPD#

CK_33M_TPM

1
NI
VC14
5.6PF/50V

2
NPO 0.25PF
C C
GND
GND

B B

A A

ASUS OEM-DT MB RESTRICTED SECRET


Title : TPM HEADER
PEGATRON CORP. Engineer: Wayne Hsieh
Size Project Name Rev
A3 IPM41-D3 1.00G
Date: Thursday, July 09, 2009 Sheet 37 of 55
5 4 3 2 1
5 4 3 2 1

+5V +12V +VCORE

1
Voltage over 2.048V or less than 0V I
I I I O2U1A
O2R13 O2R14 Please add those divider res if you need to O2R24
22K 56K 4.7K
2
1% 1% monitor the voltage with +5V or +12V

2
100 CPUVCORE CPUFANOUT0 115 CPUFAN_PWM [43]
GP20/CPUFANOUT1 120 CHAFAN_PWM [43]
D +5VIN 99 116 D
VIN0 SYSFANOUT
AUXFANOUT0 7
+12VIN 98 VIN1
97 VIN2
1

I I 96 VIN3
O2R16 O2R15
10K 10K
1% 1% 112 CPUFAN_TACH [43]
2

CPUFANIN0
GP21/CPUFANIN1 119 CHAFAN_TACH [43]

1
I I I SYSFANIN 113
O2C7 O2C8 O2C4 111
0.1UF/16V 0.1UF/16V 0.1UF/16V AUXFANIN0
58

2
GND GND SI/AUXFANIN1

GND GND GND GND GND GND GND GND

+5V +3P3VSB 101 IO_VREF


VREF

1
C5: Please close to pin101 I

6
O2C5
ORN2D ORN1C 0.1UF/16V

2
4.7KOHM 4.7KOHM
Please note: pin94 need have pull-up 5% 5% TRD_CPU_P [7]
C C
res on IDE connector side. NI I

1
I
GND C6: Please close to SIO O2C6
75 103 2200PF/50V

2
[21] RSMRST# RSMRST#/GP51 CPUTIN X7R 10%
94 RSTOUT0# CPUD- 105 TRD_CPU_N [7]

[24,25,32] PCIES_RST# 93 RSTOUT1# I

1
104 O2Q21
SYSTIN PMBS3904 2
90 GP32/RSTOUT2#/SCL NOBOM

1
102 I
E JP2
AUXTIN O2C10 SHORTPIN
+3P3VSB +3P3VSB +5VSB +3P3V +3P3VSB
89 GP33/RSTOUT3#/SDA B 1
2200PF/50V

2
C
88 X7R 10%

2
GP34/RSTOUT4# 3

4
ORN2A ORN1B ORN1A ORN2C ORN1D ORN2B
GND 4.7KOHM 4.7KOHM 4.7KOHM 4.7KOHM 4.7KOHM 4.7KOHM
GND 5% 5% 5% 5% 5% 5%
NI I I NI I NI
+BATT

3
Please note: pin68 need have pull-up
res on power connector side.
1

PSIN#/GP56 68 PWRBTN# [44]


I PSOUT#/GP57 67 SB_PWRBTN# [21]
Please note PIN76: You also used O2R25 64
GP37/SUSC# SLP_S5# [19,21]
1M 73
B this pin as inducder function. SUSB#/GP52 SLP_S3# [21] B
72 PSON# [45]
2

PSON#/GP53
GP35/ATXPGD 87 ATX_PWRGD [45]
PWROK/GP54 71 PWROK [13,21]
CPU_OPEN# 76 92
CASEOPEN# GP30/PWRGD 06/29 NI for Linear, I for Switching power with +3P3VSB by TSL

Pin 117 : During power-on reset, this +3P3VSB +3P3VSB +3P3VSB +3P3V +3P3VSB +3P3VSB
Add inverter circuit

1
pin is pulled down internally and is for +3VSBSW function

1
defined as fan rotation rate is 50%. I
NI I I I NI O2R168
Only CPUFANOUT0 supports. +1P1V_FSB_VTT 10/1 modify O2R33 O2R30 O2R31 O2R32 O2R8 4.7K
109 4.7K 1K 4.7K 4.7K 1K

2
NC1
+3VSBSW [50]

2
Pin108 : from CPU 110 I 3
NC2 O2R169 C I

1
Pin106 : To SB 107 91 1 4.7K 2 1 B O2Q4 NI
+3P3V +3P3V VTT GP31/3VSBSW# PMBS3904 O2C11
PECI_CPU 108 86 E 1UF/10V
[7] PECI_CPU LPC_PME# [21]

2
PECI PME# 2 mx_c0603
106 PECI_SB HM_SMI#/OVT# 5 LPC_SMI# [21]
1

NI NI SIO_SST 114 70 SIO_SUSLED 9/5 modify


O2R5 O2R6 SST GP55/SUSLED(EN_AS) GND GND
1K 1K SR72 2
Only S3
[44] PLED_P 117 FAN_STE/PLED GP36/RESETCON# 69 I 1 0 SYS_RESET# [7,9,21,44]
S0/S1 high S4/S5
2

118 SIO_BEEP
BEEP/SO SIO_BEEP [55]
1
A 19 GP22/SCE Please note: Pin118 is OD pin, please add Please note: pin69 need have pull-up S3 A
a pull-up res when you have used it. res on power connector side.
2 GP23/SCK 0
ASUS OEM-DT MB RESTRICTED SECRET
1

10/1 modify NI Please note: Pin71/Pin92 have


O2R34 I the same timing sequence
680
5%
O2R35
4.7K W83627DHG-A
Title : SIO W83627DHG 1 - 2
02G230362761
PEGATRON CORP. Engineer: Wayne Hsieh
2

83627DHG(C) 02X230362760 C.S W83627DHG-A(C) PQFP128 WINBOND (SORT)


Size Project Name Rev
02G230362761
GND GND C.S W83627DHG-A(C) PQFP128 WINBOND (SORT)
A3 IPM41-D3 1.00G
Date: Thursday, July 09, 2009 Sheet 38 of 55
5 4 3 2 1
5 4 3 2 1

+5V +5V

I
I O2RN1B 3 4
P10 1K

1
I O2RN1A 1 2 I
1K
BOX_HEAD_2X17P_K5 I O2RN1D 7 8 I
1K
1 2 I O2RN1C 5 6 O2R1
3 4
1K
1K O2U1B +3P3VSB
6

2
7 8
D 9 10 DENSEL# 1 61 D
INDEX# DRVDEN0 3VSB
11 12 3 INDEX#
13 14 MTRA# 4 MOA#

1
15 16 DRVA# 6 I
DIR# DSA# O2CB1
17 18 8 DIR#
19 20 STEP# 9 0.1UF/16V

2
WDATA# STEP#
21 22 10 WD#
23 24 WGATE# 11
TRK0# WE#
25 26 13 TRAK0#
27 28 WPT# 14 GND
RDATA# WP#
29 30 15 RDATA#
31 32 HDSEL# 16
DSKCHG# HEAD# +BATT
33 34 17 DSKCHG#

VBAT 74

1
GND I
44 O2CB2
[40] XINIT# INIT# 1UF/10V
43

2
[40] XSLIN# SLIN# mx_c0603
[40] SLCT 31 SLCT
[40] PE 32 PE
[40] BUSY 33 BUSY
34 GND
[40] ACK# ACK#
45 +3P3V
[40] ERROR# ERR#
[40] XAFD# 46 AFD#
[40] XSTB# 47 STB#
3VCC_1 12
3VCC_2 28
C 35 48 C
[40] XPD7 PD7 3VCC_3

1
+3P3V +3P3V +3P3V 36 95 I I I NI
[40] XPD6 PD6 AVCC
37 O2CB3 O2CB4 O2CB5 O2CB6
[40] XPD5 PD5
38 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V
[40] XPD4

2
PD4
1

[40] XPD3 39 PD3


NI NI I [40] XPD2 40 PD2
O2R2 O2R3 O2R4 41
[40] XPD1 PD1
4.7K 4.7K 4.7K 42 GND GND GND GND
[40] XPD0 PD0
2

[21,37] LAD0 27 LAD0 IOCLK 18 CK_48M_SIO [5]


[21,37] LAD1 26 LAD1
[21,37] LAD2 25 LAD2
[21,37] LAD3 24 LAD3

[21,37] LFRAME# 29 LFRAME#


[21] LDRQ# 22 LDRQ#
[13,21,37] LRESET# 30 LRESET#
[5] CK_33M_SIO 21 PCICLK VID0 128
[20,37] SERIRQ 23 SERIRQ VID1 127
VID2 126
[42] KBDATA 63 KDAT/GP26 VID3 125
[42] KBCLK 62 KCLK/GP27 VID4 124
[42] MSDATA 66 MDAT/GP24 VID5 123
[42] MSCLK 65 MCLK/GP25 VID6 122
[20] RST_KB 60 KBRST VID7 121
[20] A20GATE 59 GA20M GP50/WDTO#(EN_GTL) 77
B B
+5V
VID TRAPING -> VID_GTL
1

NI NI NI
O2C1 O2C2 O2C3 GND
0.1UF/16V 12PF/50V 0.1UF/16V VID_GTL VID VOLTAGE
2

2
2

NPO 5%
ORN3A
1KOHM 0 TTL
5% GND GND GND
I 1 VRD10
1

+5V
[41] RXD1 53 SINA/GP63 GP43/SINB/IRRX 82 RXD2 [41] IR_CON
[41] TXD1 54 SOUTA/GP62(PENKBC)GP42/SOUTB/IRTX 83 TXD2 [41] 1
[41] DSR1# 50 DSRA#/GP66 GP46/DSRB# 79 DSR2# [41] NI

1
51 80 3 RXD2 C512
[41] RTS1# RTSA#/GP65(HEFRAS) GP45/RTSB# RTS2# [41]
[41] CTS1# 49 CTSA#/GP67 GP47/CTSB# 78 CTS2# [41] I 4
52 81 5 TXD2 0.1UF/16V
DTR2# [41]

2
[41] DTR1# DTRA#/GP64(PENROM) GP44/DTRB# Y5V +80-20%
[41] RI1# 57 RIA#/GP60 GP40/RIB# 85 RI2# [41] HEADER_1X5P_K2
[41] DCD1# 56 DCDA#/GP61 GP41/DCDB# 84 DCD2# [41]
4

ORN3B ORN3C modify 7/30

1
1KOHM 1KOHM NI GND
5% 5% 20 O2R17
VSS1
I I VSS2 55 680
5%
3

2
A A

GND GND
PORT ADDRESS TRAPING -> HEFRAS ROM TRAPING -> DTR1# KEYBOARD TRAPING -> PENKBC W83627DHG-A GND GND

: During power on reset, it is internal PD : During power on reset, it is internal PD : During power on reset, it is internal PD 83627DHG(C) 02X230362760 ASUS OEM-DT MB RESTRICTED SECRET
X1_0907

RTS1# CONFIG PORT ADDR DTR1# PENROM TXD1 KEYBOARD Title : SIO W83627DHG 2 - 2
02G230362761
PEGATRON CORP. Engineer: Wayne Hsieh
0 0x002E 0 DISABLE 0 DISABLE C.S W83627DHG-A(C) PQFP128 WINBOND (SORT)
Size Project Name Rev
1 0x004E 1 ENABLE 1 ENABLE A3 IPM41-D3 1.00G
Date: Thursday, July 09, 2009 Sheet 39 of 55
5 4 3 2 1
5 4 3 2 1

<< FOR CPC >>


D D

+5V I I
D2 +5V_PRT R1
1SS355PT 2.2K
1 2 1 2
I RN2C I RN4B
5 2.2k 6 SPD0 3 2.2k 4 PARALLEL PORT
1

1
NI I I RN3A I RN4C
CB3 CB4 1 2 SPD1 5 6
2.2k 2.2k
0.1UF/16V 0.01UF/25V I RN3C I RN4D I
2

5 6 SPD2 7 8
X7R 10%
I
2.2k
RN1A I
2.2k
RN2D J50
1 2 SPD3 7 8 D-SUB_25P
2.2k 2.2k
I RN1B I RN3D 26 SIDE_G26
GND GND 3 4 SPD4 7 8
2.2k 2.2k
I RN1C I RN3B SLCT 13
[39] SLCT SLCT
5 6 SPD5 3 4 25
2.2k 2.2k GND8
I RN1D I RN2A PE 12
[39] PE PE
7 8 SPD6 1 2 24
2.2k 2.2k GND7
I RN4A I RN2B BUSY 11
[39] BUSY BUSY
1 2 SPD7 3 4 23
2.2k 2.2k GND6
C ACK# 10 C
[39] ACK# ACK#
22 GND5
I RN5D 7 8 SPD7 9
[39] XPD7 22 SPD7
I RN5A 1 2 21
[39] XPD6 22 GND4
I RN5B 3 4 SPD6 8
[39] XPD5 22 SPD6
I RN5C 5 6 20 28
[39] XPD4 22 GND3
SPD5 7 SPD5 SIDE_G28
19 GND2
SPD4 6 SPD4
18 GND1
I RN6D 7 8 SPD3 5
[39] XPD3 22 SPD3
I RN6B 3 4 SLIN# 17
[39] XPD2 22 SLIN#
I RN7D 7 8 SPD2 4 GND
[39] XPD1 22 SPD2
I RN7A 1 2 PINIT# 16
[39] XPD0 22 PINIT#
SPD1 3 SPD1
ERROR# 15 ERROR#
SPD0 2 SPD0
I RN7B 3 4 AFD# 14
[39] XAFD# 22 AFD#
I RN7C 5 6 STB# 1
[39] XSTB# 22 STB#
I RN6C 5 6
[39] XINIT# 22
I RN6A 1 2 27 SIDE_G27
[39] XSLIN# 22

[39] ERROR#
I C3 2 1 150PF/50V
I C42 2 1 150PF/50V I C43 1 2 150PF/50V I C46 2 1 150PF/50V I C7 2 1 150PF/50V GND
I C45 2 1 150PF/50V I C5 1 2 150PF/50V I C47 2 1 150PF/50V I C13 2 1 150PF/50V
I C8 2 1 150PF/50V I C10 1 2 150PF/50V I C12 2 1 150PF/50V I C17 2 1 150PF/50V
I C9 2 1 150PF/50V I C14 1 2 150PF/50V I C15 2 1 150PF/50V I C16 2 1 150PF/50V
B B

GND GND GND GND

A A

ASUS OEM-DT MB RESTRICTED SECRET


Title : PARALLEL PORT - 2
PEGATRON CORP. Engineer: Wayne Hsieh
Size Project Name Rev
A3 IPM41-D3 1.00G

Date: Thursday, July 09, 2009 Sheet 40 of 55


5 4 3 2 1
5 4 3 2 1

+12V -12V

SERIAL PORT A

3
I

1
D7 I

1
BAT54AW NI D8 NI
CB10 BAT54AW CB9 I
D 0.01UF/25V 0.01UF/25V J53 D

2
X7R 10% X7R 10%

2
I D-SUB_9P

3
+5V 10
U3 SIDE_G10

INTERFACE RS-232 GND GND


20 1 +12V_COM
DCD1# VCC VCC+ DDCD1# DDCD1#
[39] DCD1# 19 RY1 RA1 2 1 DDCD#
DSR1# 18 3 DDSR1# DDSR1# 6
[39] DSR1# RY2 RA2 DDSR#
1

I RXD1 17 4 RRXD1 RRXD1 2


[39] RXD1 RY3 RA3 RRXD
CB11 RTS1# 16 5 RRTS1# RRTS1# 7
[39] RTS1# DA1 DY1 RRTS#
0.1UF/16V TXD1 15 6 TTXD1 TTXD1 3
[39] TXD1 TTXD
2

CTS1# DA2 DY2 CCTS1# CCTS1#


[39] CTS1# 14 RY4 RA4 7 8 CCTS#
DTR1# 13 8 DDTR1# DDTR1# 4
[39] DTR1# DA3 DY3 DDTR#
RI1# 12 9 RRI1 RRI1 9
[39] RI1# RY5 RA5 RRI#
11 10 -12V_COM 5 GND1
GND VCC-
GND

RRI1 I C27 1 2 150PF/50V NPO 5%


+3P3VSB DDTR1# I C28 1 2 150PF/50V NPO 5% 11 SIDE_G11
GND CCTS1# I C29 1 2 150PF/50V NPO 5%
TTXD1 I C31 1 2 150PF/50V NPO 5%
1

RRTS1# I C32 1 2 150PF/50V NPO 5%


I RRXD1 I C33 1 2 150PF/50V NPO 5%
R1154 DDSR1# I C34 1 2 150PF/50V NPO 5%
8.2K DDCD1# I C35 1 2 150PF/50V NPO 5%
2

C [21] RING# I
Q2 I
C
3 PMBS3904 R9 I D10 GND GND
C 4.7K 1 RRI1
B 1 RRI1_B 2 1 RRI1_D 3
2 RRI2#
E
1

2 BAT54CW
1

I I
C30 R8
1000PF/50V 2.2K
2

X7R 10%
2

GND GND GND

SERIAL PORT B
I 090507 modify P53 to P52 for text
P52
B DDCD2# 1 1 2 2 RRXD2 B
TTXD2 3 4 DDTR2#
3 4 DDSR2#
5 5 6 6
RRTS2# 7 8 CCTS2#
RRI2# 7 8
9 9
BOX_HEAD_2X5P_K10
GND
I C70 1 2 150PF/50V NPO 5%
I C71 1 2 150PF/50V NPO 5%
I C72 1 2 150PF/50V NPO 5%
I C73 1 2 150PF/50V NPO 5%

I C74 1 150PF/50V
2 GND NPO 5%
I C75 1 2 150PF/50V NPO 5%
I C76 1 2 150PF/50V NPO 5%
I C77 1 2 150PF/50V NPO 5%

GND
+5V I +12V
U4
INTERFACE RS-232
20 VCC VCC+ 1
DCD2# 19 2 DDCD2#
[39] DCD2# DSR2# RY1 RA1 DDSR2#
[39] DSR2# 18 RY2 RA2 3
1

I RXD2 17 4 RRXD2
A CB12
[39]
[39]
RXD2
RTS2#
RTS2# 16
RY3
DA1
RA3
DY1 5 RRTS2# A
1

0.1UF/16V TXD2 15 6 TTXD2 NI


2

[39] TXD2 CTS2# DA2 DY2 CCTS2# CB13


[39] CTS2# 14 RY4 RA4 7
DTR2# 13 8 DDTR2# 0.01UF/25V
2

[39] DTR2# RI2# DA3 DY3 RRI2#


[39] RI2# 12 RY5 RA5 9 X7R 10%
11 10 -12V_COM
GND VCC-
GND Title : COM Port
GND GND PEGATRON CORP. Engineer: Wayne Hsieh
Size Project Name Rev
A3 IPM41-D3 1.00G
Date: Thursday, July 09, 2009 Sheet 41 of 55
5 4 3 2 1

D D

PS/2 KEYBOARD & MOUSE FOR CPC


I
FF+5V YF2 +5V_KBMS
1.1A/6V

1 2 +5V_KBMS_F

Note:
The +5V_DUAL_USB_B power
trace width must have 40
mils or more FF+5V

I YRN4A 2 1
4.7K
I YRN4B 4 3
4.7K
I YRN4C 6 5
4.7K
I I YRN4D 8 7
4.7K
+5V
J68
FF+5V MINI_DIN_6PX2
PS2_MOUSE
KBPWR CMSDATA
C 10 VCC2 MDATA 7 I YL6 2 1 120Ohm/100Mhz/0.6A MDAT I YRN3C 5 33 6 MSDATA [39]
C
1
I 2 9 GND2 MCLK 11 CMSCLK I YL7 2 1 120Ohm/100Mhz/0.6A MCLK I YRN3A 1 33 2 MSCLK [39]
3 +5VSB
13 SIDE_G13 NC3 8
HEADER_1X3P 14 12
Default as short pin 2-3 SIDE_G14 NC4
PS2_KB
4 1 CKBDATA I YL8 2 1 120Ohm/100Mhz/0.6A KDAT I YRN3D 7 8
VCC1 KDATA 33 KBDATA [39]
KBPWR: 3 5 CKBCLK I YL9 2 1 120Ohm/100Mhz/0.6A KCLK I YRN3B 3 4
GND1 KCLK 33 KBCLK [39]
1-2: +5V
1

I 15 SIDE_G15 NC1 2
2-3: +5VSB YCB2 16 SIDE_G16 NC2 6
KBPWR:23 0.1UF/16V 17
2

SIDE_G17
I
I YC5 1 2 150PF/50V NPO 5%
MINI_JUMPER I YC6 1 2 150PF/50V NPO 5%
GND GND I YC7 1 2 150PF/50V NPO 5%
I YC8 1 2 150PF/50V NPO 5%

GND

B B

A A

ASUS MBRD2_CEC RESTRICTED SECRET


Title : KB & MS FOR CPC
PEGATRON CORP. Engineer: Wayne Hsieh
Size Project Name Rev
A3 IPM41-D3 1.00G

Date: Thursday, July 09, 2009 Sheet 42 of 55

5 4 3 2 1
5 4 3 2 1

CPU FAN
COLOR: WHITE
W/POST
I +3P3V +5V +5V

+12V P70
WAFER_HD_4P

3
1 1

1
2 2
D 3 3 I I I D
4 R1150 D1 R2
4

1
+ 5 4.7K I BAT54CW 1K
NC

1
I NI R3

2
CE1 CB1 150
100uF/16V 0.01UF/25V mx_r0805

2
X7R 10% CPUFAN_PWM_C 2 1 CPUFAN_PWM
CPUFAN_PWM [38]

CFAN_D 1 2 CPUFAN_TACH
CPUFAN_TACH [38]
GND GND GND
I

1
I I R1151
C40 C2 1.5K
100PF/50V 100PF/50V

2
NPO 5% NPO 5%

GND GND

CHASIS FAN
COLOR: WHITE
W/POST
C 7/15 modify part reference I +3P3V +5V +5V C

+12V P8
WAFER_HD_4P

1
1 1

1
2 2 I
3 I I R5
3 R6 D9 1K
4 4
5 4.7K I BAT54CW

2
NC
1

+ R1152

2
1

I NI 150
CE2 CB2 mx_r0805
100uF/16V 0.01UF/25V F_CHAFAN_PWM_C 2 1 F_CHAFAN_PWM
CHAFAN_PWM [38]
2

X7R 10%

F_SFAN_D 1 2 F_CHAFAN_TACH
CHAFAN_TACH [38]
GND GND GND I
R1153
1

I I 1.5K
C41 C4
100PF/50V 100PF/50V
2

NPO 5% NPO 5%

GND GND

B B

A A

ASUS OEM-DT MB RESTRICTED SECRET


Title : 4-PIN FAN CONN
PEGATRON CORP. Engineer: Wayne Hsieh
Size Project Name Rev
A3 IPM41-D3 1.00G

Date: Thursday, July 09, 2009 Sheet 43 of 55


5 4 3 2 1
5 4 3 2 1

INTEL CONTROL PANEL / LED CIRCUITRY +5V_DUAL

D D

1
+3P3VSB
I
R1141
220

1
mx_r0805

2
NI
R1142
1K
NI

2
Q1 NI
3 PMBS3904 R1143
C 1K
B 1 SIO_LED1_G 2 1 PLED_P [38]
E
2

GND

+3P3VSB +5V +3P3VSB


+5V_DUAL
1

1
C NI I I C
R1144 R1145 R1146 I
4.7K 220 4.7K R1147
mx_r0805 I 220
2

2
P5 mx_r0805

2
10/1 modify HEADER_2X5P_K10
HDLED+ 1 2 FP_LED+
3 4 FP_LED- R1156
[27] HD_LED#
R1155 5 6 1 2 I
PWRBTN# [38]
1 2 7 8 Q3 I
[7,9,21,38] SYS_RESET# 100 Ohm 3 PMBS3904 R1149
9

1
100 Ohm 5% C 1K
1

1
I 5% I NI NI NI B 1 SIO_LED2_G 2 1
I PLED_N [21]
C36 I C37 C38 C39 R1148
0.1UF/16V 1000PF/50V 0.1UF/16V 0.1UF/16V 0 E
2

2
mx_r0805 2
X7R 10%

2
GND GND GND
GND GND GND GND GND

B B

FRONT POWER LED COLOR SUPPORT R10 Q2 R6 R11

SINGLE COLOR I NI NI NI

DUAL COLOR NI I I I

A A

ASUS OEM-DT MB RESTRICTED SECRET


Title : FRONT_PANEL
PEGATRON CORP. Engineer: Wayne Hsieh
Size Project Name Rev
A3 IPM41-D3 1.00G
Date: Thursday, July 09, 2009 Sheet 44 of 55
5 4 3 2 1
5 4 3 2 1

ATX POWER_24P SUPPLY CONNECTOR


NOTE: I
ATX_PWRGD internal pull high in PSU P1 +5V -12V +3P3V -5V
+5V +12V +5VSB +5V +3P3V POWER_CON_2X12P

25
D D
1 1 13 I

hold1
+3V1 +3V4 P1R3
NI 2 +3V2 -12V 14
P1R2 3 15 47
8.2K GND1 GND4 P1_PSON#
4 +5V1 PSON# 16 2 1 PSON# [38]
I 5 17
2

P1R4 GND2 GND5


6 +5V2 GND6 18
100 7 19
ATX_PWRGD_C GND3 GND7
[38] ATX_PWRGD 1 2 8 PWR0K -5V 20
9 5VSB +5V3 21
10 +12V1 +5V4 22

hold2
11 +12V2 +5V5 23
12 +3V3 GND8 24

1
I I I I I NI I NI NI I NI
P1C1 P1CB1 P1CB2 P1CB4 P1CB5 P1CB6 P1CB7 P1CE1 P1CB8 P1C2 P1CB3

26
2 1000PF/50V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 1000PF/50V 0.1UF/16V

2
X7R 10% X7R 10%

GND GND GND GND GND GND GND GND GND GND GND GND GND

All of the Caps Around the ATX Power Connector

C C

VRM POWER_4P SUPPLY CONNECTOR


B B

I
P3 +12V_CPU
POWER_CON_2X2P

2 2 4 4
1 1 3 3
NP_NC 5

1
NI NI
P1CB9 P1CB10
0.1UF/16V 0.1UF/16V

2
GND GND GND

A A

ASUS OEM-DT MB RESTRICTED SECRET


Title : ATX POWER
PEGATRON CORP. Engineer: Wayne Hsieh
Size Project Name Rev
A3 IPM41-D3 1.00G
Date: Thursday, July 09, 2009 Sheet 45 of 55
5 4 3 2 1
5 4 3 2 1

+12V_CPU I
I PU1
PR1 RT8857GQW
4.7
mx_r0603
1 2 VRM_VCC_C 31 35
VCC12 BOOT1 VRM_BOOT1_C [47]

1
NI I UGATE1 34 VRM_UGATE1_D [47]
PCB1 PCB2 49
0.1UF/16V 0.47UF/16V GND
33 VRM_PHASE1_C [47]

2
X7R 10% mx_c0603 PHASE1
X7R 10% 32
LGATE1 VRM_LGATE1_D [47]
D D
21 R_ISEN1+_A 2 1
ISP1 ISEN1+_A [47]
GND GND GND

1
I I I
PR12 PC1 PR3
[7] RCVID[0..7]
1KOhm 0.1UF/16V 5.6K

2
mx_r0603 X7R 10% 1%
+VTT_OUT_L +VTT_OUT_R +VTT_OUT_R RCVID0 45 1%
RCVID1 VID0 R_ISEN1-_A
44 VID1 ISN1 20 1 2 ISEN1-_A [47]
RCVID2 43 I
2009/04/30 RCVID3 VID2 PC2
42 VID3
1

1
I I PR7 change to NI I RCVID4 41 0.1UF/16V
PR4 PR5 HR57 RCVID5 VID4 X7R 10%
40 VID5
1K 1K NI 1K RCVID6 39 1 2 GND
PR7 2009/04/30 RCVID7 VID6
38 VID7 BOOT2 27 VRM_BOOT2_C [47]
0 Ohm HR57 from 51ohm change to 1Kohm
2

2
mx_r0603 46 28
[7] VID_SELECT VIDSEL UGATE2 VRM_UGATE2_D [47]
1 2 VRM_PSI#_A 47
[51] VCORE_PSI PSI#
VRM_EN_A 37 29
EN/VTT PHASE2 VRM_PHASE2_C [47]
VRMPWRGD 36
[7,51] VRMPWRGD PWRGD
1

NI LGATE2 30 VRM_LGATE2_D [47]


PC3
0.1UF/16V 18 R_ISEN2+_A 2 1 ISEN2+_A [47]
2

X7R 10% ISP2

1
I I VRM_FB_A 6 I I I
PC4 PR11 FB PR17 PC5 PR9
1

GND NI 1000PF/50V 20KOhm 1KOhm 0.1UF/16V 5.6K

2
PR10 2 1 VRM_COMP1_A 1 2 mx_r0603 X7R 10% 1%
100K X7R 10% NI 1% VRM_COMP_A 5 1%
C 1% PC6 COMP R_ISEN2-_A C
ISN2 19 1 2 ISEN2-_A [47]
0.1UF/16V I
2

I VRM_FB1_A 1 2 I PC8
PC9 X7R 10% PR13 0.1UF/16V
820PF/50V 0 X7R 10%
GND 2 1 VRM_COMP2_A 1 2 1 2 GND
I X7R 10% I
+VCORE NOBOM PR19 PR14 26
PWM3 VRM_PWM3_A [48]
PJP11 100 1K
SHORTPIN 1% 1 2 17 R_ISEN3+_A 2 1
ISP3 ISEN3+_A [48]
1 2 A1
1 2 VRM_VOUT1_A 1%

1
I I I
I I PR21 PC10 PR15
PR107 PR20 1KOhm 0.1UF/16V 5.6K

2
0 0 mx_r0603 X7R 10% 1%
1 2 1 2 VRM_VOUT_A 48 1%
[7] VCC_SENSE VOUT
I 16 R_ISEN3-_A 1 2
ISN3 ISEN3-_A [48]
PR8
1

NI 1.8KOHM I
PC19 NI 1 2 VRM_QR2_A 3 PC11
PC12 1% QR2 VRM_VCC5_A 0.1UF/16V
I 0.1UF/16V I
2

PR108 X7R 10% 120PF/50V PC13 X7R 10%


0 NPO 5% 0.1UF/16V 25 1 2 GND
PWM4
[7] VSS_SENSE 1 2 2 1 1 2
X7R 10% 14
ISP4
I I
NOBOM PR25 PC15 VRM_FBRTN_A 1 FBRTN
1

PJP12 100 NI 0.01UF/25V


SHORTPIN 1% PC14 1 2 VRM_SS_A 4
B A2 120PF/50V X7R 10% SS/EN B
1 2 1 2 I
2

CPU : AN6 NPO 5% PC16


120PF/50V 15
VRM_QR1_A ISN4
I 2 1 2 QR1
GND PR22 GND PR18 NPO 5%
1% 3KOHM 0 Ohm
I mx_r0603 PR16
1 2 VRM_ADJ2_A 1 2 VRM_ADJ1_A 1 2 VRM_ADJ_A 9 ADJ
1

NI I 510 OHM NI
PC18 PC60 1% PC20
0.1UF/16V 680PF/50V 2200PF/50V
I
2

1 2 X7R 10% 06/12 modify by Power team X7R 10%


I X7R 10%
PR29
10K GND I GND 22
mx_r0603 PR31 VRHOT
1 2 200 Ohm 23
3% +VTT_OUT_L VRM_VCC5_A 06/12 modify by Power team 1% TSEN
1 2 VRM_IMAXPSI_A 11 8 VRM_RT_A
IMAXPSI RT
I PR33 10K 1%

1
GND 1 2 VRM_IMAX_A 10 I
IMAX
1

I NIPR35 110KOHM 1% GND1 50 PR38


I I PR37 1 2 VRM_OFS_A 7 51 33K
PC22 PR36 180K OFS GND2 1%
GND3 52
0.1UF/16V 6.8K 1% VRM_VCC5_A 24 53

2
X7R 10% 1% VCC5 GND4
54
2

VRM_IMONFB_A GND5
1 2 1 2 12 IMONFB GND6 55
A GND7 56 A
VRM_IMON_A 13 57
IMON GND8
GND
1

I I I I I I I I
PR40 PR41 PC59 PC23 PC24 PR42 PR30 PC25
180K 820 0.1UF/16V 1UF/16V 1000PF/50V 240K 140OHM 1000PF/50V
2

1% 1% X7R 10% mx_c0603 X7R 10% 1% 1% X7R 10%


X7R 10% PEGATRON DT-MB RESTRICTED
Title SECRET
: VCORE CONTROLLER
2

PEGATRON CORP. Engineer: Wayne Hsieh


GND GND GND GND GND GND GND GND GND GND Size Project Name Rev

06/12 modify by Power team


A3 IPM41-D3 1.00
Date: Thursday, July 09, 2009 Sheet 46 of 55
5 4 3 2 1
5 4 3 2 1

+12V_CPU +12V_VCORE_VIN

I
PL1
0.4UH/25A
1 2

1
I +I +I +I
D PCB3 PCE3 PCE4 PCE5 D
4.7UF/16V 2009/04/30 270UF/16V 270UF/16V 270UF/16V

2
I mx_c1206 delete PCE2

2
I I PC26 NOBOM X7R 20%
PD1 PR44 0.1UF/16V PR45 2D I
BAV70WPT 1 mx_c0603 0 PQ27
1 mx_r0603 X7R 10% mx_r0603_short AOD452
3 1 2 VRM_BOOT1_RC_C 1 2 1 2 VRM_UGR1_D 1 GND GND GND GND
2 G
S
3

1
I
PR46
8.2K +VCORE
[46] VRM_BOOT1_C
I
PL2

2
0.3UH/48A
[46] VRM_UGATE1_D
[46] VRM_PHASE1_C 1 2

1
I NI
PC27 PC28
[46] VRM_LGATE1_D

2
4700PF/50V 680PF/50V

2
mx_c0603 X7R 10% NOBOM NOBOM
X7R 10% PJP1 PJP2
SHORTPIN SHORTPIN

2D I 2D I VRM_SN1_C

1
PQ2 PQ3
C AOD472 AOD472 C
1 1

2
G G I GND
S S
3 3 PR47
1 Ohm
mx_r1206

1
[46] ISEN1+_A

GND GND GND [46] ISEN1-_A

+12V_VCORE_VIN

I
I I PC29 NOBOM

1
PD2 PR48 0.1UF/16V PR49 2D I I
BAV70WPT 1 mx_c0603 0 PQ28 PCB4
1 mx_r0603 X7R 10% mx_r0603_short AOD452 4.7UF/16V

2
3 1 2 VRM_BOOT2_RC_C 1 2 1 2 VRM_UGR2_D 1 mx_c1206
2 G X7R 20%
S
3

1
I GND
PR50
B 8.2K B
[46] VRM_BOOT2_C
I

2
PL3
0.3UH/48A
[46] VRM_UGATE2_D
[46] VRM_PHASE2_C 1 2

1
I NI
PC30 PC31
[46] VRM_LGATE2_D

2
4700PF/50V 680PF/50V

2
mx_c0603 X7R 10% NOBOM NOBOM
X7R 10% PJP4 PJP3
SHORTPIN SHORTPIN
2D I 2D I VRM_SN2_C
PQ5 PQ6

1
AOD472 AOD472
1 1

2
G G I
S S
3 3 PR51 GND
1 Ohm
mx_r1206

1
[46] ISEN2+_A

GND GND GND [46] ISEN2-_A

A A

PEGATRON DT-MB RESTRICTED SECRET


Title : VCORE DRIVER-1
PEGATRON CORP. Engineer: Wayne Hsieh
Size Project Name Rev
A3 IPM41-D3 1.00
Date: Thursday, July 09, 2009 Sheet 47 of 55

5 4 3 2 1
5 4 3 2 1

+12V_CPU +12V_VCORE_VIN

I
I I PC32 NOBOM

1
PD3 PR52 0.1UF/16V PR53 2D I I
BAV70WPT 1 mx_c0603 0 PQ30 PCB5
1 mx_r0603 X7R 10% mx_r0603_short AOD452 4.7UF/16V

2
3 1 2 VRM_BOOT3_RC_C 1 2 1 2 VRM_UGR3_D 1 mx_c1206
2 G X7R 20%
S
3

1
I
D VRM_VCC5_A PR60 D
8.2K
I GND
PU2 I +VCORE

2
I RT9618PS PL4
PR58 VRM_BOOT3_C 1 8 VRM_UG3_D 0.3UH/48A
4.7 BOOT UGATE VRM_PHASE3_C
2 7 1 2
mx_r0603 [46] VRM_PWM3_A 3
PWM PHASE
6
OD# PGND

1
1 2 DRI_VCC3_B 4 5 VRM_LG3_D I NI
VCC LGATE PC33 PC35

2
4700PF/50V 680PF/50V

2
mx_c0603 X7R 10% NOBOM NOBOM

1
I X7R 10% PJP5 PJP6
PC34 SHORTPIN SHORTPIN
0.47UF/16V 2D I 2D I VRM_SN3_C

2
mx_c0603 PQ8 PQ9

1
X7R 10% AOD472 AOD472
1 1

2
G G I
S S
3 3 PR59 GND
1 Ohm
GND GND mx_r1206

1
[46] ISEN3+_A

[46] ISEN3-_A

C GND GND GND C

+VCORE
1

+ NI + NI
PCE6 PCE9
220UF/2V 220UF/2V
BOTTOM BOTTOM
2

B B

GND

+VCORE +VCORE
090515 move from 2009/5/11_D PCE31
1

+I +I +I +I +I + NI
1

1
PCE7 PCE8 PCE10 PCE11 PCE12 PCE31 I I I I I I I I I I I I I I I I I I
PCB6 PCB7 PCB8 PCB9 PCB10 PCB11 PCB12 PCB13 PCB14 PCB15 PCB16 PCB17 PCB18 PCB19 PCB20 PCB21 PCB22 PCB23
22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V
820UF/2.5V

820UF/2.5V

820UF/2.5V

820UF/2.5V

820UF/2.5V

820UF/2.5V
2

2
mx_c1206 mx_c1206 mx_c1206 mx_c1206 mx_c1206 mx_c1206 mx_c1206 mx_c1206 mx_c1206 mx_c1206 mx_c1206 mx_c1206 mx_c1206 mx_c1206 mx_c1206 mx_c1206 mx_c1206 mx_c1206
X5R 10% X5R 10% X5R 10% X5R 10% X5R 10% X5R 10% X5R 10% X5R 10% X5R 10% X5R 10% X5R 10% X5R 10% X5R 10% X5R 10% X5R 10% X5R 10% X5R 10% X5R 10%

A A

PEGATRON DT-MB RESTRICTED SECRET


GND GND
Title : VCORE DRIVER-2
+CPU VCORE OUTPUT CAPs PEGATRON CORP. Engineer: Wayne Hsieh
Size Project Name Rev
A3 IPM41-D3 1.00
Date: Thursday, July 09, 2009 Sheet 48 of 55

5 4 3 2 1
5 4 3 2 1

+1P5V_ICH (2A)
For G41 DDR3 Platform +1P5V_DUAL → +0P75V_VTT_DDR (1A)
+12V +1P5V_DUAL

D +0P75V_VTT_DDR +1P5V_DUAL +5V +1P5V_DUAL D


2

1
I I
PR907 PC903
8.2KOHM 10UF/6.3V

1
mx_c0805 I I I
X5R 10% PU4 PR762 PR57
1

RT9045GSP 0 100KOHM
+1P5V_ICH_GATE_A

9 mx_r0603 1%
GND2
1 8

2
GND VIN NC3
2 GND1 NC2 7
3 REFEN VCNTL 6
4 5 +0P75V_REF_A
2D VOUT NC1
I
PQ29

1
AOD472 +1P5V_ICH I +1P1V_FSB_VTT
+ NI I I I I I I
1 PD902 PCE15 PC81 PC80 PCB29 PCB28 PR105 PC37
G BAT54CW 330UF/6.3V 10UF/6.3V 10UF/6.3V 0.1UF/16V 1UF/16V 100KOHM 1000PF/50V
S

2
3 2 mx_c0805 mx_c0805 mx_c0603 mx_c0603 1% X7R 10%

2
3 X5R 10% X5R 10% X7R 10% X7R 10%
1
1

1
NI + NI I
PCB901 PCE714 PC902
0.1UF/16V 680UF/4V 10UF/6.3V
2

2
X7R 10% mx_c0805 GND GND GND GND GND GND GND GND
2

X5R 10% 2009/04/30


PCE16 from 820uF change to 330uF

GND GND GND


C C

+5VSB → +3P3VSB (1.5A)


Eup 1W
+5VSB ==> +3P3VSB (1.5A)
NO BOM
PU302 NI +3P3VSB
3MM_OPEN_5MIL PL9 +5VSB I
+5VSB 1 1 2 2 10UH PQ10 +3P3VSB
Irat=4A LIN REG, 1085
1 2
B B
3 VIN VOUT 2

ADJ
1

1
NI NI NI NI
PR65 PD21 PC73 PC47 I

1
100KOHM SSM24LPT 10UF/6.3V 10UF/6.3V I PR61 + I

1
NI 1% mx_c1206 mx_c1206 NOBOM PCB30 120 I
PC305 NI X5R 10% X5R 10% PJP15 0.1UF/16V 1% PCE16 PCB31
2

2
0.01UF/25V PU303 SHORTPIN X7R 10% 820UF/6.3V 10UF/6.3V

2
X7R 10% MP1482-C165DS-LF-Z NI NI X5R 10%
2 1 +3P3VSB_BST_C 1 SS 8
+3P3VSB_SS_A GND PR55 PR62 3P3VSB_ADJ mx_c0805

2
+3P3VSB_VCC_C BS +3P3VSB_EN_A 26.1KOHM 0 Ohm
2 IN EN 7
+3P3VSB_SW_C 3 +3P3VSB_COMP_A 1% GND mx_r0603
SW COMP 6 GND GND

1
4 +3P3VSB_FB_A +3P3VSB_FB1_A 2+3P3VSB_FB2_A GND GND
GND1 FB 5 1 2 1

1
NI I
NI PC38 PR63
PC74 0.1UF/16V 200

2
NI NI 1000PF/50V 1%

2
PR56 PC76 X7R 10%
1.8KOHM 0.018UF/16V 2 1
1

NI NI 1% X7R 10%
PC79 PC72 2 1 +3P3VSB_COMP1_A 2 1 GND GND
10UF/6.3V 10UF/6.3V
2

mx_c1206 mx_c1206 NI NI NI NI NI
X5R 10% X5R 10% PC77 PR64 PC78 PC75 PR54
100PF/50V 100KOHM 0.1UF/16V 0.1UF/16V 10KOhm
2

NPO 5% 1% X7R 10% X7R 10% 1%


2 1
2

A A

GND GNDGND GND GND GND GND


PEGATRON DT-MB RESTRICTED SECRET
Title : +0P9V_VTT_DDR_LDO
PEGATRON CORP. Engineer: Wayne Hsieh
Size Project Name Rev
A3 IPM41-D3 1.00G
Date: Thursday, July 09, 2009 Sheet 49 of 55

5 4 3 2 1
5 4 3 2 1

+1P5V_DUAL ==> +1P1V_FSB_VTT (1.5A)


Fixed in 1.2V
change to NI in 9/9

D D
+12V
+3P3VSB
+1P5V_DUAL

1
I
I PU6
PR68 LM358
NI 17.4K 3 A+ + VCC 8
+3P3VSB PR71 1% 1

2
68.1K 2 A- - AO 2D
1%
+1P1V_EN_A 1 2 +1P1V_FSB_VTT_REF_A 5 B+ + AOD452

1
BO 7 +1P1V_FSB_VTT_CON_A 1 PQ12
+1P1V_FSB_VTT 6 B- - G I
NI GND 4 S

1
PR70 I 3

1
1K 3 I PCB36 I
D

1
NI PR73 0.1UF/16V PCB37 I NI
2

2
1

PQ13 10K X7R 10% 0.1UF/16V PC41 PR74

2
NI VTT_SELECT# 1 2N7002 1% X7R 10% 470PF/50V 10K I +1P1V_FSB_VTT

2
PR72 G X7R 10% 1% PR76
2 S

2
62 1K
NI GND GND 1%
2

PR75 3 GND GND +1P1V_FSB_VTT_FB_A


1K C NI
2 1 9/9 DEL
1 2 R_VTT_SEL 1 B PQ14
[7] VTT_SELECT

1
PMBS3904 GND +
E I
C 2 PCE17 C
H--->1.206 1800UF/6.3V

2
L--->1.101
GND
GND

+12V
+5V
+5V_DUAL.....A +5V_DUAL_USB_B......3A
I
PR77
B 8.2K
3
S +5VSB +5V +5V_DUAL_USB B
G
1 2 +5V_DUAL_MAIN_GATE I I
1 PQ15 PQ17
I AOD452 APM9932CKC
PR78 3 D2
1K C 1 8
1 2 +5V_DUAL_MAIN 1 B I S1 D1
PQ16 +5V_DUAL_MAIN_GATE 2 N 7
E PMBS3904 G1 D1
1
1

NI 2 3 6
PC42 +5V_DUAL S2 D2
S3 2200PF/50V +5V_DUAL_AUX_GATE
S0/S1 S0/S5 4 P 5
2

X7R 10% G2 D2

0 GND

1
GND +
+5VSB I NI +5V_DUAL
PR79 PCE19
8.2K D 3 820UF/6.3V

2
1 2 +5V_DUAL_AUX_GATE G I
1 PQ18 3
D
I NTR4502PT1G I
PR80 3 S GND Q10
C 2 1
1K I +5V_DUAL_MAIN_GATE AP2306GN
1 2 +5V_DUAL_AUX 1 B PQ19 G
[38] +3VSBSW 2 S
PMBS3904 +5V
E
1

2
NI
PC43 +5VSB
6/18 modify
A A
2200PF/50V
2

X7R 10%

GND PEGATRON DT-MB RESTRICTED SECRET


GND
Title : +1P1V_FSB_VTT_LDO
PEGATRON CORP. Engineer: Wayne Hsieh
Size Project Name Rev
A3 IPM41-D3 1.00G
Date: Thursday, July 09, 2009 Sheet 50 of 55

5 4 3 2 1
5 4 3 2 1

PSI CIRCUIT VCORE_PSI [46]

D D
NI

1
NI PQ20 3
PR81 C NI
1 2 CPURST_PSI_PQ901 1 B PR82
[6,9,10] CPURESET#
0
5.1K PMBS3904 E

2
1
NI 2
PC44
10UF/6.3V

2
07/15 modify
X5R 10%
mx_c0805
CPU_PSI [7]
GND

+VTT_OUT_L

1
NI
PR83
1K
NI
PQ21 3

2
C
CPURST_PSI_PQ903 1 B
NI
NI PQ22 3 PMBS3904 E
PR84 C 2
C 1 2 CPURST_PSI_PQ902 1 B C
[6,9,10] CPURESET#
1K PMBS3904 E
2

GND GND
8/20 modify to NI

VRMPWRGD CIRCUIT
+3P3V

8
B SRN12D B
+5VSB I 8.2KOHM

7
6

SRN12C
8.2KOHM VRMPWRGD_ICH [5,21]
I
3
D
5

VQ3
2N7002
1
G I
PQ31 3 2 S
C
1 SRN12A 1 B I
[7,46] VRMPWRGD 8.2KOHM2
PMBS3904 E
I
1

NI 2
C44
0.1UF/16V
2

GND GND GND

A A
3 SRN12B
8.2KOHM4

I PEGATRON DT-MB RESTRICTED SECRET


Title : PSI CIRCUIT
PEGATRON CORP. Engineer: Wayne Hsieh
Size Project Name Rev
A3 IPM41-D3 1.00G
Date: Thursday, July 09, 2009 Sheet 51 of 55

5 4 3 2 1
5 4 3 2 1

+5V_DUAL I
PL5
1UH
Irat=14A Irms=5.86A
1 2 +1P5V_DUAL_VIN

+5V_DUAL → +1P5V_DUAL (12A)

1
NI I +I
PCB38 PC45 PCE20
0.1UF/16V 10UF/6.3V 560UF/6.3V

2
X7R 10% mx_c0805

2
X5R 10%
D D

GND VP GND GND


PR28 2D I
0 Ohm PQ23
mx_r0603 AOD452
1 2 1P5V_DUAL_HGR_D 1
G
S
3

1
I
PR86
8.2K

+1P5V_DUAL

2
+5V_DUAL +12V I I
PD6 PL6
BAT54CW 1.2UH I=3.2A / V=18.9mV
2 Irat=29A
3 1P5V_DUAL_PWM_C 1 2
1

1
NOBOM I NI

1
PJP13 PC46 PC66 I +I +I

1
SHORTPIN 4700PF/50V 680PF/50V PC67 PCE33 PCE29

2
1
I 1P5V_DUAL_OCSET1_A 2 1 mx_c0603 X7R 10% 10UF/6.3V 820UF/2.5V 820UF/6.3V NOBOM

2
PR87 X7R 10% mx_c0805 ESR=7mΩ ESR=36mΩ PJP14

2
4.7 X5R 10% SHORTPIN
mx_r0603
2D I +1P5V_DUAL_SN_C
2

2
C PQ24 C
AOD452
1 Rds(on)=14m ohm GND GND GND GND
G
S
3

1
OCP=26A I

1
NI PR89
I PR90 PR101 1
PD7 13KOHM 8.2K mx_r1206
BAT54CW 1%

2
1 2009/04/30

2
3 I PR24 from 22Kohm change to 18.2Kohm
2

I GND GND GND


PC49
0.1UF/16V
mx_c0603
X7R 10%
1 2

I
PU7 PR91 I
APW7120 2KOhm PR6
1P5V_DUAL_BST_C 1 8 1P5V_DUAL_PHASE_C I 1% 0 Ohm
1P5V_DUAL_HG_D BOOT PHASE 1P5V_DUAL_OCSET_A mx_r0603
2 UGATE OCSET 7
3 6 1P5V_DUAL_FB_A 1 2 1P5V_DUAL_FB1_A 1 2 +1P5V_DUAL_FB2_A
B 1P5V_DUAL_LG_D GND FB 1P5V_DUAL_VCC_C B
4 LGATE VCC 5
NI
PC51
1

I 0.47UF/16V
PC50 PR92 mx_c0603
0.47UF/16V 2.1KOHM X7R 10%
2

mx_c0603 1% 2 1
X7R 10%
2

GND GND GND

A A

PEGATRON DT-MB RESTRICTED SECRET


Title : +1P8V_DUAL_SW
PEGATRON CORP. Engineer: Wayne Hsieh
Size Project Name Rev
A3 IPM41-D3 1.00
Date: Thursday, July 09, 2009 Sheet 52 of 55

5 4 3 2 1
5 4 3 2 1

+3P3V
I
PL7
1UH
Irat=14A Irms=5.74A
1 2 +1P1V_VIN

D
+3P3V → +1P1V_CORE (12A) D

1
NI I +I
PCB39 PC69 PCE25
0.1UF/16V 10UF/6.3V 560UF/6.3V

2
X7R 10% mx_c0805 Irms=5700mA

2
X5R 10%

VP
GND PR26 2D I GND GND
0 Ohm PQ25
mx_r0603 AOD452
1 2 1P1V_HG1_D 1
G
S
3

1
I
PR94
8.2K +1P1V_CORE

2
PL8
1.2UH I=2A / V=12mV
Irat=29A
1 2

1
I NI I +I +I
PC53 PC70 PC71 PCE27 PCE28

1
C NOBOM 4700PF/50V 680PF/50V 10UF/6.3V 820UF/2.5V 820UF/6.3V C

2
PJP9 mx_c0603 X7R 10% mx_c0805 ESR=7mΩ ESR=36mΩ NOBOM

2
SHORTPIN X7R 10% X5R 10% PJP10
1P1V_OCSET1_A 2 1 SHORTPIN

2
2D I +1P1V_SN_C
PQ26 GND GND GND GND
AOD452
1
G
S
+12V 3
OCP=26A
2

1
I I I
PR93 PR96 PR97
1

I 13KOHM 8.2K 1
PR95 1% mx_r1206
I 4.7
1

2
PD8 mx_r0603
BAT54CW
2

1
3
2 GND GND GND

I
PC56
0.1UF/16V
mx_c0603
X7R 10%
B B
1 2

I
PU8 I I
APW7120 PR99 PR2
1P1V_BST_C 1 8 1P1V_PHASE_C 806 0 Ohm
1P1V_HG_D BOOT PHASE 1P1V_OCSET_A 1% mx_r0603
2 UGATE OCSET 7
3 6 1P1V_FB_A 2 1 1P1V_FB1_A 1 2 1P1V_FB2_A
1P1V_LG_D GND FB 1P1V_VCC_C
4 LGATE VCC 5

NI
1

+3P3V +5VSB I I PC58


PC57 PR100 0.47UF/16V
0.47UF/16V 1.96K mx_c0603
2

mx_c0603 1% X7R 10%


1

NI X7R 10% 2 1
2

PR39 PR34
1KOhm 845OHM
1%
3 NI
2

GND NI GND C PQ4 GND


SW1_PR34_A 1 B PMBS3904
3 NI
D E
PQ1
2N7002 2
SW1_PR39_A 1
G
2 S 090511 Modified by Power team.
A A

2009/05/04
Avoid 3P3V leakage issue.
PEGATRON DT-MB RESTRICTED SECRET
Title : +1P1V_CORE
GND GND
PEGATRON CORP. Engineer: Wayne Hsieh
Size Project Name Rev
A3 IPM41-D3 1.00G
Date: Thursday, July 09, 2009 Sheet 53 of 55

5 4 3 2 1
5 4 3 2 1

+5V +3P3V +1P1V_CORE +1P5V_DUAL +5VSB +3P3V

8/27 modify
1

1
NI NI NI I I NI NI NI I NI
C53 C61 C54 C55 C56 C62 C57 C58 C59 C60
D 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V D
2

2
X7R 10% X7R 10% X7R 10% X7R 10% X7R 10% X7R 10% X7R 10% X7R 10% X7R 10% X7R 10%

1
8/27 modify
C49 C50 C51 C52
0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V

2
GND GND GND GND GND X7R 10% X7R 10% X7R 10% X7R 10%
NI NI NI NI

AGND +1P5V_DUAL 6/19 modify(near SB)

GND
1

1
NI NI NI NI NI
C63 C64 C65 C66 C67
0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V
2

2
X7R 10% X7R 10% X7R 10% X7R 10% X7R 10%

GND
7/8 EMI modify

GND
C C

SPI Flash SPI_+3VSB +3P3VSB

SPI BIOS ROM - 8Mbit


10/2 modify SPI_+3VSB SPI_+3VSB

B B
1

1
I I
F3R5 F3R6
8.2K 8.2K
SPI_+3VSB
2

2
I
FU2
SPI_CS#_E16 1 8
[21] SPI_CS# CS# VCC
1 2 R_SPI_MISO 2 7 SPI_HOLD#
[21] SPI_MISO FWH_WP# SO HOLD#
3 WP# SCLK 6
I 4 5
F3R8 GND SI

1
15 IC_SCK_8P I
10/06 modify F3CB1
GND 0.1UF/16V

2
[21] SPI_MOSI

[21] SPI_CLK
GND

FU2_flash rom
1 8

2 7
I BIOS
SPI ROM Part Number: 3 6
A 05G001217000
4 5
A
PM25LV040-100PCE

05G001217000
PEGATRON DT-MB RESTRICTED SECRET
Title : SPI 4Mb
PEGATRON CORP. Engineer: Wayne Hsieh
Size Project Name Rev
A3 IPM41-D3 1.00G
Date: Thursday, July 09, 2009 Sheet 54 of 55
5 4 3 2 1

External RTC Circuitry CLEAR CMOS


+3P3VSB BATT_DUAL
I
D20
D 1 D
3 +BATT CMOS DATA
BAT 1 2 R303_D8 2 I
I SW50 1-2 Default
BAT54CW R34
R33 1
1K 2 1 2 2-3 CLEAR
I RTCRST# [21]
1% 3

1
BATT1 20K 1%
3V/220mAh XBT2 HEADER_1X3P

1
BATT_HOLDER I I I
KTS I
I 8/27 modify R35 C18 C19
LITHIUM BATT
SW50:12

2
CR2032
1KOhm 4.7UF/6.3V 1UF/10V

2
5% X5R 10% mx_c0603
8/21 modify to 12

1
GND I mx_c0805 6/21 modify

GND GND GND MINI_JUMPER


Battery Socket

SPEAKER
C
+3P3V +5V SB_PWR C

+5VSB
I=5/(100+40)=35.7mA
2

R39 I
1KOhm R36 P7
I BUZZ
5% 1 2 1 Max 40mA

2
R38 5% SPKR_O 2 I
1

I 1KOhm 100 R18


2 1 mx_r0805 AC_1205G
40Ohm 300 OHM
[38] SIO_BEEP
I 5%

1
1
I I
R37 5% Q9 3 SB_PWR

+
1KOhm PMBS3904 C GREEN
1

2 1 SPKR_B 1 B NI
[21] SPKR
CB99 I
E 0.1UF/16V
2

2
2

GND

GND GND

B B

NOBOM NOBOM NOBOM NOBOM NOBOM NOBOM


H1 H3 H4 H5 H7 H6
SCREWHOLE_160_HP SCREWHOLE_160_HP SCREWHOLE_160_HP SCREWHOLE_160_HP SCREWHOLE_160_HP SCREWHOLE_160_HP

1 GND1 NC 9 1 GND1 NC 9 1 GND1 NC 9 1 GND1 NC 9 1 GND1 NC 9 1 GND1 NC 9


2 GND2 GND8 8 2 GND2 GND8 8 2 GND2 GND8 8 2 GND2 GND8 8 2 GND2 GND8 8 2 GND2 GND8 8
3 GND3 GND7 7 3 GND3 GND7 7 3 GND3 GND7 7 3 GND3 GND7 7 3 GND3 GND7 7 3 GND3 GND7 7
4 GND4 GND6 6 4 GND4 GND6 6 4 GND4 GND6 6 4 GND4 GND6 6 4 GND4 GND6 6 4 GND4 GND6 6
GND5 5 GND5 5 GND5 5 GND5 5 GND5 5 GND5 5

GND GND GND GND AGND AGND GND GND GND GND AGND AGND AGND

A A

PEGATRON DT-MB RESTRICTED SECRET

ONLY FOR SCREW HOLE Title : RTC / CMOS / SPKR


PEGATRON CORP. Engineer: Wayne Hsieh
Size Project Name Rev
A3 IPM41-D3 1.00G
Date: Thursday, July 09, 2009 Sheet 55 of 55
5 4 3 2 1

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