Advance Computer Architecture(CS501) Total marks = 20

Assignment # 02 Deadline Date

Fall 2020 16th December,

2020

Please carefully read the following instructions before attempting the assignment.

RULES FOR MARKING

It should be clear that your assignment would not get any credit if:
 The assignment is submitted after the due date.
 The submitted assignment does not open or the file is corrupt.
 Strict action will be taken if the submitted solution is copied from any other student or the
internet.

You should consult the recommended books to clarify your concepts as handouts are not
sufficient.

You are supposed to submit your assignment in Doc or Docx format.

Any other formats like Scan Images, Pdf, Zip, Rar, Ppt and Bmp, etc will not be accepted.

OBJECTIVE
The objective of this assignment is to increase the learning capabilities of the students about

 Register Transfer Language

 External Falcon-A CPU Interface
 Falcon-A Address Bus and Data Bus

NOTE
No assignment will be accepted after the due date via email in any case (whether it is the case of
load shedding or internet malfunctioning etc.). Hence refrain from uploading assignments in the
last hour of the deadline. It is recommended to upload the solution file at least two days before
its closing date.

If you find any mistake or confusion in the assignment (Question statement), please consult with
your instructor before the deadline. After the deadline, no queries will be entertained in this
regard.

For any query, feel free to email at:

cs501@vu.edu.pk
Question No. 01 10 Marks
Write an RTL description for each of the below given Falcon-A instructions.

Instruction RTL Description

JNZ R1, [25]
SHIFTR R3, R2, 5
LOAD R4, [R1 + 20]
CALL R6, Ah
MUL R2, R3, R1

Note: You must use a sign-extended the constant in the instructions wherever needed.

Question No. 02 10 Marks

Consider the below-given tables. Table 1 shows the contents stored at different memory
addresses. Table 2 shows the contents stored in different registers.

Memory Address Memory Contents Register Register Contents

1530h 45h R[0] AB04h
1531h 90h R[1] 2010h
AB20h 66h R[2] 1520h
AB21h 02h R[3] 0230h
Table 1: Memory Contents Table2: Register Contents

What will the contents of the address bus and data bus after each of the instructions be
executed?

1. LOAD R1, [R0+28]

2. STORE R3, [R2+16]