Timestamp Score NAME REGISTER NUMBER

6/9/2020 17:30:15 9 / 29 EWFSSFSD

6/12/2020 3:50:53 7 / 30 Rty
6/12/2020 6:27:22 29 / 30 K Reethi
6/12/2020 7:30:21 30 / 30 Syed Dadapeer
6/12/2020 8:40:11 10 / 30 Ramu
6/12/2020 8:43:21 25 / 30 C.vishnuteja
6/12/2020 8:43:45 24 / 30 K.pallavi
6/12/2020 9:03:23 29 / 30 A. Uma
6/12/2020 9:10:37 30 / 30 V Lakshmi kanth
6/12/2020 9:15:10 29 / 30 Purnima .MS
6/12/2020 9:15:11 29 / 30 P. MICHAEL JOSHUA
6/12/2020 9:16:29 23 / 30 Shashidar Reddy
6/12/2020 9:17:30 28 / 30 Naveenkumar
6/12/2020 9:18:27 29 / 30 P. Bhavani
6/12/2020 9:22:45 29 / 30 M.Hari
6/12/2020 9:25:29 30 / 30 Thanmai. Yn
6/12/2020 9:28:34 29 / 30 Shaik Dadu
6/12/2020 9:30:33 29 / 30 D Sreelakshmi
6/12/2020 9:31:57 30 / 30 K.Himalaya
6/12/2020 9:32:38 24 / 30 Saqeeb
6/12/2020 9:35:13 30 / 30 Bharath K Reddy
6/12/2020 9:43:59 27 / 30 S.JEELAN BASHA
6/12/2020 9:44:35 29 / 30 N.Thrilokya
6/12/2020 9:47:18 9 / 30 Y. Mohammed ayaan
6/12/2020 9:52:12 30 / 30 ArunKumarS
6/12/2020 9:55:48 30 / 30 Sri harshini
6/12/2020 9:56:04 30 / 30 Sameera sam
6/12/2020 9:56:56 30 / 30 Anusha
6/12/2020 10:00:16 30 / 30 Yelipeta kavya
6/12/2020 10:16:38 30 / 30 R. Manipriya
6/12/2020 10:18:49 14 / 30 KR sreekanth
6/12/2020 10:20:39 30 / 30 S.Sai jagannath
6/12/2020 10:30:40 28 / 30 R.silpa
6/12/2020 10:34:11 30 / 30 Hemanth.D
6/12/2020 10:38:39 30 / 30 B.Amanulla
6/12/2020 10:48:05 30 / 30 AZUBAR ANSERY
6/12/2020 10:48:11 30 / 30 Vaibhav
6/12/2020 10:52:34 29 / 30 C.Priyanka
6/12/2020 10:56:49 30 / 30 Sabavat prashanth kumar naik
6/12/2020 11:02:55 30 / 30 N.R.Silpa
6/12/2020 11:04:37 30 / 30 K.Mamatha(18F31A0528)
6/12/2020 11:05:35 30 / 30 P Uzma
6/12/2020 11:09:07 26 / 30 BS. Nikitha
6/12/2020 11:14:45 29 / 30 k.gowthami
6/12/2020 11:19:18 30 / 30 VATTI MANOHAR (18F31A0529)
6/12/2020 11:19:50 30 / 30 V Aisha Siddiqa
6/12/2020 11:32:37 28 / 30 Lakshmi prathyusha
6/12/2020 11:35:30 28 / 30 K. V. Nikhath khanam
6/12/2020 11:46:33 24 / 30 T.Bhavana
6/12/2020 11:57:29 30 / 30 S Arun Kumar
6/12/2020 12:05:42 30 / 30 Teja Charan
6/12/2020 12:19:52 26 / 30 Divyasree.H
6/12/2020 12:44:47 30 / 30 Sowmya.K.E
6/12/2020 13:05:22 29 / 30 Syed Alibasha
6/12/2020 14:27:07 29 / 30 M. Bhanu prakash reddy
6/12/2020 16:09:42 18 / 30 C rohith kumar
6/12/2020 17:46:42 28 / 30 Sai krishna
1. Which of the following2.To detect that in which3.Key press detection and 4.How many rows and col
a) masking of bits a) we can mask the bits a) the same processes b) rows=16, columns=2
c) checking that whether c) none of the mentionedc) none of the mentionedb) rows=16, columns=2
d) all of the mentioned d) all of the mentioned b) two different works ar d) rows=2, columns=16
d) all of the mentioned d) all of the mentioned b) two different works ar d) rows=2, columns=16
b) ensuring that initially, b) we can rotate the bits b) two different works ar c) rows=16, columns=16
d) all of the mentioned d) all of the mentioned b) two different works ar c) rows=16, columns=16
d) all of the mentioned d) all of the mentioned b) two different works ar d) rows=2, columns=16
d) all of the mentioned d) all of the mentioned b) two different works ar d) rows=2, columns=16
d) all of the mentioned d) all of the mentioned b) two different works ar d) rows=2, columns=16
d) all of the mentioned d) all of the mentioned b) two different works ar d) rows=2, columns=16
d) all of the mentioned d) all of the mentioned b) two different works ar d) rows=2, columns=16
c) checking that whether b) we can rotate the bits d) any of the mentioned d) rows=2, columns=16
d) all of the mentioned d) all of the mentioned d) any of the mentioned d) rows=2, columns=16
d) all of the mentioned d) all of the mentioned b) two different works ar d) rows=2, columns=16
d) all of the mentioned d) all of the mentioned b) two different works ar d) rows=2, columns=16
d) all of the mentioned d) all of the mentioned b) two different works ar d) rows=2, columns=16
d) all of the mentioned d) all of the mentioned b) two different works ar d) rows=2, columns=16
d) all of the mentioned d) all of the mentioned b) two different works ar d) rows=2, columns=16
d) all of the mentioned d) all of the mentioned b) two different works ar d) rows=2, columns=16
d) all of the mentioned b) we can rotate the bits b) two different works ar d) rows=2, columns=16
d) all of the mentioned d) all of the mentioned b) two different works ar d) rows=2, columns=16
d) all of the mentioned d) all of the mentioned b) two different works ar d) rows=2, columns=16
d) all of the mentioned d) all of the mentioned b) two different works ar d) rows=2, columns=16
a) masking of bits c) none of the mentionedb) two different works ar c) rows=16, columns=16
d) all of the mentioned d) all of the mentioned b) two different works ar d) rows=2, columns=16
d) all of the mentioned d) all of the mentioned b) two different works ar d) rows=2, columns=16
d) all of the mentioned d) all of the mentioned b) two different works ar d) rows=2, columns=16
d) all of the mentioned d) all of the mentioned b) two different works ar d) rows=2, columns=16
d) all of the mentioned d) all of the mentioned b) two different works ar d) rows=2, columns=16
d) all of the mentioned d) all of the mentioned b) two different works ar d) rows=2, columns=16
d) all of the mentioned d) all of the mentioned b) two different works ar d) rows=2, columns=16
d) all of the mentioned d) all of the mentioned b) two different works ar d) rows=2, columns=16
d) all of the mentioned d) all of the mentioned b) two different works ar d) rows=2, columns=16
d) all of the mentioned d) all of the mentioned b) two different works ar d) rows=2, columns=16
d) all of the mentioned d) all of the mentioned b) two different works ar d) rows=2, columns=16
d) all of the mentioned d) all of the mentioned b) two different works ar d) rows=2, columns=16
d) all of the mentioned d) all of the mentioned b) two different works ar d) rows=2, columns=16
d) all of the mentioned d) all of the mentioned b) two different works ar d) rows=2, columns=16
d) all of the mentioned d) all of the mentioned b) two different works ar d) rows=2, columns=16
d) all of the mentioned d) all of the mentioned b) two different works ar d) rows=2, columns=16
d) all of the mentioned d) all of the mentioned b) two different works ar d) rows=2, columns=16
d) all of the mentioned d) all of the mentioned b) two different works ar d) rows=2, columns=16
c) checking that whether a) we can mask the bits b) two different works ar d) rows=2, columns=16
d) all of the mentioned d) all of the mentioned b) two different works ar d) rows=2, columns=16
d) all of the mentioned d) all of the mentioned b) two different works ar d) rows=2, columns=16
d) all of the mentioned d) all of the mentioned b) two different works ar d) rows=2, columns=16
d) all of the mentioned d) all of the mentioned b) two different works ar d) rows=2, columns=16
d) all of the mentioned d) all of the mentioned b) two different works ar d) rows=2, columns=16
b) ensuring that initially, b) we can rotate the bits b) two different works ar b) rows=16, columns=2
d) all of the mentioned d) all of the mentioned b) two different works ar d) rows=2, columns=16
d) all of the mentioned d) all of the mentioned b) two different works ar d) rows=2, columns=16
c) checking that whether a) we can mask the bits b) two different works ar d) rows=2, columns=16
d) all of the mentioned d) all of the mentioned b) two different works ar d) rows=2, columns=16
d) all of the mentioned d) all of the mentioned b) two different works ar d) rows=2, columns=16
d) all of the mentioned d) all of the mentioned b) two different works ar d) rows=2, columns=16
c) checking that whether d) all of the mentioned b) two different works ar d) rows=2, columns=16
d) all of the mentioned d) all of the mentioned b) two different works ar d) rows=2, columns=16
5.How many data lines a6.Which instruction is use7.Which factors indicate 8.What is the purpose of bla
c) 1 b) 0x0c b. Analog-to-digital conv c. A & B
b) 8 a) 0x08 c. Both a & b c. A & B
b) 8 c) 0x80 c. Both a & b a. B & C
b) 8 c) 0x80 c. Both a & b a. B & C
b) 8 b) 0x0c b. Analog-to-digital conv b. A & D
b) 8 c) 0x80 c. Both a & b b. A & D
b) 8 b) 0x0c c. Both a & b a. B & C
b) 8 c) 0x80 c. Both a & b a. B & C
b) 8 c) 0x80 c. Both a & b a. B & C
b) 8 c) 0x80 c. Both a & b a. B & C
b) 8 c) 0x80 c. Both a & b a. B & C
b) 8 c) 0x80 a. Instantaneous variationa. B & C
b) 8 c) 0x80 b. Analog-to-digital conv a. B & C
b) 8 c) 0x80 c. Both a & b a. B & C
b) 8 c) 0x80 c. Both a & b a. B & C
b) 8 c) 0x80 c. Both a & b a. B & C
b) 8 c) 0x80 c. Both a & b a. B & C
b) 8 c) 0x80 c. Both a & b a. B & C
b) 8 c) 0x80 c. Both a & b a. B & C
b) 8 a) 0x08 c. Both a & b c. A & B
b) 8 c) 0x80 c. Both a & b a. B & C
b) 8 c) 0x80 c. Both a & b a. B & C
b) 8 c) 0x80 c. Both a & b a. B & C
c) 1 c) 0x80 a. Instantaneous variationb. A & D
b) 8 c) 0x80 c. Both a & b a. B & C
b) 8 c) 0x80 c. Both a & b a. B & C
b) 8 c) 0x80 c. Both a & b a. B & C
b) 8 c) 0x80 c. Both a & b a. B & C
b) 8 c) 0x80 c. Both a & b a. B & C
b) 8 c) 0x80 c. Both a & b a. B & C
b) 8 c) 0x80 b. Analog-to-digital conv c. A & B
b) 8 c) 0x80 c. Both a & b a. B & C
b) 8 c) 0x80 c. Both a & b a. B & C
b) 8 c) 0x80 c. Both a & b a. B & C
b) 8 c) 0x80 c. Both a & b a. B & C
b) 8 c) 0x80 c. Both a & b a. B & C
b) 8 c) 0x80 c. Both a & b a. B & C
b) 8 c) 0x80 c. Both a & b a. B & C
b) 8 c) 0x80 c. Both a & b a. B & C
b) 8 c) 0x80 c. Both a & b a. B & C
b) 8 c) 0x80 c. Both a & b a. B & C
b) 8 c) 0x80 c. Both a & b a. B & C
b) 8 a) 0x08 c. Both a & b a. B & C
b) 8 c) 0x80 c. Both a & b a. B & C
b) 8 c) 0x80 c. Both a & b a. B & C
b) 8 c) 0x80 c. Both a & b a. B & C
b) 8 c) 0x80 c. Both a & b c. A & B
b) 8 c) 0x80 c. Both a & b a. B & C
b) 8 a) 0x08 b. Analog-to-digital conv b. A & D
b) 8 c) 0x80 c. Both a & b a. B & C
b) 8 c) 0x80 c. Both a & b a. B & C
b) 8 c) 0x80 c. Both a & b c. A & B
b) 8 c) 0x80 c. Both a & b a. B & C
b) 8 c) 0x80 c. Both a & b a. B & C
b) 8 c) 0x80 c. Both a & b a. B & C
b) 8 c) 0x80 b. Analog-to-digital conv a. B & C
b) 8 c) 0x80 c. Both a & b a. B & C
9. What does the RAM lo10.What do you mean by11.What
m is the bit size o 12.Name the architecture
a. 7-segment code for the b) Distance between 2 trb) 4-bit b) Harvard Architecture w
c. Display of select code d) Distance between 2 pic) 16-bit c) Van- Neumann Architec
a. 7-segment code for the b) Distance between 2 trc) 16-bit b) Harvard Architecture w
a. 7-segment code for the b) Distance between 2 tra) 8-bit b) Harvard Architecture w
c. Display of select code c) Size of a controller b) 4-bit c) Van- Neumann Architec
c. Display of select code b) Distance between 2 tra) 8-bit b) Harvard Architecture w
b. 7-segment code for the b) Distance between 2 tra) 8-bit b) Harvard Architecture w
a. 7-segment code for the b) Distance between 2 trb) 4-bit b) Harvard Architecture w
a. 7-segment code for the b) Distance between 2 tra) 8-bit b) Harvard Architecture w
a. 7-segment code for the b) Distance between 2 tra) 8-bit b) Harvard Architecture w
a. 7-segment code for the b) Distance between 2 tra) 8-bit b) Harvard Architecture w
c. Display of select code b) Distance between 2 tra) 8-bit b) Harvard Architecture w
a. 7-segment code for the b) Distance between 2 tra) 8-bit b) Harvard Architecture w
a. 7-segment code for the b) Distance between 2 tra) 8-bit b) Harvard Architecture w
a. 7-segment code for the b) Distance between 2 tra) 8-bit b) Harvard Architecture w
a. 7-segment code for the b) Distance between 2 tra) 8-bit b) Harvard Architecture w
a. 7-segment code for the b) Distance between 2 tra) 8-bit b) Harvard Architecture w
a. 7-segment code for the b) Distance between 2 tra) 8-bit b) Harvard Architecture w
a. 7-segment code for the b) Distance between 2 tra) 8-bit b) Harvard Architecture w
b. 7-segment code for the b) Distance between 2 tra) 8-bit b) Harvard Architecture w
a. 7-segment code for the b) Distance between 2 tra) 8-bit b) Harvard Architecture w
a. 7-segment code for the b) Distance between 2 tra) 8-bit b) Harvard Architecture w
a. 7-segment code for the b) Distance between 2 tra) 8-bit c) Van- Neumann Architec
a. 7-segment code for the d) Distance between 2 pic) 16-bit b) Harvard Architecture w
a. 7-segment code for the b) Distance between 2 tra) 8-bit b) Harvard Architecture w
a. 7-segment code for the b) Distance between 2 tra) 8-bit b) Harvard Architecture w
a. 7-segment code for the b) Distance between 2 tra) 8-bit b) Harvard Architecture w
a. 7-segment code for the b) Distance between 2 tra) 8-bit b) Harvard Architecture w
a. 7-segment code for the b) Distance between 2 tra) 8-bit b) Harvard Architecture w
a. 7-segment code for the b) Distance between 2 tra) 8-bit b) Harvard Architecture w
c. Display of select code b) Distance between 2 tra) 8-bit c) Van- Neumann Architec
a. 7-segment code for the b) Distance between 2 tra) 8-bit b) Harvard Architecture w
a. 7-segment code for the b) Distance between 2 trb) 4-bit c) Van- Neumann Architec
a. 7-segment code for the b) Distance between 2 tra) 8-bit b) Harvard Architecture w
a. 7-segment code for the b) Distance between 2 tra) 8-bit b) Harvard Architecture w
a. 7-segment code for the b) Distance between 2 tra) 8-bit b) Harvard Architecture w
a. 7-segment code for the b) Distance between 2 tra) 8-bit b) Harvard Architecture w
a. 7-segment code for the b) Distance between 2 tra) 8-bit b) Harvard Architecture w
a. 7-segment code for the b) Distance between 2 tra) 8-bit b) Harvard Architecture w
a. 7-segment code for the b) Distance between 2 tra) 8-bit b) Harvard Architecture w
a. 7-segment code for the
b) Distance between 2 tra) 8-bit b) Harvard Architecture w
a. 7-segment code for the
b) Distance between 2 tra) 8-bit b) Harvard Architecture w
a. 7-segment code for the
b) Distance between 2 trc) 16-bit b) Harvard Architecture w
a. 7-segment code for the
b) Distance between 2 tra) 8-bit b) Harvard Architecture w
a. 7-segment code for the
b) Distance between 2 tra) 8-bit b) Harvard Architecture w
a. 7-segment code for the
b) Distance between 2 tra) 8-bit b) Harvard Architecture w
a. 7-segment code for the
b) Distance between 2 tra) 8-bit b) Harvard Architecture w
a. 7-segment code for the
b) Distance between 2 tra) 8-bit b) Harvard Architecture w
a. 7-segment code for the
b) Distance between 2 tra) 8-bit b) Harvard Architecture w
a. 7-segment code for the
b) Distance between 2 tra) 8-bit b) Harvard Architecture w
a. 7-segment code for the
b) Distance between 2 tra) 8-bit b) Harvard Architecture w
a. 7-segment code for the
b) Distance between 2 tra) 8-bit b) Harvard Architecture w
a. 7-segment code for the
b) Distance between 2 tra) 8-bit b) Harvard Architecture w
a. 7-segment code for the
d) Distance between 2 pia) 8-bit b) Harvard Architecture w
a. 7-segment code for the
b) Distance between 2 tra) 8-bit b) Harvard Architecture w
a. 7-segment code for the
b) Distance between 2 tra) 8-bit a) Van- Neumann Architec
a. 7-segment code for the
b) Distance between 2 tra) 8-bit b) Harvard Architecture w
13.Number of I/O ports i 14.Is ROM is used for st 15.SCON in serial port is16.Program counter stor
b) 4 ports a) True d) Controlling and transfec) Data of the before ex
d) 4 ports with last port a) True c) Controlling b) Address of the next in
b) 4 ports b) False c) Controlling b) Address of the next in
b) 4 ports b) False c) Controlling b) Address of the next in
a) 3 ports a) True b) Receiving data b) Address of the next in
b) 4 ports b) False c) Controlling b) Address of the next in
b) 4 ports b) False c) Controlling a) Address of before inst
b) 4 ports b) False c) Controlling b) Address of the next in
b) 4 ports b) False c) Controlling b) Address of the next in
b) 4 ports b) False c) Controlling b) Address of the next in
b) 4 ports b) False c) Controlling b) Address of the next in
b) 4 ports a) True c) Controlling b) Address of the next in
b) 4 ports b) False c) Controlling b) Address of the next in
b) 4 ports b) False c) Controlling b) Address of the next in
b) 4 ports b) False c) Controlling b) Address of the next in
b) 4 ports b) False c) Controlling b) Address of the next in
b) 4 ports b) False c) Controlling b) Address of the next in
b) 4 ports b) False c) Controlling b) Address of the next in
b) 4 ports b) False c) Controlling b) Address of the next in
b) 4 ports a) True c) Controlling b) Address of the next in
b) 4 ports b) False c) Controlling b) Address of the next in
b) 4 ports a) True c) Controlling b) Address of the next in
b) 4 ports b) False c) Controlling b) Address of the next in
c) 5 ports b) False b) Receiving data c) Data of the before ex
b) 4 ports b) False c) Controlling b) Address of the next in
b) 4 ports b) False c) Controlling b) Address of the next in
b) 4 ports b) False c) Controlling b) Address of the next in
b) 4 ports b) False c) Controlling b) Address of the next in
b) 4 ports b) False c) Controlling b) Address of the next in
b) 4 ports b) False c) Controlling b) Address of the next in
a) 3 ports a) True c) Controlling a) Address of before inst
b) 4 ports b) False c) Controlling b) Address of the next in
b) 4 ports b) False c) Controlling b) Address of the next in
b) 4 ports b) False c) Controlling b) Address of the next in
b) 4 ports b) False c) Controlling b) Address of the next in
b) 4 ports b) False c) Controlling b) Address of the next in
b) 4 ports b) False c) Controlling b) Address of the next in
b) 4 ports b) False c) Controlling b) Address of the next in
b) 4 ports b) False c) Controlling b) Address of the next in
b) 4 ports b) False c) Controlling b) Address of the next in
b) 4 ports b) False c) Controlling b) Address of the next in
b) 4 ports b) False c) Controlling b) Address of the next in
b) 4 ports b) False c) Controlling b) Address of the next in
b) 4 ports b) False c) Controlling b) Address of the next in
b) 4 ports b) False c) Controlling b) Address of the next in
b) 4 ports b) False c) Controlling b) Address of the next in
b) 4 ports b) False c) Controlling b) Address of the next in
b) 4 ports b) False c) Controlling b) Address of the next in
b) 4 ports b) False c) Controlling b) Address of the next in
b) 4 ports b) False c) Controlling b) Address of the next in
b) 4 ports b) False c) Controlling b) Address of the next in
b) 4 ports b) False c) Controlling b) Address of the next in
b) 4 ports b) False c) Controlling b) Address of the next in
b) 4 ports b) False c) Controlling b) Address of the next in
b) 4 ports b) False c) Controlling b) Address of the next in
b) 4 ports a) True c) Controlling b) Address of the next in
a) 3 ports a) True c) Controlling b) Address of the next in
17.Auxiliary carry is set 18.The use of Address La
19.Which pin provides a 20.External Access is u
b) When carry is genera a) True d) Pin 9 d) Memory interfacing
c) When carry is genera a) True b) Pin 8 a) Peripherals
a) When carry is generata) True d) Pin 9 d) Memory interfacing
a) When carry is generata) True d) Pin 9 d) Memory interfacing
b) When carry is genera a) True c) Pin 11 c) ALE
b) When carry is genera a) True d) Pin 9 c) ALE
a) When carry is generata) True c) Pin 11 d) Memory interfacing
a) When carry is generata) True d) Pin 9 d) Memory interfacing
a) When carry is generata) True d) Pin 9 d) Memory interfacing
a) When carry is generata) True d) Pin 9 d) Memory interfacing
a) When carry is generata) True d) Pin 9 d) Memory interfacing
a) When carry is generata) True d) Pin 9 d) Memory interfacing
a) When carry is generata) True d) Pin 9 d) Memory interfacing
a) When carry is generata) True d) Pin 9 d) Memory interfacing
a) When carry is generata) True d) Pin 9 d) Memory interfacing
a) When carry is generata) True d) Pin 9 d) Memory interfacing
a) When carry is generata) True d) Pin 9 d) Memory interfacing
a) When carry is generata) True d) Pin 9 d) Memory interfacing
a) When carry is generata) True d) Pin 9 d) Memory interfacing
a) When carry is generata) True d) Pin 9 d) Memory interfacing
a) When carry is generata) True d) Pin 9 d) Memory interfacing
a) When carry is generata) True d) Pin 9 d) Memory interfacing
a) When carry is generata) True d) Pin 9 d) Memory interfacing
c) When carry is genera a) True d) Pin 9 a) Peripherals
a) When carry is generata) True d) Pin 9 d) Memory interfacing
a) When carry is generata) True d) Pin 9 d) Memory interfacing
a) When carry is generata) True d) Pin 9 d) Memory interfacing
a) When carry is generata) True d) Pin 9 d) Memory interfacing
a) When carry is generata) True d) Pin 9 d) Memory interfacing
a) When carry is generata) True d) Pin 9 d) Memory interfacing
a) When carry is generata) True a) Pin 1 a) Peripherals
a) When carry is generata) True d) Pin 9 d) Memory interfacing
a) When carry is generata) True d) Pin 9 d) Memory interfacing
a) When carry is generata) True d) Pin 9 d) Memory interfacing
a) When carry is generata) True d) Pin 9 d) Memory interfacing
a) When carry is generata) True d) Pin 9 d) Memory interfacing
a) When carry is generata) True d) Pin 9 d) Memory interfacing
a) When carry is generata) True d) Pin 9 d) Memory interfacing
a) When carry is generata) True d) Pin 9 d) Memory interfacing
a) When carry is generata) True d) Pin 9 d) Memory interfacing
a) When carry is generata) True d) Pin 9 d) Memory interfacing
a) When carry is generata) True d) Pin 9 d) Memory interfacing
a) When carry is generata) True d) Pin 9 d) Memory interfacing
a) When carry is generata) True d) Pin 9 d) Memory interfacing
a) When carry is generata) True d) Pin 9 d) Memory interfacing
a) When carry is generata) True d) Pin 9 d) Memory interfacing
a) When carry is generatb) False d) Pin 9 d) Memory interfacing
a) When carry is generata) True d) Pin 9 d) Memory interfacing
a) When carry is generata) True d) Pin 9 d) Memory interfacing
a) When carry is generata) True d) Pin 9 d) Memory interfacing
a) When carry is generata) True d) Pin 9 d) Memory interfacing
a) When carry is generata) True d) Pin 9 b) Power supply
a) When carry is generata) True d) Pin 9 d) Memory interfacing
a) When carry is generata) True d) Pin 9 d) Memory interfacing
a) When carry is generata) True d) Pin 9 d) Memory interfacing
b) When carry is genera a) True c) Pin 11 d) Memory interfacing
a) When carry is generata) True d) Pin 9 d) Memory interfacing
21.What is the address 22.How many interrupts ar
23.Timer 0 is a ________24.8051 series of microc
d) 70h to 80h d) 5 b) 8-bit b) Philips
b) 00h to ffh d) 5 b) 8-bit d) None of the mentione
c) 80h to ffh d) 5 c) 16-bit d) None of the mentione
c) 80h to ffh d) 5 c) 16-bit d) None of the mentione
c) 80h to ffh b) 6 d) 10-bit d) None of the mentione
c) 80h to ffh d) 5 c) 16-bit d) None of the mentione
c) 80h to ffh d) 5 c) 16-bit c) Atmel & Philips
c) 80h to ffh d) 5 c) 16-bit d) None of the mentione
c) 80h to ffh d) 5 c) 16-bit d) None of the mentione
c) 80h to ffh d) 5 c) 16-bit c) Atmel & Philips
c) 80h to ffh d) 5 c) 16-bit c) Atmel & Philips
c) 80h to ffh d) 5 c) 16-bit c) Atmel & Philips
c) 80h to ffh d) 5 c) 16-bit d) None of the mentione
c) 80h to ffh d) 5 c) 16-bit c) Atmel & Philips
c) 80h to ffh d) 5 c) 16-bit c) Atmel & Philips
c) 80h to ffh d) 5 c) 16-bit d) None of the mentione
c) 80h to ffh d) 5 c) 16-bit d) None of the mentione
c) 80h to ffh d) 5 c) 16-bit d) None of the mentione
c) 80h to ffh d) 5 c) 16-bit d) None of the mentione
c) 80h to ffh d) 5 c) 16-bit d) None of the mentione
c) 80h to ffh d) 5 c) 16-bit d) None of the mentione
c) 80h to ffh d) 5 c) 16-bit c) Atmel & Philips
c) 80h to ffh d) 5 c) 16-bit d) None of the mentione
c) 80h to ffh c) 4 b) 8-bit a) Atmel
c) 80h to ffh d) 5 c) 16-bit d) None of the mentione
c) 80h to ffh d) 5 c) 16-bit d) None of the mentione
c) 80h to ffh d) 5 c) 16-bit d) None of the mentione
c) 80h to ffh d) 5 c) 16-bit d) None of the mentione
c) 80h to ffh d) 5 c) 16-bit d) None of the mentione
c) 80h to ffh d) 5 c) 16-bit d) None of the mentione
c) 80h to ffh b) 6 a) 32-bit c) Atmel & Philips
c) 80h to ffh d) 5 c) 16-bit d) None of the mentione
c) 80h to ffh d) 5 c) 16-bit d) None of the mentione
c) 80h to ffh d) 5 c) 16-bit d) None of the mentione
c) 80h to ffh d) 5 c) 16-bit d) None of the mentione
c) 80h to ffh d) 5 c) 16-bit d) None of the mentione
c) 80h to ffh d) 5 c) 16-bit d) None of the mentione
c) 80h to ffh d) 5 b) 8-bit d) None of the mentione
c) 80h to ffh d) 5 c) 16-bit d) None of the mentione
c) 80h to ffh d) 5 c) 16-bit d) None of the mentione
c) 80h to ffh d) 5 c) 16-bit d) None of the mentione
c) 80h to ffh d) 5 c) 16-bit d) None of the mentione
c) 80h to ffh d) 5 c) 16-bit d) None of the mentione
c) 80h to ffh d) 5 c) 16-bit d) None of the mentione
c) 80h to ffh d) 5 c) 16-bit d) None of the mentione
c) 80h to ffh d) 5 c) 16-bit d) None of the mentione
c) 80h to ffh d) 5 c) 16-bit d) None of the mentione
c) 80h to ffh d) 5 c) 16-bit c) Atmel & Philips
c) 80h to ffh d) 5 c) 16-bit d) None of the mentione
c) 80h to ffh d) 5 c) 16-bit d) None of the mentione
c) 80h to ffh d) 5 c) 16-bit d) None of the mentione
c) 80h to ffh d) 5 c) 16-bit d) None of the mentione
c) 80h to ffh d) 5 c) 16-bit d) None of the mentione
c) 80h to ffh d) 5 c) 16-bit d) None of the mentione
c) 80h to ffh d) 5 c) 16-bit d) None of the mentione
c) 80h to ffh d) 5 b) 8-bit c) Atmel & Philips
c) 80h to ffh d) 5 c) 16-bit d) None of the mentione
25.8051 series has how m
26.When 8051 wakes up27.When
t the microcontroll
28.If we push data onto t
d) 0 d) PSW a) PSW b) decreases with every
d) 0 d) PSW d) PC d) none of the mentioned
a) 2 c) PC a) PSW a) increases with every
a) 2 c) PC a) PSW a) increases with every
b) 3 c) PC a) PSW a) increases with every
a) 2 c) PC a) PSW a) increases with every
a) 2 c) PC a) PSW a) increases with every
a) 2 c) PC a) PSW a) increases with every
a) 2 c) PC a) PSW a) increases with every
a) 2 c) PC a) PSW a) increases with every
a) 2 c) PC a) PSW a) increases with every
a) 2 c) PC a) PSW a) increases with every
a) 2 c) PC a) PSW a) increases with every
a) 2 c) PC a) PSW a) increases with every
a) 2 c) PC a) PSW a) increases with every
a) 2 c) PC a) PSW a) increases with every
a) 2 a) DPTR a) PSW a) increases with every
a) 2 c) PC a) PSW a) increases with every
a) 2 c) PC a) PSW a) increases with every
d) 0 c) PC a) PSW a) increases with every
a) 2 c) PC a) PSW a) increases with every
a) 2 c) PC a) PSW c) increases & decreases
a) 2 c) PC a) PSW a) increases with every
d) 0 c) PC b) SP b) decreases with every
a) 2 c) PC a) PSW a) increases with every
a) 2 c) PC a) PSW a) increases with every
a) 2 c) PC a) PSW a) increases with every
a) 2 c) PC a) PSW a) increases with every
a) 2 c) PC a) PSW a) increases with every
a) 2 c) PC a) PSW a) increases with every
d) 0 c) PC a) PSW c) increases & decreases
a) 2 c) PC a) PSW a) increases with every
a) 2 c) PC a) PSW a) increases with every
a) 2 c) PC a) PSW a) increases with every
a) 2 c) PC a) PSW a) increases with every
a) 2 c) PC a) PSW a) increases with every
a) 2 c) PC a) PSW a) increases with every
a) 2 c) PC a) PSW a) increases with every
a) 2 c) PC a) PSW a) increases with every
a) 2 c) PC a) PSW a) increases with every
a) 2 c) PC a) PSW a) increases with every
a) 2 c) PC a) PSW a) increases with every
a) 2 c) PC a) PSW a) increases with every
a) 2 c) PC a) PSW a) increases with every
a) 2 c) PC a) PSW a) increases with every
a) 2 c) PC a) PSW a) increases with every
a) 2 c) PC a) PSW a) increases with every
a) 2 c) PC a) PSW a) increases with every
a) 2 c) PC a) PSW a) increases with every
a) 2 c) PC a) PSW a) increases with every
a) 2 c) PC a) PSW a) increases with every
a) 2 c) PC a) PSW a) increases with every
a) 2 c) PC a) PSW a) increases with every
a) 2 c) PC a) PSW a) increases with every
a) 2 c) PC a) PSW a) increases with every
b) 3 b) SP c) DPTR a) increases with every
a) 2 c) PC a) PSW a) increases with every
29.On power up, the 8051
30.How many bytes of bit addressable memory is present in 8051 based microcontrollers?
a) 00-2F a) 8 bytes
d) 00-0F d) 128 bytes
b) 00-07 c) 16 bytes
b) 00-07 c) 16 bytes
b) 00-07 a) 8 bytes
b) 00-07 c) 16 bytes
a) 00-2F c) 16 bytes
b) 00-07 c) 16 bytes
b) 00-07 c) 16 bytes
b) 00-07 c) 16 bytes
b) 00-07 c) 16 bytes
b) 00-07 c) 16 bytes
b) 00-07 c) 16 bytes
b) 00-07 c) 16 bytes
b) 00-07 c) 16 bytes
b) 00-07 c) 16 bytes
b) 00-07 c) 16 bytes
b) 00-07 b) 32 bytes
b) 00-07 c) 16 bytes
b) 00-07 c) 16 bytes
b) 00-07 c) 16 bytes
b) 00-07 c) 16 bytes
b) 00-07 c) 16 bytes
c) 00-7F b) 32 bytes
b) 00-07 c) 16 bytes
b) 00-07 c) 16 bytes
b) 00-07 c) 16 bytes
b) 00-07 c) 16 bytes
b) 00-07 c) 16 bytes
b) 00-07 c) 16 bytes
c) 00-7F b) 32 bytes
b) 00-07 c) 16 bytes
b) 00-07 c) 16 bytes
b) 00-07 c) 16 bytes
b) 00-07 c) 16 bytes
b) 00-07 c) 16 bytes
b) 00-07 c) 16 bytes
b) 00-07 c) 16 bytes
b) 00-07 c) 16 bytes
b) 00-07 c) 16 bytes
b) 00-07 c) 16 bytes
b) 00-07 c) 16 bytes
b) 00-07 c) 16 bytes
b) 00-07 d) 128 bytes
b) 00-07 c) 16 bytes
b) 00-07 c) 16 bytes
b) 00-07 c) 16 bytes
c) 00-7F c) 16 bytes
b) 00-07 c) 16 bytes
b) 00-07 c) 16 bytes
b) 00-07 c) 16 bytes
b) 00-07 c) 16 bytes
b) 00-07 c) 16 bytes
b) 00-07 c) 16 bytes
a) 00-2F c) 16 bytes
a) 00-2F c) 16 bytes
b) 00-07 c) 16 bytes
051 based microcontrollers?