A

REVISIONS

REV DESCRIPTION DATE APPROVED

A BETA 23-Jan-2003

07-October-2003
The TMS320C6713DSK design is based on
TMS320C6713 device device data sheet
SPRS186B and errata SPRZ173E. This
schematic is subject to change without notification.
Spectrum Digital Inc. assumes no liability for
applications assistance, customer product design
or infringement of patents described herein.

DWN DATE
REVISION STATUS OF SHEETS
CHK DATE
REV
ENGR DATE SPECTRUM DIGITAL INCORPORATED
SH
ENGR-MGR DATE
REV A B A A A A A
QA DATE Title
SH 8 9 10 11 12 13 14
MFG DATE TMS320C6713 DSK
REV C C A C A A B NEXT ASSY USED ON Size Document Number Rev
RLSE DATE B C
SH 1 2 3 4 5 6 7 APPLICATION 506732
Date: Monday, November 24, 2003 Sheet 1 of 13
 3.3V
3.3V
USB_DSP_RST# R35 10K

DC_EMIFA_OE# R56 10K

3
D11 CPLD_MCBSP0_MUX R40 10K
R84
10K MMBD4148 CPLD_MCBSP1_MUX R23 10K
U8

5
SW2 DC_STAT0 R97 10K
R83 SN74AHC1G14
1 4
DC_STAT1 R98 10K

1
2 3 2 4

RESET FLSHCEn R57

DGND PUSHBUTTON 33 C119 10K
0.1uF

3
3.3V
DGND

DGND DSP_RST# R22

1K
BRD_RST# R24
1K

39
91

18
34
51
66
82
3
U12 FLASH_PAGE R39
1K

VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCINT
VCCINT
TD[0..31]
TD0 42 25 DGND
DSP_DQ0 DC_STAT0 DC_STAT0
TD1 64 96 PULLUP/DOWN TO KEEP LOGIC IN RESET
DSP_DQ1 DC_STAT1 DC_STAT1
TD2 41 WHEN THE CPLD IS NOT PROGRAMMED.
3.3V TD3 DSP_DQ2
63 75 DC_CNTL0
10K RN19D TD4 DSP_DQ3 DC_CNTL0
44 81 DC_CNTL1
10K RN19E TD5 DSP_DQ4 DC_CNTL1
45
10K RN19F TD6 DSP_DQ5
46 52 DC_EMIFA_DIR
10K RN19G TD7 DSP_DQ6 DC_DBUF_DIR
58 37 DC_EMIFA_OE#
DSP_DQ7 DC_DBUF_OEn
TEA[2..21] 54 DC_CNTL_OE#
TEA2 DC_CNTL_OEn
40 79 DC_RST#
SW1 TEA3 DSP_ADDR0 DC_RESETn 3.3V
13 31 DC_DET
TEA4 DSP_ADDR1 DC_DETn
4 5 100
DSP_ADDR2
3 6 69 CPLD_MCBSP0_MUX
MCBSP_SEL0 R78 R79 R80 R81 R82
2 7 98 83 CPLD_MCBSP1_MUX
TCE1n TEA21 DSP_CSn MCBSP_SEL1 150 150 150 150 150
1 8 8
CPLD/FLASHn
76 BRD_RST#
DGND SW DIP-4/SM BRD_RSn
85 DSP_RST#
DSP_RSn D6 D7 D8 D9 D10
10 84
PADDLE SWITCH TCE2n DSP_DC_CS0n DSP_RSn_LED
12
TCE3n DSP_DC_CS1n YELLOW GREEN GREEN GREEN GREEN
90
TSDWEn DSP_DC_WEn
9
3.3V TSDCASn DSP_DC_REn
14 80
TSDRASn DSP_DC_OEn CPLD_CLK_OUT
97 67 USER_LED3
R53 R34 R33 USER_SW3 USER_LED3 USER_LED2
94 47
NU 1K NU USER_SW2 USER_LED2 USER_LED1
93 68
USER_SW1 USER_LED1 USER_LED0
35 71
USER_SW0 USER_LED0
PWB_REV2 29 60
PWB_REV1 PWB_REV2 SPARE0
23 30
PWB_REV0 PWB_REV1 SPARE1 TP TP10
20 48
PWB_REV0 SPARE2
21
R54 R37 R36 SPARE3 TP TP16
CODEC_CLK 87
1K NU 1K CLKIN
6 16
EMU_RSTn RSV0 TP TP19
36 56
PONRSn RSV1
92 61
PUSHBRSn RSV2 TP TP20
99
HPIRSn
57
DGND ISR_TCK FLASH_PAGE TP TP15
62 32
ISR_TMS TCK FLSH_CEn
15 19
ISR_TDI TMS FLSH_WEn
4 17 FLASH_PAGE
USB_DSP_RST# ISR_TDO TDI FLSH_OEn
73
SVS_RST# TDO
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
FLSHCEn
PUSHB_RS
HPI_RESET# FLSHWEn
11
26
33
38
43
53
59
65
74
78
86
88
89
95
EPM3128ATC100-10
FLSHOEn
3.3V
JP3

2 1
4 3 DGND
6
8
5
7
3.3V CPLD
10 9
C38 C68 C69 C71 C72 C39 C70 C40
DGND HEADER 5X2 Title
0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 TMS320C6713 DSK
10K RN19A
10K RN19B Size Document Number Rev
10K RN19C B
506732 C
DGND
Date: Monday, November 24, 2003 Sheet 2 of 13
 C121
XDS_4.1V

0.1 DGND

U21
24
Vcc
3 2 EINT4
DC_EINT4 1A1 1B1
4 5 EINT5
DC_EINT5 1A2 1B2
7 6 EINT6
DC_EINT6 1A3 1B3
8 9 EINT7
DC_EINT7 1A4 1B4
11 10 TINP0
DC_TINP0 1A5 1B5
1
1OE

14 15 TINP1
DC_TINP1 2A1 2B1
17 16 TOUT0
DC_TOUT0 2A2 2B2
18 19 TOUT1
DC_TOUT1 2A3 2B3
21 20
2A4 2B4
22 23
2A5 2B5
13 12
2OE GND
SN74CBTD3384PW
R77 DGND

360

Maximize the distance between switching signals

DGND and the PLL external components.

Place all PLL external components as close

U10E
to the DSP. All PLL external components
must be on a single side of the board. A13
DSP_RST# RESETn

TP28 C13
R51 NU NMI
C2
GP4/EXTINT4/AMUTEIN1
C1
GP5/EXTINT5/AMUTEIN0
D2
EXCCET103U GP6/EXTINT6
E3
E1 EMI FILTER GP7/EXTINT7
DSPIO_3.3V
G2 G1
TINP0/AXR0_3 TOUT0/AXR0_2
1 3 F2 F1
GND

I O TINP1/AHCLKX0 TOUT1/AXR0_4
CT10 C92
+ 10 0.1 A7 A8
DSP_TDI TDI TDO DSP_TDO
2

DSP_TMS B7
TMS
DSP_TCK A6
TCK
DSP_TRST# B6
TRSTn
D9 DSP_EMU0
DGND EMU0
B9 DSP_EMU1
EMU1
C5 D3 DSP_EMU2
PLLHV EMU2
B10 DSP_EMU3
EMU3
C11 DSP_EMU4
EMU4
CLKMODE0 C4 B12 DSP_EMU5
CLKMODE0 EMU5
C22 A3 Y12 R25 33
CLKIN CLKOUT2/GP2 CLKOUT2
R17 Y11 D10 R26 33
ECLKIN CLKOUT3 CLKOUT3
NO-POP

NO-POP TMS320C6713GDP
DGND OPTIONAL

3.3V

L5

C114 C113
0.1 0.01 Ferrite Chip

U14
1 8
OFFn VCC DGND

4 5 R50 33 DSP_CORE_CLK
GND CLK Title

DGND 50 MHz
TMS320C6713 DSK
Size Document Number Rev
B 506732 A

Date: Monday, November 24, 2003 Sheet 3 of 13

 TEA[2..21]

U13
3.3V TEA14 23 2 TD0
U15 SDBA0 BA1 DQ0 TD1
22 4
TEA2 SDA11 BA0 DQ1 TD2
25 37 21 5
TEA3 A0 VCC TEA12 NC DQ2 TD3
24 24 7
TEA4 A1 TD0 TEA11 A10 DQ3 TD4
23 29 66 8
TEA5 A2 DQ0 TD1 TEA10 A9 DQ4 TD5
22 31 65 10
TEA6 A3 DQ1 TD2 TEA9 A8 DQ5 TD6
21 33 64 11
TEA7 A4 DQ2 TD3 TEA8 A7 DQ6 TD7
20 35 63 13
TEA8 A5 DQ3 TD4 TEA7 A6 DQ7 TD8
19 38 62 74
TEA9 A6 DQ4 TD5 TEA6 A5 DQ8 TD9
18 40 61 76
TEA10 A7 DQ5 TD6 TEA5 A4 DQ9 TD10
8 42 60 77
TEA11 A8 DQ6 TD7 TEA4 A3 DQ10 TD11
7 44 27 79
TEA12 A9 DQ7 TD8 TEA3 A2 DQ11 TD12
6 30 26 80
TEA13 A10 DQ8 TD9 TEA2 A1 DQ12 TD13
5 32 25 82
TEA14 A11 DQ9 TD10 3.3V A0 DQ13 TD14
4 34 83
TEA15 A12 DQ10 TD11 TBE3n DQ14 TD15
3 36 59 85
TEA16 A13 DQ11 TD12 TBE2n DQM3 DQ15 TD16
FLASH_PAGE 2 39 28 31
TEA17 A14 DQ12 TD13 R41 TBE1n DQM2 DQ16 TD17
1 41 71 33
TEA18 A15 DQ13 TD14 TBE0n DQM1 DQ17 TD18
TD[0..31] 48 43 16 34
TEA19 A16 DQ14 TD15 DQM0 DQ18 TD19
17 45 36
TEA20 A17 DQ15/A-1 DQ19 TD20
16 73 37
A18 10K NC DQ20 TD21
9 15 57 39
A19 RY/BY NC DQ21 TD22
30 40
NC DQ22

TD10
TD11
TD12
TD13
TD14
TD15
TD16
TD17
TD18
TD19
TD20
TD21
TD22
TD23
TD24
TD25
TD26
TD27
TD28
TD29
TD30
TD31
10 14 42 TD23
TD0
TD1
TD2
TD3
TD4
TD5
TD6
TD7
TD8
TD9
3.3V R58 10K NC1 NC DQ23 TD24
47 13 45
BYTE NC2 TCE0n DQ24 TD25
FLSHCEn 26 14 20 47
CE NC3 CS DQ25
RN6G

RN5G

RN4G

RN3G
TSDRASn TD26
RN6C
RN6D

RN6H

RN5C
RN5D

RN5H

RN4C
RN4D

RN4H

RN3C
RN3D

RN3H
RN6A
RN6B

RN6E

RN5A
RN5B

RN5E

RN4A
RN4B

RN4E

RN3A
RN3B

RN3E
28 19 48
RN6F

RN5F

RN4F

RN3F
FLSHOEn OE RAS DQ26
11 27 TSDCASn 18 50 TD27
FLSHWEn WE VSS CAS DQ27
12 46 TSDWEn 17 51 TD28
BRD_RST# RESET VSS WE DQ28
53 TD29
AM29LV400B DQ29 TD30
70 54
NC DQ30
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
DGND TEA16 69 56 TD31
256K x 16 TECLKOUT NC DQ31
68
3.3V R59 10K CLK
67
CKE
86 43
VSS VDD
ED10
ED11
ED12
ED13
ED14
ED15
ED16
ED17
ED18
ED19
ED20
ED21
ED22
ED23
ED24
ED25
ED26
ED27
ED28
ED29
ED30
ED31
72 29
ED0
ED1
ED2
ED3
ED4
ED5
ED6
ED7
ED8
ED9

VSS VDD
58 15
VSS VDD
44 1
TEA13 TEA15 VSS VDD
84 81
M19
M20
N18
N19
N20

R19
R20
K18
K19

P18
P20

VSSQ VDDQ
T18
T20
T19
L18
L19

W4

JP501
U2
U1
U3

R3
R2

N3
V4

Y3
V2
V1

P1
P2
P3
T1
T2
78 75

1
JP500 VSSQ VDDQ
52 55
VSSQ VDDQ
46 49

A
ED0
ED1
ED2
ED3
ED4
ED5
ED6
ED7
ED8
ED9
ED10
ED11
ED12
ED13
ED14
ED15
ED16
ED17
ED18
ED19
ED20
ED21
ED22
ED23
ED24
ED25
ED26
ED27
ED28
ED29
ED30
ED31
SDBA0 VSSQ VDDQ
2 2 SDA11 38 41 3.3V
B B VSSQ VDDQ
32 35
VSSQ VDDQ

C
12 9
R42 33 TECLKOUT VSSQ VDDQ
6 3
TP3 TP R55 33 TEA15 VSSQ VDDQ

3
J17 Y10 TAECLKOUT2
HOLDn ECLKOUT TEA13 MT48LC4M32B2TG-6
TARDY Y5
ARDY DGND
NEAR DSP V12 ASDWE# R48 33
TSDWEn
JUMPER3_SMT JUMPER3_SMT
AWEn/SDWEn/SSWEn
W10 ASDRAS# R45 33
TSDRASn
TEA2 33 RN8H EA2 AOEn/SDRASn/SSOEn
Y6 V11 ASDCAS# R47 33
TSDCASn
JP500 JP501
TEA3 33 RN8G EA3 EA2 AREn/SDCASn/SSADSn 2M x 32 MT48LC2M32B2TG AB AB
V7
TEA4 33 RN8F EA4 EA3 TP TP5
W7 J18
TEA5 33 RN8E EA5 EA4 HOLDAn TP TP4 4M x 32 MT48LC4M32B2TG BC BC
V8 J19
TEA6 33 RN8D EA6 EA5 BUSREQ
W8
TEA7 33 RN8C EA7 EA6 REV C ADDITION TO SUPPORT 2MX32 OR 4MX32
Y8
TEA8 33 RN8B EA8 EA7
V9
TEA9 33 RN8A EA9 EA8 33 RN12D TCE0n C6713 REQUIRES SDRAM MS ADDRESS BITS
Y9 V17
TEA10 33 RN9H EA10 EA9 ACE0n 33 RN12C
V10 W18 TCE1n CONNECT TO SDRAM BANK BITS. THIS
TEA11 33 RN9G EA11 EA10 ACE1n 33 RN7D
W13 W6 TCE2n DIFFERS F ROM THE C64xx WHERE THIS IS
TEA12 33 RN9F EA12 EA11 ACE2n 33 RN7C
V14 V6 TCE3n HANDLED INTERNALLY.
TEA13 33 RN9E EA13 EA12 ACE3n
W14
TEA14 33 RN9D EA14 EA13 33 RN12B
Y14 V20 TBE0n
TEA15 33 RN9C EA15 EA14 ABE0n 33 RN12A
W15 U19 TBE1n
TEA16 33 RN9B EA16 EA15 ABE1n 33 RN7B
Y15 Y4 TBE2n
TEA17 33 RN9A EA17 EA16 ABE2n 33 RN7A
V16 V5 TBE3n
TEA18 33 RN12H EA18 EA17 ABE3n
Y16
TEA19 33 RN12G EA19 EA18
W17
TEA20 33 RN12F EA20 EA19
Y18
TEA21 33 RN12E EA21 EA20
U18
EA21 3.3V

CT13 CT5
FLASH & SDRAM & CONFIG
+ 10 + 10 C73 C75 C95 C97 C74 C45

0.1 0.1 0.1 0.1 0.1 0.1 Title

U10A
TMS320C6713 DSK
TMS320C6713GDP Size Document Number Rev
DGND B C
506732
Date: Monday, November 24, 2003 Sheet 4 of 13
 5V
R1
DCISO-4.1V

1
1.6K
D1
LM4040DCIM3-4.1

2
DGND

C13 C28
U4 0.1 0.1 U9
16 16
VCC DGND DGND VCC
2 2 DC_CLKS0
DC_CLKS1 1B1 CLKS0 1B1
3 4 4 3
1B2 1A 1A 1B2
5 5 DC_CLKR0
DC_CLKR1 2B1 U10D CLKR0 2B1
BCLK 6 7 7 6
2B2 2A CLKS1 2A 2B2
11 E1 K3 11 DC_DR0
DC_CLKX1 3B1 CLKR1 CLKS/SCL1 CLKS0/AHCLKR0 DR0 3B1
10 9 M1 H3 9 10
3B2 3A CLKX1 CLKR1/AXR0_6 CLKR0/ACLKR0 3A 3B2
14 L3 G3 14 DC_FSR0
DC_DR1 4B1 DR1 CLKX1/AMUTE0 CLKX0/ACLKX0 FSR0 4B1
13 12 12 13
AIC23SDATAOUT 4B2 4A 4A 4B2
M2 J1
DX1 DR1/SDA1 DR0/AXR0_0
1 L2 H2 1
S DX1AXR0_5 DX0/AXR0_1 S
15 8 8 15
OE GND FSR1 GND OE
M3 J3
FSX1 FSR1/AXR0_7 FSR0/AFSR0
L1 H1
SN74CBT3257PW FSX1 FSX0/AFSX0 SN74CBT3257PW
N1
U3 SCL0 U1
N2
SDA0
16 16
VCC VCC
2 2 DC_CLKX0
DC_DX1 1B1 CLKX0 1B1
3 4 TMS320C6713GDP 4 3 CTL_CLKX0
AIC23SDATAIN 1B2 1A 1A 1B2
5 5 DC_DX0
DC_FSR1 2B1 DX0 2B1
6 7 7 6 CTL_DX0
LRCOUT 2B2 2A 2A 2B2
11 11 DC_FSX0
DC_FSX1 3B1 3.3V FSX0 3B1
10 9 9 10 CTL_FSX0
LRCIN 3B2 3A 3A 3B2
14 14
4B1 4B1
13 12 12 13
4B2 4A 4A 4B2
1 1 CPLD_MCBSP0_MUX
CPLD_MCBSP1_MUX S R49 R46 R44 R43 S
15 8 8 15
OE GND 10K 10K 10K 10K GND OE

SN74CBT3257PW SN74CBT3257PW R18

R12 360
360 DGND

DGND

R27 33
SCL0
DGND DGND
R28 33
SDA0

MCBSP
Title
TMS320C6713 DSK
Size Document Number Rev
B A
506732
Date: Monday, November 24, 2003 Sheet 5 of 13
 ENDIAN
DEVICE CONFIGURATION
BOOT-1
BOOT-0
HPI_EN
OFF - OPEN
ON - CLOSED 3.3V

SW3
HD8 iPU 1 8 R85 1K
HD4 iPD 2 7 R86 1K
HD3 iPU 3 6 R87 1K
HD14 iPU 4 5 R3 1K

SW DIP-4/SM
PENCIL SWITCH
DGND

HD12 R29 1K
iPU R30 1K
CLKMODE0

HPI DAUGHTER CARD CAN RESET

U10C
DSP VIA THIS SIGNAL. SIGNAL IS
J1
COMBINED WITH OTHER DSP
B14 HD15 1 2
HD15/GP15 1 2 RESET SOURCES.
C14 HD14 3 4
HD14/GP14 HD13 3 4 3.3V
A15 CLKOUT3 5 6
HD13/GP13 HD12 5 6
C15 7 8
HD12/GP12 HD11 HD1 7 8
A16 9 10
HD11/GP11 HD10 HD3 9 10 HD0
B16 11 12
HD10/GP10 HD9 HD5 11 12 HD2 R19
C16 13 14
HD9/GP9 HD8 HD7 13 14 HD4 10K
B17 15 16
HD8/GP8 HD7 15 16 HD6
A18 17 18
HD7/GP3 HD6 HD8 17 18
C17 19 20
HD6/AHCLKR1 HD5 HD10 19 20 HD9
B18 21 22
HD5/AHCLKX1 HD4 HD12 21 22 HD11 HPI_RESET#
C19 23 24
HD4/GP0 HD3 HD14 23 24 HD13
C20 25 26
HD3/AMUTE1 HD2 25 26 HD15
D18 27 28
HD2/AFSX1 HD1 HDS2n 27 28
D20 29 30
HD1/AXR1_7 HD0 29 30 HASn
E20 31 32
HD0/AXR1_4 HDS1n 31 32
33 34
33 34 HCNTL0
35 36
HINTn HCSn 35 36
J20 37 38
HINTn/GP1 HCNTL1 37 38 HHWIL
G19 39 40
HCNTL1/AXR1_1 HCNTL0 HCNTL1 39 40
G18 41 42
HCNTL0/AXR1_3 HHWIL 41 42 HINTn
H20 43 44
HHWIL/AFSR1 HRWn HRDYn 43 44
G20 45 46
HRWn/AXR1_0 HASn 45 46
E18 47 48
HASn/ACLKX1 HCSn HRWn 47 48
F20 49 50
HCSn/AXR1_2 HDS1n 49 50
E19 51 52
HDS1n/AXR1_6 HDS2n 51 52
F18 53 54
HDS2n/AXR1_5 HRDYn 53 54
H19 55 56
HDRYn/ACLKR1 55 56
57 58
57 58
59 60
59 60
61 62
61 62
63 64
63 64
65 66
TMS320C6713GDP 65 66
67 68 SCL0
67 68
69 70
69 70
71 72 SDA0
71 72
73 74
73 74
75 76
75 76
77 78
77 78
79 80 CLKOUT2
79 80

SFM140L2SDLC
DGND DGND
HOST PORT/McASP
Title
TMS320C6713 DSK
Size Document Number Rev
B A
506732
Date: Monday, November 24, 2003 Sheet 6 of 13
 TEA[2..21]
DC_D[31..0]
3.3V
3.3V

3.3V DC_A[21..2]
TD[0..31]
U17
42 7 R13 U5
Vcc Vcc 10K
31 18 42 7
Vcc Vcc Vcc Vcc
31 18
TD0 DC_D0 Vcc Vcc
47 2
TD1 1A1 1B1 DC_D1 TEA17 DC_A17 3.3V
46 3 47 2
TD2 1A2 1B2 DC_D2 TEA16 1A1 1B1 DC_A16
44 5 46 3
TD3 1A3 1B3 DC_D3 TEA15 1A2 1B2 DC_A15
43 6 44 5
TD4 1A4 1B4 DC_D4 TEA14 1A3 1B3 DC_A14 C17 C15 C16 C14
41 8 43 6
TD5 1A5 1B5 DC_D5 TEA13 1A4 1B4 DC_A13
40 9 41 8
TD6 1A6 1B6 DC_D6 TEA12 1A5 1B5 DC_A12
38 11 40 9 0.1 0.1 0.1 0.1
TD7 1A7 1B7 DC_D7 TEA11 1A6 1B6 DC_A11
37 12 38 11
TD15 1A8 1B8 DC_D15 TEA10 1A7 1B7 DC_A10
36 13 37 12
TD14 2A1 2B1 DC_D14 TEA9 1A8 1B8 DC_A9
35 14 36 13
TD13 2A2 2B2 DC_D13 TEA8 2A1 2B1 DC_A8 DGND
33 16 35 14
TD12 2A3 2B3 DC_D12 TEA7 2A2 2B2 DC_A7
32 17 33 16
TD11 2A4 2B4 DC_D11 TEA6 2A3 2B3 DC_A6
30 19 32 17
TD10 2A5 2B5 DC_D10 TEA5 2A4 2B4 DC_A5
29 20 30 19
TD9 2A6 2B6 DC_D9 TEA4 2A5 2B5 DC_A4
27 22 29 20
TD8 2A7 2B7 DC_D8 TEA3 2A6 2B6 DC_A3 3.3V
26 23 27 22
2A8 2B8 TEA2 2A7 2B7 DC_A2
26 23
2A8 2B8
48
1OE C20 C19 C21 C18
1 48
1DIR 1OE
25 1
2OE 1DIR
24 25 0.1 0.1 0.1 0.1
2DIR 2OE
24
2DIR
4 28
GND GND
10 34 4 28
GND GND GND GND DGND
15 39 10 34
GND GND GND GND
21 45 15 39
GND GND GND GND
21 45
GND GND 3.3V
DGND SN74LVTH16245A DGND SN74LVTH16245A
DGND DGND
C116 C115 C94 C96
3.3V 3.3V
0.1 0.1 0.1 0.1

U16 U6
42 7 42 7 DGND
Vcc Vcc Vcc Vcc
31 18 31 18
Vcc Vcc Vcc Vcc
TD16 47 2 DC_D16 TEA21 47 2 DC_A21
TD17 1A1 1B1 DC_D17 TEA20 1A1 1B1 DC_A20 3.3V
46 3 46 3
TD18 1A2 1B2 DC_D18 TEA19 1A2 1B2 DC_A19
44 5 44 5
TD19 1A3 1B3 DC_D19 TEA18 1A3 1B3 DC_A18
43 6 43 6
TD20 1A4 1B4 DC_D20 1A4 1B4 C118 C98 C99 C117
41 8 TBE3n 41 8 DC_BE3#
TD21 1A5 1B5 DC_D21 1A5 1B5
40 9 TBE2n 40 9 DC_BE2#
TD22 1A6 1B6 DC_D22 1A6 1B6 0.1
38 11 TBE1n 38 11 DC_BE1# 0.1 0.1 0.1
TD23 1A7 1B7 DC_D23 1A7 1B7
37 12 TBE0n 37 12 DC_BE0#
TD31 1A8 1B8 DC_D31 1A8 1B8
36 13 TCE3n 36 13 DC_CE3#
TD30 2A1 2B1 DC_D30 2A1 2B1
35 14 TCE2n 35 14 DC_CE2#
TD29 2A2 2B2 DC_D29 2A2 2B2 DGND
33 16 TSDCASn 33 16 DC_ARE#
TD28 2A3 2B3 DC_D28 2A3 2B3
32 17 TSDRASn 32 17 DC_AOE#
TD27 2A4 2B4 DC_D27 2A4 2B4
30 19 TSDWEn 30 19 DC_AWE#
TD26 2A5 2B5 DC_D26 2A5 2B5
29 20 DC_ARDY 29 20 TARDY
TD25 2A6 2B6 DC_D25 2A6 2B6
27 22 27 22
TD24 2A7 2B7 DC_D24 2A7 2B7 R15 33
26 23 TAECLKOUT2 26 23 DC_ECLKOUT
2A8 2B8 2A8 2B8
48 R14 48
1OE 1K 1OE
1 1
1DIR 1DIR R403
25 25
2OE 2OE 1K 3.3V
24 24
2DIR 2DIR
4 28 DGND 4 28
GND GND GND GND #OE DIR OPERATION
10 34 10 34
GND GND GND GND
15 39 15 39 L L A <-- B
GND GND GND GND
21 45 21 45 L H A --> B
GND GND GND GND
H X ISOLATION
DGND SN74LVTH16245A DGND DGND SN74LVTH16245A DGND
DC_EMIFA_OE#
DAUGHTERCARD BUFFERING
DC_EMIFA_DIR
DC_EMIFA_DIR =1 FOR WRITES
Title
TMS320C6713 DSK
Size Document Number Rev
DC_CNTL_OE# B
506732 B

Date: Monday, November 24, 2003 Sheet 7 of 13

 DC_D[31..0]

DC_A[21..2]
5V 5V
-12V 12V

3.3V 3.3V 3.3V 3.3V

External Peripheral Interface External Memory Interface

5V J3 5V J4
2 1 2 1
2 1 DC_A20 2 1 DC_A21
4 3 4 3
4 3 DC_A18 4 3 DC_A19
6 5 6 5
6 5 DC_A16 6 5 DC_A17
8 7 8 7
8 7 DC_A14 8 7 DC_A15
10 9 10 9
10 9 10 9
12 11 12 11
12 11 DC_A12 12 11 DC_A13
14 13 14 13
14 13 DC_A10 14 13 DC_A11
16 15 16 15
16 15 DC_A8 16 15 DC_A9
18 17 18 17
18 17 DC_A6 18 17 DC_A7
20 19 20 19
20 19 20 19
22 21 DC_CLKX0 22 21
DC_CLKS0 22 21 DC_A4 22 21 DC_A5
24 23 DC_FSX0 24 23
DC_DX0 24 23 DC_A2 24 23 DC_A3
26 25 26 25
26 25 26 25
28 27 DC_CLKR0 DC_BE2# 28 27 DC_BE3#
28 27 28 27
30 29 DC_FSR0 DC_BE0# 30 29 DC_BE1#
DC_DR0 30 29 30 29
32 31 32 31
32 31 DC_D30 32 31 DC_D31
34 33 DC_CLKX1 34 33
DC_CLKS1 34 33 DC_D28 34 33 DC_D29
36 35 DC_FSX1 36 35
DC_DX1 36 35 DC_D26 36 35 DC_D27
38 37 38 37
38 37 DC_D24 38 37 DC_D25
40 39 DC_CLKR1 40 39
40 39 40 39
42 41 DC_FSR1 42 41
DC_DR1 42 41 DC_D22 42 41 DC_D23
44 43 44 43
44 43 DC_D20 44 43 DC_D21
46 45 DC_TOUT0 46 45
DC_TINP0 46 45 DC_D18 46 45 DC_D19
48 47 48 47
DC_EINT5 48 47 48 47
50 49 DC_D16 50 49 DC_D17
DC_TINP1 50 49 DC_TOUT1 50 49
52 51 52 51
52 51 DC_D14 52 51 DC_D15
54 53 DC_EINT4 54 53
54 53 DC_D12 54 53 DC_D13
56 55 56 55
56 55 DC_D10 56 55 DC_D11
58 57 58 57
58 57 DC_D8 58 57 DC_D9
60 59 DC_RST# 60 59
60 59 60 59
62 61 62 61
62 61 3.3V 3.3V DC_D6 62 61 DC_D7
64 63 DC_CNTL1 64 63
DC_CNTL0 64 63 DC_D4 64 63 DC_D5
DC_STAT0 66 65 DC_STAT1 66 65
66 65 DC_D2 66 65 DC_D3
DC_EINT7 68 67 DC_EINT6 68 67
68 67 R65 R16 DC_D0 68 67 DC_D1
70 69 70 69
70 69 10K 4.7K 70 69
72 71 72 71
72 71 72 71
74 73 DC_AWE# 74 73 DC_ARE#
74 73 74 73
76 75 DC_DET DC_ARDY 76 75 DC_AOE#
76 75 76 75
DC_ECLKOUT 78 77 DC_CE2# 78 77 DC_CE3#
78 77 78 77
80 79 80 79
80 79 80 79
CONNECTOR 40 X 2 CONNECTOR 40 X 2

DGND DGND DGND DGND

R2 0

DAUGHTERCARD I/F
Title
TMS320C6713 DSK
Size Document Number Rev
B A
506732
Date: Monday, November 24, 2003 Sheet 8 of 13
 5V OPTIONAL, POWER SUPPLY
LOAD RESISTORS, 2512
BODY
Connect at pin 1
Sets Voltage
R346 R347
NU NU 0.025 OHMS FOR POWER
MEASUREMENT R10
3.74K 1%

SYSTEM POWER MEASUREMENT AGND R11 C36

DGND DGND POINT S. R IS 2512 BODY, 6 VIAS R31 3.3 sq in AGND, min 2K 1% 8200pF 3.3V
FROM PAD TO PLANE C65 C66 thermal pad
71.5K 1% C12
0.1uF 0.039uF U7 470pF 3300pF 107 1%
21 C37 R20 R38 TP1
POWERPAD
20 1
RT AGND 10K 1% 10K TP
19 2
SYNC VSENSE R21
POWER INPUT 18
SS/ENA COMP
3
5V L4 17 4
J5 VBIAS PWRGD SVS_RST#
0 5 C10
R99 BOOT 3.3V C127
CENTER 16
VIN3 0.047uF DSPIO_3.3V
SHUNT 15
BLM41P750SPT CT9 VIN2 L3 NO-POP
SLEEVE 14 6
+ CT16 C63 + C64 VIN1 PH1 2.7 uH
R52 7
2.5 MM JACK 47uF 0.1uF PH2 CT4 C11 3.3V @1.5Amp Max
180 13 8 DSPIO_3.3V
RASM712 10uF LESR 0.1uF PGND3 PH3 + D12
12 9
PGND2 PH4 0
11 10
PGND1 PH5 100uF 4V 1000pF MURS120T3 R66 TP31
1
2

TP
TPS54310PWP CT15
JP4 D3 +
NO-POP D13 100 uF
GREEN
MURS120T3 0.025 OHMS FOR POWER
EMI SUPPRE SION. LOCATE NEAR EACH REGULATOR. NO-POP MEASUREMENT

1
2
TP32 1.26V -> 24.3K 1% OPTIONAL CROSS COUPLE
6 VIAS FROM PAD TO PLANE OR DIRECT TIE.
1.2V -> 28.0K 1% DSP POWER MEASUREMENT
1 Connect at pin 1 D14
JP2 POINT S. R IS 2512 BODY, 6 VIAS
TestPoint FROM PAD TO PLANE
DGND MURS120T3
JP1
R6
24.3K 1%
J6 D15
-12V 12V R9 AGND R5 C4

1
2
3.3 sq in AGND, min 1.65K 1% 0.01uF MURS120T3 NO-POP
4 C6 C8 thermal pad DSP_CVDD
+5 TO BE POPULATED BY 71.5K C2 MURS120T3
3
GND 0.1uF 0.039uF U2 560pF D16
2 THE USER IF
-12 C5 R8 0 DSP_CVDD
1 NEEDED. 21
+12 POWERPAD 3300pF 107 1% R4
20 1
RT AGND TP2
19 2
NU SYNC VSENSE R7 SENSE_DSP_CVDD TP
18 3
Molex 53-109-0410 L2 SS/ENA COMP 10K 1% CT1
17 4
VBIAS PWRGD C3 +
5
BOOT 100 uF
16
VIN3 0.047uF 1.26V @1.5Amp Max
WARNING: 15
VIN2
BLM41P750SPT CT3 14 6 L1
DO NOT SUPPLY POWER TO BOTH C9 + C7 VIN1 PH1
7 2.7 uH
0.1uF PH2
POWER CONNECTORS AT THE 13
PGND3 PH3
8
+
10uF LESR 0.1uF 12 9 CT2 C1
SAME TIME! PGND2 PH4 100uF 4V 1000pF
11 10
PGND1 PH5

TPS54310PWP

EACH REGULATOR CAN SUPPLY UP TO 3A OF

DAUGHTERCARD STANDOFF GROUNDING CURRENT. HOWEVER COMPONENT VALUES
HAVE BEEN SELECTED FOR 1.5A OPERATION.
M1 M2 M3 M4
125_PH 125_PH 125_PH 125_PH VALUES CALCULATED WITH SWIFT DESIGN TOOL 2.0.

KEEP TRACES A MINIMUM FOLLOW TPS54310 EVM LAYOUT

OF 0.070 INCHES FROM
THESE HOLES.
POWER
Title
DGND TMS320C6713 DSK
Size Document Number Rev
B 506732 B

Date: Monday, November 24, 2003 Sheet 9 of 13

DSP_CVDD DSPIO_3.3V
U10G U10H U10I
A4 A17 A1 P19
CVDD DVDD VSS VSS
A9 B3 A2 T4
CVDD DVDD VSS VSS
A10 B8 A11 T17
CVDD DVDD VSS VSS
B2 B13 A14 U4
CVDD DVDD U10J VSS VSS
B19 C10 A19 U8
CVDD DVDD VSS VSS
C3 D1 A5 A20 U9
CVDD DVDD RSV VSS VSS
C7 D16 B5 B1 U13
CVDD DVDD RSV VSS VSS
C18 D19 C12 B4 U17
CVDD DVDD RSV VSS VSS
D5 F3 D7 B15 U20
CVDD DVDD RSV VSS VSS
D6 H18 D12 B20 W1
CVDD DVDD RSV VSS VSS
D11 J2 A12 C6 W5
CVDD DVDD RSV VSS VSS
D14 M18 B11 C8 W11
CVDD DVDD R60 RSV VSS VSS
D15 R1 C9 W16
CVDD DVDD 10K VSS VSS
F4 R18 D4 W20
CVDD DVDD VSS VSS
F17 T3 TMS320C6713GDP D8 Y1
CVDD DVDD VSS VSS
K1 U5 D13 Y2
CVDD DVDD VSS VSS
K4 U7 D17 Y13
CVDD DVDD VSS VSS
K17 U12 E2 Y19
CVDD DVDD DGND VSS VSS
L4 U16 E4 Y20
CVDD DVDD VSS VSS
L17 V13 E17
CVDD DVDD VSS
L20 V15 F19
CVDD DVDD VSS
R4 V19 G4
CVDD DVDD VSS DGND
R17 W3 G17
CVDD DVDD VSS
U6 W9 H4
CVDD DVDD VSS
U10 W12 H17
CVDD DVDD VSS
U11 Y7 J4
CVDD DVDD VSS
U14 Y17 J9
CVDD DVDD VSS
U15 J10
CVDD VSS
V3 TMS320C6713GDP J11
CVDD VSS
V18 J12
CVDD VSS
W2 K2
CVDD VSS
W19 K9
CVDD VSS
K10
VSS
TMS320C6713GDP K11
VSS
K12
VSS
K20
All capacitors on this sheet are decoupling capacito rs for the DSP. They should be placed as close as possible to the DSP. VSS
L9
DSP_CVDD VSS
L10
VSS
L11
VSS
L12
DSP_CVDD VSS
M4
CT14 CT11 C30 C32 C105 C108 C50 C46 C23 C25 C34 C58 C88 C112 C110 C104 C101 C52 C54 C56 C85 C83 C81 C27 VSS
M9
+ 10 + 10 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 VSS
M10
VSS
M11
VSS
M12
VSS
M17
VSS
N4
VSS
N17
VSS
P4
DGND C77 C79 VSS
P17
0.1 0.1 VSS

TMS320C6713GDP
DGND

DGND

DSPIO_3.3V

DSPIO_3.3V
CT6 CT8 C24 C29 C33 C62 C90 C109 C35 C100 C106 C103 C102 C78 C80 C47 C48 C59
+ 10 + 10 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1

DGND
C41 C26 C31 C51
0.1 0.1 0.1 0.1

DSP POWER & DECOUPLING

DGND Title
TMS320C6713 DSK
Size Document Number Rev
B 506732 A

Date: Monday, November 24, 2003 Sheet 10 of 13

 42 RN2C
DSP JTAG HEADER 42 RN2D
DSP_EMU0
42 RN2A
DSP_EMU1
42 RN2B
42 RN2E
DSP_EMU2
3.3V 3.3V 42 RN2F
DSP_EMU3
42 RN2G
DSP_EMU4
J8 ROUTE TRACES AS 42 RN2H
DSP_EMU5
1 2 R88
1K
ONE GROUP. MATCH
3 4
XDS_TVD 5 SIGNAL LENGTH.
7 8 3.3V
9 10
11 12
13 14 R94
LOCACTE R-PACK NEAR DSP 30.1K
HEADER 7x2, Emulation DGND J7
C2 A1 HURRICANE_DETn
EMU18 GND
JTAG MULTIPLEXERS B3
C4
EMU17 GND
A2
A3 C125
EMU16 GND
C5 A4
5V EMU15 GND
B5 A5 0.1
R93 EMU14 GND
C6 A6
XDS_4.1V EMU13 GND
XDS_4.1V B6 A7
EMU12 GND DGND
C7 A8
EMU11 TYPE0

1
1.6K C123 C9 A9
D5 EMU10 GND
B9 A10
LM4040DCIM3-4.1 0.1 EMU9 GND
C10 A11
EMU8 GND
B10 A12
EMU7 GND
C11 A13
DGND HUR_EMU5 EMU6 GND

2
B11 A14
HUR_EMU4 EMU5 GND
C12 A15
HUR_EMU3 EMU4 GND
C13
HUR_EMU2 EMU3
B13 D1
HUR_EMU1 EMU2 GND
C14 D2
3.3V DGND HUR_EMU0 EMU1 GND
B14 D3
EMU0 GND
C8 D4
R67 U19 TCKRTN GND
B12 D5
47K TCLK GND
16 B7 D6
XDS_TDO VCC TDO GND
2 B4 D7
T_TDO 1B1 TDI GND
3 4 B2 D8
T_TDO XDS_TDI 1B2 1A TMS TYPE1
5 C3 D9
T_TDI 2B1 TRSTn GND
6 7 C15 D10
T_TDI XDS_TMS 2B2 2A ID3 GND
11 C1 D11
T_TMS 3B1 ID2 GND
10 9 B15 D12
T_TMS XDS_TRST# 3B2 3A 3.3V ID1 GND
14 B1 D13
T_TRSTn 4B1 R91 1K ID0 GND
13 12 B8 D14
T_TRSTn 4B2 4A DSP_TRST# TVD GND
D15
GND
1
3.3V S DSP_TMS HEADER 4x15
15 8
OE GND DGND DGND
SN74CBT3257PW DSP_TDI
U18 DGND R100 3.3V
33 DSP_TDO
5

SN74AHC1G14
U26
HURRICANE_DETn 2 4

5
SN74LVC1G32
1
4 R96
DSP_TCK
33
3

3.3V

3
DGND 3.3V C124
U25 .1uF
R90 16
47K XDS_EMU0 VCC DGND
2
T_EMU0 1B1 MUX_EMU0 DGND
3 4
T_EMU0 XDS_EMU1 1B2 1A
5
2B1

5
T_EMU1 6 7 MUX_EMU1 U24
T_EMU1 XDS_TCK 2B2 2A
11 1
T_TCK 3B1 HUR_TCK R92
10 9 4
T_TCK XDS_TCKRET 3B2 3A 33
14 2
T_TCK_RET 4B1 HUR_TCKRTN SN74LVC1G32
13 12
T_TCK_RET 4B2 4A
DGND

3
1
3.3V S
U23 15 8
OE GND C126
5

U22 SN74CBT3257PW R95

R89 D4
4
1
4 2
DGND 100 1% DGND EMULATION
2 SN74AHC1G14 22pF
DGND
C122 150 LTST-C150GKT SN74LVC1G32
USB IN USE Title
3

.1uF
TMS320C6713 DSK
DGND Size Document Number Rev
B A
DGND
506732
Date: Monday, November 24, 2003 Sheet 11 of 13
 5 4 3 2 1

3.3V
C67

.1uFDGND

U11

5
D D

1 CLK_12MHZ
R32 4
CODEC_CLK 33 2

SN74LVC1G32

3
DGND

3.3V USB/Emulation 5V

AIC23 Audio 5V

CODEC_SYSCLK 3.3V
T_TRSTn T_TRSTn
3.3V
BCLK DATA_BCLK T_TCK T_TCK
LRCIN DATA_SYNCIN PONRSn T_TMS T_TMS
SVS_RST#
AIC23SDATAIN DATA_DIN AIC3.3V T_TDI T_TDI
C AIC23SDATAOUT DATA_DOUT T_TDO T_TDO C
LRCOUT DATA_SYNCOUT T_EMU0 T_EMU0
T_EMU1 T_EMU1
USB_DSP_RST# USB_DSP_RST#
CTL_DX0 CTL_DATA
CTL_CLKX0 CTL_CLK
CTL_FSX0 CTL_CS GND CLK_12MHZ T_TCK_RET T_TCK_RET
AIC23 Audio
CLK_24MHZ
GND
DGND

USB/Emulation DGND

B B

A
Hierarcharical Blocks A

Title
TMS320C6713 DSK
Size Document Number Rev
B 506732 A

Date: Monday, November 24, 2003 Sheet 12 of 13

5 4 3 2 1