Logical Effort

LE: How much worse a given gate is at producing output current compared to the inverter.
LE is the Cinof a gate input divided by Cinof the inverter.

p –Intrinsic delay
1 •Predominantly caused by the internal capacitance associated with its transistors.
2 •Increasing size of transistor, increases their ability to overcome their own increased internal capacitance.
3 •‘p’value stays constant irrespective of the size of the gate.

Gain (G) –Electrical Effort

1
2 •How the gate’s electrical environment (what the gate is connected to) affects its performance.
3 •It is defined as Cout/Cin.
4 •Gain explains
5 –Increasing load will slow the transistor
6 –Increasing size will speedup the transistor
7 –Increasing size will increase the gate’s CinValue
8 •Delay depends on the Gain of the gate.

What happens to the delay and the gain of the cell if the load capacitance doubles?
New delay 2D and gain = 2Cout/Cin

Answer:It's easy, maintain a constant gain constant gain yields a

constant delay increase the drive (size) of the inverter until the
input capacitance double or increase the drive (size) of the inverter until the gain returns to the original value.

Gain = 2 Cout / 2 Cin = Cout/Cin

1 Fix the delays, estimate the load and resize the cell.
2 Timing + Parasitics= Size
3 Synthesis tool uses a Supercell(Shown with a spring).
4 During Placement the cell sizes are adjusted depending on the value of ‘d’
5

1 Size driven Placement: Size the gates to meet timing budget

2 •Load-driven routing: Size the wires and spacings to maintain the original timing budget
Logical effort is the ratio of the input capacitance of a gate to the input capacitance of an inverter delivering the same output
current.•Measure from delay vs. fanout plots•Or estimate by counting transistor widths
The NOR gate has a higher logical effort than the NAND (5/3 versus 4/3 for a 2-input gate), and thus is slower.
The typical inverter has an input capacitance of 3 units, since the PMOS is typically twice the size of the NMOS. The inverter's
drive resistance is taken to be 1, and thus the bottom of the fraction is always 3.

To achieve the same drive strength as the inverter, the 2-input NAND must have an input capacitance of four units (as seen by
each input), and thus its logical effort is taken to be 4/3. The 2-input NOR has an input capacitance of five units (as seen by each
input) and thus its logical effort is taken to be 5/3.
Let us now design a 2-input NAND gate so that it has the same drive characteristics
as an inverter with a pulldown of width 1 and a pullup of width 2.

. The capacitance of the transistor’s gate is proportional to W and its ability to produce output current,
or conductance, is also proportional to . Under this assumption, an inverter will have a pulldown transistor of width W and a
pullup transistor of width 2W_ 􀀀
so the total input capacitance can be said to be 3W By contrast, each of the two pullup transistors in parallel need be only as
large as the inverter pullup transistor to achieve the same drive as the reference inverter. Here we assume that if either input to
the NAND gate is LOW, the output must be pulled HIGH, and so the output drive of the NAND gate must match that of the
inverter even if only one of the two pullups is conducting.
We find the logical effort of the NAND gate in Figure 4.1b by extracting capacitances from the circuit schematic. The input
capacitance of one input signal is the sum of the width of the pulldown transistor and the pullup transistor, or
_ 􀀀Let us now design a 2-input NAND gate so that it has the same drive characteristics as an inverter with a pulldown of width
1 and a pullup of width 2. Because the two pulldown transistors of the NAND gate are in series, each must have twice the
conductance of the inverter pulldown transistor so that the series connection has a conductance equal to that of the inverter
pulldown transistor. Therefore, these transistors are twice as wide as the inverter pulldown transistor or 2 + 2 = 4. The input
capacitance of the inverter with identical output drive is 2+ 1 = 3 . We designed the NOR gate in Figure 4.1c in a similar way.
To obtain the same pulldown drive as the inverter, pulldown transistors one unit wide suffice. To obtain the same pullup drive,
transistors four units wide are required, since two of them in series must be equivalent to one transistor two units wide in the
inverter. Summing the input capacitance on one input, we find that the NOR gate has logical effort, g=5/3 This is larger than
the logical effort of the NAND gate because pullup transistors are less effective at generating output current than pulldown
transistors.

Size vsLoad -Magma Flow

1 •The Magma flow operates in the "Size vsLoad" plane

2 •The cell delay is fixed based on the applied timing constraints
3 •The fixed cell delay is expressed in the form of a gain value
4 •Gain values are assigned during logic synthesis without the needof output load estimate; no wire load models are
needed
5 •As the load value changes during physical design, the cell delaycan be held constant by holding the gain value
constant

Gain Based Synthesis

1 •Synthesis and place-and-route tools should work on the same plane.

2 •A three dimensional space involving size, delay and load.
3 •Logical Effort technique says delay = d*T, where ‘d’is calculated in a slightly complicated manner, and T is a process-
specific constant, normally representing the speed of the basic transistor for the technology.

1 d = (LE x G) + p
2 –LE –Logical effort
3 –G –Gain
4 –p –intrinsic delay
5 •All parameters in calculation of ‘d’is normalized to a base logical function.
6 •The base function is a inverter driving another identical inverter with no parasitics.
Making delay independent of load

Fixed Timing Methodology

Fixed Timing in a nutshell􀂃
Goal
􀂋Correct by construction (eliminate iterations)
􀂋Emphasis on timing, not on size.
􀂃Map to size-independent supercells
􀂃Pick optimized delay up-front = pick a gain
􀂋If no feasible gain can be found: change your RTL
􀂃Fix this delay throughout placement and routing
􀂃Keep delay constant primarily by cell sizing.