Professional Documents
Culture Documents
2 , May 2000
Application Note
AN-SMPS-1683X – 1
CoolSET
TDA16831 ... 34 for OFF – Line Switch Mode Power Supplies
Power Conversion
N e v e r s t o p t h i n k i n g
TDA1683X for OFF – Line Switch Mode Power Supplies
Contents:
CIRCUIT DESCRIPTION............................................................................................ 2
DESIGN PROCEDURE
DEFINE INPUT PARAMETERS:....................................................................................... 5
INPUT DIODE BRIDGE (BR1):....................................................................................... 5
DETERMINE INPUT CAPACITOR (C3):............................................................................ 5
TRANSFORMER DESIGN (TR1): ................................................................................... 7
WINDING DESIGN: ...................................................................................................... 8
OUTPUT RECTIFIER (D1):.......................................................................................... 10
OUTPUT CAPACITORS (C5 & C9): ............................................................................. 10
OUTPUT FILTER (L3 & C9): ...................................................................................... 11
VCC – SUPPLY:....................................................................................................... 11
CALCULATION OF SNUBBER NETWORK: ...................................................................... 12
CALCULATION OF LOSSES: ........................................................................................ 13
VOLTAGE REGULATION LOOP: ................................................................................... 15
REGULATION LOOP:.................................................................................................. 16
TRANSFER CHARACTERISTICS OF REGULATION LOOP ELEMENTS: ................................ 16
TRANSFORMER CONSTRUCTION ................................................................................ 21
Page 1 of 28 AN-SMPS-1683X – 1
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Circuit Description
The TDA 16831 ... 34 is a current mode pulse width modulator with an integrated CoolMOS
Transistor. It meets the need for minimum external control circuitry for a flyback application.
Current mode control means that the current (IPRI) through the CoolMOS Transistor and flyback
transformer is compared with a feedback signal derived from the output voltage (VOUT) of the flyback
application. The result of that comparision determines the on time (tON) of the CoolMOS Transistor.
To minimize external circuitry the current sense circuitry is integrated within the CoolSET controller.
The oscillator resistor and capacitor which determine the switching frequency are also integrated,
reducing the external connections. Special efforts have been made to compensate temperature
dependancy of clock frequency and to minimize the number of the passive components.
Operating Principles
The TDA 16831 ... 34 is designed for a current mode flyback configuration in discontinous current
mode.
The control circuit has a fixed frequency and the duty cycle (D) of integrated CoolMOS Transistor is
controlled to maintain a constant output voltage (VOUT).
The diagram below (Fig. 1) shows the input voltage (VDC IN) and the primary (IPRI) and secondary (ISEC)
transformer current.
When the CoolMOS Transistor is turned on, the start of all windings on the transformer will go positive.
The rectifier diode (D1) on the secondary side will be reverse-biased and will not conduct. Therefore
no current will flow in the secondary while the CoolMOS Transistor is turned on. During this phase,
energy is being stored in the primary winding inductance and the transformer may be treated as a
simple series inductor. The diagram shows (Fig. 1) that there will be a linear increase of primary
current (IPRI) while the primary CoolMOS Transistor is on.
When the CoolMOS Transistor is turned off, the voltage will reverse on all windings (flyback action)
until clamped by the secondary side widing through the secondary rectifier diode. Now the secondary
rectifier diode (D1) will conduct, and the magnetizing energy in the core will now transfer to the
secondary side during the reset interval.
This current will decrease from it’s peak value to zero, as shown in the diagram (ISEC). In this period
the complete stored energy in the primary inductance will be transferred to the secondary side
(neglecting losses), before the next store cycle starts. The secondary voltage (VSEC) is “reflected” back
(VR) through the transformer turns ratio to the primary winding and added to the input voltage
(VDC IN + VR). Additional transient voltage may appear on the primary winding due to energy stored in
uncoupled “leakage” inductance in the primary winding which isn’t clamped by the secondary side
winding. If the flyback current does not reach zero before the next “on” – Cycle the converter is
operating in continous current mode. When this system reverts to the continous operation, the transfer
function is changed to a two pole system with low output impedance and additional design rules
become important.
Page 2 of 28 AN-SMPS-1683X – 1
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VDC IN min + VR
VDC IN
Voltage
VDC IN min
Current
IPEAK IPEAK
ISEC ISEC
t ON
Fig. 1 Duty Cycle: D=
T
Page 3 of 28 AN-SMPS-1683X – 1
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Circuit Diagram:
Fig. 2
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Procedure Example
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æ V ö æ 100V ö
ç arcsin DC min ç arcsin
TD = 5ms ⋅ ç1 + T D = 5ms • ç1 +
V DC min PK 120V = 8,1ms
(Eq 6)
ç 90 ç 90
ç ç
è è
2 ⋅ WIN 2 ⋅ 0,41Ws
CIN = (Eq 8) CIN = = 185µF
V 2
DC min PK − V DC
2
min 14400V 2 − 10000V 2
2 ⋅ WIN 2 ⋅ 0,41Ws
VDC min = VDC
2
min PK − (Eq 9) VDC min = 14400V 2 − = 99,2V
C IN 180 µF
Page 6 of 28 AN-SMPS-1683X – 1
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D max 0,5
I LRMS = I LPK ⋅ (Eq 11) I LRMS = 2,02 A ⋅ = 0,83 A
3 3
LP 246µH
NP = (Eq 13) NP = = 31,75 turns
AL 244nH
we choose Np = 32 turns
Page 7 of 28 AN-SMPS-1683X – 1
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4 ⋅ π ⋅10 −7 ⋅ N P2 ⋅ Ae 4 ⋅ π ⋅ 10 −7 ⋅ 32 2 ⋅ 83mm 2
s= (Eq 19) s= = 0,43mm
LP 250µH
Winding Design:
AN ⋅ BWe
ANe = (Eq 21)
BW
Page 8 of 28 AN-SMPS-1683X – 1
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Copper space factor fCu :0,2 ....0,4 We calculate the available area for each winding:
Used for calculation: fCu =0,3
AWG = 9,97 ⋅ (1,8277 − (2 ⋅ log(d ))) (Eq 23) diameter dp ≈ 0,64mm 22 AWG
BWe 12,1mm
NP = (Eq 26) NP = = 17 turns per layer
dP 0,64mm
2 layer needed
Secondary:
12,1mm
NS = = 4 turns per layer
2 ⋅ 0,8mm
Auxiliary:
Can be neglected !
Page 9 of 28 AN-SMPS-1683X – 1
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æ N ö æ 4ö
VRDiode = VOUT + ççV DC max PK ⋅ S (Eq 27) VRDiode = 12V + ç 382V ⋅ = 59,8V
è NP è 32
NP 32
I SPK = I LPK ⋅ (Eq 28) I SPK = 1,98 A ⋅ = 15,8 A
NS 4
Output Capacitors (C5 & C9): To calculate the output capacitor, it is necessary to fix
the maximum voltage overshoot in case of switching
off @ maximum load condition.
Output capacitors are highly stressed in flyback After switching off the load, the regulation loop needs
converters. Normally the capacitor will be selected for about 5...10 periods of internal clock to reduce the
3 major parameters: capacitance value, low ESR duty cycle.
and ripple current rating.
The following types are preferred: We select 470µF 25V (based on Eq 30):
Page 10 of 28 AN-SMPS-1683X – 1
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1 1
f ZCOUT = (Eq 31) f ZCOUT = = 5,6kHz
2 ⋅ π ⋅ R ESR ⋅ COUT 2 ⋅ π ⋅ 0,06Ω ⋅ 470µF
RESR 0,06Ω
LOUT = (Eq 32) LOUT = = 0,57 µH
2 ⋅ π ⋅ f ZCOUT ⋅ n pCOUT 2 ⋅ π ⋅ 5,6kHz ⋅ 3
VCC – Supply:
Page 11 of 28 AN-SMPS-1683X – 1
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(R10/C12/D3)
VSnub = V( BR ) DSS − VDC max − VR (Eq 35) VSnub = 650V − 382V − 100V = 168V
Page 12 of 28 AN-SMPS-1683X – 1
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Calculation of Losses:
PCu = I LPK
2
⋅ DMAX ⋅ 1 ⋅ RCu (Eq 40) PPCu = (1,98 A) 2 ⋅ 0,5 ⋅ 1 ⋅ 114,3mΩ = 74,7mW
3 3
1 − Dmax 1 − 0,5
PDDIODE = I SPK ⋅ ⋅ V FDIODE (Eq 41) PDDIODE = 15,8 A ⋅ ⋅ 0,7V = 4,52W
3 3
COOLMOS TRANSISTOR:
TDA16834
Calculated @ VDCmin = 99V
CO ≈ 50pF (CO = COSS + CExtern)
RDSON = 1,6Ω (@ 150°C) (see also TDA 16831 ... 34 Data Sheet)
Switching losses:
PSON = 1 ⋅ C O ⋅ VDC
2
min ⋅ f (Eq 42) PSON = 1 ⋅ 50 pF ⋅ 99V 2 ⋅ 100 *10 3 Hz = 24,5mW
2 2
PSOFF = 1 ⋅ (VDC min + VR ) ⋅ I LPK ⋅ f ⋅ t r (Eq 43) PSOFF = 1 ⋅ (99V + 100V ) ⋅ 2,02 A ⋅100kHz ⋅ 30ns = 197mW
6 6
Conduction losses:
PD = 1 ⋅ R DSON ⋅ I LPK
3
2
⋅ Dmax (Eq 44) PD = 1 ⋅ 1,6Ω ⋅ (1,98 A) 2 ⋅ 0,5 = 1,05W
3
Page 13 of 28 AN-SMPS-1683X – 1
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Summary of Losses:
PLosses = PSON + PSOFF + PD (Eq 44a) PLosses = 25,4mW + 197mW + 1005mW = 1,27W
Thermal Calculation:
K
Table of typical thermal Resistance [ ]:
W
Heatsink DIP8 SO14
No 90 112
3 cm² 64 92
6 cm² 56 78
K
dT = PLosses * Rth (Eq 44b) dT = 1,27W * 56 = 71,2 K
W
Tj = dT + Ta (Eq 44c) Tj = 71,2 K + 50°C = 121°C
Page 14 of 28 AN-SMPS-1683X – 1
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Primary side: R3 R4 R1
Feedback voltage: R5
Values from TDA16831...34 datasheet
VRef int = 5.5V typ. C1
VFBmax = 4,8V C2
RFB = 3,7k typ.
TL431 R2
Fig. 4
æV ö æ 12V ö
R1 = R2 çç OUT − 1 (Eq 47) R1 = 4,7k ⋅ ç − 1 = 17,86k
è VREF è 2,5V
the value of R2 can be fixed at 4,7k
æ I ö æ 0,2mA ö
V FD + ç R3 ⋅ FB min 1,2V + 910 R ⋅ ç
è Gc è 1
R4 ≤ (Eq 49) R 4 ≤ = 1,4k ≈ 1,2k
I KA min 1mA
Page 15 of 28 AN-SMPS-1683X – 1
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Regulation Loop:
KFB KVD
Fr(p)
+
Fig. 5
Vref
GC ⋅ 3k 7
K FB = Feedback
R3
R2 V
K VD = = REF Voltage Divider
R1 + R 2 VOUT
æ ö
ç
1 L P ⋅ f ⋅ η ç R L (1 + p ⋅ R ESR ⋅ C 5 )
FPWR ( p ) = ⋅ ⋅ç Power stage
Z PWM 2 ⋅ RL ç æç1 + p ⋅ æç R L + R ö÷ ⋅ C ö÷
çç è 2
ESR 5÷
èè
ZPWM = Transimpedance ∆VFB/∆ID
1 + p ⋅ R ESR ⋅ C 9
FLC ( p) = Output filter
1 + p ⋅ R ESR ⋅ C 9 + p 2 ⋅ L ⋅ C 9
1 + p ⋅ R5 ⋅ (C1 + C 2 )
Fr ( p) = Regulator
R1 ⋅ R 2
p⋅ ⋅ C1 ⋅ (1 + p ⋅ R5 ⋅ C 2)
R1 + R 2
Page 16 of 28 AN-SMPS-1683X – 1
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2 2
VOUT 12V 2 VOUT 12V 2
RLH = = = 3,6Ω RLL = = = 144Ω
POUT max 40W POUT min 1W
1 1
f OH = f OH = = 62,7 Hz
π ⋅ R LH ⋅ C 5 π ⋅ 3,6Ω ⋅ 1410µF
1 1
f OL = f OL = = 1,57 Hz
π ⋅ RLL ⋅ C 5 π ⋅ 144Ω ⋅ 1410µF
The gain (Gc) of the optocoupler stage KFB and the voltage divider KVD we use as a constant.
GC ⋅ 3k 7
K FB = KFB = 6,6 GFB = 16,4db
R3
R2 V
K VD = = REF KVD = 0,208 GVD = -13,6db
R1 + R 2 VOUT
With adjustment of the transfer characteristics of the regulator we want to have equal gain within the
operating range and to compensate the pole fo of the powerstage FPWR(ω).
Because of the compensation of the output capacitors zero (see page 11 Eq31, Eq32) we neglect this zero
and the LC-Filter pole.
So the transfer characteristics of the power stage is reduced to a single pole response.
In order to calculate the gain of the open loop we have to select the crossover frequency.
We calculate the gain of the Power-Stage with max. output power at the selected crossover frequency
fg = 3kHz:
− t ON − t ON
é ù é ù
Z PWM (t ON ) = Z PWM ⋅
1
⋅ êt ON − T 1 + T 1 ⋅ e T 1 ú + 0, 6 ⋅ ê 1 − e T2
(formula according data sheet p. 12)
t ON êë ú êë
Page 17 of 28 AN-SMPS-1683X – 1
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−4 , 7 µs −4 , 7 µ s
é ù é ù
Z PWM (t ON ) = 1,3 ⋅
V 1 V
⋅ ê4,7 µs − 850ns + 850ns ⋅ e 850 ns
ú + 0,6 ⋅ ê1 − e
200 ns
= 1,7
A 4,7 µs ë ë A
æ ö
ç
1 RL ⋅ L p ⋅ f ⋅ η ç 1
FPWR ( fg ) = ⋅ ⋅ç
Z PWM 2 ç 2
ç 1 + æç fg ö÷
ç ç fo ÷
è è
æ ö
ç
1 3,6 R ⋅ 250µH ⋅ 100kHz ⋅ 0,8 ç 1
FPWR (3kHz ) = ⋅ ⋅ç = 0,073
1,7 2 ç æ 3000 ö
2
çç 1 + ç ÷
è è 62,7
GPWR(3kHz) = -22,7db
Transfer characteristics:
50
50
Gr(ω)
G PWR ( ω )
Gain GFB
[db]
Gr( ω )
G FB 0
GVD
G MOD
0
GPWR(ω)
50 50
3 4 5
1 10 100 1 10 1 10 1 10
1 ω( i) 5
Fig. 6 1. 10
2. π
Page 18 of 28 AN-SMPS-1683X – 1
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At the crossover frequency (fg) we calculate for the open loop gain:
With the equations of the transfer characteristics we calculate the gain of the regulation loop @ fg.
Gs = -19,9db
1 + p ⋅ R5 ⋅ (C1 + C 2) )
Fr ( p) =
R1 ⋅ R 2
p⋅ ⋅ C1 ⋅ (1 + p ⋅ R5 ⋅ C 2)
R1 + R 2
R5 ⋅ (R1 + R 2 ) R1 ⋅ R 2
Gr
Gr = 20 ⋅ log R5 = 10 20
⋅
R1 ⋅ R 2 R1 + R 2
20, 9
R5 = 10 20
⋅ 3,72k = 41,7k ≈ 43k
1 1
fp = C2 = fp = 2*fg
2 ⋅ π ⋅ R5 ⋅ C 2 2 ⋅ π ⋅ R5 ⋅ 2 ⋅ fg
1
C2 = = 617 pF ≈ 680pF
2 ⋅ π ⋅ 43k ⋅ 6kHz
In order to have enough phase margin @ low load condition we select the zero frequency of compensation
network at the middle between min. and max. load pole of power stage.
f ol 1, 57
0 , 5⋅log 0 , 5⋅log
f om = f oh ⋅ 10 f oh
f om = 62,7 Hz ⋅ 10 62, 7
= 9,92 Hz
1 1
fz = C1 = − C2
2 ⋅ π ⋅ R5 ⋅ (C1 + C 2) 2 ⋅ π ⋅ R5 ⋅ fom
1
C1 = − 680 pF = 384nF ≈ 390nF
2 ⋅ π ⋅ 43k ⋅ 9,92 Hz
Page 19 of 28 AN-SMPS-1683X – 1
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70
50
Gr( ω )
Gs( ω )
G( ω ) 0
50
60
3 4 5
1 10 100 1 10 1 10 1 10
1 ω( i) 5
1. 10
2. π
Fig. 7
10 10
28
φr( ω )
66
φs( ω )
φ( ω )
104
0
142
180 180
3 4 5
1 10 100 1 10 1 10 1 10
1 ω( i) 5
1. 10
2. π
Fig. 8
Page 20 of 28 AN-SMPS-1683X – 1
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Transformer Construction
The winding topology has a considerable influence on the performance and relaibility of the
transformer.
To reduce leakage inductance and proximity to acceptable limits, the use of a sandwich construction is
recommended.
In order to meet international safety requirements a transformer for Off - Line power supply must have
adequate insulation between primary and secondary winding.
This can be achived by using a margin wound construction or using triple insulated wire for the
secondary winding.
The creepage distance for universal input voltage range is typically 8mm. This sets a minimum margin
width as a half of the creepage distance to 4mm. Additional the neccesary insulation between primary
and secondary winding is provided using three layers of basic insulation tape.
BW*
BWe
Primary
Creepage second half
distance
Secondary
Triple insulation
Auxiliary
Primary
first half
margin margin
Fig. 9
Example of winding topology with triple insulated wire for secondary winding:
BW*
Primary
second half
Triple Insulated
Wire Secondary
Auxiliary
Primary
first half
Fig. 10
Page 21 of 28 AN-SMPS-1683X – 1
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Layout Recommendation:
Fig. 11
In order to avoid crosstalk between Power- and Signal-Path on the board we have to use care
regarding the track layout when designing the PCB.
The Power-Path (see Fig. 11) has to be as short as possible and separated from the VCC-Path and
the Feedback-Path. All GND-Paths have to be connected together at pin 8 (star ground) (1 and 14 at
G-type) of TDA16831...34.
Page 22 of 28 AN-SMPS-1683X – 1
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The conduction losses are calculated with the typical RDSON @ Tj = 125°C (see Data Sheet TDA 1683x
page 13). The OFF switching losses are calculated with a typical fall time of tf = 50 ns (see Data Sheet
TDA 1683x page 13), the ON switching losses with the effective capacitance (+ estimated external
capacitances) of the used device (see also Data Sheet TDA 1683x page 13).
*The current limitation regulates the output power (see Data Sheet TDA 1683x page 13)
** The power losses are spitted in switching losses (CoolMOS) and conduction losses. It´s depending
on VDCin witch part on losses having more impact of the power losses (Chart: Select your device).
1,60
1,40
1,20
Small – Range
1,00
Power Losses [W]
0,80
0,60
0,40
0,20
0,00
90 115 140 165 190 215 240 265 290 315 340 365
Input Voltage - Vdcin [V]
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References
Revision History
Application Note AN-SMPS-1683X-1
Actual Release: V1.2 Date:11.05.2000 Previous Release: V1.1
Page of Page of Subjects changed since last release
actual prev. Rel.
Rel.
28 21 Formatting
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For questions on technology, delivery and prices please contact the Infineon
Technologies Offices in Germany or the Infineon Technologies Companies and
Representatives worldwide: see the address list on the last page or our webpage at
http://www.infineon.com
Edition 2000--05--11
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
D-81541 München
© Infineon Technologies AG 2000.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as warranted characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts
stated herein.
Infineon Technologies is an approved CECC manufacturer.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in
Germany or our Infineon Technologies Representatives worldwide (see address list).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your
nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon
Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the
safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support
and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be
endangered.
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