LAB 4

1) Optimum form of boolean expression: SOP Form with 2-input-NAND-only

implementation.

F = AD + AB + BD + A’B’D’

2) Gate-level modelling Style:

a) Program:
module P2_Lab4_demo_module (F, D, C, B, A);
output F;
input D, C, B, A;
wire w1, w2, w3, w4, w5, w6, w7, w8, w9, w10, w11, w12, w13;

nand
G1(w1, A, A),
G2(w2, D, D),
G3(w3, B, B),
G4(w4, w3, w2),
G5(w5, w4, w4),
G6(w6, w1, w5),
G7(w7, B, A),
G8(w8, w7, w6),
G9(w9, w8, w8),
G10(w10, D, A),
G11(w11, D, B),
G12(w12, w10, w11),
G13(w13, w12, w12),
G14(F, w13, w9);
endmodule

b) Testbench:
module tb_P1_Lab4_demo;
wire F;
reg [0:3]tb_input;
 P1_Lab4_demo_module demo1(F, tb_input[3], tb_input[2], tb_input[1],
tb_input[0]);
initial
begin
tb_input = 4'b0000;
repeat(15)
#50 tb_input = tb_input + 4'b0001;
end

initial
begin
$monitor("A = %b B = %b C = %b D = %b | Output F = %b",
tb_input[0], tb_input[1], tb_input[2], tb_input[3], F);
end

initial #800 $finish;

endmodule

c) Output (Transcript):
3) Dataflow modelling Style:
a)Program:
module P1_Lab4_demo_module (F, D, C, B, A);
output F;
input D, C, B, A;

assign F = ( (D & A) | (D & B) | (B & A) | (~D & ~B & ~A) );

endmodule

b) Testbench:
module tb_P1_Lab4_demo;
wire F;
reg [0:3]tb_input;
 P1_Lab4_demo_module demo1(F, tb_input[3], tb_input[2], tb_input[1],
tb_input[0]);

initial
begin
tb_input = 4'b0000;
repeat(15)
#50 tb_input = tb_input + 4'b0001;
end
initial
begin
$monitor("A = %b B = %b C = %b D = %b | Output F = %b",
tb_input[0], tb_input[1], tb_input[2], tb_input[3], F);
end

initial #800 $finish;

endmodule
 c) Output (Transcript):

4) Wave form: for A = 1 B = 1 C = 1 D = 0 | F = 1