210 ACTIVE FILTERS
ACTIVE FILTERS
An electrical filter may be defined as ‘‘a transducer for sepa-
rating waves on the basis of their frequencies’’ (1). There are
numerous everyday uses for such devices ranging from the
filter that allows one to select a particular radio station, to
the circuit that detects brainwaves, to resonant cavities that
operate at microwave frequencies. Indeed, filters are needed
for operation across the electromagnetic spectrum. Further-
more, they are required to perform frequency selection to sat-
isfy various specialized approximating functions, not neces-
sarily confined to the conventional low-pass, bandpass, high-
pass, and band-stop forms.
However, the purpose of this article is to focus on a partic-
ular category of filter, the active filter, whose evolution over
the past 40 years has been heavily influenced by advances in
microelectronic circuit fabrication. The earliest active filters
were motivated by the need to overcome significant limita-
tions of inductor–capacitor (LC) passive filters, namely:
1. In the audio band, inductors are bulky and prone to
pick up.
2. Resistor–capacitor (RC) filter structures offer a limited
range of responses and are subject to substantial pass-
band attenuation.
By contrast, active RC structures can realize (theoreti-
cally) lossless filter characteristics in miniaturized form. Pas-
sive and active filter properties are summarized in Table 1.
A disadvantage of the active filter is its need for a power
supply and the incorporation of one or more active elements,
usually operational amplifiers. As a result, highly selective
filters need careful design so as to avoid instability. However,
as active filter design has matured, a small number of highly
reliable topologies have evolved that provide solid perfor-
mance across a variety of fabrication technologies.
The earliest active filters used discrete components and
were based upon direct synthesis of RC sections with appro-
priately embedded active devices such as the negative imped-
ance converter (2). Second-order sections were then cascaded
to form higher order structures.
Subsequently, a catalog of building blocks was developed
by Sallen and Key (3), which led to a much broader interest
in active filters. This was due in no small part to removal of
the need for classical synthesis expertise.
However, widespread use of active filters was still inhib-
ited by concerns over sensitivity, particularly when compared
to the passband performance of passive filters. This was over-
come by the simulation of the floating inductor (4) and the
widespread availability of operational amplifiers whose high-
Table 1. Comparison of Active and Passive Filter Properties
Audio Band Filters
LC Active RC
Bulky Small
Lossy (low Q) Lossless (high Q)
Stable (absolutely) Stability depends upon design
Transmission loss Capable of transmission gain
J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.
quality performance and low cost resulted in a fundamental
change in design philosophy.
Designers, previously cost-constrained to single-amplifier
second-order sections, were now able to consider multiampli-
fier sections whose performance and multipurpose functions
made commercial production a viable proposition. In particu-
lar, the state variable topology (5) formed the basis for a uni-
versal filter yielding all basic filtering functions from a sin-
gle structure.
Inductor replacement and direct simulation techniques
such as the leapfrog approach (6) offered low-sensitivity ana-
logs of classical LC filters. The difficulty in tuning these de-
vices was simplified enormously by the introduction of com-
puter-controlled laser trimming using hybrid microelectronics
technology. Indeed, by the mid-1970s, sophisticated fifth-or-
der elliptic characteristic filters were in large-scale production
within the Bell System (7).
Thus, over a period of 20 years (1954–1974), active filter
designers had come to rely upon a relatively small number of
basic building blocks to form second-order sections, or were
basing higher-order designs on analogs of LC structures. Al-
though many realizations used discrete components, larger-
scale production of thick and thin film hybrid microelectronic
structures was quite common.
The advent of switched-capacitor filters in 1979 (8) over-
came the need to laser trim resistors and yielded the first
fully integrated active filters. While truly a sampled-data
technique, the use of sufficiently high clock frequencies meant
that active filters could be used up to 100 kHz, far higher
than by conventional analog techniques. Subsequent develop-
ments have led to metal-oxide semiconductor field-effect tran-
sistor-capacitor (MOSFET-C) and operational transconduc-
tance amplifier-capacitor (OTA-C) filters (9) which yield
authentic analog performance at frequencies exceeding 1
MHz.
The following sections will concentrate on a few fundamen-
tal filter design techniques that form the basis for modern
active filter design. The Sallen and Key, multiple loop feed-
back, and state variable structures have stood the test of time
and have proven to be as effective in discrete component real-
izations as they have in MOSFET-C structures. They all form
higher-order filters when cascaded with similar sections. Fi-
nally, the leapfrog design and direct replacement techniques
are discussed as examples of direct higher-order filter syn-
thesis.
SECOND-ORDER STRUCTURES
The fundamental building blocks for active RC filters are sec-
ond-order structures which can readily be cascaded to realize
higher-order approximating functions described by the gen-
eral voltage transfer function:
 
ωz
s2 + s + ωz2
Vo Qz
=H·  (1)
Vi ωp
s2 + s + ωp2
Qp
where 웆z, Qz and 웆p, Qp refer to the zero and pole frequency
and Q, respectively. All-pole functions (low-pass, bandpass,
high-pass) occur when only one of the numerator terms (s0,
 ACTIVE FILTERS 211

G2
3 G1 C2
1 RC 2 K
K
network
V1 C1 G3 V3
V1 V3

Figure 2. Sallen and Key second-order bandpass filter using posi-

Figure 1. Sallen and Key structure consisting of a controlled source tive-gain controlled source.
and an RC network. Appropriate choice of the RC network yields all
basic forms of second-order transfer functions.
Table 2 illustrates four topologies and the resulting voltage
transfer function when that RC structure is used in the cir-
s1, or s2) is present. A notch occurs when the s1 term disap- cuit of Fig. 1. Thus, it is seen that low-pass and high-pass
pears in the numerator. We will not discuss the more general sections can be achieved with a positive-gain controlled
case (10) that arises when all numerator terms are present source, whereas the two bandpass sections require a negative-
simultaneously. gain controlled source (11).
The topologies that follow are suitable for design using dis- Although not included in the original catalog, the five-ele-
crete, hybrid, or fully monolithic fabrication. Furthermore, ment bandpass circuit of Fig. 2, which utilizes a positive-gain
they have stood the test of time for ease of design, tuning controlled source, is now generally incorporated under the
simplicity, and relatively low cost. Sallen and Key banner. In this case:

Sallen and Key KG1

s
V3 C1
Sallen and Key originally proposed (3) a family of all-pole fil- =   (3)
ters based upon the circuit shown in Fig. 1, for which V1 G 2 (1 −K) (G 1 +G 3) G G (G +G2 )
s2 + + + 3 s+ 3 1
C1 C1 C1 C1C2
V3 −Ky21
= (2)
V1 y22 + Ky23 Design is most commonly restricted to the positive-gain
controlled source realizations, despite the inherent positive
By appropriate choice of the passive RC network, it is possible feedback used to enhance Qp. In general, if realizations are
to realize all forms of basic filter. However, because the cre- restricted to Qp ⱕ 10, the advantages of the lower component
ation of a band-stop (notch) section requires the use of twin T spread in this design outweigh the stability considerations.
networks, which are inherently difficult to tune, we confine Design is relatively straightforward and proceeds by coeffi-
our discussion to the realization of all-pole functions. cient matching.

Example 1. For our example, we design a second-order low-

Table 2. Sallen and Key Realizations pass Chebyshev filter having 0.5 dB passband ripple and a
Circuit
passband gain of 20 dB. From the standard tables (12–15),
No. RC Structure Voltage Transfer Function
a the normalized transfer function is

冢 冣
3 KG1G2 V3 H
C1 C1C2 = 2 (4)
1 1 2 V1 s + 1.426s + 1.516
冦 冧
G1 G2 C2 G2 G1 + G2 KG2 G1G2
s2 + s + — +
C2 C1 C2 C1C2
A passband gain of 20 dB is equivalent to an absolute gain of
3 10, so that H ⫽ 15.16. By matching the low-pass expression
G1 Ks 2 from Table 2 and the coefficients of Eq. (4), we obtain
冦 冧
2 1 2 G2 G2 G1 G1G2
s2 +s + + (1 — K ) +
C1 C2 G2 C2 C1 C1 C1C2 KG1 G2
= 15.16 (5a)
C1C2

冢 冣
3 KG2 G1 G2
G1 s
C2 = 1.516 (5b)
3
C1C2
1 2

冦 冧 G + G2
C1 G2 C2 G2 G1 + G2 G1G2 G2 KG2
s2 + s + + (1 — K )
C2 C1 C1C2 + 1 − = 1.426 (5c)
C2 C1 C2

冢 冣
3 KG1
C1 s
(1 — K )C1 Thus, K ⫽ 10 [from Eqs. (5a) and (5c)]. The remaining two
4 1 2 equations contain four unknowns, indicating freedom of
冦 冧
G1 C2 G2 s G1 G2 G2 G1G2
s2 + + + + choice for two of the elements. Such freedom of choice is a
(1 — K ) C1 C1 C2 (1 — K )C1C2
a
characteristic of the coefficient-matching technique. For con-
K > 0 for circuits 1 and 2, K < 0 for circuits 3 and 4. venience, set C1 ⫽ C2 ⫽ IF, since this is highly desirable in
212 ACTIVE FILTERS

Table 3. MFB Structure and Voltage Transfer Functions

Filter Type Network Voltage Transfer Function

3
1 RC 2 G4 C5
– — —G1G3
network (a) Low-pass +
+ G1 G3 s 2C2C5 + sC5(G1 + G3 + G4) + G3G4
C2
V1 V3

C4 G5
— —s 2C1C3
(b) High-pass C1 C3 +
Figure 3. Multiple feedback (MFB) structure consisting of an opera- s 2C3C4 + sG5(C1 + C3 + C4) + G2G5
G2
tional amplifier and an RC network. Appropriate choice of the RC
network yields all basic forms of second-order transfer functions.

C4 G5
— —sG1C3
(c) Bandpass G1 C3 +
many practical realizations. As a result, G2
s 2C3C4 + sG5(C3 + C4) + G5(G1 + G2)

G1 G2 = 1.516 (6a)
G1 − 8G2 = 1.426 (6b)

The only solution yielding positive values is G1 ⫽ 4.268 S and

G2 ⫽ 0.355 S. Impedance and frequency denormalization can
be applied, depending upon specific design requirements.
Realization of the basic low-pass Sallen and Key filter has
been widely discussed in the literature (11). Popular alterna-
tives to the C1 ⫽ C2 ⫽ IF used above are as follows:
1. Setting C1 ⫽ C2 ⫽ C, G1 ⫽ G3 ⫽ G, and K ⫽ 3 ⫺ (1/Q)
2. Setting K ⫽ 1 (thereby eliminating two gain-setting re-
sistors), G1 ⫽ nG3 and C1 ⫽ mC2
3. Setting K ⫽ 2 (for equal-valued gain-setting resistors),
C1 ⫽ C2 ⫽ C and G3 ⫽ Q2G1
Multiple Feedback Structure
stable, negtive-feedback circuit. Specific realizations of the
all-pole functions are shown in Table 3.
As for Sallen and Key sections, design proceeds by coeffi-
cient matching. A widely used design set is illustrated in Ta-
ble 4, for which both bandpass and high-pass circuits use
equal-valued capacitors. No such solution is possible for the
low-pass circuit, though an equal-valued resistor pair is pos-
sible.
Although highly stable, the MFB structure has a pole Q
dependent upon the square root of component ratios. Thus,
for a Qp of n, the maximum component spread will be propor-
tional to n2. As a result, the MFB arrangement is best suited
to modest values of Qp, typically not greater than 10.

The multiple feedback (MFB) structure (16) is derived from

the general feedback configuration of Fig. 3, in which the ac-
tive element is an ideal operational amplifier.
The most common realization of the RC network is shown
in Fig. 4, which yields the MFB transfer function
V3 −Y1Y3
= (7)
V1 Y5 (Y1 + Y2 + Y3 + Y4 ) + Y3Y4
Modified Multiple-Loop Feedback Structure
In positive-feedback topologies such as the Sallen and Key,
Qp is enhanced by subtracting a term from the damping (s1)
coefficient in the denominator. By contrast, in negative-feed-
back topologies such as the MFB, high values of Qp are ob-
tained at the expense of large spreads in element values. The
two techniques are combined in the modified multiple-loop

The basic all-pole functions can be realized by single-element

replacement of the admittances Y1 씮 Y5, yielding a highly

Table 4. Element Values for MFB Realizations (H is the

3 Numerator Constant in Each Case)
Element Value
Bandpass High-pass Low-pass
Y4 Y5 G1 ⫽ H C1 ⫽ H H
Y1 Y3 G1 ⫽
1 2 웆p
G2 ⫽ 2웆p Qp ⫺ H G2 ⫽ 웆p(2 ⫹ H)Qp Qp(2웆2p ⫹ H)
C2 ⫽
웆2p
Y2 C3 ⫽ 1 C3 ⫽ 1 G 3 ⫽ 웆p
C4 ⫽ C 3 C4 ⫽ C 3 G4 ⫽ G 3
웆p 웆p 웆2p
Figure 4. Three-terminal, double-ladder structure for use in MFB G5 ⫽ G5 ⫽ C5 ⫽
2Qp Qp(2 ⫹ H) Qp(2웆2p ⫹ H)
sections.
 ACTIVE FILTERS 213

versatility and ease of tuning. The advent of the operational

C4 amplifier eliminated earlier cost concerns, and the ability to
G5
G1 realize relatively high-Q sections remains an attractive con-
– sideration. However, it is the ability of the circuit to yield all
+ basic forms of second-order sections by appropriate choice of
C3
output terminal that has made it so popular for commercial
Vi Vo manufacture (19). Custom filters are readily fabricated by ap-
Gb propriate interconnection of terminals, yielding the universal
Ga
filter terminology of several vendors. In particular, highly re-
liable notch filters are possible through the addition of a sum-
ming amplifier to the basic three-amplifier array.
Figure 5. Modified multiple-loop feedback (MMFB) structure due to The circuit shown in Fig. 7 is an example of a state-vari-
Deliyannis which yields a second-order bandpass function. By judi- able section and can be recognized as an analog computer re-
cious use of positive feedback, this circuit reduces the large compo- alization of a second-order differential equation. It is more
nent spreads which are characteristic of the MFB structure while commonly referred to as the Huelsman-Kerwin-Newcomb
yielding greater stability margin than the Sallen and Key ar- (HKN) filter (5). In the frequency domain it is capable of yield-
rangement. ing a variety of voltage transfer functions, according to the
particular output connections used. Assuming ideal opera-
tional amplifiers, the specific transfer functions are as follows:
feedback (MMFB) circuit (17) of Fig. 5, for which
1. The low-pass response with
Vo −sC3 G1 (1 + k)
= 2 (8)  
Vi s C3C4 + s{G5 (C3 + C4 ) − kC3 G1 } + G1 G5 V1 R2 [R3 + R10 ]
= D(s) (9a)
Vi R3 [R1 + R2 ]
where k ⫽ Gb /Ga, and the Q-enhancement term signifies the
presence of positive feedback.
Design of this bandpass circuit proceeds by coefficient 2. The bandpass response with
matching, although the reader is advised to adopt the step-  
by-step procedure developed by Huelsman (11). V2 R2 [R3 + R10 ]
= −R9C2 s D(s) (9b)
A generalization of the MMFB circuit, yielding a fully bi- Vi R3 [R1 + R2 ]
quadratic transfer ratio has been developed by Friend et al.
(18), as shown in Fig. 6. This arrangement was used exten- 3. The high-pass response with
sively in the Bell System where the benefits of computer-con-

trolled (deterministic) laser trimming techniques and large- V3 R (R + R10 )
scale manufacture were utilized. Although this resulted in = 2 3 C C R R s2 D(s) (9c)
Vi R3 (R1 + R2 ) 1 2 8 9
quite exacting realizations using tantalum thin-film technol-
ogy, the structure is less suited to discrete component realiza-
where
tions. An ordered design process based upon coefficient
matching is presented elsewhere by Huelsman (15).  
R1 (R3 + R10 ) R
D(s) = C1C2 R8 R9 s2 + C2 R9 s + 10
R3 (R1 + R2 ) R3
State Variable Structure
Based upon analog computer design techniques, the state A general biquadratic function may be obtained by combin-
variable (SV) structure (5) assumed popularity because of its ing the various outputs via a summing network, as shown in
Fig. 8. The composite voltage transfer function then becomes

C2 Vo R (R + R3 )R5 (R6 + R7 )
= 2 10
Vi (R1 + R2 )R3 (R4 + R5 )R7
R2    

 [R4 + R5 ]R6 R4 


 C1C2 R8 R9 s +
2
R9C2 s + 
 (10)
R4 C1 R [R + R7 ] R5
·  5 6 
– 
 R1 [R3 + R10 ] R10 

 C1C2 R8 R9 s2 +
 C2 R9 s + 

R6 R3 [R1 + R2 ] R3
+
Rc
Now consider the design of a low-pass response
Vi Rb Vo
H
R5 R7 RD T (s) = (11)
s2 + (ωp s/Qp ) + ωp2

It is clear from Eqs. 9(a) and (10) that there is considerable

Figure 6. The Friend biquad which generalizes the MMFB structure flexibility in the design since there are nine passive compo-
of Fig. 5 so as to yield biquadratic filters. nents and only three specified variables in Eq. (11).
214 ACTIVE FILTERS

V3 (high-pass)

R10 C1 C2

R3
– R9
– – Vi
Vi + R8 (low-pass)
+ +
R1
R2

Figure 7. State variable filter capable of yielding

a variety of all-pole second-order transfer func- V2
tions. (bandpass)

The design equations are thus Setting C ⫽ IF and R8 ⫽ R9 ⫽ R⬘ yields the following simpli-
 fied equations
R10
ωp = (12a) 1
R3 R8 R9C1C2 ω2p = (14a)
 R2
R10  
· C1C2 R8 R9 1 R
R3 Qp = 1+ 2 (14b)
Qp =   (12b) 2 R
R1 (R3 + R10 )
· R9C2
R3 (R1 + R2 ) 2R2 /R
H=   (14c)
R
R2 (R3 + R10 ) 1 + 2 R2
H= (12c) R
R3 (R1 + R2 )C1C2 R8 R9
Therefore, the design equations are
Selecting C1 ⫽ C2 ⫽ C and R1 ⫽ R3 ⫽ R10 ⫽ R gives

ωp = (R8 R9C2 )−1/2 (13a) 1

R = (15a)
 ωp
(R + R2 ) R8
Qp = (13b) R2
2R R9 + 2Qp − 1 (15b)
R
2R2
H= (13c)
(R + R2 )C2 R8 R9 The gain constant, H, is fixed as [2 ⫺ (1/Qp)]웆p2.

R10 C1 C2
V3 V2
R3
– R9
– – V1
Vin + R8 + +
R1
R2

R6

R7
–
Vout
+
Figure 8. Composite state variable structure. R4
The addition of an output summing network to
the arrangement of Fig. 7 yields fully biquad-
R5
ratic transfer functions.
 ACTIVE FILTERS 215

Example 2. Here we design a state-variable filter satisfying HIGHER-ORDER REALIZATIONS

the following normalized elliptic function characteristic hav-
ing a notch at 1.4 kHz. Higher-order filters may be designed by cascading second-or-
der structures of the form described in the previous section.
H(s2 + ωz2 ) s2 + 1.438664 Odd-order functions are accommodated by the addition of a
T (s) = ω = (16)
s2 +
p
s + ωp2 s + 0.314166s + 1.167222
2 single-pole section or, if combined with a low-Q pole-pair, by
Qp the addition of a third-order section. The section types (Sallen
and Key, MFB, MMFB, SV) may be mixed in a realization so
Thus, 웆z ⫽ 1.199, 웆p ⫽ 1.08038, and Qp ⫽ 3.4389. that the SV is used for higher Q and notch functions. Particu-
Realization requires the use of the summing network to lar care must be taken with the selection of pole-zero pairs
combine the low-pass and high-pass outputs. Since no band- and the ordering of sections due to considerations of dynamic
pass component is required, the left-hand end of resistor R7 range. A fuller discussion of these features is described else-
(Fig. 8) should be grounded. where (20–22).
Now consider the realization of the low-pass section. Set The major advantage of the cascade approach is the ability
R ⫽ C ⫽ 1 and Eqs. 15(a) and (b) to give the normalized to independently tune each pole pair. This is offset to some
component values as degree by the higher sensitivity to component changes and
the care needed to properly order the sections and pair the
C1 = C2 = 1F
poles and zeroes. A widely used alternative bases designs on
R = R8 = R9 = 0.926 the passive LC prototype whose passband sensitivity is mini-
R = 1 so that R1 = R3 = R10 = 1 mal. The most common approaches are described below.
and R2 = 5.878
Inductor Replacement
The gain constant, H, has the value 1.995. The frequency As indicated above, it is highly desirable to base active RC
denormalization factor, 웆n, is filter designs upon passive LC prototypes because of the re-
sulting low passband sensitivity. An added advantage results
2π × 1.4 × 103
ωn = = 7.351 × 103 from the availability of tabulated LC designs (12–15), which
1.199 obviate the need for sophisticated synthesis techniques. Thus,
Assume that available capacitors have a value of 6800 pF. for a given standard approximating function, the LC proto-
Then, the impedance denormalization factor is evaluated as type may be established with the aid of design tables.
The resulting inductors may be replaced by means of an
1 appropriately terminated generalized impedance converter
Zn = = 20 k (GIC). The ideal GIC is shown in Fig. 9, for which
6800 × 10−12 × 7.351 × 103

Therefore, the denormalized values are a11

Z11 = = k(s)ZL (18a)
a22
C1 = C2 = 6800 pF
 a 1
R1 = R3 = R10 = 20 k Z22 = 22 = Z (18b)
 a11 k(s) L
R8 = R9 = 18.7 k standard 1% values


R2 = 118 k if a12 ⫽ a21 ⫽ 0.

The high-pass and low-pass outputs may now be combined

to yield the desired transfer function of Eq. (16). Thus, by
substituting normalized element values into Eq. (10) 1 2
  GIC ZL
Vo 1.709R5 (R6 + R7 ) s2 + 1.1672(R4/R5 ) [a]
= (17)
Vin R7 (R4 + R5 ) s2 + 0.314179s + 1.1672 1′ 2′

The location of 웆z is obtained by appropriate choice of the re- Z11µZL

sistor ratio, R4 /R5. Hence,
(a)
R4
= 1.2326
R5 1 2
ZL GIC
Choosing R5 ⫽ 20 k⍀ gives R4 ⫽ 24.65 k⍀. The dc gain of [a]
the filter is determined by appropriate choice of R6 /R7. If these 1′ 2′
resistors are set equal at 20 k⍀, the resulting dc gain is
5.52 dB. Z22µZL
The filter may be tuned by means of the R4 to R5 ratio to
(b)
locate the notch accurately. In practice, this may be observed
by closing a Lissajous pattern on an oscilloscope. The fre- Figure 9. Generalized impedance converter (GIC). (a) Load at termi-
quency at which this occurs will be 웆z. nal 2. (b) Load at terminal 1.
216 ACTIVE FILTERS

R C1 C2 C3

L1 L2 L3 L4 R
– +

(a)
1 2
Z1 Z2 Z3 Z4
R C1 C2 C3
ZL ZL
– +

R1 R2 R3 R4
Figure 10. Antoniou GIC—the most widely used realization of this
important circuit element.

(b)

The most commonly used realization of the GIC, from An-
toniou (23), is shown in Fig. 10. In this case
Z1 Z3
k(s) =
Z2 Z4
Thus, if we select
1
Z1 = Z3 = Z4 = R and Z2 =
sC
we obtain k(s) ⫽ sk⬘. If ZL ⫽ R1, then
Z11 = sk R1
and we have simulated a grounded inductor whose Q value
far exceeds that of a conventional coil. Indeed, audio band Q
factors of the order of 1000 are readily obtained if high-qual-
ity capacitors are used in the GIC.
Grounded inductor simulation is readily applicable to the
realization of high-pass filters, as illustrated in Fig. 11. Note
that a dot ( • ) is used to denote terminal 1 of the GIC, because
it is a directional device having a conversion factor k(s) from
terminal 1, and 1/k(s) from terminal 2.
The simulation of a floating inductor requires the use of
two GICs, as shown in Fig. 12. However, the simulation of
structures containing several floating inductors can become
undesirable due to the excessive number of active blocks.
Frequency-dependent Negative Resistance
Depending upon the choice of impedances Z1 씮 Z4, the GIC of
Fig. 10 may be used to provide conversion factors of sn, where
n ⫽ ⫾1, ⫾2. If one internal port impedance is capacitive and
the other three are resistive, the conversion factor is k⬘s in
one direction and 1/k⬘s in the other. Use of two internal ca-
pacitors yields k⬙s2 and 1/k⬙s2, respectively. Using the first
combination of elements and a capacitor at port 1 produces a
port 2 impedance given by Z22 ⫽ (1/s2)D, where D is frequency
invariant. At real frequencies, this represents a second-order
Figure 11. High-pass filter realization using direct inductor replace-
ment. (a) Passive prototype. (b) Active realization using resistor-ter-
minated GICs to realize the grounded inductors.
(19)
capacitor, because

 −1
Z22  = (20)
s= jω ω2 D
However, the term frequency-dependent negative resistance
(FDNR) has achieved universal adoption. D is in units of
(farad)2 ⭈ohms and is represented by the symbol shown in
Fig. 13.
A synthesis technique incorporating FDNRs (24) over-
comes the need for floating inductor simulation in LC proto-
types. If the admittances in a network are scaled by a factor
s, neither the voltage nor current transfer ratios are affected,
because they are formed from ratios of impedance or admit-
tance parameters. However, scaling does affect the network
elements as follows:
Admittance Y(s) becomes sY(s) (transformed admittance)
Capacitor sC becomes s2C (FDNR)
Inductor 1/sL becomes 1/L (resistor)
Resistor 1/R becomes s/R (capacitor)
Inductors are thus eliminated and a new, but topologically
equivalent, network is formed.
Example 3. In this example, we realize a doubly terminated
low-pass filter having a fourth-order Butterworth characteris-
kR
ks ks
Figure 12. GIC realization of a floating inductor.
 ACTIVE FILTERS 217

for which, for example, RA may be set at 100 ⍀ so as to avoid

1 loading the capacitor.
Z= ––––
s 2D
D
Denormalization of the circuit is straightforward, noting
that an FDNR of normalized value Dn, is denormalized using
(a) the expression

Dn
D= (21)
ks2 Zn ωn2

R k
–– The FDNR approach is most effective when all inductors
R
are floating. In more complex arrangements, floating FDNRs
result whenever a floating capacitor is present in the original
(b)
prototype. Since the replacement of each floating FDNR re-
quires the use of two GICs, the alternative of partial transfor-
mation (25,26) is preferred.
ks The technique is illustrated in Fig. 15, for which the com-
posite transmission matrix [a⬘] for the three-section cascade
C kC
is given as
 
(c)    a12 k2
1 1 a12  a11 
  a11 1 0  k1 
Figure 13. FDNR symbol and realization. (a) Symbol for FDNR of [a ] =  1  k s n
=   (22)
0
1
0 k 2 sn  
value D. (b) Realization of FDNR by resistively-terminated GIC. (c)
k1 s n k 1 a 21 s n
a 22
 a 22 k 2 
Realization of FDNR by capacitively-terminated GIC. a21
k1

tic. From design tables, we obtain the LC prototype of Fig. Hence, for matched GICs (k1 ⫽ k2), we see that [a⬘] ⫽ [a].
14(a). Transformation yields the so-called DCR network of The technique is illustrated in Fig. 16(a)–(c) for a band-
Fig. 14(b). If biasing problems are encountered due to the pass section. Using direct FDNR realization of Fig. 16(b)
presence of floating capacitors, they may be overcome by the would require a total of five GICs. The partial transformation
addition of shunt resistors, RA and RB, as shown in Fig. 14(c). of Fig. 16(c) reduces the requirement to three GICs. Clearly,
In order to preserve the passband loss of the original network, the savings are more dramatic for higher-order realizations.
these resistors are arranged to yield a dc gain of 0.5. Hence,
Leapfrog Realization
RB
= 0.5 The leapfrog technique (6) was introduced over 40 years ago
RA + 0.7654 + 1.8478
and represents the first of several multiloop feedback simula-
tion methods (27–29). Its simplicity and elegance derives
1Ω 0.7654 H 1.8478 H from a one-to-one relationship between passive reactances in
a ladder structure and integrators in the leapfrog model.
The technique is particularly well suited to the realization
1Ω
1.8478 F 0.7654 F of low-pass responses, which are the most difficult to realize
by direct replacement methods. Although the presence of mul-
(a) tiple feedback loops can render tuning difficult, the close
matching of capacitor ratios and the similarity of the active
1F 0.7654 Ω 1.8478 Ω blocks rendered this approach ideal for the realization of
switched-capacitor filters (SCF). Indeed, SCF technology revi-
talized interest in the leapfrog approach.
1F
1.8478 F2 0.7654 F2
Consider the output sections of the low-pass LC filter of
Fig. 17(a). The relationships between the various voltages
(b) and currents are shown in Eqs. 23

i1 = sC1 RV 0 (23a)
RA
i2 = i1 + i0 (23b)
0.7654 Ω 1.8478 Ω sL1
V2 = i (23c)
R 2
1F RB V3 = V2 + V0 (23d)
1.8478 F2 0.7654 F2 1F i3 = sC2 RV 3 (23e)
(c) i4 = i3 + i2 (23f )
sL2
Figure 14. FDNR realization of low-pass filter. (a) LC prototype of V4 = i (23g)
fourth-order Butterworth filter. (b) DCR network derived from (a). (c) R 4
Resistive shunts added for biasing purposes. V5 = V4 + V3 (23h)
218 ACTIVE FILTERS

1 2 1 a11 a12 2
[a] k1sn k1sn k2sn
k1a21 sn a22
Figure 15. The use of two GICs to yield an embed-
ded network equivalence which eliminates the need
to realize floating FDNRs.

Thus, working from output to input, we have alternating pro-

Co Lo L2 C2 cesses of differentiation and addition. Now, consider the
multifeedback integrator structure of Fig. 17(b), for which

θ1 = sT 1 θ0 (24a)
L1 C1 θ2 = θ1 + θ0 (24b)
θ3 = sT 2 θ2 (24c)
θ4 = θ3 + θ0 (24d)
(a) θ5 = sT 3 θ4 (24e)
θ6 = θ5 + θ4 (24f )
A B
Do Ro R2 D2 θ7 = sT 4 θ6 (24g)
θ8 = θ7 + θ6 (24h)

Thus, for every current and voltage in Eqs. (23a–h), there is

R1 D1 a corresponding quantity ␪i in Eqs. (24a–h). Furthermore, if
corresponding factors such as C1R1 and T1, L1 /R and T2 are
set equal, the two systems have full equivalence.
As a result, LC low-pass structures may be simulated
A′ B′
by a straightforward process, as illustrated in Fig. 18. More
(b) detailed discussions of this approach, including its extension
beyond the low pass are presented elsewhere (14, Ch. 10).
Co Ro R2 C2 As an analog of a passive LC filter, the leapfrog structure
s s provides a low sensitivity structure, and one which is inher-
ently stable.

R1 D1
INTEGRATED FILTERS

As indicated previously, the earliest active filters were fabri-

(c)
Figure 16. Partial transformation to eliminate floating FDNRs. (a)
LC bandpass section. (b) DCR realization of (a). (c) Partial transfor-
mation of (a) by embedding the section AA⬘BB⬘ between two GICs.
cated using discrete components and, eventually, operational
amplifiers. The selection of high-quality capacitors and low-
tolerance, high-performance resistors is crucial to the ulti-
mate quality of the filter (20). Finally, the circuit must be
tuned by the adjustment of one or more trimmer pots.

V4 V2

i4 i2 i0
L2/ R L1/ R
i3 i1
C2 V3 C1 1
V5 V0

(a)

1/ sT 1/ sT 1/ sT 1/ sT
4 3 2 1
θ8 θ7 θ6 θ5 θ4 θ3 θ2 θ1 θ0
– – – –

Figure 17. Basic equivalence of LC and leapfrog

structures. (a) LC prototype. (b) Multifeedback inte-
grator structure. (b)

The advent of laser trimming, combined with thick and
thin film hybrid microelectronic processing, not only led to
larger-scale production but allowed for much more precise
adjustment of resistors. Coupled with numerically controlled
resistor adjustment, hybrid microelectronics fabrication led
to more widespread use of active filters. However, the quest
for ever-smaller structures, and for higher cut-off frequen-
cies ultimately led to fully integrated filters. Several major
technical problems inhibited the fabrication of fully inte-
grated filters:
1. The relatively low bulk resistance of silicon, which
meant that large values of resistance required an un-
duly large volume.
2. The relatively low dielectric constant of silicon which
resulted in excessively large capacitor plate area.
3. The inability to trim passive elements.
Active-R filters (30–31) which utilize the single-pole roll-
off model of an operational amplifier provide an effective ca-
pacitance for simple, high cut-off filters. However, the need to
accurately determine the roll-off properties of each amplifier
renders this approach inefficient in the absence of sophisti-
cated on-chip self-tuning circuitry (9).
Switched-capacitor filters were the first fully-integrated
structures. Although they are strictly sampled-data systems,
they simulate an analog system if the clock frequency is much
higher than the cut-off frequency. Although a more detailed
description of SCFs is presented in SWITCHED CAPACITOR NET-
WORKS, two of their advantages are worthy of note at this time:
1. The filters are fully integrated.
2. Performance depends upon the ratio of relatively small
capacitors and an accurate clock to establish circuit
time constants with high precision.
Vi
(a)
Vi
T5 T4
(b)
Figure 18. Leapfrog realization of low-pass LC filter. (a) Fifth-order LC filter. (b) Leapfrog real-
ization of (a).
ACTIVE FILTERS 219
Fully integrated filters have been developed using the
MOSFET-C (32) technique, which is based upon monolithic
operational amplifiers, capacitors, and MOS (metal oxide
semiconductor) transistors. The latter are biased in their
ohmic region to yield tunable resistors. The technique allows
the designer to take advantage of well-tried RC active filter
design methods but is restricted in frequency by the opera-
tional amplifiers and the nonlinear nature of the simulated
resistance.
Further limitations occur due to integrated circuit parasit-
ics and switching noise resulting from the tuning circuitry.
These problems can be overcome by using fully balanced dif-
ferential circuits so that parasitic effects appear as common
mode signals. Fully balanced circuits are usually derived from
their single-ended counterparts, and are based upon well-
tried structures such as those described in earlier sections. A
useful general rule (9) for converting from single-ended to a
balanced circuit is presented below:
• Identify ground node(s) in the single-ended circuit.
• Mirror the circuit at ground, duplicating all elements,
and divide the gain of all active devices by two.
• Change the sign of the gain of all mirrored active devices
and merge so that any resulting pair with inverting-non-
inverting gains becomes one balanced differential input-
differential output device.
• Realize any devices whose sole effect in the original cir-
cuit is a sign inversion by a simple crossing of wires.
The conversion process for a state variable filter is shown
in Fig. 19(a–b), while Fig. 19(c) shows the MOSFET-C real-
ization in which the resistors of Fig. 19(b) have been replaced
by MOSFET-simulated resistors.
By contrast, fully integrated active filters based upon the
operational transconductance amplifier (OTA) (33–34) are
V0
Vo
T3 T2 T1
220 ACTIVE FILTERS

R4

R2

R1 C1 C2
R3
– R
–
+ –
+
Vi +
Vo

(a)

R4

C1

R2
C2
R1 R3
V i+ – – V o+
+ +
R1 R3
– –
V i– + + Vo–

C2
R2

C1 R4

(b)

R4

R2

C1 C2
R1 R3
V i+ – – V o+
+ +
– –
V i– + + Vo–
R1 R3
C2
C1

R2

R4

(c)

Figure 19. Realization of MOSFET-C state variable filter. (a) Original active RC version using
single-ended amplifiers. (b) Fully differential, active-RC version. (c) MOSFET-C version with
MOSFETs R1 . . . R4 replacing equivalent resistors of (b).
 ACTIVE FILTERS 221

V+ + I0
gm I1
V– – + I0

–
V1 Req
Figure 20. Circuit symbol for the operational transconductance am-
plifier (OTA). Req

(a)
simpler to design and have a much wider frequency range.
This has led to OTA-C structures capable of accurate opera- Req
I1 I2
tion at frequencies beyond 100 MHz (35).
The OTA is a high-gain voltage-controlled current source,
– +
which is relatively easy to fabricate using CMOS or comple-
mentary bipolar technology. Some basic properties of the OTA + –
V1 V2
V1 V2
are as follows:

1. High gain-bandwidth product that yields filters with

higher operating frequencies than those using conven- (b)
tional operational amplifiers. Figure 21. Resistance simulation using OTAs. (a) Grounded resistor.
2. Can be electronically tuned to modify its transconduc- (b) Floating resistor.
tance.
3. Infinite input impedance and infinite output impedance.
from which:
The circuit symbol for the OTA is shown in Fig. 20, for     
I1 gm1 −gm1 V1
which = (29)
I2 −gm2 gm2 V2
I0 = gm (V + − V − ) (25)
For matched devices, gm1 ⫽ gm2, and Eq. (29) represents a
where gm is the transconductance, a typical value being 500 floating resistor of value 1/gm. Various building blocks can
애A/V. gm can be controlled by Ic such that: now be developed, forming the basis for simulation of struc-
tures such as the state variable. For example, the simple
gm = KIc (26) summer shown in Fig. 22(a) yields
gm1 g
where Ic is in microamps and a typical value of K is 15. Of V0 = V + m2 V (30)
gm3 1 gm3 2
particular importance, Eq. (26) is valid over a wide range,
perhaps as much as six decades for Ic, that is, 0.001 to 1000
애A. In addition, the gain-bandwidth is also proportional to
Ic and may extend to hundreds of megahertz. This will be +
limited by input and output parasitics. 1
An OTA-C filter structure depends upon the ability of the –
–
OTA to simulate large values of resistance. Hence, in conjunc-
+ 3
tion with relatively small values of capacitance, it is possible V1 +
2
to set the appropriate filter time constants without undue use V2 V0
–
of silicon real estate.
Resistance can be simulated by the circuits shown in Figs.
21(a,b). For the grounded resistance,
(a)
−I1 = I0 = gm (0 − V − ) = −gmV1

Hence, +
1 – 2
– +
V 1 V+
Req = 1 = (27) V0
I1 gm V– C

Thus, if gm ⫽ 10⫺5S, Req ⫽ 100 k⍀.

For the floating resistance of Fig. 21(b):
(b)
I1 = −gm1 (V2 − V1 ) (28a)
Figure 22. OTA filter building blocks. (a) Summer. (b) Damped inte-
I2 = −gm2 (V1 − V2 ) (28b) grator.
222 ACTIVE FILTERS

Bandpass 5. W. J. Kerwin, L. P. Huelsman, and R. W. Newcomb, State-vari-

Low-pass able synthesis for insensitive integrated circuit transfer func-
+
tions, IEEE Journal, SC-2: 87–92, 1967.
1 –
– 2 + 6. F. E. Girling and E. F. Good, Active filters, Wireless World, 76:
+ 3 341–345, 445–450, 1970. The leapfrog method was first described
– by the same authors in RRE Memo No. 1177, September, 1955.
7. R. A. Friedenson et al., RC active filters for the D3 channel bank
filter, Bell Syst. Tech. J., 54 (3): 507–529, 1975.
8. R. W. Brodersen, P. R. Gray, and D. A. Hodges, MOS switched-
– capacitor filters, Proc. IEEE, 67: 61–75, 1979.
4 9. R. Schaumann, M. S. Ghausi, and K. R. Laker, Design of Analog
+ Filters, Englewood Cliffs, NJ: Prentice-Hall, 1990.
10. R. W. Daniels, Approximation Methods for Electronic Filter De-
sign, New York: McGraw-Hill, 1974.
11. P. Bowron and F. W. Stephenson, Active Filters for Communica-
Figure 23. OTA circuit yielding both bandpass and low-pass second- tions and Instrumentation, London: McGraw-Hill, 1979.
order transfer functions.
12. A. I. Zverev, Handbook of Filter Synthesis, New York: Wiley, 1967.
13. E. Christian and E. Eisenman, Filter Design Tables and Graphs,
New York: Wiley, 1966.
whereas the circuit of Fig. 22(b) realizes a damped integrator, 14. F. W. Stephenson (ed.), RC Active Filter Design Handbook, New
for which York: Wiley, 1985.
gm1 15. L. P. Huelsman, Active and Passive Analog Filter Design—An
V0 = (V + − V − ) (31) Introduction, New York: McGraw-Hill, 1993.
sC + gm2
16. F. W. Stephenson, Single-amplifier multiple-feedback filters, in
W-K. Chen, (ed.), The Circuits and Filters Handbook, New York:
Furthermore, by setting gm2 ⫽ 0 (eliminating the second OTA), CRC Press/IEEE Press, 1995.
Eq. (31) reduces to that of an undamped integrator.
17. T. Deliyannis, High-Q factor circuit with reduced sensitivity,
Other biquads, not based directly on earlier topologies, Electron. Lett., 4 (26): 577–579, 1968.
may also be realized. For example, the biquad of Fig. 23 may
18. J. J. Friend, C. A. Harris, and D. Hilberman, STAR: an active
be analyzed to yield a bandpass output of biquadratic filter section, IEEE Trans. Circuits Syst., CAS-22:
115–121, 1975.
Vbp s(gm1 /C1 )
=   (32)
Vi gm2 g g
s2 + s + m3 m4
C2 C1C2
SUMMARY
RC active filters have reached a degree of maturity that could
not have been envisaged when they were first conceived over
40 years ago. The successive introductions of operational am-
plifiers, laser trimming, hybrid microelectronic fabrication,
and, finally, fully integrated filters have all helped advance
the state of the art. However, the thread linking all of these
technological advances has been the retention of a small num-
ber of topologies and techniques that have been proven to
yield reliable filters for large-scale practical applications.
These structures have formed the basis for discussion in this
article. By no means do they represent all the possibilities,
but they do form a solid basis upon which further study may
be based.
BIBLIOGRAPHY
1. F. Jay (ed.), IEEE Standard Dictionary of Electrical and Electronic
Terms, 4th ed., New York: IEEE Press, 1988.
2. J. G. Linvill, RC active filters, Proc. IRE, 12: 555–564, 1954.
3. R. P. Sallen and E. L. Key, A practical method of designing RC
active filters, IRE Trans., CT-2: 74–85, 1955.
4. A. G. J. Holt and J. R. Taylor, Method of replacing ungrounded
inductances by grounded gyrators, Electron. Lett., 1 (4): 105,
1965.
19. L. P. Huelsman and P. E. Allen, Introduction to the Theory and
Design of Active Filters, New York: McGraw-Hill, 1980.
20. F. W. Stephenson and W. B. Kuhn, Higher-order filters, in J. T.
Taylor and Q. Huang (eds.), CRC Handbook of Electrical Filters,
New York: CRC Press, 1997, pp. 119–139.
21. G. S. Moschytz, A second-order pole-zero pair selection for nth-
order minimum sensitivity networks, IEEE Trans., CT-17 (4):
527–534, 1970.
22. M. S. Ghausi and K. R. Laker, Modern Filter Design, Englewood
Cliffs, NJ: Prentice-Hall, 1981.
23. A. Antoniou, Realization of gyrators using operational amplifiers
and their use in RC-active network synthesis, Proc. IEEE, 116
(11): 1838–1850, 1969.
24. L. T. Bruton, Network transfer functions using the concept of
frequency-dependent negative resistance, IEEE Trans., CT-16:
406–408, 1969.
25. A. W. Keen and J. L. Glover, Active RC equivalents of RCL net-
works by similarity transformation, Electron. Lett. 7 (11): 288–
290, 1971.
26. L. T. Bruton and A. B. Haase, Sensitivity of generalized immit-
tance converter-embedded ladder structures, IEEE Trans., CAS-
21 (2): 245–250, 1974.
27. G. Hurtig, The primary resonator block technique of filter synthe-
sis, Proc. IEEE International Filter Symposium, Santa Monica,
CA, April 1972, p. 84, [US Patent 3,720,881, March, 1973].
28. K. R. Laker and M. S. Ghausi, Synthesis of low-sensitivity
multiloop feedback active RC filter, IEEE Trans., CAS-21 (2):
252–259, 1974.
29. J. Tow, Design and evaluation of shifted-companion form of ac-
tive filters, Bell Syst. Tech. J., 54 (3): 545–568, 1975.
30. J. R. Brand and R. Schaumann, Active R filters: Review of theory
and practice, IEEE J., ECS-2 (4): 89–101, 1978.
 ACTIVE PERCEPTION 223

31. A. S. Sedra and P. O. Brackett, Filter Theory and Design: Active

and Passive, Portland OR: Matrix, 1978.
32. Y. Tsividis, M. Banu, and J. Khoury, Continuous-Time MOSFET-
C Filters in VLSI, IEEE Trans., CAS-33: 1125–40, 1986.
33. Y. P. Tsividis and J. O. Voorman (eds.), Integrated Continuous-
Time Filters, Piscataway, NJ: IEEE Press, 1993.
34. R. L. Geiger and E. Sanchez-Sinencio, Active filter design using
operational transconductance amplifiers: A tutorial, IEEE Circ.
Dev. Mag., CDM-1: 20–32, 1985.
35. M. Atarodi and J. Choma, Jr., A 7.2 GHz bipolar operational
transconductance amplifier for fully integrated OTA-C filters, J.
Analog Integ. Circ. Signal Process., 6 (3): 243–253, 1994.

F. WILLIAM STEPHENSON
Virginia Polytechnic Institute and
State University

ACTIVE FILTERS. See ANALOG FILTERS; CASCADE NET-

WORKS.
ACTIVE NETWORK SYNTHESIS. See CURRENT CON-
VEYORS.
 ADAPTIVE FILTERS 259

Now consider the expectation of Eq. (37): For stable convergence each term in Eq. (45) must be less
than one, so we must have
w (n + 1)] = E[w
E[w w (n)] + 2µE[d(n)xx(n)]
(38) 1
w (n)]
− 2µE[xx (n)xx (n)T ]E[w 0<µ< (46)
λmax
We have assumed that the filter weights are uncorrelated
with the input signal. This is not strictly satisfied, because where ␭max is the largest eigenvalue of the correlation matrix
the weights depend on x(n); but we can assume that 애 has R, though this is not a sufficient condition for stability under
small values because it is associated with a slow trajectory. all signal conditions. The final convergence rate of the algo-
So, subtracting the optimum solution from both sides of Eq. rithm is determined by the value of the smallest eigenvalue.
(38), and substituting the autocorrelation matrix R and cross- An important characteristic of the input signal is therefore
correlation vector p, we get the eigenvalue spread or disparity, defined as

w (n + 1)] − R−1 p = E[w

E[w w (n)] − R−1 p + 2µR{R−1 p − E[w
w (n)]} λmax/λmin (47)
(39)
So, from the point of view of convergence speed, the ideal
Next, defining value of the eigenvalue spread is unity; the larger the value,
the slower will be the final convergence. It can be shown (3)
w (n + 1)] − R−1 p
ξ (n + 1) = E[w (40) that the eigenvalues of the autocorrelation matrix are
bounded by the maximum and minimum values of the power
from Eq. (39) we obtain spectral density of the input.
It is therefore concluded that the optimum signal for fast-
ξ (n + 1) = (I − 2µR)ξξ (n) (41) est convergence of the LMS algorithm is white noise, and that
any form of coloring in the signal will increase the conver-
This process is equivalent to translation of coordinates. Next, gence time. This dependence of convergence on the spectral
we define R in terms of an orthogonal transformation (7): characteristics of the input signal is a major problem with the
LMS algorithm, as discussed in Ref. 6.
R = K T QK (42)
LMS-Based Algorithms
where Q is a diagonal matrix consisting of the eigenvalues
(␭0, ␭1, . . ., ␭N) of the correlation matrix R, and K is the uni- The Normalized LMS Algorithm. The normalized LMS
tary matrix consisting of the eigenvectors associated with (NLMS) algorithm is a variation of the ordinary LMS algo-
these eigenvalues. rithm. Its objective is to overcome the gradient noise amplifi-
Substituting Eq. (42) in Eq. (41), we have cation problem. This problem is due to the fact that in the
standard LMS, the correction 애e(n)x(n) is directly propor-
ξ (n + 1) = (I − 2µK T QK)ξξ (n) tional to the input vector x(n). Therefore, when x(n) is large,
(43) the LMS algorithm amplifies the noise.
= K T (I − 2µQ)Kξξ (n)
Consider the LMS algorithm defined by
Multiplying both sides of the Eq. (43) by K and defining
w (n + 1) = w (n) + 2µe(n)xx (n) (48)
v (n + 1) = Kξξ (n + 1)
(44) Now consider the difference between the optimum vector w*
= (I − 2µQ)v
v (n)
and the current weight vector w(n):
we may rewrite Eq. (44) in matrix form as
v (n) = w ∗ − w (n) (49)
 
v0 (n)
 v (n)  Assume that the reference signal and the error signal are
 1 
 
 .. 
 .  d(n) = w ∗Tx (n) (50)
vN−1 (n) e(n) = d(n) − w (n)Tx (n) (51)
 
(1 − 2µλ1 )n
 (1 − 2µλ2 )n  Substituting Eq. (50) in Eq. (51), we obtain
 
=
 .. 

 .  e(n) = w ∗Tx (n) − w (n)Tx (n)
(1 − 2µλN )n w ∗T − w (n)T ]xx (n)
= [w (52)
 
v0 (0) = v (n)xx (n)
T
 v (0) 
 1 
  (45)
 ..  We decompose v(n) into its rectangular components
 . 
vN−1 (0) v (n) = v o (n) + v p (n) (53)
260 ADAPTIVE FILTERS

vp(n–1) Therefore, the NLMS algorithm given by Eq. (64) is equiva-

vp(n) lent to the LMS algorithm if

α
2µ = (66)
x T (n)xx (n)
vp(n) vp(n) x(n)

Figure 13. Geometric interpretation of the NLMS algorithm. NLMS Algorithm

Parameters : M = filter order
α = step size
where vo(n) and vp(n) are the orthogonal component and the Initialization : Set w (0) = 0
parallel component of v(n) with respect to the input vector. Computation : For n = 0, 1, 2, . . ., compute
This implies
y(n) = w (n)Tx (n)
v p (n) = Cxx (n) (54) e(n) = d(n) − y(n)
α
where C is a constant. Then substituting Eq. (53) and Eq. (54) β= T
x (n)xx (n)
in Eq. (52), we get
w (n + 1) = w (n) + βe(n)xx (n)
e(n) = [v
v o (n) + v p (n)]Tx (n) (55)
e(n) = [v
v o (n) + Cxx (n)]Tx (n) (56) Time-Variant LMS Algorithms. In the classical LMS algo-
rithm there is a tradeoff between validity of the final solution
Because vo(n) is orthogonal to x(n), the scalar multiplication and convergence speed. Therefore its use is limited for several
is practical applications, because a small error in the coefficient
vector requires a small convergence factor, whereas a high
v Tox (n) = 0 (57) convergence rate requires a large convergence factor.
The search for an optimal solution to the problem of ob-
Then solving for C from Eqs. (56) and (57) yields taining high convergence rate and small error in the final
solution has been an arduous in recent years. Various algo-
e(n) rithms have been reported in which time-variable conver-
C= (58)
x T (n)xx (n) gence coefficients are used. These coefficients are chosen so
as to meet both requirements: high convergence rate and low
and MSE. Interested readers may refer to Refs. 9–14.

e(n)xx (n)
v p (n) = (59) Recursive Least-Squares Algorithm
x T (n)xx (n)
The recursive least-squares (RLS) algorithm is required for
The target now is to make v(n) as orthogonal as possible to rapidly tracking adaptive filters when neither the reference-
x(n) in each iteration, as shown in Fig. 13. The above men- signal nor the input-signal characteristics can be controlled.
tioned can be done by setting An important feature of the RLS algorithm is that it utilizes
information contained in the input data, extending back to
v (n + 1) = v (n) − αv
v p (n) (60) the instant of time when the algorithm is initiated. The re-
sulting convergence is therefore typically an order of magni-
Finally, substituting Eq. (49) and Eq. (59), we get tude faster than for the ordinary LMS algorithm.
In this algorithm the mean squared value of the error sig-
e(n)xx (n)
w ∗ − w (n + 1) = w ∗ − w (n) − α (61) nal is directly minimized by a matrix inversion. Consider the
x T (n)xx (n) FIR filter output
e(n)xx (n)
w (n + 1) = w (n) + α (62) y(n) = w Tx (n) (67)
x T (n)xx (n)

where, in order to reach the target, 움 must satisfy (9) where x(n) is the input vector given by x(n) ⫽ [x(n), x(n ⫺ 1,
. . ., x(n ⫺ M ⫹ 1)]T and w is the weight vector. The optimum
0<α<2 (63) weight vector is computed in such a way that the mean
squared error, E[e2(n)] is minimized, where
In this way
e(n) = d(n) − y(n) = d(n) − w Tx (n) (68)
w (n + 1) = w (n) + βe(n)xx (n) (64)
E[e (n)] = E[{d(n) − w x (n)} ]
2 T 2
(69)
where
To minimize E[e2(n)], we can use the orthogonality principle
α in the estimation of the minimum. That is, we select the
β= T (65)
x (n)xx (n) weight vector in such a way that the output error is orthogo-
 ADAPTIVE FILTERS 261

nal to the input vector. Then from Eqs. (67) and (68), we ob- Next, for convenience of computation, let
tain
Q(n) = R−1 (n) (82)
E[xx (n){d(n) − x (n)w
w}] = 0
T
(70)
and
Then
R−1 (n − 1)xx (n)
E[xx (n)xxT (n)w
w] = E[d(n)xx (n)] (71) K(n) = (83)
λ + x T (n)R−1 (n − 1)xx (n)

Assuming that the weight vector is not correlated with the

Then from Eq. (81) we have
input vector, we obtain
1
E[xx (n)xxT (n)]w
w = E[d(n)xx (n)] (72) w (n) = [Q(n − 1) − K(n)xx T (n)Q(n − 1)]
λ (84)
p (n − 1) + d(n)xx(n)]
[λp
which can be rewritten as
1
w (n) = Q(n − 1)p
p (n − 1) + d(n)Q(n − 1)xx (n)
w=p
Rw (73) λ
− K(n)xx T (n)Q(n − 1)p
p (n − 1) (85)
where R and p are the autocorrelation matrix of the input 1
signal and the correlation vector between the reference sig- − d(n)K(n)xxT (n)Q(n − 1)xx (n)
λ
nal d(n) and input signal x(n), respectively. Next, assuming
ergodicity, p can be estimated in real time as 1
w (n) = w (n − 1) + d(n)Q(n − 1)xx (n)
λ

n
Q(n − 1)xx (n)xxT (n)w
w (n − 1)
p (n) = λn−k d(k)xx (k) (74) − (86)
k=0
λ + x T (n)Q(n − 1)xx (n)

n−1 1 d(n)Q(n − 1)xx (n)xxT (n)Q(n − 1)xx (n)
−
p (n) = λn−k d(k)xx (k) + d(n)xx (n) λ λ + x T (n)Q(n − 1)xx (n)
k=0
(75) 1 Q(n − 1)xx (n)

n−1 w (n) = w (n − 1) +
=λ λ n−k−1
d(k)xx (k) + d(n)xx (n) λ λ + x T (n)Q(n − 1)xx (n)
k=0 × [λd(n) + d(n)xxT (n)Q(n − 1)xx (n) (87)

p (n) = λp
p (n − 1) + d(n)xx(n) (76) − λxxT (n)w
w (n − 1) − d(n)xxT (n)Q(n − 1)xx (n)]
1 Q(n − 1)xx (n)
where ␭ is the forgetting factor. In a similar way, we can ob- w (n) = w (n − 1) +
tain λ λ + x T (n)Q(n − 1)xx (n) (88)
× λ[d(n) − x T (n)w
w(n − 1)]
R(n) = λR(n − 1) + x (n)xx T (n) (77)
Finally, we have
Then, multiplying Eq. (73) by R⫺1 and substituting Eq. (76)
and Eq. (77), we get w (n) = w (n − 1) + K(n)(n) (89)

w = [λR(n − 1) + x (n)xxT (n)]−1 [λp

p (n − 1) + d(n)xx (n)] (78) where

Next, according to the matrix inversion lemma Q(n − 1)xx (n)

K(n) = (90)
λ + x T (n)Q(n − 1)xx (n)
−1 −1 −1 −1 −1 −1 −1
(A + BCD) =A −A B(DA B +C ) DA (79)
and ⑀(n) is the a priori estimation error, based on the old
with A ⫽ ␭R(n ⫺ 1), B ⫽ x(n), C ⫽ 1, and D ⫽ xT(n), we least-square estimate of the weights vector that was made at
obtain time n ⫺ 1, and defined by

1 −1 1 −1


w (n) = R (n − 1) − R (n − 1)xx (n) (n) = d(n) − w T (n − 1)xx (n) (91)
λ λ

−1 1
1 T Then Eq. (89) can be written as
× x (n)R−1 (n − 1)xx (n) + 1 x T (n)R−1 (n − 1)
λ λ
w (n) = w (n − 1) + Q(n)(n)xx(n) (92)
× [λp
p (n − 1) + d(n)xx (n)]
(80)
1 −1
R (n − 1)xx (n)xx (n)R xT −1
(n − 1)

where Q(n) is given by
w (n) =
λ
R−1 (n − 1) −
[λ + x T (n)R−1 (n − 1)xx (n)] 1 Q(n − 1)xxT (n)Q(n − 1)


Q(n) = Q(n − 1) − (93)
× [λp
p (n − 1) + d(n)xx(n)] (81) λ λ + x T (n)Q(n − 1)xx (n)
262 ADAPTIVE FILTERS
The applicability of the RLS algorithm requires that it ini-
tialize the recursion of Q(n) by choosing a starting value
Q(0) to ensure the nonsingularity of the correlation matrix
R(n) (3).
RLS Algorithm
Initialization : Set Q(0)
w (0) = 0
Computation : For n = 1, 2, . . ., compute
Q(n − 1)xx (n)
K(n) =
λ + x T (n)Q(n − 1)xx (n)
(n) = d(n) − w T (n − 1)xx (n)
w (n) = w (n − 1) + K(n)(n)
w (n + 1) = w (n) + βe(n)xx (n)
Q(n) = R−1 (n)
IMPLEMENTATIONS OF ADAPTIVE FILTERS
In the last few years many adaptive filter architectures have
been proposed, for reducing the convergence rate without in-
creasing the computational cost significantly. The digital im-
plementations of adaptive filters are the most widely used.
They yield good performance in terms of adaptivity, but con-
sume considerable area and power. Several implementations
achieve power reduction by dynamically minimizing the order
of the digital filter (15) or employing parallelism and pipelin-
ing (16). On the other hand, high-speed and low-power appli-
cations require both parallelism and reduced complexity (17).
Is well known that analog filters offer advantages of small
area, low power, and higher-frequency operation over their
digital counterparts, because analog signal-processing opera-
tions are normally much more efficient than digital ones.
Moreover, since continuous-time adaptive filters do not need
analog-to-digital conversion, it is possible to prevent quanti-
zation-related problems.
Gradient descent adaptive learning algorithms are com-
monly used for analog adaptive learning circuits because of
their simplicity of implementation. The LMS algorithm is of-
ten used to implement adaptive circuits. The basic elements
used for implementing the LMS algorithm are delay elements
(which are implemented with all-pass first-order sections),
multipliers (based on a square law), and integrators. The
techniques utilized to implement these circuits are discrete-
time approaches, as discussed in Refs. 18 to 21, and continu-
ous-time implementations (22,23,24).
Several proposed techniques involve the implementation of
the RLS algorithm, which is known to have very low sensitiv-
ity to additive noise. However, a direct analog implementa-
tion of the RLS algorithm would require a considerable effort.
To overcome this problem, several techniques have been pro-
posed, such as structures based on Hopfield neural networks
(23,25,26,27).
BIBLIOGRAPHY
1. S. U. H. Qureshi, Adaptive equalization, Proc. IEEE, 73: 1349–
1387, 1985.
2. J. Makhoul, Linear prediction: A tutorial review, Proc. IEEE, 63:
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3. S. Haykin, Adaptive Filter Theory, 3rd ed., Upper Saddle River,
NJ: Prentice-Hall, 1996.
4. B. Friedlander, Lattice filters for adaptive processing, Proc.
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5. J. J. Shynk, Adaptive IIR filtering, IEEE ASSP Mag., 6 (2): 4–
21, 1989.
6. P. Hughes, S. F. A. Ip, and J. Cook, Adaptive filters—a review of
techniques, BT Technol. J., 10 (1): 28–48, 1992.
7. B. Widrow and S. Stern, Adaptive Signal Processing, Englewood
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8. B. Widrow and M. E. Hoff, Jr., Adaptive switching circuits, IRE
WESCON Conv. Rec., part 4, 1960, pp. 96–104.
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cation, IEEE Trans. Autom. Control, AC-12: 282–287, 1967.
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11. I. Nakanishi and Y. Fukui, A new adaptive convergence factor
with constant damping parameter, IEICE Trans. Fundam. Elec-
tron. Commun. Comput. Sci., E78-A (6): 649–655, 1995.
12. T. Aboulnasr and K. Mayas, A robust variable step size LMS-
type algorithm: Analysis and simulations, IEEE Trans. Signal
Process., 45: 631–639, 1997.
13. F. Casco et al., A variable step size (VSS-CC) NLMS algorithm,
IEICE Trans. Fundam., E78-A (8): 1004–1009, 1995.
14. M. Nakano et al., A time varying step size normalized LMS algo-
rithm for adaptive echo canceler structures, IEICE Trans. Fun-
dam., E78-A (2): 254–258, 1995.
15. J. T. Ludwig, S. H. Nawab, and A. P. Chandrakasan, Low-power
digital filtering using approximate processing, IEEE J. Solid
State Circuits, 31: 395–400, 1996.
16. C. S. H. Wong et al., A 50 MHz eight-tap adaptive equalizer for
partial-response channels, IEEE J. Solid State Circuits, 30: 228–
234, 1995.
17. R. A. Hawley et al., Design techniques for silicon compiler imple-
mentations of high-speed FIR digital filters, IEEE J. Solid State
Circuits, 31: 656–667, 1996.
18. M. H. White et al., Charge-coupled device (CCD) adaptive dis-
crete analog signal processing, IEEE J. Solid State Circuits, 14:
132–147, 1979.
19. T. Enomoto et al., Monolithic analog adaptive equalizer inte-
grated circuit for wide-band digital communications networks,
IEEE J. Solid State Circuits, 17: 1045–1054, 1982.
20. F. J. Kub and E. W. Justh, Analog CMOS implementation of high
frequency least-mean square error learning circuit, IEEE J. Solid
State Circuits, 30: 1391–1398, 1995.
21. Y. L. Cheung and A. Buchwald, A sampled-data switched-current
analog 16-tap FIR filter with digitally programmable coefficients
in 0.8 애m CMOS, Int. Solid-State Circuits Conf., February 1997.
22. J. Ramirez-Angulo and A. Dı́az-Sanchez, Low voltage program-
mable FIR filters using voltage follower and analog multipliers,
Proc. IEEE Int. Symp. Circuits Syst., Chicago, May 1993.
23. G. Espinosa F.-V. et al., Ecualizador adaptivo BiCMOS de tiempo
continuo, utilizando una red neuronal de Hopfield, CONIELEC-
OMP’97, UDLA, Puebla, México, 1997.
24. L. Ortı́z-Balbuena et al., A continuous time adaptive filter struc-
ture, IEEE Int. Conf. Acoust., Speech Signal Process., Detroit,
1995, pp. 1061–1064.
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Hopfield neural networks, Proc. IASTED Int. Conf. Signal Image
Process., Orlando, FL, November 1996, pp. 168–172.
26. G. Espinosa F.-V., A. Dı́az-Méndez, and F. Maloberti, A 3.3 V
CMOS equalizer using Hopfield neural network, 4th IEEE Int.
Conf. Electron., Circuits, Syst., ICECS97, Cairo, 1997.
 ADAPTIVE RADAR 263

27. M. Nakano-Miyatake and H. Perez-Meana, Analog adaptive fil-

tering based on a modified Hopfield network, IEICE Trans. Fun-
dam., E80-A: 2245–2252, 1997.

Reading List
M. L. Honig and D. G. Messerschmitt, Adaptive Filters: Structures,
Algorithms, and Applications, Norwell, MA: Kluwer, 1988.
B. Mulgrew and C. F. N. Cowan, Adaptive Filters and Equalisers,
Norwell, MA: Kluwer, 1988.
S. Proakis et al., Advanced Signal Processing, Singapore: Macmillan.

GUILLERMO ESPINOSA FLORES

VERDAD
JOSÉ ALEJANDRO DÍAZ MÉNDEZ
National Institute for Research in
Astrophysics, Optics and
Electronics
ALL-PASS FILTERS
NETWORKS, ALL-PASS
FILTERS, ALL-PASS
PHASE EQUALIZERS
All-pass filters are often included in the catalog of classical
filter types. A listing of types of classical filters reads as
follows: low-pass, high-pass, bandpass, band-stop, and all-
pass filters. The transfer functions (see Transfer func-
tions) of all of these filters can be expressed as real, ra-
tional functions of the Laplace transform variable s (see
Laplace transforms). That is, these transfer functions
can be expressed as the ratio of two polynomials in s which
have real coefficients. All of the types of filters listed have
frequency-selective magnitude characteristics except for
the all-pass filter. That is, in the sinusoidal steady state,
a low-pass filter passes low-frequency sinusoids relatively
well and attenuates high-frequency sinusoids. Similarly, a
bandpass filter in sinusoidal steady state passes sinusoids
having frequencies that are within the filter’s passband
relatively well and attenuates sinusoids having frequen-
cies lying outside this band. It should be kept in mind that
all of the filters on the list modify the phase of applied
sinusoids (see Filtering theory). Figure 1 shows idealized
representations of the magnitude characteristics of classi-
cal filters for comparison.
However, the all-pass filter is the only filter on the list
having a magnitude characteristic that is not frequency
selective; in the sinusoidal steady state, an all-pass filter
passes sinusoids having any frequency. The filter does not
change the amplitude of the input sinusoid or it changes
the amplitudes of input sinusoids by the same amount no
matter the frequency. An all-pass filter modifies only the
phase, and this is the property that is found useful in signal
processing.
Only the transfer function of the all-pass filter, ex-
pressed as a rational function of s must have zeros (loss
poles) in the right-half s plane (RHP). The poles and zeros
of the transfer function are mirror images with respect to
the origin. The transfer functions of the other filters are
usually minimum phase transfer functions, meaning that
the zeros of these transfer functions are located in the left-
half s plane (LHP) or on the imaginary axis but not in the
open RHP. As a result of these properties, the transfer func-
tion of an all-pass filter, TAP (s), can be expressed as a gain
factor H times a ratio of polynomials in which the numer-
ator polynomial can be constructed from the denominator
polynomial by replacing s by −s thereby creating zeros that
are images of the poles. H can be positive or negative.
The primary application of all-pass filters is in phase
equalization of filters having frequency-selective magni-
tude characteristics. A frequency-selective filter usually re-
alizes an optimum approximation to ideal magnitude char-
acteristics. For example, a Butterworth low-pass filter ap-
proximates the ideal brick-wall low-pass magnitude char-
acteristic [see Fig. 1(a)] in a maximally flat manner. An
ideal filter also has linear phase in the passband in order
to avoid phase distortion. But the Butterworth filter does
not have linear phase. So an all-pass filter is designed to
be connected in cascade with the Butterworth filter in or-
der to linearize its phase characteristic. This application is
discussed in greater detail later in this article.
Another application of all-pass filters is creation of delay
for a variety of signal-processing tasks. A signal-processing
system may have several branches, and, depending on the
application, it may be important to make the delay in each
branch approximately equal. This can be done with all-
pass filters. On the other hand, a signal processing task
may require delaying one signal relative to another. Again,
an all-pass filter can be used to provide the delay. This
application is also discussed in greater detail in this article.
PROPERTIES OF ALL-PASS FILTERS
The transfer function of an all-pass filter, TAP (s), has the
form
where the constant H is the gain factor, which can be posi-
tive or negative, and D(s) is a real polynomial of s. Thus, a
first-order all-pass filter transfer function, denoted by TAP1 ,
with a pole on the negative real axis at s = −a is given by
and a second-order transfer function, denoted as TAP2 , with
complex poles described by undamped natural frequency
(or natural mode frequency) ω0 and Q (½ < Q < ∞ for
complex poles in the open LHP) is given by
Of course, an all-pass transfer function can be created that
has two real-axis poles as would be obtained by cascad-
ing two buffered first-order transfer functions, but all-pass
transfer functions with complex poles are the most useful
for phase equalization of filters.
To show that the magnitude characteristic is constant
for all frequencies for all-pass transfer functions of any or-
der, we first obtain from Eq. (1)
where ∗ indicates the conjugate. Then from Eq. (4), we ob-
tain
This result is also shown graphically in Fig. 2 for the case
of a second-order all-pass transfer function with complex
poles. An arbitrary point P has been selected on the jω axis,
and we see that the lengths of the vectors from the poles to

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright © 2007 John Wiley & Sons, Inc.
2 Phase Equalizers

Figure 1. Idealized magnitude characteristics of classical filters. (a) Low-pass filter. (b) High-pass
filter. (c) Bandpass filter. (d) Band-stop filter. (e) All-pass filter.

Figure 3. Phase plots for the first-order all-pass transfer func-

tion of Eq. (2) with a zero at s = 1 and for second-order transfer
functions of Eq. (3) with ω0 = 1 and Q = ½, 1, 2, and 4. H is positive
Figure 2. A pole-zero plot for a second-order all-pass transfer
for all the transfer functions.
function with complex poles is shown. An arbitrary point on the
jω axis, denoted as P, has been selected. The lengths of the vectors
from the poles to point P are the same as the corresponding lengths for the second-order transfer function in Eq. (3) with ω0 =
of the vectors from the zeros to point P 1 and Q values equal to ½, 1, 2, and 4. H is positive for
all the transfer functions. Upon examination of the plots
generated by the second-order transfer functions, it is seen
the point are the same as the lengths of the vectors from
that for Q = ½, there is no point of inflection. For certain
the zeros to point P. Thus, the magnitude characteristic is
higher values of Q, there is a point of inflection. The point
determined only by H and is not a function of frequency.
of inflection is obtained by differentiating the expression
The phase, however, is a function of frequency. Denoting
for phase two times with respect to ω, equating the result
the phase of the all-pass transfer function as θ AP , selecting
to zero, and solving for a positive ω. The result is
H to be positive for convenience, and denoting the phase of
D(jω) as θ D , we can write:

The all-pass transfer function produces phase lag, see 1. Thus, for Qs greater than 0.578, there is a point of inflection
If H is negative, then an additional phase of π radians is in the phase plot.
introduced. Figure 3 shows the phase plots obtained for The negative of the derivative of phase with respect to
the first-order transfer function in Eq. (2) with a = 1 and ω is the group delay, denoted as τ(ω). Group delay is also

termed envelope delay or merely delay, and its units are
seconds. Oftentimes, designers prefer working with delay
rather than phase because delay can be expressed as a ra-
tional function of ω. The expression for phase involves a
transcendental function tan−1 ( ). For example, the phase
of the second-order transfer function with positive H, ω0 =
1 and Q = 2 (see Eq. 3) is
However, the delay is given by
which is a rational function of ω resulting from the deriva-
tive of the arctangent function. Figure 4 depicts the de-
lays corresponding to the phase plots given in Fig. 3. For
Q greater than 0.578, the plots of delay exhibit peaks. For
Q2 > ½, the peaks occur at ω
ω0 = 1.
PHASE DISTORTION
At steady state, a linear, time-invariant network affects
only the amplitude and phase of an applied sinusoid to
produce an output sinusoid. The output sinusoid has the
same frequency as the input sinusoid. If the input sig-
nal is composed of two sine waves of different frequencies,
then, depending on the network, the output signal could
be changed in amplitude or in phase or both. For exam-
ple, suppose the network is a low-pass filter and that the
input signal consists of two sinusoids with different fre-
quencies, but both frequencies lie within the passband. In
this case, the network should pass the signal to the out-
put with minimum distortion. Since the frequencies of the
sine waves that make up the input signal lie within the
passband, very little amplitude distortion is encountered.
However, the result can be severely phase distorted. If no
phase distortion is to be produced, then the phase charac-
teristic in the passband of the network must be linear and,
hence, have the form −kω + θ 0 , where k is the magnitude of
the slope of the phase characteristic and θ 0 is the phase at
ω = 0. Furthermore, if θ 0 is neither 0 nor a multiple of 2π
radians, then a distortion known as phase-intercept distor-
tion results. In the following, phase-intercept distortion is
not considered. The interested reader is referred to Ref. 2
for further information on phase-intercept distortion.
To illustrate the effects that a system with linear phase
has on an input signal, let an input signal v(t), given by
be applied to a network with transfer function T(s). Assume
the phase of the system is given by θ(ω) = −kω, where k is
a positive constant, and assume that |T(jω)| = |T(2jω)| =
1. In Eq. (10), A1 and A2 are the peak amplitudes of the
two sinusoids that make up v(t). The output signal can be
written as
Phase Equalizers 3
Rewriting Eq. (11), we obtain
where it is seen that each sinusoid in vo (t) is delayed by the
same amount, namely k seconds. The output voltage has
been delayed by k seconds, but there is no phase distortion.
However, suppose the phase of the system is given by θ =
−kω3 , a nonlinear phase characteristic. With the input sig-
nal given by Eq. (10) and, as before, assuming that |T(jω)|
= |T(2jω)| = 1, we obtain
From Eq. (13), it is seen that the sinusoids are delayed by
different amounts of time. The nonlinear phase character-
istic has resulted in phase distortion. Although the human
ear is relatively insensitive to phase changes (3), applica-
tions such as control and instrumentation can be greatly
impaired by phase distortion. To illustrate this important
point further, assume that a signal vi (t) is applied to three
different hypothetical amplifiers. The signal vi (t) is com-
posed of two sinusoids and is given by
One sinusoid has twice the frequency of the other sinusoid.
One amplifier is perfectly ideal and has a gain G1 = 10 with
no phase shift. The second amplifier has a gain magnitude
equal to 10 and has a linear phase shift given by θ = −ω.
Thus, its transfer function can be expressed as
The third amplifier also has a gain magnitude equal to 10,
but it has a nonlinear phase characteristic given by θ =
−ω3 . Thus, its transfer function is given by
Figure 5 depicts the output of the first amplifier. Since
the amplifier is perfectly ideal, the output is exactly 10vi .
Figure 6 shows the output of the second amplifier, and it is
seen that the waveform at the output of the amplifier with
linear phase is the same as shown in Fig. 5 except that the
waveform in Fig. 6 has been delayed by 1 s. Delay of the
entire waveform does not constitute phase distortion. On
the other hand, the output of the amplifier with nonlinear
phase, shown in Fig. 7, is clearly distorted. For example, its
peak-to-peak value is more than 12% larger than it should
be. In the next section, we examine the use of a second-
order all-pass filter to linearize the phase of nth-order low-
pass filters.
PHASE EQUALIZATON
Phase equalization is the term used to describe compen-
sation employed with a filter or a system to remedy phase
distortion. The goal is to achieve linear phase (flat time
delay), and the compensator is labeled a phase equalizer.
In this section, we derive the specifications for a second-
order all-pass filter that can be used to linearize the phase
of most all-pole low-pass filters. The technique can also be
4 Phase Equalizers

Figure 4. Delay plots for the all-pass transfer

functions listed in Fig. 3. The plot for Q = ½ has
the largest delay near the origin.

Figure 5. Output voltage of perfectly ideal

amplifier with input voltage given by Eq. (14).
The amplifier has a gain equal to 10 with no
phase shift.

Figure 6. Output voltage of amplifier with lin-

ear phase characteristic. The output voltage is
delayed 1 s in comparison to the output voltage
shown in Fig. 5.
 Phase Equalizers 5

Figure 7. Output voltage of amplifier with non-

linear phase characteristic with input voltage
given by Eq. (14). The effects of phase distortion
are easily seen when this waveform is compared
with those in Figs. 5 and 6.

The use of a program that is capable of performing symbolic

algebra is recommended to obtain the Maclaurin series for
θ L . The results are
Figure 8. Cascade connection of a second-order low-pass filter
with a second-order all-pass filter. It is assumed there is no loading
between the two filters.

extended to other phase-equalization tasks. We begin the

derivation by linearizing the phase of a second-order low-
pass filter having a transfer function given by
Equation (20) can be used also to write the series for the
phase of the all-pass filter directly. Then, forming θ = θ L +
θ A and truncating the results after the term containing ω7
we obtain
Figure 8 depicts the cascade connection of this low-pass
filter with a second-order all-pass filter with transfer func-
tion TAP (s). The form of the transfer function of the all-pass
filter is given by Eq. (3), but for the purposes of this deriva-
tion, let us designate its undamped natural frequency as
ωA and its Q as QA . The overall phase of the cascade cir-
cuit is θ(ω) = θ L (ω) + θ A (ω) where θ L and θ A are the phase
contributed by the low-pass filter and the all-pass filter, re-
spectively. We wish to make θ(ω) approximate linear phase
in the Maclaurin sense (1). Since θ is an odd function of ω,
the Maclaurin series for θ has the form The next step is to set the coefficients of ω3 and ω5 equal to
zero in Eq. (21). Thus, we must satisfy the equations

where K1 is the first derivative of θ(ω) with respect to ω with

the result evaluated at ω = 0, and K3 is proportional to the
third derivative evaluated at ω = 0, and so on. Therefore, we
want to choose ωA and QA to make K3 and K5 equal to zero
in Eq. (18). Then K7 ω7 will be the lowest order undesired
term in the series for θ(ω).
Introduce parameters a and b to represent the left sides of
The phase θ L contributed by the second-order low-pass
Eqs. 22a and 22b, respectively. That is, let
filter can be expressed as
6 Phase Equalizers

is given by
Thus, we have two equations, Eqs. 22a and 22b, that involve
a, b, QA , and ωA . Upon eliminating ωA , we obtain a twelfth-
order equation for QA given by

k is positive, and TE (s) is the remaining portion of the over-

all transfer function and is of even order. We have assumed
that the odd order of To (s) arises because of the existence
of one real axis pole, the usual case. All other poles of To (s)
occur in complex conjugate pairs. Denoting the phase of
T1 (jω) as θ 1 (ω), we write
where

If we consider the case of linearizing the phase given in

For a given second-order low-pass transfer function, d can
be found from Eqs. 23a, and 23b. Then a positive solution
for QA is sought from Equation (24). Finally, ωA is obtained
from
Eq. (30) with a second-order all-pass transfer function, we
obtain
and the terms given in Eq. (31) are added to the expressions
for the parameters a and b for higher order odd transfer
functions.

Note that a positive result must be found both for QA from

Eq. (24) and for ωA from Eq. (26) in order to obtain a solu-
tion.
Although only a second-order low-pass filter transfer
function was utilized to derive Eqs. 24 and 26, these two
equations are used for the nth order all-pole case as well
because only the parameters a, b, and d need to be modi-
fied. For example, suppose we wish to linearize the phase
of a normalized fourth-order Butterworth filter, denoted as
B4 (s), with a second-order all-pass filter. The transfer func-
tion B4 (s) is given by

where ω1 = ω2 = 1, Q1 = 0.541196, and Q2 = 1.306563. The

parameters a and b become

Table 1 provides the values for QA and ωA needed to

Calculating d from Eq. (25) and employing Eqs. 24 and 26,
we obtain QA = 0.5434 and ωA = 1.0955. If the normalized
Butterworth transfer function is to be frequency scaled to
a practical frequency, then the all-pass transfer function
must be frequency scaled by the same amount.
Phase equalization has been applied only to transfer
functions of even order in the derivation and the example.
To apply phase equalization to an odd-order filter, we must
determine the additional factor to add to each parameter a
and b. An odd-order, all-pole, low-pass filter transfer func-
tion To (s) can be expressed as To (s) = T1 (s)TE (s) where T1 (s)
linearize the phase of low-pass Butterworth filters with a
3.01-dB variation in the passband and the phase of 1-dB
ripple Chebyshev low-pass filters. Note that no solution
exists for the second-order Butterworth filter. As an appli-
cation of Table 1, we find the step responses of two normal-
ized fifth-order Butterworth filters. One filter has a second-
order all-pass connected in cascade in order to linearize its
phase, and the other does not. The transfer function B5 (s)
is given by
In Fig. 9, the step response of B5 (s) has less delay, and the
step response of B5 (s)TAP2 (s) with QA and ωA obtained from

Figure 9. Step responses of fifth-order Butterworth low-pass fil-
ters with and without phase equalization. The step response of the
filter with phase equalization exhibits preshoot and has greater
delay.
Table 1 has greater delay due to the presence of the all-pass
filter. However, it is seen from Fig. 9 that the response for
the phase-equalized filter more nearly approximates the
step response of an ideal low-pass filter with delay because
the response of an ideal filter should begin ringing before it
rises to the upper amplitude level. In other words, it should
exhibit “preshoot.”
Oftentimes, the design of filters having frequency-
selective magnitude characteristics other than low-pass is
accomplished by applying Cauer transformations to a low-
pass prototype transfer function. Unfortunately, the Cauer
transformations do not preserve the phase characteristics
of the low-pass transfer function. Thus, if a Cauer low-pass
to bandpass transformation is applied to a low-pass filter
transfer function that has approximately linear phase, the
resulting bandpass filter transfer function cannot be ex-
pected to have linear phase, especially if the bandwidth of
the bandpass filter is relatively wide. An approach to lin-
earizing the phase of filters other than low-pass filters is to
make use of a computer program that plots delay resulting
from the cascading of a specified magnitude-selective filter
with one or more all-pass filters. Using Eq. (7) and Figure
4 as guides, the peaks of the time delays of the all-pass fil-
ters can be placed to achieve approximately linear overall
phase.
AN APPLICATION OF DELAY
An all-pass filter can be combined with a comparator to ob-
tain a slope-polarity detector circuit (4). The basic arrange-
ment of the all-pass filter and the comparator is shown in
Fig. 10. An LM311 comparator works well in this circuit,
and a first-order all-pass filter can be used for input signals
that are composed of sinusoids that do not differ greatly in
frequency. To understand the behavior of this circuit, sup-
pose vi (t) = Asin(ωt), where A is positive and represents the
peak value of the sine wave. The output voltage of the all-
pass filter is vA (t) = Asin(ωt-ωt1 ), where t1 is the delay in
seconds caused by the filter. Figure 11 depicts vi (t), vA (t),
and the output voltage of the comparator vo (t), for A = 4 V
and ω = 2π(100) rad/s. The output terminal of the compara-
tor has a pull-up resistor connected to 5 V. Ideally, when the
Phase Equalizers 7
Figure 10. Essential components of a slope-polarity detector.
slope of vi (t) is positive, vo (t) is high, and vo (t) is low when
the slope of vi (t) is negative. Actually, the circuit’s output
changes state at a time which is slightly past the time at
which vi (t) changes slope. It is at this later time that the
delayed input to the comparator, vA (t), causes the polarity
of the voltage (vi (t) − vA (t)) between the leads of the com-
parator to change. The need for an all-pass filter in this
application is clear because the amplitude of the input sig-
nal must not be changed by the delaying circuit no matter
the frequencies present in the input signal. A first-order
all-pass filter is ordinarily adequate for the task. The pole
and zero can be set far from the origin, and their placement
is not overly critical. Too little delay results in insufficient
overdrive for the comparator. Too much delay increases the
error in the time at which the comparator changes state be-
cause the polarity of the voltage between the leads of the
comparator does not change soon enough after the slope
of vi (t) changes. For the example illustrated in Fig. 11 in-
volving a simple sine wave, the amplitudes of the input
and delayed sine waves are equal at a time closest to zero
denoted by tE and given by
The voltage difference, denoted as VE , between the peak of
the input sine wave and the level at which the input and
delayed sine waves are equal is given by
If, for example, the delay provided by the all-pass filter is
0.5 ms for the 100-Hz input sine wave, then the input sine
wave will have decreased by approximately 50 mV from its
peak value before the comparator begins to change state.
This circuit works well at steady state for input signals
that do not contain significant high-frequency components.
Thus, it works reasonably well if the input signal is a tri-
angular waveform, but it does not work well with square
waves.
A SYNTHESIS APPLICATION
First-order all-pass filters can be utilized to realize filters
with magnitude-selective characteristics. For example, the
circuit shown in Fig. 12, which is based on (5) and (6), re-
alizes a bandpass filter transfer function by using a first-
order all-pass circuit in a feedback loop. The overall trans-
8 Phase Equalizers
Figure 11. Input voltage vi (t), delayed input voltage vA (t), and
comparator output voltage vo (t) for the slope-polarity detector
shown in Figure 10 when the input voltage is a sine wave.
fer function of the circuit is
where K1 is the gain factor associated with the transfer
function of the first-order all-pass filter. If C1 R1 = CR, K1
= 1, and R2 = R3 , then Eq. (35) reduces to the transfer
function of a standard second-order bandpass filter given
by
The Q and ω0 of the poles in Eq. (36) are
Although the circuit requires the matching of elements and
several operational amplifiers, including, possibly, a buffer
at the input, it demonstrates that all-pass filters can be
employed in the realization of filters having frequency-
selective magnitude characteristics.
Figure 12. Second-order bandpass filter realized by incorporat-
ing a first-order all-pass filter in a feedback path.
Figure 13. Passive circuit that can be used to realize a first-order
all-pass filter. Only one capacitor is needed.
ALL-PASS CIRCUIT REALIZATIONS
Voltage-mode Realizations
In this section, we examine a variety of circuits used to
realize all-pass transfer functions for which the input and
output variables of interest are voltage. Inductorless cir-
cuits for first-order all-pass filters can be realized using
the bridge circuit shown in Fig. 13. The transfer function
of this circuit is given by
If R1 = R2 , then Eq. (38) reduces to the transfer function of
an all-pass filter (7). However, the requirement that R1 =
R2 results in a gain factor equal to −½, which is small in
magnitude. Also, a common ground does not exist between
the input and output ports of the circuit.
The bridge circuit shown in Fig. 14, which can be re-
drawn as a symmetrical lattice, can realize first-order all-
pass transfer functions with a gain factor equal to 1. The
transfer function of this circuit is
If ZB = R and ZA = 1/(sC), a first-order all-pass transfer
function is obtained. If inductors are allowed in the circuit,
then the circuit in Fig. 14 can realize higher order all-pass
 Phase Equalizers 9

Figure 14. Passive circuit that can be used to realize first-order

all-pass filters with gain factor equal to 1. Two capacitors are
needed. If inductors are allowed, this circuit can realize higher
order all-pass transfer functions with complex poles.

transfer functions. For example, suppose a circuit is needed

to realize a third-order all-pass transfer function TAP3 (s)
given by

where p(s) and q(s) are the numerator and denomina-

tor polynomials, respectively. The denominator polynomial Figure 15. Single op-amp active realizations of first-order all-
q(s) can be expressed as the sum of its even part, m(s), and pass filters. (a) First-order all-pass circuit with gain factor equal
its odd part, n(s). Thus, q(s) = m(s) + n(s). If the roots of q(s) to +1. (b) First-order circuit with gain factor equal to −1.
are confined to the open LHP, then the ratios n/m and m/n
meet the necessary and sufficient conditions to be an LC
to realize the all-pass circuits used in Figs. 10 and 12. Both
driving point impedance (8). Thus, if the numerator and de-
circuits in Fig. 15 can be modified to realize second-order
nominator of the transfer function in Eq. (40) are divided
inductorless all-pass transfer functions, but the poles and
by m(s), we obtain
zeros are confined to the real axis. Resistor R1 in Fig. 15(a)
and resistor R2 in Fig. 15(b) are replaced by RC impedances
Z1 and Z2 , respectively. The circuit in Fig. 15(a) is clearly
related to the all-pass circuit shown in Fig. 13. An op-amp
By comparing the result in Eq. (41) with Eq. (39), it is seen has been employed so that the input and output voltages
that ZA = 1  and the box labeled ZB in Fig. 14 consists of have a common point of reference.
the series connection of a 1 Henry inductor and an LC tank The realization of inductorless second-order all-pass cir-
circuit that resonates at 1 rad/s. However, the resulting cuits with complex poles can be achieved with the circuits
circuit requires six reactive elements and does not have a shown in Fig. 16. These circuits are minimal in the num-
common ground between the input and output ports, and ber of capacitors required. If the op-amps are ideal in the
these properties may preclude the use of bridge circuit all- sense of having infinite gain-bandwidth product, then both
pass networks in some applications. circuits have the same transfer function, namely,
Single transistor first-order all-pass transfer function
realizations have been described by several authors. The
interested reader may refer to Refs. 9 and 10 for addi-
tional information. Inductorless second-order realizations
are also described in Refs. 9 and 10 but the poles and zeros
of the transfer functions are confined to the real axis. Rubin
and Even extended the results in Ref. 9 to include higher where
order all-pass transfer functions with complex poles, but
inductors are employed (11).
Figure 15 shows two first-order all-pass circuits based
on operational amplifiers (op-amps) (12, 13, also see Active
filters). The transfer functions are given by Ta = (Z2 − In order to obtain an all-pass transfer function, we must
kR1 )/(Z2 + R1 ) and Tb = (−kZ1 + R2 )/(Z1 + R2 ). Thus, if impose the requirement
Z2 in Fig. 15(a) or if Z1 in Fig. 15(b) are selected to be the
impedances of capacitors and k = 1, then first-order all-pass
circuits are realized. The circuit in Fig. 15(a) can be used
10 Phase Equalizers

Figure 17. Second-order all-pass circuit realization based on a

bandpass filter circuit with negative gain factor.

a second-order all-pass can be realized by summing the

output of the bandpass filter with the input signal. Figure
17 shows an all-pass realization using this scheme that is
based on the bandpass filter described earlier in this arti-
cle. The transfer function is

where ω0 and Q are given in Eq. (37). To obtain an all-pass

Figure 16. Op-amp circuits for the realization of inductorless
second-order all-pass filters with complex poles. (a) Circuit use-
ful in low Q applications in which a light load must be driven. (b)
Circuit employed in higher Q applications, but it requires a buffer
if a load must be driven.
If Eq. (44) is satisfied, then Eq. (42) becomes
where
filter, RX and RY must satisfy
It is seen that this same scheme is employed in the all-
pass filter circuit depicted in Fig. 16(b). If a second-order
band-pass filter is available that has a positive gain fac-
tor, then a second-order all-pass filter can be obtained by
“interchanging input and ground” (17).
Operational transconductance amplifiers (OTAs) can
also be used to obtain active circuit realizations of voltage-
mode all-pass filters. These active devices are approx-
imations to differential-input voltage-controlled current
sources (18, 19) and ideally have infinite input and out-
put impedances. Figure 18 shows circuit configurations for
a first-order and a second-order all-pass filter. If the OTAs
are ideal, the transfer function for the first-order filter is

Although both circuits have the same transfer function

when the op-amp is ideal, there are differences in the cir-
cuits. The circuit in Fig. 16(a) can drive light loads with-
where gm1 and gm2 are the transconductances of OTA1 and
out an output buffer (14), whereas the circuit in Fig. 16(b)
OTA2, respectively. The transconductance is controlled by
requires a buffer for such loads (15). However, it can be
a control current that is applied to a terminal (not shown)
shown that when the finite op-amp gain-bandwidth prod-
of the OTA. Ideally, the transconductance is constant for
uct is taken into account, the circuit in Fig. 16(b) is better
a constant control current. If the control currents for the
suited for the realization of all-pass transfer functions with
OTAs in Fig. 18(a) are adjusted so that gm1 = gm2 , then a
poles having a Q greater than about five. Since the Qs re-
first-order all-pass filter is obtained. The transfer function
quired for phase equalization of low-pass filters are usually
for the circuit shown in Fig. 18(b) is
quite low, the circuit in Fig. 16(a) is a good choice for that
application.
If the requirement for a minimum number of capaci-
tors is relaxed, then many inductorless active circuits are
available that can realize second-order all-pass transfer To obtain a second-order all-pass circuit, the transconduc-
functions with complex poles. The interested reader is in- tances in Fig. 18(b) must satisfy
vited to consult Ref. 16. In fact, if a second-order bandpass
circuit is available which has a negative gain factor, then

Figure 18. Operational transconductance amplifier (OTA) all-
pass filter realizations. (a) First-order all-pass circuit. (b) Second-
order all-pass circuit.
and gm4 = gm5 . For realizing integrated circuit versions of
filters (see Analog processing circuits), OTAs are partic-
ularly suited, because they are relatively simple in struc-
ture, and they can operate at higher frequencies than, say,
voltage-mode op-amps. However, OTAs depart from ideal
in many aspects, of which the chief aspects are finite input
and output impedances, a frequency-dependent transcon-
ductance, and a limited range of input signal that is allowed
for linear operation. The input and output impedances also
are dependent on the control current (18, 19). The non-
ideal characteristics of OTAs must be taken into account
in the design of most circuits if accurate results are to be
obtained.
Voltage-mode all-pass filters can also be constructed us-
ing current-feedback op-amps (CFOAs). Soliman (20) pro-
vides several useful realizations.
Current-mode Realizations
All-pass filters in which the input and output variables
of interest are currents are called current-mode circuits.
If, in addition, the variables of interest throughout the
circuit are currents, then the current is a fully current-
mode circuit. Active, fully current-mode circuits are of in-
terest because they offer a larger bandwidth if properly
designed than do active voltage-mode circuits (21). Pas-
Phase Equalizers 11
Figure 19. Current-mode all-pass circuits. (a) First-order. (b)
Second-order.
sive current-mode all-pass filters are easily obtained from
passive voltage-mode filters because the networks are re-
ciprocal. Thus, if the output port of the voltage-mode cir-
cuit is excited by a current source and if the input port of
the voltage-mode circuit is shorted with the output current
flowing through this short, then the current transfer func-
tion of the resulting circuit is the same as the voltage-mode
transfer function of the original circuit. However, the input
and output currents do not have a common ground. Active
current-mode all-pass filters with a common ground can be
obtained from voltage-mode filters that incorporate a volt-
age amplifier by using the adjoint network concept (22). For
example, the application of the adjoint network concept to
the first-order voltage-mode all-pass circuit in Figure 15(b)
results in the fully current-mode all-pass circuit shown in
Fig. 19(a). This first-order all-pass filter employs a second-
generation, positive current conveyor (CCII+) as the active
device (see Current conveyors). The transfer function of
the circuit is
If Z1 is chosen as (1/(sC), then a first-order current-mode
all-pass filter is obtained. Although the all-pass filter in
Fig. 19(a) uses the minimum number of passive elements,
the capacitor is not counted as a grounded capacitor (a ca-
pacitor in which one lead of the capacitor has its own con-
nection to ground), because it is connected to ground only
through the output lead. If this circuit is cascaded with
another circuit, the output lead may be connected to a vir-
tual ground, and in this case, the capacitor would not be
a physically grounded one. Other first-order all-pass real-
izations that incorporate one (grounded) capacitor and use
one CCII have been given (23), although they employ four
resistors. These realizations are easily cascaded.
A second-order all-pass filter that uses only one CCII is
shown in Fig. 19(b). This circuit can realize complex poles
12 Phase Equalizers

and uses the minimum number of capacitors (23). Note that

no feedback elements are connected to the output terminal
z of the current conveyor, and so this all-pass realization
can be easily cascaded to achieve higher order realizations.
Either a positive or a negative current conveyor can be
employed. The transfer function of the circuit is given by

where a and b are identified in Fig. 19(b) and k is

The plus sign is chosen if a CCII+ is used, and the minus

sign is chosen if a CCII− is utilized.
To realize an all-pass transfer function, the elements
must also satisfy
Figure 20. Transfer function pole-zero plots. (a) and (c) Plots for
minimum phase transfer functions. (b) and (d) Plots for nonmini-
mum phase transfer functions. The transfer functions correspond-
ing to the plots in (a) and (b) have the same magnitude character-
Minimum passive sensitivities are obtained with C1 = C2 , istics but differ in phase characteristics. The transfer functions
but the spread of element values can be reduced for larger corresponding to the plots in (c) and (d) have the same phase char-
Qs by choosing C2 larger than C1 . acteristics but differ in magnitude characteristics.
CCIIs are simpler to construct than first-generation cur-
rent conveyors (CCIs), and so are much more widely used.
same, but the magnitude characteristics differ. Still, the
However, a second-order all-pass filter with complex poles
second-order transfer function corresponding to Fig. 20(d)
can be realized using a single CCI (24). This circuit uses
is a nonminimum phase one. Note that it has the same
the minimum number of capacitors, and both capacitors
phase as the fourth-order transfer function corresponding
are grounded.
to Fig. 20(c).
A nonminimum phase transfer function can be ex-
MINIMUM PHASE AND ALL-PASS FILTERS pressed as the product of a minimum phase transfer func-
tion and an all-pass transfer function. For example, sup-
We say that a real, rational, stable transfer function in s pose we have the transfer function
is a minimum phase transfer function if all its zeros are
confined to the closed LHP. No zeros are allowed in the (s − 1)[(s − 3)2 + 1]
T (s) =
RHP. On the other hand, a nonminimum phase transfer [(s + 1)2 + 1][(s + 2)2 + 1]
is one that has one or more zeros in the RHP. An all-pass By multiplying T(s) by
transfer function is nonminimum phase. Figure 20 depicts
pole-zero diagrams for minimum phase [Figs. 20(a) and (c)]
and nonminimum phase [Figs. 20(b) and (d)] transfer func-
tions. To convert the diagram in Fig. 20(a) to a diagram cor-
responding to a nonminimum phase transfer function with and regrouping the factors, we obtain
the same magnitude characteristic, we reflect the zeros in
Fig. 20(a) through the origin. Thus, z3 = −z1 and z4 = −z2 in
Fig. 20(b). The corresponding transfer functions have the
same magnitude characteristics because the lengths of the
vectors from the zeros z1 and z2 to an arbitrary point P on
the jω axis in Fig. 20(a) are the same as the lengths of the where TMP (s) is a minimum phase transfer function and
vectors from the zeros z3 and z4 to P in Fig. 20(b). How- TAP (s) denotes an all-pass transfer function.
ever, considering the order of the transfer functions (third For sinusoidal steady state analysis applications, a min-
order) and that both have the same magnitude character- imum phase transfer function T(s) can be expressed in the
istic, there is more phase lag associated with the pole-zero form
diagram in Fig. 20(b) than with Fig. 20(a).
In Figs. 20(c) and 20(d), a pair of complex poles, labeled
p1 and p2 , has been reflected into the RHP as zeros labeled where α(ω) is the attenuation function in nepers and θ(ω)
z1 and z2 , where z1 = −p1 and z2 = −p2 . The phase char- is the negative of the phase function in radians. These
acteristics of the corresponding transfer functions are the two functions are not independent but are related by the

Hilbert transforms given by
where  is a dummy variable and α(0) is the value of the
attenuation function at zero frequency (25). Equations 55a
and 55b show that if α(ω) is specified for all ω, then θ(ω)
is also specified over all ω for a minimum phase transfer
function. Thus, α(ω) and θ(ω) cannot be specified indepen-
dently. Even if α(ω) is specified over only part of the jω axis
and θ(ω) is specified over the remaining parts, then T(jω)
is determined over the whole axis.
However, attenuation and phase are independent of
each other in the case of nonminimum phase transfer func-
tions. This is the reason that nonminimum phase transfer
functions usually are used to meet simultaneous attenu-
ation and phase specifications (26). Nevertheless, all-pole
low-pass minimum phase transfer functions can serve as
useful prototypes for all-pass filters (27). An all-pole filter
has a transfer function given by
where we take the gain factor H to be positive for conve-
nience, and m(s) and n(s) are the even and odd parts of
the denominator polynomial q(s), respectively. The phase
of this low-pass filter is given by
An all-pass transfer function constructed from this low-
pass transfer function has the form
and has a phase characteristic that can be expressed as
Thus, the phase and delay characteristics are the same
as for the low-pass prototype transfer function except for
the factor of two. Suppose that the low-pass prototype is
a Bessel filter transfer function. Then an all-pass transfer
function can be devised that also has maximally flat delay
at ω = 0 and which has, ideally, a lossless magnitude charac-
teristic. For example, the third-order Bessel filter transfer
function is
Thus, the corresponding all-pass transfer function is
The Bessel filter produces a 1-s delay, and the all-pass fil-
ter generates a 2-s delay, but the delay in both cases is
Phase Equalizers 13
maximally flat at ω = 0.
DIGITAL ALL-PASS FILTERS
Digital filters can be classed into two categories: finite im-
pulse response (FIR) filters and infinite impulse response
(IIR) filters (see Digital filters). The FIR filters can be
designed with perfectly linear phase. However, in general,
stable, realizable IIR filters cannot achieve perfectly linear
phase. Although IIR filters can be designed to approximate
given magnitude and phase requirements, a popular ap-
proach to digital filter design is to base a design on contin-
uous time filter approximations and transform the result
to digital filter form. Then the phase is linearized (equal-
ized) using cascaded digital all-pass filters. This approach
is a practical one (among several practical approaches) if
the order of the all-pass filter required is reasonable (28).
To devise a first-order, real, stable, all-pass transfer
function, we place a zero outside the unit circle in the z
plane on the real axis at z = (1/r1 ) corresponding to a pole
at z = r1 , |r1 | < 1. The resulting transfer function is given
by
or
Evaluating H(z) in Eq. (68) for z = ejωT , where T is the sam-
pling interval, we obtain
The numerator of the term in parentheses in Eq. (69) is the
conjugate of the term in the denominator. Thus, the magni-
tude of the term in parentheses is one. Also, the magnitude
of −ejωT is one. As a result, we have |H(ejωT )| = 1/|r1 |. The
phase, denoted as β(ω), for r1 assumed to be positive is ob-
tained from Eq. (69) as
Since the magnitude characteristic is a constant over fre-
quency and yet the phase characteristic changes as a func-
tion of frequency as can be seen from Eq. (70), the transfer
function in Eq. (67) is an all-pass one.
A second-order, real, stable all-pass transfer function
with complex poles can be devised in a manner similar to
that used for the first-order transfer function. For a com-
plex pole at z = rejθ , 0 < θ < π, we must have another pole
at z = re−jθ if the transfer function is to be real. We take
r positive for convenience and r < 1 for stability. Thus, for
each pair of complex poles given by z = re±jθ , we place a pair
14 Phase Equalizers
Figure 21. Poles and zeros of a digital third-order all-pass filter
transfer function.
of complex zeros outside the unit circle at z = (1/r)e±jθ . The
resulting transfer function is given by
which can be rearranged into
The magnitude characteristic is easily obtained by evalu-
ating H(z) in Eq. (72) for z = ejωT . The result is |H(ejωT )| =
1/r2 , and the phase is given by
A pattern is indicated by Eqs. 68 and 72 for higher order,
real, stable all-pass transfer functions. Let N be the order
of the all-pass transfer function, and let the poles be inside
the unit circle and occur in conjugate pairs if complex. That
is, each complex pole pair is described by
where 0 ≤ m ≤ N/2 and 0 < ri < 1. Then the transfer func-
tion is given by
where k is given by
and all the coefficients ai in Eq. (75) are real. The mag-
nitude characteristic of the transfer function in Eq. (75)
evaluated for z = ejωT is 1/|k|. Figure 21 shows a pole-zero
plot on the z plane for an all-pass transfer function with a
real pole at z = r1 and two conjugate complex poles at z =
r2 e±jθ . The transfer function is real and stable.
Figure 22. Plots of the first function to the right of the equal sign
in Eq. (70) for values of r = 0.2, 0.4, 0.6, 0.75, and 0.8.
The delay of an IIR digital filter can be made more flat
by connecting all-pass filters in cascade. The coefficients
required for the all-pass filters as well as the number of
all-pass filters needed are best determined by a cut-and-try
process using a computer program that plots delay charac-
teristics interactively and quickly. However, an aid for de-
lay equalization can be established. For this purpose, let θ
in the transfer function for a second-order all-pass transfer
function in Eq. (71) be expressed in terms of the sampling
interval T as θ = αT. Then the normalized time delay char-
acteristic can be obtained from −dβ/dω applied to Eq. (73).
Thus, we have
Equation (77) expresses the normalized delay as the sum
of two functions. Let us examine the first function to the
right of the equal sign. Its maximum value is (1 + r)/(1 −
r), which occurs at ω = α in −π ≤ ωT ≤ π. Since the de-
lay characteristics obtained from cascaded all-pass filters
are described by a sum of functions of this type, a conve-
nient design aid (29) is obtained by plotting this function
for several values of r. These plots are shown in Fig. 22. The
frequency axis has been normalized to (ω − α)/ωs , where ωs
is the sampling frequency given by ωs = 2π/T.
As an illustration of the concept, we apply delay equal-
ization to a bandpass filter transfer function (8) given by
 Phase Equalizers 15

Figure 24. Digital all-pass filter realizations. (a) First-order re-

alization. (b) Second-order realization.

where X and Y are the input and output variables, respec-

Figure 23. Equalizing the delay characteristic of a bandpass fil- tively, and a1 is the coefficient of a multiplier. The structure
ter in the neighborhood of its center frequency with a second-order in Fig. 24(b) can be used to realize second-order all-pass
all-pass filter. transfer functions. Its transfer function is given by

Both structures in Fig. 24 are minimal in the number of

delays required. Higher order all-pass filters can be con-
This filter has its center frequency at ω = ωs /4 and has a structed by cascading first- and second-order realizations.
bandwidth described by 0.2ωs ≤ ω ≤ 0.3ωs . The normal- There are many other structures that can be used to re-
ized delay characteristic of the bandpass filter is denoted alize first- and second-order all-pass filters; an extensive
by τ BP /T and is shown in Fig. 23. It is clear that this charac- catalog of such structures is given in Ref. 30, and a discus-
teristic would benefit by the addition of a delay lump from sion of the effects of multiplication roundoff and hardware
a second-order all-pass filter located at ω = ωs /4 with r = requirements is provided.
0.7. That is, a second-order all-pass filter is utilized with
normalized delay characteristic given by Eq. (77) with α
= ωs /4 and r = 0.7. The normalized delay characteristic of
the all-pass filter is labeled τ AP /T in Fig. 23. The resulting
overall normalized delay characteristic, denoted by τ o /T, is
also shown, and it is seen that the result is flatter in the
neighborhood of the center frequency at the expense of the
characteristic at the edges of the bandpass filter passband.
Additional all-pass delay lumps can be employed to correct
the delay at the band edges.
First- and second-order digital all-pass filters can be re-
alized using the structures shown in Fig. 24. Figure 24(a)
shows a realization for a first-order filter that employs only
one delay (30). Its transfer function is
16 Phase Equalizers

BIBLIOGRAPHY 25. C. S. Lindquist Active Network Design, Long Beach, CA: Stew-
ard & Sons, 1977.
1. A. Budak Active and Passive Network Analysis and Synthesis, 26. A. S. Sedra P. O. Brackett Filter Theory and Design: Active and
Boston: Houghton Mifflin, 1974; reprinted Prospect Heights, Passive, Portland: Matrix Publishers, 1978.
IL: Waveland Press, 1991. 27. L. P. Huelsman Active and Passive Analog Filter Design, New
2. H. J. Blinchikoff A. I. Zverev Filtering in the Time and Fre- York: McGraw-Hill, 1993.
quency Domains, New York: Wiley, 1976; reprinted Malabar, 28. L. R. Rabiner B. Gold Theory and Application of Digital Signal
FL: Robert E. Krieger, 1987. Processing, Englewood Cliffs, NJ: Prentice-Hall, 1975.
3. M. S. Ghausi K. R. Laker Modern Filter Design, Englewood 29. S. A. Tretter Introduction to Discrete-Time Signal Processing,
Cliffs, NJ: Prentice-Hall, 1981. New York: Wiley, 1976.
4. P. Klemp Phase shifter yields slope-polarity detection, EDN, 30. S. K. Mitra K. Hirano Digital all-pass networks, IEEE Trans.
41 (6): 92, 94, 96, 1996. Circuits Syst. CAS-21: 688–700, 1974.
5. D. J. Comer J. E. McDermid Inductorless bandpass charac-
teristics using all-pass networks, IEEE Trans. Circuit Theory,
CT-15 (4), 501–503, 1968. Reading List
6. D. T. Comer D. J. Comer J. R. Gonzalez A high-frequency in-
tegrable bandpass filter configuration, IEEE Trans. Circuits W.-K. Chen ed., The Circuits and Filters Handbook, Boca Raton,
Syst. II, Analog Digit. Signal Process., 44 (10): 856–860, 1997. FL: CRC Press, 1995.
A. B. Williams F. J. Taylor Electronic Filter Design Handbook, New
7. A. Budak Circuit Theory Fundamentals and Applications, 2nd York: McGraw-Hill, 1995.
ed, Englewood Cliffs, NJ: Prentice-Hall, 1987.
8. H. Lam Analog and Digital Filters, Englewood Cliffs, NJ: PETER ARONHIME
Prentice-Hall, 1979. University of Louisville, 10
9. P. Aronhime A one-transistor all-pass network, Proc. IEEE, Eastern Parkway, Louisville,
55: 445–446, 1967. KY, 40292
10. H. J. Orchard Active all-pass networks with constant resis-
tance, IEEE Trans. Circuit Theory, CT-20: 177–179, 1973.
11. H. Rubin R. K. Even Single-transistor all-pass networks,
IEEE Trans. Circuit Theory, CT-20: 24–30, 1973.
12. R. Genin Realization of an all-pass transfer function using
operational amplifiers, Proc. IEEE, 56: 1746–1747, 1968.
13. P. Aronhime A. Budak An operational amplifier all-pass net-
work, Proc. IEEE, 57: 1677–1678, 1969.
14. T. Deliyannis RC active allpass sections, Electron. Lett., 5 (3):
59–60, 1969.
15. A. Budak P. Aronhime Frequency limitations on an opera-
tional amplifier realization of all-pass transfer functions with
complex poles, Proc. IEEE, 58: 1137–1138, 1970.
16. G. S. Moschytz A general all-pass network based on Sallen-Key
circuit, IEEE Trans. Circuit Theory, CT-19: 392–394, 1972.
17. D. Hilberman Input and ground as complements in active fil-
ters, IEEE Trans. Circuit Theory, CT-20: 540–547, 1973.
18. R. Schauman M. S. Ghausi K. R. Laker Design of Analog Fil-
ters, Englewood Cliffs, NJ: Prentice-Hall, 1990.
19. P. Aronhime Applications of operational amplifiers. InJ. C.
Whitaker (ed.), The Electronics Handbook, 2nd Ed. Boca Ra-
ton, FL: CRC Press, 2005.
20. A. M. Soliman Applications of the current feedback opera-
tional amplifiers, Analog Integr. Circuits Signal Process., 11:
265–302, 1996.
21. C. ToumazouF. J. LidgeyD. G. Haigh eds., Analogue IC Design:
The Current-Mode Approach, London: Peter Peregrinus, 1990.

22. G. W. Roberts A. S. Sedra All current-mode frequency selective

circuits, Electron. Lett., 25 (12): 759–761, 1989.
23. A. M. Soliman Generation of current conveyor-based all-pass
filters from op amp-based circuits, IEEE Trans. Circuits Syst.
II, Analog Digit. Signal Process., 44: 324–330, 1997.
24. P. Aronhime D. Nelson J. Zurada C. Adams Realization of
current-mode complex pole all-pass networks using a single
current conveyor. In Proceedings of the International Sympo-
sium on Circuits and Systems, vol.4, 1990, pp. 3193–3196.
446 ANALOG COMPUTER CIRCUITS

VI
–
V0 = K(VP – VI )
+
VP
(a)

+15

VI
–
+
– V0 = K(VP – VI )
+
VP

–15
(b)

Figure 1. Operational amplifier symbol. (a) Operational amplifier.

(b) Operational amplifier with power supply voltages attached.

and transistors) connected to process analog signals (as op-

posed to digital signals) which are conceptually modeled as
continuous functions of time. Analog computers have limited
bounds namely, Emax and Emin. Since the early 1960s, analog
computers have used solid state components, and the signal
range is typically ⫾10 V. The operational amplifiers are usu-
ally made in integrated circuit form. They may be supplied as
separate modules, mounted on a circuit board, or a part of a
larger integrated circuit. We are here primarily interested in
the operation of such electronic systems to solve ordinary dif-
ferential equations, although operational amplifiers are often
used in the design of signal filtering circuits and in the design
of interface signal-conditioning subsystems to go between
real-world signals from a wide variety of transducers and sub-
sequently to digital signal processing systems used for data
logging and analysis.
A typical ideal operational amplifier model is shown in Fig.
1. The ideal model has an input–output description

V0 = K(VP · VI ), where K  1

V1 –K1

V2 –K2
Σ V0
Vn –Kn

(a)
–K1
–K2
V0
–Kn

(b)
–K1
V1
V2 –K2
V0
Vn –Kn
ANALOG COMPUTER CIRCUITS
(c)
The term analog computer usually refers to an electronic cir- Figure 2. Conventional operational amplifier circuit block symbols.
cuit consisting of operational amplifiers, resistors, and capaci- (a) Summer–inverter. (b) Inverting summer–integrator. (c) Older
tors along with additional electronic components (e.g., diodes symbol for inverting summer–integrator.

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.
 ANALOG COMPUTER CIRCUITS 447

R1 R1 Basic input–output relations for the circuit in Fig. 3(c) are

V1 V1
R2 R2

n

V2 V2 V0 = −RF (V /R) i = 1, 2, . . ., n
i=1
RF C
= −RF (V1 /R1 + V2 /R2 + · · · )
Rn Rn Zini = Ri
Vn – Vn –
V0 V0 For Fig. 3(d):
+ +
RF ZF V0 = −(1 + RF /Ri )V
Ki = Ki =
Ri Ri
Example. Consider the mechanical system of Fig. 4(a). A
(a) (b)
simple force balance equation gives

RF f =0
R1 R1 RF
RF
V2 – with initial conditions X(0) and X(0) or
R2 Vo
V2 + – −F + MẌ − DẊ − KX = 0
Vo
Vn Vin + or
Rn
Ẍ = (K/M)X + (D/M)Ẋ + (F/M)
(c) (d)

Figure 3. Operational amplifier circuits. (a) Summer–inverter. (b) Let M ⫽ 5 kg, D ⫽ 0.1 Ns/m, and K ⫽ 1.0 m/N; then
Inverting summer–integrator. (c) Basic summer–inverter circuit. (d)
Basic noninverting circuit. Ẍ = (0.2)X + 0.02Ẋ + 0.2F)

The operational amplifier circuit of Fig. 4(b) shows a basic

More information on operational amplifiers is available in
Refs. 1 and 2.
Primary operational amplifier circuits for analog comput-
ing are integrating and summing circuits. Figure 2(a) shows
the block diagram for a summer–inverter. Figure 2(b) shows
a summer–inverting integrator. A skilled analog computer
programmer learns to cleverly program his or her collection
of summers and integrators to implement an electronic model
which ‘‘solves’’ a set of ordinary differential equations (ODEs)
F (t) = a0 X + a1 Ẋ + a2 Ẍ + · · ·
analog computer model for this system. F(t) may be a voltage
generated by a variety of signal sources—for example, ‘‘func-
tion generator’’ types of variable-frequency sine-square wave
generators, recorded signal sources, and so on. Often we may
not want a ‘‘real’’ model of this system but will want to scale
or denormalize the circuit to get a repetitive display (e.g., on
an oscilloscope). We can slow down a simulation by making
the capacitors larger, or we can speed it up by making them
smaller by the same time scale factor.

;;;
OPERATIONAL AMPLIFIER CIRCUITS
Figure 3 shows corresponding operational amplifier circuits.
As indicated in Chapter 1 of Ref. 1, the ideal operational For precise signal processing, one often uses nonlinear opera-
amplifier has a very high open loop gain and input impedance tional amplifier circuits. Important nonlinear operations in-
and a relatively low output impedance. clude:

;
C C R

5R
x F – R
5R – R
+ X –
K + –X
M X
F(t) +
mass
Spring 50R

Friction
D

(a) (b)

Figure 4. Spring-mass system. (a) Mechanical system. (b) Operational amplifier analog com-
puter model. R ⫽ 106 ⍀, C ⫽ 10⫺6 F.
448 ANALOG COMPUTER CIRCUITS

R1
eg 5R
Nonlinear
V1
network
+15 V
R2 RA
V2 – V0 = f ( in ) D1 1500 Ω

+
Vin RB
500 Ω
eg 0 i1 + i2 + in = 0 R1 RF
5 kΩ
Figure 5. General nonlinear operational amplifier circuit configu-
ration.
–
V0
+
p i
+
RC
On
D2 500 Ω
i V
On i > 0 Off i < 0
Off V RD
RF
– K= 1500 Ω
R1
n
(a) (b) (c) (d) –15 V

Figure 6. P–n junction diode. (a) Diode symbol; (b) ‘‘demon-with-a- Figure 9. Operational amplifier circuit for a limiter amplifier.
switch’’ model; (c) diode ON or forward biased (d) diode OFF or re-
verse biased.

V0
iE iC
VE VC No RF
Emitter Collector 5
RF /R1

With RF

VEB VCB V1
α RI C α FI E
iB
αF
βF ≤ 1– α
VB F
1
Base 1– αF –5

Figure 7. Npn bipolar junction transistor model (BJT). 웁F is forward

biased current gain.
Figure 10. Direct-current transfer characteristic for circuit in Fig. 9.

V1 V0 V1
V0
ER

V0 V0

L+

K
V1
ER
V1
L–

Figure 11. Comparator block symbol. ER is reference voltage.

Figure 8. Limiter operator.

 ANALOG COMPUTER CIRCUITS 449

Clamp or VI
5R
feedback – V0
limiter
+
V1 VP VV
– V0 = 1 2
10
V0 (a)
+
RA – V2 > 0
–ER
+
RB R2
R1
V0 – V0
(a)
+ 10R2 V1
V0 V0 = –
R1 V2

V+ (b)

Eh Figure 13. Block symbols: (a) Multiplier. (b) Divider.

V1

E RR 1
R2 used in instrumentation systems to prevent signal overloads.
One amplifier actually provides an inverting limiter.
(b) The one-amplifier limiter or comparator circuit of Fig. 9
V0 V0 actually provides the transfer characteristic of Fig. 10. The
With hysteresis resistance string RA –RD sets the limiting levels.
Without RF, the circuit of Fig. 9 provides a comparator,
V+
V+ which may operate with a reference voltage ER, (Figs. 11 and
12).
0 t 0 t Useful comparator circuits should have some hysteresis
Squegging Eh to prevent an ambiguous chattering or ‘‘squegging’’ at the
comparator switch point (just as a household thermostat pro-
(c) (d)
vides hysteresis with a small magnet associated with its con-
Figure 12. Comparator behavior. (a) General circuit diagram. (b) Di- tacts). Figure 12 shows a one-amplifier (inverting) compara-
rect-current transfer characteristic. (c) ‘‘squegging’’ (i.e., no hystere- tor. The hysteresis is established by the network RA –RB,
sis). (d) Comparator behavior with hysteresis. which yields

Eh = RB (V+ )/(RA + RB )
Limiters (Figs. 8 to 10)
Comparators (Figs. 11 and 12) Analog multipliers and dividers are designed in a variety of
Multipliers and dividers (Fig. 13) ways (Fig. 13). A popular method uses logging–antilogging
Waveform generators (Figs. 14 and 15) circuits (see Ref. 1). Sinusoidal waveform generators may be
implemented using the block diagrams of Figs. 14 and 15. The
circuit of Fig. 14 generates sine waves by implementing the
Circuits based upon these types of operations may be ex-
solution of an undamped second-order ODE. The block dia-
tended to circuits that precisely measure absolute value, am-
plitude, peak value, and logarithmic operations. (Another way
of making a multiplier is by the use of antilog or exponentia-
tion operators.) A variety of other waveform generators, in-
cluding triangle waveform and very low-frequency oscillators Soft amplitude Inverting
(function generators) and frequency modulation (FM) oscilla- included limiter integrator
tors, may be implemented. Detailed discussions of nonlinear –w0 –w0
operators appear in Refs. 1 and 2. V0
Figure 5 shows a general diagram for nonlinear opera-
tional amplifier circuits. The operational amplifier forces the
– w0
current at the inverting terminal or ‘‘summing junction volt-
age’’ to be zero.
Figure 6 shows a ‘‘demon with a switch’’ model of a junc- –1
tion diode. When the diode is ‘‘on,’’ the forward drop is not –V0
really zero but may be as much as 0.5 V. The bipolar junction
<< 1
transistor (BJT) (Fig. 7) provides a more flexible active device
for nonlinear circuit design. The limiter operator (Fig. 8) is Figure 14. Sinusoidal waveform generator.
450 ANALOG COMPUTERS
VT
—K
V1
Inverting Bistable
integrator
Figure 15. Function generator block diagram for generating low-fre-
quency triangle and square waves.
gram of Fig. 15 shows a diagram of the ‘‘function generator’’
type of circuit to generate square and triangle waveforms (see
Ref. 1).
BIBLIOGRAPHY
1. J. V. Wait, L. P. Huelsman, and G. A. Korn, Introduction to Opera-
tional Amplifier Theory and Applications, New York: McGraw-
Hill, 1992.
2. S. Franco, Design with Operational Amplifiers and Analog Inte-
grated Circuits, New York: McGraw-Hill, 1988.
Reading List
Analog Devices, Designers References Manuals, Norwood, MA.
Burr-Brown Corp., Integrated Circuits Data Books, Tucson, AZ.
F. H. Mitchell, Jr. and F. H. Mitchell, Sr., Introduction to Electronics
Design, Englewood Cliffs, NJ: Prentice-Hall, 1988.
R. J. Smith and R. C. Dorf, Circuits, Devices and Systems, 5th ed.,
New York: Wiley, 1992.
Texas Instruments, Linear Circuits, Dallas, TX.
JOHN V. WAIT
ANALOG COMPUTERS
Computing devices capable of mapping inputs to outputs
without human intervention and of providing numerical solu-
tions to complex problems have been available in various
forms for over 150 years. In many of the early devices, infor-
mation was represented in mechanical form, as in the me-
chanical calculators that became invaluable for business data
processing in the first half of the twentieth century. Others
employed electric representations, as in the network ana-
lyzers that played an important role in a wide variety of engi-
neering applications during same period.
The utilization of electronic circuits as components of auto-
matic computers was made possible by developments and in-
ventions stimulated by military requirements during World
War II, particularly in the United States and Great Britain.
One class of these computers was primarily developed as part
of the Manhattan Project to help solve the complex partial
differential equations that characterize various physical pro-
cesses in atomic bombs. These represented extensions of me-
chanical calculators, but were vastly more powerful in their
ability to do arithmetic. A second class of computing tech-
niques was developed to help in the performance of integral
and differential calculus as required for the simulation of dy-
namic mechanical and electromechanical systems, such as
ships and aircraft, and for a wide variety of control tasks.
The members of the first category became known as digital
computers, while the second class was termed analog comput-
ers and devices.
The years immediately following World War II saw the
rapid extension of electronic computers to new application
areas and the formation of industrial enterprises to commer-
cialize them. For a variety of reasons, analog computing de-
vices emerged from military projects more ready for immedi-
ate general application than did digital computers, and in the
late 1940s a number of companies were formed to market
products specifically designed for the solution of the systems
of nonlinear ordinary differential equations characterizing dy-
namic systems. These computers were termed electronic dif-
ferential analyzers (EDAs), and they became so widely used
in the 1950s that the term analog computer became largely
synonymous with EDA.
As digital computers evolved during the same period, they
gradually began to be used in competition with analog com-
puters. Until well into the 1970s, however, digital computers
tended to be less cost effective than analog computers in the
specialized simulation application, and they were too slow to
permit real-time operation. EDAs had their heydays in the
1970s as free-standing simulators or in concert with digital
computers in hybrid computer systems. Companies such as
Electronic Associates, Inc., Comcor, Inc., Applied Dynamics,
Inc., and a number of others in the United States, Germany,
and Japan grew to large size and maintained an important
position in the military and industrial marketplace. In the
meantime companies such as IBM, Control Data Corporation,
Digital Equipment Corporation, and many others developed
more and more powerful simulation hardware and software.
By the end of the 1970s, the balance began to shift in favor
of digital simulation, and gradually the market for EDAs
evaporated. It disappeared almost completely in the 1990s.
By then, all the tasks formerly performed by electronic analog
computers in the simulation of dynamic systems were han-
dled more effectively by digital computing systems. In other
application areas, however, analog devices thrived as special-
purpose components embedded in a wide variety of systems.
The requirements for these analog devices in communication
and control systems and in a myriad of military, industrial,
and commercial projects has grown almost continuously, and
many prosperous companies throughout the world specialize
in their manufacture.
In this article, the evolution analog computing devices is
first briefly reviewed, including a discussion of the electrical
network analyzers and mechanical differential analyzers that
were important before World War II. Next, a survey of the
EDAs that became popular during the 1960s and 1970s is pre-
sented. Finally, the rise and eventual decline of hybrid
(analog/digital) computers in the 1980s and early 1990s is
considered. Further details may be found in Refs. 1–5.
ANALOG AND DIGITAL PROCESSING
Modern science and engineering are based upon a quantita-
tive description of the physical universe. A variety of so-called

physical variables is measured, and inferences are drawn
from the results of these measurements. In this connection,
it is necessary first to distinguish between independent and
dependent variables. In most system analyses, time and space
constitute the independent variables. That is, measurements
are distinguished from each other and ordered according to
the location in the time–space continuum at which the mea-
surements were made. The measured quantities are the de-
pendent variables, and they may be expressed as functions of
time and/or space. Some familiar dependent variables include
voltage, displacement, velocity, pressure, temperature, stress,
and force. The measurement of these variables requires the
selection of appropriate instruments, along with a decision as
to the manner in which the measurements are to be recorded
and utilized. There are two major ways in which a dependent
variable is treated by instrumentation and data processing
systems: analog and digital. These are defined as follows:
1. A dependent variable is said to be an analog variable if
it can assume any value between two limits.
2. A dependent variable is said to be a digital variable if
its magnitude is limited or restricted to certain specified
values or levels.
It should be recognized that this distinction does not apply to
the domains of the independent variables. Thus analog com-
puters or simulators may maintain the time and the space
variables in continuous form, or they may restrict their atten-
tion to discretely spaced points in the time and space do-
mains.
The decision as to whether to process data in analog or
digital form has far-reaching consequences on the organiza-
tion of the computer system and its cost, upon the accuracy
of the computations, and upon their speed. In order to place
the discussion of analog signal processing in its proper per-
spective, these considerations are briefly summarized.
A basic distinction between analog and digital data pro-
cessing is that digital computations are usually performed se-
quentially or serially, while analog computations are per-
formed simultaneously or in parallel. Digital data processing
generally requires reference to data and programmed instruc-
tions stored in a memory unit. For technical reasons, there
exists a bottleneck at the entrance to this memory, so that
only one item (or a very small number of items) of information
can be read into or read out of the memory at any particular
instant of time. Therefore, only one arithmetic operation can
be performed at a time. This implies that data processing con-
sists of a sequence of arithmetic operations. For example, if
10 numbers are to be added, 10 successive additions are per-
formed. No additional equipment is needed if 100 additions
are required instead.
By contrast, an analog processor generally does not require
a memory, which must be time-shared among the various
mathematical operations. Rather, a separate electronic unit
or ‘‘black box’’ is supplied for each mathematical operation. If
a computation requires 10 additions, 10 analog operational
units must be provided and interconnected; and all of these
units operate simultaneously. If the number of required addi-
tions is increased to 100, the amount of electronic equipment
necessary is multiplied by a factor of 10. The hardware struc-
ture and the cost of an analog data processing system is
therefore determined by the types and numbers of specific
ANALOG COMPUTERS 451
mathematical operations which are to be performed. The
structure of a digital processing system, on the other hand,
includes standardized memory, control, and arithmetic units
and is more or less independent of the types of computations
that are to be performed.
The accuracy of a computation performed by a digital pro-
cessor is determined by the number of bits employed to repre-
sent data. For example, if two numbers are to be multiplied
in a digital processing system in which numbers are repre-
sented by 32 binary digits, the result of the multiplication
must be rounded up or down to the nearest least significant
bit. There is, therefore, a chance of a roundoff error corre-
sponding to one-half of the least significant bit. In an analog
processor, data are not discretized, and roundoff errors are
therefore not incurred. Instead, the accuracy is limited and
error is introduced by the nonideal functioning of the opera-
tional units used to carry out the computations—that is, by
the quality of its components. If two variables are to be added
electrically, they are each applied as continuous voltages to
an adder unit. The output voltage of the adder then corre-
sponds to the sum of the two variables. The accuracy of this
addition operation is limited by the quality (tolerance) of the
electronic components making up the adder and by the preci-
sion with which the output voltage can be measured and re-
corded. In the performance of linear mathematical operations
(such as addition, subtraction, and multiplication by a con-
stant), relative errors are usually larger than 0.01% of full
scale; in the case of nonlinear operations, the best available
electronic units are subject to relative errors of 0.1%.
The speed with which a sequential digital computation can
be performed is determined by the complexity of the computa-
tions. The larger the number of arithmetic operations that
must be performed, the longer the time required. One hun-
dred additions require nearly 10 times as much computing
time as 10 additions. By contrast, in analog data processing,
the time required for computations is independent of problem
complexity. One hundred additions require precisely the same
time as 10 additions; approximately 10 times as much hard-
ware is required, however. The speed with which a mathe-
matical operation can be performed using an analog unit is
determined by the characteristics of its electronic components
as well as by the characteristics of the measuring or output
devices.
In most modern systems utilizing analog processing, only
the operational units actually required for the specific task at
hand are provided. These are interconnected in a permanent
or semipermanent fashion for a specific application. By con-
trast, the so-called general-purpose analog computers or
EDAs, which have by now almost completely disappeared,
were fashioned by assembling a variety of operational units
and permitting the user sufficient flexibility to interconnect
them as required for the solution of differential equations.
Since the analog methods described in this article were ap-
plied almost exclusively to the implementation of mathemati-
cal models of real-world systems and to the experimentation
with these models, the terms analog computer and analog
simulator gradually became synonymous and are used in this
way in this article.
CLASSIFICATION OF ANALOG METHODS
The various devices and methods comprising the general area
of analog computers and simulators are best classified ac-
452 ANALOG COMPUTERS
cording to their basic principles of operation. The systems
falling into the resulting categories are subdivided, in turn,
according to the type of physical variables which constitute
the continuous data within the computer.
One major class of analog devices depends for its operation
upon the existence of a direct physical analogy between the
analog and the prototype system being simulated. Such an
analogy is recognized by comparing the characteristic equa-
tions describing the dynamic or static behavior of the two sys-
tems. An analogy is said to exist if the governing, characteris-
tic equations are similar in form, term by term. For every
element in the original system, there must be present in the
analog system an element having mathematically similar
properties—that is, an element having a similar excitation/
response relationship. Furthermore, the analog elements
must be joined or interconnected in a similar fashion. Mem-
bers of this category of analog devices are termed direct ana-
logs. Direct analogs may be of either the continuous (distrib-
uted) or the discrete variety.
Continuous direct analog simulators make use of distrib-
uted elements such as sheets or solids, made of an electrically
conductive material, so that every spatial point in the analog
corresponds to a specific point in the system being simulated.
The conductive sheets and electrolytic tanks described below
fall into that category. Stretched membrane models, in which
soap films or thin rubbers sheets are supported by a mechani-
cal framework, were also used for a time to simulated fields
governed by Laplace’s and Poisson’s equations. Hydrody-
namic models, termed fluid mappers, as well as direct analog
simulators utilizing thermal fields, electrochemical diffusion
phenomena, polarized light, and electrostatic fields, have also
been successfully used for that purpose.
Discrete direct analog simulators employ lumped physical
elements, such as electrical resistors and capacitors, in which
case the behavior of the system being simulated is obtained
only for the points in the system that correspond to the junc-
tions in the electrical circuit. Networks of electrical resistors,
resistance–capacitance networks, and inductance–capaci-
tance networks have all been widely used to simulate fields
governed by elliptic, parabolic, hyperbolic, and biharmonic
partial differential equations.
The other major class of analog simulation systems in-
cludes mathematical rather than physical analogs. The be-
havior of the system under study is first characterized by a
Direct
Electrical
Conductive paper
Eletrolytic tank
Resistance network
R-C network
Figure 1. Classification of analog simula- L-C network
tion methods and analog computers. L-C transformer network
set of algebraic or differential equations. An assemblage of
analog computing units or elements, each capable of per-
forming some specific mathematical operation, such as addi-
tion, multiplication or integration, is provided, and these
units are interconnected so as to generate numerical solutions
of the problem. Such computing systems are termed indirect
analog computers. Prior to World War II, powerful indirect
analogs for the solution of differential equations were fash-
ioned from mechanical components and termed mechanical
differential analyzers. Electronic differential analyzers were
introduced after World War II and became very important
tools in the design of aerospace systems, control systems, and
chemical process controllers in the United States, western
Europe, Japan, and the Soviet Union.
An important distinction between direct and indirect ana-
logs involves the significance of the physical variables within
the computer. In a direct analog, an analog variable has the
same significance everywhere within the analog system. For
example, in the electrical analog simulation of a mechanical
system, voltage everywhere in the analog may represent ve-
locity. The time derivative of the analog voltage would then
represent acceleration. In an indirect analog, on the other
hand, a transient voltage at some junction in the analog may
represent acceleration; this voltage is then applied to an inte-
grator unit, and the transient voltage at the output of the
integrator would represent velocity.
The general classification of analog methods is illustrated
diagrammatically in Fig. 1. It should be emphasized that con-
tinuous and discrete direct analog simulators played a very
significant role before World War II. By 1980 they had all
been virtually completely eclipsed by digital simulation meth-
ods. Indirect analog computers enjoyed wide use in the 1960s,
1970s, and 1980s; but by the early 1990s, they too had largely
been replaced by digital computers.
DIRECT ANALOG SIMULATORS
Examples of Continuous Direct Analog Simulators
One of the fundamental equations characterizing distributed
parameter systems in a wide variety of areas of physics is
Laplace’s equation,
∇ 2φ = 0 (1)
Analog computer and simulators
Indirect
Mechanical Electronic Mechanical
One-Shot Repetitive
Stretched membrane EAI-PACE Philbric Mechanical
Mass–spring system Comcor GPS differential
Fluid mapper Applied Dynamics analyzer
Beckman EASE
etc.
 ANALOG COMPUTERS 453

and Poisson’s equation

∇2φ = K (2)
Conductive sheet Direct-current
Equation (1) arises, for example, in the study of the steady- oscillograph
state temperature distribution in a flat plate, subject to heat
Probe
sources or sinks at its boundaries. Let’s apply a direct analog
simulation method to such a problem:
Silver
1. A sheet made of an electrically conductive material hav- electrode Silver
electrode
ing the same geometrical shape as the field under study (a)
is fashioned in the laboratory.
2. The boundary conditions of the original field are simu-
lated in the analog system by appropriate voltage and
Potentiometer P
current sources. For example, if one boundary of the
sheet is specified to have a temperature of 100⬚C, and
another boundary a temperature of 0⬚C, voltage sources
100 V and 0 V in magnitude might be applied to the
Microammeter M
corresponding locations in the analog.
3. By means of suitable sensing equipment, such as a volt-
meter or an oscilloscope, lines of equal voltage in the
conductive medium are detected and recorded.
4. The voltage distribution measured in the analog then
Probe Silver
constitutes the solution to the problem. Silver electrode
electrode
Over the years, the suitability of many different conductive Teledeltos
materials was investigated so as to devise practical analog (b)
simulators. One technique widely used in the 1960s and Figure 2. (a) Simple conductive sheet analog simulator for modeling
1970s involved the utilization of Teledeltos Paper developed fields governed by Laplace’s equation in two dimensions. (b) Potenti-
and marketed by the Western Union Telegraph Company as ometer plotting arrangement for drawing equipotential lines directly
a recording medium for telegrams and graphic chart instru- on the conductive paper.
ments. This paper is formed by adding carbon black, a con-
ductive material, to paper pulp in the pulp-beating stage of
the paper-manufacturing process. This results in a high-qual- 3. Alternating-current (ac) voltage sources of appropriate
ity paper with a fairly uniform dispersion of carbon. Because magnitudes are applied to all equipotential boundaries.
of its wide use, the paper was quite inexpensive and well- 4. The voltage distribution along the surface of the electro-
suited for ‘‘rough and dirty’’ simulation applications. A typical lyte is measured and recorded. Lines of constant voltage
setup of this type is shown in Fig. 2(a). At times, lines of equal within the analog then correspond directly to the equi-
potential were drawn directly on the conductive paper, using potential lines of the system being simulated.
a ball point pen, as illustrated in Fig. 2(b). In that case, the
potentiometer is set to the voltage corresponding to the equi- If a field governed by Laplace’s equation in three dimensions
potential line to be sketched, and the probe is moved over the was to be simulated, the sensing probe could be extended into
paper in such a manner that the deflection of the microameter
remains zero. When a complete equipotential line has been
drawn, the potentiometer is set to a different voltage, and the
process is repeated until the equipotential lines of the entire
field have been plotted. Power supply
For greater accuracy, an electrically conductive liquid was
used in place of the resistance paper. Such so-called electro-
lytic tank analog simulators, shown in Fig. 3, were employed
to simulate fields governed by Laplace’s equation and were
used as follows:
Null
indicator
1. A large container (the tank), open at the top is filled Probe Plotter
with a suitable weak saline solution (the electrolyte).
2. A scale model of the boundary configuration of the two- Potentiometer Electrolyte
dimensional field under study, or a conformal transfor- Tank
mation thereof, is immersed in the container. Bound-
Electrodes
aries which are equipotential surfaces are made of
metal, while streamline boundaries are fashioned from Figure 3. Typical conductive liquid analog simulation system (elec-
an insulating material. trolytic tank) for modeling fields governed by Laplace’s equation.
454 ANALOG COMPUTERS

3 3
5
R3 R5 R3

R2 R1 R2 R1 R2 R1
2 0 1 2 0 1 2 0 1

Figure 4. Typical nodes of resistance– R6

capacitance networks used to simulated C0 C0
C0 R4 R4
fields governed by the heat-transfer or dif- 6
fusion equations. Networks may contain
thousands of such node elements. (a) One 4 4
dimension, (b) two dimensions, (c) three
space dimensions. (a) (b) (c)

the liquid and a three-dimensional record of the potential dis-
tribution within the tank obtained. Great care was taken to
achieve highly accurate modeling and sensing devices, so that
relative solution errors could be kept below 0.01%. Through-
out the first half of the twentieth century and until the advent
of digital simulators in the 1980s, electrolytic tanks remained
the premier method for the accurate mapping of potential
fields (see Ref. 1).
Examples of Discrete Direct Analog Simulators
Electrical network simulators are based on finite difference or
finite element approximations of one-, two-, or three-dimen-
sional partial differential equations. By far the most widely
used discrete direct analog simulators were the resistance/
capacitance networks for the simulation of fields governed by
the diffusion equation,
Other network simulators for the simulation of fields char-
acterized by partial differential equations included one-, two-,
and three-dimensional networks of resistors. These served to
model fields governed by elliptic partial differential equations
such as Eqs. (1) and (2). Networks of inductors and capacitors
were occasionally used to simulate fields governed by the
wave equation, particularly in the design of electromagnetic
systems such as waveguides and cavity resonators.
One very sophisticated and elaborate network computer
was designed at Caltech and by Computer Engineering Asso-
ciates for the simulation elastic beam problems governed by
the biharmonic partial differential equations,
∇4φ = 0 (5a)
∂ 2φ
∇4φ = k 2 (5b)
∂t

∂φ In addition to inductors and capacitors, this simulator in-

∇2φ = k (3)
∂t cluded high-quality transformers in every network node ele-
ment. Figure 5 illustrates the simulation of the vibration of a
in one, two, and three Cartesian coordinates. In this ap- cantilever beam using this approach. Similar networks were
proach, the derivatives with respect to the space variables are used to simulate the deflection of two-dimensional systems
replaced by finite differences, while the time variable is kept such as elastic plates. Another network analyzer including re-
in continuous form, as sistors, reactors and transformers was marketed by General
Electric and used for the simulation of electric power distribu-
φ1 − φ0 φ −φ ∂φ
+ 2 20 ∼ =k 0 (4a) tion networks. More details are provided in Ref. 1.

x2
x ∂t
φ1 − φ0 φ2 − φ0 φ3 − φ0 φ4 − φ0 ∼ ∂φ0
+ + + =k (4b)

x2
x2
y2
y2 ∂t INDIRECT ANALOG SIMULATORS
φ1 − φ0 φ2 − φ0 φ3 − φ0 φ4 − φ0
+ + + Mechanical Differential Analyzers

x2
x2
y2
y2
φ −φ φ −φ ∂φ The possibility of obtaining computer solutions of ordinary
+ 5 20 + 6 20 ∼ =k 0 (4c)

z
z ∂t differential equations by successive mechanical integrations
was first suggested by Lord Kelvin in 1876. No successful
Electrical networks are then fashioned from resistors and ca- machines using this method appear to have been con-
pacitors, with typical nodes as shown in Fig. 4, where the structed until researchers at MIT, under the leadership of
magnitudes of the circuit elements are determined by the lo- Vannevar Bush, constructed a series of these computers,
cal magnitudes of the parameters in the field being simulated. termed mechanical differential analyzers, in the 1930s. In
Networks of this type proved extremely useful in the study of the 1940s, General Electric marketed several such analog
transient heat transfer (so-called thermal analyzers) and of machines, and others were subsequently constructed and
the flow of fluids in porous media as in aquifers and oil reser- installed at a number of locations in Western Europe and
voirs. In a number of instances, such networks contained in the Soviet Union.
many thousands of node elements, as well as sophisticated In mechanical differential analyzers, all dependent prob-
electronic circuitry for the application of boundary and ini- lem variables are represented by the rotations of as many as
tial conditions. 100 parallel shafts, rather than by voltages as in electronic
;; S1
2
0
∆x
1

2
∆x
2

2
∆x

(a)
3
∆x

m1∆ x S1 1 m2∆ x S2 1 m3∆ x S3 1 m4∆ x S4 1

2
4

2
1
∆x

2 m5 ∆ x
5

S5
z
x
ANALOG COMPUTERS

z
455

M0 M1 M2 M3 M4 M5
x+ y
z=
2
(EI)0 (EI)1 (EI)2 (EI)3 (EI)4
∆x ∆x ∆x ∆x ∆x (a)

(b)
Input

10n
9n
8n
7n
6n
5n
4n
3n
Figure 5. Network for the simulation of the vibrations of an elastic
cantilever beam, governed by the biharmonic equation, which is
fourth-order in x and second order in time. (a) Schematic of the beam
including five finite difference or finite element sections. (b) Network
containing inductors, capacitors and a transformer at each node. (See
Refs. 1 and 2.)

4m
Splined coutershaft

10n
differential analyzers. These shafts are interconnected and
driven by mechanical units that accept one or more shaft ro-
tations as inputs, and they drive another shaft the rotation of
Output
which provides the output corresponding to the desired func-

12m
4m
6m
tional input–output relationship.
The addition of two dependent variables, x and y, is accom-
plished with the aid of differential gears, as shown in Fig.
6(a). Multiplication by a constant is readily achieved by cou-
pling two shafts by gears. By selecting appropriate gear ra-
(b)
tios, one turn of one shaft can be translated into a desired
multiple or fraction of a turn of the second shaft. This is illus-
trated in Fig. 6(b).
Integration of a dependent variable with respect to another
dependent variable or with respect to an independent vari- z
a
able can be carried out using a disk-and-wheel integrator as
shown schematically in Fig. 6(c). The turns of the disk, called
y
the turntable, represents the differential variable x to a suit-
able scale factor. The distance of the wheel centerplane from
the axis of the turntable represents the integrand, y, again to
some suitable scale factor. These are the two inputs to the x
integrator. The turns of the integrating wheel represent the
value z of the integral to a scale factor determined by the two
input scale factors and the actual structural details of the (b)
unit. This is the output of the integrator.
A rotation of the disk through an infinitesimal fraction of Figure 6. Mechanical computing elements employed in mechanical
differential analyzers. (a) Differential gear for producing a shaft rota-
a turn, dx, causes the wheel to turn through a correspond-
tion z which is proportional to the sum of rotations x and y. (b) Multi-
ingly small part of a turn, dz. For a wheel of radius a, we
plication of the rotation of a shaft using step-up or step-down gear
obtain ratios. (c) Disk-wheel integrator for generating the integral z of wheel
displacements y with respect to wheel displacement x of the disk.
1
dz = y dx (6)
a
456 ANALOG COMPUTERS

D
Motor
;;C

B
A

Figure 7. Polarized-light servomecha- Amplifier

nism for torque amplification in a wheel–
disk integrator.

During a finite time interval, the x turntable will turn taken into account by providing suitable initial settings of the
through a finite number of revolutions, and the distance y two integrator wheels. Note that this equation would be much
will vary, ranging through positive (on one side of center) to more difficult to implement using an electronic analog com-
negative (on the other side of center) values as called for by puter, since electronic integrators are limited to integrating
the problem. The total number of turns registered by the inte- with respect to time.
grating wheel will then be To illustrate the application of the mechanical differential
 analyzer, consider first the almost-trivially simple problem of
x
1 finding the area under a curve. Specifically, a curve y ⫽ f(x)
z= y dx (7)
a x0 is shown plotted on a sheet of paper fastened to an input ta-
ble I in Fig. 9(a). The curve starts at some value, x1, of the
Adequate operation of the integrator requires that the wheel independent variable x and ends at some other value x2. The
roll with negligible slip, even as the rotation z is transmitted curve
mechanically to other shafts. This calls for torque amplifica-  x1
tion, and a variety of ingenious mechanism were introduced z= y dx (9)
for that purpose. The polarized light servomechanism for x1
torque amplification is shown schematically in Fig. 7. The in-
tegrating wheel, A, consists of a polarizing disk with a steel is to be plotted on the output table O. The differential equa-
rim and a steel hub. The direction of optical polarization is tion corresponding to Eq. (9) is
shown by the direction of the crosshatch lines on the wheel.
The follow-up system consists of a pair of similar polarizing dz
=y (10)
disks B and C on the motor-driven output shaft D. The two dx
disks are mounted with their planes of polarization at right
angles to each other. Two beams of light pass through polar- where y is given as a plotted function of x. The mechanical
izer A and are polarized in the same direction. One light beam differential analyzer system for generating this solution is
passes through polarizer B, while the other passes through shown in detail in Fig. 9(a) and schematically in Fig. 9(b).
polarizer C. The light beams are picked off by separate pho- The variable y displaces the integrating wheel when the hand
totubes, which are connected through an amplifier to a split-
field series motor. Any difference in light intensity striking
the two phototubes will cause the motor to turn. This will
cause the output shaft D to assume an orientation with re- z = xy
spect to wheel A so that the plane of polarization of wheel A
bisects the right angle between the two planes of polarization
of disks B and C. The output shaft D is thus constrained to +
y
follow the motions of the integrating wheel, with only the
light beams as the coupling medium between them. x
Note that the shafts representing the variables x and y can
be driven by the outputs of other integrators or by a separate
motor. For example, the turntable can be driven by a motor
at constant speed. In that case, integration with respect to
time is achieved. Multiplication of two dependent variables x
and y can be effected by connecting two integrators as shown
in Fig. 8, resulting in an output:
  y dx x dx
xy = x dy + y dx (8)
Figure 8. Schematic diagram showing the multiplication of two de-
In Fig. 8, conventional symbols are used to represent the inte- pendent variables x and y by implementing the formula for integra-
grators, adder, and shafts. The initial values of the product is tion by parts, Eq. (8).
 ;; ;;
ANALOG COMPUTERS 457

I O

y z
P

; ;
;;;;;;;;;
x1 x2 x x

Motor

;; C

;;
W
D

(a)

x x

z z

Figure 9. Mechanical differential ana-

lyzer method for generating the area un-
der a specified curve. (a) Detailed figure,
(b) (b) schematic diagram.

crank on the input table is turned manually to keep a peep- curve z ⫽ f(x), as a nut on the horizontal lead screw traverses
hole on the given curve, while the x lead screw shifts the the x range.
peephole horizontally via the independent variable motor Consider now a simple second-order differential equation
drive. The motor also turns the integrator disk D. The inte- of the form
grator wheel W operates through a torque-amplifying cou-
pling C to drive the vertical lead screw on the output table d2y dy
M +b + ky = 0 (11)
O. A nut on this lead screw carries a pen P which traces the dx2 dx
458 ANALOG COMPUTERS

where M, b, and k are specified constants, and initial values ferential analyzers became available in installations ranging
of y and dy/dx are also given. The solution process is from a modest 10 operational amplifiers to well over 2000 op-

d2y

b dy k
 erational amplifiers. The accuracies of these computers in
solving nonlinear equations ranged from 2% of full scale for
=− + y (12a)
dx2 M dx M relatively low-cost devices to better than 앑0.1% for the most
 x elegant models.
dy d2y ◦
= dx + y(0) (12b) Very early in the development of electronic analog comput-
dx 0 dx2
 x ers, it became apparent that there exist two distinct philoso-
dy
y= dx + y(0) (12c) phies or approaches to the application of these devices. In one
0 dx class of analog computers, the time necessary to obtain a solu-
tion varies from approximately 10 s to several minutes. The
Assume that it is desired to plot y and dy/dx as functions of
initial conditions and driving functions are applied at an in-
x and that dy/dx is also required as a function of y and also
stant of time corresponding to t ⫽ 0, and continuous graphical
as a function of the second derivative of y with respect to x.
outputs are generated from selected points in the computer
The mechanical differential analyzer implementation is
system. This type of EDA is termed a long-time or one-shot
shown schematically in Fig. 10. All variable shafts are shown
analog computer. The other class of differential analyzers op-
as horizontal lines. Adders and the gear trains interconnect-
erates on a greatly speeded-up time scale, so that solutions of
ing the various shafts are shown at one end. Connections
problems are obtained in several milliseconds. In that case,
from the various shafts are carried over to the integrators and
the problem run is repeated automatically several times per
output tables by cross shafts. In a similar manner, systems of
second, and the result of the computation is displayed on a
simultaneous nonlinear differential equations with variable
cathode-ray oscilloscope. Members of this second class are
coefficients can be solved.
termed repetitive or high-speed analog computers. While both
Major mechanical differential analyzer facilities included
approaches had their enthusiastic adherents, the long-time
20 or more integrators and a substantial number of input and
computer assumed a preponderant position by a wide margin,
output tables. Using high-precision mechanical components,
in terms of both (a) the number of companies engaged in its
they were capable of solving complex engineering problems to
production and (b) the number of computers actually in use.
a higher accuracy than were the electronic differential ana-
Almost all commercial ‘‘long-time’’ installations are de-
lyzers that eventually replaced them. At the time they were,
signed around a centrally located patch-bay housed in a con-
however, very costly to construct and to maintain, and they
trol console. Wires leading to the inputs and outputs of all
occupied an inordinate amount of space. Additional details
computer units and components are brought out to an array
are discussed in Ref. 2.
of several hundred or even thousands of patch-tips. Remov-
able problem boards, made of an insulating material, are ma-
Electronic Differential Analyzers (EDAs)
chined to fit precisely over these tips in such a manner that
Electronic analog computers were first developed for military a clearly identified hole in the problem board lies directly over
applications during World War II. Subsequently, numerous each patch-tip. Most of the programming and connecting of
manufacturers entered into competition to provide progres- the computer can then be accomplished by means of patch-
sively larger, more accurate, and more flexible general-pur- cords interconnecting the various holes in the problem board.
pose computers. The design of the electronic computer units Usually a considerable number of problem boards are avail-
and the programming of EDAs is considered in detail in other able with each computer. Problems can be programmed on
articles in this encyclopedia. General-purpose electronic dif- these boards, which can be stored for subsequent experimen-

x y
y d 2y
dy/dx dy/dx dx2

k dy/dx
– y
M d 2y
+
dx2
b dy
–
M dx k
– b
y M –
M
dy/dx
x

Figure 10. Mechanical differential ana-

lyzer schematic for the solution of the sec- dy d 2y
dx dx
ond-order differential equation, Eq. (11). dx dx2

Digital-analog Analog-hold
converters circuits
Demultiplexer
Demultiplexer
Buffer
Timing
and
Digital data control
processor unit
Recorders
Printer,
tape units
Analog-digital
converter
Buffer Multiplexer
(digital-hold)
tal work while the computer is being employed to solve an
entirely different problem. In that manner, the computer in-
stallation is not ‘‘tied-up’’ by a single problem. A considerable
effort has been expended in optimizing the design of problem
boards to facilitate their use. Even so, the programming of
reasonably complex problems results in a veritable maze of
plug-in wires, a factor which not infrequently leads to errors
and makes debugging very difficult. To help alleviate this sit-
uation, most manufacturers introduced color-coded plug-in
connectors and multicolored problem boards, as well as spe-
cial ‘‘problem-check’’ circuitry.
In addition to the patch-bay, the control console generally
includes the principal operating relays or solid-state switches
for resetting initial conditions and for commencing computer
runs, as well as potentiometers and amplifier overload indica-
tors. One set of solid-state switches facilitates the connection
of direct-current (dc) power supplies to the outputs of all inte-
grators for the setting of specified initial conditions. At the
start of the computer run, at t ⫽ 0, all of these switches open
simultaneously, and at the same instant of time, other
switches connect the specified driving functions into the cir-
cuit. To repeat the computer run, the control switch is moved
from the ‘‘compute’’ to the ‘‘reset’’ position, and the identical
initial conditions are again applied. Frequently a control unit
includes a ‘‘hold’’ setting. In this position, all integrator capac-
itors are disconnected from the input resistors, so that they
are forced to maintain whatever charge they possess at the
instant the control switch is turned to the ‘‘hold’’ position. The
voltages at various points in the circuit can then be examined
at leisure.
The rest of the components are mounted in standard racks
in such a manner that the computer facility can readily be
expanded by purchasing and installing additional racks of
equipment. Precision resistors and capacitors are used
throughout; and in the more refined high-accuracy installa-
tions, all resistors and capacitors actually taking part in the
computing operation are kept in a temperature-controlled
ANALOG COMPUTERS 459
Analog
system
Figure 11. Major components of a hybrid
(analog/digital) computer system of the type
widely used in the aerospace industry in the
1970s and 1980s for the design of systems
and for the training of pilots and astronauts.
oven so as to minimize drift errors. All computers have vari-
able dc power supplies for the application of initial conditions
to the integrators and for the generation of excitations. The
output devices are generally mounted separately and may in-
clude direct-writing oscillographs for relatively high-speed re-
cording, servo-driven recorders, and digital voltmeters. In ad-
dition, most analog facilities possess a number of multipliers,
resolvers for the generation of trigonometric functions, arbi-
trary function generators, Gaussian noise generators, and
time-delay units for simulating transport lags. Further de-
tails are presented in Refs. 3 and 5.
Hybrid (Analog/Digital) Computers
When relatively low-cost, on-line digital computers became
available in the late 1960s and 1970s, so-called hybrid com-
puters became popular. Analog and digital computer units
were interconnected, using analog–digital and digital–analog
converters, while a single control unit controlled all comput-
ers comprising the system. In such a hybrid computer, the
computing tasks were divided among the analog and digital
units, taking advantage of the greater speed of the analog
computer and the greater accuracy of the digital computer.
For example, in simulating a space vehicle, the guidance
equations were solved digitally, while the vehicle dynamics
were implemented on the analog computer. Such a hybrid
computer system is shown in Fig. 11. Further details are to
be found in Ref. 4.
Throughout the 1970s and well into the 1980s, hybrid com-
puters played a crucial role in the development of many mili-
tary and civilian aerospace systems, including guided mis-
siles, aircraft and space vehicles, and so on, as well as in
training pilots and astronauts. By 1990, however, the devel-
opment of minicomputers and microprocessors had reached a
level of performance that permitted all tasks formerly as-
signed to the analog computer to be performed digitally at
adequate speed and greatly reduced cost. This effectively
460 ANALOG FILTERS

spelled the end of hybrid computers as a tool for engineering

design and simulation.

BIBLIOGRAPHY

1. W. J. Karplus, Analog Simulation: Solution of Field Problems, New

York: McGraw-Hill, 1958.
2. W. J. Karplus and W. W. Soroka, Analog Methods: Computation
and Simulation, New York: McGraw-Hill, 1959.
3. R. Tomovic and W. J. Karplus, High-Speed Analog Computers, New
York: Wiley, 1962.
4. G. A. Bekey and W. J. Karplus, Hybrid Computation, New York:
Wiley, 1968.
5. A. S. Jackson, Analog Computation, New York: McGraw-Hill,
1960.

WALTER J. KARPLUS
University of California at Los
Angeles
494 ANALOG PROCESSING CIRCUITS

−
+
+
V− +
+ Vout
V+
− − −

Figure 1. General analog signal processing circuit.

In recent years, the trend to smaller and cheaper electronic

systems has resulted in mixed-mode integrated systems
where both digital and analog signal processing circuits are
manufactured in the same chip (3).
Analog signal processing circuits can be divided in two cat-
egories: linear and nonlinear circuits. Among linear circuits
for signal processing are filters (4) which use amplifiers,
adders, and integrators. High-frequency signal processing is
an area where analog circuits are the main signal processors.
For nonlinear analog signal processing, the most impor-
tant circuits are data converters, where comparators are
widely used, as well as adders and integrators. Instrumenta-
tion and control (5) are also areas that use analog signal pro-
cessing circuits intensively, for example, to measure ac sig-
nals or to control positioning motors.
This article is divided into two parts. The first part covers
linear circuits, such as adders and integrators, and circuits
that use them, such as filters. The second part covers nonlin-
ear circuits, such as comparators, limiters, log and antilog
amplifiers, and their applications. Because most analog signal
processing circuits use operational amplifiers, a brief section
on op-amps is included.

OPERATIONAL AMPLIFIERS

An operational amplifier (op-amp), shown in Fig. 1, is a three-

terminal device that has a high-input impedance Zin, a low
output impedance Zo, and a very high gain A (6). For an ideal
op-amp, these quantities are

Zin → ∞
Zo = 0 (1)
A→∞

The op-amp input–output relationship is given by

Vout = A(V+ − V− ) (2)

The input terminal with a plus sign is called the noninverting

input, and the input terminal with a minus sign is called the
ANALOG PROCESSING CIRCUITS inverting input.

Analog signal processing is still the primary mode of signal

processing in many applications, despite the tremendous de-
velopment in digital signal processing circuitry. For example, + +
at high frequencies signal processing is implemented with
very simple analog circuits. Very low-power applications are +
V− A(V+ − V−) Vout
+ −
also realized with analog circuitry. In addition, even in sys-
V+
tems using digital signal processing, it is necessary to include − − −
some form of analog signal processing and data conversion as
an interface for analog systems (1,2). Figure 2. Operational amplifier characteristics.

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.
 ANALOG PROCESSING CIRCUITS 495

Iout
IF RF
Rin
+
−
+
V− gm(V+ − V−) Iin
+ Vin +
+ Vout
V+
− − − −

Figure 3. Operational amplifier macromodel.

(a)

The op-amp variables are shown in Fig. 1. In addition to

Eqs. (1) and (2), the very high input impedance forces
RF
Vin K=– Vout
I+ = I− = 0 (3) Rin

A macromodel for an ideal op-amp, where A 씮 앝, is given in (b)

Fig. 2. Note that Zo ⫽ 0, and Zin 씮 앝. Furthermore, because
Vout is finite when A 씮 앝, (V⫹ ⫺ V⫺) must be very small. That Figure 5. Inverting amplifier. (a) Circuit; (b) block, diagram.
is,

V+ = V− (4) current law

Iin + IF = 0 (7)
Another type of op-amp that has the macromodel shown in
Fig. 3, also has a high input impedance, but it has as the In addition, because V⫺ ⫽ 0 due to the infinite op-amp gain,
output variable an output current given by (6)
Vin
Iin = (8)
Iout = gm (V+ − V− ) (5) Rin

and
Note that now the output impedance is infinite because the
output element is a current source. The value of the transcon- Vout
iF = (9)
ductance gm is a function of the bias current Ibias. Thus, RF

gm = gm (Ibias ) (6) Thus,

Vin V
+ out = 0 (10)
Because the gain factor for this op-amp is the transconduc- Rin RF
tance gm, this op-amp is called an operational trasconductance
amplifier (OTA). The symbol for an OTA is shown in Fig. 4. which can be rewritten as
Usually, the OTA has a higher operating frequency than the RF
conventional voltage mode op-amp and thus, it is usually Vout = − V (11)
Rin in
found in high-frequency circuits.
Thus, the output voltage is given by the product of the input
voltage and the inverting amplifier gain ⫺RF /Rin. Figure 5(b)
LINEAR CIRCUITS FOR SIGNAL PROCESSING shows a block diagram for the inverting amplifier. An in-
verting unity gain amplifier is obtained by making Rin ⫽
The simplest circuit in linear signal processing is the in- RF ⫽ R as shown in Fig. 6. Now let us consider the circuit
verting amplifier (2) shown in Fig. 5(a). Because no current
flows into the inverting input of the op-amp, by Kirchhoff ’s

IF Rin
Rin
−
+
− Iout Iin
+ Vin +
+ Vout
+ − −
V− + Ibias
V+
− −

Figure 4. OTA macromodel. Figure 6. Inverting adder. (a) Circuit; (b) block diagram.
496 ANALOG PROCESSING CIRCUITS

RF
K1 = –
R1
V1

R1 RF
K2 = –
V1 R2
R2 RF V2
V2
RF
R3 K3 = –
R3
V3 − V3 Σ Vo
Vo
+
Rn
Vn Vn
RF
Figure 7. Two input inverting adder. (a) Kn = –
(a) Rn (b)
Circuit; (b) block diagram.

shown in Fig. 7 (8). The currents ik are Thus, we have obtained an inverting adder. Each input is am-
plified by the factor ⫺RF /Ri. A block diagram for the inverting
V1 adder is shown in Fig. 7(b).
I1 = (12a)
R1
V EXAMPLE 1. Figure 8(a) shows a two-input inverting adder.
I2 = 2 (12b)
R2 The output voltage is given by
..
. 10 k 10 k
Vo = − V − V (17)
and 5 k 1 1 k 2

Vo Thus,
IF = (13)
RF
Vo = −2V1 − 10V2 (18)
Furthermore, because no current flows into the inverting in-
put, by Kirchhoff ’s current law A block diagram is shown in Fig. 8(b).

I1 + I2 + · · · + In + IF = 0 (14)
A more general inverting adder (2) is shown in Fig. 9.
Thus, Here each impedance Zi is given by the T-circuit in Fig.
10. The input short circuit impedances at nodes 1 and 2
V1 V Vn Vo are given by
+ 2 + ··· + + =0 (15)
R1 R2 Rn RF  
V1 (s)  V2 (s) 
Zsc (s) = =
Solving for Vo, I2 (s) V I1 (s) V
2 (s)=0 1 (s)=0
(19)
R R R Z (s)Z2 (s) + Z2 (s)Z3 (s) + Z1 (s)Z3 (s)
Vo = − F V1 − F V2 − · · · − F Vn (16) = 1
R1 R2 Rn Z2 (s)

5 kΩ 10 kΩ −2
V1 V1
1 kΩ
V2 −
Vo
Σ Vo

−10
+ V2

Figure 8. General inverting adder. (a) (b)

 ANALOG PROCESSING CIRCUITS 497

Zo(s) 10 kΩ 10 kΩ

V1(s) Z1(s) R2 = ?

− V1 10 kΩ
−
Vo(s) Vo = −100 V1
+
V2(s) Z2(s) +

Vn(s) Zn(s)
Figure 11. Noninverting amplifier.

Figure 9. Tee network. and

Vo − V1
I2 = (23)
R2

As with the inverting adder, Kirchhoff ’s current law at node Using Kirchhoff ’s current law at the inverting input node,
Vg gives
I2 = I1 (24)
V1 (s) V2 (s) Vn (s) Vo (s)
+ + ··· + + =0 (20)
Z1 (s) Z2 (s) Zn (s) Zo (s) Thus,

Solving for Vo, Vo − V1 V

= 1 (25)
R2 R1
Zo (s) Zo (s) Zo (s)
Vo (s) = − V1 (s) − V2 (s) − · · · − V (s) (21)
Z1 (s) Z2 (s) Zn (s) N Solving for Vo,

R1 + R2
EXAMPLE 2. We want the circuit shown in Fig. 11 to have Vo = V1
an inverting gain of 100. By solving Eq. (19) with R1 ⫽ R3 ⫽
R1 R  (26)
10 k⍀, R2 ⫽ 102.04 ⍀.
= 1 + 2 V1
R1
A noninverting amplifier is shown in Fig. 12. Because the
op-amp forces the inverting input voltage to be equal to the We readily see that the amplification factor for the nonin-
noninverting input voltage, the currents I1 and I2 are given verting amplifier is always greater than unity.
by
EXAMPLE 3. If we desire to design a noninverting amplifier
V with a gain of 3, we can choose R2 ⫽ 2 k⍀ and R1 ⫽ 1 k⍀.
I1 = 1 (22)
R1 Thus,

R2 2 k
1+ =1+ =3 (27)
R1 1 k

I1 I2 The final circuit is shown in Fig. 13.

V1 Z1 Z3 V2

R2

Z2 I2
R1
−
I1 Vo(s)
V1(s) +

Figure 10. Amplifier with a gain of 100. Figure 12. Noninverting amplifier with a gain of three.
498 ANALOG PROCESSING CIRCUITS

2 kΩ

−
1 kΩ
− Vo(s)
V1(s) +
Vo(s)
V1(s) +
Figure 15. Differential amplifier.
Figure 13. General noninverting amplifier.

A general inverting amplifier is shown in Fig. 14. Simi- Thus, we see that the circuit takes the difference of the input
larly to the noninverting amplifier, the output voltage is given voltages. Therefore, this circuit is called a differential ampli-
by fier. By choosing Ro ⫽ R3 and R1 ⫽ R2, we can write Eq. (33)
as


Z (s)
Vo (s) = 1 + 2 V (s) (28) Ro
Z1 (s) 1 Vo = (V − V1 ) (34)
R1 2
As before, the gain is noninverting and greater than unity. If
Z2(s) ⫽ 0 (short circuit), the circuit equation is which gives the input voltage difference amplified by the fac-
tor Ro /R1.
Vo (s) = V1 (s) (29)

that is, we have a unity gain amplifier. Note that Z1(s) has no EXAMPLE 4. It is desired to find an amplifier whose output
effect and can be deleted (an open circuit.) The resulting cir- voltage is given by
cuit, shown in Fig. 15 is also called a voltage follower be-
cause the output voltage follows the input voltage. Now let Vo = 10(V2 − V1 )
us consider the circuit (9) in Fig. 16. Voltage V⫹ is given
by

R3
V+ = V (30)
R2 + R3 2
R1 V− Ro
Using superposition, voltage V⫺ is given by V1

Ro R1
V− = V + V (31) −
Ro + R1 1 Ro + R1 2
Vo
+
Because the op-amp forces both voltages V⫺ and V⫹ to be
equal, R2 R3
V2
R3 Ro R1
V = V + V (32) V+
R2 + R3 2 Ro + R1 1 Ro + R1 2
(a)
Solving for Vo,

R3 (Ro + R1 ) Ro R1 Ro
Vo = V − V (33) V−
R1 (R2 + R3 ) 2 R1 1 V1

−
Vo
+
Z1(s) Z2(s)
R1 R0
V2
−
V+
Vo(s)
V1(s) + (b)

Figure 14. Voltage follower. Figure 16. Differential amplifier with a gain of 10.
 ANALOG PROCESSING CIRCUITS 499

1 kΩ 10 kΩ Defining impedances ZA(s) and ZB(s) by

V1
 
1 1 
m
1 1
= + + (37)
−
ZA (s) ZIS (s) i=1 ZIi (s) Zo (s)
Vo
+ and
 
1 kΩ 10 kΩ 1 1 
n
1
V2 = + (38)
ZB (s) ZNS (s) k=1 ZNk (s)

Figure 17. General inverting and noninverting amplifier. and because for an ideal op-amp,

VA = VB (39)

from Eqs. (35)–(39) we can write

By choosing Ro ⫽ R3 ⫽ 10 k⍀ and R1 ⫽ R2 ⫽ 1 k⍀ in Fig. 16,
we obtain the desired output voltage. The final circuit realiza-
VA Vo (s) m
VIi (s)
tion is shown in Fig. 17. = + (40)
ZA (s) Zo (s) i=1 ZIi (s)
A differential amplifier (2) can be extended to the general
combined inverting and noninverting amplifier shown in Fig. and
18. Kirchhoff ’s current law at nodes A and B gives
VB 
n
VNk (s)

 = (41)
1 1 1 1 ZB (s) k=1 ZNk (s)
VA + + ··· + +
ZIS (s) ZI1 (s) ZIm (s) Zo (s)
Vo (s) m
VIi (s) Finally, from Eqs. (40) and (41) together with Eq. (39), we can
= + (35) write
Zo (s) i=1 ZIi (s)

Vo m
VIi (s) VB
and = + (42)
Zo (s) i=1
Z Ii (s) Z A (s)

  n
1 1 1 VNk (s)
VB + + ··· + = (36) Solving for Vo,
ZNS (s) ZN1 (s) ZNn (s) Z (s)
k=1 Nk
 
ZB (s) n
VNk (s) m
VNi (s)
Vo (s) = Zo (s) − (43)
ZA (s) k=1 ZNk (s) i=1 ZIi (s)

V (s)
– + Im This equation allows us to design combined inverting and
ZIm(s) ZIS(s)
noninverting adders. Each inverting input has a gain
....

....
...

V (s)
– + I2 Zo (s)
ZI2(s)
GIi (s) = − (44)
ZIi (s)
– +VI1(s)
ZI1(s) Zo(s)
and each noninverting input has a gain given by

VA − ZB (s) Zo (s)
GNk (s) = (45)
Vo(s) ZA (s) ZNk (s)
VB +
The values of ZIS(s) and ZNS(s) can be picked such that
–
V (s)
+ N1 ZA(s) ⫽ ZB(s), so that the noninverting gains are given by
ZN1(s)
Zo (s)
V (s) GNk (s) = (46)
– + N2 ZN2(s) ZNk (s)
......
....

....

....

V (s) EXAMPLE 5. Consider the circuit in Fig. 19(a). Suppose we

– + Nn
ZNn(s) ZNS(s)
want

Figure 18. Inverting and noninverting adder. V0 = 2VN1 + 3VN2 − 4VI1 − 2VI2
500 ANALOG PROCESSING CIRCUITS

RIS

RI1 Ro 50 kΩ 100 kΩ
VI1 VI1 +2
VN1
RI2 50 kΩ
VI2 − VI2 − +3
VN2

+
Vo
+
Vo
VI1
−2 Σ Vo

RN1 RNs −2
50 kΩ 20 kΩ VI2
VN1 VN1
RN2 33.3 kΩ
VN2 VN2
(a) (b) (c)

Figure 19. Inverting and noninverting amplifier. (a) Schematic circuit; (b) block diagram.

We start by picking Ro ⫽ 100 k⍀. We set RA ⫽ RB by a proper From Eqs. (37) and (38)
choice of RIS and RNS (usually this can be done by making any
RA = RIS RI1 RI2 R0 = RIS 20 k
one infinite.) From our desired output
RB = RNS RN1 RN2 = RNS 25 k
GN1 = 2
By setting RIS ⫽ 앝,
GN2 = 3
RA = 20 k
GI1 = −2
GI2 = −2 Then, the value that makes RA ⫽ RB is
RNS = 100 k
From Eq. (46) for the noninverting gains
The final circuit is shown in Fig. 19(b), and a block diagram
Ro 100 k is shown in Fig. 19(c).
RN1 = = = 50 k
GN1 2
INTEGRATORS
and
Integrators are basic building blocks in analog signal pro-
Ro 100 k
RN2 = = = 33.3 k cessing (10). For example, state variable filters such as the
GN2 3 KHN (11) and Tow–Thomas (12) filters are based on inte-
grators within a loop. The most popular integrator circuit is
and for the inverting gains the inverting Miller integrator depicted in Fig. 20. For an
ideal op-amp, its transfer function is given by
Ro 100 k Vout 1
RI1 = = = 50 k =− (47)
GI1 2 Vin sRC
and As can be seen, this integrator has its pole at the origin.
Ro 100 k Another widely used integrator circuit is the inverting
RI2 = = = 50 k lossy integrator shown in Fig. 21. Its transfer function is
GI2 2

R2

C C

R R1
Vin − Vin −
Vout Vout
+ +

Figure 20. Miller inverting integrator. Figure 21. Lossy inverting integrator.
 ANALOG PROCESSING CIRCUITS 501

V+ + Vin +
+ +
Vout Vout
+ +
V− − −
+ C C R
− − − − −

Figure 22. OTA based integrator. Figure 24. OTA-based lossy integrator with external resistor.

given by of these dc errors, the integrator output consists of two com-

ponents, namely, the integrator signal term and an error
1 term. Thus, now Vout is given by
Vout R1 C  
=− (48) 1 1
Vin 1 Vout (t) = − Vin (t) dt + Vos (t) dt
s+ RC RC
R2 C  (52)
1
+ ID (t) dt + VDS
From this transfer function we see that a pole is located on C
the negative real axis at
An option for high-frequency applications is using an opera-
1 tional transconductance amplifier (OTA). Because Iout ⫽
s=− (49) gm(V⫹ ⫺ V⫺) in an OTA, by loading the OTA with a capacitor,
R2 C
as shown in Fig. 22, we obtain (13)
Now if we take into account the finite op-amp gain A0, routine
Iout gm (V+ − V− )
circuit analysis gives the inverting Miller integrator transfer Vout = = (53)
function as sC sC

Vout A0 If any one of the input voltages is zero, we obtain either an

=− (50) inverting or a noninverting integrator, as shown in Fig. 23 for
Vin 1 + (1 + A0 )sRC
an inverting integrator. Note that OTA-based integrators are
open loop integrators. We can realize a lossy integrator with
Note that the pole shifts from the origin to a location on the
the circuit in Fig. 24. In this case the transfer function is
negative real axis given by
given by
1 gm
s=− (51)
(1 + A0 )RC Vout C
= (54)
Vin 1
Because A0 is very large, this pole is very close to the origin s+
RC
but on the negative real axis. Thus, the Miller integrator for
very high frequencies behaves like a lossy integrator. We can also realize a lossy integrator by producing a resistor
Other sources of error in the inverting Miller integrator with the OTA, as shown in Fig. 25. In this case the transfer
are the op-amp dc offset voltage and bias current (8). Because function achieved is given by
gm
Vout C
= gm (55)
Vin s+
Vin + C
+
Vout
+
− If we require realizing Eq. 55 with different numerator and
C denominator coefficients, then we can use an additional OTA
− − to produce the resistor, as shown in Fig. 26. The resulting

(a)

Vin −
+
Vout −
+
+ Vout
C +
Vin +
+ C
− −
− −
(b)
Figure 25. OTA-based lossy integrator without external resistor.
Figure 23. (a) Non-inverting integrator. (b) Inverting integrator. The OTA feedback realizes the resistor.
502 ANALOG PROCESSING CIRCUITS

NONLINEAR ANALOG SIGNAL PROCESSING CIRCUITS

−
gm2 The general form of a nonlinear analog signal processing cir-
Vin + Vout
+ + cuit (2) is shown in Fig. 29, where f is a nonlinear function of
gm1 +
C
the current IN. In Fig. 29, the output voltage is given by
−
− − Vout = f (IN ) (57)

Figure 26. OTA-based lossy integrator with different coefficients. Because no current flows into the inverting input of the op-
amp
transfer function is given by IN = −I1 − I2 (58)
gm1 and, because the inverting input voltage is zero due to the
Vout C
= g (56) infinite gain
Vin s + m2
C Vin1
I1 = (59a)
R1
There are some advantages when using OTAs in integrators:
and
1. The operating frequency range is greatly increased.
Vin2
2. The dynamic range is also increased because now we I2 = (59b)
have a current as the output variable for the opera- R2
tional amplifier.
Thus,
3. Modern OTAs require lower supply voltages.
Vin1 Vin2

Vout = f − − (60)
EXAMPLE 6. As an application of integrators, let us consider R1 R2
the circuit shown in Fig. 27. This circuit is known as a state
variable filter, or KHN filter (11), after its inventors. As can
COMPARATORS
be seen, this circuit is formed by two Miller inverting inte-
grators and an inverting and noninverting adder. The trans-
A comparator is a circuit that has the transfer characteristic
fer function is given by
shown in Fig. 30. Here we have a comparison level ER. The

 function of this circuit is to compare the input voltage Vin with
1 + R6 /R5 s
− the reference voltage ER and decide which one is larger. The
VBP (s) 1 + R3 /R4 R1C1
= ideal comparator is described by
V1 (s) s 1 + R6 /R5 R6 /R5
s2 + + 
R1C1 1 + R4 /R3 R1 R2C1C2 
L+ Vin > ER
Vout = 0 Vin = ER (61)
The first op-amp realizes the adder and the last two op-amps 

L− Vin < ER
realize the integrators.
This function is plotted in Fig. 31.
EXAMPLE 7. Another very popular filter realization is the Now let us consider the circuit shown in Fig. 32. The func-
Tow–Thomas filter (12). This filter is shown in Fig. 28(a). It
tion f(•) is realized by a zener diode [see Fig. 33(a)] for which
consists of a lossy integrator followed by a noninverting inte- an ideal description is given by
grator. The noninverting integrator is formed by a Miller in-

verting integrator cascaded with a unity inverting amplifier. Ez IN < 0
An alternative realization of this filter using OTAs is shown f (iN ) = (62)
0 IN > 0
in Fig. 28(b).

R5

C1
R6 C2
− R1
R3 − R2
+ −
+ +
+
V1 VBP
− − +

R4
Figure 27. KHN biquad filter.
 ANALOG PROCESSING CIRCUITS 503

C2 R

C1
Rin RQ R
− R1
+
V1 − R
+ VBP −
−
+
+

(a)

+
gm1 −
− VBP gm2
+
+
V1
− C1 C2

Figure 28. Tow–Thomas biquad filter.

(a) With voltage mode op-amps; (b) with
(b) OTAs.

Vout

R1 I1 IN L+
Vin1 ƒ

0 ER Vin
R2 I2
Vin2 −
L−
Vout = ƒ(In)
+
Figure 31. Transfer characteristic for a comparator.

Figure 29. General nonlinear signal processing circuit. F is a nonlin-

ear function.

R1
Vin Clamp

−
R2 Vout
VREF +

RB
Vin
RA
Vout
ER

Figure 30. Block diagram for a comparator circuit. Figure 32. Comparator circuit.
504 ANALOG PROCESSING CIRCUITS

IN Vout

Forward
IN
biased
+ VREF R1
−
vD EZ R2
− 0 vD
Vin
Reversed
biased −EZ

(a) (b) Figure 35. Transfer characteristic for the comparator from Fig. 32
with the zener diode reversed.
Figure 33. Zener diode. (a) Symbol and variables; (b) I-V character-
istic.

that is, the circuit compares the input voltage Vin with the
reference voltage ⫺VREFR1 /R2. If Vin is either smaller or
as shown in Fig. 33(a). For our circuit, greater than ⫺VREFR1 /R2, then Vout is chosen according to Eq.
(62). Thus the circuit is a comparator. Its transfer character-
Vin istic is shown in Fig. 34. This is equal to the comparator char-
I1 = (63)
R1 acteristic from Fig. 31 with a sign reversal. By reversing the
diode, we get the characteristic shown in Fig. 35. Figure 36
and shows a bipolar comparator using a double-anode zener diode.
Using two zener diodes with different zener voltages we ob-
VREF tain different output voltages.
I2 = (64)
R2 A related circuit is the limiter whose function is shown in
Fig. 37. A limiter is realized by adding resistive feedback to a
The current IN is given by comparator, as shown in Fig. 38(a). The circuit acts as a volt-
age amplifier with gain RF /Rin as long as the output voltage
Vin VREF is between ⫺Ez2 and Ez1. When this condition does not hold,
IN = − − (65)
R1 R2 then the output is clamped either to Ez1 for positive output
voltage or to ⫺Ez2 when the output voltage is negative. Thus,
Thus, the two zener diodes act as a level clamp or feedback limiter

Vin VREF

Vout = f − − (66)
R1 R2

Using Eq. (62) in Eq. (66),

 Vin −
 R1

E z Vin < −VREF Rin Vout
R2 +
Vout = (67)

 R
0 Vin > −VREF 1
R2
(a)

Vout Vout

EZ

0 Vin

VREF R1 Vin
−
R2

(b)

Figure 36. Comparator using double-anode zener diodes. (a) Circuit;

Figure 34. Transfer characteristic for the comparator from Fig. 32. (b) transfer characteristic.
 ANALOG PROCESSING CIRCUITS 505

characteristics. This comparator is called a soft comparator

Vin Vout
Figure 37. Block diagram for a limiter circuit.
whose purpose is to limit output level excursions but other-
wise do not affect the inverting amplifier behavior. This char-
acteristic is shown in Fig. 38(b).
Let us consider the circuit in Fig. 39(a). There are two com-
binations of possible diode states.
1. D1 ON, D2 OFF. If Vin is sufficiently positive, Vout will be
sufficiently negative and eventually e1 reaches 0 V, and
D1 turns on. Node e1 acts as a virtual ground, and the
output voltage is given by [see Fig. 39(c)]
E 1 RB
Vout = −
RA
because there is rounding in the corners and nonzero
slopes.
A hard comparator, where the clamp levels are well con-
trolled, is shown in Fig. 40. The input-output transfer charac-
teristic for the comparator is shown in Fig. 41. Here the di-
odes are substituted by transistors. The operation is similar
to the comparator from Fig. 39, but the slopes are reduced by
the transistors 웁’s (2).
Suppression of Leakage Currents and Stray Capacitances
If the design calls for a precision comparator where the clamp
levels are to be as accurate as possible, then we have to sup-
press leakage currents from the diodes D1 and D2 in the clamp
circuit which tend to create an offset error similar to an op-
amp offset current. In addition, the use of low resistance val-
ues helps to improve circuit speed and reduces the effects of
offset currents and parasitic capacitances. The comparator of
Fig. 39 is improved in Fig. 42 with extra diodes D3 and D4
(68) and resistor R5 to suppress leakage currents and establish
precision comparator levels (2).

2. D1 OFF, D2 ON. This state is reached when Vin is nega-

tive. Then Vout becomes positive, e2 is eventually 0 V,
and D2 turns ON. Similar to state 1, the equivalent cir- HYSTERESIS
cuit is shown in Fig. 39(d), and Vout is given by
A comparator is improved by adding positive feedback to cre-
E 2 RD
Vout = + (69) ate a hysteresis loop. Hysteresis is usually added to a compa-
RC rator to give some noise immunity. Figure 43 shows an
example (2) where hysteresis adds noise immunity to a
3. The transfer characteristic is shown in Fig. 39(b). The comparator. Let us consider the circuit shown in Fig. 44
slopes in the limiting region are given as follows: which is a comparator with positive feedback added. With-
For state 1, out the positive feedback, a fast amplifier presents a posi-
tive oscillation at the output [see Fig. 43(a).] If the amount
dVout R of positive feedback is small, the amount of hysteresis in
=− B (70)
dVin RA Fig. 45 is given by

and for state 2, RA E W

EH = (72)
RA + E W
dVout R
=− D (71)
dVin RC
And, usually, EH is small, on the order of 10 mV to 20 mV.
As can be seen the slopes are nonzero. In addition there Figure 43(b) shows how noise immunity has been added to
is rounding in the corners because of the nonideal diode the comparator.

D1 D2 Vout

E Z1

RF
0 RF Vin
Vin − −
Rin
Rin Vout E Z2
+

Figure 38. Limiter circuit. (a) Schematic

(a) (b) circuit; (b) transfer characteristic.
506 ANALOG PROCESSING CIRCUITS

+E1 > 0

RA Vout
D1
E 2R C
e1
RD

Rin RB
vin −
Vout
Vin
+
RC

E 1R B
−
RA
D2
RD

−E2 < 0
(a) (b)

+E1 > 0

RA
RB

RA Rin RB
E1 − Vin −
e1
Vout Vout
+ +
RC

RD

−E2 < 0
(c) (d)

Figure 39. Improved comparator. (a) Schematic circuit; (b) transfer characteristic; (c) equivalent
circuit for state 1; (d) equivalent circuit for state 2.

A more accurate circuit is shown in Fig. 46. The dimen- and

sions of the hysteresis loop are given by R2 R6 E N
S− = (73d)
R E R1 R7
L+ = 2 P (73a)
R1 The hysteresis loop is shown in Fig. 47.
R E
L− = − 3 N (73b) LOGARITHMIC AMPLIFIERS
R4
R R E
S+ = 3 6 P (73c) Logarithmic amplifiers, simply called log amplifiers (8), are
R4 R7 extensively used to produce multipliers and signal compres-
 ANALOG PROCESSING CIRCUITS 507

+E1 and

Vin
RA IC = I1 = (77)
D1 R1

then
Q1
kT Vin
RB V0 = − ln (78)
RF q RIS
Rin
Vin −
Vout Thus, we obtain an output voltage proportional to the loga-
+ rithm of the input voltage. The only constraint is that Vin ⬎ 0.
External compensation is usually needed (2) for frequency
RC stability. This compensation can be achieved with a capacitor
Q2
CC in parallel with the feedback element which in our case is
the transistor. Unfortunately, this solution lowers the gain as
the operating frequency increases. To compensate for this, we
D2 add a series resistor rC in series with the emitter, placing a
RD limit on the negative feedback resistance through the transis-
tor. This scheme is shown in Fig. 49. Values for CC and rC are
best determined empirically because parasitic effects play a
−E2 < 0
large role but they are usually in the range of 100 pF for CC
Figure 40. Transistor-based improved comparator. and 1 k⍀ for rC. Note that Eq. 78 for the log amplifier is tem-
perature-sensitive. Furthermore, IS is also temperature-de-
pendent. A solution for this problem is provided by the circuit
shown in Fig. 50. Resistor RTC has a positive temperature co-
sors. Figure 48 shows a basic log amplifier circuit. Note that efficient. It can be shown that
the transistor collector is connected to the virtual ground
node. Because the base is also grounded, the transistor volt-
R2
 kT Vin
age–current relationship is Vout = − 1 + ln (79)
RTC q VREF
−qV0 / kT
IC = aIS (e − 1) (74)

Where kT/q 앒 25 mV at 25⬚C. Equation 74 can be rewritten

as
kT

I0

V0 = − ln +1 (75) +E1 > 0
q aIS
D3
Also, because 움 앒 1 RA
I0 D1

1 (76)
aIS
R
D4 RB
Vout Vin Rin
RC
− Slope −
β 2R 1 E 2R C Vout
RD
+
Rin RC

Vin D2
VREF RD

E 1R B
−
RC RB −E2 < 0
Slope −
β 1R 1
Figure 42. Scheme to reduce leakage currents and stray capaci-
Figure 41. Transfer characteristic for the comparator from Fig. 40. tance.
508 ANALOG PROCESSING CIRCUITS

Vin Vout

ER E R1

t t

E R2
(a)

Vin Vout

ER E R1

Figure 43. Noise immunity in comparator cir- t t

cuits. (a) Comparator without positive feedback;
E R2
(b) comparator with positive feedback. The noise
immunity is evident. (b)

Note that as T increases, the factor kT/q also increases, but Antilog Amplifiers
because RTC has a positive temperature coefficient, the first
A basic antilog amplifier (8) is shown in Fig. 51. Because
factor in Eq. 79 decreases. By properly matching temperature
coefficients and resistor values, negligible variation of Vout

R2
 kT Vin
with temperature is achieved. Vout = − 1 + ln (80)
RTC q VREF

R1
Vout
Vin Clamp

−
R2 Vout
EH
VREF +

Vin
EW
RB
RA

VREF R1
R2
Figure 44. Comparator with added positive feedback to provide hys-
teresis and noise immunity. Figure 45. Hysteresis loop for the comparator in Fig. 43.
 ANALOG PROCESSING CIRCUITS 509

+E1 Q1

D3
R1
D4 D1

Rin CC
Vin R6
Vin −
− R5 R2
A1 Vout
− Vout +
+
+ R1
Q2
R3

D2
R4 rC RTC
Rin CC
−
R7 −E2 A2
VREF
+

Figure 46. Improved circuit with hysteresis loop.

Figure 50. Improved temperature-insensitive logarithmic amplifier.
Includes compensation circuit.
Vout

L+ IC IR

Vin
Q1 RF
−
S− S+
Vout
Vin
+

L− Figure 51. Antilog amplifier.

Q1
Figure 47. Hysteresis loop for the circuit in Fig. 46.

Q1
rC

Rin
Vin − R1
CC
Vout −
Vout
+
+

Figure 48. Logarithmic amplifier. Q2

Rin
Vin
Q1
RTC

rC

Rin CC R1 CC
Vin − −
Vout
VREF
+ +

Figure 49. Logarithmic amplifier with compensation. Figure 52. Improved antilog amplifier.
510 ANALOG-TO-DIGITAL CONVERSION
Log
Vin1
amp
Vin2 Log
Figure 53. Multiplier circuit realized amp
with log and antilog amplifiers.
For Vout, assuming 움 앒 1 and IC /움IS Ⰷ 1, we obtain
Vout = −RIS e −qVin /kT (81)
This is equivalent of saying that Vout is the antilog of Vin. This
circuit has the same drawbacks as the log amplifier for stabil-
ity and temperature dependence. A better circuit is shown in
Fig. 52 which includes the compensation circuit (2).
It can be shown that


q RTC
Vout = VREF exp −Vin (82)
kT R2 + RTC
EXAMPLE 8. The most popular application of log and antilog
amplifiers is in the realization of multipliers. Figure 53 shows
a block diagram of such a multiplier. Each input is fed into a
log amp. Then, the logs of the inputs are summed. Recall that
the sum of the logarithms is the logarithm of the product.
Finally, the antilog amp outputs this product. Then the out-
put has the form
Vout = K · Vin1 · Vin2 (83)
where K is a constant that depends upon the circuit parame-
ters. The only limitation in the circuit is that the input signal
and reference voltage must have the same polarity for each
log amplifier. Thus, our multiplier is a one-quadrant multi-
plier.
Other useful applications of multipliers are frequency dou-
blers, amplitude modulation, phase detection, oscillators, and
automatic gain control (9).
CONCLUDING REMARKS
We have presented circuits for analog signal processing. The
circuits are all based on operational amplifiers. Although the
most commonly used op-amp is the conventional voltage mode
op-amp, simply called op-amp, we have also included the op-
erational transconductance amplifier (OTA) usually found in
high-frequency integrated circuits. The circuits presented are
those currently used in analog signal processing, and in many
cases they are off-the-shelf parts.
BIBLIOGRAPHY
1. C. Tomazou, J. B. Hughes, and N. C. Battersby, Switched-Cur-
rents, An Analogue Technique for Digital Technology, London: Per-
egrinus, 1993.
2. J. V. Wait, L. P. Huelsman, and G. A. Korn, Introduction to Oper-
ational Amplifier Theory and Applications, 2nd ed., New York:
McGraw-Hill, 1992.
k1 ln Vin1
k3(ln Vin1 + ln Vin2) Antilog k4 Vin1 × Vin2
+
amp
k2 ln Vin2
3. F. Dielacher, Design aspects for mixed analog-digital circuits, in
W. Sansen, J. H. Huijsing, and R. J. Van de Plassche, (eds.), Ana-
log Circuit Design, Mixed A/D Circuit Design, Sensor Interface
Circuits and Communication Circuits, Dordrecht: Kluwer, 1994.
4. L. P. Huelsman, Active and Passive Analog Filter Design, New
York: McGraw-Hill, 1993.
5. S. Norsworthy, R. Schreier, and G. Temes, Delta-Sigma Convert-
ers, New York: IEEE Press, 1996.
6. G. E. Tobey, J. G. Graeme, and L. P. Huelsman, Operational Am-
plifiers, New York: McGraw-Hill, 1971.
7. J. Silva-Martı́nez, M. S. J. Steyaert, and W. C. Sansen, A large-
signal very low distortion transconductor for high-frequency con-
tinuous-time filters, IEEE J. Solid State Circuits, SC-27: 1843–
1853, 1992.
8. J. M. Jacob, Applications and Design with Analog Integrated Cir-
cuits, Reston, VA: Reston, 1982.
9. I. M. Faulkenberry, An Introduction to Operational Amplifiers
with Linear IC Applications, New York: Wiley, 1992.
10. A. S. Sedra and P. O. Bracket, Filter Theory and Design: Active
and Passive, Portland, OR: Matrix, 1978.
11. W. J. Kerwin, L. P. Huelsman, and R. W. Newcomb, State-vari-
able synthesis for insensitive integrated circuit transfer func-
tions, IEEE J. Solid-State Circuits, SC-2: 87–92, 1967.
12. L. C. Thomas, The Biquad: Part I-Some practical design consider-
ations, IEEE Trans. Circuit Theory, CT-18: 350–357, 1971.
13. D. Johns and K. Martin, Analog Integrated Circuit Design, New
York: Wiley, 1997.
14. B. Nauta, Analog CMOS Filters for Very High Frequencies, Dor-
drecht: Kluwer, 1993.
15. J. G. Graeme, Applications of Operational Amplifiers, Third Gen-
eration Techniques, New York: McGraw-Hill, 1973.
16. A. Barna and D. I. Porat, Operational Amplifiers, New York: Wi-
ley, 1989.
17. S. Franco, Design with Operational Amplifiers and Analog Inte-
grated Circuits, New York: McGraw-Hill, 1998.
DAVID BÁEZ-LÓPEZ
University of the Americas-Puebla
National Institute for Astrophysics,
Optics, and Electronics
510 ANALOG-TO-DIGITAL CONVERSION

ANALOG-TO-DIGITAL CONVERSION

Analog-to-digital (A/D) converters (ADCs) constitute the key

interface function between analog signals in the physical
world and digital signal processing systems. The importance
of integrated ADCs has grown enormously in recent years, in
line with the increasing importance of mixed analog-digital
VLSI systems. Indeed, with the powerful digital signal pro-
cessing engines available today the fidelity and accuracy of
digitally processed analog signals is fundamentally limited by

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.
 ANALOG-TO-DIGITAL CONVERSION 511

b1 Quantization error
Vin b2 LSB
ADC . b3
.
.
bN
Vref 1 LSB
Vin
Figure 1. Symbol of an ADC.
LSB

Figure 3. Quantization error produced by an ADC when the input

the performance of ADCs rather than by any meaningful digi- signal is a ramp.
tal circuitry limitation. Moreover, given the continuing need
to achieve higher integration functionality at minimum cost
and with minimum energy consumption, the design of ADCs
is becoming increasingly tailor-made to specific applications
rather than, as not long ago, being considered as general pur- where Vref is the reference voltage of the converter and
pose components (1). As a result, a wide variety of ADC archi-

N
tectures and circuit design techniques has emerged in recent n= 2i−1 bi (2)
years, ranging from low to high conversion frequency as well i=1
as from high to low conversion resolution. The most relevant
of such conversion architectures and circuit design techniques represents the output digital code. The difference between
are described in this article. two consecutive quantization levels is usually designated the
least significant bit (LSB) of the converter. From Eq. (1) this
is given by
FUNDAMENTAL ASPECTS OF A/D CONVERTERS
Vref
Conversion Between Analog and Digital Samples LSB = (3)
2N
Ideal Conversion Characteristic. An ADC is usually repre-
sented by the symbol indicated in Fig. 1, where the number Quantization Noise. Even assuming that the conversion
of bits N of the output digital word indicates the conversion characteristic of an ADC is ideal, the quantization process
resolution. The conversion characteristic of an ADC is ob- produces a quantization error signal that is a function of the
tained by determining the transition voltages (VT)n of the in- conversion resolution. This is often called the quantization
put analog signal that produce a change of the output digital noise of the converter (2). Figure 3 illustrates the shape of
code. The time interval between two consecutive input sam- such a quantization error signal when the input signal is a
ples indicates the sampling period Ts. The conversion fre- ramp. Assuming that the maximum quantization error is uni-
quency is Fs ⫽ 1/Ts. formly distributed between ⫺LSB/2 and ⫹LSB/2, then it can
Figure 2 illustrates a portion of the ideal conversion char- be shown that the total quantization noise power can be ex-
acteristic of an ADC. The analog input transition voltages are pressed as
defined by
LSB2
V PQ = (4)
VT n = ref n (1) 12
2N
In most practical cases the quantization noise power is
uniformly distributed in the Nyquist frequency band from dc
to ⫹Fs /2, as depicted in Fig. 4, such that the corresponding
Digital output
power spectral density SQ2 ( f) is expressed as
 
111 LSB2 2
S2Q ( f ) = (5)
110 LSB 12 Fs

101

100

011 S Q( f )

010
LSB 2
001 12 Fs
000
0 VT1 VT 2 VT3 VT4 VT 5 VT6 VT7 Vref Vin 0 Fs /2 f

Figure 2. Ideal conversion characteristic of an ADC. Figure 4. Uniform power spectral density of the quantization noise.
512 ANALOG-TO-DIGITAL CONVERSION
For any given frequency band within the Nyquist band, that
is, from dc to f c ⬍ Fs /2, the total noise power is given by
  2 
fc
LSB 1 LSB2
√  df =
0 12 Fs /2 12
Equation (6) indicates two possible solutions for reducing
the quantization noise of a converted signal at a given fre-
quency. One solution is to reduce the converter LSB by in-
creasing its resolution N, whereas the alternative solution
corresponds to having a conversion frequency much higher
than the signal being converted. This is called oversampling
and the factor of oversampling the signal would be defined by
(Fs /2)
OSR =
fc
Increasing the resolution of an ADC gives a reduction of the
noise power of approximately 6 dB per added bit of resolution.
As this would be guaranteed over the full Nyquist range, such
type of converters are called Nyquist converters. In the so-
called oversampling converters, a further reduction of the
quantization noise power is obtained by oversampling the sig-
nal with respect to the Nyquist frequency; it yields an addi-
tional gain of approximately 3 dB per octave of oversampling.
Dynamic Range of a Quantized Signal. The dynamic range
of a quantized signal is commonly determined with respect to
a sinusoidal waveform between 0 and Vref , whose power is
2
Vref /8. Thus, from Eq. (4), the resulting signal-to-noise (SNR)
ratio of the quantized signal will be given by
 
Pin 2
Vref /8
SNR(dB) = 10 log = 10 log
PQ LSB2 /12
From Eq. (3) this results in
 
3 2N
SNR(dB) = 10 log 2 = (6.02N + 1.76) dB
2
For example, the conversion of an analog sine waveform using
a 10-bit ADC will lead to a digital sine waveform with an
SNR of approximately 61.8 dB.
Conversion Codes. When an ADC operates with only posi-
tive (or negative) signals its output is normally a natural bi-
nary code. There are many cases, however, when the ADC
has to operate with both positive and negative signals, thus
resulting in the need to produce both positive and negative
output digital codes. Two of the most popular of such codes
are the sign magnitude code and the 2’s complement code.
In the sign magnitude code, negative and positive digital
numbers are represented by the same code except for the
most significant bit (MSB): for positive codes MSB ⫽ 0,
whereas for negative codes MSB ⫽ 1. For example, the sign-
magnitude representation for 7 is 0111, whereas for ⫺7 it is
1111.
In the 2’s complement code, positive codes are represented
as natural binary codes with MSB ⫽ 0. The negative codes
are obtained from the equivalent positive number by first
complementing all the bits and then adding 1 LSB. For exam-
Digital output
 111
1 - Offset error
2 fc
(6) 110 2 - Full-scale error 2
Fs
101
100
011
010
001 1
000
0 VT1 VT 2 VT3 VT4 VT 5 VT6 VT7 Vref Vin
(7)
Figure 5. Illustrating offset, full scale and gain errors of an ADC.
ple, for the representation of ⫺7 we obtain first 0111 (corre-
sponding to the positive number ⫹7), then we obtain 1000
(corresponding to the complement of all bits of 0111) and fi-
nally we obtain code 1001 (adding 1 LSB to 1000). An impor-
tant advantage of the 2’s complement code is that the addition
of both positive and negative numbers is made by straightfor-
ward addition and no extra computations are needed. For ex-
ample, 0111 (number ⫹7) added to 1001 (number ⫺7) gives
0000 (of course the carry bit is neglected).
ADC Limitations and Performance Parameters
Offset, Full Scale and Gain Errors. Figure 5 represents both
the ideal and actual conversion characteristics of a 3-bit ADC
(3). The former is represented by the broken line that unites
(8)
the white dots corresponding to the ideal input transition
voltages between all digital codes in the absence of conversion
errors, whereas the latter is represented by the full line that
unites all black dots corresponding to the actual analog tran-
sition voltages between all digital codes. On the lower ex-
(9) treme of the conversion characteristic, the offset error corre-
sponding to 䊊 1 represents the difference between the actual
and ideal input voltage that produces a transition of one LSB
from the output digital code 0. On the upper extreme of the
conversion characteristic, the full-scale error corresponding to
䊊2 represents the difference between the actual and ideal in-
put voltages that produce the transition of the output to the
full scale digital code. The gain error of the ADC corresponds
to the difference between the ideal slope of the conversion
characteristic and its actual value.
Differential and Integral Nonlinearity. The differential non-
linearity (DNL) in the ADC expresses the deviation of the dif-
ference between the actual input transition voltages Va(n)
and Va(n ⫹ 1) that produce any two consecutive output digital
codes from the difference voltage corresponding to one LSB.
Such LSB must be determined through a linear characteristic
with the same offset and full-scale errors. This gives a mea-
sure of the linearity of operation for small incremental signals
and can be expressed by
Va (n + 1) − Va (n)
DNL(n) = −1 (10)
LSB
 ANALOG-TO-DIGITAL CONVERSION 513

for any digital code between n ⫽ 1 and n ⫽ 2N ⫺ 2. The nor- Ideally sampled signal
mal specification for the DNL of the ADC is ⬍ ⫾(1/2) LSB. It Sampling with jitter noise
should also be mentioned that when the DNL is larger than
1 LSB a phenomenon of nonmonotonicity occurs whereby the
output digital code decreases with an increase of the analog
input signal.
Ts
By contrast with the DNL, the integral nonlinearity (INL)
in the ADC gives a measure of the linearity of operation for
t
large signals, as it expresses the deviation between the actual
input transition voltages obtained for a given digital code and
the corresponding ideal transition voltages assuming a linear
characteristic with the same offset and full-scale errors. For
any digital code from n ⫽ 1 to n ⫽ 2N ⫺ 1, this can be defined
as (a)

Va (n) − Va (1)
INL(n) = − (n − 1) (11) n
LSB
(b)
and relates to the DNL through the equation Figure 7. Illustrating the effect of sampling jitter. (a) Sampled sine
waveform. (b) Jitter related error signal.

n−1
INL(n) = DNL(i) (12)
i=1 pling instants, as illustrated in Fig. 7(a). For a fixed conver-
sion frequency, it is easily seen that the resulting signal error,
The normal specification for the INL of an ADC is also ⬍ ⫾(1/ represented in Fig. 7(b), increases as the frequency of the in-
2) LSB. Figure 6 illustrates the preceding definitions of the put analog signal increases. It can be shown that in order to
DNL and INL of an ADC. obtain an error signal smaller than the LSB of the converter
the sampling jitter must be such that

1
Sampling Jitter. An important dynamic error that affects
ts < (13)
the performance of an ADC, especially for high-frequency op- π2N+1 f
eration, is due to the timing uncertainty of the sampling in-
stants that produce the input analog samples for conversion where f is the frequency of the input signal. For example, for
(4). Because of this error, commonly called sampling jitter, the a 10-bit ADC at 1 MHz this corresponds to a maximum timing
actual sequence of analog samples is not equally spaced in uncertainty of 310 ps.
time but rather varies with respect to the nominal ideal sam-
Effective Number of Bits. A global parameter that summa-
rizes the performance behavior of an ADC is the effective
number of bits (ENOB) expressed as

SINADdB − 1.76
Digital output ENOB = (14)
6.02

111 where the parameter SINADdB (signal-to-noise-plus-distortion

110
ratio) represents the combined effect of quantization and har-
monic distortion due to the various sources of nonlinearity of
101 INL the converter. An example of the graphical evolution of the
100
ENOB is given in Fig. 8, for an ADC with Fs ⫽ 40 MHz con-
DNL
version frequency, showing that the effective number of bits
011 of the converter decreases as the signal-to-noise-plus-distor-
LSB tion ratio decreases for higher frequencies of input analog
010
signal.
LSB
001
0 Vref
000 NYQUIST ANALOG-TO-DIGITAL CONVERTERS
VT1 VT 2 VT3 VT4 VT 5 VT6 VT7 (ideal transitions) Vin
From the standpoint of the conversion frequency, we can clas-
VT1 VT 2 VT3 VT4 VT 5 VT6 VT7 (actual transitions) sify ADCs into three main groups. Serial converters are the
slowest of all because each bit of the output digital word is
Figure 6. Integral nonlinearity (INL) and differential nonlinearity usually determined in a number of clock cycles that rises pro-
(DNL) of an ADC. portionally to the equivalent bit weight. For example, for the
514 ANALOG-TO-DIGITAL CONVERSION

10.0 trated in Fig. 9(a), comprising an active-RC integrator with

Fs = 40 MHz multiplexed input, a comparator and a digital counter and
60
9.5 control logic. Figure 9(b) illustrates the time-domain wave-
Effective number of bits

forms typically produced in the converter during a complete

9.0 56 conversion cycle. At the beginning of the conversion cycle the

SINAD (dB)
capacitor around the feedback loop of the opamp is reset to
8.5
zero. Then, the integrator input is connected to the input sig-
52
nal terminal to generate the first integration ramp that is
carried out during a fixed time interval T1 controlled by the
8.0
48 digital counter. Thus, for a clock period of Ts the opamp out-
put voltage reached after the first integration ramp is
7.5
44
N1 Ts
7.0 Vx = (−Vin ) (15)
100 k 200 k 500 k 1M 2M 5M 10 M 20 M RC
Input signal frequency (Hz)
where N1 is the fixed number of clock cycles counted during
Figure 8. Evolution of the effective number of bits of an ADC as a
T1. Next, the input terminal is switched to the reference volt-
function of the frequency of the input signal.
age terminal and a second integration ramp is generated
whose slope is the negative of the first integration ramp. This
is carried out until the comparator detects that the output
voltage of the amplifier crosses zero and thereby stops the
LSB this may take only one clock cycle, but for the most sig- digital counter. The duration of this second integration ramp,
nificant bit this may take as long as 2N clock cycles. By con- T2 ⫽ N2Ts, varies as the voltage at the output of the amplifier
trast with their low speed, serial processing converters offer at the end of the first integration ramp is larger or smaller.
the highest resolution of all the converters described in this This is determined from
section. They are therefore particularly useful to interface
slowly varying signals for very high precision signal pro- N2 Ts
0 = Vx + V (16)
cessing as required, for example, in instrumentation and bio- RC ref
medical applications.
Following the serial converters in the speed scale is the
group of algorithmic ADCs. Here, conversion takes place in a
number of clock cycles that is typically proportional to the
conversion resolution. Hence, depending on the actual fre-
quency limitations of the constituting building blocks, conver- C
Vin
sion frequencies of a few megahertz can be achieved without
too much difficulty in modern complementary metal oxide R
–
semiconductor (CMOS) technology. Algorithmic ADCs consti-
– bN
tute a versatile group of converters that can meet a wide Vref
+ Vx Counter
range of specifications in terms of the conversion frequency + and logic b1
as well as resolution. A particular type of ADC based on the
successive approximation algorithm constitutes an industry
workhorse for a large variety of applications.
The fastest group of converters is based on parallel pro- (a)
cessing techniques that allow a full conversion period to be
performed in only one or, at most, a few (e.g., 2) clock cycles. Vx
One-clock cycle (flash) ADCs in modern CMOS technology can –Vin3
reach conversion frequencies above 100 MHz but their resolu- Phase (II)
tion is limited to no more than 8-bits. An increasingly popular Phase (I)
(Constant slope)
group of parallel ADCs is based on pipeline architectures that
can perform a full conversion period in only two clock cycles, –Vin2
although there is an initial latency period that depends on
the total number of stages of the pipe. Pipeline converters
–Vin1
with optimized silicon and power dissipation are in great de-
mand for video processing applications for the consumer Time
Constant T1
market.
Varying T2 for
three inputs
Serial Processing ADCs (b)
Double-Ramp Integration. One of the best known architec- Figure 9. Serial processing ADC with double-ramp integration. (a)
tures for serial processing analog-digital conversion is illus- Typical circuit realization. (b) Waveforms.
 ANALOG-TO-DIGITAL CONVERSION 515

Reset where ⫺Vref (Ci /Cf ) ⱕ Vx ⱕ 0 and n is the output of the counter
(digital integrator). This implies
Vin Reset
+ Vout  
– Vin
– Control n = 2N + (19)
logic Vref
+
CKc U/D
b
where the residual error is 0 ⱕ ⑀ ⱕ 1. Thus, n is an N-bit
b+1
(–1) digital representation of the sampled input voltage, with a
Counter quantization error ⑀ ⱕ 1 LSB.
As in the double-ramp integrator, the conversion charac-
Vref teristic expressed by Eq. (19) is independent of the capaci-
Data out (N ) tance ratio and, hence, resolutions of the order of 16-bits and
Figure 10. Conceptual block diagram of an incremental ADC. above can also be achieved without too much difficulty. Of
course this will be possible only for very low frequency of con-
version due to the serial processing nature of the converter.
and which, combined with Eq. (15), yields
Algorithmic A/D Converters
N2
Vin = V (17) Next in the scale of conversion frequency is the group of algo-
N1 ref
rithmic ADCs where the number of clock cycles needed for
Hence, the variable time interval of the second integration conversion is directly, rather than exponentially, proportional
ramp (expressed in terms of the counted number of clock cy- to the conversion resolution. Two types of algorithmic ADCs
cles) is a measure of the value of the analog input signal inte- will be described. The first is based on the classical successive
grated during the first integration ramp. approximation algorithm and constitutes the industry work-
Because the conversion function Eq. (17) is independent of horse for a large variety of applications. The second is based
the passive circuit elements it allows very high conversion on a cyclic divide-by-two and subtract algorithm whose circuit
resolutions to be achieved, although at rather low conversion implementations can be made more compact than in the case
frequencies. Such high-resolution and low-speed conversion of the successive approximation ADC.
characteristics render double-ramp ADCs particularly suit-
able for applications in telemetry, instrumentation, and mea-
surements.
Vin S1
SR
Incremental Converters. Another type of serial processing
ADC is based on the so-called incremental converter (5,6). Its S2 Ci S5
Vref Cf Latched
conceptual block diagram is illustrated in Fig. 10 where, as – comparator
before, the processing core of the converter is formed by an –
S3
integrator and a comparator. The control logic and digital GND S4 + Vx
counter provide the additional digital processing functions re- + To
quired for conversion. The main difference with respect to the control
logic
previous double-ramp converter lies in the fact that the inte-
gration variable is now formed by the difference between the (a)
sampled input signal and an analog signal determined as a
function of the output voltage of the comparator.
A switched-capacitor implementation of the processing Vx
core of an incremental ADC is shown in Fig. 11(a). It is as-
sumed that during a full conversion cycle the sampled input
signal of the converter is held constant. For simplicity of the 0
t
following discussions it is further assumed that the input
sampled and held signal is positive. At the beginning of the
conversion cycle, the integrating capacitor is reset by closing
switch SR. In each subsequent conversion step switches S1,
S3, S4, and S5 are controlled in such a way as to produce an
incremental variation of ⌬Vx ⫽ ⫺(Ci /Cf )Vin at the output volt-
age of the opamp. Then, whenever Vx reaches zero, a fraction
of the reference voltage, actually (Ci /Cf )Vref , is subtracted from –VRef Ci/C2
the output using switches S2, S3, S4 and S5, and the digital N
1 2 3 4 5
counter is advanced by 1. The typical waveform observed at
the output of the opamp is depicted in Fig. 11(b). At the end 2n integration cycles
of 2N conversion steps the output voltage becomes
(b)
C C
Vx = 2 Vin i − n × Vref i
N
(18) Figure 11. Switched-capacitor incremental ADC. (a) Circuit diagram
Cf Cf and (b) Typical output waveform.
516 ANALOG-TO-DIGITAL CONVERSION

Vref
1111

approximation
111x

Successive
1110

register
11xx
1101 D/A
110x
1100
1xxx –
1011
101x +
1010
10xx
1001 Comparator
100x Vin S/H
1000
xxxx
0111 Figure 13. Block diagram of a successive approximation ADC.
011x
0110
01xx
0101
010x employing digital-to-analog converters with capacitive divi-
0100
sion (1). The latter is one of the most popular forms of imple-
0xxx
0011 mentation, especially for CMOS technology, as it uses a ca-
001x pacitor array that can also provide the additional functions of
0010
00xx sample-and-hold and subtraction needed in the conversion al-
0001
000x gorithm.
0000 Figure 14 illustrates the implementation of a successive
approximation ADC using an array of switched binary-
weighted capacitors. During the execution of one conversion
(MSB) (LSB)
cycle the circuit is sequentially reconfigured as illustrated in
Figure 12. Illustrating the successive approximation algorithm for Fig. 15. First, as seen in Fig. 15(a), the opamp is connected in
analog-to-digital conversion. a unity-gain feedback configuration while the capacitors are
connected to the input terminal. Because of the virtual
ground created at the negative terminal of the opamp the in-
Successive Approximation ADC. The successive approxima- put voltage signal is sampled onto the top plate of the capaci-
tion ADC is based on the algorithm schematically represented tors. In the next phase, shown in Fig. 15(b), the most signifi-
in Fig. 12, for an example of 4-bits conversion. The equivalent cant capacitor is connected to the reference voltage and, as a
analog weights of the digital bits are Vref /2, for bit b4 (the result, a process of charge redistribution between this and the
MSB), Vref /4 for bit b3, Vref /8 for bit b2, and finally Vref /16 for remaining capacitors takes place, yielding a new voltage ex-
the LSB (bit b1). The execution of the algorithm is done from pressed by
the MSB to the LSB during a number of clock cycles equal to
the resolution of conversion. At the beginning of the conver- Vref
Vx = −Vin + (20)
sion, the input signal is compared with the analog weight of 2
the MSB and the result is either b4 ⫽ 1 or b4 ⫽ 0, depending
on whether the signal is above or below Vref /2. If the result is at the negative terminal of the open loop opamp. If this is
‘1,’ then the analog weight of the MSB is subtracted from the negative, then the output voltage indicates the equivalent
input signal; otherwise the input signal remains unchanged. logic value ‘1’; otherwise it indicates the equivalent logic value
In the next phase, the available analog signal is compared ‘0.’ In the former case, the MSB is set to ‘1’ and the corre-
with the analog weight of bit b3 and the result is either b3 ⫽ sponding branch remains connected to the reference voltage.
1 or b3 ⫽ 0, depending on whether the signal is above or be-
low Vref /4. If the result is ‘1,’ then the analog weight of bit b3
is subtracted from the analog signal; otherwise the signal re-
mains unchanged. Similar operations are carried-out in two 1
more steps until the LSB is resolved. 2N– 1C 2N– 2C 2C C C Vx
–
Figure 13 represents a possible conceptual block diagram Vo
for the implementation of the forementioned successive ap- +
..
..
.

proximation algorithm. The input sample-and-hold block pro- Vin

vides the analog sampled signal for conversion. The digital- 1
..
..
.

2
to-analog converter generates the equivalent analog values of 1
the digital words containing the bits that are sequentially re- 2
..
..
.

solved, from the MSB to the LSB. The comparator acts as

the decision element that indicates to the digital successive bN bN–1 b2 b1
Vref
approximation register how the input analog signal is being
approximated by the reconstructed analog values. Successive approximation register
There are various possible circuit solutions for the imple-
mentation of the block diagram in Fig. 13, some employing Figure 14. Switched-capacitor implementation of a successive ap-
digital-to-analog converters with resistive division and some proximation ADC.

2N– 1C 2N– 2C 2C C C Vx
–
..
...
+ 2
Vin
(a)
2N– 1C 2N– 2C 2C C C Vx
–
bN
..
...
+ Figure 16. Conceptual block diagram of a multiply-by-two cyclic
Vref
(b)
2N–1C 2N– 2C 2C C C Vx
–
...
..
+ in the conceptual diagram shown in Fig. 16, comprising an
Vref
bN = 1 bN–1 = 1 b2 = 0 b1 = 0
(c)
Figure 15. Sequence of configurations of the SC successive approxi-
mation ADC during one cycle of the conversion algorithm.
In the latter case, the MSB is set to ‘0’ and the corresponding
branch is connected back to ground. In this case, there will be
a further charge redistribution in the array such that the
original input voltage appears again at the negative terminal
of the opamp. After all bits have been tested by similar se-
quences of charge redistribution and comparison, the connec-
tion of the capacitors either to ground or to the reference volt-
age will reflect the final configuration of the converted output
digital word, as seen in Fig. 15(c).
In the preceding SC successive approximation ADC the ac-
curacy of conversion is limited both by capacitance mismatch
errors and by the input referred offset voltage of the opamp.
Capacitance matching accuracy can be maximized by adopt-
ing careful layout designs of the capacitor arrays properly
sized, whereas the input-referred offset of the opamp can be
virtually eliminated by means of auto-zero techniques. Thus,
untrimmed conversion resolutions of up to 9 to 10 bits can be
comfortably achieved by SC successive approximation ADCs.
For higher resolutions it is mandatory to employ calibration
techniques which can extend the inherent matching accuracy
of integrated capacitor-arrays well above the inherent tech-
nology-dependent 10-bit level.
Regarding the speed of conversion, there are two main lim-
itations imposed on the operation of the SC successive ap-
proximation ADC in Fig. 14. One is due to the speed of the
comparator, whereas the other results from the RC time con-
stants associated with each SC branch because of the equiva-
lent on-resistance of the switches. In most cases such time
constants can be properly controlled by sizing accordingly
both the transistor aspect ratios and the input capacitors and
hence the speed of conversion becomes limited essentially by
the speed of the comparator. This allows the design of SC
successive approximation ADCs in modern CMOS technology
ANALOG-TO-DIGITAL CONVERSION 517
Vin
1 Vx
S/H 2X +
bi
–
Vref
+
–
ADC.
to meet a wide range of conversion specifications, from a few
kilohertz to the megahertz range.
Cyclic ADC. Another type of algorithmic ADC is illustrated
input sample-and-hold, a two-fold gain amplifier, a compara-
tor, and an adder (7). In the sampling phase, the input multi-
plexer is initially connected to the input terminal. Next, the
input signal is multiplied by two and compared with Vref to
resolve the most significant bit. Depending on the result, a
residual signal will be fedback to the input of the circuit for
further processing (thus the designation of cyclic conversion).
If Vin ⬎ Vref , then MSB ⫽ 1 and the generated residual signal
will be (2Vin ⫺ Vref ). If, on the contrary, Vin ⬍ Vref , then
MSB ⫽ 0 and the residual signal will be simply the signal
2Vin. The residual signal will be again multiplied by two and
compared with Vref to resolve the second most significant bit
and again generate a new residue. This cycle repeats as many
times as the number of bits to be resolved and, hence, the
conversion time is directly proportional to the resolution of
the converter.
A possible SC implementation of a cyclic ADC is shown in
Fig. 17. The first opamp samples the input signal in the first
conversion cycle, and the residue signal in the remaining con-
version cycles. The second opamp performs the combined
functions of amplification by two of the recycling residue and
addition. The 1-bit digital-to-analog conversion function is
performed by the switched capacitor that can be connected
either to Vref or ground. The number of components and capac-
itance spread is independent of the conversion resolution and,
Vin
C C
– 2C C
– Vx
+ –
+ bi
+
C
Vref
Figure 17. Switched-capacitor realization of a cyclic ADC.
518 ANALOG-TO-DIGITAL CONVERSION

Vin put of the comparators is encoded into an N-bit two’s-comple-

ment binary code and then latched.
VT One circuit solution that is particularly suitable for inte-
2N S/H φ
grated circuit implementation in CMOS technology is shown
in Fig. 19. Here, the multilevel reference voltage generator is
VT
formed by a resistor-string with direct connection of the out-
Multilevel reference voltage generator

2N–1 – put voltage taps to the inputs of a bank of latched compara-

Thermometer to binary encoder

+ ploys input offset voltage compensation by auto-zero. Slight
VT
i –
+ With only one clock cycle per conversion period, the flash
VT
1 –
+ D
VT
0 the two-step flash converters.
Figure 18. Typical block diagram of a flash ADC.
hence, the converter can be very compact even for medium to
high resolution.
Parallel Processing ADCs (8)
Flash ADC. The block diagram of a flash ADC is repre-
sented in Fig. 18 (9). It comprises an input sample-and-hold
circuit, a multilevel reference voltage generator with output
taps directly connected to the inputs of a bank of comparators
and, finally, some digital circuits for latching and encoding
the output voltages of the comparators. The input voltage is
sampled and held and then compared simultaneously with
2N ⫺ 1 voltages (for a resolution of N-bit) of the reference
voltage generator. The resulting thermometer code at the out-
D Q
tors. Each of the latched comparators in the converter em-
. bN
. modifications of this architecture can also be considered if a
. specialized sample-and-hold circuit is employed, rather than
the distributed scheme already mentioned here.
D Q
. ADC gives the fastest possible time of conversion. However,
. b3
. because of the very large number of resistances and especially
b2 comparators needed (proportional to 2N), this type of convert-
Q ers usually occupies a very large area for implementation and
b1
burns a significant amount of power. In practice, they are
therefore limited to conversion resolutions of no more than 8-
bits. In order to overcome such limitations and still achieve
high speed of conversion, two alternative types of parallel pro-
cessing ADCs are described next, namely the subranging and
Subranging ADC. The conceptual block diagram of the sub-
ranging ADC is illustrated in Fig. 20 and which comprises,
besides the input sample-and-hold, two flash-like converters,
one with N1-bits and the other with N2-bits, connected by a
digital-to-analog conversion block (10). The resulting digital
codes of both flash converters are combined to form the con-
verted output digital word of the converter. After input signal
sampling, the operation of the subranging converter is per-
formed in two phases, namely a coarse conversion phase
where typically the N1 most significant bits are determined,
and a fine conversion phase where the remaining N2 least sig-
nificant bits are obtained.
The behavior of the subranging converter in both the
coarse and fine conversion phases is identical to the behavior
of the flash, although the set of voltages to which the input
voltage is compared is different from one phase to the other,

Vref + Vin

R φ1 φ1 φ1 φ1
Thermometer to binary encoder

..
.
voltage taps

φ2
.. φ 2
.. ..
.. .. bN
R . . .
φ1 φ1 φ1 φ1

..
N –1

.
.. φ 2 φ2
. b3
2

.. ..
R .. .. b2
φ1 . φ1 . φ1 φ1
b1

R
φ2 φ2
Figure 19. The CMOS implementation of
a flash ADC.
Vref –
 ANALOG-TO-DIGITAL CONVERSION 519

Vin V

Sample and
Sample and hold
hold
res ra
+ G
_
VT VT
2N 2N
VT
2N
G= 2 N1

N1-bits flash quantizer

N2-bits flash quantizer

N1-bits flash quantizer

N2-bits flash quantizer

VT N1-bits N2-bits
(i + 1) 2 N2

D/A converter
N1-bits N2-bits
D/A converter

VT
(i) 2 N2

VT VT
0 0
VT
0 bN bN bN bN b2 b1
.
.
.

.
.
.
2+2 2 +1 2
bN bN bN bN b2 b1
.
.
.

.
.
.

2+2 2 +1 2
Figure 22. Conceptual block diagram of a two-step flash ADC.
Figure 20. Conceptual block diagram of a subranging ADC.

as seen in Fig. 21. In the coarse conversion phase the input ADCs offer an attractive solution for the integrated imple-
voltage is compared with a set of 2N/2 ⫺ 1 voltages spanning mentation of high-speed ADCs with 8-bits resolution and
the whole input signal range, and the resulting MSBs indi- above.
cate the specific conversion interval that encompasses the
sampled input voltage. Then, in the fine conversion phase the Two-Step Flash ADC. The conceptual block diagram of a
selected conversion interval is segmented into a further two-step flash ADC is shown in Fig. 22, comprising two flash
2N/2 ⫺ 1 voltages in order to determine the remaining LSBs. quantizers, one with N1-bits and the other with N2-bits, a digi-
In subranging ADCs the required number of comparators tal-to-analog converter (DAC) and also a gain block that am-
and resistors is only proportional to 2N/2 rather than to 2N as plifies the difference between the input analog signal and the
in the case of the pure flash ADC. Therefore subranging partially reconstructed analog signal obtained at the output
of the DAC (11,12). The conversion cycle is divided into a sam-
pling phase, a coarse conversion phase, and a phase for the
1st Step 2nd Step amplification of the residue and its fine conversion. After
MSBs LSBs sampling, the input voltage is applied to the input of the N1-
VT bits coarse quantizer to determine the MSBs that are latched
16
into a digital register. Afterwards, the converted digital code
11 is reconstructed back to an analog voltage by means of the
DAC. This voltage is then subtracted from the input voltage
VT VT signal to form the residue signal of the converter. This, in
12 12 11
VT turn, is amplified by the gain block G ⫽ 2N1 and then applied
x x 11 10
10 VT to the N2-bits fine quantizer to determine the LSBs of the
10 01
VT converter. The final output digital code is obtained by combin-
9 00
VT VT ing the MSBs of the first quantization phase together with
18 8
the LSBs of the second quantization. The accuracy of the am-
01 plified residue signal generated internally in the two-step
flash ADC is a key factor to determine the overall linearity of
VT the converter. Under ideal circuit conditions it evolves be-
4
tween two consecutive digital codes as illustrated in Fig. 23,
00
where the slope of the characteristic is defined by the ampli-
fication factor of the gain block.
VT A circuit implementation of the two-step flash ADC that is
0
particularly suitable for integration in CMOS technology is
Figure 21. Illustrating the two quantization phases in a subrang- shown in Fig. 24. The multiplying DAC uses an array of
ing ADC. switched capacitors and an opamp, whereas the flash quan-
520 ANALOG-TO-DIGITAL CONVERSION

pled voltage. A residue amplified by 2N/2 is then generated at

the output of the amplifier. This is again applied to the flash
+1/2 to determine the remaining N/2 LSBs.
Residue (in LSB of the
1st conversion)

Digital Error Correction. Because of unavoidable circuit im-

0 pairments associated with practical integrated circuit realiza-
–1/2
VT VT
0 2 N2
Figure 23. Amplified residue signal internally generated in the two-
step flash converter under ideal circuit components characteristics.
tizer is identical to the one presented in Fig. 19 because it
first samples the voltages generated by the resistor-string
into the input capacitors (Ci), and then compares them with
the input voltage. It is possible to realize both the coarse and
fine conversions by the same flash. The operation of this par-
ticular configuration is as follows. The input voltage is sam-
pled in the top plates of the capacitor array, while the input
capacitors of the flash sample the corresponding voltages gen-
erated in the resistor-string. In the next phase, the whole
array is connected as the feedback of the opamp, thus holding
at its output the sampled voltage. This output is next applied
to the input of the flash to determine the N/2 MSBs. In the
next phase, the resolved bits are applied to the DAC to sub-
tract the reconstructed analog voltage from the original sam-
tions, the quantization window determined by the first flash
quantizer in both the subranging and two-step flash ADCs is
determined with a maximum error of ⫾1/2 LSB of its nominal
resolution, rather than with an ideal 0 LSB error. When this
error is passed on to the second quantization phase it may
overflow the quantization range of the flash and thus produce
Vin errors in the overall conversion characteristic.
VT VT
(2N1 – 1) 2N2 2N To correct for such errors the flash quantizer may be aug-
mented beyond its nominal resolution, for example by ⫹1/2
LSB on the upper boundary of the quantization window and
by ⫺1/2 LSB on the lower boundary of the quantization win-
dow, such that the additional resolved bit can be subse-
quently used for digital code correction. This technique is il-
lustrated in Fig. 25. The quantization zone A corresponds to
the original comparators in the center of the flash quantizer,
zone B corresponds to the additional lower comparators and
zone C corresponds to the additional upper comparators.
When the MSB flash quantizer determines correctly the
quantization zone A, as in Fig. 25(a), the output digital code
is obtained directly from the outputs of the comparators.
When the flash quantizer resolves instead a code within zone
B, as shown in Fig. 25(b), the output digital code of the previ-
ous quantization will be corrected by ⫺1. Finally, when the
flash quantizer resolves a code within zone C, as illustrated
in Fig. 25(c), the output digital code of the previous quantiza-
tion will be corrected by ⫹1.

Vref + Vin φ1 Vref + Vin Vref + φ2

φ1 φ2 φ1 C N1–1 φ2 φ1
R′ φ1 R′′
φ2 – 1 φ2 φ1 –
D Q CF φ2 .. D Q
.. .. + .. 0 .. .. + ..
. . .. .. . . . ..
.. . . .. .. .
. .. ..
φ1 φ2 .. .. φ1 . φ1 φ2 φ1 ..
R′ .. .. . C2 R′′ .. .
. . .
.. – φ2 – Vref – .. –
. φ2 1 . φ1
+ D Q + + D Q
0

φ1 φ2 φ1 C1 φ2 φ1
R′ R′′
φ2 – 1 φ2 φ1 –
+ D Q + D Q
0
φ1 C0
R′ 2 N1–1 R′′ 2 N2 –1
rows φ2 rows

Vref – Vref –
Vref –
Thermometer to Thermometer to
binary encoder binary encoder
bN b N2 + 1 b N2 b1

Figure 24. The CMOS implementation of a two-step flash ADC.

 ;
ANALOG-TO-DIGITAL CONVERSION 521

MSBs FLG LBSs Digital error correction Pipeline A/D Converters

. .

;
. . Architecture and Operation. Pipelined ADCs constitute a
. .
1011 type of parallel processing converters that have gained popu-
1 0111
larity in a variety of high-speed conversion applications due
C to the cost/benefit they can achieve over the subranging and
two-step flash converters (13,14). The conceptual block dia-

;
1 0000
0 1111 gram of a pipeline ADC is shown in Fig. 26(a), for an example
MSBs LBSs FLG with five pipelined stages, and the associated timing diagram
Vin Vin is given in Fig. 26(b). During the first phase of the first clock
1010 0 1000 A 1010 1000 0 = no error
cycle, the input stage samples the input signal and executes

;
the first quantization. Then, in the second phase the residue
is generated, amplified, and transmitted to the second stage
0 0000 of the pipeline for further processing. In subsequent clock cy-
1 1111 1010 1000 final result cles similar operations of sampling, quantization, and residue
B generation are again carried out in the first stage. Mean-

;
while, in the second stage, these operations are performed in
1001 1 1000 opposite phases. Input sampling and quantization are per-
. .
. . formed when the first stage is amplifying the residue,
. .
(a) whereas residue amplification and transmission to the next

;
stage are performed when the first stage is receiving a new
MSBs
. .
FLG LBSs Digital error correction input sample. In parallel with this form of horizontal propa-
. . gation of the signal (actually, the signal residues), the digital
. .
words quantized in each stage and in each clock cycle are
1101
1 0111 propagated vertically through digital registers, as seen in Fig.
C 26(a), such that at the end of five clock cycles they are all
available at the output of the converter to produce the con-
1 0000 verted digital word. Then, after this latency period, which is
0 1111
MSBs LBSs FLG needed to fill all the vertical digital registers, there will be

;
one converted digital word every clock cycle.
1011 A 1011 1100 1 = error The maximum resolution achieved with such an architec-
ture is limited mainly by thermal noise, the nonlinearity of
– 1 the MDACs produced by capacitor mismatches and also by
the residue amplification error that is due to the amplifier

;
0 0000 nonidealities. The error from the flash quantizer can be digi-
1 1111 1010 1100 final result
Vin Vin B tally corrected if kept within ⫾1/2 LSB of the nominal resolu-
1 1100 tion of the quantizer and redundancy is used for digital er-
1010 1 1000 ror correction.
. .

;
. .
. . Time-Interleaved Converters
(b)
An extended concept for parallel processing conversion is
MSBs FLG LBSs Digital error correction based on the use of the type of time-interleaved architectures
. .
. .

;
. . illustrated in Fig. 27(a) (15,16). These are formed by M paral-
1010 leled channels whose operation is multiplexed in time, as il-
1 0111
lustrated in the timing diagram depicted in Fig. 27(b). Each
C channel in a time-interleaved converter can be formed by any
Vin Vin 1 0010 of the types of ADCs previously described. At any given clock

;
1 0000
0 1111 cycle, the input and output multiplexers connect only one
MSBs LBSs FLG ADC channel between the input and output terminals, so that
one converted digital word is delivered at the output and a
1001 A 1001 0011 1 = error new sample of the input signal is taken for conversion. In the

;
next clock cycles the same operation is sequentially repeated
+ 1
with the remaining ADC channels while the first channel car-
ries out the signal conversion; everything should be completed
0 0000
1 1111 1010 0011 final result only after the M channels have been served by the multi-
B plexers. Thus, for a given conversion frequency Fs of the ADCs
the time-interleaved operation allows to achieve an overall
1000
. .
1 1000 conversion frequency of MFs.
. . A variation of the basic time-interleaved ADC architecture
. .
(c) based on a quadrature-mirror filter (QMF) bank is indicated
in Fig. 28 (17). At the input there is an analysis filter bank,
Figure 25. Illustrating the digital error correction technique in an typically realized in switched-capacitor form, whereas the
ADC. output filter bank is a digital network. In this approach the
522 ANALOG-TO-DIGITAL CONVERSION

In
S/H MDAC MDAC MDAC MDAC

FLASH FLASH FLASH FLASH FLASH

3b 3b 3b 3b 4b

Clk
12b Out

Digital error correction logic

(a)

1 2 5 1
Cycle

Stage 1 Sampling and Residue Sampling and Residue Sampling and Residue Sampling and Residue
quantization amplification quantization amplification quantization amplification quantization amplification

Stage 2 Sampling and Residue Sampling and Residue Sampling and Residue Sampling and
quantization amplification quantization amplification quantization amplification (5) quantization
. . . . . . . . .
. . . . . . . . .
. . . . . . . . .

Stage 5 Sampling and Sampling and

quantization quantization

Digital q[x(2)] q[x(2)]

output

5 cycles latency
(b)

Figure 26. (a) Conceptual block diagram of a five-stage pipelined ADC. (b) Illustration of the
timing of the pipe operation and latency of the converter.

input signal is first decomposed into a number of contiguous
frequency bands (subbands) so that a specific ADC (subcon-
verter) can be assigned to each subband signal. Due to the
synthesis filters the linearity performance due to mismatches
among the subconverters is substantially reduced. Similarly,
the jitter problem that arises in the basic time-interleaved
converter due to uneven sample timing, especially for high-
frequency input signals, is also reduced by the filtering and
downconversion stage. Besides, this type of QMF-based con-
verter also incorporates the advantages of subband coding
such that by appropriately specifying the resolution of the
subconverters throughout the respective subbands the quan-
tization noise can be separately controlled in each band, and
the shape of the reconstruction error spectrum can be con-
trolled as a function of the frequency.
Theoretically, the overall resolution of a QMF-based ADC
depends solely on the resolution of the subconverters used. If
successive approximation subconverters are used, then sub-
stantial savings in die area can be obtained when compared
to flash converters.
OVERSAMPLING CONVERTERS
The common characteristic of all the converters already de-
scribed herein concerns the uniform power spectral density of
the quantization noise in the Nyquist band, that is, the fre-
quency range from dc to half the conversion frequency. Hence,
their designation of Nyquist converters. In order to achieve
high SNR, Nyquist converters must have a correspondingly
high conversion resolution, which, in turn, requires very high
matching accuracy from the constituting elements responsible
for the scaling operations in the converter. This can be
achieved without too much difficulty for conversion resolu-
 ANALOG-TO-DIGITAL CONVERSION 523

A/D 1 N @ Fs
in out
@ Fs

A/D 2 N @ Fs
in out
@ Fs

V . . .
N
. . .
. . .
@ MFs @ MFs
A/D M – 1
in out
@ Fs N @ Fs

A/D M N @ Fs
in out
@ Fs

(a)

n MT (n+1)MT t

A/D 1 V(nM) V [(n+1)M ]

n MT+T t

A/D 2 V(nM+1)

. . .
. . .
. . .
n MT+(M–2)T t

A/D M–1 V(nM+M–2)

n MT+(M–1)T t

A/D M V(n M+ M–1)

Ts
Figure 27. (a) Conceptual block diagram
T = Ts / M of a time-interleaved ADC and (b) illus-
(b) tration of its time multiplexed operation.

tions up to about 10-bits. For conversion resolutions above 10-
bits self-calibration techniques should be employed to extend
the matching accuracy of the elements above the inherent ac-
curacy provided by the technology.
Because of the increased difficulty of designing self-cali-
brated converters alternative techniques have been sought to
achieve equivalent high-resolution conversion within the lim-
its of matching accuracy that can be achieved with a given
technology. Such conversion techniques are based on shaping
the quantization noise of an oversampled signal, that is,
where its sampling frequency is much higher than the Ny-
quist frequency, such that the resulting power spectral den-
sity is significantly reduced within the frequency band of in-
terest and increases outside such a band. Hence, the resulting
converters are commonly known as oversampling converters.
The notion of using such artificially high sampling rates
and simple single-bit quantization to represent analog signals
has been of interest ever since the introduction of delta modu-
lation. However, the oversampling technique alone would re-
quire sampling frequencies too high to be of much practical
use. Subsequent developments introduced the methods of
negative feedback, noise shaping and higher-order modula-
tors (18). These improvements allowed the practical imple-
mentation of very high resolution converters at the expense
of an increase in complexity of the digital filters that are
needed to extract the baseband signal from the high speed
bit-stream produced by the modulator (19). Because these can
be implemented rather efficiently by modern CMOS technol-
ogy, oversampling converters have been making inroads in
mixed-signal analog-digital integrated circuits for high per-
formance applications. The sections that follow describe the
basic concepts and most relevant implementation techniques
of oversampling ADCs.
Quantization Noise with Oversampling and Shaping
To reduce the in-band noise power of an oversampled quan-
tized signal beyond the value obtained for the uniform noise
524 ANALOG-TO-DIGITAL CONVERSION

Analysis Down- Up- Synthesis

filter bank samplers samplers filter bank

H0 (z) N ADC N F0 (z)

H1(z) N ADC N F1(z) +

Analog Digital
H2(z) N ADC N F2(z) +
input .. output
.
. . . ..
. . . .
. . .

HN–1(z) N ADC N FN–1(z)

Figure 28. Block diagram of a time-inter-

leaved ADC based on a quadrature-mirror
filter (QMF) bank. Analog Digital

distribution, a specific noise shaping function should be per-
formed, as illustrated in Fig. 29. A portion of the quantization
noise is now pushed into higher frequencies, thereby improv-
ing the equivalent bit-resolution in the signal bandwidth of
interest while keeping the oversampling ratio constant. Such
shaping effect can be obtained by means of the circuit shown
in Fig. 30 for an example in which an integrator is used to
produce a first-order noise shaping. Its operation can be intu-
itively understood from the theory of closed loop systems. Be-
cause in the baseband the integrator has a very large gain,
the overall transfer characteristic is determined by the feed-
back branch and any nonlinearity in the feed-forward branch
is attenuated by the large loop gain. The feedback branch con-
sists of a digital-to-analog converter and the overall resolu-
tion will be determined solely by the linearity of this com-
ponent.
An interesting case is when only two quantization levels
are used, that is, one-bit resolution. This is called a single-bit
first-order sigma-delta (⌺⌬) modulator and is represented by
the circuit diagram shown in Fig. 31. It comprises an inte-
grator for the filter function, a comparator with latch for the
1-bit quantizing function, and a switch to either ⫺Vref or
⫹Vref that realizes the 1-bit digital-to-analog conversion pro-
viding the reconstruction of signal prior to the subtraction
Quantization noise
from the incoming signal at the input of the modulator. Be-
cause of its simplicity and use of 1-bit converters the system
becomes very robust and precise. In particular, the implemen-
tation of the 1-bit DAC renders such a structure inherently
linear, possibly yielding only offset and gain errors. Thus, the
⌺⌬ modulator offers the potential for high resolution conver-
sion without the need for accurate components.
Analysis of First- and Second-Order ⌺⌬ Modulators
Due to the highly nonlinear element in the loop, the exact
analysis of a ⌺⌬ modulator is not simple to do and any form
of analytical solution is too complex to be of much practical
use. Therefore, a simplified linearized model of the modulator
is used in which the comparator is replaced by an additive
noise source. Although this approximation allows prediction
of some important aspects of the modulator behavior, such as
noise level and spectrum, it must be nevertheless carefully
interpreted because it assumes a set of conditions not thor-
oughly satisfied in most applications.
First-Order ⌺⌬ Modulator
Linearized Model. Referring to the circuit in Fig. 31, the
corresponding linearized model of the modulator is repre-
sented in Fig. 32, where the integrator is modeled by a dis-
crete-time function and the quantizer is modeled as a unity
gain block with an additive noise source VQ. It can be readily
obtained that the transfer function for the input signal is
given by

Fs
Baseband
+
Input + Integrator A/D Output
–
Quantization noise shaped

Fs D/A
Baseband

Figure 29. Effect of shaping the quantization noise. Figure 30. Oversampling and noise-shaping modulator.
 ANALOG-TO-DIGITAL CONVERSION 525

Vout (z) 1
S(z) = = z−1 (21)
Vin (z) 1– z –1
Input Output
whereas the transfer function relative to the quantization + + Delay +
–
noise source is given by
Delay VQ
V (z)

Q(z) = out = 1 − z−1 (22) Integrator Quantizer
VQ (z)
Figure 32. Linearized model of the first-order ⌺⌬ modulator.
to yield the frequency response
 
πf
Q( f ) = 2 sin (23) From the preceding expression it is now clear that each oc-
Fs
tave of the oversampling ratio leads to a 9 dB improvement
Thus, while the input is unaffected throughout the modulator of the SNR, which corresponds to an equivalent increase of
processing chain (apart from the delay term), the quantiza- 1.5 bit of the conversion resolution.
tion noise VQ is filtered by a high-pass function with notch One important aspect in the type of oversampling modula-
frequency at dc. tor considered above, and that is not predicted by the approxi-
Signal-to-Noise Ratio. For the circuit considered above with mated linearized model, is the appearance of limit cycles for
the noise related transfer function given by Eq. (23), the total certain input waveforms (20). The reason is that the quanti-
quantization noise power in a frequency band from dc to f c zation noise becomes highly correlated with the input. Then,
can be calculated from the assumption that the quantization noise spectrum is white
is no longer valid. Actually, the quantization noise is concen-
   
 2 trated in discrete frequency bands that, when falling in the
fc
LSB2 1 πf
PQ = 2 sin df (24) baseband, produce noise tones much above the noise level pre-
0 12 Fs /2 Fs
dicted by Eq. (25). This effect can be attenuated by introduc-
ing a high frequency dither signal superimposed on the input
where, as previously indicated, LSB represents the quantizer
signal, thereby creating sufficient disturbance so as to destroy
step size.
the tones. However, the addition of this dither signal reduces
Considering that the signal band of interest is highly
the dynamic range of the modulator and complicates the
oversampled, that is, ( fc /Fs) Ⰶ 1, the total in-band noise power
design.
can be expressed as follows:
   3 Second-Order ⌺⌬ Modulator. By adding another integrator
LSB2 π2 1
PQ = (25) in the forward loop, a stronger reduction of low-frequency
12 3 OSR
quantization noise is possible for the same oversampling ra-
tio. Furthermore, due to the additional integrator the quanti-
as a function of the quantization step and oversampling ratio
zation noise becomes a more complex function of the circuit
of the modulator. Hence, for a sine waveform with maximum
parameters and it is, therefore, less correlated with the input.
peak value of (2N ⫺ 1)(LSB/2) it results in a signal-to-noise
Thus, a second-order modulator will be much less prone to
ratio given by
enter in limit cycle conditions than its first-order counterpart

   and the corresponding noise tone power is very small. In ap-
3 N 3
SNR = 10 log (2 − 1)2 + 10 log OSR 3
(26) plications where the input signal is sufficiently busy so as to
2 π2
completely randomize the quantization noise there is no need
and which, for a 1-bit quantizer (N ⫽ 1), can also be expressed to add a dither signal. Figure 33 shows the schematic dia-
as gram of such a second-order oversampling modulator. The in-
ner second feedback loop has been added to ensure operation
SNR(dB) = 9 log2 (OSR) − 3.41 (27) stability.
Two of the most common implementations of second-order
modulators are represented by their linearized discrete-time
models illustrated in Fig. 34. The first one, represented in
Fs
Fig. 34(a), employs two delay-free integrators whereas the
other one, represented in Fig. 34(b), employs a delayed inte-
Input + Output grator in the first stage and a different coefficient in the inner
+ Integrator Comparator Latch loop. The latter implementation allows more design flexibility
– due to the relaxed timing requirements, and smaller voltage
swings on the integrator outputs (21).
From the linearized models represented in the preceding
+Vref illustration (Fig. 34), it is readily seen that the signal is
merely affected by a delay term corresponding to one clock
–Vref period, in the case of the delay-free integrators, and two clock
periods in the other case. Both forms of implementation pro-
Figure 31. Schematic diagram of the first-order ⌺⌬ modulator. duce the same noise shaping effect determined by a high-pass
526 ANALOG-TO-DIGITAL CONVERSION

Fs

Input Output
+ Integrator + Integrator Comparator Latch
– –

+Vref /2
Figure 33. Schematic diagram of a sec-
ond-order ⌺⌬ modulator with two feed-
–Vref /2
back loops for operation stability.

transfer function expressed as and which for a single-bit quantizer yields

Q(z) = (1 − z−1 )2 (28)

SNR(dB) = 15 log2 (OSR) − 11.14 (31)
yielding the frequency response

 2 Therefore, each doubling of the oversampling ratio provides a
πf 15 dB increase in the SNR, which gives an equivalent resolu-
Q( f ) = 2 sin (29)
Fs tion increase of 2.5 bits.
Figure 36 compares the SNR characteristics obtained for
It can be appreciated that while at low frequencies the quan- oversampling ⌺⌬ modulators with first- and second-order fil-
tization noise will be strongly attenuated due to the second- tering as well as for oversampling modulators with no noise
order noise shaping the high-frequency portion of the spec- shaping function (zero-order). For example, in order to
trum will be substantially amplified, as is illustrated in Fig. achieve an equivalent 12 bit of resolution with a second-order
35. oversampling modulator a signal-to-noise ratio of 74 dB must
Following a similar procedure as for the first-order modu- be obtained. In practical application designs, in order to allow
lator, it can be shown that in both forms of implementation for secondary sources of noise such as thermal noise in the
the resulting quantization noise power at the output, in a fre- input stage and degradation of noise shaping due to imperfect
quency band from dc to f c ⫽ Fs /2OSR, is given by the approxi- components, a margin of approximately 6 dB should be added.
mate expression From Fig. 36 we can see that for obtaining SNR ⫽ 80 dB
 5 such a second-order modulator would need an OSR of only 65,
LSB2 π 4 1
Q∼
= (30) whereas a first-order modulator would required a much
60 OSR higher OSR of 600.

1 1
1 – z–1 1 – z–1
Input Output
+ + + + Delay +
– –

Delay Delay VQ

Integrator-1 Integrator-2 Quantizer

(a)

z–1 1
1 – z–1 1 – z–1
Input Output
+ + Delay + + Delay +
– –

Delay VQ

Integrator-1 Integrator-2 Quantizer

1 2
Figure 34. Linearized equivalent circuits
of second-order ⌺⌬ modulators for two of
the most popular implementations. (b)

16
Spectral density
12
Second order
8
First order
4 Baseband
Quantization noise
0 including an analog modulator and a digital decimator.
0 0.5
Frequency (normalized to Fs = 1)
Figure 35. Shaping functions of the output quantization noise for
the case of first- and second-order ⌺⌬ modulators.
System Aspects of Oversampling ADCs
The general architecture of a complete ADC based on
oversampling techniques is represented in Fig. 37. Besides
the analog modulator clocked at a high (oversampled) fre-
quency, the system includes a digital filter, also clocked at the
oversampling frequency, and an output register clocked at the
lower Nyquist frequency. The combined digital filter and out-
put register with different clock rates perform the so-called
decimation function of the converter, which purpose is to re-
move the high-frequency noise components produced by the
shaping effect of the modulator.
Figure 38 depicts several time-domain waveforms and cor-
responding signal spectra that illustrate the operation of the
complete oversampling ADC. It is assumed that an input sig-
nal band limited from dc to f c Ⰶ Fs is sampled at the high-
frequency clock, as seen in Fig. 38(a). Next, the 1-bit quan-
tized bit stream at the output of the modulator contains basi-
cally the baseband information from dc to f c and a large
amount of out-of-band quantization noise above f c. The corre-
sponding time-domain waveform and frequency spectrum are
depicted in Fig. 38(b). The out-of-band quantization noise is
then removed by means of the digital filter and which, at the
same time, increases the length of the digital signal from 1
bit to the full N-bits resolution of the converter. The resulting
spectrum is shown in Fig. 38(c). Finally, the output sampling
rate is reduced by means of an M-fold down sampler in order
to obtain to the required output conversion frequency and
thus yields the periodic (digital) spectrum illustrated in Fig.
140
Signal-to-noise ratio (dB)
120
100
Second order
80
60
First order
40
20
0 No noise shaping
–20
1 10 100 1000
Oversampling ratio
Figure 36. The SNR characteristics of oversampling modulators
with zero-order (no noise shaping), first-order, and second-order noise
shaping as functions of the oversampling ratio.
ANALOG-TO-DIGITAL CONVERSION 527
High-speed clock Nyquist
clock
Analog Digital
input Analog Digital output
Register
modulator filter
Figure 37. Block diagram of a complete oversampled ADC system,
38(d). This last stage of the processing chain is called deci-
mation.
The design of a complete oversampling ADC based on the
preceding system architecture involves the selection of key
design parameters for both the analog modulator and the dig-
ital decimator, bearing in mind the interaction between them.
For the analog modulator, on the one hand, the parameters
of concern are the order of the filtering function and the num-
ber of quantized bits. On the other hand, the relevant design
parameters for the digital decimator are the oversampling ra-
tio, the word length at both the output of the analog modula-
tor and at the output of the system, and the required level of
attenuation of the out-of-band noise. Next, we shall discuss
more advanced architecture options for designing oversam-
pled ADCs.
Higher-Order Modulators. The oversampling ratio required
to meet a specific level of performance may be decreased be-
low that needed in a first-order ⌺⌬ modulator by increasing
the order of the modulator. Higher-order noise shaping can
be accomplished by including a higher order filter, such as
additional integrators, in the forward path of the modulator.
However, higher-order modulators require careful attention
to the placement of appropriate zeros in the transfer function
of the analog filter (22,23). Moreover, when a higher-order
modulator is driven by a large input, the two level quantizer
is overloaded, causing an increase in the quantization noise.
The increased quantization noise is amplified by the analog
filter, leading to instability in the form of large, uncontrolla-
ble, low-frequency oscillations. Thus, third- and higher-order
modulators based on the use of a single two-level quantizer
are potentially unstable and may require circuitry to reset the
integrators when large signals are detected in the integrator
outputs (24).
Cascaded Modulators. The danger of having saturating
limit cycles in high-order modulators can be avoided by cas-
cading a number of first- and second-order ⌺⌬ modulators to
produce the effect of high-order prediction. One such architec-
ture is represented in Fig. 39 showing a cascade of two first-
order ⌺⌬ modulators. In this arrangement the second modula-
tor takes at the input the quantization error of the first stage
while the outputs of both modulators are combined together.
In the combined output signal the first-stage quantization er-
ror is removed, thus leaving only the error corresponding to
the second modulator stage. The technique can generally be
extended to more than two stages and to both first- and sec-
ond-order modulators.
The forgoing type of cascade architectures, called Multi-
stAge noise SHaping (MASH) gives the advantage of achiev-
528 ANALOG-TO-DIGITAL CONVERSION

Out-of-band components

t
fc Fs/2
(a)

Quantization noise

t
fc Fs/2

(b)

t
fc Fs/2
(c)

t
fc Fs/M Fs/2

(d)

Figure 38. Time-domain waveforms and signal spectra throughout the processing chain of an
oversampling ADC. (a) Sampled input analog signal. (b) Digital bitstream signal. (c) Digitally
filtered signal. (d) Decimated digital signal.

1
First stage
1 – z–1
Input Output
+ + + +
–

Delay VQ1

Integrator-1 Quantizer-1

+
1 –
Second stage
1 – z–1 1– z–1

+ + + +
– –

Delay VQ2 Delay

Figure 39. Second-order noise shaping Integrator-2 Quantizer-2 Differentiator

by cascading two first-order modulators.

MFs 4Fs 2Fs
FIR Filter
FIR FIR
Sinc2
halfband halfband
LPF LPF LPF
Figure 40. A two-stage architecture for designing the digital decima-
tor using only FIR filter sections.
ing high-order noise shaping functions using inherently sta-
ble modulator stages (25–28). Rather than regarding the
MASH architecture as a method of obtaining high-order cir-
cuits, it is usually more correct to regard it as a means of
enhancing the performance of the first modulator in the cas-
cade. For example, a modulator composed of a second-order
sigma-delta circuit followed by a first-order circuit has attrac-
tive properties. Unfortunately, however, these modulators are
sensitive to the opamp finite dc gain as well as to mismatches
among the circuit parameter values. Their resolution is usu-
ally determined by how well individual modulators are
matched. Specifically, in switched-capacitor implementations,
cascaded modulators require close capacitance matching, high
opamp dc gain, and nearly complete settling of the integra-
tor outputs.
Despite their attractive features, which allow lower
oversampling ratios and, therefore, higher conversion rate for
a given modulator operating speed, sophisticated modulator
architectures such as the ones discussed above do not neces-
sarily ease the performance required on the overall circuit.
For example, a larger percentage of the thermal noise intro-
duced by the sampling switches in switched capacitor inte-
grators falls in the baseband. To maintain the dynamic range,
the capacitors must be increased accordingly. This implies
proportionally higher-load capacitances on the operational
amplifiers in the integrators. Also, the complexity of the anti-
aliasing filter that precedes the modulator and the decimator
filter following it are increased. Their attenuation specifica-
tions are tighter because the sampling rate is lower with re-
spect to the baseband.
N-Bit Quantizer. As previously discussed, the advantage of
single-bit modulators is that the linearity of the feedback
DAC is inherently ideal, besides being extremely simple for
implementation. Single-bit modulators, however, also have
the disadvantage of a large amount of quantization noise,
which may easily cause saturation and lead to potential insta-
bility conditions. Multibit quantizers, by contrast, generally
provide improved stability conditions of the ⌺⌬ modulators,
Fs Fs Fs
+ z–1 + z–1 + z–1
1 (1 – z–M )3
(1 – z–1)3
Figure 41. Typical architecture of a third-order Sinc filter for digital decimation.
ANALOG-TO-DIGITAL CONVERSION 529
Fs especially in the case of higher order modulators, as well as
minimization of the occurrence of idle tones. However, modu-
lators based on a quantizer with more than two levels place
stringent linearity demands on the DAC in the feedback loop
and generally require sophisticated linearization techniques
(29–32).
Decimation Filter. The output of the modulator represents
the input signal together with its spurious out-of-band compo-
nents, quantization noise, and noise or interference that may
have entered the analog circuits. As already discussed, the
digital filter in the general architecture of Fig. 36 serves to
attenuate all out-of-band energy, so that the signal may be
resampled at the Nyquist rate without being corrupted with
the folded-back components of the high frequency noise.
Fairly simple digital filters would suffice to remove only
quantization noise because it rises slowly, for example at 12
dB per octave for the case of a second-order modulation. By
contrast, highly selective filters are usually needed to remove
the out-of-band components of the input. Such filters are
rather expensive when operated at high sample rates. There-
fore, in practice, the decimator filter is usually implemented
in two stages, as seen in Fig. 40. First, there is a decimator
with output at four times the Nyquist rate and which is de-
signed predominantly to remove the quantization noise com-
ponent that is dominant at high frequencies. The second-
stage filter resamples the signal at the Nyquist rate and
defines the baseband cut-off characteristics. Typically this is
the most complex and larger circuit and should be carefully
designed to suit the application.
A convenient filter for the first stage of decimation is based
on the Sinc function expressed as
 k
1 1 − z−M
Sinck = (32)
M 1 − z−1
where M is the decimation factor and k is the order of the
filter. This filter is very easy to implement as it requires no
multipliers. It has the advantage of having zeros at the multi-
ples of the output sample frequency, which remove the noise
components that would otherwise be aliased into the base-
band with the decimation operation (33–35). The order of this
filter should be equal to the modulator order plus one in order
to suppress the high frequency quantization noise adequately.
Eventually, the order of the decimating filter can be made
equal to that of the modulator, in order to reduce the imple-
mentation complexity. However, this results in some degrada-
tion of the overall signal-to-noise ratio. A typical architecture
for the implementation of a third-order Sinc filter is illus-
trated in Fig. 41.
Fs/M Fs/M Fs/M
z–1 + z–1 + z–1 +
Fs/M
530 ANALOG-TO-DIGITAL CONVERSION
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23. D. R. Welland et al., A stereo 16-bit delta-sigma A/D converter
for digital audio, J. Audio Eng. Soc., 37 (6): 476–486, 1989.
24. S. Mohsen Moussavi and B. H. Leung, High-order single-stage
single-bit oversampling A/D converter stabilized with local feed-
back loops, IEEE Trans. Circuits Syst.-II: Analog Digital Signal
Process., 41: 19–25, 1994.
25. Y. Matsuya et al., A 16-bit oversampling A-to-D conversion tech-
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JOSÉ EPIFÂNIO DA FRANCA
CARLOS AZEREDO LEME
JOÃO CALADO VITAL
Instituto Superior Técnico
ANALYSIS AND DESIGN ALGORITHMS FOR CON-
TROL SYSTEMS. See SOFTWARE FOR CONTROL SYSTEM
ANALYSIS AND DESIGN, SINGULAR VALUE DECOMPOSITION.
ANALYSIS, CEPSTRAL OF SPEECH. See CEPSTRAL
ANALYSIS OF SPEECH.
ANALYSIS, COST. See COST ANALYSIS.
ANALYSIS, COST-BENEFIT. See COST-BENEFIT ANALYSIS.
ANALYSIS, INTERVAL, FOR CIRCUITS. See INTERVAL
ANALYSIS FOR CIRCUITS.
ANALYSIS, NETWORK. See NETWORK ANALYSIS USING
LINEARIZATION.
ANALYSIS, OF CIRCUITS IN THE FREQUENCY DO-
MAIN. See FREQUENCY-DOMAIN CIRCUIT ANALYSIS.
ANALYSIS OF FAILURE MODES AND EFFECTS.
See FAILURE MODES AND EFFECTS ANALYSIS.
 ANTENNA ACCESSORIES 531

ANALYSIS OF MICROWAVE AND MILLIMETER-

WAVE STRUCTURES. See SPECTRAL-DOMAIN ANALYSIS.
ANALYSIS OF RELIABILITY DATA. See STATISTICAL
ANALYSIS OF RELIABILITY DATA.
ANALYSIS, QUALITATIVE OR DYNAMIC CIR-
CUITS. See QUALITATIVE ANALYSIS OF DYNAMIC CIRCUITS.
ANALYSIS, SENSITIVITY. See SENSITIVITY ANALYSIS.
ANALYSIS, SPEECH. See SPEECH ANALYSIS; SPEECH
PROCESSING
ANALYSIS, SYSTEMS. See SYSTEMS ANALYSIS.
ANALYSIS, TRANSIENT. See TRANSIENT ANALYSIS.
ANALYZER, POWER SYSTEM. See POWER SYSTEM MEA-
SUREMENT.
ANIMATION, COMPUTER. See COMPUTER ANIMATION.
ANNUNCIATORS. See ALARM SYSTEMS.
716 ASYNCHRONOUS CIRCUITS

ASYNCHRONOUS CIRCUITS

Digital Very Large Scale Integration (VLSI) circuits are usu-

ally classified into synchronous and asynchronous circuits.
Synchronous circuits are generally controlled by global syn-
chronization signals provided by a clock. Asynchronous cir-
cuits, on the other hand, do not use such global synchroniza-
tion signals. Between these extremes there are various
hybrids. Digital circuits in today’s commercial products are
almost exclusively synchronous. Despite this big difference in
popularity, there are a number of reasons why asynchronous
circuits are of interest.
In this article, we present a brief overview of asynchronous
circuits. First we address some of the motivations for design-
ing asynchronous circuits. Then, we discuss different classes
of asynchronous circuits and briefly explain some asynchro-
nous design methodologies. Finally, we present an asynchro-
nous design in detail.

MOTIVATIONS FOR ASYNCHRONOUS CIRCUITS

Throughout the years researchers have had a number of rea-

sons for studying and building asynchronous circuits. Some of
the often mentioned advantages of asynchronous circuits are
speed, low energy dissipation, modular design, immunity to
metastable behavior, freedom from clock skew, and low gener-
ation of and low susceptibility to electromagnetic interfer-
ence. We elaborate here on some of these potentials and indi-
cate when they have been demonstrated through comparative
case studies.

Speed
Speed has always been a motivation for designing asynchro-
nous circuits. The main reasoning behind this advantage is
that synchronous circuits exhibit worst-case behavior,
whereas asynchronous circuits exhibit average-case behavior.
The speed of a synchronous circuit is governed by its clock
frequency. The clock period should be large enough to accom-
modate the worst-case propagation delay in the critical path
of the circuit, the maximum clock skew, and a safety factor
due to fluctuations in the chip fabrication process, operating
temperature, and supply voltage. Thus, synchronous circuits
exhibit worst-case performance, in spite of the fact that the
worst-case propagation in many circuits, particularly arith-
metic units, may be much longer than the average-case prop-
agation.
Many asynchronous circuits are controlled by local commu-
nications and are based on the principle of initiating a compu-
tation, waiting for its completion, and then initiating the next
one. When a computation has completed early, the next com-
putation can start early. For this reason, the speed of asyn-
chronous circuits equipped with completion-detection mecha-
nisms depend on the computation time of the data being
processed, not the worst-case timing. Accordingly, such asyn-
chronous circuits exhibit average-case performance. An exam-
ple of an asynchronous circuit where the average-case poten-
tial is nicely exploited is reported in (1), an asynchronous
divider that is twice as fast as its synchronous counterpart.
Nevertheless, to date, there are few concrete examples dem-
onstrating that the average-case performance of asynchro-
nous circuits is higher than that of synchronous circuits per-

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

forming similar functions. The reason is that the average-case
performance advantage is often counterbalanced by the over-
head in control circuitry and completion-detection mecha-
nisms.
Besides demonstrating the average-case potential, there
are case studies in which the speed of an asynchronous design
is compared to the speed of a corresponding synchronous ver-
sion. Molnar et al. report a case study (2) of an asynchronous
FIFO that is every bit as fast as any synchronous FIFO using
the same data latches. Furthermore, the asynchronous FIFO
has the additional benefit that it operates under local control
and is easily expandable. At the end of this article, we give
an example of a FIFO with a different control circuit.
Immunity to Metastable Behavior
Any circuit with a number of stable states also has metasta-
ble states. When such a circuit gets into a metastable state,
it can remain there for an indefinite period of time before re-
solving into a stable state (3,4). Metastable behavior occurs,
for example, in circuit primitives that realize mutual exclu-
sion between processes, called arbiters, and components that
synchronize independent signals of a system, called synchro-
nizers. Although the probability that metastable behavior
lasts longer than period t decreases exponentially with t, it is
possible that metastable behavior in a synchronous circuit
lasts longer than one clock period. Consequently, when meta-
stable behavior occurs in a synchronous circuit, erroneous
data may be sampled at the time of the clock pulses. An asyn-
chronous circuit deals gracefully with metastable behavior by
simply delaying the computation until the metastable behav-
ior has disappeared and the element has resolved into a sta-
ble state.
Modularity
Modularity in design is an advantage exploited by many asyn-
chronous design styles. The basic idea is that an asynchro-
nous system is composed of functional modules communicat-
ing along well-defined interfaces. Composing asynchronous
systems is simply a matter of connecting the proper modules
with matching interfacial specifications. The interfacial speci-
fications describe only the sequences of events that can take
place and do not specify any restrictions on the timing of
these events. This characteristic reduces the design time and
complexity of an asynchronous circuit, because the designer
does not have to worry about the delays incurred in individual
modules or the delays inserted by connection wires. Designers
of synchronous circuits, on the other hand, often pay consider-
able attention to satisfying the detailed interfacial timing
specifications.
Besides ease of composability, modular design also has the
potential for better technology migration, ease of incremental
improvement, and reuse of modules (5). Here the idea is that
an asynchronous system adapts itself more easily to advances
in technology. The obsolete parts of an asynchronous system
can be replaced with new parts to improve system perfor-
mance. Synchronous systems cannot take advantage of new
parts as easily, because they must be operated with the old
clock frequency or other modules must be redesigned to oper-
ate at the new clock frequency.
One of the earliest projects that exploited modularity in
designing asynchronous circuits is the Macromodules project
ASYNCHRONOUS CIRCUITS 717
(6). Another example where modular design is demonstrated
is the TANGRAM compiler developed at Philips Research
Laboratories (7).
Low Power
Due to rapid growth in the use of portable equipment and the
trend in high-performance processors towards unmanageable
power dissipation, energy efficiency has become crucial in
VLSI design. Asynchronous circuits are attractive for energy-
efficient designs, mainly because the clock is eliminated. In
systems with a global clock, all of the latches and registers
operate and consume dynamic energy during each clock pulse,
in spite of the fact that many of these latches and registers
may not have new data to store. There is no such waste of
energy in asynchronous circuits, because computations are
initiated only when necessary.
Two notable examples that demonstrated the potential of
asynchronous circuits in energy-efficient design are the work
done at Philips Research Laboratories and at Manchester
University. The Philips group designed a fully asynchronous
digital compact-cassette (DCC) error detector which con-
sumed 80% less energy than a similar synchronous version
(8). The AMULET group at Manchester University success-
fully implemented an asynchronous version of the ARM mi-
croprocessor, one of the most energy-efficient synchronous mi-
croprocessors. The asynchronous version achieved a power
dissipation comparable to the fourth generation of ARM,
around 150 mW (9), in a similar technology.
Recently, power management techniques are being used in
synchronous systems to turn the clock on and off condition-
ally. However, these techniques are only worthwhile imple-
menting at the level of functional units or higher. Besides,
the components that monitor the environment for switching
the clock continue dissipating energy.
It is also worth mentioning that, unlike synchronous cir-
cuits, most asynchronous circuits do not waste energy on haz-
ards, which are spurious changes in a signal. Asynchronous
circuits are essentially designed to be hazard-free. Hazards
can be responsible for up to 40% of energy loss in synchronous
circuits (10).
Freedom from Clock Skew
Because asynchronous circuits generally do not have clocks
they do not have many of the problems associated with clocks.
One such problem is clock skew, the technical term for the
maximum difference in clock arrival time at different parts of
a circuit. In synchronous circuits, it is crucial that all modules
operating with a common clock receive this signal simultane-
ously, that is, within a tolerable period of time. Minimizing
clock skew is a difficult problem for large circuits. Various
techniques have been proposed to control clock skew, but gen-
erally they are expensive in terms of silicon area and energy
dissipation. For instance, the clock distribution network of
the DEC Alpha, a 200 MHz microprocessor at a 3.3 V supply,
occupies 10% of the chip area and uses 40% of the total chip
power consumption (11). Although asynchronous circuits do
not have clock skew problems, they have their own set of
problems in minimizing the overhead needed for synchroniza-
tion among the parts.
718 ASYNCHRONOUS CIRCUITS
MODELS AND METHODOLOGIES
There are many models and methodologies for analyzing and
designing asynchronous circuits. Asynchronous circuits can
be categorized by the following criteria: signaling protocol and
data encoding, underlying delay model, mode of operation,
and formalism for specifying and designing circuits. This sec-
tion presents an informal explanation of these criteria.
Signaling Protocols and Data Encodings
Modules in an asynchronous circuit communicate data with
some signaling protocol consisting of request and acknowledg-
ment signals. There are two common signaling protocols for
communicating data between a sender and a receiver, the
four-phase and the two-phase protocol. In addition to the sig-
naling protocol, there are different ways to encode data. The
most common encodings are single-rail and dual-rail encod-
ing. We explain the two signaling protocols first and then dis-
cuss the data encodings.
If the sender and receiver communicate through a two-
phase signaling protocol, then each communication cycle has
two distinct phases. The first phase consists of a request initi-
ated by the sender. The second phase consists of an acknowl-
edgment by the receiver. The request and acknowledgment
signals are often implemented by voltage transitions on sepa-
rate wires. No distinction is made between the directions of
voltage transitions. Both rising and falling transitions denote
a signaling event.
The four-phase signaling protocol consists of four phases, a
request followed by an acknowledgment, followed by a second
request, and finally a second acknowledgment. If the request
and acknowledgment are implemented by voltage transitions,
then at the end of every four phases, the signaling wires re-
turn to the same voltage levels as at the start of the four
phases. Because the initial voltage is usually zero, this type
of signaling is also called return-to-zero signaling. Other
names for two-phase and four-phase signaling are two-cycle
and four-cycle signaling, respectively, or transition and level
signaling, respectively.
Both signaling protocols are used with single and dual-rail
data encodings. In single-rail data encoding each bit is en-
coded with one wire, whereas in dual-rail encoding, each bit
is encoded with two wires.
In single-rail encoding, the value of the bit is represented
by the voltage on the data wire. When communicating n data
bits with a single-rail encoding during periods where the data
wires are guaranteed to remain stable, we say that the data
are valid. During periods where the data wires are possibly
changing, we say the data are invalid. A two-phase or four-
phase signaling protocol is used to tell the receiver when data
are valid or invalid. The sender informs the receiver about
the validity of the data through the request signal, and the
receiver, in turn, informs the sender of the receipt of the data
through the acknowledgment signal. Therefore, to communi-
cate n bits of data, a total number of (n ⫹ 2) wires are neces-
sary between the sender and the receiver. The connection pat-
tern for single-rail encoding and two or four-phase signaling
is depicted in Fig. 1(a).
Figure 2(a) shows the sequence of events in a two-phase
signaling protocol. The events include the times when the
data become valid and invalid. The transparent bars indicate
the periods when data are valid. During the other periods,
Request
R R
S e S e
e
n c e
2n c
n e n e
Data Data
d i d i
e v e v
r e r e
r r
Acknowledge Acknowledge
(a) Bundled data convention (b) Dual-rail data encoding
Figure 1. Two different data communication schemes.
data are invalid. Notice that a request signal occurs only after
data become valid. This is an important timing restriction as-
sociated with these communication protocols, namely, the re-
quest signal that indicates that data are valid should always
arrive at the receiver after all data wires have attained their
proper value. The restriction is referred to as the bundling
constraint. For this reason the communication protocol is of-
ten called the bundled data protocol. Figure 2(b) shows a se-
quence of events in a four-phase protocol and single-rail data
encoding. Other sequences are also applicable for the four-
phase protocol.
The dual-rail encoding scheme uses two wires for every
data bit. There are several dual-rail encoding schemes. All
combine the data encoding and signaling protocol. There is no
explicit request signal, and the dual-rail encoding schemes all
require (2n ⫹ 1) wires as illustrated in Fig. 1(b). In four-phase
signaling, there are several encodings that are used to trans-
mit a data bit. The most common encoding has the following
meaning for the four states in which each pair of wires can
be, 00 ⫽ reset, 10 ⫽ valid 0, 01 ⫽ valid 1, and 11 is an unused
state. Every pair of wires has to go through the reset state
before becoming valid again. In the first phase of the four-
phase signaling protocol, every pair of wires leaves the reset
state for a valid 0 or 1 state. The receiver detects the arrival
of a new set of valid data when all pairs of wires have left the
reset state. This detection replaces an explicit request signal.
The second phase consists of an acknowledgment to inform
the sender that data has been consumed. The third phase con-
sists of the reset of all pairs of wires to the reset state, and
the fourth phase is the reset of the acknowledgment.
In a two-phase signaling protocol, a different dual-rail en-
coding is used. An example of an encoding is as follows. Each
pair of wires has one wire associated with a 0 and one wire
associated with a 1. A transition on the wire associated with
0 represents the communication of a 0, whereas a transition
on the other wire represents a communication of a 1. Thus, a
transition on one wire of each pair signals the arrival of a
new bit value. A transition on both wires is not allowed. In
the first phase of the two-phase signaling protocol every pair
of wires communicates a 0 or a 1. The second phase is an
acknowledgment sent by the receiver.
Of all data encodings and signaling protocols, the most
popular are the single-rail encoding and four-phase signaling
protocol. The main advantages of these protocols are the
small number of connecting wires and the simplicity of the
encoding, which allows using conventional techniques for im-
plementing data operations. The disadvantage of these proto-
cols are the bundling constraints that must be satisfied and
the extra energy and time wasted in the additional two
phases compared with two-phase signaling. Dual-rail data en-

Request
Data
Acknowledge
One cycle
(a)
Figure 2. Data transfer in (a) two-phase signaling and (b) four-phase signaling.
codings are used to communicate data in asynchronous cir-
cuits free of any timing constraints. Dual-rail encodings, how-
ever, are expensive in practice, because of the many
interconnecting wires, the extra circuitry to detect completion
of a transfer, and the difficulty in data processing.
Delay Models
An important characteristic distinguishing different asyn-
chronous circuit styles is the delay model on which they are
based. For each circuit primitive, gate or wire, a delay model
stipulates the sort of delay it imposes and the range of the
delays. Delay models are needed to analyze all possible be-
havior of a circuit for various correctness conditions, like the
absence of hazards.
A circuit is composed of gates and interconnecting wires,
all of which impose delays on the signals propagating through
them. The delay models are categorized into two classes, pure
delay models and inertial delay models. In a pure delay
model, the delay associated with a circuit component pro-
duces only a time shift in the voltage transitions. In reality,
a circuit component may shift the signals and also filter out
pulses of small width. Such a delay model is called an inertial
delay model. Both classes of delay models have several ranges
for the delay shifts. We distinguish the zero-delay, fixed-delay,
bounded-delay, and unbounded-delay models. In the zero-de-
lay model, the values of the delays are zero. In the fixed-delay
model, the values of the delays are constant, whereas in the
bounded-delay model the values of the delays vary within a
bounded range. The unbounded-delay model does not impose
any restriction on the value of the delays except that they
cannot be infinite. Sometimes two different delay models are
assumed for the wires and the gates in an asynchronous cir-
cuit. For example, the operation of a class of asynchronous
circuits is based on the zero-delay model for wires and the
unbounded-delay model for gates. Formal definitions of the
various delay models are given in (12).
A concept closely related to the delay model of a circuit is
its mode of operation. The mode of operation characterizes the
interaction between a circuit and its environment. Classical
asynchronous circuits operate in the fundamental mode
(13,14), which assumes that the environment changes only
one input signal and waits until the circuit reaches a stable
state. Then the environment is allowed to apply the next
change to one of the input signals. Many modern asynchro-
nous circuits operate in the input-output mode. In contrast to
the fundamental mode, the input-output mode allows input
ASYNCHRONOUS CIRCUITS 719
Request
Data
Acknowledge
One cycle
(b)
changes immediately after receiving an appropriate response
to a previous input change, even if the entire circuit has not
yet stabilized. The fundamental mode was introduced in the
1960s to simplify analyzing and designing gate circuits with
Boolean algebra. The input-output mode evolved in the eight-
ies from event-based formalisms to describe modular design
methods that abstracted from the internal operation of a
circuit.
Formalisms
Just as in any other design discipline, designers of asynchro-
nous circuits use various formalisms to master the complexi-
ties in designing and analyzing their artifacts. The formal-
isms used in asynchronous circuit design are categorized into
two classes, formalisms based on Boolean algebra and formal-
isms based on sequences of events. Most design methodolo-
gies in asynchronous circuits use some mixture of both for-
malisms.
The design of many asynchronous circuits is based on Bool-
ean algebra or its derivative switching theory. Such circuits
often use the fundamental mode of operation, the bounded-
delay model, and have, as primitive elements, gates that cor-
respond to the basic logic functions, like AND, OR, and inver-
sion. These formalisms are convenient for implementing logic
functions, analyzing circuits for the presence of hazards, and
synthesizing fundamental-mode circuits (12,14).
Event-based formalisms deal with sequences of events
rather than binary logic variables. Circuits designed with an
event-based formalism operate in the input-output mode, un-
der an unbounded-delay model, and have, as primitive ele-
ments, the JOIN, the TOGGLE, and the MERGE, for example.
Event-based formalisms are particularly convenient for de-
signing asynchronous circuits when a high degree of concur-
rency is involved. Several tools have been generated for auto-
matically verifying asynchronous circuits with event-based
formalisms (15,16). Examples of event-based formalisms are
trace theory (17–19), DI algebra (20), Petri nets, and signal
transition graphs (21,22).
DESIGN TECHNIQUES
This section introduces the most popular types of asynchro-
nous circuits and briefly describes some of their design tech-
niques.
720 ASYNCHRONOUS CIRCUITS
TYPES OF ASYNCHRONOUS CIRCUITS
There are special types of asynchronous circuits for which for-
mal and informal specifications have been given. Here are
brief informal descriptions of some of them in a historical
context.
There are two types of logic circuits, combinational and se-
quential. The output of a combinational circuit depends only
on the current inputs, whereas the output of a sequential cir-
cuit depends on the previous sequence of inputs. With this
definition of a sequential circuit, almost all asynchronous cir-
cuit styles fall into this category. However, the term asyn-
chronous-sequential circuits or machines generally refers to
those asynchronous circuits based on finite-state machines
similar to those in synchronous sequential circuits (14,23).
Muller was the first to rigorously formalize a special type
of circuit for which he coined the name speed-independent cir-
cuit. An account of this formalization is given in (24,25). In-
formally, a speed-independent circuit is a network of gates
that satisfies its specification irrespective of any gate delays.
From a design discipline that was developed as part of the
Macromodules project (6) at Washington University in St.
Louis, the concept of another type of asynchronous circuits
evolved, which was given the name delay-insensitive circuit,
that is, a network of modules that satisfies its specification
irrespective of any element and wire delays. It was realized
that proper formalization of this concept was needed to spec-
ify and design such circuits in a well-defined manner. Such a
formalization was given by Udding (26).
Another name frequently used in designing asynchronous
circuits is self-timed systems. This name was introduced by
Seitz (27). A self-timed system is described recursively as ei-
ther a self-timed element or a legal connection of self-timed
systems. The idea is that self-timed elements can be imple-
mented with their own timing discipline, and some may even
have synchronous implementations. In other words, the ele-
ments ‘‘keep time to themselves.’’ In composing self-timed sys-
tems from self-timed elements, however, no reference to the
timing of events is made. Only the sequence of events is rel-
evant.
Some have found that the unbounded gate-and-wire delay
assumption, on which the concept of a delay-insensitive cir-
cuit is based, is too restrictive in practice. For example, the
unbounded gate-and-wire delay assumption implies that a
signal sent to multiple recipients by a fork incurs a different
unbounded delay for each of the recipients. In (28) it is pro-
posed to relax this delay assumption slightly by using iso-
chronic forks. An isochronic fork is a fork whose difference in
the delays of its branches is negligible compared with the de-
lays in the element to which it is connected. A delay-insensi-
tive circuit that uses isochronic forks is called a quasi-delay-
insensitive circuit (17,28). Although isochronic forks give more
design freedom in exchange for less delay insensitivity, care
has to be taken with their implementation (29).
Asynchronous-Sequential Machines
The design of asynchronous-sequential, finite-state machines
was initiated with the pioneering work of Huffman (23). He
proposed a structure similar to that of synchronous-sequen-
tial circuits consisting of a combinational logic circuit, inputs,
outputs, and state variables (14). Huffman circuits, however,
store the state variables in feedback loops containing delay
elements, instead of in latches or flip-flops, as synchronous-
sequential circuits do. The design procedure begins with cre-
ating a flow table and reducing it through some state mini-
mization technique. After a state assignment, the procedure
obtains the Boolean expressions and implements them in
combinational logic with the aid of a logic minimization pro-
gram. To guarantee a hazard-free operation, Huffman circuits
adopt the restrictive single-input-change fundamental mode,
that is, the environment changes only one input and waits
until the circuit becomes stable before changing another in-
put. This requirement substantially degrades the circuit per-
formance. Hollaar realized this fact and introduced a new
structure in which the fundamental mode assumption is re-
laxed (30). In his implementation, the state variables are
stored in NAND latches, so that inputs are allowed to change
earlier than the fundamental mode allows. Although Hol-
laar’s method improves the performance, it suffers from the
danger of producing hazards. Besides, neither technique is
adequate for designing concurrent systems. Models and algo-
rithms for analyzing asynchronous-sequential circuits have
been developed by Brzozowski and Seger (12).
The quest for more concurrency, better performance, and
hazard-free operation, resulted in the formulation of a new
generation of asynchronous-sequential circuits known as
burst-mode machines (31,32). A burst-mode circuit does not
react until the environment performs a number of input
changes called an input burst. The environment, in turn, is
not allowed to introduce the next input burst until the circuit
produces a number of outputs called an output burst. A state
graph is used to specify the transitions caused by the input
and output bursts. Two synthesis methods have been pro-
posed and automated for implementing burst-mode circuits.
The first method employs a locally generated clock to avoid
some hazards (33). The second method uses three-dimen-
sional flow tables and is based on Huffman circuits (34). One
limitation of burst mode circuits is that they restrict concur-
rency within a burst.
Speed-Independent Circuits and STG Synthesis
Speed-independent circuits are usually designed by a form of
Petri nets (35). A popular version of Petri nets, signal-transi-
tion graphs (STG), was introduced by Chu. He also developed
a synthesis technique for transforming STGs into speed-inde-
pendent circuits (21). Chu’s work was extended by Meng, who
produced an STG-based tool for synthesizing speed-indepen-
dent circuits from high-level specifications (36). In this tech-
nique, a circuit is composed of computational and intercon-
necting blocks. Computational blocks range from a simple
shifter module to more complicated ones, such as ALUs,
RAMs, and ROMs. Interconnecting blocks synchronize the
operation of computational blocks by producing appropriate
control signals. Computational blocks generate completion
signals after their output data becomes valid. The intercon-
necting blocks use the completion signals to generate four-
phase handshake protocols.
Delay-Insensitive Circuits and Compilation
Several researchers have proposed techniques for designing
delay-insensitive circuits. Ebergen (37) has developed a syn-
thesis method based on the formalism of trace theory. The
 ASYNCHRONOUS CIRCUITS 721

WIRE a b The simplest primitive is the WIRE, a two-terminal element

that produces an output event on its output terminal b after
IWIRE a b every input event on its input terminal a. Input and output
events in a WIRE must alternate. An input event a must be
a followed by an output event b before another event a occurs.
JOIN c A WIRE is physically realizable with a wire, and events are
b implemented by voltage transitions. An initialized WIRE, or
IWIRE, is very similar to a WIRE, except that it starts by pro-
a ducing an output event b instead of accepting an input event
MERGE M c
b a. After this, its behavior exactly resembles that of a WIRE.
The primitive for synchronization is the JOIN, also called
the RENDEZVOUS (6). A JOIN has two inputs a and b and one
b output c. The JOIN performs the AND operation of two events
TOGGLE a
c a and b. It produces an output event c only after both of its
inputs, a and b, receive an event. The inputs can change
Figure 3. Some primitives in event-based designs.
again after an output is produced. A JOIN can be implemented
by a Muller C-element, explained in the next section.
The MERGE component performs the OR operation of two
method consists of specifying a component by a program and events. If a MERGE component receives an event on either of
then transforming this program into a delay-insensitive net- its inputs, a or b, it produces an output event c. After an input
work of basic elements (18). event, there must be an output event. Successive input events
Martin proposes a method (28) that starts with the speci- are not allowed. A MERGE is implemented by a XOR gate.
fication of an asynchronous circuit in a high-level program- The TOGGLE has a single input a and two outputs b and c.
ming language similar to Hoare’s Communicating Sequential After an event on input a, an event occurs on output b. The
Processes (CSP) (38). An asynchronous circuit is specified as next event on a results in a transition on output c. An input
a group of processes communicating over channels. After vari- event must be followed by an output event before another in-
ous transformations, the program is mapped into a network put event can occur. Thus, output events alternate or toggle
of gates. This method led to the design of an asynchronous after each input event. The dot in the TOGGLE schematic indi-
microprocessor (39) in 1989. Martin’s method yields quasi- cates the output which produces the first event.
delay-insensitive circuits.
Van Berkel (17) designed a compiler based on a high-level The Muller C-Element
language called Tangram. A Tangram program also specifies
a set of processes communicating over channels. A Tangram The Muller C-element is named for its inventor D. E. Muller
program is first translated into a handshake circuit. Then (24). Traditionally, its logical behavior is described as follows.
these handshake circuits are mapped into various target ar- If both inputs are 0 (1), then the output becomes 0 (1). Other-
chitectures, depending on the data-encoding techniques or wise the output remains the same. For the proper operation
standard-cell libraries used. The translation is syntax-di- of the C-element, it is also assumed that, once both inputs
rected, which means that every operation occurring in a Tan- become 0 (1), they do not change again until the output
gram program corresponds to a primitive in the translated changes. A state diagram is given in Figure 4. The behavior
handshake circuit. This property is exploited by various tools of the output c of the C-element is expressed in terms of the
that quickly estimate the area, performance, and energy dis- inputs a and b and the previous state of the output ĉ by the
sipation of the final design by analyzing the Tangram pro- following Boolean function:
gram. Van Berkel’s method also yields quasi-delay-insensi-
c = [ĉ · (a + b)] + (a · b) (1)
tive circuits.
Other translation methods from a CSP-like language to a
The C-element is used to implement the JOIN, which has a
(quasi-) delay-insensitive circuit are in (40,41).
slightly more restrictive environment behavior in the sense
that an input is not allowed to change twice in succession. A
AN ASYNCHRONOUS DESIGN EXAMPLE

In this section we present a typical asynchronous design, a

100 011
micropipeline (5). The circuit uses single-rail encoding with
a b a b
the two-phase signaling protocol to communicate data be-
tween stages of the pipeline. The control circuit for the pipe- c
000 110 111 001
line is a delay-insensitive circuit. First we present the primi-
tives for the control circuit, then we present the latches that b a b a
store the data, and finally we present the complete design.
010 101

The Control Primitives

Figure 3 shows a few simple primitives used in event-based (c)
design styles. The schematic symbol for each primitive is de-
picted opposite its name. Figure 4. State diagram of the C-element.
722 ASYNCHRONOUS CIRCUITS

VDD
VDD

a P1 P3 b
c
a P3 P4 b
a P1
P6 P5
b P2 P5 b P2 P4 a P6

c’ c c’ c

b N2 N5 b N2 N4 a N6
N6 N5
a N1
b N3 N4 a
c
a N1 N3 b

(a) (b)

Figure 5. Two CMOS implementations of the C-element: (a) conventional and (b) symmetric.

state graph for the JOIN is produced by replacing the bidirec-
tional arcs by unidirectional arcs.
There are many implementations of the C-element. We
have given two popular CMOS implementations in Figure 5.
Implementation (a) is a conventional pull-up, pull-down im-
plementation suggested by Sutherland (5). Implementation
(b) is suggested by Van Berkel (29). Each implementation has
its own characteristics. Implementation (b) is the best choice
for speed and energy efficiency (42). There are many varia-
tions of the C-element and other elements that are convenient
for the design of asynchronous circuits. For some of these
variations and their uses, in particular the asymmetric C-ele-
ment, see Ref. 28.
Storage Primitives
Two event-controlled latches due to Sutherland (5) are de-
picted in Figure 6. Their operation is managed through two
input control signals, capture and pass, labeled c and p, re-
spectively. They also have two output control signals, capture
done, cd, and pass done, pd. The input data is labeled D, and
the output data is labeled Q. Implementation (a) is composed
of three so-called double-throw switches. Implementation (b)
includes a MERGE, a TOGGLE, and a level-controlled latch con-
sisting of a double-throw switch and an inverter.
A double-throw switch is schematically represented by an
inverter and a switching tail. The tail toggles between two
positions based on the logic value of a controlling signal. A
double-throw switch, in fact, is a two-input multiplexer that
produces an inverted version of its selected input. A CMOS
implementation of the double-throw switch is shown in Fig-
ure 7 (5). The position of the switch corresponds to the state
where c is low.
An event-controlled latch can assume two states, transpar-
ent and opaque. In the transparent state no data is latched,
but the output replicates the input, because a path of two
inverting stages exists between the input and the output. In
the opaque state, this path is disconnected so that the input
data may change without affecting the output. The current
data at the output, however, is latched. Implementations in
Figs. 6(a) and 6(b) are both shown in their initial transparent
states. The capture and pass signals in an event-controlled
latch always alternate. Upon a transition on c, the latch cap-

c p c p

D Q Q

cd pd cd pd
Figure 6. Two event-driven latch imple-
mentations. (a) (b)
 ASYNCHRONOUS CIRCUITS 723

VDD
c’ c LET microprocessor (9) is one example. Although there are
c many asynchronous implementations of micropipelines, we
x
y x
z z
y x
y
c c’
Figure 7. A CMOS implementation of a double-throw switch.
tures the current input data and becomes opaque. The follow-
ing transition on cd is an acknowledgment to the data pro-
vider that the current data is captured and that the input
data can be changed safely. A subsequent transition on p re-
turns the latch to its transparent state to pass the next data
to its output. The p signal is acknowledged by a transition on
pd. Notice that in implementation (a) of Fig. 6 signals cd and
pd are merely delayed and possibly amplified versions of c
and p, respectively.
A group of event-controlled latches, similar to implementa-
tion (a) of Fig. 6, can be connected, sharing a capture wire
and a pass wire, to form an event-controlled register of arbi-
trary data width. Implementation (b) of Fig. 6 can be general-
ized similarly into a register by inserting additional level-con-
trolled latches between the MERGE and the TOGGLE. A
comparison of different micropipeline latches is reported in
(43) and later in (44).
Pipelining
Pipelining is a powerful technique for constructing high-per-
formance processors. Micropipelines are elegant asynchro-
nous circuits that have gained much attention in the asyn-
chronous community. Many VLSI circuits based on
micropipelines have been successfully fabricated. The AMU-
only show an asynchronous implementation based on two-
phase signaling and data bundling, as given in Ref. 5. For
other implementations of pipelines involving four-phase sig-
naling, the reader is referred to Ref. 45.
The simplest form of a micropipeline is a First-In-First-
Out (FIFO) buffer. A four-stage FIFO is shown in Figure 8. It
has a control circuit composed solely of interconnected JOINs
and a data path of event-controlled registers. The control sig-
nals are indicated by dashed lines. The thick arrows show the
direction of data flow. Data is implemented with single-rail
encoding, and the data path is as wide as the registers can
accommodate. Adjacent stages of the FIFO communicate
through a two-phase, bundled-data signaling protocol. This
means that a request arrives at the next stage only when the
data for that stage becomes valid. A bubble at the input of a
JOIN is a shorthand for a JOIN with an IWIRE on that input. It
implies that, initially, an event has already occurred on the
input with the bubble, and the JOIN produces an output event
immediately upon receiving an event on the other input.
Initially, all control wires of the FIFO are at a low voltage
and the data in the registers are not valid. The FIFO is acti-
vated by a rising transition on Rin, which indicates that input
data is valid. Subsequently, the first-stage JOIN produces a
rising output transition. This signal is a request to the first-
stage register to capture the data and become opaque. After
capturing the data, the register produces a rising transition
on its cd output terminal. This causes a transition on Ain and
a transition on r1, which is a request to the second stage of
the FIFO. Meanwhile, the data has proceeded to the second-
stage register and has arrived there before the transition on
r1 occurs. If the environment does not send any new data, the
first stage remains idle, and the data and the request signals
propagate further to the right. Notice that each time the data
is captured by a stage, an acknowledgment is sent back to the
previous stage which causes its latch to become transparent
again. When the data has propagated to the last register, it

Rin a1 r2 a3 Rout

c pd cd p c pd cd p
Dout
Din Reg Reg Reg Reg

cd p c pd cd p c pd

Figure 8. A four-stage micropipeline

Ain r1 a2 r3 Aout FIFO structure.
724 ASYNCHRONOUS CIRCUITS

Rin a1 r2 a3 Rout
Delay Delay

c pd cd p c pd cd p
Dout

Logic

Logic

Logic

Logic
Din Reg Reg Reg Reg

cd p c pd cd p c pd

Figure 9. A general four-stage micropipe- Delay Delay

Ain r1 a2 r3 Aout
line structure.

is stored and a request signal Rout is forwarded to the con-
sumer of the FIFO. At this point, all control signals are at a
high voltage except for Aout. If the data is not removed out of
the FIFO, that is, Aout remains at low voltage, the next data
coming from the producer advances only up to the third-stage
register, because the fourth-stage JOIN cannot produce an out-
put. Finally, Aout also becomes high when the consumer ac-
knowledges receipt of the data. Further data storage and re-
moval follows the same pattern. The operation of each JOIN is
interpreted as follows. If the previous stage has sent a request
for data capture and the present stage is empty, then send a
signal to capture the data in the present stage.
The FIFO is modified easily to include data processing. A
four-stage micropipeline, in its general form, is illustrated in
Figure 9. Now the data path consists of alternately positioned
event-driven registers and combinational logic circuits. The
event-driven registers store the input and output data of the
combinational circuits, and the combinational circuits per-
form the necessary data processing. To satisfy the data-
bundling constraint, delay elements are occasionally required
to slow down the propagation of the request signals. A delay
element must at least match the delay through its corre-
sponding combinational logic circuit, either by some comple-
tion detection mechanism or by inserting a worst-case delay.
A micropipeline FIFO is flexible in the number of data
items it buffers. There is no restriction on the rate at which
data enter or exit the micropipeline, except for the delays im-
posed by the circuit elements. That is why this FIFO and mi-
cropipelines generally are termed elastic. In contrast, in an
ordinary synchronous pipeline, the rates at which data enter
and exit the pipeline are the same, dictated by the external
clock signal. A micropipeline is also flexible in the amount of
energy it dissipates, which is proportional to the number of
data movements. A clocked pipeline, however, continuously
dissipates energy as if all stages of pipeline capture and pass
data all the time. Another attractive feature of a micropipe-
line is that it automatically shuts off when there is no activ-
ity. A clocked pipeline, on the other hand, requires a special
clock management mechanism to implement this feature.
This sensing mechanism, however, constantly consumes en-
ergy because it should never go idle.
CONCLUDING REMARKS
We have touched only on a few topics relevant to asynchro-
nous circuits and omitted many others. Among the topics
omitted are the important areas of verifying, testing, and ana-
lyzing the performance of asynchronous circuits. We hope,
however, that within the scope of these pages we have pro-
vided enough information for further reading. For more infor-
mation on asynchronous circuits, see (12, 46, or 47). A com-
prehensive bibliography of asynchronous circuits is in (48).
Up-to-date information on research in asynchronous circuit
design is at (49).
The authors wish to thank Bill Coates for his generous
criticisms of a previous draft of this article.
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MAITHAM SHAMS
University of Waterloo
JO C. EBERGEN
Sun Microsystems Laboratories
MOHAMED I. ELMASRY
University of Waterloo
ASYNCHRONOUS SEQUENTIAL LOGIC
In sequential logic (see Sequential Circuits), output is a
function of current input and the state stored in the sys-
tem. In synchronous sequential logic circuits, time is quan-
tized, making all actions and state changes take place at
discrete intervals of time, determined by a regular source
of pulses called a clock. For the other more general class,
called asynchronous sequential circuits (ASCs), timing in-
formation is introduced without the use of a global clock;
thus, events in signals and changes in states take place at
any time. The use of ASCs may often bring some advan-
tages when implementing digital control and processing
structures. Such advantages come from the decentraliza-
tion of the timing control in the operation of the system,
with self-synchronization taking place at a local level.
This article introduces most of the fundamental issues
related to ASCs: comparison with synchronous circuits and
potential advantages of ASCs, major specification and de-
sign techniques, different implementation architectures,
and performance characteristics.
An ASC can be simply defined as a sequential circuit
whose internal states change only in response to changes
in its inputs, with no common timing reference (see Ref. 1
for a complete introduction). While the reader can easily
understand how a privileged signal—called the clock—can
control the change of the state in a synchronous sequential
circuit, the way to ensure correct operation in an ASC is not
so clear. Thus, it is necessary to establish more precisely
the operational procedure of the ASC, establishing suppo-
sitions about the delay models of components and inter-
connections in the system. Negligible, bounded, arbitrary,
or unbounded delay models in gates and interconnections
can be considered.
A simple ASC model is the Huffman circuit (Fig. 1),
which is basically composed of a combinatorial circuit and
a set of feedback lines, with a bounded (or zero) delay model
for interconnections. For a Huffman ASC to work properly
(hazard- and race-free operation), the input signals can
only change once the internal state has been correctly set-
tled (operation under fundamental mode and single-input
change). There are some other operation modes, such as
input–output, multiple, or unrestricted input change, with
different constrains. A special operation mode, called burst
mode operation, allows operation in the fundamental mode
but on bursts of inputs rather than single inputs. For ad-
ditional information, see Reading List.
Figure 1. Huffman Circuit. Delay elements can be explicitly
placed or being simply the delay in feedback lines.
J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright © 2007 John Wiley & Sons, Inc.
More generally, an ASC is called speed-independent
when it operates correctly (hazard-free) for any finite delay
in gates. A subset of these circuits generates a completion
signal indicating that its operation has finished. For cor-
rect behavior, changes in input signals are only allowed
when a completion signal is activated. More restrictive is
the delay-insensitive ASC, which works correctly for any
finite delay in gates and interconnections. An intermedi-
ate category is the quasi-delay-insensitive ASC, which is
a delay-insensitive ASC that considers isochronic forks. In
this type of ASC, delay in interconnections is arbitrary ex-
cept in forks, where the two branches have similar delays.
SELF-TIMED APPROACH
A self-timed circuit, also called a handshake circuit, is
an ASC that is self-synchronized with its environment
through a handshaking protocol (see Ref. 2 for a complete
introduction). The behavior of components and elements in
a self-timed system is conducted by events in their termi-
nal ports: The beginning of the operation of the system is
caused by a specific event in an input signal (request), and
the end of the operation is indicated to the outside by an-
other event in an output signal (acknowledgment). Thus,
the time required to perform the computation or processing
is determined by internal delays of gates and interconnec-
tions inside the circuit, corresponding to the time elapsed
between the request and the acknowledgment events. A
precedence relation exists between such events, in that
initiation must take place prior to finishing, indicating a
sequence of events.
A self-timed system can be defined either as (1) a self-
timed circuit itself, or (2) a correct connection of self-timed
circuits. Such a correct connection incorporates the restric-
tions in the communication between such elements, im-
posed by the handshaking protocol. In a simplified model,
the handshaking protocol is verified by specific signals
called protocol signals. In such signals at least two events
are necessary to describe the self-timed operation (request
and acknowledgment), and these events must alternate.
Figure 2(a) shows a so-called two-phase, or no-return-to-
zero (NRZ), handshaking protocol characterized by the
events that occur at the edges of protocol signals. Thus,
logic circuits operating under this protocol should be edge-
triggered. On the other hand, Fig. 2(b) displays a so-called
four-phase, or return-to-zero (RZ), handshaking protocol,
which is level-sensitive. Systems incorporating such proto-
cols will present different performance: The two-phase pro-
tocol is faster and, since it has less transitions, consumes
less power. However, the four-phase protocol is easier to im-
plement because it operates with less-costly level-sensitive
hardware.
Potential advantages in the use of the self-timed ap-
proach are based on its higher efficiency in computing data,
especially in those cases where processing time is strongly
data-dependent; self-timed ASCs operate on an average-
case basis, while synchronous circuits operate on a worst-
case basis.
2 Asynchronous Sequential Logic
Figure 2. Handshaking protocol: (a) 2-phase or edge-sensitive;
(b) 4-phase or level-sensitive.
GLOBALLY ASYNCHRONOUS LOCALLY
SYNCHRONOUS APPROACH
A promising method between pure synchronous and self-
timed circuits is the Globally Asynchronous Locally Syn-
chronous (GALS) approach. Although the background for
this technique was set in 1984 (3), recently has received
a lot of attention because it offers advantages from both
the synchronous and asynchronous domains. In GALS sys-
tems, the components are synchronous modules operating
at their own clock speed, which allows the proven syn-
chronous design methodologies to be used. The interface
between the synchronous components is made with self-
timed circuitry, generating the local clock signal under a
request-acknowledgement basis. The main advantages in
using the GALS technique are the elimination of problems
related to the usage of a global clock (see next section)
and the possibility of using classical synchronous cores,
methodologies and CAD tools. The main drawback is the
metastability problem when interacting synchronous and
asynchronous signals, being this problem faced with design
solutions (4).
LIMITATIONS OF SYNCHRONOUS CIRCUITS
Most of the problems and limitations of synchronous cir-
cuits stem from the existence of a global clock signal. The
main problems are crosstalk noise and, especially, clock-
skew and synchronization faults.
Clock-Skew Problems
In synchronous circuits, the clock signal must arrive
simultaneously at the memory elements to avoid race
problems. However, generating and distributing high-
frequency clocks inside very large-scale (VLSI) integrated
circuits (ICs) is a very difficult and expensive task, so that
eliminating clock skew often limits system performance (5–
7). Clock skew appears because the clock paths suffer dif-
ferent delays, causing synchronization failures in the sys-
tem. The nature of clock skew is unpredictable for two main
reasons: first, at a logic level, the designer cannot prevent
the placement of memory elements in the layout, and sec-
ond, the variations in the delays depend on various factors,
such as operation temperature and technological process
deviations. Thus, the designer cannot ensure clock-skew-
free operation.
Figure 3 shows an example of the pernicious effects of
clock skew. The correct operation requires that the first
bistable store its input datum D1 , while the second bistable
stores Q1 . However, if the delay in the clock signal is greater
than the delay in the datum line (
2 >
1 + propagation
delay of first bistable), D1 may be stored instead in the
second bistable, so that the Q1 value is lost.
This problem is nowadays aggravated because, with cur-
rent technologies, delays in interconnection paths are be-
coming comparable to delays in gates. Classical solutions
to this problem, such as (1) routing of clock signals in the
opposite direction to data flow and (2) use of nonoverlap-
ping clocks, limit the overall performance of the system.
The most effective solutions, such as identical buffering in
each clock path or routing clock signals through H-tree net-
works, are much more expensive in design time and cost
(5–7). Parameters that should be taken into account in gen-
erating and distributing clock signals are routing layers,
clock network shape, clock generators, rise and fall times,
and capacitive and resistive load in lines.
Synchronization Problems
Synchronization problems can have various causes, but
the primary cause is metastable operation in bistables.
The probability of failure increases with the complexity
and operation speed of the system. In synchronous op-
eration, some timing restrictions in bistables, concerning
hold time, setup time, and pulse width, must be observed.
Due to asynchronous interactions—a delay between data
and clock signals, for instance—that cause a violation in
such restrictions, a bistable may enter its metastable state,
showing in its output an undetermined logic state for an
indefinite time. If such output acts as the input of two par-
allel bistables, these may read different logic values upon
the arrival of the next clock edge. In such a case, a system
error occurs as a consequence of a synchronization fault.
In view of these problems, it is of interest to consider the
design of ASCs, which provide solutions in that (1) ASCs do
not need a global clock to synchronize the operation of the
circuit, and (2) the handshaking protocol imposes restric-
tions on changes in the inputs of the memory elements.
DESCRIPTION AND REPRESENTATION TECHNIQUES
OF ASYNCHRONOUS SEQUENTIAL CIRCUITS
Flow diagram and tables are the classic ways of describing
ASC (1). States are stored in the feedback loops or in asyn-
chronous latches. Correct operation is ensured with the as-
sumption of operation in the fundamental mode and with
single-input change. Once the flow table has been gener-
ated or obtained, minimization and assignment processes
generate an asynchronous implementation, which should
be race- and hazard-free.

Figure 4. State table (a) and STG (b) corresponding to an
asynchronous pipeline interface (c), working under a 4-phase
handshaking protocol, and implemented with two two-input C-
elements (d).
The characteristic of ASCs by which changes in inputs
directly bring about changes in states and outputs makes
graph-based descriptions suitable. Such representations
easily describe precedence relations between events in sig-
nals and allow for parallelism, decisions, and conflict be-
tween processes as well. An important, but not unique,
graph-based description is the signal transition graph
(STG), an interpreted Petri net. Basically, STGs are formed
by places—signal transitions, labeled + for rise transitions
and—for fall transitions—and by arcs connecting places. If
the STG satisfies some criteria of “good behavior” (liveness,
safety, persistence, semimodularity, etc.), it may represent
a hazard-free ASC (5). Other techniques based on Petri nets
are change diagrams and I nets.
Figure 4 shows the table- and graph-based description
and a possible implementation of a pipeline interface op-
erating under a four-phase handshaking protocol. Rin per-
forms a request from block A, acknowledged by Aout and
transmitted to block B through the Rout signal, depending
on the value of Ain , which indicates if B is ready to accept
data. All signals are considered active high.
Starting from an initial state (Rout Aout = 0 0) with no re-
quest stored, activation of a request (R+in ) leads the system
Asynchronous Sequential Logic 3
Figure 3. Illustrative example of neg-
ative effects of clock skew. Datum in Q1
can be lost if delay in clock line is higher
than delay in datum line plus propaga-
tion delay in first bistable.
to the state (Rout Aout = 0 1), indicating that the request
has been acknowledged and considered. Only when Ain is
disabled (A− in ), indicating that the following cell is idle, does
the system go to the state (Rout Aout = 11), transferring the
request from the present to the next stage. Disabling the
input request (R− in ) forces the falling of the acknowledge
signal (A− out ), leading the system to the state (Rout Aout =
10), from which the system is returned to the initial state
by disabling Ain .
The proposed race-free implementation uses as a mem-
ory cell a C-Muller element: a bistable that stores its input
values when they are coincident. The characteristics of this
bistable (i.e., the fact that it performs the AND operation
on events) make it the recommended memory element for
self-timed implementations, as suggested by Meng (8) and
Martin (9).
Peculiarities of ASCs exclude classic synthesis tools
used for synchronous sequential circuits. Different
methodologies have been presented, which are focused on
graph- and state-based descriptions. Also, VLSI program-
ming and sintax-driven translation has recently received
attention (9–11).
Synthesis tools using state representation (flow dia-
grams and tables) are oriented toward the implementa-
tion of race-free tables by using techniques of state mini-
mization and efficient assignment. For instance, so-called
“single-transition table” (STT) state assignments provide
race-free VLSI circuits (see Reading List).
Synthesis tools using graph representations (STG or
Petri nets) utilize as input an original graph that contains
the desired behavior. This graph is transformed by using
different techniques in such a way that the transformed
graph verifies some properties of “good behavior,” such as
liveness, safety, or semimodularity. Some algorithms gen-
erate a state diagram and a hazard-free circuit is synthe-
sized. The transformation of the original graph into the
modified one takes place but adding arcs (causal relations)
and signals in such a way that the transformed graph ver-
ifies the above-mentioned properties, and the resulting cir-
cuit is hazard-free (see Reading List).
VLSI programming allows the description of typical
asynchronous VLSI processes such as concurrence and par-
allelism between processes. Synthesis tools based on VLSI
programming, as for instance TANGRAM (10), BALSA
(11) or the one used in (9), directly translate a high-level
description into hardware through connections between
handshake signals and circuits.
4 Asynchronous Sequential Logic
ARCHITECTURES OF ASYNCHRONOUS SEQUENTIAL
CIRCUITS
The main parameter that characterizes the architecture
of ASCs is the way that the self-synchronization is per-
formed. In self-timed ASCs, the timing control is carried
out by data themselves, assisted by specific protocol—
handshake—signals. The way that this information is in-
cluded depends on the data encoding and on the rela-
tionship between data and handshake signals. There are
two main data signaling schemes used in self-timed ASCs:
dual- and single-rail codification.
Dual-Rail Codification
Using dual-rail code, also called self-synchronizing or
delay-insensitive code, allows the inclusion of information
about the validity of data by including redundancy of in-
formation. A simple code uses two signal bits (xt and xf )
per data bit (x). Thus, we can express four possible values:
when both xt and xf are inactive (low level, for instance),
an “empty” or “spacer” state is defined, indicating that data
are not valid. When either xt or xf is active (high level, for
instance), the data are valid (true or false, respectively).
By definition, xt and xf cannot be simultaneously active.
Figure 5 presents a waveform diagram showing the syn-
chronization scheme using dual-rail data, working with a
four-phase handshaking protocol. Only one transition per
bit takes place per operation cycle, while valid data and
spacers are forced to alternate. Delay-insensitive operation
may be ensured, since delay in interconnections would only
bring about additional delays in transitions, but events oc-
cur in the right sequence.
Single-Rail Codification
This approach, also called bundled data, uses a specific
handshake signal to validate data, in such a way that only
one signal per data bit is needed. However, synchronization
between the validation signal and data signal is required
to ensure correct operation; thus, delay-insensitive opera-
tion is not guaranteed. To validate the output data of an
ASC, it is necessary to generate a completion signal once
the operation of the circuit is finished. This completion sig-
nal can be used as a request signal for other ASCs. The
two most widely accepted mechanisms for generating com-
pletion signals are based on the use of matched delays and
the use of differential circuits as computation or processing
elements.
Matched Delays. This technique (2, 12) generates a com-
pletion signal by using a delay element that matches the
worst-case delay of the combinational logic (Fig. 6). When
the request is activated, input data are valid. Since the
combinational logic takes less time to process data than
the propagation time of the delay element, once the com-
pletion signal is activated, the output data are necessarily
valid. This scheme has the advantage of simplicity, but its
operation is always performed considering the worst-case
delay. Furthermore, the correct calculation of propagation
delays and implementation of delay elements requires ex-
haustive timing simulations (see Delay circuits).
Differential Circuits. Using differential circuits as
computation or processing blocks provides an effi-
cient way of generating completion signals (8). These
circuits, which are well suited for complementary
metal–oxide–semiconductor (CMOS) implementations,
generate both the true and the complemented outputs.
However, dual-coded inputs are needed. Conversion of
single-rail to dual-rail data can be performed at a local
level. The generic schematic and waveform diagrams are
shown in Fig. 7. In the precharge phase, outputs take the
same value, while in the evaluation phase, the logic func-
tion is performed and the two outputs take complemented
values. A simple logic gate detecting the complemented
values can generate the completion signal. The main
advantage is the adaptability to new operation conditions,
but at the cost of expensive hardware resources.
Figure 8 shows an example of bundled-data architec-
ture using differential circuits to generate completion sig-
nals. Synchronous memory elements (D flip-flops) are lo-
cally clocked by protocol signals (not shown in the figure)
in such a way that data must be stored and stable while
they are being processed. Single- to dual-rail data conver-
sion takes place in the memory elements. Interconnection
circuits are implemented with two C elements, as we can
see in the ASC shown in Fig. 4. The Rout signal acts as a
request signal for the differential circuit, while the comple-
tion signal is the Rin signal for the following interconnec-
tion circuit.
MACROMODULE-BASED CIRCUITS
Most current handshake circuits combine some of the
above-mentioned characteristics: two- or four-phase hand-
shaking protocol, matched delays or differential circuits,
and single-rail or dual-rail codification. A common charac-
teristic is their modularity, in the sense that we can inter-
connect several modules that work under the same hand-
shaking protocol and codification schemes to build a com-
plex self-timed ASC. Thus, an efficient approach to the de-
velopment of handshake circuits is the use of a library of
macromodules that, correctly interconnected, can perform
any desired functionality.
With respect to interconnections between macromod-
ules, although they can be used to design delay-insensitive
control modules, their implementation is not delay-
insensitive or even speed-independent.
Micropipelines
A very important macromodule-based approach, called mi-
cropipelines, was presented by Sutherland (12). It uses a
two-phase handshaking protocol, single-rail codification,
and matched delays, and its basic architecture is shown in
Fig. 9. For the data path, it uses data pass–capture latches
to store data in events of protocol signals. For control, it
uses a library of event-sensitive macromodules, shown in
Fig. 10. The XOR gate and the C element perform the OR
and AND operation of events, respectively. The toggle cell
transfers an event from its input to its two outputs alter-
nately, starting with the dotted output. The select block
allows a Boolean to direct the input event to the true or

false output. The call block allows two independent, mu-
tually exclusive processes to share a common subprocess.
The arbiter cell grants a common resource to only one of
the elements that requested it. The mutually exclusive el-
ement (MUTEX) ensures that the resource can never be
used simultaneously by the two elements that requested
it.
Control and Data Handshake Circuits
One of the main approaches to the design of ASCs uses
VLSI programming for direct translation of high-level de-
scriptions into hardware (9–11). Control and data hand-
shake circuits are the result of compiling the behav-
ior description. A handshake circuit is a (quasi) delay-
insensitive network of components connected by commu-
nication channels. A control handshake circuit communi-
cates with other components through request/acknowledge
signaling through the channels. Data handshake circuits
also include data signaling. Following heuristic or system-
atic techniques, you can design more complex components
based on simple handshake circuits.
Asynchronous Sequential Logic 5
Figure 5. Speed-independent buffer as example of a dual-rail
scheme for data signaling. A 4-phase handshaking protocol has
been used. Empty (E) and Valid Data values are forced to alter-
nate.
Figure 6. Bundled-data scheme using matched delays to gen-
erate complete signal.
1 (
2 ) matches the worst case delay of
C1 (C2 ). Data signals must be validated by handshake signals.
Figure 7. (a) Logic schematic of a generic differential logic block.
LOAD block sets the precharge values and the differential tree
generates both the true and the complemented logic output. (b)
Waveform diagram showing how precharge and evaluation phases
alternate.
As an example of an ASC built with handshake circuits
(taken from Ref. 10), Fig. 11 shows the high-level descrip-
tion, symbol, and handshake-based implementation of one-
and two-stage first-in, first-out (FIFO) memories. There is
a direct translation from language (forever do) into a hand-
shake circuit (repeater block, marked with ∗; and with
a possible implementation is shown in Fig. 12). Blocks
marked “;” are sequencers, which complete handshaking
from the ASC’s input to its outputs alternatively. The T
and x blocks, called transferrers and handshake latches, re-
spectively, are data handshake blocks, capable of transfer-
ring and storing data signals according to the handshake
protocol. An open circle a block indicates that the request
acts as input and the acknowledge as output (passive port),
while a filled circle indicates an output request and input
acknowledge (active port).
For the one-stage FIFO in Fig. 11 (see Fig. 4 for the
same basic functionality), the statement (a?x0; b!x1) indi-
cates that input a is loaded in variable x, which can be read
through the b port. The action of the sequencer makes it
possible for data to be written before being read, verify-
ing the handshaking protocol. The two-stage FIFO is built
6 Asynchronous Sequential Logic

Figure 8. Example of bundled-data architecture using differential circuits as computation blocks.

The generation of complete signals is quite straightforward by using a logic gate. A 4-phase hand-
shaking protocol is used.

Figure 9. Micropipelined single-rail data architecture. The data path is implemented with combi-
natory logic to perform the logic function and Pass–Capture latches to store data. Control manages
protocol signals and write/read operation in latches. Matched delays are used for completing hand-
shaking protocol (see reference 12 for more complex examples).

with two cascaded one-stage FIFOs operating in parallel; it
is marked with the symbol  in the specification (Fig. 11).
The final circuit can be synthesized by substituting each
handshake component for its schematic and layout.
DISCUSSION OF CHARACTERISTICS AND
PERFORMANCES
Current state-of-the art ASCs are more complex and, in
general, more difficult to design than their synchronous
counterparts. Many advantages of ASCs over synchronous
circuits have been claimed, such as automatic adapta-
tion to physical properties, better accommodation to asyn-
chronous external inputs, better technology migration po-
tential, more timing reliability, lower noise and electro-
magnetic emission, and higher modularity. However, the
most prominent advantages of ASCs come from their spe-
cial ability to exploit data dependence in operation time
and their lower power consumption. Thus, there are some
applications where ASCs can be recommended, such as dig-
ital signal processing and low-power applications. Some
emergent applications are in the field of thermally-aware
circuits, secure systems as smart cards, and the implemen-
tation of bio-inspired artificial vision systems, based on
the asynchronous address-event-representation communi-
cation scheme. Advanced aspects, such as testability or ver-
ification, are still under development.
 Asynchronous Sequential Logic 7

Figure 10. Event-sensitive macromodule library and a possible CMOS implementation of each cell.

Figure 11. High-level description, symbol and module imple-

mentation of 1-stage and 2-stage FIFO memories.

To show the data dependence, let us consider (Fig. 13)
a ripple carry adder (see Summing circuits), where the
time needed to perform the operation depends on the input
words (2). The best cases correspond to direct generation of
output carry of all cell bits, and this occurs when the added
bits have the same value (ai , bi , ci−1 ) = (1, 1, x) or (0, 0, x),
giving as output carry 1 and 0, respectively, regardless of
the value of the input carry. The worst case is given by the
propagation of carry throughout the whole chain, whereby
each cell needs the output carry of the previous cell to fin-
8 Asynchronous Sequential Logic
Figure 12. A possible implementation of a Repeater block. Its
functionality is summarized as follows: a requests b (ar+ ); b is indef-
initely executed (br+ → bk+ → br− → bk− ); a is released (ak+ ). A 4-phase
handshaking protocol is supposed.
Figure 13. Ripple carry adder as an example (taken from ref-
erence 2) showing the dependence of processing time with input
data. The operation performed by each full adder is ci = ai bi + ai
ci−1 + bi ci−1 ; si = ai xor bi xor ci−1 . If an bn = 1 1, then cn = 1; if an
bn = 0 1, then cn = an−1 bn−1 + an−1 cn−1 + bn−1 cn−1 , depending
recursively on the previous carry.
ish its processing. An input vector such as (ai , bi , ci−1 ) = (1,
0, x) will create such a situation. This example shows how
the data themselves lead to very different time process-
ing. While synchronous circuits must take into account the
worst-case operation, ASC can operate on the average case.
Operation Speed
At a circuit level, ASCs show more tolerance for physical
variations, such as deviation in the technological process
and variations in supply voltage and temperature. This is
mainly due to the action of the handshake and the gen-
eration of completion signals (indicating when the opera-
tion has been finished) and to their working at the max-
imum speed possible. At an algorithmic or architectural
level, ASCs’ ability to operate on an average case is help-
ful, especially when the worst and average cases are very
different; and they are not limited by the slowest process-
ing block (2, 8). However, verification of the handshaking
protocol requires two processes: (1) monitoring the state,
and (2) “wait or go” operation. Thus a tradeoff exists be-
tween the two approaches.
Power Consumption
In synchronous circuits, clock lines have to be toggled and
circuit nodes charged and discharged even in unused parts
or when the circuit is idle and there are no data to compute.
Also, the generation of “good” clock signals (vertical edges)
consumes a lot of power in each transition. Although ASCs
often require more signal transitions in a given computa-
tion than do synchronous circuits, these transitions usually
Figure 14. Representation of the power consumption vs opera-
tions performed. In the synchronous case, there is power consump-
tion even if there are no data to compute. In a self-timed ASC, for
relatively low input data rate, consumption is lower.
occur in areas involved in the current computation. More-
over, problems related to the generation of clocks are min-
imized. Figure 14 shows a generic representation of power
consumption versus operations performed. Because a clock
consumes power when the circuit is idle, depending on the
input data rate, the ASC consumes less power. A good ex-
ample of an ASC exhibiting less power consumption than
its synchronous counterpart is found in Ref. 13.
There are some interesting approaches combining the
advantages of the synchronous and the asynchronous style.
These structures are locally clocked and are based on the
generation of a local clock that ensures correct operation
of the circuit under asynchronous inputs. The most impor-
tant are those based on burst-mode operation, metastable-
insensitive Q-modules, and stoppable clocks (10).
BIBLIOGRAPHY
1. S. H. Unger, Asynchronous Sequential Switching Circuits.,
New York: Wiley-Interscience, 1969.
2. C. L. Seitz, System timing, inC. A. Mead andL. Conway (eds.),
Introduction to VLSI Systems. Reading, MA: Addison-Wesley
Pubs., 1980.
3. D. M. Chapiro, Globally-asynchronous locally-synchronous,
PhD thesis, Stanford University, 1984.
4. D. Sokolov and A. Yakovlev, Clockless Circuits and System
Synthesis, IEE Proc. Computers and Digital Techniques, 152
(3): 298–316, 2005.
5. H. B. Bakoglu, Circuits, Interconnections and Packaging for
VLSI. Reading, MA: Addison-Wesley Pubs., 1990.
6. J. M. Rabaey, Digital Integrated Circuits. A Design Perspective.
Englewood Cliffs, NJ: Prentice-Hall, 1996.
7. E. G.Friedman, Clock Distribution Networks in Synchronous
Digital Integrated Circuits, Proceedings of the IEEE, 89 (5):
665–692, 2001.
8. T. H. Y. Meng, Synchronization Design for Digital Systems.
Norwell, MA: Kluwer Academic Pubs., 1991.
9. A. J. Martin, Compiling communicating processes into delay-
insensitive VLSI circuits. Distributed Computing, 1 (4):
226–234, 1986.
10. K. van Berkel, Handshake Circuits: an Asynchronous Archi-
tecture for VLSI Programming. Cambridge University Press,
1993.
 Asynchronous Sequential Logic 9

11. A. Bardsley,The BALSA Asyn-

chronous Synthesis Systems web pages:
http://www.cs.manchester.ac.uk/apt/projects/tools/balsa/

12. I. E. Sutherland, Micropipelines. Commun. of the ACM, 32 (6):

720–738, 1989.
13. K. van Berkel, R. Burgess, J. Kessels, M. Roncken, F. Schalij,
and A. Peeters, Asynchronous circuits for a low power: A DCC
error corrector. IEEE Design and Test of Computers, 11 (2):
22–32, 1994.

Reading List

Most classical textbooks dedicated to digital logic design discuss

asynchronous sequential logic. A summary of them is as follows:

A. E. A. Almaini, Electronic Logic Systems. Englewood Cliffs, NJ:

Prentice-Hall, 1994, chap. 5.
E. J. McCluskey, Logic Design Principles. Englewood Cliffs, NJ:
Prentice-Hall, 1986, chap. 9.
F. J. Hill and G. R. Peterson, Computer Aided Logical Design with
Emphasis on VLSI. New York: John Wiley & Sons, 1993, chap.
14.
R. F. Tinder, Digital Engineering Design: A Modern Approach. En-
glewood Cliffs, NJ: Prentice-Hall 1991, chap. 6.
S. H. Unger, The Essence of Logic Circuits. 2nd ed., Piscataway,
NJ: IEEE Press, 1997, chap. 6.

ANTONIO J. ACOSTA-JIMÉNEZ
MANUEL J. BELLIDO-DÍAZ
ANGEL BARRIGA-BARROS
University of Seville, Seville,
Spain
ATTENUATORS
Attenuators allow a known source of power to be reduced
by a predetermined factor usually expressed as decibels.
Attenuators are linear, passive or active networks or de-
vices that attenuate electrical or microwave signals, such
as voltages or currents, and hence power in a system by
a predetermined ratio. The most commonly used method
in attenuators is placing resistors at the center of an elec-
tric field, which induces a current resulting in ohmic loss. A
great advantage of attenuators is that since it is made from
non-inductive resistors, they are able to change a source or
load, which might be reactive, into one which is precisely
known and resistive. This power reduction is achieved by
the attenuator without introducing distortion. Attenuators
are used in a wide variety of applications and can sat-
isfy almost any requirement where a reduction in power is
needed. Attenuators are used to extend the dynamic range
of devices such as power meters and amplifiers, reduce sig-
nal levels to detectors, match circuits and are used daily in
lab applications to aid in product design. Attenuators are
also used to balance out transmission lines that otherwise
would have unequal signal levels. Attenuation is usually
expressed as the ratio of input power (Pin ) to output power
(Pout ), in decibels (dB), as
This is derived from the standard definition of attenuation
in Nepers (Np), as
where α is attenuation constant, Np/m, and x is the dis-
tance between the voltages of interest, E1 and E2 .
Figure 1a Concept and definition of attenuation.
Figure 1b Alternative representation.
J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright © 2007 John Wiley & Sons, Inc.
Figure 1 illustrates this concept. The relation between
Np and dB is,
Here the load and source are matched to the characteristic
impedance. The decibels are converted to the attenuation
ratio as follows: Pin /Pout = log−1 10 dB/10 or Vin /Vout = log−1 10
dB/20.
APPLICATION
There are many instances when it is necessary to reduce
the value or level of electrical or microwave signals, such
as voltages and currents by a fixed or variable amount to
allow for the rest of the system to work properly. Atten-
uators are used for this purpose. For example, in turning
down the volume on a radio, stereo CD player or IPod, we
make use of a variable attenuator to reduce the signal. Al-
most all electronic instruments use attenuators to allow
for the measurement of a wide range of voltage and cur-
rent values, such as voltmeters, oscilloscopes, and other
electronic instruments. Thus, the various applications in
which attenuators are used include the following:

To reduce signal levels to prevent overloading

To match source and load impedances to reduce their
interaction

To measure loss or gain of two-port devices

To provide isolation between circuit components, or
circuits or instruments so as to reduce interaction
among them

To extend the dynamic range of equipment and pre-
vent burn-out or overloading equipment
TYPES
There are various types of attenuators based on the nature
of circuit elements used, type of configuration, and kind of
adjustment. They are as follows:

Passive and active attenuators

Absorptive and reflective attenuators

Fixed and variable attenuators
A fixed attenuator is used when the attenuation is con-
stant. Variable attenuators have varying attenuation, us-
ing varying resistances for instance. The variability can be
in steps or continuous, obtained either manually or pro-
grammably. There are also electronically variable attenu-
ators. They are reversible, except in special cases, such as
a high-power attenuator. They are linear, resistive, or re-
active, and are normally symmetrical in impedance. They
include waveguide, coaxial, and strip lines, as well as cali-
brated and uncalibrated versions. Figures 2, 3, and 4 show
fixed, manual step, and continuously variable commercial
attenuators.
2 Attenuators

HP 84904L programmable step attenuator, direct cur-

rent (dc) to 40 GHz, 0 dB to 11 dB, 1 dB steps
HP 84906K programmable step attenuator, dc to 26.5
GHz, 0 dB to 90 dB, 10 dB steps
HP 84904L programmable step attenuator, dc to 40
GHz, 0 dB to 70 dB, 10 dB steps
HP 8495B manual step attenuator, dc to 18 GHz, 0 dB
to 70 dB, 10 dB steps
HP 355F programmable step attenuator, dc to 1 GHz, 0
Figure 2. Fixed coaxial attenuator. (Courtesy of Weinschel dB to 120 dB, 10 dB steps
Associates.) HP 8493A Coaxial fixed attenuator, dc to 12.4 GHz

Based on their utility, military attenuators are classified

as:
Class I For use as a primary standard
Class II For use as a secondary standard, and in
lab and precision test equipment
A—with lumped-constant or dis-
tributed shunt and series elements
B—with lossy-line pads
Class III For use in general field equipment
Class VI For use in equipment where precision
and stability are secondary considera-
tions
Typical mil specifications for fixed coaxial attenuators
are as follows:

Mil-A-3933/1: Attenuators, fixed, coaxial line, dc to 3

Figure 3. Manual step attenuator. (Courtesy of Weinschel GHz, class IIA, low power
Associates.) Mil-A-3933/2: Attenuators, fixed, coaxial line, 1 GHz to
4 GHz, class IIB, medium power
Mil-A-3933/10: Attenuators, fixed, coaxial line, dc to 18
GHz, class III, medium power
Mil-A-3933/26: Attenuators, fixed, coaxial line, 0.4 GHz
to 18 GHz, class IV low power

SPECIFICATIONS

To specify an attenuator, the purpose of the attenuator

should be known. Attenuators are used to provide protec-
Figure 4. Continuously variable attenuator. (Courtesy of Wein- tion, reduce power, and extend the dynamic range of the
schel Associates.) test equipment. In choosing an attenuator, the frequency
range of operation should be considered since the accuracy
depends on the frequency. Attenuation involves placing re-
Based on their usage, IEEE Std 474 classifies them as sistive material to absorb the signal’s electric field. This
Class I Standard
means, there will always be some reflection. So, attenua-
Class II Precision
Class III General purpose
tors must be designed to minimize reflection. This is quan-
Class VI Utility tified in terms of voltage standing wave ratio (VSWR). An-
other factor to be considered is the insertion loss, which is
Typical commercial attenuators are listed below: the ratio of power levels with and without the component
insertion. If it is a variable step attenuator, the step size is
to be known. Thus, the parameters available in the specs
WA 1 (0 GHz to 12.4 GHz), WA 2 (0 GHz to 3 GHz),
are as follows:
coaxial, fixed attenuators: 1 dB to 60 dB; 5 W av./1
kW PK
WA 115A manual step attenuators: 0 GHz to 18 GHz, 0 dB rating
dB to 9 dB, 1 dB steps VSWR
VA/02/100 continuously variable attenuators, resistive, Accuracy
0 GHz to 2 GHz, 5 W av./0.5 kW PK Power rating

Step size (if variable)
Frequency band
Degree of stability (measured by the change in atten-
uation due to temperature, humidity, frequency, and
power level variations)
Characteristic impedance of attenuator
Repeatability
Life
Degree of resolution (difference between actual attenu-
ation and measured value)
The definitions of various parameters used in selecting at-
tenuators are given below.
Electrical Parameters and Definitions (From
MIL-HDBK-216)
Attenuation A general transmission term used to indi-
cate a decrease in signal magnitude. This decrease
in power is commonly expressed in decibels (dB) as:
Deviation of Attenuation from Normal Difference in ac-
tual attenuation from the nominal value at 23◦ C and
an input power of 10 mW at a specified reference fre-
quency or frequency range. When used in a frequency
range, it involves the frequency sensitivity.
Frequency Sensitivity This is the peak-to-peak varia-
tion in the loss of the attenuator through the speci-
fied frequency range.
Frequency Range Range of frequency over which the
accuracy of attenuator is specified.
Insertion Loss Amount of power loss due to the insertion
of the attenuator in the transmission system. It is
expressed as a ratio of the power delivered to that
part of the system following the attenuator, before
and after the insertion.
Figure 5. Symmetrical pads with matched impedances. (a) T pad. (b) Pi pad. (c) Bridged T pad. (d) Balanced pad.
Attenuators 3
Characteristic Insertion Loss This is the insertion loss
in a transmission line or waveguide that is reflection-
less in both directions from the inserted attenuator.
Power-Handling Capabilities Maximum power that can
be applied to the attenuator under specified condi-
tions and durations without producing a permanent
change in the performance characteristics that would
be outside of specification limits.
Power Sensitivity This is the temporary variation in
attenuation (dB/W) under steady-state conditions
when the input power is varied from 10 mW to max-
imum input power.
Stability of Attenuation Capability of attenuator to re-
tain its parameters when subjected to various envi-
ronmental conditions.
Operating Temperature Range Temperature range the
attenuator can be operated with maximum input
power.
Temperature Sensitivity Temperature variation in at-
tenuation [dB/(dB × ◦ C)] over the operating range.
Input VSWR This is the level of reflected signal cre-
ated at the attenuator input when the output is ter-
minated with a load with the same characteristic
impedance as the source.
Output VSWR This is the level of reflected signal cre-
ated at the attenuator output when the input is ter-
minated with a load with the same characteristic
impedance as the source.
PASSIVE ATTENUATORS
Resistance Networks for Attenuators
Typically T, Pi, or L designs are used for attenuators.
Figure 5 shows four commonly used symmetrical (input
and output resistors of equal value) configurations. The
formulas for the resistance values in ohms for these pads
when the characteristic resistance R0 = 1  are given be-
low. If R0 is other than 1 , multiply each of the resistance
4 Attenuators

Figure 6. Unsymmetrical matching L attenuator.

values (a, b, c, 1/a, 1/b, and 1/c) by R0 , where

Simple wirewound resistors are used in audio applica-

tions. Nonreactive wirewound resistors, such as mica card,
Aryton-Perry winding, woven resistors are used for high
frequencies. For coaxial applications (over 26.5 GHz), thin-
film resistors are used. For higher frequencies, distributive
resistive films, such as nichrome alloy film, on a high qual-
ity ceramic substrate, such as alumina or sapphire, is used.
Figure 7. Definition of characteristic insertion loss. (a) Original
An unsymmetrical pad is shown in Figure 6, and the for-
setup without attenuator. (b) Original setup with attenuator be-
mulas for this pad are
tween source and load.

Typical values for the pads in Figure 5 are shown in

Table 1, and those of Figure 6 are shown in Table 2.
For a broad-band match between impedances R1 and R2 ,
Figure 8. T attenuator configuration.
use the minimum loss L pad (Figure 6).

Power Dissipation within a T Pad

Table 3 lists values of power dissipation within a T pad.
The values are for an input of 1 W; for other input powers,
multiply the values by the input power.

INSERTION LOSS

An attenuator is used to introduce attenuation between a

source and a load. Due to the introduction of the attenua-
tor, there is change in the current. This loss is designated
as insertion loss, which depends on the configuration. Usu-
ally, the load and source impedances are matched. Figure
7 illustrates this concept. If IL0 is the load current without
the attenuator pad, and IL is the current with the attenu-
ator pad, then the ratio IL /IL0 is called the insertion loss,
one of the parameters of the attenuates. Figure 7(a) shows
the source and load connected without an attenuator, and
Figure 7(b) shows the same system with an attenuator.
(The quantities, IL , Rin , and Rout depend on the attenuator
configuration.) The quantities insertion loss (IL ), input re-
sistance (Rin ), and output resistance (Rout ) depend on the
Figure 9. Pi attenuator configuration.
attenuator configuration. The value of each of the three re-
sistors of the T (Figure 8) and Pi (Figure 9) attenuators can
be chosen independently of others. This enables the three-
design criteria of input resistance, output resistance, and
insertion loss to be met. In many situations, the only func-
tion of the pad is to provide matching between source and
load; and although attenuation will be introduced, this may
not be a critical design parameter. This allows a simpler
type of pad to be designed, requiring only two resistors; it
is known as an L pad.
 Attenuators 5

Table 1. Resistance Values for Attenuator Pads When R0 = 1 a

dBb a b 1/b 1/a c 1/c a 1/a

0.100 0.006 86.853 0.012 173.710 0.012 86.356 0.006 173.710
0.200 0.012 43.424 0.023 86.859 0.023 42.930 0.012 86.859
0.300 0.017 28.947 0.034 57.910 0.035 28.455 0.017 57.910
0.400 0.023 21.707 0.046 43.438 0.047 21.219 0.023 43.438
0.500 0.029 17.362 0.058 34.753 0.059 16.877 0.029 34.753
0.600 0.034 14.465 0.069 28.965 0.072 13.982 0.034 28.965
0.700 0.040 12.395 0.081 24.830 0.084 11.915 0.040 24.830
0.800 0.046 10.842 0.092 21.730 0.096 10.365 0.046 21.730
0.900 0.052 9.634 0.104 19.319 0.109 9.160 0.052 19.319
1.000 0.057 8.667 0.115 17.391 0.122 8.195 0.058 17.391
2.000 0.115 4.305 0.232 8.724 0.259 3.862 0.115 8.724
3.000 0.171 2.838 0.352 5.848 0.412 2.424 0.171 5.848
4.000 0.226 2.097 0.477 4.419 0.584 1.710 0.226 4.419
5.000 0.280 1.645 0.608 3.570 0.778 1.285 0.280 3.570
6.000 0.332 1.339 0.747 3.010 0.995 1.005 0.332 3.010
7.000 0.382 1.116 0.896 2.614 1.239 0.807 0.382 2.614
8.000 0.430 0.946 1.057 2.323 1.512 0.661 0.430 2.323
9.000 0.476 0.812 1.232 2.100 1.818 0.550 0.476 2.100
10.000 0.519 70.273c 1.423 1.925 2.162 46.248c 0.519 1.925
20.000 0.818 20.202 c 4.950 1.222 9.000 11.111c 0.818 1.222
30.000 0.939 6330.900c 15.796 1.065 30.623 3265.500c 0.939 1.065
40.000 0.980 2000.200c 49.995 1.020 99.000 1010.100c 0.980 1.020
50.000 0.994 632.460c 158.110 1.006 315.230 317.230c 0.994 1.006
60.000 0.998 200.000c 500.000 1.002 999.000 100.100c 0.998 1.002
70.000 0.999 63.246c 1581.100 1.006 3161.300 31.633c 0.999 1.001
80.000 1.000 20.000c 5000.000 1.000 9999.000 10.001c 1.000 1.000
90.000 1.000 6.3246c 15.811 1.000 31.622 3.163c 1.000 1.000
100.000 1.000 2.000c 50.000 1.000 99.999 1.000c 1.000 1.000
a If R = 1 , multiply all values by R . (From Ref. data for Radio Engineers, 1985.)
0 0
b For other decibel values, use formulas in text.
c These values have been multiplied by 103 .

Table 2. Resistance Values and Attenuation for L Pada

R1 /R2 j j dB
20.00 19.49 1.03 18.92
16.00 15.49 1.03 17.92
12.00 11.49 1.04 16.63
10.00 9.49 1.05 15.79
8.00 7.48 1.07 14.77
6.00 5.48 1.10 13.42
5.00 4.47 1.12 12.54
4.00 3.47 1.16 11.44
3.00 2.45 1.22 9.96
2.40 1.83 1.31 8.73
2.00 1.41 1.41 7.66
1.60 0.98 1.63 6.19
1.20 0.49 2.45 3.77
1.00 0.00 ∞ 0.00
a For R = 1  and R > R . If R = 1 , multiply values by R . For ratios not in the table, use the formulas in the text. (From Ref. data for
2 1 2 2 2
Radio Engineers, 1985.)
Examples of use of table:
If R1 = 50  and R2 = 25 , then R1 /R2 = 2.0, and j = k = 1.414 × 25  = 35.35 .
If R1 /R2 = 1.0, minimum loss = 0 dB.
For R1 /R2 = 2.0, the insertion loss with the use of j and k for matching is 7.66 dB above that for R1 /R2 = 0
6 Attenuators

Table 3. Power Dissipation in T Pada

dB Watts, Input Series Resistor Watts, Shunt Resistor Watts, Output Series Resistor
0.100 0.006 0.011 0.006
0.300 0.017 0.033 0.016
0.500 0.029 0.954 0.025
0.700 0.040 0.074 0.034
0.900 0.052 0.093 0.042
1.00 0.058 0.102 0.046
1.200 0.069 0.120 0.052
1.400 0.080 0.114 0.058
1.600 0.092 0.152 0.064
1.800 0.103 0.167 0.068
2.000 0.114 0.181 0.072
2.200 0.126 0.195 0.076
2.400 0.137 0.208 0.079
2.600 0.149 0.220 0.082
2.800 0.160 0.232 0.084
3.000 0.171 0.242 0.086
3.200 0.182 0.252 0.087
3.400 0.193 0.260 0.088
3.600 0.204 0.270 0.089
3.800 0.215 0.278 0.090
4.000 0.226 0.285 0.090
5.000 0.280 0.314 0.088
6.000 0.332 0.332 0.083
7.000 0.382 0.341 0.076
8.000 0.430 0.343 0.068
9.000 0.476 0.338 0.060
10.000 0.519 0.328 0.052
12.000 0.598 0.300 0.038
14.000 0.667 0.266 0.027
16.000 0.726 0.230 0.018
18.000 0.776 0.200 0.012
20.000 0.818 0.163 0.010
30.000 0.938 0.059 0.001
40.000 0.980 0.020 0.000
a For 1 W input and matched termination. If input = 1 W, multiply values by P . (From Ref. data for Radio Engineers, 1985.)
in

Table 4. Resistors R1 and R2 values for various Attenuators (assuming Z0 = 50 )

Tee Pi Bridged Tee Reflection
dB R1 R2 R1 R2 R1 R2 R1 R2
0 0.0 open open 0.0 0.0 open 0.0 open
1 2.9 433.3 869.5 5.8 6.1 409.8 2.9 869.5
2 5.7 215.2 436.2 11.6 12.9 193.1 5.7 436.2
3 8.5 141.9 292.4 17.6 20.6 121.2 8.5 292.4
5 14.0 82.2 178.5 30.4 38.9 64.2 14.0 178.5
7 19.1 55.8 130.7 44.8 61.9 40.4 19.1 130.7
8 21.5 47.3 116.1 52.8 75.6 33.1 21.5 116.1
10 26.0 35.1 96.2 71.2 108.1 23.1 26.0 96.2
15 34.9 18.4 71.6 136.1 231.2 10.8 34.9 71.6
20 40.9 10.1 61.1 247.5 450.0 5.6 40.9 61.1
30 46.9 3.2 53.3 789.8 1531.1 1.6 46.9 53.3
40 49.0 1.0 51.0 2499.8 4950.0 0.5 49.0 51.0
50 49.7 0.3 50.3 7905.6 15761.4 0.2 49.7 50.3
100 50.0 0.0 50.0 open open 0.0 50.0 50.0
 Attenuators 7

and

and

Example: (T Attenuator) A T-type attenuator is re-

quired to provide 3 × 0 dB insertion loss and to match
50  input and output. Find the resistor values.

using the following equation:

Figure 10. L attenuator configuration. (a) Rs < RI . (b) Rs > RI .

using the following equation:

Figure 10 shows an L attenuator, which can be derived
from either a T or a pi attenuator, simply by removing one
of the resistors. As shown, different configurations are re-
quired depending on whether RS > RL or RS < RL .
Check:
T Attenuator Insertion Loss
The T attenuator contains resistors R1 , R2 , and R3 ; these
form a T configuration, as shown in Figure 6. Insertion
loss is usually measured in dB, defined as IL (dB) = −20 The Pi Attenuator Insertion Loss. Figure 9 shows a Pi
log IL or |20 log IL |, the amount of attenuation required. attenuator formed by resistors Ra , Rb , and Rc . The insertion
The insertion loss IL is given as loss and conductances Gin and Gout are given by

The input and the output of resistances of the attenuator

are given by

and
where G = 1/R; i.e., GL = 1/RL and so on.
The same Pi attenuator can be realized using a T atten-
uator with R1 , R2 , and R3 values using the Y– transfor-
In many cases, the attenuator has also to match the load mation, as
and the source impedance. In this case, R1 = R2 = R and
Rin = Rout = R0 . Thus,

and the insertion loss is given by

8 Attenuators

shows that for RS > RL , we have

Table 5. Attenuator Input Power Reduction
% Input Power attenuated = (1-10−dB/10 ) × 100%
dB % dB %
1 20.57 12 93.70 and
2 36.90 13 94.98
3 49.88 14 96.02
4 60.19 15 96.84
5 68.38 16 97.58
from which it can be shown that
6 74.88 17 98.00
7 80.05 18 98.42
8 84.15 19 98.74
9 87.41 20 99.00 and
10 90.00 30 99.90
11 92.06 40 99.99

Table 6. HPND-4165 PIN Diode Specifications

and when we put R2 = 0, the insertion loss is calculated as
Parameter HPND-4165 Test Conditions
High-resistance limit, RH 1100–1660  10 µA
Low-resistance limit RL 16–24  1 mA
Maximum difference in
resistance versus bias slope x 0.04 10 µA and 1 mA
Example Design an L attenuator to match a 300 source
to a 50 load and determine insertion loss. Here RS > RL
The selection between Pi and T is based on the value of using the following equation:
resistors that can be used in practice. With matching source
and load impedances, the values of the pi attenuator are

Using the following Equation:

and

Example: (Pi Attenuator) Repeat the above problem

using a Pi attenuator:
For Rs < Rl , we have

and
Using the following equation:

and
Using the following equation:

and

The L Attenuator Insertion Loss. An L attenuator can be The corresponding insertion loss is
derived from a T or a Pi attenuator by removing one resis-
tor. As shown in Figure 10, two configurations are obtained
depending upon RS > RL or RS < RL . Simple circuit theory
 Attenuators 9

Table 7. Attenuator Resistor Values for Different Levels of Attenuation

Attenuation (dB) R1 () R2 ()
2 5.73 215.24
4 11.31 104.83
6 16.61 66.93
8 21.53 47.31
10 25.97 35.14
12 29.92 26.81
14 33.37 20.78
22 42.64 7.99

Table 8. π-Attenuator Resistor Values for Different Levels of Attenuation

Attenuation (dB) R1 () R2 ()
2 436 11.61
4 221 23.85
6 150.5 37.35
8 116.14 52.84
10 96.25 71.15
12 83.54 93.25
14 74.93 120.31
22 58.63 312.90

Frequency: 0 GHz to 3 GHz

Attenuation: 50 dB
Example Design an L attenuator to match 50 source to Accuracy: ±0.10 dB (dc)
75 load and determine the insertion loss. ±0.15 dB (0 GHz to 2 GHz)
RS < RL , using the following equation: ±0.13 dB (0 GHz to 3 GHz)
VSWR: 1.15 (0 GHz to 1 GHz)
Input power: 1.20 (1 GHz to 3 GHz)
Connectors: 1 W av., 1 kW PK at −30◦ to 70◦ C
Length: Type N; St. St.; m, f
Diameter: 68 mm (2.7 in.)
Weight: 210 mm (0.83 in.)
using the following equation: Power sensitivity: 100 g (3.6 oz)
Temperature stability <0.005 dB/dB × W; bidirectional in power
<0.0004 dB/dB × ◦ C

Applications
Fixed attenuators are used in numerous applications. In
general, they can be classified into two distinct categories:
using the following equation:
1. Reduction in signal level
2. Impedance matching of a source and a load

Those in the first category are used in the following situa-

tions:

Operation of a detector in its square-law range for

FIXED ATTENUATORS
Fixed attenuators, commonly known as pads, reduce the
input signal power by a fixed amount, such as 3 dB, 10
dB, and 50 dB. For example, an input signal of 10 dBm
(10 mW) passing through a 3 dB fixed attenuator will exit
with a power of 10 dBm − 3 dB = 7 dBm (5 mW). Figure 2
shows a fixed coaxial commercial attenuator. A typical data
sheet for a fixed coaxial attenuator is as follows (courtesy
of Weinschel Associates).
most efficient operations.

Testing of devices in their small signal range.

Reduction of a high-power signal to a level compatible
with sensitive power measuring equipment, such as
power sensors and thermistor mounts.
Those in the second category are used in the following sit-
uations:

Reduction of signal variations as a function of fre-
quency. The variations here are caused by a high
10 Attenuators
Figure 11. T/Pi fixed attenuator configuration. (a) T section. (b)
Pi section.
VSWR. The attenuator provides a reduction in these
variations and a better match.

Reduction in frequency pulling (changing the source
frequency by changing the load) of solid-state sources
by high reflection loads.
Figure 12. T/Pi fixed attenuator construction.
Types
Based on construction, they are available in coaxial, waveg-
uide, and strip line configurations. The various types are:
1. Waveguide vane
2. Rotary vane (fixed)
3. Directional coupler
4. T or Pi
5. Lossy line
6. Distributed resistive film
Coaxial Fixed Attenuators. T or Pi configurations are
most commonly used both at low and high frequencies. At
low frequencies, normal wirewound resistors are used. At
high frequencies, thin film resistors are used. Figures 11
and 12 show T and Pi fixed attenuators. Thin-film resis-
tors designed for microwave frequencies are used, in place
of carbon resistors. These resistors employ a nichrome alloy
film on a high-quality ceramic substrate to ensure a firmly
bonded film with low-temperature coefficients. This type of
construction makes the resistors extremely stable at high
frequencies. The skin effect of these resistors is excellent,
used extensively the microwave applications.
The T and Pi configuration is obtained by placing the
resistors in series on the center conductor and in shunt,
contacting both the center and outer conductor. Thus, the
T configuration with one shunt flanked by two series re-
sistors and the Pi configuration with one series flanked by
two shunt resistors can be fabricated. The series resistors
in the T and Pi configuration have less than 1 W capacity,
thereby severely limiting the use at high-power applica-
tions, unless an elaborate heat sinking is provided. Power
attenuators usually have huge sinks to handle high-power
applications.

Figure 13. Fixed resistive card attenuator configuration.
Figure 14. Fixed RF attenuator.
Resistive Card Attenuator. In a fixed dissipative,
waveguide-type resistive card attenuator, the card is
bonded in place (Figure 13). It is tapered at both ends
to maintain a low-input and low-output VSWR over the
useful waveguide band. Maximum attenuation per length
is obtained when the card is parallel to the E field and
at the center, where the TE10 mode is maximum. The
conductivity and the dimensions of the card are adjusted,
by trial and error, to obtain the desired attenuation, which
is a function of frequency. The attenuation increases with
increase in frequency. In power applications, ceramic-type
absorbing materials are used instead of a resistive card.
RF Fixed Attenuators
Figure 14 shows a commercial RF fixed attenuator whose
specifications are shown below:
Average Power, W 5 A series of fixed attenuators are mechanically arranged
Peak Power, W 125
Attenuation, dB 1, 6, 10, 20, 30
Frequency, GHz DC-4, 4-6
VSWR 1.15:1, 1.20:1
Tolerance, dB ±0.30, ±0.50, ±0.75
Fixed Fiber optic Attenuators
Fiber optic attenuators are engineered and manufactured
with continuous light absorbing metal-ion doped fiber.
Metal-ion fiber optic attenuators offer better feed-back
reflection and noise performance than other attenuators
based on spliced fiber, air-gap or offset-fiber designs. The
salient features of these attenuators are:
Frequency:
Attenuation:
Step size: 1 dB, 10 dB, 1 dB, respectively, for the above range
VSWR: 1.20, 1.25, 1.40, 1.50 for the above frequency range 1.25, 1.30, 1.45, 1.60 for the above frequency range
Connectors:
Height:
Depth: 79 mm (3.1 in.) (excludes shaft and knob)
Width: 65, 65, 118 mm (2.6, 2.6, 4.7 in.) for the above three attenuation ranges
Attenuators 11
Figure 15. Fixed single-mode, fiber optic attenuator.
Environmentally stable over temperature, humidity,
and vibration
High performance and low polarization dependent loss
(PDL)
Simple plug-in style enables rapid deployment
Wavelength independent: 1310/1550nm
The specifications of a commercial, fiber-optic, fixed,
single-mode attenuator is given below. Figure 15 shows a
typical sample.
Technology Type Doped Fiber
Attenuation, dB 1–10, 15, 20
Return Loss, dB >50, typically 55
Attenuation accuracy ±0.5 for 1-5 dB; ±10% for > 6 dB
Operating Temperature, ◦ C −40 to 75
VARIABLE ATTENUATORS
Variable attenuators have a range, such as 0 dB to 20 dB,
0 dB to 100 dB, and so on. The variation can be continuous
or in steps, obtained manually or programmably.
Step Attenuators
to offer discrete step variation. The fixed attenuators are
arranged in a rotatable drum or in a slab for switching be-
tween contacts. This arrangement provides discrete values
of attenuation in each position and a high reliability fac-
tor. The step size can be 0.1 dB, 1 dB, or 10 dB. Stationary
coaxial contacts provide the input and output of the de-
vice. These are used in applications requiring broadband
flatness with low VSWR and satisfactory resettability over
ranges from 0 to 120 dB. Their application range is dc to
18 GHz.
Figure 3 shows a commercial manual step attenuator.
A typical data sheet looks as follows:
Manual Step Attenuators
Figure 3 shows manual step attenuator. A typical data
sheet looks as follows:
0 to 4, 0 to 8, 0 to 12.4, 0 to 18 GHz
0 to 9, 0 to 60, 0 to 69
N/SMA; St. St.
83 mm (3.3 in.)
12 Attenuators

Continuously Variable Attenuators Digital Step Attenuator

Figure 4 shows a continuously variable attenuator. Typical 50, RF digital step attenuators are available with the fol-
specs are: lowing specifications. Fig. 17 shows a functional schematic
Frequency: 1 GHz to 18 GHz, 1 W av./1 kW PK diagram.
Connectors: St. St., M, F; type N, SMA
Zero loss: typically 0.5 dB to 1 dB Number of Bits 6
Attenuation: 0 to 9, 0 to 60, 0 to 69 dB Range, dB 0.5 dB steps to 31.5
Frequency, GHz DC to 4.0 GHz
The various types of continuously variable attenuators Programming Interfaces Flexible, serial and parallel
Insertion Loss, dB 1.5
are:
Return Loss (DC −2.2 GHz) 20 dB

Lossy wall
Moveable vane (Flap)
Rotary vane
Variable coupler Programmable Attenuators
Absorptive type
These are rapid switching attenuators with high accuracy
Coaxial resistive film and repeatability, useful for remote and computerized
Variable T applications. Switching speeds can be as low as 30 ns.
Waveguide below cutoff (Piston) Two varieties of the programmable attenuators are the
step-controlled and voltage-controlled types. The attenu-
Variable Fiber Optic attenuator ation is varied by controlling the electrical signal applied
to the attenuator. These signals can be in the form of
The specifications of a commercial, variable, fiber-optic, either a biasing current or binary digit. The biasing can be
single- and multi-mode attenuator is given below. pulses, square waves, or sine waves. A typical data sheet
Back-Reflection > 30 dB, >50 dB, >60 dB
for coaxial programmable step attenuator is as follows:
Attenuation Range 2 to 80 dB
Resolution 0.01 dB up to 10 dB, 0.1 dB up to 30 dB Frequency: dc to 40 GHz
Wavelength 400–1625 nm Attenuation: 0 dB to 11 dB, in steps of 1 dB
Fiber type Single mode, multimode Maximum VSWR: 1.3 GHz to 12.4 GHz
Temperature Range, ◦ C −35 to 70 1.7 GHz to 34 GHz
1.8 GHz to 40 GHz
Insertion loss: 0.8 dB + 0.04 GHz
0 dB setting
Digital Attenuators
Repeatability: 0.03 dB
Digital attenuators provide more than one step in attenua- Power rating average: 1W
tion. It depends on number of bits, LSB, attenuation range Peak: 50 W
and power rating. Fig. 16 shows the functional schematic Maximum pulse width: 10 µs
of a commercial, 5-bit, 15.5 dB, DC-GHz, digital attenua- Life: 5 million cycles per section minimum
Solenoid
tor that can be used for broadband communication system
Voltage: 20 V to 30 V
applications which require accurate, fast and low power de-
Speed: <20 ms
vices. This is made of patented silicon On Insulator (SIO) Power: 2.7 W
CMOS manufacturing technology, which provides the per- RF connectors: 2.4 mm, F
formance of GaAs with the economy and integration capa- Shipping weight: 291 g (10.3 oz)
bilities of conventional CMOS.

Figure 16. Bit digital attenuator.

 Attenuators 13

Figure 17. Digital step attenuator.

Solid State Programmable Attenuators

Solid state programmable attenuators operating from 30
MHz to 3 GHz are introduced in the market. They have
low insertion loss and high switching speed. Specifications
for two types are given below.
Model 1 Model 2
Frequency Range 30 MHz to 3 GHz 400-2000 MHz
Impedance,  50 50
Attenuation 0 to 127 in 1 dB steps 0 to 127 in 1 dB steps
Attenuation Steps, dB 1, 2, 4, 8, 16, 32 and 64 1, 2, 4, 8, 16, 32 and 64
VSWR 1.6:1 max
Accuracy
1, 2, 4, 8 dB ± 0.3 dB to 2 GHz −0.25 dB for 1, 2, 4, 8 dB
1, 2, 4, 8 dB ± 0.4 dB to 2 GHz −0.35 for 16 and 32 dB
16, 32, 64 dB ± 0.5 dB or 3% (whichever is higher) −0.50 dB for 64 dB
Max error ±0.5 dB or 2%
Insertion Loss 6 dB max to 2000 MHz 5 dB max t@ 1 GHz
8 dB max to 3000 MHz 7 dB max t@ 2 GHz
RF Input power ±15 dBm operating +10 dB
±30 dBm no damage
Switching Speed 20 µs max 2 µs
Operating Temperature 0 to 70◦ C 0 to 70◦ C
Programming TTL low for thru path TTL low for “0” setting
TTL high for attenuation TTL high for pad setting

Lossy Wall Attenuator Moveable Vane (Flap) Attenuator

Figure 18 shows lossy wall variable attenuator. It con-
sists of a glass vane coated with a lossy material, such as
aquadag or carbon. For maximum attenuation the vane is
placed in the center of the guide’s wide dimension, where
the electric field intensity is the maximum. A drive mecha-
nism with a dial then shifts the vane away from the center
so that the degree of attenuation is varied. This needs cali-
bration by a precise attenuator. To match the attenuator to
the waveguide, the vane can be tapered at each end; usu-
ally a taper of λg/2 provides an adequate match. Thus, it
is frequency sensitive and the glass dielectric introduces
appreciable phase shift.
Attenuation may also be obtained by inserting a resis-
tive element through a shutter. The plane of the element
lies in the distribution of the electric field across the wide
dimension of the waveguide and the result is a degree of
attenuation, which increases with the depth of insertion.
However, due to the discontinuity, there is reflection of
energy.
Figure 19 shows a waveguide variable, dissipative attenu-
ator. The card enters the waveguide through the slot in the
broad wall, thereby intercepting and absorbing a portion of
the TE10 wave. The card penetration, and hence the atten-
uation, is controlled by means of the hinge arrangement
to obtain variable attenuation. The ratings are typically
30 dB and widely used in microwave equipment. However,
the attenuation is frequency sensitive and the phase of the
output signal is a function of card penetration and hence
attenuation. This may result in nulling when the attenu-
ator is part of a bridge network. Since it is not simple to
calculate the loss in dB, this type of attenuator has to be
calibrated against a superior standard. To overcome these
drawbacks, a rotary vane attenuator is used.
Rotary Vane Attenuator
The rotary vane attenuator is a direct reading precision
attenuator which obeys a simple mathematical law, A =
−20 log cos2 θ = −40 log cos θ dB. As such, it is frequency
independent, which is very attractive criterion for an at-
tenuator. A functional diagram illustrates the operating
14 Attenuators
Figure 18. Lossy wall attenuator configuration. (a) Minimum attenuator. (b) Maximum attenuator.
Figure 19. Movable vane (flap) variable attenuator configura-
tion.
principle of this attenuator. It consists of three sections
of waveguide in tandem as shown (Figure 20). A rectan-
gular to circular waveguide transition containing a hori-
zontal attenuator strip is connected to a rotatable circular
waveguide containing an attenuator strip. This in turn is
connected to a circular to rectangular waveguide transition
containing a horizontal attenuator strip.
The incoming TE10 mode is transformed into the TE11
mode in the circular waveguide by the rectangular to cir-
cular waveguide transition with negligible reflections. The
polarization of the TE11 mode is such that the e field is
perpendicular to the thin resistive card in the transition
section. As such, this resistive card has a negligible effect
on the TE11 mode. Since the resistive card in the center can
be rotated, its orientation relative to the electric field of the
incoming TE11 mode can be varied so that the amount by
which this mode is attenuated is adjustable.
When all the strips are aligned, the electric field of the
applied wave is normal to the strips and hence no current
flows in the attenuation strips and therefore no attenu-
ation occurs. In a position where the central attenuation
strip is rotated by an angle θ, the electric field of the ap-
plied wave can be resolved into two orthogonally polarized
modes; one perpendicular and one parallel to the resistive
card. That portion which is parallel to the resistive slab
will be absorbed, whereas the portion, which is polarized
perpendicular to the slab, will be transmitted.
Variable Coupler Attenuator
These are basically directional couplers where the attenu-
ation is varied by mechanically changing the coupling be-
tween two sections. This is accomplished by varying the
spacing between coupled lines. These attenuators have a
large range, high power handling capability, and retain cal-
ibration over a range of ambient conditions. They have a
higher insertion loss at lower frequencies (Figure 21).
Absorptive Attenuator
Figure 22 shows an absorptive variable attenuator. Atten-
uation is obtained by using a lossy dielectric material. The
TEM electric field is concentrated in the vicinity of the cen-
ter strip of the stripline. When the absorbing material is in-
serted in the high field region, a portion of the TEM wave is
intercepted and absorbed by the lossy dielectric. Thus, the
attenuation increases. Since the characteristic impedance
of the stripline changes with the dielectric material in-
sertion, the SWR tends to increase as the attenuation in-
creases. To minimize this, the ends of the lossy material
are tapered to provide a smooth impedance transforma-
tion into and out of the lossy section. SWR values of >1.5

Figure 20. Rotary vane attenuator configuration.
Figure 21. Variable coupler attenuator configuration.
Figure 22. Absorptive-type variable attenuator configuration.
are possible over a limited frequency range. In general, the
SWR deteriorates at low frequencies. The attenuation in-
creases with increasing frequency for a fixed setting. This
is another disadvantage, since this makes the calibration a
cumbersome procedure. Compensation techniques are oc-
casionally used to reduce this variation with frequency.
Coaxial Resistive Film Attenuator
Figure 23 shows a coaxial resistive film attenuator. In this
configuration, if r is the RF resistance per unit length, by
adjusting the length l, the series resistance R = rl of the
center conductor is changed; thus, the attenuation is vari-
able. If I is the conduction current on the center conductor,
the voltage drop is V = RI = Irl. If Ei is the input voltage,
then the output voltage is E0 = Ei − rlI and the attenuation
is
Attenuators 15
Figure 23. Coaxial resistive film attenuator configuration.
Figure 24. Variable T attenuator.
Figure 25. Coaxial variable cutoff attenuator configuration.
Variable T
The variable T attenuator is the same as the fixed attenu-
ator except that the resistors are variable (Figure 24). All
the three resistors are variable simultaneously to give good
input/output VSWR.
Waveguide Below Cutoff or Piston Attenuator
The simple principle of cutoff below frequency is used in
the piston or the cutoff attenuator. The cylindrical waveg-
uide used is operating at a frequency below cutoff. For high
power applications, a coaxial configuration is used. A sim-
ple waveguide cutoff attenuator is shown in Figure 25. A
metal tube, acting as a waveguide, has loops arranged at
each end to couple from the coaxial lines into and out of
the waveguide. One of the loops is mounted on a movable
plunger or hollow piston so that the distance between the
16 Attenuators

Figure 26. (a) Standard variable piston attenuator and (b–d) calibration curves. (b) Typical VSWR
versus frequency of SPA-2 attenuator with frequency. (c) Typical variation of insertion loss of SPA-2
attenuator with frequency in a 50- system. (d) Deviation versus indicated incremental insertion.
Typical deviation from linearity for the model SPA-2 operating frequency is 30.0 MHz.

Figure 28. CDMA handset transmit application.

loops is variable. The input coupling loop converts the in-

coming TEM wave into the TE11 mode in the circular guide,
while the output loop converts the attenuated TE11 mode
back to TEM. The attenuator can be matched by adding Z0
resistors. The attenuation is given as:

Figure 27. Laser piston attenuator. (Courtesy of Weinschel As-

sociates.)

Figure 29. Functional block diagram of a digital cellular phone,
using variable attenuators.
Figure 30. Pin diode high-frequency equivalent circuit.
Figure 31. Typical RF resistance versus dc bias current for
HPND-4165.
Figure 32. Series pin RF attenuator or switch. (a) Complete circuit. (b) Idealized RF equivalent circuit.
Attenuators 17
By choosing the diameter such that λc < λo , and hence
f/fc < 1, the above equation reduces to
This was obtained from
(If λoc = 10 cm, and λo is much greater (10 times or more
(in this case, 1 m or more)), the attenuation increases 5.45
dB per cm of outward movement of the plunger.)
The sliding cylindrical conductors allow length l to be
varied, which varies the attenuation, since attenuation
A = αl, where α is the attenuation constant due to the cutoff
effect, and l is the length of the circular guide. The cutoff
wavelength is, λc = 1.706D, where D is the diameter of the
waveguide. Thus the attenuation is:
or
The attenuation is independent of frequency; it depends
only on the physical dimensions and hence can be accu-
rately controlled by maintaining tight tolerances on the
length and diameter of the circular guide. With A linearly
proportional to l, the cutoff attenuator is easily calibrated
and hence particularly useful as a precision variable atten-
uator.
The cutoff attenuator is one of the most widely used pre-
cision variable attenuators in coaxial measurement equip-
ment. This is a reflective-type attenuator, since the waveg-
uide is essentially dissipationless. The signal is reflected
rather than absorbed. For higher attenuation (>10 dB),
the SWR at both ports is very high (>30). This can cause
problems in certain applications.
This type of attenuator is very useful, but has the dis-
advantage of high insertion loss. Due to cutoff nature,
the insertion loss is high, up to 15 dB to 20 dB. If this
loss is overcome, piston attenuators are one of the most
18 Attenuators

Figure 33. Shunt pin RF attenuator or switch. (a) Complete circuit. (b) Idealized RF equivalent circuit.

Figure 34. Constant impedance pin diode attenuators. (a) Pi attenuator. (b) Bridged T attenuator. (c) T attenuator. (d) Resistive line
attenuator.

Figure 35. Fixed Pi attenuator.

 Attenuators 19

accurate attenuators available. Values of 0.001 dB/10 dB tor for leveling and amplitude modulating a RF signal.
of attenuation over a 60 dB range are common. A good in- These attenuators provide local oscillator, IF, and RF
put/output match is obtained using inductive loops within signal level control throughout communications, measure-
the waveguides. Excellent matching is obtained over the ment, and control circuits. One example is the reduction
entire range of attenuation due to inductive loop coupling. in the output of a receive mixer in a Code-Division Multi-
Figure 26 shows a commercially available standard vari- ple Access (CDMA) base station prior to the IF amplifier.
able piston attenuator and the various calibration curves. Also, to provide one step of transmit level control with lit-
It contains an accurately dimensioned tube acting as a cir- tle degradation of the noise figure (NF), it could be used in
cular waveguide, below cutoff TE11 mode. Typical specifi- a CDMA handset transmit chain between the mixer (up-
cations are (Courtesy of Weinschel Associates): converter) and the bandpass filter (Figure 28). Since the
Frequency: 30 MHz
attenuator is purely passive, it produces no additive noise
Mode: TE11 cutoff and the NF is essentially its insertion loss. Even in the
Range: 0 dB to 120 dB attenuator mode, the effect on the noise figure would be
12.5 dB zero insertion loss minimal.
VSWR: 1.2 max in 50  system In Personal Communication Service (PCS) systems, the
Connectors: Type-N, panel mounted base stations may be fed from multiple picocells that are
Accuracy: 0.01 dB from 0 dB to 15 dB physically separated from it by up to 100 feet or more of
0.005 db/10 dB from 15 dB to 100 dB coaxial cable. The signal levels coming into the base sta-
0.01 dB/10 dB from 100 dB to 120 dB tion will vary depending on the cable length and individ-
Resolution: 0.001 dB direct reading digital indicator
ual transponder power. It is desirable to keep the signals
at uniform levels coming into the base station; to do so,
Laser Piston Attenuator. Figure 27 shows a laser piston it may be necessary to attenuate the stronger signals. An
attenuator. The heart of this instrument is a precise attenuator can be easily inserted for this purpose.
stainless steel circular waveguide, operated in the TE11 The upper end of a receiver’s linear dynamic range is
cutoff mode. Laser light, traveling between two antennas determined by the largest signal it can handle without be-
in the center of the circular waveguide, measures directly ing overdriven and producing unacceptable levels of distor-
the changes in actual separation of the two antennas along tion caused by device nonlinearities. Inserting an attenu-
the same path as the TE11 mode propagates. The laser
signal is converted to attenuation in dB and corrected
for skin effect, the refractive index of air, and changes
due to temperature of the waveguide and pressure. The
specifications are (Courtesy of Weinschel Associates):
Operating frequency: Dual frequency 1.25 MHz + 0.05 MHz and 30.0 MHz + 0.1 MHz
Waveguide mode: TE11 , below cut-off
Incremental attenuation range: 100 dB
Min insertion loss: 10 dB nominal
Resolution: 0.0001 dB for  dB, 0.002 dB for total loss
Attenuation readout: Front panel 7 digit LED or remotely via IEEE bus
Connectors: Type N jacks
VSWR (input and output): 1.2 max at 1.25 and 30 MHz in 50  system
Accuracy: 0.001 dB/10 dB + 0.0005 dB between 15 and 115 dB total loss
Weight: Net: 77 kg (170 lb); shipping: 145 kg (320 lb)
Accessories: Power supply, controller, calibration tape, two power cables, one
22 wire power cable, Instruction and Maintenance manual

ACTIVE ATTENUATORS
PIN Diode Attenuators
The normal diode junction consists of a p-type material
brought together with an n-type material to form the fa-
miliar PN junction. The PIN diode is distinguished from
the normal PN junction type by an area called an intrinsic
region sandwiched between the p+ doped and n+ doped sil-
icon layers. This intrinsic layer has almost no doping and
thus has a very large resistance. When a variable dc con-
trol voltage forward biases the PIN diode, the dc bias or
control current causes it to behave as almost a pure resis-
tance at RF frequencies, with a resistance value that can
be varied over a range of 1  to 10 K. As the bias current
is increased, the diode resistance decreases. This relation
makes the PIN diode ideally suited as a variable attenua-
ator before a low noise amplifier (LNA) in the presence of
strong, in-band signals produces better reception by pre-
venting them from overdriving the receiver’s front end.
This effectively shifts the dynamic range upward by the
amount of attenuation. It must be remembered that when
inserted into the system, the attenuator will also present
a load and a source impedance to the previous and suc-
ceeding stages, respectively, hence the importance of the
attenuator impedance match.
RF variable attenuators are used to control the trans-
mitting and receiving signal power levels to prevent
strong–weak adjacent signals from seriously degrading the
bit error rate (BER) of digital mobile communication sys-
tems, such as TDMA or CDMA. Figure 29 shows the basic
RF functional block diagram of a typical digital cellular
phone system, where variable attenuators are required.
20 Attenuators
Characteristics of the Pin Diode
The approximate high frequency equivalent circuit of a PIN
diode is shown in Figure 30. Here, RI is the effective resis-
tance of the intrinsic (I) layer, given by
where IDC is the dc bias current in mA, and k and x are
device-dependent empirical constants. Although shown as
a variable, this resistance is constant with respect to the RF
signal. The high frequency resistance function is plotted in
Figure 31 for the Hewlett Packard HPND-4165 diode. For
a specific diode design, the exponent X is usually a con-
stant. For the HPND-4165, X is typically 0.92. The con-
stant k and therefore, RI , however, are highly dependent
on the fabrication and process control and its value can
vary by as much as 3:1 from diode to diode. For analog ap-
plications, such as a variable attenuator, where repeatable
attenuation with bias current is desired, the variation of
RI must be controlled. The HPND-4165 is precisely con-
trolled in manufacturing, and resistance values at specific
bias points are specified and the slope of resistance versus
bias matched with narrow limits. The specification limits
of these parameters are shown in Table 4.
Applications
The PIN diode is ideally suited to switch and attenuate
RF signals. Since the PIN diode is a RF variable resistor,
the logical application is that of a variable attenuator. This
attenuator may be either a step or a continuously variable
type. Two of the simplest circuits are the series and shunt
attenuators shown in Figures 32 and 33.
Attenuation in the series PIN circuit is decreased (more
power appears at the output) as the RF resistance of the
diode is reduced. This resistance is reduced by increasing
the forward bias control current on the diode. The oppo-
site occurs for the shunt configuration. The attenuation in
the shunt circuit is decreased when the RF resistance of
the diode increases because less power is absorbed in the
diode and more appears at the output. If the control bias is
switched rapidly between high and low (zero) values, then
the circuit acts simply as a switch. When used as a switch,
the attenuation that exists when the switch is “on” is called
insertion loss. The attenuation provided when the switch
is “off” is called isolation. If the diode is a pure resistance,
the attenuation for the series and shunt circuit can be cal-
culated as
where Z0 = RG = RL = circuit, generator, and load resis-
tance, respectively. In reviewing these equations, it is seen
that the attenuation is not a function of frequency but only
a ratio of circuit and diode resistances, which is a great ad-
vantage. As the bias on the diode is varied, the load resis-
tance experienced by the source also varies. These circuits
are generally referred to as reflective attenuators because
they operate on the principle of reflections.
Many RF systems require that the impedance at both
RF ports remain essentially constant at the design value
Z0 . Four such circuits and their PIN diode counterparts are
shown in Figure 34. All four circuits operate on the princi-
ple of absorbing the undesired RF signal power in the PIN
diodes. In circuits (a), (b), and (c), the control current varia-
tion through each diode is arranged in such a way that the
impedance at both RF ports remain essentially constant at
the characteristic impedance (Z0 ) of the system while the
attenuation can be varied over a range of less than 1 dB to
greater than 20 dB. In circuit (d), the input impedance is
kept constant by using a distributed structure with a large
number of diodes. The impedance variation of each diode
is also shaped so that the diodes in the center of the struc-
ture vary more than those near the ports. The resulting
tapered impedance structure results in an essentially con-
stant impedance at the ports, while the overall attenuation
can be varied up to a range of 40 dB to 80 dB, depending
on the length of the structure.
PIN diode Pi attenuator in Figure 30(a) is often selected
when designing a variable attenuator. The basic Pi fixed
attenuator is shown, along with its design equations, in
Figure 35. Shunt resistors R1 and the series resistor R3
are set to achieve a desired value of attenuation, while si-
multaneously providing an input and output impedance
which matches the characteristic impedance Z0 of the
system.
Three PIN diodes can be used as shown in Figure 36 to
replace the fixed resistors of the Pi circuit to create a vari-
able attenuator. The attenuator provides good performance
over the frequency range of 10 MHz to over 500 MHz. How-
ever, the use of three diodes as the three variable resistors
in a Pi attenuator results in a complex unsymmetrical bias
network. If resistor R3 is replaced by two diodes, as shown
in Figure 37, the resulting attenuator is symmetrical and
the bias network is significantly simplified. V+ is a fixed
voltage, and Vc is the variable control voltage, which con-
trols the attenuation of the network. The only drawback to
using two series diodes in place of one is the slight increase
in insertion loss. Resistors R1 and R2 serve as bias returns
for series diodes D2 and D3 . Resistors R3 and R4 are cho-
sen to match the specific characteristics of the PIN diodes
used. Properly selected, they will provide the correct split
of bias current between series and shunt diodes required to
maintain a good impedance match over the entire dynamic
range of attenuation.
The PIN diode variable attenuator is an excellent cir-
cuit used to set the power level of an RF signal from a volt-
age control; used widely in commercial applications, such
as cellular telephones, PCN (personal communication net-
works), wireless LANs (local area networks), and portable
radios.
GaAs NMESFET Attenuator
The GaAs N-semiconductor metal semiconductor field ef-
fect transistor (NMESFET) is used in microwave attenu-
ator designs. The metal–semiconductor FET (MESFET) is
a field effect transistor that operates on the principle that
the gate-to-source voltage controls the drain current. The
MESFET is a device extension of a JFET, where the gate
 Attenuators 21

Figure 36. Three-diode Pi attenuator.

Figure 37. Wideband four-diode  attenuator.

Figure 38. MESFET T attenuator.

22 Attenuators
Figure 39. MESFET Pi attenuator.
structure is a Schottky MN (metal–N semiconductor) junc-
tion.
In GaAs NMESFET attenuator designs, the devices are
operated either in the linear region where the device is
modeled as a voltage variable resistor or they operate as
an on/off switch in conjunction with thin-film nichrome re-
sistors to provide appropriate levels of attenutation. The
channel resistance of the GaAs NMESFET is known to fol-
low the classical theory for a FET in the linear region of
operation. With the FET biased in the linear region, the
resistance varies inversely to the gate voltage as shown
below:
where Vg = gate bias voltage (V), Vp = pinch-off voltage
(V), and Rdso = channel resistance () with Vg = 0 V.
As the gate voltage approaches the pinch-off voltage, the
resistance becomes very high (relative to 50 ). Conversely,
as the gate voltage approaches zero, so does the channel re-
sistance. For each attenuator configuration, two indepen-
dent gate bias voltages are used; one to control the series
MESFETs and one to control the shunt MESFETs. The T
attenuator configuration is shown in Figure 38, with one
voltage controlling the series resistance arms, and another
the shunt resistance arm. Table 5 gives the resistor values
of the series and shunt resistances in a Z0 = 50  system.
The channel resistances of the MESFETs are matched as
closely as possible for these resistances. A matched condi-
tion at the input and output port to Z0 occurs when,
The resulting matched attenuation is
The Pi attenuator configuration is shown in Figure 39, with
one voltage controlling the shunt resistance arms, and an-
other the series resistance arm. Table 6 gives the values
of the series and shunt resistances for different levels of
attenuation in a Z0 = 50  system. Shunt resistor R1 and
series resistor R2 provide and input and output impedance
which matches the characteristic impedance Z0 = 50  of
the system, while setting the desired level of attenuation.
The design equations are:
where K is the input to output voltage ratio.
GaAs NMESFET digital attenuators allow a specific
value of attenuation to be selected via a digital n bit pro-
gramming word. In these designs, the NMESFET oper-
ates as an on/off switch and is used in conjunction with
nichrome thin-film resistors to provide the desired level
of attenuation. Figure 40 shows the circuit configurations
used for individual attenuator bits. The switched bridged
T attenuator consists of the classical bridged T attenuator
with a shunt and series FET. These two FETs are switched
on or off to switch between the two states. The attenuation
in dB is given by
where Z2 0 = R1 R2 .
The performance is determined by the FET character-
istics in the on and off states and the realizability limit on
required resistance values and their associated parasitics.
The switched T or Pi attenuators are similar in principle
to the switched bridged T attenuator except for the circuit
topology. These attenuators are normally used for high at-
tenuation values. To obtain smaller values of attenuation,
the thin-film resistors are replaced with appropriate chan-
nel resistances.
There are GaAs NMESFET digital RF attenuators on
the market with excellent performance, in both step and
continuously variable types. The variable or programmable
class allows a specific value of attenuation to be selected
from an overall range via an N-bit programming word.
They are more flexible than step attenuators, as they al-
low any amount of attenuation to be set, but the cost is
greater circuit complexity. Both types have a bypass state
when no attenuation is selected, and the attenuation is just
the insertion loss of the device. An example of each type is
presented.
The RF Microdevices RF 2420 is a multistage mono-
lithic variable or programmable attenuator which has as

Figure 40. GaAs digital attenuator circuit configurations.
Figure 41. RF 2420 functional block diagram.
attenuation programmability over a 44 dB range in 2 dB
steps. The attenuation is set by five bits of digital data. A
functional block diagram of the RF 2420 is shown in Fig-
ure 41. It consists of five cascaded, dc-coupled attenuator
sections, each with its own logic translator. The logic trans-
lator converts the one-bit control signal, which uses logic
levels approximating standard TTL logic, to the voltage lev-
els required to switch the attenuator stage FETS. The RF
input and output signal lines are biased at approximately
VDD , and therefore external dc blocking capacitors are re-
quired. An external VDD bypass capacitor is also required.
A functional schematic of the RF portion of one atten-
uator section is shown in Figure 42. A MESFET bridges
the series resistor in a resistive Pi attenuator, and two
more MESFETs are connected as a double-pole single-
throw (DPST) RF switch connecting the shunt branches
of the Pi attenuator to RF ground. In the bypass state, the
bridge MESFET is in its high conductance state, and the
DPST switch is open, so that the Pi-attenuator is effec-
tively removed from the circuit. When the attenuator bit
is selected, the bridge MESFET is put into its low con-
ductance state or cutoff state and the shunt FETs are put
into their on state, so that the Pi-attenuator is connected
into the RF series path. This attenuator has only moderate
Attenuators 23
Figure 42. Functional schematic of RF 2420 (one attenuator
section).
variation across a broad band of operation from 100 MHz
to 950 MHz, as illustrated in Figure 43.
Furthermore, the attenuation varies smoothly and con-
sistently with attenuator switch settings. Other features
of the device are single 3 V to 6 V supply operation, and
4 dB insertion loss, and the input and output have a low
VSWR 50  match. All these features make the RF 2420 an
excellent component for communications systems that re-
quire RF transmit power control by digital means. Typical
applications are in dual mode IS-54/55 compatible cellu-
lar transceivers and TETRA systems. Figure 44 shows the
complete schematic details of the RF 2420 being employed
in a typical RF/IF switching attenuator application.
The RF Microdevice RF 2421 is a GaAs MESFET
switched step attenuator. It has a single-step digitally con-
trolled attenuation of 10 dB. A functional block diagram
of the device is shown in Figure 45. The supply voltage
range required is 2.7 V to 6 V dc. The input and output of
the device have a low voltage standing wave ratio (VSWR)
50  match and the RF output can drive up to +16 dBm. It
has 1.0 dB of insertion loss over the specified 500 MHz to
3 GHz operating frequency range. The resistors are nickel
chromium (nichrome) and provide excellent temperature
stability. The RF ports are reversible, which means the in-
put signal can be applied to either port. The attenuation
control pin has an internal pull-down resistor which causes
the attenuator to be turned off when it is not connected.
Figure 46 illustrates the RF 2421 being used to set the RF
signal level in a communications system.
24 Attenuators

Figure 43. Attenuation and frequency response characteristics of RF 2420 5-bit digital RF
attenuator.

Figure 44. RF 2420 RF/IF switching attenuator schematic.

MOSFET Attenuators
Active voltage attenuators have many useful applications
in analog integrated circuit design. Some of the applica-
tions are in the feedback loops of finite gain amplifiers and
in the input stages of transconductance amplifiers. In dis-
crete circuit design, the most popular way to design a finite
gain amplifier with precisely controlled gain, high linear-
ity, and low output noise is to use operational amplifier and
a voltage attenuator in the feedback loop. Here the voltage
attenuator consists of two resistors connected in series as
Figure 45. RF 2421 functional block diagram.
shown in the classical noninverting and inverting op amp
gain configurations of Figure 47. Resistor attenuators are
 Attenuators 25

Figure 46. RF 2421 single-step 10 dB attenuator application.

Figure 47. Op-amp noninverting (a) and inverting (b) gain configurations.

not useful in integrated circuit design because of their large VI Input voltage
areas, low input impedance, large power dissipation, and Vo Output voltage
parasitic capacitances, and precise resistance values can- VDD Drain supply voltage
not be realized. VB Bias supply voltage 1
Three MOS active voltage attenuator configurations VBB Bias supply voltage 2
VTON = VTON1 = VTON2 Zero bias threshold voltage of
useful for the realization of finite gain amplifiers in mono-
M1 and M2
lithic circuits are presented. The attenuators are two
VT2 Threshold voltage of M2 due
single-input attenuators and a summing attenuator that to body bias effect
has two inputs. These attenuators are simple in structure, V1 Input voltage 1
consisting only of MOSFETs. Therefore, they are easy to V2 Input voltage 2
fabricate in standard CMOS semiconductor processes. The γ Body effect parameter
attenuation factor is precisely controlled over a wide range φ Barrier potential
of gains because it ideally depends only on the ratios of the ID Drain current
dimensions of the MOSFETs. W Width of channel
Attenuator I, shown in Figure 48 is an active linear L Length of channel
W1 , W2 Width of channels 1, 2
voltage attenuator consisting of two n-channel MOSFETs
L1 , L2 Length of channels 1, 2
fabricated in a common substrate. The capability to fabri-
K Device constant, µn CoX
cate the MOSFETs in a common substrate has several ad- µn Mobility of electron
vantages. First, both n-channel and p-channel attenuators CoX Gate oxide capacitance per
can be monolithically fabricated in a standard CMOS pro- unit area
cess. Second, the required area of the attenuator is much
smaller. As seen in Figure 48, the substrate is common for The zero bias threshold voltage of both MOSFETs is
both MOSFETs and is connected to the source of the bot- VTON1 = VTON2 = VTON . The proper operating conditions will
tom transistor M1. The circuit operates as a linear voltage be met, provided
attenuator when M1 is in the ohmic region and M2 is in
the saturation region.
The operating conditions of the MOS attenuators in this where
section are derived as follows: The list of symbols used are:
26 Attenuators
Figure 48. (a) Circuit and block diagram of attenuator I consisting of two n-channel MOSFETs, and (b) block diagram of amplifier
consisting of an op-amp and attenuator.
Since M1 is operating in the ohmic region and M2 is in the
saturation region, the drain current of each MOSFET is
given by
and
Equating the two drain currents, the relationship between
V1 and Vo is obtained as
where
If each MOSFET in the attenuator is fabricated in a
separate substrate and the substrate of each MOSFET is
connected to its source (γ = 0), the dc transfer characteristic
relating VI and Vo becomes a linear equation:
where α is the small signal attenuation factor.
In this case, α is
Eq. (70) is a special case of Eq. (68), when the bulk effect
term due to γ is ignored. When the substrate is separate,
the small signal attenuation factor from Eq. (71) is pre-
cisely determined by width/length ratios. If the substrate
is common, the relationship between the input and output
is still very linear as given by Eq. (68) even though the
equation appears to be a nonlinear quadratic.
Figure 49 shows the typical dc transfer characteristic of
the attenuator consisting of M1 (12 × 10 µm2 ) and M2 (3
× 10 µm2 ) when the substrate is common (γ = 0) and VDD
= 5 V. The dc transfer characteristic exhibits a high degree
of linearity for the input range 2 V to 5 V. The small signal
attenuation factor (α) which is the slope of the dc transfer
Figure 49. Dc transfer characteristic of attenuator I (α =
0.07824).
characteristic is 0.07824 at an input quiescent voltage of
3.5 V.
A finite gain amplifier consisting of an ideal op amp and
attenuator I in the feedback loop is shown in Figure 48.
Since the op amp is assumed ideal,
or
That is, the dc transfer function of the amplifier is the in-
verse function of the dc transfer function of the attenuator
in the feedback loop. Thus, the transfer function between
 
the input V I and the V o of the amplifier is given by Eq. (68)
 
when Vo is replaced by V I and VI by V o . The small signal
voltage gain
is the reciprocal of the attenuator’s attenuation factor in
the feedback loop. Figure 50 illustrates the dc transfer
characteristic of the finite gain amplifier.
Two slightly different linear inverting voltage attenua-
tor configurations consisting of two n-channel MOSFETs
are shown in Figure 51. These circuits operate as a linear
inverting voltage attenuator when both transistors are in
the saturation region. Assuming the zero bias threshold of
both of the MOSFETs is VTON , the condition will be met,

Figure 50. Dc transfer characteristic of amplifier (AV = 1/α =
12.78).
provided
and
Under this condition, the drain currents of the transistors
are given by:
where
Since the two drain currents are the same for the circuit,
the dc transfer function relating VI and Vo is found by
equating Eqs. (77) and (64):
where
If γ = 0 in Eq. (80) which corresponds to the case of circuit
(b) in Figure 51 where the substrate is separate, the dc
transfer characteristic reduces to a linear equation,
In this case, the small signal attenuator factor is
which is precisely determined by the width/length ratios
of the MOSFETs. From Eqs. (80) and (68), it is noted that
the output dc operating voltage is controlled by VB , inde-
pendent of the attenuation factor.
The dc transfer characteristic between VI and Vo calcu-
lated from Eq. (80) for the common substrate case, R1 =
0.1149 and VB = 3.993, and the dc transfer characteristics
calculated from Eq. (82) for the separate substrate case, R1
= 0.1 and VB = 3.449 are shown in Figure 48–52 for the
Attenuators 27
Figure 51. Circuit and block diagrams of linear inverting voltage
attenuators consisting of two n-channel MOSFETs.
Figure 52. Dc transfer characteristics of attenuator II linear in-
verting voltage attenuators.
range restricted by Eq. (76). The parameter values (γ =
0.525 V1/2 , φ = 0.6 V, and VTON1 = VTON2 = VTON = 0.777 V)
were used in the calculation. The dc transfer function given
by Eq. (80) for the common substrate case appears non-
linear, but the degradation from linearity due to practical
values of γ is not significant. The small signal attenuation
factor α, the slope of transfer characteristic in Figure 52, is
−0.1. The high degree of linearity supports the usefulness
of both configurations in precision attenuator or finite gain
amplifier applications.
Figure 53 shows a finite gain amplifier with attenuator
II in the feedback loop of an op amp. Assuming the op amp
is ideal,
The transfer function of the amplifier is the inverse func-
tion of the transfer function of the attenuator in the feed-
back loop. The dc transfer function of the amplifier is given

by Eq. (80) when VI is replaced by V o and Vo is replaced
 
by V I . If the substrate is separate, VI replaces V o and Vo

replaces V I in Eq. (82); then
where the small signal attenuator factor α = −R1 .
A summing attenuator is necessary to realize versatile
multiple input finite gain amplifiers in integrated circuits.
28 Attenuators
Figure 53. Amplifier consisting of op-amp and attenuator II in
the feedback loop.
Figure 54. Circuit and block diagram of summing attenuator.
Figure 54 shows a two-input active linear inverting volt-
age summing attenuator which consists of two attenuators
cascaded. For the summing attenuator, VBB is used to con-
trol the output dc operating voltage and input signals are
designated as V1 and V2 .
As for the inverting attenuator, the summing attenua-
tor works when all the MOSFETs M1–M4 are operating in
the saturation region. The dc transfer characteristics are
found by equating the drain currents in the saturation re-
gion for each transistor. Assuming the zero bias threshold
voltages for the four MOSFETs are matched at VTON , the
four transistors are in the saturation region provided,
By equating the drain currents of M3 and M4 given by
and
where
The dc transfer function between V2 and VB is obtained as
where
Similarly, it can be shown, that the dc transfer function
between V1 and Vo is obtained as
where
If γ = 0 in Eqs. (92) and (80), the equations become linear.
This is realized if each transistor is fabricated in a separate
substrate and the substrate of each transistor is connected
to its source. In this case, the attenuation factors are given
by α1 = −R1 , and α2 = −R2 . Even when γ = 0, which is the
case when the substrates are common, the transfer char-
acteristics between V1 and Vo and between V2 and Vo are
nearly linear as shown in Figure 57 for practical values of
γ. In the calculation of Figure 55, γ = 0.5255 V1/2 , φ = 0.6 V,
and VTON = 0.777 V were used which are standard for a 2 µ
CMOS process and R1 = 0.1149 and R2 = 0.1290 were set
such that the small signal attenuation factors for V1 and
V2 are both −0.1. The operating points were set by VBB =
5.712 V such that VoQ = 2.5 V (VBQ = 3.993 V) when V1Q =
V2Q = 2.5 V.
Summing and subtracting amplifier configurations us-
ing the inverting attenuator and the inverting summing
attenuator are shown in Figure 56.
Circuit (a) in Figure 56 functions as a summing ampli-
fier and the circuit (b) functions as a subtracting amplifier,
with controllable weights. Assuming ideal op amps and at-
tenuators, we obtain
Equating V− and V+ , the output is given by
From Eq. (98), the circuit in Figure 56(a) is a summing
amplifier with a wide range of available gain from each
input. Similarly, for the circuit in Figure 56(b), we obtain
Equating V+ and V− , the output is given by
From Eq. (99), the circuit in Figure 56(b) is a subtracting
amplifier with a wide range of available gain for each input.
The active attenuator and the active summing atten-
uator have many desirable characteristics such as small
size, nearly infinite impedance, low power dissipation, and
precisely controllable attenuation ratio with excellent lin-
earity. These attenuators and the finite gain amplifiers
 Attenuators 29

Figure 55. Dc transfer characteristics of summing attenuator.

Figure 56. (a) Summing amplifier. (b) Subtracting amplifier.

obtained from these attenuators and op amps will find in-

creased applications in analog integrated circuits.

Noise
Noise in a communication system can be classified in
2 broad categories, depending on its source. Noise gen-
erated by components within a communication system,
such as resistive, extender, and solid-state active devices,
comprise internal noise. The second category, external
noise, results from sources outside a communication sys-
tem, including atmospheric, man-made, and extraterres-
trial sources.
External noise results from the random motion of a
charge carrier in electronic components. The three types
include:

1. Thermal noise: caused by random motion of free elec-
trons in a conductor or semiconductor excited by ther-
mal agitation;
2. Shot noise: caused by random amount of discrete charge
carriers in such devices as thermionic tubes or semicon-
ductors in devices
3. Flicker noise: produced by semiconductors by a mecha-
nism not well understood and is more severe the lower
the frequency.
Atmospheric noise results primarily from spurious ra-
dio waves generated by the natural discharges within the
atmosphere associated with thunderstorms. Man-made
noise sources include high voltage power line discharge and
computer-generated noise in electric motors.
Figure 57. Variable attenuator using GaAs MESFET
CONT+/CONT− = VDD/GND in attenuation mode and
CONT+/CONT− = GND/VDD in through mode.
Other noises include:

Generation–recombination noise: due to free carriers
being generated and recombining in semiconductor
material. They are random and can be treated as a
shot noise process.

Temperature-fluctuation noise: the result of the fluc-
tuating heat exchange between a small body, such as
a transistor, and its environment due to the fluctua-
tions in the radiation and heat conduction processes.
30 Attenuators
Figure 58. Microstrip–slot-line attenuator on a silicon substrate
with an override ferrite slab.
ADDITIONAL TYPES
Figure 57 shows a 4 dB step, 28 dB variable attenuator for
1.9 GHz personal handy phone system transmitter fabri-
cated using silicon bipolar technology with fT of 15 GHz.
The GaAs MESFET variable attenuator is configured with
resistive Pi attenuators and GaAs switches as shown. Step
accuracy within 1.2 dB and total vector modulation error
of less than 4% were realized for −15 dBm output. The
attenuator consumes 21 mA with 2.7 V power supply and
occupies 1.1 mm × 0.5 mm. This unit is being developed.
This shows the technology trend.
Figure 58 shows the top view and cross section of a pro-
totype optical microwave attenuator that can be controlled
by illuminating the silicon substrate. The maximum atten-
uation is 30 dB using laser diode illumination. It is a mi-
crostrip line whose substrate consists of silicon and ferrite
slabs. The ferrite slab is overlaid on the microstrip. There
is a slot on the ground plane under the strip. A white light
from a xenon arc lamp with a parabolic mirror is focused
by a lens to the silicon surface through the slot. The in-
tensity of the light is not uniform along the slot direction.
Due to the light, electron–hole pairs are induced and the
permittivity and conductivity of the silicon are changed,
which vary the phase and amplitude of the microwave.
With 240 mW optical power illumination, an attenuation in
the range of 17 dB to 26 dB was obtained in the frequency
range from 8 GHz to 12 GHz.
Figure 59. Switchable-network attenuator.
Figure 60. Switchable-element attenuator.
Figure 61. Switchable attenuator.
Switchable Attenuators
Switchable attenuators allow users to vary the attenuation
for various applications, such as in production, field, and
bench-top applications. They offer mechanically or electri-
cally controllable attenuation levels. There are two types
of switchable attenuators: (1) switched-network attenua-
tors, and (2) switched element attenuators. In switched-
network attenuators, PIN diode switches are used to de-
velop two or more paths for changing attenuation values.
Once developed, it can be used to obtain several attenua-
tion values. In switched-element attenuator, the resistive
elements have multiple values. Either a pi pad, a tee pad
or a reflection attenuation configuration can be used as the
initial network in which the resistive elements are vari-
able. Typically FETs are used for switching and the set-up
is implemented in MMIC format.
A typical data sheet for one model is shown in Table x
Frequency DC-0.5 GHz
dB 0 to 102 by 1 dB
Impedance 50 
VSWR 1.2:1 to 0.5 GHz
Accuracy ±0.5 dB to 0.03 GHz ±1 dB to 0.5 GHz
Insertion Loss 0.3 dB max to 0.1 GHz 1.5 dB max to 0.5 GHz
Average Power 0.5 W (25◦ C)
Peak Power 750 W, 3 µs pulse
Connectors BNC
Audio Attenuators
Audio attenuators need compact design to reduce noise and
give audio volume controls with accurate attenuation and
tracking (0.05 dB). Resistor network using surface mount
resistors for short signal path and very low inductance and
stray capacitance seem to be successful in achieving the
end results. Shown in Fig. 62 is a surface mount audio at-
tenuator with 24 steps. The series resistor networks consist
of 23 non-inductive, low noise surface mount film resistors.
The layout of the PC boards and the surface mount resis-
tors reduce the signal path compared to normal leaded re-
sistors. The surface mount film resistors also have very low
 Attenuators 31

Model 1 Model 2
Power, W 50 150
Impedance,  50 50
Frequency Range, GHz DC to 18 DC to 8
Attenuation 3, 6, 10, 20, 3, 6, 10, 20, 30, 4
30, 4
Connection N N M/F
Max VSWR
4 GHz 1.20:1
Figure 62. Stereo attenuator. 8 GHz 1.30:1
18 GHz 1.35:1

ACKNOWLEDGMENT

The author is grateful to Mr. Grant Richards of ECET

Dept., Purdue University for his help with fixed and vari-
able fiber optic attenuators.

Figure 63. High power attenuator—Model 1.

BIBLIOGRAPHY

Reading List

F. G. Ananasso “A Low Phase Shift Step Attenuator using PIN

Figure 64. High power attenuator—Model 2.
series inductance and very low stray capacitance, allowing
a wide bandwidth.
High Power Attenuators
Shown in Fig. 63 is the group of high power attenuator, a
new addition to commercial, fixed attenuators. This model
features a frequency range of DC-18 GHz with an input
power rating of 50 W CW. Standard attenuation values are
3, 6, 10, 20, 30 and 40 dB and the VSWR is rated at 1.35:1 at
18 GHz. A robust mechanical package with stainless steel
Type N connectors is designed to meet the requirements
of MIL-A-3933. Applications include high power amplifier
design and test environments as well as defense and radar
requirements.
For applications including high power radar, amplifier
test, telecommunication labs and MRI calibration another
new type, high power, fixed attenuators were introduced
in the market (Figure 64). This type features a frequency
range of DC-8 GHz with an input power rating of 150 W
CW. Standard attenuation values are 3, 6, 10, 20, 30 and
40 dB and the VSWR is rated at 1.20:1 @ 4 GHz and 1.30:1
@ 8 GHz. The specifications of the above two models are
shown below.
Diode Switches”, IEEE Trans. Microwave Theory Tech., MTT-
28 (7): July 1980.
P. S. Bochert FET Attenuator, 0-1 GHz Applied Microwave and
Wireless, Spring 1996.
R. G. Brown et al. Lines, Waves, Ana Antennas, New York: The
Ronald Press Co. 1973.
R. S. Elliot An Introduction to Guided Waves and Microwave Cir-
cuits, Englewood Cliffs, NJ: Prentice-Hall, 1993.
Engineering staff of the Microwave Division, Microwave Theory
and Measurements, Hewlett-Packard Co., 1962.
S. C. Harsany Principles of Microwave Technology, Englewood
Cliffs, NJ: Prentice Hall, 1997.
M. R. Haskard Thick Film Hybrids—Manufacture and Design,
New York: Prentice-Hall, 1988.
Hewlett Packard Application Note 1048, A Low-Cost Sur-
face Mount PIN Diode π Attenuator, Hewlett Packard Co.,
1996.
Hewlett Packard Application Note 922, Applications of PIN
Diodes, Hewlett Packard Co., 1997.
IEEE Std 474-1973, Specifications and Test methods for Fixed and
Variable Attenuators, DC to 40 GHz.
T. Koryu Ishii Microwave Engineering, New York: Harcourt Brace
Jovanovich, Publishers, 1989.
Joon-Yu Kim R. L. Geiger “MOS Active Attenuators for Analog ICS
and Their Applications to Finite Gain Amplifiers”, Proceedings-
IEEE International Symposium on Circuits and Systems,
1994.
Joon-Yu Kim R. L. Geiger “Performance Characterization of an
Active Attenuator Using Two Cascaded MOSFETS”, Proceed-
ings of the 36th Midwest Symposium on Circuits and Systems,
1993.
Joon-Yu Kim R. L. Geiger “Characterization of Linear MOS Active
Attenuator and Amplifier” Elec. Lett., 3 (7): March 30, 1995.
Joon-Yu Kim R. L. Geiger “An Inverting MOS Active Attenuator for
Monolithic Applications”, Proceedings of the Midwest Electro-
Technology Conference, 1993.
32 Attenuators

T. S. Laverghetta Practical Microwaves, Englewood Cliffs, NJ: Digital attenuator, www.psemi.com, Aug 2006
Prentice-Hall, 1996. Audio attenuators, www.dact.com, Aug 25 2006
R. LaVerne Libbey Video Attenuator using a Multiplier and FET, Parallel, digital attenuator, www.mysolservices.com, Sep 04 2006
A Publication of RCA, New Jersey: 1975.
Switchable attenuators, www.trilithic.com, Sep 04 2006
RF Microdevices, RF 2420 Programmable Attenuator Data Sheet,
Solid state programmable attenuators, www.trilithic.com, Sep 04
1997.
2006
RF & Microwave Test Accessories Catalog, HP, 1997/98.
RF Microdevices Technical Application note TA 0027 Integrated,
Single Step, 10 dB Attenuator for Power Control Applications,
RAJI SUNDARARAJAN∗
1997.
EDWARD PETERSON
RF Microdevices, RF 2421 10 dB Switched Attenuator Data Sheet,
ROBERT NOWLIN
1997.
Arizona State University East,
MIL-HDBK-216, Military handbook, R. F. Transmission Lines and
Mesa, AZ
Fittings, Section 14, Attenuators, Nov. 1976. ∗ Currently at ECET Dept.,
MIL-A-3933E, Military specification, attenuators, fixed, general
Purdue University
specification for 1985.
MIL-A-3933E, Suppl. 1, Military specification, Attenuators, Fixed,
General Specification for 1985.
S. Otaka et al. “A 1.9 GHz Si-Bipolar variable Attenuator for PHS
Transmitter”, IEEE J. Solid State Circuits, 32 (9): 1424–1429,
September, 1997
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phone and Telegraph Corp., New York.
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D. Roddy Microwave Technology, Englewood Cliffs, NJ: Prentice-
Hall, 1986.
S. E. Saddow C. H. Lee “Scattering Parameter Measurements on
Optoelectronic Attenuator”, IEEE MIT-S Digest, 1994.
H. W. Sams Reference Data for Radio Engineers, 7th ed., 1985,
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G. E. Schafer A. Y. Rumfelt “Mismatch Errors in Cascade-
Connected Variable Attenuators”, IRE Trans. Microwave The-
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H. Shimasaki S. Matsuda M. Tsutsumi “Phase compensation in
an Optically Controlled Microwave attenuator”, IEEE MTT-S
Digest, 1703–1706, 1997.
V. A. Suprynowicz Electrical and Electronics Fundamentals—An
Applied Survey of Electrical Engineering, New York: West Pub-
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A Vector Attenuator for Feedforward Amplifier and RF Predistor-
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Systems, Modulation, and Noise, New York: Wiley, 1988.
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Prentice-Hall, 1987.

Additional Reading List

Attenuators, www.electronics-tutorials.com
www.microwaves101.com/encyclopedia/attenuators.cfm, Aug 28
2006
Rf Fixed attenuators, www.e-meca.com/rf-attenuators.htm, Aug
25 2006
Fiber optic attenuators, www.Telect.com, Aug 25 2006
Fiber optic fixed and variable attenuators, www.fiberdyne.com, sep
2006
High power attenuators, www.Trilithic.com, Aug 28 2006
218 BANDPASS FILTERS

BANDPASS FILTERS
A bandpass filter is an electrical device that passes the spec-
tral components of an electrical signal around a certain fre-
quency f 0 with little or no attenuation, while it mostly rejects
other spectral components (Fig. 1). Bandpass filters are com-
mon building blocks of many electronic systems. They find
applications in diverse fields such as communications, audio,
instrumentation, and biomedicine. To illustrate a typical ap-
plication of a bandpass filter, consider the simultaneous
transmission of n signals in one communications channel us-
ing frequency multiplexing techniques. The signals can share
the same channel because their individual frequency spectra
are shifted so that they occupy nonoverlapping regions (or
bands) of the frequency spectrum. Frequency modulation is
used to shift the baseband spectrum of each of the signals
(centered originally at zero frequency or dc) to center frequen-
cies f 01, f 02, . . ., f 0n (Fig. 2). In order to avoid overlapping, the
center frequencies must have a minimum separation of at
least the bandwidth of the signals. Bandpass filters are used
on the receiver side in order to select or ‘‘filter out’’ only one
of the signals transmitted in the channel. A process called
demodulation is used to shift the spectrum of the selected sig-
nal back to baseband (to a zero center frequency).

T( f )

BW
A

fp1 f0 fp2 f

Figure 1. Frequency response of ideal bandpass filter.

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

A
f01 f02 f03 f0n f Figure 4. Pole–zero plot of second-order bandpass filter.
Figure 2. Spectrum of n signals in a communication channel.
IDEAL BANDPASS FILTERS
Ideally, a bandpass filter is characterized by its center fre-
quency f 0 and its bandwidth BW. The bandwidth is defined in
terms of upper and lower passband edge frequencies f p1 and
f p2, respectively, and given by BW ⫽ f p2 ⫺ f p1. Typically, f p1
and f p2 specify frequency points at which the gain decreases
by a factor 兹2. The frequency response plot of Fig. 1 shows
the gain A as a function of frequency f of an ideal bandpass
filter. An important parameter of a bandpass filter is its selec-
tivity factor SF, which is expressed by SF ⫽ f 0 /BW. The selec-
tivity is a measure of the filter’s ability to reject frequencies
outside its passband. It is also a relative measure of the recip-
rocal bandwidth. Highly selective filters (also denoted nar-
rowband filters) have a bandwidth that constitutes only a
small fraction of f 0. Narrowband filters with large selectivity
factors (e.g., SF ⬎ 50) are commonly required in communica-
tion systems. For ideal bandpass filters, the frequency range
is divided into three regions: the passband region where the
gain is approximately constant ( fp1 ⬍ f ⬍ f p2) and the lower
and upper stopbands ( f ⬍ f p1 and f ⬎ f p2, respectively), where
the gain is ideally zero or the attenuation or reciprocal gain
is infinite. The ideal bandpass filter has sharp transitions be-
tween the passband and the two stopbands.
PRACTICAL BANDPASS FILTERS
The typical frequency response of a practical passband filter
is shown in Fig. 3. It has a relatively constant gain possibly
with fluctuations (ripple) with maximum amplitude Ap within
the passband. The passband edge frequencies f p1 and f p2 are
defined, in this case, as the minimum and maximum frequen-
cies with gain, A ⫺ Ap. The center frequency f 0 is commonly
T( f )
BW
A Ap
As
fs1 fp1 f0 fp2 fs2 f
Figure 3. Practical bandpass filter.
BANDPASS FILTERS 219
s-plane
the center of geometry of the passband edge frequencies: f 0 ⫽
兹f p1 f p2. In a practical filter, there is a gradual transition be-
tween the passband and the upper and lower stopbands.
Therefore, besides the passband and stopband there are also
two transition bands. Two frequencies f s1 and f s2, each de-
noted lower and upper stopband edge frequencies, respec-
tively, define the stopbands in a practical bandpass filter.
Stopband regions are characterized by a small gain with max-
imum value, 1/As, where As is the stopband attenuation. Pass-
band ripple Ap and stopband attenuation As are commonly
specified in a logarithmic unit denoted decibel according to
As (dB) ⫽ 20 log As. Practical bandpass filters can have mono-
tonic decreasing gain or equal gain fluctuations (ripple) both
within the passband and the stopband.
MATHEMATICAL CHARACTERIZATION
OF A BANDPASS FILTER
The simplest bandpass filter is the second-order filter. It is
characterized by the input–output relation or transfer func-
tion:
j BW f
T( f ) = (1)
f 20 + j BW f − f 2
This transfer function is a complex function with magnitude
and phase. The magnitude (frequency response) obtained
from Eq. (1) has the form
BW f
|T ( f )| = √ (2)
( f − f 2 )2 + (BW f )2
2
0
The pole–zero plot (in the complex frequency plane also
known as the s-plane) of a second-order bandpass filter is
shown in Fig. 4. It has a zero at the origin (shown as a circle)
and two complex conjugate poles (shown as marks). The selec-
tivity is associated with the relative distance of the poles from
the imaginary axis in the s-plane. The distance from the ori-
gin to the poles corresponds to the center frequency in radi-
ans, 웆0 ⫽ 2앟f 0.
BANDPASS FILTER IMPLEMENTATIONS
Depending on the center frequency and selectivity, there exist
several possible implementations of bandpass filters. In gen-
eral, the higher the selectivity and the center frequency, the
more complex the filter becomes. Two very important aspects
are: miniaturization and compatibility with very large scale
integration (VLSI) systems technology. These have dictated
220 BANDPASS FILTERS

R
vOUT

vIN + L C
–

–
Figure 5. Second-order RLC bandpass filter. vIN +
– –
+ vOUT
+
the evolution of bandpass filters and of most other electronic
circuits. Compatibility refers to the fact that the filter can be
fabricated on a CMOS integrated circuit as a part of a VLSI Figure 7. Second-order switched-capacitor filter.
system in CMOS technology. This technology allows the fabri-
cation of very complex analog and digital electronic systems
with hundreds of thousands or even millions of transistors on RC Active Filters
a single integrated circuit. CMOS compatibility is crucial in
In the 1960s, RC active filters using operational amplifiers,
order to reduce manufacturing costs and to increase system
capacitors, and resistors led to the implementation of highly
reliability. Automatic tuning and low power consumption are
selective low-cost filters without inductors (Fig. 6). These fil-
also important aspects for bandpass filters. Tuning consists
ters are known as RC active filters (2). They constituted the
in the process of adjusting the filter’s response to compensate
first step toward filter miniaturization. RC active filters were
for unavoidable fabrication tolerances in the values of the fil-
mass produced in miniaturized form using thin-film and/or
ter elements. These tolerances cause the filter’s response to
thick-film technology. These filters still required individual
deviate from the ideal (nominal) response. Low power is im-
tuning. This was automatically done using computer-con-
portant for portable equipment like cellular phones and bio-
trolled laser beams that burn sections of resistor material to
implantable devices.
change the resistance and achieve the desired filter response.
Within a short time, RC active filters replaced most inductor-
Passive Filters
based filters in the audio frequency range.
For many years, most filters were exclusively implemented as
passive RLC circuits using resistors, inductors, and capacitors Monolithic Analog Filters
(1). Figure 5 shows an example of a resonant RLC circuit used
In the mid 1980s, RC active filters were replaced by fully inte-
as a bandpass filter. This filter is characterized by the trans-
grated switched-capacitor filters (3). These use only switches,
fer function of Eq. (1) with f 0 ⫽ 1/2앟 ⭈ 1/ 兹LC and BW ⫽
operational amplifiers, and capacitors and can be fabricated
1/(CR). The transfer function of this circuit has the pole–zero
in CMOS VLSI technology (see Fig. 7). Switched-capacitor
plot shown in Fig. 4. Ceramic filters based on bulk electrome-
filters require no tuning and can operate at center frequencies
chanical resonance phenomena in piezoelectric materials
have been used in the radio frequency range specially for re-
quirements of high selectivity and accurate center frequency.
Inductors have several problems: they have large physical di-
mensions and cannot be integrated unless their value is very
–
small; they are temperature dependent; and their value is –
subject to large manufacturing tolerances. They also have + +
poor characteristics at low frequencies, and their value tends +
vIN + vout –
to change with time. RLC passive filters cannot be automati-
cally tuned at the manufacturing stage. Additionally, RLC
and ceramic filters are not compatible with CMOS VLSI tech-
nology. (a)

–
+
iIN + –
– –
– +
+ – iout
vIN + vOUT
– +
+
(b)

Figure 8. Second-order OTA-C bandpass filter: (a) voltage mode im-

Figure 6. Second-order RC active filter. plementation; (b) current mode implementation.

x(n) T T
x(n) T T a0
a0 a1 a2
+ – –
+ y(n)
+ +
b2
T T
(a)
up to a few hundred kilohertz. Starting in the mid 1970s sur-
face acoustic wave (SAW) filters—another family of filters—
were developed to implement filters for center frequencies
spanning from 10 to several hundred megahertz. These filters
are miniaturized filters that also require no tuning. They are
based on the controlled propagation of electromechanical
waves on the surface of a piezoelectric crystal with very small
dimensions. SAW filters are not compatible with CMOS tech-
nology. But because of their excellent performance character-
istics and low cost, they are currently being used to imple-
ment the intermediate frequency filter of most televisions.
Recently, electronically tunable elements in CMOS tech-
nology have allowed the integrated circuit implementation of
active filters for center frequencies up to a few tens of mega-
hertz. These filters are compatible with CMOS VLSI technol-
ogy. Most of these implementations are based on electroni-
cally tunable elements called operational transconductance
amplifiers (transconductors or OTAs) and include on-chip au-
tomatic tuning circuitry (4). The tuning circuit continuously
(or periodically) monitors the filter’s response and electroni-
cally adjusts the gain of the OTAs to tune the frequency re-
sponse of the bandpass filter. This family of filters is known
as OTA-C filters (see Fig. 8). They require no tuning and can
be integrated as part of a VLSI system (5). Figure 8a shows
a conventional ‘‘voltage mode’’ filter, while Fig. 8b shows a
‘‘current mode’’ filter where input, output, and intermediate
variables are represented by electrical currents rather than
voltages as it is done in conventional ‘‘voltage mode’’ filters
(6). In analog signal processing systems, the range above 100
MHz is still based, to a large exent, on passive RLC filters.
At these frequencies, high-quality, small-dimension inductors
are available. A very recent trend for the implementation of
high-frequency high-selectivity integrated analog filters is
based on microelectromechanical (MEM) structures, which
are based on electromechanical resonance. This approach has
shown potential for the implementation of bandpass filters
operating in the radio frequency range and with very high
selectivity factors similar to those achievable with ceramic
and SAW structures. These MEM-based filters, unlike the
SAW filters, are CMOS VLSI compatible.
Digital Filters
Currently, the availability of low-cost digital circuitry in VLSI
systems has made it convenient to replace many traditional
BANDPASS FILTERS 221
a1 a2
+
+ y(n)
+ +
b1
Figure 9. Second-order digital filters (a)
(b) FIR filter; (b) IIR filters.
analog functions by digital ones and to process signals in the
digital domain rather than in analog form. Successful imple-
mentation of digital filters for center frequencies up to a few
megahertz, as stand-alone units or as part of a VLSI system
has recently been achieved. Digital filters are fully integrated
filters that are compatible with CMOS technology and require
no tuning (7). Their characteristics ( f0, BW, or Q) can be eas-
ily reprogrammed for many different applications. A digital
filter consists basically in various addition, multiplication,
and delay operations applied to an ordered sequence of num-
bers that represent the digitized values of a signal. These dig-
itized values are obtained by sampling the signal at regular
time intervals (t ⫽ T, 2T, 3T, . . .) and transforming the sam-
pled values into binary codes. In digital filters, present val-
ues x(n) ⫽ x(nT) and past values x(n ⫺ 1) ⫽ x((n ⫺ 1)T),
x((n ⫺ 2) ⫽ x((n ⫺ 2)T) . . . of both input and output signals
are processed. The steps performed on these digitized values
lead to an output sequence y(n), y(n ⫺ 1), y(n ⫺ 2), . . ., which
can be transformed by means of a digital-to-analog converter
into a filtered output signal y(t). A digital filter is, therefore,
an algorithm or sequence of mathematical steps that relates
input and output sequences by means of multiplication, addi-
tion, and delay operations. A digital filter is mathematically
characterized by a difference equation. There are two types of
digital filters: finite impulse response (FIR) filters, where the
current value of the output signal y(n) depends only on the
current and past values of the input signal, and infinite im-
pulse response (IIR) filters, where the current value of the
output signal depends also on past values of the output sig-
nal. For example, the difference equation of a second-order
FIR filter is expressed by
y(n) = a0 x(nT ) + a1 x(n − 1) + a2 x(n − 2) (3)
while the difference equation of a second-order IIR digital fil-
ter has the form
y(n) = a0 x(n) + a1 x(n − 1) + a2 x(n − 2)
(4)
− b1 y(n − 1) − b2 y(n − 2)
where a0, a1, a2, b1, and b2 are multiplying coefficients; x(n)
and y(n), stand for x(t ⫽ nT) and y(t ⫽ nT), are the current
values of the input and output signals; and x(n ⫺ 1), x(n ⫺
222 BAND-STOP FILTERS

2), y(n ⫺ 1), and y(n ⫺ 2) correspond to the two previous val-
ues of the input and output signals, respectively. The values
of the multiplying coefficients and the sampling frequency,
f s ⫽ 1/T, determine the selectivity and center frequency of the
digital filter and can be easily reprogrammed. Figures 9(a, b)
illustrate the block diagram of second-order FIR and IIR fil-
ters, respectively.
High-speed digital filters can be implemented using spe-
cial-purpose VLSI hardware in the form of digital signal pro-
cessors (6) or as relatively low-speed filters using software in
general-purpose digital systems such as computers or micro-
processors.

BIBLIOGRAPHY

1. A. B. Williams and F. J. Taylor, Electronic Filter Design Handbook:

LC Active and Digital Filters, New York: McGraw-Hill, 1988.
2. M. E. Van Valkenburg, Analog Filter Design, Forth Worth, TX:
Holt, Reinhart and Winston, 1982.
3. R. Schaumann, M. S. Ghausi, and K. R. Laker, Design of Analog
Filters: Passive, Active RC and Switched Capacitors, Englewood
Cliffs, NJ: Prentice-Hall, 1990.
4. J. Silva-Martinez, M. Steyaert, and W. Sansen, High Performance
CMOS Continuous-time Filters, Norwell, MA: Kluwer Academic
Publishers, 1995.
5. Y. P. Tsividis and J. O. Voorman, Integrated Continuous Time Fil-
ters: Principles Design and Applications, Piscataway NJ: IEEE
Press, 1992.
6. J. Ramirez-Angulo, E. Sanchez-Sinencio, and M. Robinson, Cur-
rent mode continuous time filters: two design approaches. IEEE
Trans. Circuits Syst., 39: 337–341, 1992.
7. R. Higgins, Digital Signal Processing in VLSI, Englewood Cliffs,
NJ: Prentice-Hall, 1990.

JAIME RAMIREZ-ANGULO
New Mexico State University

BAND-REJECT FILTERS. See BAND-STOP FILTERS.

222 BAND-STOP FILTERS

Atternuation (dB)
As

Ap

1
Normalized frequency

Figure 2. Normalized low-pass requirements.

at least As dB. In the passbands (below f 1 Hz and above f 2

Hz), the maximum attenuation is Ap dB. The bands from f 1
to f 3 and from f 4 to f 2 are called the transition bands. The
filter requirement is said to be geometrically symmetrical if
f 1 f 2 ⫽ f 3 f 4.
An approach to designing a circuit (a band-stop filter) with
a frequency response that satisfies the band-stop require-
ments shown in Fig. 1 is described below. It consists of two
steps: the approximation of the requirements by a transfer
function, and the synthesis of the transfer function.
In the approximation part of the design process, it is desir-
able to find a transfer function with a frequency response that
satisfies the band-stop requirements. To find that transfer
function, first convert the band-stop requirements into the
normalized low-pass requirements. For the case that the
band-stop requirements are symmetrical, the corresponding
normalized low-pass requirements are shown in Fig. 2. The
normalized passband frequency Fp ⫽ 1 and the passband at-
tenuation is Ap dB. The normalized stopband frequency is

f2 − f1
Fs =
f4 − f3

and the stopband attenuation is As dB.

With such low-pass requirements, we can obtain the corre-
sponding low-pass transfer function TLP(s). (See LOW-PASS FIL-
TERS for more information about how to obtain the transfer
BAND-STOP FILTERS function.) The band-stop filter transfer function TBS(s) is ob-
tained by making the transformation
A band-stop filter (also known as band-reject, band-elimina-



tion, or notch filter) suppresses a band of frequencies of a sig- TBS (s) = TLP (s)


nal, leaving intact the low- and high-frequency bands. A s= 2 Bs
s + (2π f ) 2
band-stop filter specification can be expressed as shown in 0

Fig. 1. In the stopband from f 3 Hz to f 4 Hz, the attenuation is

where B is the bandwidth of the band-stop filter defined as

B = 2π ( f 2 − f 1 )
Atternuation (dB)

As
and f 0 is the center frequency of the band-stop requirement
defined as
√ √
f0 = f1 f2 = f3 f4
Ap Ap
To use this method when the requirement is not symmetri-
f1 f3 f4 f2 cal, for the case that f 1 f 2 ⬎ f 3 f 4, we form a more stringent
requirement by either decreasing f 2 or increasing f 4, so that
Frequency (Hz)
the symmetrical condition is met. The band-stop transfer
Figure 1. Band-stop filter specification. function that satisfies the new requirements must also satisfy

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.
 BATCH PROCESSING IN COMPUTERS 223

the original requirements. In case f 1 f 2 ⬍ f 3 f 4, we either in- Compare with Eq. (1),
crease f 1 or decrease f 3 and then apply the same procedure.
A simple example is provided to illustrate this concept. For R12
a1 = 0, a2 = ,
the band-stop requirements As ⫽ 25 dB, Ap ⫽ 3.01 dB, f 1 ⫽ 1 R11 R21 R31C1C2
kHz, f 2 ⫽ 100 kHz, f 3 ⫽ 8 kHz, and f 4 ⫽ 12.5 kHz; the corre- 1 1 1
sponding normalized low-pass requirements are: As ⫽ 25 dB, b1 = + , b2 =
R31C1 R32C1 R22 R31C1C2
Ap ⫽ 3.01 dB, Fp ⫽ 1, and Fs ⫽ 22. Choosing a single-pole
Butterworth approximation, the low-pass transfer function
for the normalized low-pass requirements is Choose C1 ⫽ C2 ⫽ 1, R12 /R11 ⫽ K, R31 ⫽ R32. Solving for the
other values,
1
TLP (s) = Kb1 b1 2
s+1 R21 = , R22 = , R31 =
2a2 2b2 b1
which meets the stopband requirements easily. The band-stop
transfer function is obtained by the transformation
The impedance scaling method can be used to scale the values


1
of R and C into the practical ranges. In general, a higher-
TBS (s) =


order band-stop transfer function can be factorized into a
S+1 3 3
S= 2 2π (100×10 3−1×10 )s 3
s + (2π 100×10 ) (2π 1×10 ) product of biquadratic functions. Each of the biquadratic
function can be synthesized by using the Bainter or other cir-
which simplifies to cuits. By cascading all the circuits together, the band-stop fil-
ter is realized.
s2 + 3.948 × 109
TBS (s) =
s2 + 6.220 × 105 s + 3.948 × 109
BIBLIOGRAPHY
Note that the single-pole low-pass function has been trans-
formed to a two-pole band-stop function. The above band-stop 1. J. J. Friend et al., STAR, An active filter biquad section, IEEE
transfer function is in the so called biquadratic form, which Trans. Circuits Syst., CAS-22: 115–121, 1975.
is an expression of the form
2. S. A. Boctor, Single amplifier functionally tunable low-pass notch
s2 + a 1 + a 2 filter, IEEE Trans. Circuits Syst., CAS-22: 875–881, 1975.
(1) 3. G. Daryanani, Principles of Active Network Synthesis and Design,
s2 + b 1 s + b 2
New York: Wiley, 1976.
There are a number of ways to synthesize and biquadratic 4. J. R. Bainter, Active filter has stable notch and response can be
function as an active network, such as the Friend biquad cir- regulated, Electronics, 115–117, Oct. 1975.
cuit (1,5), the Boctor circuit (2), and the summing four-ampli- 5. G. Moschytz and P. Horn, Active Filter Design Handbook, New
fier biquad circuit (3,5). The Friend or Boctor circuit uses one York: Wiley, 1981.
operational amplifier. The summing four-amplifier biquad cir-
cuit is much easier to tune. When a1 ⫽ 0, the Bainter circuit CHIU H. CHOI
can be used. The Bainter circuit (4) is shown in Fig. 3. For University of North Florida
higher performance circuits, see Ref. 5 for the description of
different band-stop circuit topologies.
The transfer function is
BANDWIDTH EFFICIENCY. See MODULATION ANALYSIS
R12 FORMULA.
s2 +
Vout (s) BANG-BANG CONTROL. See NONLINEAR CONTROL SYS-
=
1 
R11 R21 R31C1C2
Vin (s) 1 1 TEMS, ANALYTICAL METHODS.
s2 + + s+
R31C1 R32C1 R22 R31C1C2 BANK BRANCH AUTOMATION. See BRANCH AUTO-
MATION.
BARCODES, TWO-DIMENSIONAL CODES, AND
R22 SCANNING EQUIPMENT. See MARK SCANNING
R12 EQUIPMENT.
C2
R11 BARE DIE PRODUCTS. See KNOWN GOOD DIE TECH-
R21 NOLOGY.
Vin – R31
+ –
+ +
BARIUM TITANATE MAGNETORESISTANCE. See
– Vout
MAGNETORESISTANCE.
C1 BATCHED I/O. See BATCH PROCESSING IN COMPUTERS.

R32

Figure 3. Bainter circuit.

454 BIPOLAR AND MOS LOGIC CIRCUITS
BIPOLAR AND MOS LOGIC CIRCUITS
Logic is the science that deals with the principles of reason-
ing. Reasoning can be either valid or faulty, and a statement
can be either true or false. In electronic circuits, this trans-
lates into a device being on or off or an output voltage being
high or low. The work of Claude Shannon, based on the ear-
lier theoretical work of George Boole, established an algebra
of logic. Boolean algebra describes logical operations on bi-
nary state variables such as and, or, and exclusive or, as well
as the invert (not) function. Electronic circuits, defined by the
Webster’s New Collegiate Dictionary, as ‘‘an assemblage of
electronic components: hookup,’’ implement each of the basic
J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.
logic functions, which in turn can be interconnected to achieve
more complex arithmetic or control operations.
BIPOLAR LOGIC CIRCUITS
Bipolar junction transistors (BJTs) along with resistors and
diodes can be used to create electronic circuits that perform
Boolean logic functions. Bipolar refers to transistors that
have two polarities of charge carriers inside: electrons and
holes. These were the first transistors developed commer-
cially, starting in 1949. Junctions of p-type and n-type semi-
conductors were formed from silicon with small amounts of
impurities to produce the BJT structure. Two types of BJTs
are possible: pnp and npn, which refer to the arrangement
and types of the semiconductor junctions.
Historical Background
The first bipolar logic circuits were implementation with dis-
crete transistors on small circuit boards or as hybrids. In
1956, the first integrated circuits (ICs) were designed, which
consisted of resistors, diodes, and bipolar transistors, all in-
terconnected on chip by metal lines. Bipolar logic ICs have
been designed in several styles or families, some of which are
obsolete today. The first logic families were resistor–
transistor logic (RTL) and diode–transistor logic (DTL).
Later, as the cost of adding transistors to a circuit became
secondary, the number of active devices (transistors) was in-
creased to replace the resistors and diodes.
Transistor–transistor logic (TTL) was introduced in the
early 1960s and was quickly accepted around the world, be-
coming the most popular logic family. Most mainframe com-
puters of the 1970s were designed based on TTL logic chips,
and only the TTL’s density and speed changed significantly
over the course of many years. Later, Schottky barrier diodes
(SBDs) were used to prevent saturation in the bipolar transis-
tors, which reduced power consumption and improved switch-
ing speed. Saturation in a BJT describes the condition when
the base-collector junction becomes forward biased and con-
ducts current. Saturated transistors slow down considerably.
TTL used a single 5 V power supply, which became the de
facto standard for logic circuits. Only recently has this begun
to change to 3.3 V. Digital circuits based on TTL are still
widely sold today. TTL held the largest market share until
the early 1980s, when complementary metal–oxide–silicon
(CMOS) began to overtake it.
For a period of time in the 1970s, integrated injection logic
(IIL), also known as merged transistor logic, was a successful
logic family. It promised the highest speeds and levels of inte-
gration. However, the processing complexity and the inferior
speed–power product, compared to modern emitter-coupled
logic (ECL) designs, have relegated IIL technology to histori-
cal interest.
ECL, a derivative of current-mode logic (CML), has been
popular for over two decades. It made its first commercial ap-
pearance in 1962, introduced by Motorola as MECL1, and
within a few years was capable of 1 to 2 ns propagation de-
lays. In CML, whose name derives from the current steering
realized by differential amplifiers, the transistors do not satu-
rate by design. ECL logic is fairly dense, since several differ-
ential amplifiers are stacked on top of each other and share a
single current source. ECL is used in high-speed computers

Vplus
Out
Vplus
R2
Out
R1
In Q1
0.1 V
0.75 V In
(such as the Crays), in instrumentation, and in communica-
tions. Typical propagation delays for ECL logic today are less
than 100 ps per gate, and the maximum frequency of opera-
tion is greater than 10 GHz.
Nonthreshold logic (NTL) is a relatively new nonsaturat-
ing logic family that uses common-emitter (CE) stages with
large emitter resistors to prevent saturation. The layouts of
some NTL designs are very small; others have achieved some
of the highest speed and speed–power records.
Bipolar CMOS (BICMOS) was introduced in the middle
1980s as an optimal technology containing both high-speed
and high-density devices. The current drive of bipolar transis-
tors could be used to drive long metal lines or large capaci-
tances, which metal–oxide–silicon (MOS) is poor at doing. On
the other hand, CMOS had made it possible to integrate very
large numbers of logic gates, and memory cells, on a single IC
chip, compared to bipolar.
Another new logic family, called current mirror control
logic (CMCL), is claimed to achieve the highest speed–power
product of any technology. It operates at less than 2 V and is
derived from CML by removing the current sources and re-
placing them with current mirrors.
Bipolar Logic Circuits Operation
The most fundamental property of logic circuits is that their
transfer characteristics (e.g., voltage transfer function from
input to output) are such that they clamp at the output. Their
gain is high enough so that a minimum input voltage swing
will causes the output to swing fully on or off. This limiting
action allows a large number of logic circuits to function si-
multaneously, for example in a microprocessor, without suf-
fering any errors. The amount of signal degradation that can
be tolerated at the input of a logic circuit is called its noise
immunity, and it is proportional to the circuit gain.
Vplus
A A
Out B B
Out
A B
Out = A Nor B
Figure 2. Resistor–transistor logic (RTL) nor gate. Timing wave-
forms show Boolean relationship.
BIPOLAR AND MOS LOGIC CIRCUITS 455
High output
Low output Figure 1. Simple inverter circuit and voltage transfer
curve.
Figure 1 shows a simple inverter circuit consisting of a
common emitter (CE) transistor with its load resistor R2, and
a current limiting resistor R1 at its input. Also shown is a
simplified voltage transfer curve. When the input voltage in-
creases from zero to the normal on voltage of the base-emitter
junction (Vbe, 0.75 V), the transistor begins to turn on and the
output level begins to drop. The low output voltage will be
reached when the transistor saturates, resulting in a level
close to zero (about 0.1 V or less). This voltage is lower than
what is needed to turn on the next stage, and therefore it is
a logic zero.
A simple RTL circuit is shown in Fig. 2 as well as curves
indicating changes in time at the inputs and the correspond-
ing output change. No limiting resistors are shown for the
inputs A and B, although these are normally necessary; they
serve the secondary purpose of preventing one transistor from
taking all the current coming from the power supply. RTL is
a saturating logic family, and its transistors take longer to
come out of saturation (turn off) than to go into saturation.
Therefore its rising output voltage occurs with more delay
than its falling voltage.
In Fig. 3, we show a two-input DTL nand gate. The input
threshold of this circuit is equal to two diode drops (2Vbe),
since the input voltage goes up one diode and down three di-
odes. Only when both inputs are above the turn-on threshold
does the output go low, corresponding to the nand function.
The advantage of DTL over RTL is that the inputs do not
draw any current when they are high, because of the reverse
bias at their diodes. The resistor at the base of the output
transistor speeds up its turnoff.
Vplus
Vplus
Out
Figure 3. Diode–transistor logic (DTL) nand gate. Output is high
for all input combinations except A ⫽ 1 and B ⫽ 1.
456 BIPOLAR AND MOS LOGIC CIRCUITS
Vplus
R2
R1 Q4
Q5
R5
Q1
Q2
A Out
B Q6
R3 R4
Q3
Figure 4. Schottky transistor–transistor logic (TTL) nand gate with
totem-pole output and squaring circuit.
The Schottky TTL nand gate shown in Fig. 4 has similar
operation to the DTL implementation except that the input
diodes have been merged into two emitters at the input tran-
sistor. The output stage is composed of a totem-pole configu-
ration driven by a phase-splitter transistor (Q2). The output
is pulled up by a Darlington connect pair. Schottky diodes
connected internally across base–collector junctions prevent
those transistors that might saturate from doing so. The addi-
tional two resistors and a transistor circuit connected at the
base of the output transistor (Q3, R3, and R4) are known as a
squaring circuit, and it is used to sharpen the voltage transfer
function. The TTL output levels are particularly troublesome,
since they require driving large capacitive loads and uncon-
trolled (impedance) transmission lines; they must also source
and sink current in a historically asymmetric way.
IIL circuits are similar to RTL circuits except that all resis-
tors are replaced by pnp current sources, realizing an all-
transistor design style. Figure 5 shows that the current
sources are applied to the inputs of transistors and that the
gates consist of the parallel connection of several transistors.
IDC
A and between signals B and BN, so that the emitter of Q1, for
IDC
Out
IDC
B
Figure 5. Integrated injection logic (IIL): pnp transistors make up
the current sources. All-transistor design.
GND
R1 R2
Q6
Q7
A Q1 Q2
Out
AN
B Q3 Q4 Outn
BN
VCS Q5 R4 R5
R3
VEE
CML
ECL
Figure 6. Emitter-coupled logic (ECL) and gate with full differential
inputs and outputs. The addition of an emitter follower turns CML
into ECL.
Because CE stages are loaded by current sources, the satura-
tion is light. The pnp’s are integrated with the npn’s in a sin-
gle tub. Multiple emitters on the pnp side further compress
the layout. One shortcoming of IIL was that it required spe-
cial processes to make npn transistors that could operate up-
side down, with the collector on top, and also special steps to
make pnp transistors.
ECL/CML circuits are based on the differential amplifier.
Figure 6 shows an ECL and gate consisting of two differential
amplifiers stacked on top of each other. The addition of emit-
ter follower outputs turns a CML circuit into an ECL circuit.
In the figure, the emitter followers are simply loaded by resis-
tors, but current sources are more commonly employed. At
the bottom of the differential amplifiers, transistors Q5 imple-
ments a current source that is biased from a common voltage
Vcs. Since the so-called tail current is constant, the amount of
voltage swing developed across load resistors R1 and R2 is
well controlled and saturation prevented. The bases of the dif-
ferential amplifiers connect to dc levels such that their base–
collector junctions do not saturate. There is normally a volt-
age difference of Vbe (a diode drop) between signals A and AN
example, makes the collector of Q3 be no lower than the base
of Q3. The and operation is verified by noting that only when
both Q1 and Q3 are on will the current flow into R1, making
the output OUTN low, and OUT high.
Although Fig. 6 shows fully differential inputs and out-
puts, it is common to use single-ended versions of both. This
requires connecting one side of each differential amplifier to
an appropriate threshold voltage level. These levels are usu-
ally generated by the same circuit that provides the bias to
the current sources, and are typically separated from each
 BIPOLAR AND MOS LOGIC CIRCUITS 457

GND Vplus

In M1
Q1
Q1 M2
D Q1N
DN Out
CKN
M3
CK Q2
VCS M4

VEE Figure 9. Standard BICMOS inverting buffer. All-transistor design

requires no resistors. Bipolar transistors provide high current drive
Figure 7. ECL latch. Outputs latch on CK high. for large (or unknown) loads.

other by diode drops. The bias circuit is often a bandgap volt-
age regulator, which is capable of operating with great immu-
nity from temperature and supply voltage variations.
An ECL latch is an interesting circuit that shows some of
the special characteristics of this logic family. Figure 7 shows
that two differential amplifiers are stacked on top of a third,
all three sharing the same current source. When current flows
through the input differential pair, on CKN high, the outputs
Q and QN simply follow the inputs D and DN. When CK se-
lects the current to flow though the differential pair on the
right, it latches to the voltage that was previously presented
at its inputs. This differential pair has its outputs cross-con-
nected to its inputs, and also connected to the collectors of the
input differential pair. The figure also shows emitter follow-
ers with constant current source loading.
Figure 8 shows a two-input nonthreshold logic gate. The
NTL transistors do not saturate, since the current demand is
proportional to the input voltage. However, this makes the
transfer function fairly linear, resulting in lower gain and a
soft voltage transfer curve. This is not desirable for logic cir-
cuits, but can be alleviated by adding parallel capacitors
across the emitter resistors. In NTL the maximum collector
current is predictable, and selected so that the logic voltage
swing does not saturate the next stage. Emitter followers be-
tween stages improve interstage loading and the ability to
drive more logic inputs (fanout).
As an example a standard BICMOS inverting buffer,
which can be used to drive large capacitive loads, is shown in
Fig. 9. The two npn transistors in combination can pull up
and pull down larger currents, and faster, than MOS devices
of similar area. The CMOS inverter, M1 and M2, drive the
top npn in opposite phase to the drive presented to the bot-
tom npn. The bottom npn is both buffered and kept out of
saturation by the n-channel MOS (NMOS) device connected
across its base and collectors. The CMOS inverter also drives
a fourth NMOS transistors, M4, that speeds the turnoff of the
bottom bipolar transistor.
An example of a current mirror control logic (CMCL) xor
gate can be seen in Fig. 10. The removal of current sources in
GND

A
Vplus Q
AN
QN

B
VREF

Q5
A B Out
Q6

–2 V
QN = A XOR B

Figure 8. Nonthreshold logic (NTL), including speedup capacitor. Figure 10. Current mirror control logic (CMCL) xor gate.
458 BIPOLAR AND MOS LOGIC CIRCUITS
Table 1.
Parameter BJT MOS
gm /I Highest, 1/VT ⫽ 1/(26 mV) 1/(250 mV)
1/f Best Poor
Voffset Very good, exp(Vbe /Vt) Poor (surface effects)
Rin Medium, base current Infinite
Rb Yes, limits Fmax No
Switch Not ideal Yes
Complementary Lateral PNP, 200 MHz PMOS, 40% speed
device
Ft Function of current Function of Vgs ⫺ Vt
an ECL circuit allows it to operate from 2 V. As shown, two
levels of logic, corresponding to signals A and AN, and B, are
possible. The differential signals A and AN swing about 0.5 V
and drive the master side of two separate current mirror cir-
cuits. When A is high, the current through Q5 is on, while
AN, being low, produces almost no current in Q6. The signal
B is applied against a reference voltage that is regulated
against supply voltage changes.
Comparison of BJT with Other Technologies
At the highest speeds, bipolar logic survives the CMOS on-
slaught; it also enjoys the advantage of being differential and
semianalog. The reasons why bipolar technology continues to
be so important will become apparent from the comparison
of the advantages and disadvantages of both BJTs and MOS
devices shown in Table 1.
Bipolar transistors have a tremendous (exponential) gain
and high current drive capability, allowing small devices to
develop large gain and to drive loads of considerable size, by
contrast to MOS. In addition, the small offset voltage of bipo-
lar differential pairs is good for logic at small signal swings.
Fully differential signals can have smaller levels, with the
additional benefit of better common-mode signal and noise re-
jection, resulting in better noise immunity.
Small logic swing (the way to the future for all logic fami-
lies) can naturally take bipolar logic to lower supply voltages
and higher speeds. Speed and power improve with reduced
voltage swing. In addition, the much lower 1/f frequency cor-
ner of BJTs, related to its bulk properties, makes them much
superior in applications where memory effects are detrimen-
tal, as in data transmission and test equipment.
Because bipolar logic is built around a lot of the same ele-
ments used in analog design (BJTs, resistors, diodes, capaci-
tors, and even inductors), it lends itself nicely to mixed signal
design, combining analog and digital on the same circuit. For
example, some of the key bipolar and BICMOS analog func-
tions, such as analog-to-digital converters, digital-to-analog
converters, phase-locked loops, and disk-drive electronics,
contain a mix of logic circuits.
Concerning GaAs metal semiconductor field effect transis-
tors (MESFETs), all of the above comparisons apply, since
their operation is very similar to that of MOS transistors, ex-
cept that the higher mobility (at low electric fields) of GaAs
gives it an advantage. GaAs ICs also are manufactured on a
semiinsulating substrate that gives reduced signal loading
and improved crosstalk. However, competing directly with
GaAs logic, Si–BJT processes are cheaper, more stable (sta-
tistical corners), better at low temperature, lower in noise for
data transmission (dc-coupled), and nontoxic.
New silicon–germanium (SiGe) bipolar technologies are
challenging even the most advanced processes in other mate-
rials, since they achieve very high cutoff frequencies (e.g., 75
GHz) and have other improved transistor parameters. Since
1995, the circuit speed performance of SiGe has not only ex-
ceeded GaAs MESFETs but almost equaled that of other more
exotic technologies such as HEMT (high electron mobility
transistor) and HBT (heterojunction bipolar transistor). Fi-
nally, silicon-on-insulator and higher resistivity substrates
will remove the last obstacle in the competition for the high-
speed and mixed-signal markets, namely, the substrate’s ca-
pacitance, loss, and cross-talk.
CMOS LOGIC CIRCUITS
Although bipolar processes are used for many high-speed de-
signs, CMOS has become the dominant technology for most of
today’s digital ICs. Lower power and higher integration densi-
ties are two reasons for the success of the CMOS process.
Field effect transistors (FETs) were conceived as early as
1925, more than two decades before the invention of the bipo-
lar transistor. However, development of fabrication processes
to support the manufacture of FETs did not occur until the
1960s. The earliest MOS processes were based on single tran-
sistor types. The CMOS fabrication process allows both types
of MOSFETs, p-channel and n-channel, to be fabricated to-
gether. Schematic symbols for an n-channel MOS transistor
and a p-channel MOS (PMOS) transistor are shown in Fig.
11. Circuits consisting of NMOS and PMOS transistors can
be used to perform boolean logic functions.
Classical CMOS Gates
In order to understand how CMOS logic circuits behave, a
model for the operation of an individual FET is needed. The
simplest model of an NMOS transistor is that of a switch that
closes when the logic level on the gate is high, passing the
logical state on the input to the output. With a low on the
gate, the switch modeling the NMOS transistor is open. For
modeling a PMOS transistor, the switch is open when the
gate is driven with a high and closed when the gate is driven
with a low. Boolean logic functions such as nand, nor, and
invert can be easily implemented by networks of PMOS and
NMOS transistors as shown in Fig. 12.
Series connections of transistors perform a logical and op-
eration, whereas parallel connections perform a logical or op-
eration. For the nand gate in Fig. 12, two NMOS transistors
are in series between the output (y) and ground (the source of
a low logic level). When both x1 and x2 are asserted high, the
output is pulled to ground, thus passing a low voltage level to
Gate Gate
Input Output Input Output
NMOS PMOS
Figure 11. MOS transistor schematics. As shown, the input is arbi-
trarily connected to the transistor source, and the output to the drain.
The gate controls the switch action.
 BIPOLAR AND MOS LOGIC CIRCUITS 459

x1 x2 y x1
x2 0 1
x1 x1 x2 0 0 1 0 1 0
0 1 0
y
1 0 0
1 0 0
x2 x1 1 1 0

x y y Figure 13. Nor truth table and Karnaugh map with groupings for
both the PMOS network and the NMOS network.
x1 x2 x2

truth table describing the logical function of a two-input nor

invert 2-input nor 2-input nand gate can be entered into a Karnaugh map and the 1’s and 0’s
can be grouped together as shown in Fig. 13. These groupings
Figure 12. Basic logic gates are constructed by parallel and series
imply that a 1 must be passed to the output under the input
combinations of NMOS and PMOS transistors.
condition x1x2 and that a 0 must be passed to the output when
x1 ⫽ 1 or when x2 ⫽ 1. Using the pass notation introduced,
the output. The two PMOS transistors are connected in paral- y = x1 x2 (1) + x1 (0) + x2 (0) (2)
lel between the high-voltage supply and the output. When ei-
ther x1 is low or x2 is low, a path is closed between the high Equation (2) describes the network of MOS transistors
supply and the output, passing a high voltage level to the needed. The first term is a logical and operation. This implies
output. The Boolean operation of a nand function is thus per- a series path between the output and the high supply, since
formed. both x1 and x2 must be low to pass a 1 to the output. Since p-
To understand why PMOS transistors are used to pass channel transistors pass good 1 levels and the switch model
high levels to the output while NMOS transistors are used to closes when the gate is driven by a low level, a pair of series
pass low levels, the switch model must be modified to take PMOS gates are used. The next two terms imply parallel
account of the threshold voltage. The switch modeling an paths passing 0’s when x1 or x2 is high. Parallel n-channel
NMOS transistor is actually closed only when the difference transistors are therefore used. Figure 12 shows the classical
between the voltage on the gate, Vg, and the voltage on the CMOS nor gate with series PMOS transistors between the
source, Vs, is greater than a threshold voltage, Vt. If an NMOS output and the high supply and parallel NMOS transistors
transistor is used to pass a low level, then Vg is always between the output and the low supply.
greater than Vt and the switch is always closed. If, however, Digital MOS ICs can be designed using exclusively nand,
an NMOS transistor were used to pass a high level, the out- nor, and invert gates; however, the cost of an IC is propor-
put would rise until the voltage was Vt less than the gate tional to the size of the die, and this design methodology
voltage, at which point the switch would open and the output might not result in the most economical solution. Several
would cease to rise. NMOS transistors will pass good 0’s, but logic families have been developed to reduce the number of
degrade the voltage level of a 1. PMOS transistors, by similar transistors required to implement a given Boolean logic ex-
arguments, pass good 1’s, but poor 0’s. pression. As an example, the implementation of the Boolean
The operation of digital CMOS circuits can be described by function described by the truth table in Fig. 14 will be de-
Boolean algebra. The normal boolean expression describing scribed for several static logic families. Using basic logic
the nand function is given by y ⫽ x1x2, which conveys that gates, two two-input nand gates and one three-input nand
both x1 and x2 must be high before y ⫽ 0. An alternative Bool- gate would be needed to implement the design example, re-
ean expression for the nand function is y ⫽ x1 ⫹ x2, which quiring a total of 14 transistors.
implies that if either x1 or x2 is low, then y ⫽ 1. Both concepts
are needed to describe the CMOS nand gate fully.
Let y ⫽ x(0) be read as ‘‘y is equal to x passing a 0,’’ mean-
ing that when x ⫽ 1, a 0 is passed to the output. Also, let x1 x2 x3 x4 y
y ⫽ x(1) be ‘‘y is equal to x passing a 1,’’ meaning that when 0 0 0 0 0
x ⫽ 1, a 1 is passed to the output. The CMOS nand function 0 0 0 1 1
0 0 1 0 0
can then be fully described by the following expression:
0 0 1 1 1
0 1 0 0 0
y = x1 x2 (0) + x1 (1) + x2 (1) (1) 0 1 0 1 0
0 1 1 0 1
This can be read as ‘‘y is equal to x1x2 passing a 0 or x1 passing 0 1 1 1 1 x 1x 2
1 0 0 0 1 x 3x 4 00 01 11 10
a 1 or x2 passing a 1.’’ This notation conveys the meaning that
1 0 0 1 1
when x1 is high and x2 is high, the output is low, and if either 1 0 1 0 1
00 0 0 1 1
x1 or x2 is low, the output is high. The first term of Eq. (1) 1 0 1 1 1 01 1 0 1 1
implies the series connection to ground of two NMOS transis- 1 1 0 0 1
tors. The second and third terms imply a parallel connection 1 1 0 1 1 11 1 1 1 1
of PMOS transistors. 1 1 1 0 1
10 0 1 1 1
1 1 1 1 1
The concept of passing 1’s and 0’s can be used to derive
other classical CMOS gates. The derivation of the two-input Figure 14. Design example used for comparison of several CMOS
nor gate will be used as an example. The information in a logic families.
460 BIPOLAR AND MOS LOGIC CIRCUITS

resistor representing the enhancement NMOS transistors in

x1 x3 x4
the pulldown path. The value of the resistance of a FET is
inversely proportional to the width of the transistor. The volt-
age value representing a low logic level could be controlled by
x2 x2 the ratio of the widths of the depletion and enhancement
NMOS transistors. The enhancement NMOS transistors were
y y
sized to be of much smaller resistance than the depletion
x1 x1 transistor setting a low voltage for the low logic level.
This NMOS structure can be imitated in today’s CMOS
process, by replacing the depletion pullup transistor with ei-
x2 x2 x2 x2 ther a PMOS transistor whose gate is tied to a logic low
(pseudo-NMOS), or an NMOS transistor whose gate is driven
with a bias voltage that is greater than the supply voltage
x3 x4 x3 x4 plus Vt (modified pseudo-NMOS). The pseudo-NMOS struc-
ture is shown in the right half of Fig. 15 and requires just six
transistors. A modified pseudo-NMOS structure would also
Complex gate pseudo-NMOS gate require only six transistors.
There is a cost associated with the pseudo-NMOS ap-
Figure 15. Complex gate implementation using fully complementary proaches. When y ⫽ 0, a current flows between the supply
networks and a pseudo-NMOS approach. voltage and ground. This current flow is minimized by mak-
ing the pullup resistance just low enough to maintain the de-
sired speed of operation for the circuit, but still represents
A complex gate with just one node can perform the same enough current to be the reason that CMOS processes re-
function. Using a Karnaugh map, the required PMOS and placed the NMOS and PMOS processes of the 1970s. Al-
NMOS networks to implement a complex CMOS gate can be though entire chip designs have been based on this logic style,
derived in the same manner that the nor gate was derived. it is normally used in conjunction with dynamic techniques,
For the Karnaugh map groupings shown in Figure 14, which will be discussed in a following section.
y = x1 [x2 x3 (0) + x2 x4 (0)] + x1 (1) + x2 x3 (1) + x2 x4 (1) (3)
Pass Gates
Using NMOS transistors to pass 0’s and PMOS transistors to The concept of passing 1’s and 0’s helps to understand the
pass 1’s, and remembering that a PMOS switch is closed operation of static CMOS gates. The limitation of passing only
when driven with a low logic level, we obtain the 10-transis- 0’s and 1’s requires the use of more transistors than necessary
tor solution shown on the left in Fig. 15. This reduction in for many Boolean functions. This constraint is lifted for pass
transistor count motivates cost-conscious circuit designers to transistor gates. The first grouping, in the Karnaugh map of
find alternative implementations, especially for logic blocks Fig. 16, is x1x2, passing the variable x4. The second is x1x2,
that will be placed many times on a digital IC. passing x3. The resulting equation is

Pseudo-NMOS Gates y = x1 [ x2 (x4 ) + x2 (x3 )] + x1 (1) (4)

Another alternative approach reaches back into history to re- The four-transistor circuit shown on the right side of Fig. 16
duce the transistor count even further. In the 1970s, MOS implements the desired function. Since the variables x3 and
processes were dominantly single-transistor processes. An x4 can be either 1’s or 0’s, the voltage level of 1’s will be de-
NMOS processes had typically two types of n-channel FETs: graded at y and must therefore be restored. One approach for
an enhancement transistor similar to the NMOS transistor passing good levels would be to use an NMOS and a PMOS
available in today’s CMOS process, and a depletion transistor. transistor in parallel (a transmission gate) whenever a vari-
If the gate and source of the depletion device were tied to- able is passed. The NMOS device would pass a good 0, while
gether (self-sourced), the transistor could be modeled as a re- the PMOS transistor would pass a good 1. If transmission
sistor. The model for the NMOS enhancement transistor also gates were used, seven transistors would be required. The
need to be expanded to include the concept of resistance. second approach would be to actively restore the output level
When Vg ⫺ Vs ⬎ Vt and the drain voltage Vd is such that at the output of the pass network.
Vd ⫺ Vs ⬍ Vg ⫺ Vs ⫺ Vt, then the closed switch modeling the
NMOS transistor has the property of resistance.
x 1x 2
In the NMOS process, Boolean logic was implemented with x2 x2
x 3x 4 00 01 11 10 x1
an NMOS network identical to the one shown in Fig. 15,
while the PMOS network was replaced by a single, self- 00 0 0 1 1
sourced depletion transistor connected to the high supply. 01 1 0 1 1 x3 y
When the input state was such that y ⫽ 1, the NMOS net-
11 1 1 1 1
work’s path to ground would be broken and the output would
charge to the high supply through the resistance of the deple- 10 0 1 1 1
x4
tion NMOS transistor. When the inputs were such that y ⫽
0, then the output would be a voltage division between the Figure 16. Pass transistor design eliminates the constraint of pass-
resistor representing the depletion transistor pullup and the ing only 1’s and 0’s.

CK CK
y
x1
x2 x2 x2
x3 x4 x1 x3
CK CK
Dynamic logic gate Domino logic gate
The logic of this design example is to perform the function
of a synchronous set and load/hold when used to drive the d
input of a master–slave flip-flop. Since an array of 100 of
these circuits was needed on an actual design and since active
level restoration of the 1 level was inherent in the master
section of the flip-flop, the pass transistor design shown in
Fig. 16 was used, saving 1000 transistors in comparison with
the nand-gate approach.
Dynamic Gates
Unlike static logic, in which there is a path between the out-
put and either the high supply or ground for every input
state, dynamic logic relies on storage of charge on the capaci-
tive load seen at the output to maintain the logic level for
periods of time. The time base for storage is normally estab-
lished by a clock. The output of dynamic logic is also valid
only during a portion of the charge storage time. A dynamic
logic gate that implements the design example of Fig. 14 is
shown on the left side of Fig. 17. When the clock CK is low, y
is precharged to a 1 level. When the clock transitions high,
the NMOS transistor at the bottom of the NMOS network
evaluates the state of the inputs and conditionally discharges
the output to ground. If there is no path to ground through
the NMOS array, the output remains high. This high voltage
level is stored on the capacitance seen at the output node.
Over time this level will degrade due to parasitic leakage
paths. This leakage establishes a lower limit on the rate of
the clock signal. This limit could be eliminated by adding a
PMOS transistor, like the pseudo-NMOS pullup device of Fig.
15, with a resistance just low enough to overcome the effects
of leakage. A total of seven transistors are required to imple-
ment the design example.
There are two design considerations for dynamic logic
gates. The output of the dynamic gate of Fig. 17 is floating or
at a high impedance when storing a high level. The logic level
is stored in the form of charge on the capacitance of the node.
This floating node is susceptible to charge sharing introduced
by crosstalk from adjacent lines. Charge sharing occurs be-
tween two physically adjacent conductors due to the parasitic
capacitance formed by the node metals separated by an the
insulating layer. When an adjacent node voltage changes,
charge is coupled through this parasitice capacitance to the
otherwise unrelated node. Charge can be moved off of the
BIPOLAR AND MOS LOGIC CIRCUITS 461
y
x3
x4
Figure 17. Dynamic logic structures. A
basic precharge evaluate structure (left) is
compared with a domino logic structure.
node by charge sharing, reducing the voltage level of the
stored logic 1. Charge sharing across the gate capacitance of
transistors within the NMOS pulldown structure also can de-
grade the output 1 level if the inputs transition while clock is
high. The second consideration occurs when one dynamic gate
drives the input of a second dynamic gate. A race exists be-
tween when the clock transitions high and the first dynamic
gate evaluates low. This race occurs because both outputs are
precharged high when the clock is low and evaluate when the
clock is high. With the inputs to the NMOS transistors of the
second stage high due to the precharge of the first stage,
the second node begins to fall even though the first stage might
transition low, requiring the second stage to remain high.
Due to the charge sharing and inherent race condition of
dynamic gates, they are not generally used for random logic.
When the NMOS and PMOS arrays for implementing a de-
sired function are large, the effort required to ensure proper
operation is worthwhile. Dynamic logic is often used, for ex-
ample, to implement the address decode logic of a memory
circuit.
In order to overcome the race condition and external cross-
talk susceptability of dynamic logic, the domino logic configu-
ration shown on the right side of Fig. 17 can be used. The
inverter on the output node isolates the high-impedance node
from charge-sharing effects external to the node. Also, since
precharging the internal node to a 1 sets the output to a 0,
no race exists between cascaded stages. The first state evalu-
ates, and if the input transitions, it may cause the second to
transition, and so on in a domino effect. The NMOS network
is simply designed to produce the inverse of the function de-
sired at the output of the inverter.
Future Challenges for CMOS
The new set of constraints presented by today’s submicro-
meter CMOS processes are opening for debate again design
questions long thought answered. MOS processing technolo-
gies underwent a evaluation in the past. NMOS, with inher-
ent speed advantages, replaced PMOS as the dominant MOS
technology in the early to mid 1970s. CMOS, with inherent
power advantages, replaced NMOS processes in the late
1970s and early 1980s. The speed and density of the circuits
being designed at that time had risen to the point where
packaging technology could no longer deal with the power lev-
462 BIPOLAR MEMORY CIRCUITS

els generated by NMOS designs. Today we are faced once BIPOLAR LOGIC CIRCUITS. See BICMOS LOGIC CIR-
again with the same power dilemma. Architecture, logic, cir- CUITS.
cuit, and fabrication techniques are evolving to reduce power
while maintaining or increasing performance. As the submi-
crometer geometries continue to shrink, previous assump-
tions about the choice of design methodologies and families
are no longer valid. For instance, the area of a circuit is now
a much stronger function of interconnect than transistor
count. Off-state leakage is no longer negligible and can in the
case of large memory cores actually dominate as the main
component of static power. Switching power, the power asso-
ciated with charging and discharging capacitive loads, in-
creases with capacitance. This is allowing the design tradeoff
between capacitance and static power to be reevaluated. As
with most engineering disciplines, VLSI logic design will con-
tinue to evolve.

BIBLIOGRAPHY

A. R. Alvarez, BICMOS Technology and Applications, Norwell, MA:

Kluwer Academic, 1989.
A. Barna, VHSIC: Technologies and Tradeoffs, New York: Wiley-Inter-
science, 1981.
M. I. Elmasry, Digital Bipolar Integrated Circuits, New York: Wiley-
Interscience, 1983.
S. H. K. Embabi, A. Bellaouar, and M. I. Elmasry, Digital BICMOS
Integrated Circuit Design, Norwell, MA: Kluwer Academic, 1993.
E. D. Fabricius, Introduction to VLSI Design, New York: McGraw-
Hill, 1990.
L. A. Glasser and D. W. Dobberpuhl, The Design and Analysis of VLSI
Circuits, Reading, MA: Addison-Wesley, 1985.
L. J. Herbst, Monolithic Integrated Circuits, Oxford: Clarendon
Press, 1985.
Integrated Circuit Engineering Corporation, STATUS 1997, Scotts-
dale, AZ: ICE, 1997.
K. Kishine, Y. Kobayashi, and H. Ichino, A high-speed, low-power
bipolar digital circuit for Gb/s LSI’s: Current mirror control logic,
IEEE J. Solid-State Circuits 32:, 215–221, 1997.
P. L. Mathews, Choosing and Using ECL, London: Granada Publish-
ing, 1983.
R. Meyer, Advanced Integrated Circuits for Communications, Course
ECE242 Notes, Berkeley: Univ. of California 1994.
J. M. Rabaey, Digital Integrated Circuits: A Design Perspective, Upper
Saddle River, NJ: Prentice-Hall, 1996.
H. Rein and M. Moller, Design considerations for very-high-speed Si-
bipolar IC’s operating up to 50 Gb/s, IEEE J. Solid-State Circuits,
31: 1076–1090, 1996.
M. I. Rocchi (ed.), High Speed Digital IC Technologies, Norwood, MA:
Artech House, 1990.
M. Shoji, CMOS Digital Circuit Technology, Englewood Cliffs, NJ:
Prentice-Hall, 1988.
N. H. E. Weste and K. Eshraghian, Principles of CMOS VLSI Design:
A Systems Perspective, 2nd ed. Reading, MA: Addision-Wesley,
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CA: Lattice Press, 1990.

GERMAN GUTIERREZ
Silicon Wave, Inc.
STERLING WHITAKER
NASA Institute for Advanced
Microelectronics
 BOOTSTRAP CIRCUITS 531

BOOTSTRAP CIRCUITS Vdd

The word bootstrapping is defined in Webster’s New World Col- M1

lege Dictionary (1) as ‘‘to lift (or raise) oneself by the (or one’s
(Va) a
own) bootstraps to achieve success by one’s own unaided ef- Cpar M2
forts.’’ A similar phenomenon may occur in some electrical (Vo)
and electronic circuits. A circuit can sense a voltage change Cboot
at one terminal of a two-terminal element and cause an equal
change in the voltage of the other terminal (2). Thus the volt- Input M3 Cout
age drop across that element remains almost unchanged. For (Vin)
example, while terminal a of the device shown in Fig. 1 may
have higher potential than terminal b (by V volts), if the volt-
age or potential at b is somehow raised, a potential change at Figure 2. Bootstrapped NMOS inverter (4). The bootstrapping is
achieved by Cboot.
a follows that at node b. This is referred to as bootstrapping
since it is similar to a person trying to lift himself or herself
off the ground by pulling his or her bootstraps. In actual cir-
cuits where bootstrapping is used, the voltage across the ele-
ment may change.
The bootstrapping technique has been used for both digital
and analog circuits. Some examples of each are presented
next.

Vdd
BOOTSTRAPPING IN DIGITAL CIRCUITS

Bootstrapping has been used in digital circuits (CMOS and Mf1

BiCMOS) mainly to increase the voltage swing of the logic
gates. In such circuits, bootstrapping is achieved by using ca-
Vin Mp1 Cboot
Q1
pacitive coupling (3), as in the NMOS bootstrapped inverter
shown in Fig. 2 (4). Mb1 I2
In Fig. 2, M1 maintains the voltage of node a at Vdd ⫺ VT
(where VT is the threshold voltage of the NMOS transistor). V0 Vo
If the input is grounded, M3 is turned off, whereas M2 is I3
turned on and thus provides current to charge Cout. This VDD
CL
causes the output voltage Vo to rise toward Vdd. If Cboot is ig- Mf2
nored temporarily, M2 should turn off as soon as Vo ⫽ Vdd ⫺
2VT. However, due to the capacitor coupling provided by Cboot, Mp2
the voltage of the gate of M2 will follow the rising output. In I1 Q2
other words, node a is bootstrapped. Notice that M1 cuts off Mb2
once Va exceeds Vdd ⫺ VT; thus node a can be assumed floating
(isolated from Vdd). This allows the voltage Va to rise above
Vdd until it reaches Vdd ⫹ VT, and as a result Vo can be pulled
up to Vdd. This is the main advantage of using bootstrapping
Figure 3. A bootstrapped BiCOMOS inverter (5).
in the case of the NMOS inverter. To achieve proper boot-
strapping, Cboot must satisfy the following condition (4):

2VT
Cboot ≥ Cpar
Vdd − 2VT − VOL

a a I
Voltage α +
Boot Va V
+
strapping V + –
V
circuit Vb VB Io Ro
– V –

b b
Time
Current source/sink
Figure 1. Bootstrapping in electronic circuits: The bootstrapping cir-
cuit forces the voltage at node a to track any voltage changes oc- Figure 4. Bootstrapping to increase the output resistance of a cur-
curring at node b. rent source.

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.
532 BOUNDARY-SCAN TESTING

3. R. E. Joynsan et al., Eliminating threshold losses in MOS circuits

I2 by bootstrapping using varacter coupling, IEEE J. Solid-State
a (va) I
Q2 Circuits, SC-7: 217–224, 1972.
+ 4. L. A. Glasser and D. W. Dobberpuhl, The Design and Analysis of
Q1 VLSI Circuits, Reading, MA: Addison-Wesley, 1985.
+ +
VEE2 VBB1 5. S. H. K. Embabi, A. Bellaoucer, and K. I. Islam, A bootstrapped
I1
– – bipolar CMOS (B2CMOS) logic gate for low voltage applications,
V IEEE J. Solid-State Circuits, 30: 47–53, 1995.
b (vb) 6. R. L. Gerzer, P. E. Allen, and N. R. Strader, VLSI Design Tech-
R niques for Analog and Digital Circuits, New York: McGraw-Hill,
– 1990.

SHERIF H. K. EMBABI
Figure 5. A bipolar bootstrapped current source. Any change in va Texas A&M University
will cause a similar change in vb, such that the voltage across Q1
remains constant.

BOUNDARIES, SEMICONDUCTOR-INSULATOR.
See SEMICONDUCTOR-INSULATOR BOUNDARIES.
where Cpar is the parasitic capacitor at node a and VOL is the
low logical level of the NMOS inverter. It is important to no-
tice that the bootstrapping due to capacative coupling is valid
for a finite period of time. The charge stored on the boot node
(node a) will leak off as time passes, and the voltage at node
a will drift back to its nominal value Vdd ⫺ VT; Vo will conse-
quently drift to Vdd ⫺ 2VT.
Bootstrapping has also been used for BiCMOS digital in-
verters to force the output logic high levels to approach Vdd
(similar to NMOS). One example of such circuits is shown in
Fig. 3 (5).

BOOTSTRAPPING FOR ANALOG CIRCUITS

Bootstrapping techniques can be effective in analog circuits,

for instance, to increase the output resistance of a current
source (2,6). This can be explained conceptually using Fig. 4.
The bootstrapping circuit senses any change in V (the voltage
of node a) and generates an equal change at node b so that
the voltage across the current source is almost constant. This
implies that the output resistance of the current source re-
mains high. It can be shown that output resistance R0 in-
creases by a factor 1/1 ⫺ 움, where 움 is the small signal volt-
age gain (2) where va is the small signal voltage at node a
and Vb is the small signal voltage at node b. The gain 움 should
ideally be unity so that the output resistance of the current
source is infinite. But in practice it will have a finite value (움
⬍ 1).
Figure 5 shows how the current source, consisting of Q1
and VBB1, is bootstrapped using Q2, VEE2, and R. The voltage
gain from the base of Q2 (node a) to the emitter of Q1 (node b)
is less than but very close to unity. Therefore, node b tracks
node a. Thus the collector–emitter voltage and the collector
current of Q1 remains almost unchanged even though the
voltage at node a may vary. This implies that the output re-
sistance is increased.

BIBLIOGRAPHY

1. Webster’s New World College Dictionary, 3rd ed., 1997.

2. A. S. Sedra and K. C. Smith, Microelectronics Circuits, Philadel-
phia: Saunders College Publishing, 1991.
558 BRIDGE CIRCUITS

BRIDGE CIRCUITS
Bridges are the most commonly used circuits in measurement
techniques. They enable accurate static measurements of re-
sistance, capacitance, or inductance. Measurement accuracy
is provided by the null-balance method of output indication,
and by the fact that the bridge circuit configuration allows
comparison of unknown components with precise standard
units. This resulted in development of bridge instruments as
complete units of laboratory equipment. The balance in
bridges is highly sensitive with respect to variations of the
bridge components, and this brought about the widespread
use of bridge configurations in transducer and sensor applica-
tions. In addition, the bridge circuits may be found as ‘‘work-
ing’’ circuitry in electric filters where they provide the flexi-
bility inachievable for other filter configurations, in radio
receivers and transmitters where the bridge approach is used
to design stable sinusoidal oscillators, and elsewhere in elec-
tronic hardware, where they are met in a wide variety of cir-
cuits used for determination of impedance, reactance, fre-
quency, and oscillation period. The number of circuits based
on the bridge configuration is increasing, and this article de-
scribes the elements of the general theory of bridge circuits,
and outlines some of their above-mentioned basic applications
with more stress on measurement and transducer ones.
The circuit [Fig. 1(a)] including four arms with imped-
ances, Z1, Z2, Z3, Z4, an element (in applications called ‘‘bal-
ance detector’’ or ‘‘balance indicator’’) with impedance Zo, and
a voltage source of value Eg and output impedance Zg is an
example of the so-called bridge circuit. Figure 1(b) shows the
equivalent ‘‘lattice’’ form of this circuit. This is the simplest
circuit, for which the currents in the impedances cannot be
found using the circuit reduction based on parallel or series
connection of two or more impedances. To find these currents,
one has to write, for example, a system of three loop equa-
tions. As a result, this circuit, which is not very complicated,
is frequently used for demonstration of general (1) (mesh,
loop, and nodal analysis) and special methods (2) (wye-delta
transformation) of circuit analysis. The calculation of the cur-
rent Io in the impedance Zo is a favorite example for demon-
stration of Thévenin and Norton theorems (1,3).
Most technical applications of this bridge circuit are based
on a simple relationship that exists among the circuit arm

Z1

Z1 Z2 Z2
Zg Zo
Zg Io Zo
Z4
Eg Io
Eg
Z4 Z3 Z3

(a) (b)

Figure 1. (a) Bridge circuit and (b) its lattice form.

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.
 BRIDGE CIRCUITS 559

Ig Io
Zg

(1) (a) (2) (2) (b) (1)

Eg Vg Vo Zo Eg
(3) Io (3)

Zin Zout
(a) (c)

(1) (2)
(a)
(3) Io

Eg
(1) (2)
(b)
(3) Figure 2. (a) Bridge circuit as a transmission
system; (b) two-ports with crossed input or output
wires; (c) two subcircuits in a bridge: (d) their par-
(b) (d) allel-series connection is clearly seen.

impedances so that the current (or voltage) of the detector The terms a11, a12, a21, and a22, (called ‘‘chain parameters’’) are
impedance has a zero value. One can easily see that in the the terms of a-parameter matrix. Equations (2) show that the
circuits of Fig. 1 the condition Io ⫽ 0 (or the ‘‘balance’’ condi- two-port does not transmit voltages and currents from left to
tion) is achieved when right if one of the following conditions is satisfied:

Z1 Z3 = Z2 Z4 (1) a11 = ∞ a12 = ∞ a21 = ∞ a22 = ∞ (3)

In measurements, this relationship allows one to calculate

The investigation of the terms g-, y-, z-, and h-matrices (4)
one of the impedances if three others are known. In transduc-
allows one to formulate other specific relationships pertaining
ers, it is used in inverse sense—that is, if Io ⬆ 0 then Eq. (1)
to the balanced bridge circuits. In these circuits, correspond-
is violated as well. The deflection 웃Io of the current Io from
ingly, the parameters of other two-port matrices have the val-
zero (the value and sign) is used to evaluate the deviation of
ues
Z1, Z2, Z3, Z4 or their combinations from their nominal values
satisfying Eq. (1). If these impedances are dependent on some
g21 = 0 y21 = 0 z21 = 0 h21 = 0 (4)
physical variables (which are called measurands), then 웃Io
provides information on these physical variables.
The simplicity of Eq. (1) and its independence of Zo and Zg From the other side, the bridge is a reciprocal circuit, and if
(which in many applications are not well specified) make the Eq. (2) is satisfied then the conditions
bridge measurements of physical variables reliable and sensi-
tive. This feature brought about the widespread use of bridge g12 = 0 y12 = 0 h12 = 0 z12 = 0 (5)
circuits in instrumentation and, recently, in microsensors.
By analogy, all circuits (of usually simple configurations) are also, correspondingly, satisfied, and the circuit will not
where a certain relationship between the elements results in transmit voltages and currents as well from right to left.
a zero current in a given element, or zero voltage between a In addition, for reciprocal circuits the following relation-
given pair of nodes, are called bridge circuits here. ship exists among the chain parameters:

|a| = a11 a22 − a12 a21 = 1 (6)

BRIDGE CIRCUIT BALANCE CONDITIONS

Let us consider the bridge circuit as a passive two-port con- Now let one consider the input and output impedances
nected between the impedances Zo and Zg [Fig. 2(a)] and as-
sume the balance conditions. Investigation of the systems of a11 Z0 + a12 a22 Zg + a12
Zin = Zout = (7)
parameters applied for two-port description (4) allows one to a21 Z0 + a22 a21 Zg + a11
formulate some specific relationships pertaining to bridge cir-
cuits. One easily finds that if Eqs. (6) is valid and one of the condi-
The four terminal quantities for this two-port are related tions of Eq. (3) is satisfied, these impedances are given by one
by the equations of the following expressions:
Vg = a11V0 − a12 I0 a11 a12 a22 a12
(2) Zin = Zin = Zout = Zout = (8)
Ig = a21V0 − a22 I0 a21 a22 a21 a11
560 BRIDGE CIRCUITS

Hence, the condition of balance indeed is independent of Zo port matrix terms. If the initial two-port is described by a z,
and Zg (they are ‘‘not seen’’ from the input and output termi- y, h, or g matrix, then only the diagonal terms of these matri-
nals) if the two-port is a linear one. ces should change their sign.
The set of conditions of Eqs. (3) and (4) can be used, to some Many bridge circuits can be represented as a connection of
extent, for synthesis of bridge circuits (5). A bridge circuit can two two-ports shown in Fig. 2(c), where the bridge output
frequently be represented as a regular connection (4) of k two- branch is a wire carrying the current Io. This connection can
ports. Then the conditions of Eqs. (3) and (4) are modified into be redrawn as shown in Fig. 2(d). Then the condition of bal-
ance (Io ⫽ 0) for this circuit can be written as g21 (a)
⫽ g(b)
21 or as

i=k 
i=k
1 (a)
a11 ⫽ a(b) .
(i) 11
g21 = 0 or =0 (9) The following three bridges serve as examples. The circuit
i=1
a(k)
i=1 11
of the twin-T bridge [Fig. 3(a)] is a parallel connection of two
T circuits. The parameter y21 (i)
(i ⫽ 1, 2) for each of these cir-
for parallel-series connection of these two-ports. They are
cuits can be easily calculated, and their sum y(1) 21 ⫹ y21 , in ac-
(2)
modified into
cordance with Eq. (10) gives the balance condition

i=k 
i=k
1 Z1 Z3 Z Z
(i)
y21 =0 or (k)
=0 (10) Z1 + Z3 + + Z4 + Z6 + 4 6 = 0 (13)
i=1
a
i=1 12 Z2 Z5

for parallel connection of two-ports. Then they will give The ordinary bridge can be represented as a series-parallel
connection of two simple two-ports [Fig. 3(b)]. Calculating the

i=k 
i=k
1
(i)
a22 (i ⫽ 1, 2) parameters and using Eq. (11), one obtains
(i)
z21 = 0 or (k)
=0 (11)
i=1
a
i=1 21 Z1 Z4
= (14)
Z1 + Z2 Z4 + Z3
for series connection of two-ports. Finally, the conditions of
Eqs. (3) and (4) will be modified into from which Eq. (1) follows immediately.
The double bridge [Fig. 3(c)] is easily recognized as the con-

i=k 
i=k
1 nection of two two-ports shown in Fig. 2(c). Equating the pa-
(i)
h21 =0 or =0 (12) rameters a(1) (2)
a (k) 11 (left part) and a11 (right part), one can find the
i=1 i=1 22
balance condition
for series-parallel connection of two-ports. Z6 (Z5 + Z7 ) + (Z1 + Z4 )(Z5 + Z6 + Z7 ) Z + Z3
= 2 (15)
Some bridge circuits include a two-port with input or out- Z6 Z7 + Z4 (Z5 + Z6 + Z7 ) Z3
put crossed wires [Fig. 2(b)]. Such a two-port is described by
an a matrix with terms that are negatives of the initial two- for this bridge.

Z1 Z3 Z2

Z2
Z1

Z4 Z6 Vo Z3
Vo

Z5 Z4

(a) (b)

Z1 Z2
Z5

Z6
Io

Z7
Z4 Z3
Figure 3. Examples of bridge circuits: (a) twin-T
bridge; (b) simple bridge redrawn as a series-parallel
connection of two two-ports; (c) double bridge. (c)
 BRIDGE CIRCUITS 561

I10 δ Z
Z1 + δ Z Z1 I10 Z1 + δ Z + –
+
Z2 Z2 Z2

Zg Zo Zg Zg Zo
Z4 Z4 Z4
Eg Eg Eg
Z3 Z3 Z3

(a) (b) (c)

e1 e2 e2
+ – Z1 + δ Z – + Z1 – +
+ + +
Z2 Z2

Zg Zo Zo
Figure 4. Calculation of sensitivity in a
Z4 Z4 simple bridge circuit: (a) initial circuit; (b)
Eg circuit in balance; (c) introduction of com-
Z3 Z3
pensating source: (d) extraction of exter-
nal sources in autonomous two-port; (e)
(d ) (e) circuit for calculation of current variation.

SENSITIVITY can find that

An important parameter of the bridge circuit is sensitivity. It
is usually calculated for the balanced bridge condition. One
defines the sensitivity of the bridge output (or balanced) cur-
rent as
dI0 δI
Si = ≈ 0
dZk δZk
where the derivative is determined at the point Io ⫽ 0, and
the sensitivity of the bridge balanced voltage as
dV0 δV0
Sv = ≈ (17)
dZk δZk
with the derivative determined at Vo ⫽ 0. Here Zk is the ele-
ment of the bridge circuit that varies (it is frequently called a
‘‘tuning element’’). The right sides of Eqs. (16) and (17) show
that variations are used for practical calculations of the sensi-
tivities. In addition, 웃Vo ⫽ Zo웃io so that
Sv = Z0 Si
and calculation of only one sensitivity suffices.
The calculation of sensitivity requires a sequence of steps
that can be demonstrated (Fig. 4) using the bridge of Fig. 1(b).
Assume that it is required to find the sensitivity
dI0
Si =
dZ1
of this bridge with respect to variation of the element Z1 [Fig.
4(a)]. First, let us calculate the current I10 through this ele-
ment in the condition of balance, when Io ⫽ 0. In this calcula-
tion the element Zo can be disconnected [Fig. 4(b)] and one
Eg Z2
I10 = (20)
Zg (Z1 + Z2 ) + Z1 (Z2 + Z3 )
Let the element Z1 vary, and let its variation be 웃Z (Fig. 4c).
In accordance with the compensation theorem (2,5), the cur-
rent 웃Io occurring in the element Zo can be calculated if one
(16) introduces in the branch with Z1 ⫹ 웃Z a compensating voltage
source I10웃Z, as shown in Fig. 4(c), and consider a circuit (Fig.
4c) that is an active autonomous two-port (5) connected be-
tween the impedances Zg and Zo. Then, this active autono-
mous two-port can be represented by a passive two-port (of
the same structure, in this case) and two equivalent sources,
which appear at the two-port terminals. This step is simply a
generalization of the Thévenin-Norton theorem for two-ports.
If, for example, one decides to use e1 and e2 connected in series
with the two-port terminals [Fig. 4(d)], one can find that
I10 Z3 δZ
e2 ≈ (21)
Z2 + Z3
(in this calculation it is assumed Z1 ⫹ 웃Z 앒 Z1, and Z1Z3 ⫽
Z2Z4). As for e1, there is no need of calculating it, because the
bridge two-port in the circuit of Fig. 4(d) is nearly at the bal-
(18)
ance condition, and the contribution of e1 to the current in Zo
can be neglected. Simultaneously, for the same reason, the
source e2 does not produce any current in the impedance Zg.
Hence, one can calculate the current in Zo using the ‘‘approxi-
mate’’ circuit of Fig. 4(e). One obtains
Eg Z2 Z3 δZ
δI0 ≈
[Zg (Z1 + Z2 ) + Z1 (Z2 + Z3 )][Z0 (Z2 + Z3 ) + Z2 (Z3 + Z4 )]
(19) (22)
From Eq. (22) it immediately follows that
Eg Z2 Z3
Si ≈
[Zg (Z1 + Z2 ) + Z1 (Z2 + Z3 )][Z0 (Z2 + Z3 ) + Z2 (Z3 + Z4 )]
(23)
562 BRIDGE CIRCUITS

(1)
I 10
(1)
I 10
(1) (1) (1)
Zg Zg
IT0 ZT
Zo

Eg (2) Eg (2)

(a) (b) (c)

– +
(1) +
ZT (1)
e2
IT0 ZT + δ Z
δ Io Zo
+
(2)
I10 δ Z +
–

(d) (e)

Figure 5. Calculation of sensitivity in series connection of two two-ports: (a) initial circuit; (b)
circuit in balance; (c) current in tuning element; (d) introduction of compensating source; (e)
extraction of external sources in autonomous two-port and the circuit for calculation of current
variation.

This calculation of sensitivity may be formalized if the with corresponding inputs. The source e2 can be found as
bridge circuit represents a regular connection of two two-ports
(bridge circuits with more than two subcircuits are very rare). e2 = K2 ec (27)
We assume that the tuning branch is located in the first
two-port. where K2 is another transfer coefficient. Consider that the
Let us consider as an example the series connection of two bridge circuit is nearly balanced, the current 웃I of the detector
two-ports [Fig. 5(a)]. As a first step we assume the condition may be found from the ‘‘approximate’’ circuit shown in Fig.
of balance and then disconnect the indicator branch [Fig. 5(b)] 5(e). The result will be
and calculate the input current I(1)
10 . One can see that this cur-
rent is equal to e2
δI0 ≈ (1) (2)
(28)
Z0 + z22 + z22
(1) Eg
I10 = (1) + z (2)
(24)
Zg + Z11 11
Finally, one can find that
The current IT0 in the tuning branch, ZT, may be determined
K1 K2 Eg
by considering the first two-port only [Fig. 5(c)] with the out- Si ≈ (1) + z (2) )(Z + z (1) + z (2) )
(29)
put open and the current I(1) (Zg + z11
10 applied to its input. For a linear 11 0 22 22
two-port one can write that
The extension of this approach for other regular connections
(1)
IT0 = K1 I10 (25) of two two-ports does not present any difficulty (5).

where K1 is a transfer coefficient. Using the compensation

theorem, one introduces in the tuning branch the compensat- APPLICATION OF BRIDGE CIRCUITS FOR
ing voltage MEASUREMENT OF COMPONENT PARAMETERS

ec = IT0 δZ (26) Bridges are commonly used circuits in measurements. They

(other forms of the compensation theorem may also be used).
For exact calculation of 웃Io one has to preserve the variation
웃Z of the tuning impedance, as is shown in Fig. 5(d). Yet, to
simplify the results (and assuming that 웃Z is small), this vari-
ation is usually omitted. The first two-port now becomes an
autonomous active two-port. It may be represented as a pas-
sive two-port having the sources e1 and e2 connected in series
have high sensitivity and allow accurate measurements of re-
sistance, capacitance, and inductance. Measurement accuracy
is due to the null-balance method of output indication and to
the fact that the bridge circuit configuration conveniently
allows direct comparison of unknown components with pre-
cise standard units. Here we outline the basic ideas of such
measurements. They are useful in laboratory environments
and form the basis of commercial equipment designs (6).

Dc Bridges
The dc bridges are used for precise measurements of dc resis-
tance. The conventional Wheatstone bridge is shown in Fig.
6(a). It consists of four arms R1 to R4, a zero-center galvanom-
eter G, which serves as a balance detector, a protection shunt
Rp, a battery VB (1.5 to 9 V), and a set of switches S1 to S3.
We assume that the resistor R1 is a resistor whose value is
unknown, the resistor R4 is a standard resistor (usually a
variable decade box providing, for example, 1 ⍀ steps from 1
to 11,100 ⍀), and the resistors R2 and R3 are ratio-arm resis-
tors that serve to provide multiplication of the standard resis-
tance by convenient values, such as 100, 10, 1, 1/10, and
1/100.
The goal of the operating procedures is to achieve balance,
which is indicated by a zero reading of the galvanometer with
the switches S1 and S2 closed and the switch S3 open. In the
beginning of the procedure, S3 is closed and S1 and S2 are
open. To avoid transient galvanometer overloading, S1 is
closed first. Then S2 is closed, and an approximate balance is
achieved. Only then is switch S3 opened, and the final balance
is achieved. When balanced, the condition R1R3 ⫽ R2R4 is sat-
isfied, and the unknown resistor value can be found as
R2
R1 = R (30)
R3 4
When the measurement procedure is finished the switches
are returned to their initial state in reverse order (i.e., S3 is
closed first, then S2 is opened, and, finally, S1 is opened).
The main sources of measurement errors are the variance
of ratio-arm resistors (the design characteristic), additional
resistance introduced by poor contacts, resistance in the re-
mote wiring of the unknown (the tactics used against these
sources of errors are discussed in Ref. 7), changes in resis-
tance of arms due to self-heating, spurious voltages intro-
duced from the contact of dissimilar metals, and incorrect bal-
ance. The well-made bridge can be expected to measure from
about 0.1 ⍀ to the low megohm range with approximately 1%
accuracy, and for the range 10 ⍀ to 1 M⍀ accuracies of 0.05%
can be expected. A good practice is to make measurements on
a series of extremely accurate and known resistors and to use
the obtained errors as an error guide for measurements with
the closest bridge constants. For measuring very high resis-
tances, the galvanometer should be replaced by a high-imped-
ance device. For measuring very low resistances, one has to
use the double bridge described later.
In measurements of very low resistances, the resistance of
the connector (yoke) between the unknown resistance R1 and
S1 R1
R1 R2 R5
G G
VB S2 VB R6
S3
RP
R4 R3 R7
R4
(a) (b)
BRIDGE CIRCUITS 563
the standard resistance R4 may seriously affect accuracy. The
double (Kelvin) bridge [Fig. 6(b)] is devised to circumvent this
difficulty. In this circuit the resistor R6 represents the resis-
tance of this connector, and R5 and R7 are small resistances
of two additional arms. If one chooses
R5 R
= 2 (31)
R7 R3
(this is easily done in practical designs; see Ref. 6), then, us-
ing Eq. (15), one can find that the relationship among R1 to
R4 given by Eq. (30) will be preserved.
The Kelvin bridge allows one to measure the resistances in
the range 1 ⍀ to 10 ⍀ with accuracy better than 0.1%, and in
the range 0.1 ⍀ to 1 ⍀ better than 1%.
Ac Bridges
The Wheatstone bridge circuit may also be used for imped-
ance measurements at audio/radio frequencies. The battery is
replaced by a generator of sinusoidal voltage, and a sensitive
headset or oscilloscope is used as the balance detector [Fig.
7(a)]. The arms now may include reactive components, and
when the condition of balance, as in Eq. (1), is satisfied, one
can find the component Z1 from the equality
Z2
Z1 = Z (32)
Z3 4
Introducing Zi ⫽ Ri ⫹ Xi (i ⫽ 1, 2, 3, 4) in Eq. (32), one obtains
R2 + jX2
R1 + jX1 = (R + jX4 ) = A + jB (33)
R3 + jX3 4
Hence, to measure two quantities R1 and X1, one can use six
parameters to achieve the balance. This results in an enor-
mous number of different bridges (8) adapted for particular
circumstances.
The selection of configurations to be used in a wider range
of applications (6) is dictated by two factors. First, in general,
attainment of balance is a progressive operation requiring
back and forth in-turn improvements in resistive and reactive
balances. For rapid balancing it is desirable that the adjust-
ment of resistive part A be independent of the adjustment
made in the reactance part jB. This cannot always be done.
In the region of balance the detector voltage is
δV0 = K(Z1 Z3 − Z2 Z4 ) (34)
R2
R3
Figure 6. (a) Wheatstone and (b) Kelvin bridges.
564 BRIDGE CIRCUITS

C1

R1 R2 R2
R1

D D

R4
R4 R3 R3
C4

(a) (b)

L1 L1
R2 R2
R1 R1
D D

R3
R4 R3 C3 R4
C3
Figure 7. Ac bridges: (a) Wheatstone bridge; (b) ratio-arm
capacitive bridge; (c) Maxwell inductance bridge; (d) Hay
inductance bridge. (c) (d)

where K may be assumed constant (9). In general, the most desire to have a constant standard capacitor prevails, and
rapid convergence to balance is obtained when the phase four basic configurations shown in Fig. 7 are used in general-
angle between the selected pair of adjustable components in purpose universal impedance bridges (6).
Eq. (34) is 앟/2 and least rapid when the angle tends to zero. It is impossible here to give even a brief survey of special-
For example, for the bridge of Fig. 7(b) the balance equations ized bridges; yet four configurations deserve to be mentioned.
are Figure 8(a) shows the bridge with the voltage source and de-
tector interchanged. This allows one to apply a polarizing
R2 R3 voltage and measure the parameters of electrolytic capacitors.
R1 = R C1 = C (35)
R3 4 R2 4 The battery that supplies this voltage must be shunted by a
bypass capacitor, CB. Figure 8(b) shows a configuration (the
If R4 and C4 can be adjusted, rapid balancing is obtained. If Owen bridge) adapted for incremental inductance measure-
R4 and R2 are chosen for adjustment, the convergence can be ments. A filter reactor LRF inserted in the bridge measure-
very slow (9). ment circuit minimizes the effect of core-induced harmonics
The second important factor is that a standard capacitance in determining the balance point (R2 and C3 are used for
more nearly approaches the ideal no-loss reactance than does balance).
the best wire-wound coil type of inductance. Hence, it is desir- Figure 8(c) shows the Shering bridge, which is also used
able to measure an inductance in terms of capacitance. This for measuring the capacitance and dissipation factor of the
can be obtained in the Maxwell bridge [Fig. 7(c)]. The balance capacitors—especially at high voltages. The lower part of this
equations for the Maxwell bridge are bridge (resistors R4 and R3 and capacitor C3) may be main-
tained at a relatively low potential, and the adjustment to the
R2 variable elements can therefore be made safely. The balance
L1 = R2 R4C3 R1 = R (36)
R3 4 equations are

The Maxwell bridge is mainly applied for measuring coils of R3 C3

C1 = C2 R1 = R4 (38)
low Q-factors. Indeed, Q1 ⫽ 웆L1 /R1 ⫽ 웆C3R3, and a coil with R4 C2
Q1 ⬎ 10 may require very high values of R3. This limitation
is removed in the Hay bridge [Fig. 7(d)]. The balance equa- Other useful configurations of ac bridges with a wide range
tions for the Hay bridge are of application (bridges for measuring mutual inductances) can
be found in Refs. 6 and 9. Some improvements of the measur-
R2 1 1 ing techniques (the Wagner ground) are described well in
R1 = R L1 = R2 R4C3 (37)
R3 4 Q21 + 1 Q21 + 1 Ref. 9.
As a consequence in the development of transformers with
where Q1 ⫽ 웆L1 /R1 ⫽ 1/(웆C3R3). very tight magnetic coupling, the ratio arms of some bridges
One can see that a disadvantage of the last two circuits is may be replaced by transformer coils. A transformer can also
the interaction between reactive and resistive balance, yet the be used as a current comparator. An example of a circuit us-
 BRIDGE CIRCUITS 565

ing these two properties of transformers is shown in Fig. 8(d)
(9). Here the generator is connected to the primary winding
of voltage transformer T1, and the secondary windings of T1
are tapped to provide adjustable sections of N1 and N2 turns,
respectively. The primary windings of the current trans-
former T2 are also tapped to provide sections with adjustable
turns n1 and n2. The secondary of T2 is connected to a detector.
Let Y1 ⫽ G1 ⫹ jB1 be the unknown admittance, and Y2 ⫽
G2 ⫹ jB2 be a suitable comparison standard. Balance may be
achieved by any suitable combination of adjustments of Y2
and tap positions. The balanced condition corresponds to zero
net flux in the primary of T2. Hence, the condition of balance
is
n1 I1 = n2 I2
If the resistance and the flux leakage in the primary windings
of T2 can be neglected and the core flux is zero, the external
ends of the current transformer have the same potential as
the ground line. The voltages V1 and V2 then appear across
Y1 and Y2, respectively, so that I1 ⫽ Y1V1 and I2 ⫽ Y2V2. In
addition, the ratio of the induced voltages in the secondary of
T1 is V2 /V1 ⫽ N2 /N1. Substituting these simple relationships
in Eq. (39) and separating real and imaginary parts, one ob-
tains
n2 N2 n2 N2
G1 = G B1 = B (40)
n1 N1 2 n1 N1 2
Hence, using suitable combinations of the tappings, a wide
range of multiplying factors are available. For a given set of
standards, this provides a much wider range of measure-
ments than does the conventional ac Wheatstone bridge. This
bridge also allows independent balancing of the conductive
and susceptive components (9).
The degree of accuracy obtained in bridge impedance mea-
surements can be considerably enhanced by adopting substi-
tutional methods of measurement. In these methods, the
bridge is first balanced with the unknown impedance con-
nected in series or in parallel with a standard component in
one of the bridge arms and then rebalanced with the un-
known either short- or open-circuited. The unknown can then
be determined in terms of the changes made in the adjustable
elements, and the accuracy depends on the difference between
the two sets of balance values obtained. Residual errors, such
as stray capacitance and stray magnetic coupling, and any
uncertainty in the absolute values of the fixed bridge compo-
nents are virtually eliminated. These effects are nearly the
same whether or not the unknown is in the circuit.
APPLICATION OF BRIDGE CIRCUITS IN TRANSDUCERS
(39)
Bridge circuits are frequently used to configure transducers—
that is, the circuits providing information about physical vari-
ables (temperature, force, pressure, etc.) capable of changing
the value of one or more components of the bridge. In trans-
ducers, one measures the voltage occurring at the detector (or
a current through the detector). The problems that occur in
this case can be demonstrated using the circuit shown in
Fig. 9(a).
In this circuit the resistors R1, R2, R3 are constant and the
resistor R3 ⫽ R0(1 ⫹ x) is a linear function of a dimensionless
variable x. One can assume that the detector resistance R0 is
very high, and then find the voltage V0 at the detector termi-
nals. One then has
px + (p − mn)
V0 = V (41)
(n + p)(m + 1 + x)
where m ⫽ R2 /R0, n ⫽ R4 /R0. When the variable x ⫽ 0, the
circuit should be balanced; this requires that the condition
p ⫽ mn be satisfied. The voltage at the detector then becomes
mx
V0 = V (42)
(m + 1)(m + 1 + x)

–
C1 L1
+ CB R2
R1 R2 R1 V Cc
B
CC
D
D
R4 VB
Cc R4
R3
C4 C4 LRF C3

(a) (b)

I1
C1 V1
C2
Z1
R1 N1 n1
D
D
N2 n2
Z2
R3 C3 –V2
R4
Voltage I2 Current
transformation transformation Figure 8. Some special ac bridges: (a) electrolytic capac-
itor bridge; (b) Owen increment inductance bridge; (d)
(c) (d ) transformer bridge.
566 BRIDGE CIRCUITS

I I
R1 R2
R0 (1 + x) R0
Vo
– +
V V Vo
Ro

R4 I3 R3 = R0 R0 (1 + x)
R0 (1 + x)

(a) (b)

I I
R0 R0 (1 – x) R0 (1 + x) R0 (1 – x)

– + – +
V Vo V Vo

R0 R0 (1 + x) R0 (1 – x) R0 (1 + x)
Figure 9. Resistive transducer bridges: (a) with
one variable resistor; (b) with two variable resis-
tors; (c) with push-pull variable resistors; (d) with
four variable resistors. (c) (d)

One can see that V0 is a nonlinear function of x. The desired However, this situation is not always inevitable. If the cur-
ideal response would be rent I in the circuit of Fig. 9(a) is constant the detector voltage
will be
mx
V0i = V (43) mnx
(m + 1)2 V0 = IR0
(m + 1)(n + 1) + x

 (47)
The relative error due to nonlinearity, ⑀n, may be calculated mnx x
as ≈ IR0 1−
(m + 1)(n + 1) (m + 1)(n + 1)
V0i − V0 x x The nonlinearity error is
n = = ≈ (44)
V0i m+1+x m+1
x
n = (48)
The reduction of ⑀n is a frequent requirement in transducer (m + 1)(n + 1)
applications. In the case being considered this can be
achieved by increasing m and restricting the range of x. This This error is decreasing for increasing m and n. The sensitiv-
means that one is trying to establish a constant current ity in this case is
through R3 (assuming that the voltage V is constant) and is mnx
using the bridge measurements for reasonably small x. Sv = I (49)
(m + 1)(n + 1) + x
Another important parameter of the circuit of Fig. 9(a) is
its sensitivity. Resistor R3 may be considered as the ‘‘tuning’’ and its maximum value, achievable for m ⫽ 앝, n ⫽ 앝, is
element of the bridge; in this case its variation for small x is
웃 x ⫽ R0 x, and in the vicinity of balance one can take 웃V0 ⫽ Svmax = I (50)
V0. Then the voltage sensitivity is
Hence, in this case there is no contradiction between optimi-
V0 V m zation of sensitivity and reduction of nonlinearity. In the pas-
Sv = = (45)
R0 x R0 (m + 1)(m + 1 + x) sive circuit, though, the condition of constant current I can be
achieved only approximately.
Its maximum value The results of analysis for the bridge with one variable re-
sistor may be represented by Table 1. It allows one to con-
V 1 clude (7) that—to reduce the nonlinearity error—one has to
Svmax = (46)
R0 (m + 1)2 restrict the measuring range, work with reduced sensitivity,
or consider current source realization in order to use it as a
is achieved when m 앒 1. This result shows that in this partic- power supply for the bridge or the variable resistor.
ular case the condition of maximum sensitivity conflicts with An increase of sensitivity with a simultaneous decrease of
minimization of nonlinearity error. nonlinearity can also be achieved by using two variable resis-
 BRIDGE CIRCUITS 567

Table 1. Properties of the Bridge with One Variable Resistor

Supply Nonlinear Maximal Parameters Approximate
Condition Sensitivity Error, ⑀n Sensitivity Required Conditions
Vo
Sv ⫽
xR0
V m x V 1
V constant m2 ⫽ 1 ⫹ x, q ⫽ 앝 R2 ⫽ R3
R0 (m ⫹ 1)(m ⫹ 1 ⫹ x) m⫹1 R0 (m ⫹ 1)2
mn x m ⫽ 앝, n ⫽ 앝, q ⫽
I constant I I R2 Ⰷ R0 , R4 Ⰷ R0
mn ⫹ m ⫹ n ⫹ 1 ⫹ x mn ⫹ m ⫹ n ⫹ 1 앝
m
I3 constant I3 absent I3 m ⫽ 앝, q ⫽ 앝 R2 Ⰷ R0
m⫹1
Io
Si ⫽
xR0

V m x(m2 ⫹ 움) V (1 ⫺ m) q ⫽ m2(q ⫹ 1), n ⫽ 0

V constant R4 Ⰶ R0
R 20 (m ⫹ 1)움 ⫹ (m2 ⫹ 움)x 움(m ⫹ 1) R0 (1 ⫹ m) small x
I mn x[m(n ⫹ 1) ⫹ q] I 1 q ⫽ n2 ⫺ 1, m ⫽ 앝
I constant R2 Ⰷ R0
R0 (n ⫹ 1)움 ⫹ [m(n ⫹ 1) ⫹ q]x (n ⫹ 1)움 R0 (n ⫹ 1) small x
I m I3 1 m⫽앝
I3 constant absent R2 Ⰷ R0 , Rm Ⰷ R0
R0 (m ⫹ 1)q R0 q large q
Note: m ⫽ R2 /R0 , n ⫽ R4 /R0 , p ⫽ R1 /R0 , q ⫽ Ro /R0 ; R3 ⫽ R0(1 ⫹ x); 움 ⫽ q(m ⫹ 1) ⫹ m(n ⫹ 1); balance requirement p ⫽ mn.

tors in opposite arms [Fig. 9(b)] or by using resistors undergo-
ing opposite variations in adjacent arms [Fig. 9(c)] or by using
variable resistors in all four arms [Fig. 9(d)]. Table 2 (7) sum-
marizes and compares the results for the output voltage in all
such bridges for the case in which all resistors have the same
initial value of R0. Again, one can see that the bridges pow-
ered by a current source (which leads to active circuits) have
more choices for linearization.
The realization (10) of the current source for the powering
bridge usually involves [Fig. 10(a)] a second voltage source
(denoted here as Zener diode voltage, VR) and an operational
amplifier. The bridge current is I ⫽ VR /RR.
Switching to active circuits, some other alternatives should
be considered. The circuit of Fig. 10(b), which provides a lin-
early dependent output voltage
x Two variable impedances (sensor arms), Z ⫹ 웃Z and Z ⫺ 웃Z,
V0 = −V
2 operate in a push-pull fashion. The ratio arms represent a
can be considered as one alternative. The circuit of Fig. 10(b)
requires the bridge to have five accessible terminals. The cir-
cuit of Fig. 10(c), with two operational amplifiers, can also be
considered. It provides a linearly dependent output voltage
RG
V0 = V x (52)
R0
and amplifies the bridge output signal.
Capacitive and inductive transducers can be used in a vari-
ety of ac bridge circuits. Here we discuss only the so-called
Blumlein bridge circuit. It has particular advantages for use
with variable capacitive transducers (11) and is used fre-
quently with inductive transducers as well. The circuit is
shown in Fig. 11(a). Let the detector impedance be Z0 ⫽ 앝.
(51)

Table 2. Output Voltage for Bridges with Variable Resistors and Supplied by a Constant Voltage or Current
R1 R2 R3 R4 Constant V Constant I
x x
R0 R0 R0(1 ⫹ x) R0 V IR0
2(2 ⫹ x) 4⫹x
x x
R0(1 ⫹ x) R0 R0(1 ⫹ x) R0 V IR0
(2 ⫹ x) 2
2x x
R0 R0 R0(1 ⫹ x) R0(1 ⫺ x) V IR0
4 ⫺ x2 2
x x
R0 R0(1 ⫺ x) R0(1 ⫹ x) R0 V IR0
2 2
x2 x2
R0(1 ⫺ x) R0 R0(1 ⫹ x) R0 ⫺V ⫺IR0
4 ⫺ x2 2
R0(1 ⫹ x) R0(1 ⫺ x) R0(1 ⫹ x) R0(1 ⫺ x) Vx IR0 x
568 BRIDGE CIRCUITS

VCC
R0
RB R1 R2 R0 R0 (1 + x)

+
Vo
A1 –
V
– A1
R4 R3 + Vo

R0
VR I RR

(b)
(a)

R0 RG
R0 (1 + x)
–
R0 R0 A2
– Vo
+
A1
V
+

Figure 10. (a) Current source for bridge powering

and linearized active bridge circuits: (b) with one am-
plifier and (c) with two amplifiers. (c)

I1
Z – δZ Z + δZ Z I2 Z

V Vo V Vo = 0

M M

L L L L

(a) (b)

– +
Iδ Z Iδ Z + Z + δZ
+ –
V Z1
δ I1 Z Z δ I2 –

δ V0 –

M + +
δ V0
}

V
–
L L Z – δZ

Figure 11. (a) Blumlein bridge and (b) the circuits for cal-
culation of branch currents and (c) current variations; (d)
pseudobridge circuit. (c) (d)
 BRIDGE CIRCUITS 569

transformer with two tightly coupled coils (i.e., L ⫽ M ). The transfer function of this system is
bridge is fed by a sinusoidal voltage V.
Analysis of steady state can be done in two stages. When V0 z21Z0
T (s) = = (59)
the sensor arms have equal impedances Z [Fig. 11(b)], one Eg Zg Z0 + Zg z22 + Z0 z11 + |z|
finds that
where
V
I1 = I2 = I = (53)
Z (Z1 + Z4 )(Z2 + Z3 ) (Z1 + Z2 )(Z3 + Z4 )
z11 = z22 =
Z1 + Z2 + Z3 + Z4 Z1 + Z2 + Z3 + Z4
Indeed, in this condition the magnetic flux in the transformer
is zero and the detector voltage and the voltage at each trans- Z2 Z4 − Z1 Z3
z12 = z21 = |z| = z11 z22 − z212
former coil are zero. The variations of the impedances may be Z1 + Z2 + Z3 + Z4
represented, in accordance with the compensation theorem
(see the first section of this article), by two voltage sources. One of the main problems of network synthesis is the real-
The circuit [Fig. 11(c)] that includes only these two sources ization of a transfer function with prescribed zeros. The zeros
can be used for calculation of current variations. Writing two of transmission (which are the zeros of the transfer function)
loop equations for this circuit, one finds that can now be interpreted as the frequencies at which the bridge
is balanced. This result, obtained for the simple bridge, is
IδZ valid for all bridge configurations. Hence, the synthesis of
δI1 = δI2 = δI = (54)
Z + 2 jωL simple rejection filters (such as the twin-T bridge, or T
bridge), the transfer function of which includes two complex-
The variation of the detector voltage is conjugate zeros, can be simplified if the balance condition is

δZ

2 jωL
 used directly for the choice of filter elements.
δV0 = 2IδZ − 2ZδI = 2V (55) The control of transmission zeros location becomes espe-
Z Z + 2 jωL cially simple if the lattice is symmetric. For Z2 ⫽ Z4 ⫽ Za and
Z1 ⫽ Z3 ⫽ Zb, the transmission zeros occur at those values of
This result can be used for evaluation of the Blumlein bridge s for which the two branch impedances have equal values.
sensitivity. For a capacitive sensor, Z ⫽ 1/i웆C. Then 웃Z/Z ⫽ This can be arranged to occur for any value of s; hence, the
⫺웃C/C, and one obtains locations of the transmission zeros of a lattice are un-

δC

2ω2 LC
 restricted and may occur anywhere in the s-plane. For exam-
δV0 = 2V (56) ple, if Z1 ⫽ Z3 ⫽ R0 and Z2 ⫽ Z4 ⫽ R ⫹ Ls ⫹ 1/Cs, the trans-
C 1 − 2ω2 LC mission zeros are given by the zeros of a polynomial

Hence, the sensitivity of the Blumlein bridge with capacitive LCs2 + (R − R0 )Cs + 1 = 0 (60)
sensor arms is a function of frequency. For a stable result one
must choose the parameters so that 2웆2CL Ⰷ 1. and are located in the left-half s-plane for R ⬎ R0, on the j웆-
For an inductive sensor Z ⫽ i웆l. Then 웃Z/Z ⫽ 웃l/l and axis for R ⫽ R0, and in the right-half s-plane for R ⬍ R0. If
δl

2L
 L ⫽ 0, one can obtain a zero on the positive real axis.
δV0 = 2V (57) It can be proved (13) that every symmetric, passive, recip-
l 1 + 2L rocal, lumped, and time-invariant two-port has a physically
realizable lattice equivalent. Thus, the lattice is the ‘‘most
This analysis demonstrates that in the Blumlein bridge
general’’ symmetric two-port. The lattice has an important
one essentially has comparison of currents at zero potential
role in the modern network synthesis (15) and, in the past,
of the transformer arms. Hence, the capacitive parasitics at
was a useful tool in the general image parameter theory of
the detector terminals are not important. Using a third out-
filter design (16).
put transformer coil (as was the case for the transformer
bridge), one can realize a very sensitive capacitive sensor.
The idea of current comparison is more directly used in BRIDGE CIRCUITS IN ELECTRONICS
the ‘‘pseudobridge’’ circuit [Fig. 11(d)], where the difference in
currents of the sensor arms is entering the virtual ground and In this section we describe oscillators, the operation of which
produces the output signal can only be fully understood if the bridge balanced condition
is considered.
Z1 δZ
δV0 ≈ 2V (58) Figure 12 shows the Wien bridge [Fig. 12(a)], twin-T bridge
Z Z [Fig. 12(b)], and Meachem bridge [Fig. 12(c)] sinusoidal oscil-
lators. The steady-state operation of all three oscillators re-
Pseudobridges are mostly used with capacitive sensors (12).
quires that, at a certain frequency, the condition

BRIDGE CIRCUITS IN NETWORK SYNTHESIS AT B ( jω) = 1 (61)

Let us return to the lattice form of the bridge [Fig. 1(b)] and be satisfied. Here, TB( j웆) is the transfer function of the corre-
consider the impedances Z1 to Z4 as a coupling two-port of the sponding bridge calculated at s ⫽ j웆. The transfer functions
transmission system [Fig. 2(b)]. One then finds that the of the Wien bridge and twin-T bridge should be designed so
570 BRIDGE CIRCUITS

C1
R1 R3
R1 R2
– – Avo(t)
vo (t) C6
+ – +
+ Avo (t) +
C4 C4 vo (t)
R4 R3
C2 R5
–

(a) (b)

jω
C1 jω 0

R1 R2 jω 0
–
σ σ
L1 –σ 1 –σ2 –α2 α 1
+
vo (t) –jω 0
+ –
Figure 12. Sinusoidal oscillators: (a) Wien
R4 R3 –jω 0
bridge; (b) twin-T bridge; (c) Meachem
bridge; and pole-zero diagrams of bridge
transfer functions: (d) Wien and twin-T
bridge; (e) Meachem bridge. (c) (d) (e)

that A very important oscillator parameter (16) is the indirect

(s2 − α1 s + ω02 )
TB (s) = K
(s + σ1 )(s + σ2 )
has two complex-conjugate zeros located in the right half of
the s-plane in the vicinity of the points ⫾j웆0 [the result of Eq.
(62) assumes that, for the twin-T bridge, the real zero and
real pole are cancelled]. For the Wien bridge, 웆0 ⫽
兹(R1C1R4C4), 움1 ⫽ [(R2R4 ⫺ R1R3)/(R1R3R4C4)] ⫺ 1/(R1C3). For
the twin-T bridge the elements providing desirable zeros loca-
tion should be chosen using the balance condition of Eq. (13).
The transfer function of the Meachem bridge should be
(s2 − α1 s + ω02 )
TB (s) = K
(s + α2 s + ω02 )
Here, 웆0 ⫽ 兹(L1C1), 움1 ⫽ (R2R4 ⫺ R1R3)/(2L1R3), and 움2 ⫽
(R1 ⫹ R4)/(2L1). In all cases, 웆0 is the desirable oscillation fre-
quency.
In the vicinity of the points ⫾j웆0, the transfer function of
the bridge will be
TB ( jω0 ) = |TB ( jω0 )|eφ ( jω 0 )
and the condition of Eq. (61) can be rewritten as
A|TB ( jω0 )| = 1 φ( jω0 ) = 0 or 180◦
The first condition in Eq. (65) gives the required amplifier
gain, and the second condition gives the required sign of gain.
frequency stability, S웆. It is calculated as
(62) 
dφ 
Sω = ω0 (66)
dω ω=ω
0
In the vicinity of 웆0, only the nearest zeros and poles are im-
portant, and this stability will be
Sω ≈ −2Qz (67)
for the Wien-bridge and twin-T oscillators. Here Qz ⫽ 웆0 /
(2움1). For the Meachem bridge oscillator, one has
(63)
Sω ≈ −2Qz − 2Qp (68)
where Qp ⫽ 웆0 /(2움2). One can see that the achieved indirect
frequency stability is determined by the chosen bridge imbal-
ance [the reactance branch in Meachem bridge oscillator is
usually a crystal, and the location of poles in TB(웆) is deter-
mined by the crystal parameters]. The connection between
(64) bridge imbalance and design for frequency stability is well
known for the Wien bridge and Meachem bridge oscillators
(16), however, it is still not clearly understood in the twin-T
bridge oscillator design (17).
(65) The application of the bridge circuits to design of nonsinu-
soidal oscillators is less known. Using switches in a two-oper-
ational amplifier multivibrator, one can obtain control of the
oscillation frequency by detuning a resistive bridge (Fig. 13).
 BRIDGE INSTRUMENTS 571

3. E. Brenner and M. Javid, Analysis of Electric Circuits, 2nd ed.,

P1 + New York: McGraw-Hill, 1967.
VCC
4. S. Seshu and N. Balabanyan, Linear Network Analysis, New
R1 R2
C York: Wiley, 1959.
– 5. E. V. Zelyakh, General theory of linear electric networks, Moscow:
– Acad. of Sci. USSR, 1951 (in Russian).
+ v0
6. H. E. Thomas and C. A. Clarke, Handbook of Electronic Instru-
+ Ra ments and Measurement Techniques, Englewood Cliffs, NJ: Pren-
Rb tice-Hall, 1967.
–
R4 R3 VCC 7. R. Pallás-Areny and J. G. Webster, Sensor and Signal Condition-
ing, New York: Wiley, 1991.
P2
8. B. Hague, Alternating Currents Bridge Methods, London: Pit-
man & Sons, 1938.
(a)
9. R. G. Meadows, Electric Network Analysis, Harmondsworth, Mid-
dlesex, UK: Penguin Books, 1972.
+ 10. S. Franco, Design with Operational Amplifiers and Analog Inte-
P1 VCC
grated Circuits, New York: McGraw-Hill, 1988.
R1 R2 C 11. H. K. P. Neubert, Instrument Transducers, Oxford, UK: Claren-
don Press, 1975.

– 12. L. Baxter, Capacitive Sensors, New York: IEEE Press, 1997.

+ 13. W. H. Chen, Linear Network Design and Synthesis, New York:
+ McGraw-Hill, 1964.
– v0
14. D. F. Tuttle, Electric Networks: Analysis and Synthesis, New York:
–
VCC McGraw-Hill, 1965.
R4 R3
15. M. B. Reed, Electric Network Synthesis—Image Parameter
P2
Method, Englewood Cliffs, NJ: Prentice-Hall, 1955.
16. K. K. Clarke and D. T. Hess, Communication Circuits: Analysis
(b) and Design, Reading, MA: Addison-Wesley, 1971.
Figure 13. Bridge-controlled multivibrators: (a) with Schmitt trig- 17. N. Boutin and A. Clavet, The misunderstood twin-T oscillator,
ger; (b) with comparator. IEEE Circuits Syst., 2: 8–13, 1980.
18. J. H. Huizing, G. A. van Rossum, and M. van der Lee, Two wire
bridge-to-frequency converter, IEEE J. Solid-State Circuits, SC-
For normal circuit operation, the bridge should be unbal- 22: 343–349, 1987.
anced. The oscillation frequency of this circuit is

1

R R3
 I. M. FILANOVSKY
f0 = 2
− University of Alberta, Edmonton
2C R1 R4
+ −
(VCC − VCC )Rb
(69)
[Rb (R3 − R2 )(VCC
+ − V − ) + R (R + R )(V + − V − )]
CC a 2 3 0 0

The use of a comparator allows one to eliminate the feedback

resistances of the Schmitt trigger [Fig. 13(b)]. For this circuit,
the oscillation frequency is

1

R R3

2
f0 = − (70)
4CR3 R1 R4

Both circuits are used as bridge-to-frequency converters in

two-wire transducers (18).

CONCLUSION

Bridge circuits form a specialized, yet a wide-ranging, group

of circuits that find application in measurement techniques,
transducers, network synthesis, and electronics.

BIBLIOGRAPHY

1. H. H. Skilling, Electrical Engineering Circuits, New York: Wi-

ley, 1958.
2. R. E. Scott, Linear Circuits, Reading, MA: Addison-Wesley, 1960.

BUTTERWORTH FILTERS
Electrical filters made by linear, lumped, and finite compo-
nents present a real rational transfer function T(s) ⫽
Vout(s)/Vin(s). For real frequencies, T( j웆) ⫽ 兩T( j웆)兩ej⌰(웆), where
兩T( j웆)兩 is the filter linear gain. Alternatively we may use
J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.
BUTTERWORTH FILTERS 657
G(웆) ⫽ 20 log10 兩T( j웆)兩, the filter gain in dB, or A(웆) ⫽
⫺G(웆), the filter attenuation. ⌰(웆) is the filter phase, but we
may advantageously use the group delay ␶(웆) ⫽ ⫺⭸⌰(웆)/⭸웆.
Ideal filters should have constant gain and constant group
delay in frequency bands called pass bands and infinite atten-
uation in frequency bands called stop bands. Real filters only
approximate these characteristics. In general, no attention is
paid to phase when approximating gain characteristics, for
satisfying gain and phase in tandem is a problem that usually
does not admit closed-form solution and requires an iterative
optimization procedure. If phase equalization is necessary,
the usual practice is to perform it later using other circuits.
Classical approximation methods are usually developed for
normalized low-pass filters with a pass band between 0 rad/s
and 1 rad/s, where the attenuation variation—the pass-band
ripple—must not exceed Ap, and with a stop band from 웆s ⬎
1 rad/s to infinity, where attenuation must exceed the mini-
mum attenuation in the pass band by at least As.
Other low-pass, high-pass, band-pass, and band-stop filters
can be designed by trivial frequency transformations applied
onto the normalized low-pass-filter prototype, and will not be
discussed here.
HISTORICAL BACKGROUND
The concept of electrical filters was independently developed
by Campbell and Wagner during World War I. These early
electrical wave filters easily accomplished the stop-band re-
quirements, but a reasonably constant gain in the pass band
required heuristically tuning of some filter resistors.
In his seminal work, Butterworth (1) attacked the problem
of designing linear intervalve resonating circuits in such a
way that the overall circuit combined amplification and fil-
tering, matching the desired characteristics in both stop band
and pass band without a tuning procedure. For the normal-
ized low-pass filter, Butterworth proposed a ‘‘filter factor’’ F,
nowadays corresponding to the filter gain 兩T( j웆)兩, such that
|T ( jω)|2 = 1/(1 + ω2n ) = 1/L(ω2 ) (1)
where n is the filter order. Figure 1 shows 兩T( j웆)兩 vs. 웆 for
n ⫽ 2, 4, 7, and 10. It is clear that 兩T( j웆)兩 approaches the
ideal low-pass-filter characteristics when n is increased, satis-
fying pass-band and stop-band requirements. Moreover, But-
terworth cleverly realized that for n even L(웆2) could be de-
composed as a product of n/2 second-order polynomials Pi(웆),


n/2

n/2
L(ω2 ) = Pi (ω) = [1 + 2ω cos(2i − 1)π/2n + ω2 ]
i=1 i=1
and showed that (1) the product of conveniently selected pairs
of polynomials comprised a function Li(웆2) ⫽ Pi(웆)Pn/2⫺i(웆),
which could be associated with a second-order filter, and (2)
the product of four polynomials selected as described pre-
viously comprised a function Li(웆2)Lj(웆2), which could be asso-
ciated with a fourth-order filter. All components of these low-
order filters could be easily calculated, and the filters could
be used as coupling stages between amplifier tubes. For the
first time it was possible to construct a filter amplifier that
required no heuristic tuning (2).
658 BUTTERWORTH FILTERS

1 we verify that ⭸jL(웆2)/⭸웆j at 웆 ⫽ 0 is zero for j odd and equals

j!aj for j even. For the moment, let us normalize 兩T( j0)兩 ⫽ 1.
0.9
This leads to a0 ⫽ 1 in Eq. (3). For a filter to be of order n,
0.8 a2n ⫽ ⑀2 ⬆ 0 in Eq. (3). From these considerations, to cancel
the maximum number of derivatives of L(웆2)—and conse-
0.7
quently those of 兩T( j웆)兩—at 웆 ⫽ 0, we must choose aj ⫽ 0 for
0.6 j ⫽ 1 to 2n ⫺ 1, leading to
H(jω)

0.5 L(ω2 ) = 1 +  2 ω2n (4)

0.4
which is similar to L(웆2) in Eq. (1) if we choose ⑀ ⫽ 1. The
0.3 n=2 Butterworth approximation is the answer we were looking
0.2 for. Two important considerations must be given on this new
n=4 parameter ⑀.
0.1 n = 10 n=7
0 1. As A(0) ⫽ 0 and A(웆) is clearly a monotonically increas-
0 0.5 1 1.5 2 2.5 3 3.5 ing function, ⑀ controls the attenuation variation, or
ω (rad/s) gain ripple, in the pass band:
Figure 1. Magnitude of the Butterworth transfer function for n ⫽ 2,
4, 7, and 10.
Ap = A(1) − A(0) = 10 log10 (1 +  2 ) (5)

It is interesting to notice that the pass-band ripple is

SOME COMMENTS ON BUTTERWORTH FILTERS independent of the filter order n, depending only on ⑀.
On the other hand,
Butterworth’s contribution for approximating and synthesiz-
ing filters that are well behaved both in the pass band and As = A(ωs ) − A(0) = 10 log10 (1 +  2 ωs2n ) (6)
stopband was immediately recognized and still stands for its
historical and didactic merits. Even nowadays, compared with From Eqs. (5) and (6) we verify that the require-
others, Butterworth’s approximation is simple, allows simple ments for the pass band and stop band are satisfied if
and complete analytical treatment, and leads to a simple net-
work synthesis procedure. For these reasons, it is an invalu-  ≤ (100.1A p − 1)1/2 (7)
able tool to give students insight on filter design and to intro-
and
duce the subject to the novice. From now on, we intend to
present the Butterworth filter with emphasis on this didac-
log10 [(100.1A s − 1)/ 2 ]
tic approach. n≥ (8)
The Butterworth approximation is an all-pole approxima- 2 log10 ωs
tion, that is, its transfer function has the form
2. As ⑀2웆2n ⫽ (⑀1/n웆)2n, Eq. (4) and consequently the filter
T (s) = k0 /D(s) (2) gain may be written as a function of ⑀1/n웆 instead of 웆.
So ⑀1/n is merely a frequency scaling factor that may be
and its n transmission zeros are located at infinity. normalized to 1 without loss of generality in the study
The Butterworth approximation is sometimes called the of the maximally flat approximation, yielding the origi-
maximally flat approximation, but this denomination, first nal Butterworth approximation given by Eq. (1).
used by Landon (3), also includes other approximations. The
idea of the maximally flat gain is to preserve filter gain as
BUTTERWORTH TRANSFER FUNCTION
constant as possible around the frequency at which the most
important signal components appear, by zeroing the largest
We are now interested in determining the filter transfer func-
possible number of derivatives of the gain at that frequency.
tion T(s), which corresponds to Eq. (1). Using the analytical
The Butterworth approximation is just the all-pole approxi-
continuation 웆 ⫽ s/j (or 웆2 ⫽ ⫺s2)
mation with maximally flat gain at 웆 ⫽ 0.

1 1 
|T ( jω)|2 = T (s)T (−s)|s= jω =
MAXIMALLY FLAT APPROXIMATION D(s) D(−s) s= jω
 (9)
1 
Let us consider the family of normalized low-pass all-pole fil- =
L(−s2 ) −s 2 =ω 2
ters of order n. We search for the approximation with maxi-
mally flat gain at 웆 ⫽ 0. For all-pole approximations, L(웆2) is
a polynomial in 웆2. Comparing the polynomial L(웆2) and its and
MacLaurin series
L(−s2 ) = D(s)D(−s) = 1 + (−s2 )n = 1 + (−1)n s2n
  
n 2n
1 ∂ j L(ω2 ) 
L(ω2 ) = a2i ω2i = ωj (3) we verify that the roots of L(⫺s2) are the filter poles and their
i=0 j=0
j! ∂ω j ω=0
symmetrical points with respect to the origin. The roots si of
 BUTTERWORTH FILTERS 659

1.5 1.5

jω jω

1 1

0.5 0.5

σ σ
0 0

–0.5 –0.5

–1 –1

–1.5 –1.5
–12 –1 –0.8 –0.6 –0.4 –0.2 0 0.2 –12 –1 –0.8 –0.6 –0.4 –0.2 0 0.2
Figure 2. Butterworth filter poles for (a) n ⫽ 4 and (b)
(a) (b) n ⫽ 7.

L(⫺s2) are Table 1 shows the coefficients di and the Qi factors of the
poles of D(s) for n ⫽ 1 to 7.
si = e j(2i+n−1)π /2n, i = 1, 2, . . ., 2n
PHASE AND GROUP DELAY
where j ⫽ ⫹兹(⫺1). All roots si have unitary modulus and are
equally spaced over the unitary-radius circle. As the filter Group delay gives more practical information than phase
must be stable, we take the roots si in the left-half s plane as characteristics and is easier to calculate. From Eqs. (9) and
the roots pi of D(s) (the poles of the filter), that is, (10) we verify that T(s) may be written as the product of first-
and second-order functions, and so the group delay is the ad-
dition of the group delay of each of these functions. Using
pi = e j(2i+n−1)π /2n, i = 1, 2, . . ., n

1 ∂T (s)  
τ (ω) = Ev 
For n odd there exists a real pole at s ⫽ ⫺1; for n even all T (s) ∂s 
s= jω
poles are complex. Figure 2 shows the filter poles for n ⫽ 4
and n ⫽ 7. in these low-order functions, where Ev( ⭈ ) is the even part of
Knowledge of the roots of D(s) allows us to calculate its ( ⭈ ), it is easy to show that the group delay is given by
coefficients di, or to factor D(s) in second-order polynomials
(s2 ⫹ s/Qi ⫹ 1) where 1  1 1 + ω2
τ (ω) = +
1+ω 2
i
Qi 1 − (2 − 1/Q2i )ω2 + ω4
1
Qi = −
2 cos [(2i + n − 1)π/2n] where the first term comes from the first-order term of T(s),
if it exists, and the summation is done over all second-order
for i ⫽ 1, . . ., n/2 if n is even or i ⫽ 1, . . ., (n ⫺ 1)/2 if n is
odd, when a factor s ⫹ 1 is also added.
Table 1. Coefficients and Q Factors for the




n/2 Butterworth Filters

 (s2 + s/Qi + 1) for n even

n  n d1 d2 d3 Q1 Q2 Q3
D(s) = d i si = i=1 (10)



(n−1)/2
1 1.0000


 (s + 1) (s2 + s/Qi + 1) for n odd
i=0
2 1.4142 1.0000 0.7071
i=1 3 2.0000 2.0000 1.0000 1.0000
4 2.6131 3.4142 2.6131 1.3066 0.5412
A curious property is that, as D(s) is real and its roots are 5 3.2361 5.2361 5.2361 1.6180 0.6180
on the unitary-radius circle, its coefficients are ‘‘symmetrical,’’ 6 3.8637 7.4641 9.1416 1.9319 0.7071 0.5176
7 4.4940 10.0978 14.5918 2.2470 0.8019 0.5550
that is, di ⫽ dn⫺i for i ⫽ 0, . . ., n. Obviously d0 ⫽ dn ⫽ 1.
660 BUTTERWORTH FILTERS

14 For a given source resistor Rs, P1(웆) reaches its maximum

Pm when Z1( j웆) matches Rs, that is, at frequencies where
12 Z1( j웆) ⫽ Rs.
 
 V (ω) 2
10 P1 (ω) =  in  Re{Z ( jω)}
n = 10 Z1 ( jω)  1

8 |Vout (ω)|2
Po (ω) =
τ (ω) (s)

n=7
6 |Vin (ω)|2
4 n=4
2 n=2
0
0 0.5 1 1.5
ω (rad/s)
Figure 3. Group delay of Butterworth filters for n ⫽ 2, 4, 7, and 10.
terms of T(s). The first term monotonically decreases from 1
to 0 as 웆 increases. The other terms begin as 1/Qi at 웆 ⫽ 0,
peak to 앒2Qi at 웆 앒 1 ⫺ 1/8Qi2 앒 1, and then decrease to zero
as 웆 further increases. The approximations hold for 4Qi2 Ⰷ 1.
The result is that for the cases of interest, with Ap not too
large, say Ap ⬍ 1 dB, and n not too small, say n ⬎ 4, the group
delay of Butterworth filters is practically monotonically in-
creasing in the pass band and is easily compensated by sim-
ple all-pass filters. Figure 3 shows the group delay for n ⫽ 2,
4, 7, and 10. Remember that, due to the frequency scaling
used to reduce the pass-band ripple, the pass-band edge corre-
sponds to ⑀1/n ⬍ 1.
SYNTHESIZING BUTTERWORTH FILTERS
RL
Pm =
4Rs
where Re兵 ⭈ 其 means the real part of 兵 ⭈ 其. Butterworth filters
present maximum gain at 웆 ⫽ 0, and at this frequency the
filter must transmit the maximum possible power to the load
RL. At 웆 ⫽ 0 inductors act as short circuits, capacitors as open
circuits, and by inspection of Fig. 4 we verify that Z1( j0) ⫽
RL. For maximum power gain at 웆 ⫽ 0 we choose RL ⫽ Rs.
Still by inspection of Fig. 4, we verify that 兩T( j0)兩 ⫽ 
. As
d0 ⫽ 1, we must choose k0 ⫽ 
in Eq. (2) and consequently
Eq. (1) becomes
|T ( jω)|2 = 1/4L(ω2 )
We will use here the simple synthesis procedure described
in Ref. 4 and will make use of all simplifications allowed by
the Butterworth approximation. Let us introduce the filter
transducer function H( j웆) such that
Pm R 1
|H( jω)|2 = = L = L(ω2 ) = 1 + ω2n
P1 (ω) 4Rs |T ( jω)|2
measures the power rejection by the filter at frequency 웆. As
Pm ⱖ P1(웆), 兩H( j웆)兩2 ⱖ 1, and the equality is reached only at
the frequencies of maximum power gain. Let us also introduce
the filter characteristic function K( j웆) such that

The filter is implemented as a linear network synthesized to |K( jω)|2 = |H( jω)|2 − 1 = ω2n
exhibit the desired frequency behavior. Implementation is re-
lated to the technology chosen for the filter assemblage. Al-
though progress has brought new technologies for synthesiz-
Rs L2 Ln –1 Vout
ing and implementing filters, the doubly loaded LC ladder
network with maximum power gain still remains the basis of
most synthesis procedures, due to the its low gain sensitivity Vin
to the network components. This synthesis method is usually C1 C3 Cn RL
very complex, but the peculiarities of Butterworth equations
allow simplifications that make this filter very adequate to
introduce the doubly loaded LC ladder network synthesis
Z1
method to students.
(a)
First, we already know a structure to be used with all-pole
filters. As the transmission zeros of a ladder network are the
Rs L2 Ln Vout
poles of the series-branch impedances and the shunt-branch
admittances, a possible network topology is shown in Fig. 4
for n odd and even. Vin
If we find a suitable Z1(s), the synthesis problem reduces C1 C3 Cn – 1 RL
to the easy realization of a one-port network with impedance
Z1(s) through the extraction of poles at infinity, alternating
from the residual admittance and impedance (the ‘‘chop-chop’’
Z1
method) until it remains only a constant, implemented by the
(b)
load resistor RL. The final topology will be given by Fig. 4.
As the LC network is lossless, the active power P1(웆) going Figure 4. Low-pass all-pole doubly loaded LC ladder network for (a)
into Z1( j웆) will be dissipated as active power P0(웆) at RL. n odd and (b) n even.
 BUTTERWORTH FILTERS 661

Table 2. Element Values for the Butterworth Filter 4. Obtain the normalized low-pass prototype by frequency-
scaling the standard filter, multiplying all reactive ele-
n A1 A2 A3 A4 ments by ⑀1/n.
1 2.0000 5. Invert step 1, that is, denormalize the low-pass proto-
2 1.4141 1.4142 type obtained in step 4.
3 1.0000 2.0000 1.0000
4 0.7653 1.8478 1.8478 0.7653
5 0.6180 1.6180 2.0000 1.6180 CONCLUSIONS
6 0.5176 1.4142 1.9319 1.9319
7 0.4450 1.2470 1.8019 2.0000 Butterworth’s paper is the touchstone of modern filter-ap-
proximation theory. However, its low selectivity when com-
pared to that of other approximations restricts its use to situ-
ations that require low sensitivity at the center of the pass
is also a measurement of the power rejection by the filter at band and/or a good group delay flatness. Probably the major
frequency 웆. As 兩H( j웆)兩2 ⱖ 1, 兩K( j웆)兩2 ⱖ 0, and the equality is importance of Butterworth filter nowadays is for didactic pur-
reached only at the frequencies of maximum power gain. poses. Its simplicity and complete analytical formulation
After some algebraic manipulation and using analytical make it the best option to introduce filter synthesis to stu-
continuation to obtain dents.
K(s) sn
= BIBLIOGRAPHY
H(s) D(s)

it is possible to show that 1. S. Butterworth, On the theory of filter amplifiers, Wireless Engi-
neer, Vol. 7, pp. 536–541, 1930. Reprinted in M. E. Van Valken-
K(s) burg (ed.), Circuit Theory: Foundations and Classical Contribu-
1− tions, from J. B. Thomas (series ed.), Benchmark Papers in
H(s) D(s) − sn
Z1 (s) = Rs = Rs Electrical Engineering and Computer Science, Pennsylvania: Dow-
K(s) D(s) + sn den, Hutchinson & Ross, 1974.
1+
H(s) 2. V. Belevitch, Summary of the history of circuit theory, Proc. IRE,
50: 848–855, 1962. Reprinted as (1).
and Z1(s) may be easily synthesized by the chop-chop method, 3. V. D. Landon, Cascade amplifiers with maximal flatness, RCA
concluding the synthesis procedure. Rev., 5: 347–362, 1941.
For Butterworth filters the number of frequency points 4. G. Daryanani, Principles of Active Network Synthesis and Design,
with maximum power transfer is maximum (all concentrated New York: Wiley, 1976.
at the origin). All-pole filters with this characteristic are sym- 5. L. Weinberg, Explicit formulas for Tschebyscheff and Butter-
metrical if n is odd and antisymmetrical if n is even, that is, worth ladder networks, J. Appl. Phys., 28: 1155–1160, 1957.
Ai is equal to An⫹1⫺i for all i, where Ai denotes the numerical 6. H. J. Orchard, Synthesis of ladder networks to give Butterworth
value of either Ci or Li. Table 2 presents the values of Ai for or Chebyshev response in the pass band (review), IRE Trans. Cir-
n ⫽ 1 to 7 and for Rs ⫽ RL ⫽ 1 ⍀. cuit Theory, CT-1 (Dec.): 37, 1954.
There exists a simple equation that directly provides the 7. L. Weinberg and P. Slepian, Takahasi’s results on Tchebycheff
component values, but its deduction is rather complicated. and Butterworth ladder networks, IRE Trans. Circuit Theory, CT-
For Rs ⫽ RL ⫽ 1 ⍀, 7 (June): 88–101, 1960.
8. M. E. Van Valkenburg, Introduction to Modern Network Synthesis.
Ai = 2 sin(2i − 1)π/2n (11) New York: Wiley, 1960.
9. G. C. Temes and J. W. LaPatra, Circuit Synthesis and Design,
For a more complete discussion on the synthesis of Butter- New York: McGraw-Hill, 1977.
worth ladder network design, even with arbitrary resistors 10. DeV. S. Humpherys, The Analysis, Design, and Synthesis of Elec-
Rs and RL, as well as the historical facts surrounding the dis- trical Filters, Englewood Cliffs, NJ: Prentice-Hall, 1970.
covery of those formulas, the reader is referred to Refs. 5 to 7. 11. L. Weinberg, Network Analysis and Synthesis, New York:
McGraw-Hill, 1962.
12. A. S. Sedra and P. O. Brackett, Filter Theory and Design: Active
DESIGNING BUTTERWORTH FILTERS and Passive, Matrix, 1978.

Only few steps are necessary to design a Butterworth filter: LUIZ P. CALÔBA
MARCELLO L. R. dE CAMPOS
1. Obtain the normalized low-pass filter and its restric- Universidade Federal do Rio de
tions Ap, As, and 웆s. Janeiro
2. Determine ⑀ and n using Eqs. (7) and (8).
3. Synthesize, use tables, or use Eq. (11) to obtain the
standard filter of order n. BUYING COMPUTERS. See COMPUTER SELECTION.
CASCADE NETWORKS
Cascade design refers to the procedure in which the de-
signer chooses to factor a complex circuit requirement of
order n ≥ 2 that is difficult or impossible to realize in its
given form into a number of simpler specifications that re-
sult in more practical circuits and are more readily imple-
mented. These are then connected in a chain, that is, in a
cascade circuit, to realize the specified requirements. Typ-
ically, one factors a required high-order transfer function
with n ≥ m and n > 1, into a number of lower-order func-
tions Tj (s). H(s) in Eq. (1) is a ratio of two polynomials N(s)
and D(s) of degrees 2m and 2n, respectively. We selected,
without loss of generality, the coefficient a2n = 1, because
numerator and denominator can always be divided by a2n .
The realization then connects the functions Tj (s) such that
that is, the total transfer function is obtained from the
product of lower-order functions. Examples of cascade syn-
thesis extend from the early days of electronics when
RLC circuits were isolated by vacuum-tube amplifiers
to the present-day discrete or fully integrated realiza-
tions of active filters (RC circuits augmented or isolated
by operational amplifiers) and switched-capacitor circuits
where resistors in active filters are replaced by periodically
switched capacitors. Cascade design is used widely not only
for the implementation of magnitude and phase responses
but also for group-delay equalizers. The goal is to realize
H(s) via simpler circuits in an efficient way with low sensi-
tivities to component tolerances. The sensitivity issue will
be addressed below.
In Eq. (1), we have labeled the degrees of the numera-
tor and denominator polynomials N(s) and D(s) as 2m and
2n, respectively, to emphasize the fact that we assume the
degrees to be even. Both N(s) and D(s) can therefore be
factored into the product of second-order pole-zero pairs,
as expressed in the following form:
The notation assumes that both N and D are of degree 2n;
if m < n, the numerator will contain 2(n − m) factors of
unity. If the degree of H(s) is odd, the function can always
be factored into the product of even terms as shown in Eq.
(3) and a first-order factor. First-order sections can easily
be realized by a passive RC network and can be appended
J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright © 2007 John Wiley & Sons, Inc.
to the higher-order circuit as an additional term.
Example 1. We now illustrate the decomposition of a
higher-order transfer function into a product of lower-order
transfer functions. The transfer function of a sixth-order
filter, with a normalized frequency parameter, is
To realize this filter as a cascade circuit, the numerator
and denominator are factored by a suitable root-finding
algorithm as follows:
In this case, n = 3 and the numerator is odd, that is, N(s)
is factored into a product of two second-order factors and
a first-order factor, and the function is presented as the
product of three terms according to Eq. (2).
Example 2. This example illustrates how cascading of
lower-order sections enables the realization of an ampli-
fier with a large inverting gain, K = −1,000,000. The band-
width must be at least 5 kHz and the smallest resistor used
should be 1 k
to minimize currents and loading effects.
If one attempts to realize the amplifier in the usual way
with a 741-type operational amplifier as shown in Fig. 1(a),
a 1000 M
= 1 G
= 109
resistor is required. This re-
sistor is too large to be realized; it is essentially an open
circuit and leaves the operational amplifier operating in
an open loop. The bandwidth would be less than 1 Hz.
Because of such processing or technology constraints, it
is convenient, even necessary, to partition the prescribed
gain into several factors, such as K = K1 K2 K3 = (−100) ×
(−100) × (−100), and connect the resulting circuits in cas-
cade [Fig. 1(b)]. In this configuration, the second amplifier
picks up the output of the first one with gain −100 and
multiplies it by a second factor −100, and so on, to realize
K = −1,000,000 as required. Of course, with this large am-
plification of the factor 106 , the designer must pay careful
attention to avoid signal-level distortion. This issue will not
be addressed here. At the expense of additional circuitry,
cascade design enabled us to realize the specifications with
the required gain, bandwidth (it is larger than 8 kHz), and
practical component values. Without the cascade method,
the specifications placed such demands on the components
to render the circuit unrealizable.
In a similar manner, high-order active filters described
by a transfer function, H(s), are most frequently designed
as a cascade of low-order circuits. The method results in
filters that can be adjusted (or tuned) easily and have low
sensitivity to component tolerances Ref. 1. In addition, the
design method is completely general, in that transfer func-
2 Cascade Networks

Figure 1. (a) Proposed operational amplifier circuit to realize K = −R2 /R1 = −1,000,000. The
circuit is not practical because of the large resistor R2 and because the minimal feedback limits the
bandwidth to very low values; (b) practical realization as a cascade of three amplifiers with gain
Ki = −100.

tions of arbitrary form can be realized. Naturally, to keep

where we assumed that the component x is located in sec-
the circuits stable, that is, to prevent them from oscillating,
tion j, and partial derivatives are used because H is a func-
the poles, the roots of D(s), are restricted to the left half of
tion of s and of all circuit components. Customarily, both
the complex s plane (α0j > 0, α1j > 0). The transmission
the transfer function deviation ∂H and the component de-
zeros, the roots of N(s), however, can be anywhere in the s
viation ∂x are normalized to H and x, respectively, so that
plane; their location depends only on the desired response.
we obtain from Eq. (8) with Eq. (2)
An additional advantage is that in cascade design the de-
signer can focus on the low-order sections Tj (s) that are
generally simpler to implement than the high-order func-
tion H(s). The low-order sections are then simply connected
in a chain, or cascaded, as shown in Fig. 2. If Tj (s) is defined These quantities are the classical sensitivities, defined as
as a voltage transfer function,
Vo j
T j (s) = (5)
Vi j
Equation (6) can be rewritten in the form
the total transfer behavior realized by that circuit is de-
rived to be
Vout Vo1 Vo2 Vo3 Vo(n−1) Vout
H(s) = = ...
Vin Vin Vo1 Vo2 Vo(n−2) Vo(n−1) (6)
= T1 (s)T2 (s) . . . Tn−1 (s)Tn (s) which means that the percentage error in a function F(x)
caused by a component with tolerance ∂x is computed by
as required by Eq. (2). Equation (7) holds because the con-
multiplying the percentage error of the component by the
nection guarantees that the input voltage of section j is
sensitivity. From Eq. (9) we have the important result
equal to the output voltage of section j − 1, Vij = Vo(j −1) .

SENSITIVITY
The sensitivity of a cascade realization of a transfer func-
tion H(s, x) to a component x is calculated via derivatives,
which says that in a cascade circuit the sensitivity of the
total transfer function H to a component is equal to the
sensitivity of the section Tj that contains the component.
In contrast to noncascaded implementations, in which the
sensitivity to a component may depend on all poles and
zeros and may become very large Ref. 1, here it depends
only on the pole and zero in section j and is not affected by
 Cascade Networks 3

Figure 2. Cascade realization of a 2nth-order transfer function. The realized transfer function is
the product of the individual function realized by the blocks T1 .

any of the other sections. Equation (12) verifies formally
the intuitive expectation that the cascade circuit with good
sensitivity behavior should be built from low-sensitivity
sections.
CASCADING CONDITION
contend with more than a resistor ratio that would multi-
ply T1T2 simply by a frequency-independent constant.
To illustrate this point consider the example of a second-
order low-pass filter being built by cascading two identical
first-order sections as in Fig. 4. The sections have the trans-
fer function,

A general condition that must be satisfied for Eq. (7) to

hold in the simple form shown is that the sections do not
load each other and do not otherwise interact. This condi- The intent is to multiply the transfer functions T1 and T2
tion requires that the output impedance Zout of any section so that
ideally is zero and its input impedance Zin infinite. Figure Vo2 1 1
H(s) = = T1 (s)T2 (s) =
3 illustrates this requirement for two sections T1 and T2 , V1 sCR + 1 sCR + 1 (16)
defined as 1
=
Vn1 Vn2 (sCR)2 + 2sCR + 1
T1 (s) = and T2 (s) =
V1 Vi2 However, because of the finite impedances identified in the
figure,
Vn1 and Vn2 are the voltages at the respective internal
nodes n1 and n2 in Fig. 3. The complete sections, realisti- 1 1
Zi2 = R + and Zo1 =
cally modeled to include a finite input impedance Zi (s) and sC sC + 1/R
output impedance Zo (s), are contained in the dashed boxes.
by Eq. (15) the proposed circuit in Fig. 4 realizes the trans-
Assuming that V1 is an ideal voltage source so that Zi1 has
fer function
no effect and that there is an open circuit at Vo2 so that no
current flows through Zo2 , analysis of the configuration in 1
Vo2 1 R+
Fig. 3, starting from the output, yields H(s) = =( )2 sC
V1 sCR + 1 1 R
Zi2 (s) (R + )+( ) (17)
Vo2 = T2 (s)Vi2 = T2 (s) Vn1 sC sCR + 1
Zi2 (s) + Zo1 (s) (12) 1 (sCR + 1) 2
1
Zi2 (s) = =
= T2 (s) T1 (s)V1 (sCR + 1)2 (sCR)2 + 3sCR + 1 (sCR)2 + 3sCR + 2
Zi2 (s) + Zo1 (s)
The desired performance is completely altered as can be
Thus, the transfer function of the two-section cascade is
confirmed by direct analysis. It is seen that the finite
Vo2 Zi2 (s) frequency-dependent input and output impedances sub-
H(s) = = T1 (s)T2 (s) (13) stantially change the desired transfer function. If cascad-
V1 Zi2 (s) + Zo1 (s)
ing must be used but Eq. (16) is not satisfied, buffering us-
rather than the simple product T1T2 intended. The problem ing a voltage follower can be employed as in Fig. 5 so that
is that the current through Zo1 is not zero, that is, section no current is drawn from the first section and the second
1 is loaded by section 2. Equation (15) indicates that the section is driven by a nearly ideal voltage source.
desired result is achieved provided that To repeat the important condition that must be satisfied
|Zi2 ( jω)|  |Zo1 ( jω)| (14) if two circuits are to be connected in cascade: the trailing
section must not load the leading section. The circuits to be
Ideally, Zi2 = ∞ and Zo1 = 0. Condition (14) is satisfied in cascaded can be of low order, high order, active, passive, or
the circuit in Fig. 1(b) because the operational amplifier any desired combination; the loading restriction does not
circuits with feedback and a gain of 100 have very small change. For designing high-order active filters, the cascade
output resistance (Rout < 50
) compared to the input re- connection normally consists of first- and second-order ac-
sistance of the following stage (Rin = 1 k
). The condition tive building blocks because they can be cascaded directly
to permit cascading is, therefore, that the input impedance with no need of buffering: since active circuits usually have
of the loading section must be much larger than the output an operational amplifier output as their output terminal,
impedance of the driving section so that the voltage divider unbuffered cascading is possible because the operational
factor that multiplies the ideal product T1T2 in Eq. (15) is amplifier output resistance in a feedback network is very
as close to unity as possible. The voltage divider ratio is small (see Example 2). On the other hand, as in the ex-
written on purpose in terms of impedances as functions of ample of Fig. 4, it can be expected intuitively that passive
s or jω to emphasize that, in practice, the designer needs to circuits can generally not be connected in cascade without
4 Cascade Networks

Figure 3. Two-section cascade with finite input and output impedances. The second section loads
the first one unless its input impedance, Zi2 , is much larger than the output impedance, Zo1 , of the
first section.

Figure 4. Cascade connection of two first-order passive low-

pass sections with finite input and output impedances. The two
modules interact so that the realized transfer function is not
equal to the product of the two first-order functions. Isolating
the sections is required as shown in Fig. 5.

Figure 5. Two low-pass modules isolated by an operational amplifier. The unity-gain voltage fol-
lower isolates the sections’ performance so that the total transfer function is the product of the two
first-order modules.

buffering because the condition in Eq. (16) will rarely be widely in industry because it is applicable generally, is well
satisfied. understood, very easy to implement, and efficient in its use
of active devices (as few as one operational amplifier per
pole pair). It uses a modular approach and results in fil-
ters that for the most part show satisfactory performance
THE DESIGN APPROACH AND TRADE-OFFS
in practice. One of the main advantages of cascade filters
is that they are very easy to tune because each biquadratic
The problem to be addressed is how the transfer function
section, referred to as biquad in the literature, is responsi-
of Eq. (1) can be realized in an efficient way with simple
ble for the realization of only one pole pair and zero pair:
low-order circuits and low sensitivities to component toler-
the realizations of the individual critical frequencies of the
ances. As was mentioned, the sensitivity behavior of high-
filter are decoupled from each other. The disadvantage of
order filter realizations shows Ref. 1 that, in general, it is
this decoupling is that for filters of high order, say larger
not advisable to realize the transfer function H(s) of Eq. (1)
than order eight (n > 4), with stringent requirements and
in the so-called direct form, using only one or maybe two
tight tolerances, cascade designs are often found to be still
operational amplifiers embedded in a high-order passive
too sensitive to component variations in the passband. In
RC network. Although it is possible in principle to realize
these cases, ladder simulations may lead to more reliable
Eq. (1) in direct form, the resulting circuits are normally
circuits Ref. 1.
so sensitive to component tolerances that reliable perfor-
As shown in Eq. (3), the high-order transfer function
mance cannot be expected in practice. A further disadvan-
H(s) is factored into a product of second-order blocks,
tage of the direct synthesis method is the use of a very
large number of passive components to realize a function
of given order.
In the cascade approach, the high-order function H(s)
is factored into functions of second order as indicated in
Eq. (3). The resulting biquadratic functions are realized by where the denominator is expressed in terms of the usual
the methods discussed elsewhere in this encyclopedia and filter parameters, the quality factor Q and the pole fre-
connected in cascade such that their product implements quency ω0 . We have also introduced a suitably defined gain
the prescribed function H(s). The cascade method is used constant, kj , for example such that the leading coefficient in

the numerator of the gain-scaled transfer function tj (s) is
unity or such that |tj (jω0j )| = 1. The sections Tj (s) are quite
arbitrary; for example, they can realize a low-pass function
(β2j = β1j = 0), a bandpass function (β2j = β0j = 0), a high-
pass function (β1j = β0j = 0), or a pair of finite transmission
zeros on the jω axis (β1j = 0), as the process does not change.
Because second-order filter sections can be built to realize
arbitrary functions of the form of Eq. (21), cascade design
is very general in permitting the realization of any type of
stable transmission requirement. If we then may assume
that the output impedances of the biquadratic functions
are sufficiently small (compared to the input impedances),
all second-order blocks can be connected in cascade, Fig.
2, without causing mutual interactions due to loading, and
the product of the biquadratic functions is realized as re-
quired by Eq. (7).
Although this simple process leads in a straightforward
way to a possible cascade design, it leaves several questions
unanswered:
1. Which zero should be assigned to which pole in Eq.
(3) when the biquadratic functions Tj (s) are formed?
Since we have n pole pairs and n zero pairs (counting
zeros at 0 and at ∞) we can select from n factorial, n!
= 1 × 2 × 3 × · · · × n, possible pole–zero pairings.
2. In which order should the biquadratic sections in Eq.
(7) be cascaded? Does the cascading sequence make
a difference? For n biquadratic sections, we have n!
possible sequences.
3. How should the gain constants kj in Eq. (21) be cho-
sen to determine the signal level for each biquad? In
other words, what is the optimum gain distribution?
Because the total transfer function is the product of the
biquadratic sections, the selections in steps 1–3 are quite
arbitrary as far as H(s) is concerned. However, they do de-
termine significantly the dynamic range, that is, the dis-
tance between the maximum possible undistorted signal
and the noise floor: the maximum and minimum signal lev-
els throughout the cascade filter can be shown to depend on
the choices in steps 1–3. Although the sensitivities to com-
ponent tolerances are functions of pole–zero pairing, the
effect usually is not very strong. For a detailed treatment
see Refs. 2 and 3. Also, the selection of pole–zero pairing
for best sensitivity can be shown to conflict often with the
choice necessary for best dynamic range. Since the imple-
mentation of the blocks Tj (s) normally makes use of active
devices, such as operational amplifiers, depending on the
operating frequency, the maximum undistorted signal volt-
age that a filter can process is limited either by the power
supply or by the slew rate of the operational amplifiers.
The optimal cascading routine to be discussed
(pole–zero pairing, section ordering) and gain assignment,
is entirely general and does not depend on the transfer
function or its type. It is independent of the actual im-
plementation of the second-order building blocks. The de-
signer may choose any convenient technology and the cir-
cuit architecture that seems preferable from the point of
view of sensitivity, numbers and kinds of elements, values
and element value spreads, power consumption, or other
Cascade Networks 5
practical considerations.
DYNAMIC RANGE
Since it is the dominant effect of pole–zero pairing, section
ordering, and gain assignment, we will be concerned here
only with dynamic range issues. To help tackle the problem,
let us label the maximum signal level that can be handled
with no distortion as Vo,max . We assume that it is measured
at the output of the biquadratic sections. This assumption
will always be correct in single-amplifier biquadratic sec-
tions for which section output and operational amplifier
output are the same. In multiamplifier biquadratic sec-
tions, each operational amplifier output must be evaluated
and the maximum operational amplifier output voltage in
the biquadratic section must be determined. To avoid over-
driving any operational amplifier sooner than any other
one inside a biquadratic section, it is intuitively reason-
able that any available design freedom in the biquadratic
sections should be chosen such that all operational ampli-
fiers “see” the same signal level. If this is not possible, that
is, if the undistorted output voltage Voi of section i is only
a fraction 1/qi of the maximum internal voltage, with qi >
1, Voi in the following equations must be replaced by qiVoi .
For simplicity, we shall assume in our discussion that the
sections can be designed such that qi = 1.
We must ensure then that the signal level at any section
output, |Voi (jω)|, satisfies
max|Voi ( jω)| < Vo,max , 0 ≤ ω ≤ ∞, i = 1, . . . n (19)
Note that this condition must indeed be satisfied for all
frequencies and not only in the passband because large
signals even outside the passband must not be allowed
to overload and saturate the operational amplifiers: when
operational amplifiers are overdriven, their operation be-
comes nonlinear. The circuit, however, may still act as a
filter and remove the higher harmonics that are generated
by the nonlinear operational amplifier operation. The prob-
lem that arises when saturating the operational amplifiers
is, therefore, not so much harmonic distortion of the signal
but changed operating points, intermodulation distortion,
and deviations of the magnitude response Ref. 1.
The lower limit of the useful signal range is set by the
noise floor. If in the passband of a cascade filter the signal at
an internal stage becomes very small, it must be amplified
again to the prescribed output level. From any point in the
cascade of filter stages, say at the output of stage i, signal
and noise are amplified by the same amount, namely,
Consequently, the signal-to-noise ratio will suffer if in the
cascade filter the signal suffers in-band attenuation, that
is, if it is permitted to become very small. The function
H+ i (s), defined in Eq. (23), is referred to as the noise gain
from the output of section i to the filter output. Thus, the
second condition to be satisfied by the output voltage of any
biquadratic section is
min|Voi ( jω)| → max for ωL ≤ ω ≤ ωU , i = 1, . . . n (21)
6 Cascade Networks

ωL and ωU are the lower and upper, respectively, corners of two second-order bandpass sections instead of a high-pass
the passband. In this case we are, of course, only concerned and a low-pass section.
with signal frequencies in the passband, because in the
stopband the signal-to-noise ratio is of no interest. Note, Example 3. Determine the optimal pole-zero pairing for
however, that for a white noise input the output noise spec- the transfer function of Eq. (5) of Example 1. The transfer
trum of a filter section has the same shape as the square function was
of the transfer function magnitude, which means that the
highest noise response occurs at the pole frequencies with
the highest Q values. Since these are mostly found just be-
yond the specified corners of the passband they would not
The zeros are located at z1 = 0 and z2 = ∞, z3,4 = ±j0.5, and at
be included in the measurement defined in Eq. (24). There-
z5,6 = ±j1.5, and the poles are at p1.2 = −0.045 ± j0.9099, p3,4
fore, to avoid decreased dynamic range caused by possibly
= −0.1 ± j1.0, and p5,6 = −0.05 ± j1.085. According to the
large noise peaks at the passband corners, it is advisable to
approximate assignment rule just stated, we should pair
extend the frequency range beyond the specified passband
(z1,2 , p3,4 ), (z3,4 , p1.2 ), and (z5,6 , p5,6 ). This choice is indicated
corners, ωL and ωU , into the transition band to cover the
in Eq. (28):
pole frequencies with the highest Q values.
The steps of pole–zero pairing, section ordering, and
gain assignment will now be chosen such that the condi-
tions in Eqs. (22) and (24) are satisfied. It must be empha-
sized that these steps do not just amount to minor adjust-
ments when designing a cascade filter, but that the cascade
circuit will likely not perform to specifications in practice
unless these steps are taken at the design stage. Section Ordering

Pole-Zero Pairing After the pole-zero assignment has been solved, the optimal
ordering sequence must be determined out of the n! possi-
According to Eqs. (22) and (24), the pole–zero pairing bilities in which the biquadratic sections can be connected
should be chosen such that, in a given section, Mi = to form the cascade network. For example, for the sixth-
max|Voi (jω)| is minimized at all frequencies, and mi = order network with three sections in Example 3, there ex-
min|Voi (jω)| is maximized in the passband. In other words, ist six possible ways to cascade the biquadratic functions:
using Eq. (21), |ti (jω)| should be as flat as possible in the
frequency range of interest. Notice that Mi may lie outside
and mi at the edge of the passband, and that the actual
minimum of the magnitude |ti (jω)| lies in the stopband and
The best sequence is the one that finds the ordering that
is of no concern. As the values of Mi and mi change when the
maximizes the dynamic range. The procedure is completely
relative positions of the poles and the zeros of ti (s) are al-
analogous to the earlier discussion where pole–zero pairs
tered, the pole–zero assignment must be chosen such that
were chosen to keep the transfer functions of the individual
the ratio Mi /mi is as close to unity as possible, which means
sections as flat as possible. Now the cascade connection is
that for each biquadratic function the “measure of flatness”
designed such that the transfer functions

should be minimized. The optimal pole–zero assignment from filter input to the output of the ith intermediate bi-
for the total 2nth-order cascade filter is then the one that quadratic section are as flat as possible. Hn is, of course,
minimizes the maximum value of di : equal to the total transfer function H. This will help en-
sure that the maximum signal voltages do not overdrive
the operational amplifiers and that, over the passband,
Algorithms that accomplish this task are available in the the smallest signal stays well above the noise floor. Con-
literature Refs. 4 to 7. Even in fairly simple low-order cases sequently, the relationships in Eqs. (22) and (24) must be
the problem of pole–zero assignment can be quite compu- satisfied,
tation intensive; it requires substantial software and com-
puter resources. min|Voi ( jω)| < Vo,max 0≤ω≤∞ (26)
If the appropriate computing facilities are not available, min|Voi ( jω)| → max for ω L ≤ ω ≤ ωU (27)
a simple solution that provides good suboptimal results is
simply to assign each zero or zero-pair to the closest pole where Voi (s) is now the output voltage of the cascade of the
Refs. 4–8. On occasion, depending on system requirements, first i sections when driven by an input signal Vin (s). With
we may also preassign some pole–zero pair(s) and leave Hi (s) given in Eq. (30), we define the two measures
them out of the remaining pairing process. For instance, if max|Voi ( jω)| Voi ( jω)
the numerator contains a term s2, we may prefer to factor it Mi = = max| |
|Vin ( jω)| Vin ( jω) (28)
into s × s instead of s2 × 1, that is, we may prefer to realize = max|Hi ( jω)| for 0 ≤ ω ≤ ∞

and
min|Voi ( jω)| Voi ( jω)
mi = = min| |
|Vin ( jω)| Vin ( jω) (29)
= min|Hi ( jω)| for ωL ≤ ω ≤ ωU
and require again that the flatness criterion of Eq. (25)
be minimized, now, however, by choice of the cascading se-
quence,
The optimal sequence is the one that minimizes the max-
imum number di as prescribed in Eq. (26). Note that we
do not have to consider dn because, with all sections con-
nected in the cascade filter, dn is nothing but a measure
of the prescribed passband variations (the ripple). With
the problem identified, the optimum cascading sequence
can be found in principle by calculating di for all n! se-
quences and selecting the one that satisfies Eq. (35). As in
the pole–zero assignment problem, a brute-force optimiza-
tion approach involves a considerable amount of computa-
tion, and more efficient methods have been developed that
use linear programming techniques, such as the “branch
and bound” method of Refs. 5–7, or “back track program-
ming” Ref. 9. The necessary computer algorithms are de-
scribed in the literature.
If the required software routines are not available, the
designer must pick a cascading sequence that is based on
experience or intuition. A selection that is often very close
to the optimum is the one that chooses the section sequence
in the order of increasing values of Qi , that is,
so that the section with the flattest transfer function mag-
nitude (the lowest Q) comes first, the next flattest one sec-
ond, and so on. The possible choices are frequently further
limited by other considerations. For example, it is often de-
sirable to have as the first section in the cascade a low-pass
or a bandpass section so that high-frequency signal compo-
nents are kept from the amplifiers in the filter in order to
minimize slew-rate problems. Similarly, the designer may
wish to employ a high-pass or a bandpass section as the last
section in order to eliminate low-frequency noise, dc offset,
or power-supply ripple from the filter output. In such sit-
uations, the optimum sequencing is performed only on the
remaining sections.
The following example illustrates some of the steps dis-
cussed.
Example 4. Continue Example 3 to find the optimal cas-
cading sequence for the three second-order sections. Since
the coefficient of s in the denominators of the second-order
sections of Eq. (28) equals ω0i /Qi , and the constant coeffi-
cient equals ω2 0i , we have
Cascade Networks 7
Using Eq. (31) and using the section numbering in Eq. (28),
the optimal ordering is, therefore, T2T1T3 . If instead the de-
sign were to emphasize the elimination of high-frequency
signals from the filter and low-frequency noise from the
output, the ordering T2T3T1 ,
would be preferred because the bandpass section, T2 , has
the best high-frequency attenuation, and section T1 pro-
vides reasonable attenuation at low frequencies (0.25/0.83
= 0.3 ≈ −10.4 dB), whereas section T3 has a high-frequency
gain of 1 and amplifies low-frequency noise by more than
2.25/1.18 = 1.91 ≈ 5.6 dB. This suboptimal ordering gives
almost identical results to the optimal one, T2T1T3 , because
Q 1 ≈ Q3 .
Gain Assignment
The last step in the realization of a cascade filter is the
assignment of the gain constants. Generally, the selection
is again based on dynamic range concerns with the goal of
keeping the signals below amplifier saturation limits and
above the system noise floor. To get a handle on the pro-
cess, we note that the circuit is linear and all voltages rise
in proportion to Vin . It is clear then that the maximum
undistorted input signal can be processed if we choose the
gain constants such that all internal output voltages Voi , i
= 1, . . . , n − 1, are equal in magnitude to the presumably
prescribed magnitude of the output voltage, Von :
max|Voi ( jω)| = max|Von ( jω)| = max|Vout ( jω)|,
i = 1 = 1, . . . n − 1
Assuming as before that the output voltage of the bi-
quadratic sections reaches the critical magnitude, this
choice ensures that for a given signal level none of the op-
erational amplifiers in the blocks of Fig. 2 is overdriven
sooner than any other one. Note, however, the earlier com-
ments about precautions necessary in multiamplifier bi-
quads.
For the analysis it is convenient to use the notation of
Eqs. (2), (21), and (30), that is,
and, for the intermediate transfer functions,
Furthermore, we introduce the constant
such that
8 Cascade Networks
is the prescribed gain. Similar to the definition of Mn , let us
denote the maxima of the intermediate n − 1 gain-scaled
transfer functions by Mi , that is,
To make max|Vo1 (jω)| = max|Vout (jω)|, we then obtain the
equation k1 M1 = KMn , that is,
Similarly, k1 k2 M2 = KMn , that is, with Eq. (45),
results in max|Vo2 (jω)| = max|Vout (jω)|. Proceeding in the
same manner yields
Choosing the gain constants as in Eqs. 45, 46, 47 guaran-
tees that all operational amplifiers “see” the same maxi-
mum voltage to ensure that the largest possible signal can
be processed without distortion. Note that changing the to-
tal gain of the n-section cascade filter affects only K, that
is, k1 . The voltages in all other sections Ti (s), i = 2, . . . , n,
increase or decrease proportionally, but their relative mag-
nitudes stay the same, as determined by ki in Eq. (47).
Example 5. Continue Example 4 to find the optimal gain
constants for the three second-order sections so that their
maximum output levels are equalized. The specified mid-
band filter gain is 10 dB. Use the section ordering in Eq.
(38).
From Eq. (43), we find
corresponding to the prescribed gain of 10 dB. The maxima
Mi can be computed as
by evaluating the functions in Eqs. (43) and (44). With Mi
known, and using Eq. (48), Eqs. (45) and (47) give
that is
These values result in all section outputs being equal to
KM3 = 3.16 times the input voltage level for a uniform gain
of 10 dB. If the designer were to find out later that system
performance would improve for a different filter gain, say,
29 dB rather than 10 dB, it is necessary only to alter the
first section in the cascade from k1 = 3.16 to
to achieve the new circuit for which dynamic range is still
optimized.
To demonstrate that gain equalization is very important
in cascade realizations, consider the case where equaliza-
tion is not performed. Had the designer chosen all ki = 1
as in Eq. (38), the output levels would have been 13.9 dB
at Vo1 , 31.9 dB at Vo2 , and 41.3 dB at Vo3 . Quite apart from
the specified gain of 10 dB not being realized, the differ-
ence of a factor of 41.3 dB − 13.9 dB = 27.4 dB = 23.4 in
operational amplifier output voltages would likely result
in gross distortions unless the input voltage is kept very
small.
BIBLIOGRAPHY
1. R. Schaumann M. S. Ghausi K. R. Laker Design of Analog Fil-
ters: Passive, Active RC and Switched Capacitor, Englewood
Cliffs, NJ: Prentice Hall, 1990.
2. R. Schaumann and M. A. Van Valkenburg, Design of Active Fil-
ters, New York, NY, Oxford University Press, 2001.
3. M. S. Ghausi K. R. Laker Modern Filter Design, Englewood
Cliffs, NJ: Prentice Hall, 1981.
4. G. S. Moschytz Linear Integrated Networks—Design, New York:
van Nostrand Reinhold, 1975.
5. S. Halfin An optimization method for cascaded filters, Bell Syst.
Tech. J., 49: 185–190, 1970.
6. S. Halfin Simultaneous determination of ordering and ampli-
fications of cascaded subsystems, J. Optimiz. Theory Appl., 6:
356–360, 1970.
7. E. Lüder Optimization of the dynamic range and the noise dis-
tance of RC-active filters by dynamic programming, Int. J. Cir-
cuit Theory Appl., 3: 365–170, 1975.
8. A. S. Sedra P. O. Brackett Filter Theory and Design: Active and
Passive, Portland, OR: Matrix, 1978.
9. W. M. Snelgrove A. S. Sedra Optimization of dynamic range in
cascade active filters. In Proc. IEEE Int. Symp. Circuit Syst.,
1978, pp. 151–155.
ROLF SCHAUMANN
Portland State University,
Portland, OR
J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering
Copyright
c 1999 John Wiley & Sons, Inc.

CELLULAR ARRAYS

History

This section gives a brief overview on cellular array architectures and related computing principles. Cellular
arrays are massively parallel computing structures composed of cells placed on a regular grid. These cells
interact locally, and the array can have both local and global dynamics. Indeed, it can be shown that in
approximating any partial differential equation (PDE), continuous in space and time, one can use a cellular
array as a computing environment, either in software simulation or in analog or digital hardware emulation.
Two cellular array structures will be discussed, in detail: (i) cellular automata (CA)—discrete in space, time,
and value, and (ii) cellular nonlinear or neural networks (CNN)—discrete in space and continuous in time
and value. It will be shown that there is a biological relevance and motivation behind promoting cellular
architectures as good prototypes for parallel computing. It is discussed how a stored-program analog array
computer can be built, the CNN Universal Machine (CNN-UM), which makes it possible to synthesize novel
spatiotemporal algorithms. Various physical implementations will be discussed, with emphasis on integrated
array sensing and reconfigurable computing, that is, visual microprocessor architectures embedding stored
programmability. Some application potentials will also be highlighted in engineering, biology, chemistry, and
physics.
Historically, research on cellular arrays was initiated by von Neumann (1) in the 1960s, who studied the
homogeneous structure of cellular automata and its evolution as a general framework for modeling complex
structures. Such a structure consists of a set of cells, each one capable of performing only a set of primitive
operations. Depending on the interconnection pattern among the cells and the initial content, the structure
evolves through a sequence of states. With the introduction of CA, von Neumann’s primary interest was to
derive a computationally universal cellular space with self-reproducing and self-repair configurations. After
a thorough study, he framed a “universal” CA with a set of transition rules involving five-neighborhood cells
(a cross-shaped neighborhood of a cell), each having 29 distinct states. The transition function with this
relatively small set of states turned out to be sufficient to achieve a powerful set of elementary operations: local
logical operations, wire-branching, transmission, relative delays, construction, and destruction. Based on these
operations he successfully synthesized various organs (pulser, decoder, coded channel, etc.) and higher-level
functions (e.g., sensing); furthermore, he proposed a universal computer. Following this pioneering work, several
researchers attempted to improve the construction of von Neumann’s cellular space (23–4), and others started
analyzing CA with the tools of abstract algebra, topology, and measure theory (56–7) with the ambitious goal
of developing a unified theory of cellular models (89–10). In this first phase of CA research already a number of
applications were proposed, including parallel language recognition, image processing, and biological modeling.
The new phase of activities in CA research is due to Wolfram (11, 12) in the early 1980s, who pioneered the
investigation of CA as mathematical models for self-organizing statistical systems. He focused on a simplified
structure: a discrete lattice of cells in which each cell has only two possible values (binary cells). The next state of
a cell depends on itself and its two neighbors (three-neighborhood dependency). The cells evolve in discrete time
1
2 CELLULAR ARRAYS

steps according to some deterministic rule depending only on local neighbors. Thus, he defined a network that
can be built based on a simple storage elements and combinatorial logic. Using polynomial and matrix algebraic
tools, he moved toward in characterizing the state-transition behavior and the global properties of CA. Based on
the statistical properties Wolfram classified the three-neighborhood CA broadly into four major categories (12).
Packard and Wolfram (13) also defined the framework of the two-dimensional CA and characterized its basic
properties. At the same time, others started to characterize CA models in various unrelated fields. Among other
CA-based models for physical systems [e.g., simple crystal growth (14)], probabilistic analysis of CA behavior
[e.g., the Game of Life algorithm (15)] and the architectural research of CA machines [e.g., CAMs (16)] should
be mentioned. With the advent of very large scale integrated (VLSI) technology, a number of specific-purpose
chips were built mainly for test-pattern generation and various cryptographic applications.
Parallel to this second phase of CA investigations another research field (17) also drew the attention
of the scientific community. After almost two decades of relative silence, Hopfield’s results (18, 19) on global
optimization problems and biological modeling renewed the activity in the neural network (NN) and artificial
intelligence (AI) research. In the next few years various models and architectures were proposed for a broad
class of classification, optimization, and approximation problems (e.g., Refs 2021–22). However, because all
these structures were densely or fully connected, their implementation posed a major challenge for VLSI
designers and the wiring problems could not be adequately solved.
In the late 1980s a new cellular array architecture and computing principle was proposed by Chua and
Yang (23), called cellular neural/nonlinear networks (CNN), standing at the crossroads of CA and NN research.
CNN inherited the analog (autonomous-nonautonomous) network dynamics from NN and the cellular (locally
connected) structure from CA, and soon it proved to be a powerful paradigm fertilizing research activity in
a number of disciplines. It turned out to be a well-constructed framework for biological modeling especially
modeling vision (242526272829–30), simulating or emulating partial differential equations (PDEs) (313233–
34), and in various engineering designs (3536373839404142434445464748495051525354–55).
CNNs are regular, single-layer or multilayer, parallel processing structures with analog nonlinear comput-
ing units (base cells). The state value of the individual processors is continuous in time and their connectivity
is local in space. The program of these networks is completely determined by the pattern of the local inter-
actions, the so-called template. The time evolution of the analog transient, “driven” by the template operator
and the processor dynamics, represents the computation in CNN (results can be defined both in equilibrium or
nonequilibrium states of the network). The standard CNN equation (23) contains only first-order cells placed
on a regular grid and the interconnection pattern is linear. This was soon generalized to higher-order cells,
nonuniform grids, and nonlinear and/or delay-type templates (56, 57).
Completing the base cells of the CNN with local sensors, local data memories, arithmetical and logical
units, furthermore, with global program memories and control units results in the CNN Universal Machine
(CNN-UM) architecture [Roska and Chua (58)]. The CNN-UM is an analogic (analog and logic) supercomputer;
it is universal both in the Turing sense (59) and also as a nonlinear operator (25). Therefore, when designing
CNN processors, it can be used as a general architectural framework. Currently, there exist different physical
implementations of this architecture: mixed-signal VLSI (6061626364656667–68), emulated digital VLSI (69),
and optical implementation (70).
From hardware design point of view there is another important group of cellular arrays: smart sensors,
among them probably the most important the specific-purpose vision chips, which also appeared in the 1980s
after the pioneering work of Mead (71) and his research group. This line of investigation follows a more
bottom-up approach: cells are constructed in analog VLSI and are connected to perform a certain sensing-
computing task. Though the structures are CNN-like, there is no well-defined system level theory describing
the qualitative properties of these architectures. The emphasis is on sensing combined with a specific type of
computing for data prefiltering, reduction, and estimation of motion, of color-, and of form etc., rather than on
solving a complex task on a reprogrammable cellular architecture.
 CELLULAR ARRAYS 3

This article gives a short overview of various cellular array architectures. First the mathematical descrip-
tion of different coupled cellular structures is presented by putting the emphasis on CA or CNN frameworks
and their relation to PDE-based descriptions. Then various architectures and their biological relevance are
discussed, followed by physical implementations and some state-of-the-art engineering designs. General appli-
cation areas are also briefly described. Finally, the key concepts are summarized and future trends in cellular
array research and implementations are predicted.

Foundations and Mathematical Descriptions

In this section the mathematical description of CA- and CNN-type cellular arrays is given along with the basic
types of PDEs. It has been proven that all PDEs can be approximated to any desired accuracy by introducing
finite differences (72) (and possibly discrete variables), that is, they can always be mapped to a cellular
structure. Whereas all resulting models are locally connected, they may exhibit a very complicated global
dynamics. Cellular arrays are computationally universal (7, 15, 59) and from an engineering point of view, they
can be considered as dedicated architectures for building a universal parallel computer. The presentation of
this section aims to underline the engineering view that any “PDE machine” that can be built is likely to be a
cellular array.
PDE Machines as Cellular Arrays: an Engineering Approach. In a continuous space-time ap-
proach diffusive and wavelike transport mechanisms in physics can be well characterized by PDEs. A detailed
qualitative and quantitative analysis of these processes usually focuses on space-time evolution of these sys-
tems; however, a closed-form solution of the describing equations is available only in fairly simple cases. Then,
one may consider on constructing a universal computer programmed by PDEs and capable of calculating all the
solutions. The major obstacle in building the ideal PDE machine—continuous in both space and time—is well
explained by quantum mechanics stating that “the spectrum of the volume of any physical region is discrete”
(73). For instance, even when choosing some gas or fluid as a basic material, there is always a certain micro-
scopic scale at which these substances should be regarded as spatially discrete. On the other hand, treating
them on a macroscopic scale (thus continuous in space), another engineering problem arises: adjusting some
of the (global) physical parameters of this system would mean a very restricted way of programming. As a con-
sequence, it is very likely that this “computer” would be self-describing, capable of calculating and predicting
only those processes that it actually represents. Are there any better mathematical abstractions for parallel
computing machines in engineering design?
Discretization along all spatial coordinates maps the PDE-based system into a dynamical system described
by ordinary differential equations (ODE). Stated with other words, the PDE is approximated on a fixed grid
looking at its properties at a chosen scale. This leads to a cellular array structure in which each node represents
an analog (continuous state and time) computing device. In this case, it is easier to imagine the corresponding
universal computer composed of cells having a prescribed sphere of influence in a local neighborhood, similar
to the sensory organs and the nervous system of different species in nature. Here, reprogramming would mean
changing the cell types and/or their local interaction (in order to change the local configuration) to realize a
universal computation.
Further simplification is possible by discretizing the ODE system in time and limiting the cell states to a
finite number of states. This “fully discretized” system, described by ordinary difference-differential equations
(ODDE), is theoretically still capable of reproducing the qualitative properties of the underlying PDE while
possessing structural simplicity that makes it tailor-made for physical implementation. For instance, imagine
a structure of molecules in a chemical substance in which the spin of the electrons is described by discrete
states and the chemical reaction evolves in phases. In this cellular array structure each node represents a
digital (discrete state and time) computing device. Similarly to the analog case, reprogramming would ensure
the construction of possible local configurations and the realization of a universal computation.
4 CELLULAR ARRAYS

The above-described analog and digital cellular arrays are not only good approximations of various PDE-
based dynamical systems, but they can also be considered as universal computers (7, 15, 59). Furthermore,
it has been proven that there are cases in which for a certain cellular array structure (described by ODEs or
local rules) the limiting PDE representation with the same qualitative properties does not even exist (74). This
promotes a provocative view that PDEs are merely idealizations of (or only alternatives to) cellular structures
described by coupled ODEs or local update rules (75, 76).
Systems Described by Partial Differential Equations. In the following, some basic types of PDEs,
which describe continuous space-time systems, will be introduced. Without loss of generality the mathematical
descriptions will be specified in a two-dimensional (2-D) setting. Let us consider a planar signal flow (a spa-
tiotemporal intensity function) I(x,y,t), where (x,y) represent the spatial coordinates and t the time dependence.
Then the nonlinear reaction-diffusion equation is represented by

where g and F stand for nonlinear functions, D and L are scalars. As a special case, assuming no changes in
time (and setting F = 0), one obtains the following Laplace equation

Using the same notation, a simple wave-type equation can be described as

Other types of useful PDEs, developed particularly for 2-D signal (image) processing, can be found in 777879–
80.
Equations (1, 2, 3) and their variants are often used to describe diffusion and wave-type transport mecha-
nisms in physics. There is an important common thread in these descriptions: there are no distant interactions
in space-time; from the continuity assumption it follows that only “infinitely close” particles interact. This
makes it impossible to build a device that exactly corresponds to the above-noted PDEs; however, it provides
the chance to approximate these equations by simple locally connected cellular systems.
Systems Described by Ordinary Differential Equations: Cellular Neural or Nonlinear Network.
Cellular neural or nonlinear networks (CNN) are two- or higher-dimensional arrays defined by simple dy-
namical systems arranged at the node points of a regular grid (Fig. 1). The state of these systems (cells) is
represented by a real number, the cells interact locally, and their operation is continuous in time. The cell dy-
namics is described by the following nonlinear ordinary differential equation with delayed-nonlinear intercell
 CELLULAR ARRAYS 5

Fig. 1. A two-dimensional cellular array defined on a square grid. The ijth cell of the array is shaded black; cells that fall
within the sphere of influence of neighborhood radius r = 1 (the nearest neighbors) are gray.

coupling (the extension to higher dimensions is straightforward, allowing similar interlayer interactions):

where xij, uij, and yij are the state, input, and output voltages of the specified CNN cell, respectively. The
notation ij refers to a grid point associated with a cell on the 2-D M × N grid, and kl∈N r is a grid point in
the neighborhood within the radius r of the cell ij. Âij,kl represents the delayed nonlinear feedback, Bijˆ,kl the
delayed nonlinear control, and τA and τB represent finite time delays, respectively. The constant zij is the cell
current, which could also be interpreted as a space-varying threshold. In general, the CNN template, which is
the “program” of the CNN array, consists of the [A B z] terms (omitting the indices). The output characteristic
f is a sigmoid-type (e.g., piecewise linear) function. Note that the output equation also describes a first-order
dynamical system. The time constant of a (first-order) CNN cell is determined by the linear capacitor (C) and
the linear resistor (R), and it can be expressed as τ = RC. Without loss of generality R = 1 and C = 1 will be
considered.
Simplifying the interaction types to nondelayed linear operators (τA = 0 and τB = 0), omitting the dynamics
in the output equation (Cy = 0), and ceasing the space-variant nature of the cell current (zij → z) result in the
“standard-CNN” system [(23), the circuit theoretic model can be seen in Fig. 2]:
6 CELLULAR ARRAYS

Fig. 2. The circuit theoretic model of a standard CNN cell with voltage-controlled current sources.

Qualitative properties. Major efforts in CNN research have been concentrated on studying 2-D rectan-
gular standard cellular systems described by Eq. (5). Depending on the template values, the associated CNN
might exhibit a very complicated dynamics: stable, oscillatory, and chaotic patterns can also be generated. In
2-D signal (image) processing applications, usually the globally or completely stable CNN behavior is exploited
by creating the analog kernels of a complex algorithm. A comprehensive overview on stable CNNs can be found
in Ref. 81.
PDE versus CNN. The cellular array described by Eq. (4) can be used to approximate Eqs. (1)(2) (3)
to any required precision by introducing finite differences in space. As an example, let us derive the CNN
equation corresponding to a variant of Eq. (1), the linear heat equation [setting F = 0, L = 0 and g(I) = I], by
using a four-neighbor discretization of the Laplacian:

Thus the linear heat (diffusion) equation can be directly mapped onto the CNN array resulting in the
following simple template (choosing D = 1):

Programmed by this template and operating in the central linear region of the output characteristic, the CNN
solves the associated heat equation. Indeed, this “PDE machine” based on Eq. (5) has already been built as
an analog VLSI circuitry (e.g., Ref. 67). In general, Eq. (4) can be viewed as the mathematical framework for
analog parallel processing cellular arrays, discrete in space but continuous in time.
Systems Described by Local Rules: Cellular Automata. A CA consists of a regular lattice of cells
(see Fig. 1). Each cell takes q possible values, and is updated in discrete time steps according to a local rule 
that depends on the value of the neighboring cells. The value xij of a cell at position i,j in a 2-D CA with a rule
that depends on the neighbors within the radius k,l∈ N r evolves according to
 CELLULAR ARRAYS 7

There are several possible lattices and neighborhood structures for 2-D CAs. For instance, a five-neighbor
square CA (a “standard CA”) evolves as follows:

In most cases, xij takes binary values and  is a Boolean logic function of the neighboring cell values.
Qualitative properties. A major line of investigations in CA research deals with 1-D and 2-D standard
cellular systems described by Eq. (9). A qualitative characterization orders these CAs into four classes (12):
(i) evolution leads to a homogeneous state, (ii) evolution leads to a set of separated simple stable or periodic
structures, (iii) evolution leads to a chaotic pattern, and (iv) evolution leads to complex localized structures
(capable of “universal” computation).
PDE versus CA. The cellular array described by Eq. (8) can be used to approximate Eqs. 1, 2, 3 to any
required precision by introducing finite differences in space-time and discretizing the state variable. Taking
again the linear heat equation [derived from Eq. (1)] as an example, one obtains ( t = h)

Observe that in Eq. (10) the local rule  represents the linear combination of the neighboring cell values.
The state value Iij is quantized and in order to approximate properly the original PDE it should take multiple
discrete values.
CNN versus CA. Equation (10) is a fairly general CA model; however, it can also be viewed as a simple
discrete-time CNN model with no input (82). This also clarifies some important differences when comparing the
CA and CNN frameworks. The CA represents autonomous discrete-valued lattice dynamical systems, while the
CNN can be regarded as a general description of analog-valued nonautonomous cellular dynamical systems.
The “standard” framework of both the CA and CNN research is the mathematical description that closely
describes the core of the first hardware implementations. Note that a simple algorithm running on a CNN
hardware (67) can exactly emulate a binary CA with Boolean logic update rules (13).
Remarks. Any numerical integration formula solving (approximating) a PDE (and an associated CNN)
in the “binary universe” can be regarded as a general CA model although with multiple discrete states and
complicated local update rules. In general, Eq. (8) can be viewed as the mathematical framework for autonomous
digital parallel processing cellular arrays, discrete in space-time. A general nonautonomous nonlinear model
could be described by the discrete time version of Eq. (4), the discrete-time CNN equation [(82), DTCNN].

Architectures and Biological Relevance

Different CA and CNN architectures. Based on the preceding generic definition of the CNN [Eq. (4)]
and CA [Eq. (8)], several types of cellular arrays can be generated. They can be classified according to the
types of the grid, the processor (cell), the interaction (template or update rule), and the mode of operation.
Thus, building the core of a massively parallel computer based on cellular array architecture, the following key
points should be addressed in detail:

(1) Grid types Cellular arrays are usually defined on a spatially discrete square (rectangular) grid, however,
hexagonal and triangular arrangements can also be considered (Fig. 3(a–c)). These grids are the only
8 CELLULAR ARRAYS

Fig. 3. The most common and two special grid types of cellular architectures. Regular contiguous tessellations of the
plane based on congruent polygons are shown in the top row: (a) rectangular, (b), triangular, and (c) hexagonal lattices. In
the bottom row two special grid types are given that belong to the ornamental group. All grid types (b)–(e) could be mapped
to a rectangular grid (a) with periodic space-variant interconnections.

regular contiguous tessellations of the plane based on congruent polygons alone. Other grid types can
also be created based on nonregular congruent polygons or from a regular vertex grid through discrete
geometrical transformations: rotations and translations [ornamental groups, Fig. 3(d–e)]. A great number
of these grids can be mapped on a typical eight-neighbor rectangular structure with periodic space-variant
connections (83). Multiple and varying grid sizes (e.g., coarse and fine grids, and logarithmically changing
size) may be useful in simulating adaptive biological systems (e.g., retina, lateral geniculate nucleus (LGN),
or magno-parvo pathways in the cortex).
(2) Cell (processor) types and boundary cell types Cellular arrays can be built from linear or nonlinear, first- or
higher-order cells. A linear or “small-signal” operation (as a special case) is achievable through piecewise
linear output characteristics. A highly nonlinear dynamic behavior (typical CNN models) is attainable
through a sigmoid, Gaussian, or inverse-Gaussian type output characteristics. Cells can include additional
local analog and/or logical memories for storing intermediate processing results. A cell might perform
local logic operations (typical CA models) or a combined analogic (analog and logic) computation (extended
CNN models). The cells of an array can be uniform or nonuniform (regularly or slightly varying). In some
processing tasks two or three cell types in a regular grid might be very useful, for example, in color image
processing. Since in any physical implementation only a finite array can be built, a boundary condition
should be exactly defined. Creating boundary cells that are not involved in the cooperative computation
(“virtual cells”) can satisfy this requirement. The most important boundary cell specifications are as follows:
(i) In the fixed (Dirichlet) type, constant values are assigned to all boundary cells. (ii) In the zero-flux
(Neumann) type, boundary cells are made to follow cells that are on the same side of the array. (iii) In the
 CELLULAR ARRAYS 9

periodic (toroidal) type, boundary cells are made to track the values of cells from the opposite side of the
array.
(3) Neighborhood size and interaction types The interaction type (the biological “synapse”) between the grid
cells represents the program of a cellular array. Depending on whether these interaction types are fixed
or programmable, the array can be regarded as a specific-purpose (see previous section on CA and smart-
sensor implementations) or a reconfigurable (see previous section on the CNN-UM and its implementations)
parallel array architecture. The nearest neighborhood is the most common sphere of influence in the intercell
communication for both CA and CNN models (either the cross-shaped fourfold-connected or the star-shaped
eightfold-connected neighborhoods); however, larger neighborhood sizes can also be considered (typically
in biological modeling or when creating adaptive artificial systems). The interaction types can be linear or
nonlinear memoryless functions [e.g., a typical CA update rule corresponding to Eq. (8)] of one, two, or more
variables. Delayed nonlinear [e.g., a typical CNN template corresponding to Eq. (4)] and dynamic (lumped)
interactions are more general connection types. By breaking the symmetry or isotropy and moreover varying
the nature of the interconnections in space and/or in time, an extremely rich collection of further templates
(or local update rules) can be created.
(4) Modes of the operation The mode of operation can be continuous (general CNN models) or discrete time
(general DTCNN and CA models). In the case of a discrete-time procedure the update mechanism can be
synchronous or asynchronous. The computation can be analog, logic, or analogic (see also item 2) and can be
executed either in local mode or in propagating mode (on a decoupled or coupled array, respectively). Besides
the usual fixed-point operational mode (equilibrium computing), transient (nonequilibrium computing),
oscillating, chaotic, and general stochastic modes can also be used.

The CNN Universal Machine: An Analogic Stored Program Cellular Array Computer. A cel-
lular architecture that includes the main properties listed and discussed in the previous subsection is the
CNN Universal Machine [CNN-UM (58)] The CNN-UM makes it possible to combine efficiently analog array
operations with local logic. Because the reprogramming time is approximately equal to the settling time of a
nonpropagating analog operation, it is capable of executing complex analogic (analog and logic) algorithms. To
ensure programmability, a global programming unit was added to the array and for an efficient reuse of inter-
mediate results, each computing cell was extended by local memories. In addition to local storage, every cell
might be equipped with local sensors and additional circuitry to perform cellwise analog and logical operations.
The architecture of the CNN-UM is shown in Fig. 4.
The CNN-UM is built around the dynamic computing core of a simple CNN. An image can be acquired
through the sensory input [e.g., optical sensor (OPT)]. Local memories store analog [local analog memory
(LAM)] and logic [local logical memory (LLM)] values in each cell. A local analog output unit (LAOU) and
a local logic unit (LLU) perform cellwise analog and logic operations on the stored values. The output is
always transferred to one of the local memories. The local communication and control unit (LCCU) ensures
the communication between the extended cell and the central programming unit of the machine, the global
analogic programming unit (GAPU). The GAPU has four functional blocks. The analog program register (APR)
stores the analog program instructions, the CNN templates. In the case of linear templates, for connectivity r
= 1, a set of 19 real numbers has to be stored (this number is even less for both linear and nonlinear templates
assuming spatial symmetry and isotropy). All other units within the GAPU are logic registers containing the
control codes for operating the cell array. The local program register (LPR) contains control sequences for the
individual cell’s LLU, and the switch configuration register (SCR) stores the codes to initiate the different switch
configurations when accessing different functional units (e.g., whether to run a linear or nonlinear template).
The global analogic control unit (GACU) stores the instruction sequence of the main (analogic) program. The
GACU also controls the timing, sequence of instructions and data transfers on the chip and synchronizes the
communication with any external controlling device.
10 CELLULAR ARRAYS

Fig. 4. The architecture of the CNN Universal Machine, the stored program analogic array supercomputer.

Synthesizing an analogic algorithm running on the CNN-UM, the designer should decompose the solution
to a sequence of analog and logical operations. A limited number of intermediate results can be locally stored
and combined. Some of these outputs can be used as a bias map (space-variant bias) or fixed-state map
(space-variant mask) in the next operation by adding spatial adaptivity to the algorithms without introducing
complicated intercell couplings. Either a linear or a nonlinear template defines analog operations. The output
can be defined both in fixed and nonfixed states of the network (equilibrium and nonequilibrium computing),
depending on the control of the transient length. It can be assumed that elementary logical (NOT, AND, OR, etc.)
and arithmetical (ADD, SUB) operations are implemented and can be used at the cell level between LLM and
LAM locations, respectively. In addition, data transfer and conversion can be performed between LAMs and
LLMs.
Biological Relevance. Earlier it was explained why cellular arrays can be viewed as efficient PDE ma-
chines in simulating physics. Here, some key observations made in biology—based on morphological, pharma-
cological, and physiological measurements—will be recalled that underline the biological relevance of cellular
architectures and also the analogic operational mode of array computing.
At the neuronal level, it is instructive that many complex neural functions are performed without spikes,
and in many visual functions (e.g., within the retina of the vertebrates) 2-D layers of locally connected neurons
perform some tasks that combine both spikeless (analog) and spike-type (logic) processing as well (84). Cellular
arrays are also natural models for topographic maps of biological sensory systems (84). At the neural systems
level, recent physiological discoveries have shown that complex visual tasks are solved by using several different
projections of the same image stored “retinotopically” in different parts of the brain (cortex) as a “multiscreen
theater” (85). Finally, at the cognitive systems level, the evidence of functional cerebral hemispheric asymmetry
of the brain (86) provides a strong motivation for formulating the cellular computing model as a nonlinear
analogic (dual) computing structure (87) and justifies a novel approach to computational complexity (88).
 CELLULAR ARRAYS 11

Physical Implementation

In this section a brief overview on the main physical implementation trends of cellular arrays will be given. The
emphasis will be put on those reconfigurable cellular architectures that interact with the physical world, that
is, where on-chip sensing and flexible computing are integrated. For these engineering prototypes CA models
cannot be considered as a general framework. The unifying paradigm is rather a CNN-type general model with
locally connected analog “computing sensors” arranged on a regular rectangular grid. Specific purpose vision
chips (“smart sensors”) make up a very important class of these architectures, in which sensing is combined
with a specific functionality. These chips are special-purpose nonprogrammable (only tunable) information
sensing devices. Programmable single-chip visual microprocessors can be considered as a more general class
developed within the CNN framework. The general architecture of these reconfigurable devices (CNN-UM)
has been described in the previous section and lead to efficient optoelectronic prototypes. Throughout the
section the phrase visual sensing should be understood in a very broad sense: it rather describes a general 2-D
sampling of any physical property of the environment (e.g., color, temperature, pressure, smell) than only the
2-D representation of the light intensity within the visible spectrum.
CA implementations. The CA theory evolved in parallel with the advance of digital technology that
implemented noncellular architectures and used sequential computing principles for decades. Though the
theory of autonomous cellular automata machines (CAMs) was well developed in the 1980s, single-chip large-
scale 2-D prototypes had not been fabricated. The CA framework was used in parallel supercomputer [e.g.,
the Connection Machine (89)] and massively parallel processor design [MPP (90)], furthermore in specific
cryptographic and test hardware synthesis. However, this framework was not widely used in engineering
designs integrating array sensing and computing.
Specific-Purpose vision Chips: Smart Sensors. Carver Mead, who first introduced the idea of
neuromorphic engineering using VLSI technologies in the 1980s, pioneered the research field of smart sensors
(71, 91, 92). The main idea was to integrate the photodetecting elements with the processing circuits on the
same chip and perform sensor information processing without redundant and unnecessary data acquisition
(“smart sensing”). The smart-sensor concept implies a low-level interaction between the sensors and proces-
sors; therefore, modular camera-processor combinations do not belong to this class. During the last decade the
sensors that have been embedded into these devices were almost exclusively photodetecting elements; how-
ever, recently other types have also been designed in cellular array architectures (e.g., high-resolution tactile
sensors).
Specific-purpose vision chips are optimized for certain functionality, for the quality of processing, instead
of the acquired image quality aimed by high-resolution and precision cameras. The advantage of vision chips
lies in their very high processing speed, large (usually adaptively controlled) dynamic range, small size, and low
power dissipation compared to camera-processor combinations. At the current stage, it is a drawback that most
of these devices are fully custom designed (time consuming, costly, and error prone) and that the implemented
algorithms should account for the hardly controllable inaccuracies of analog VLSI systems. Furthermore, none
of the vision chips are of general purpose, i.e., they could be parameter tunable within certain limits but
are not programmable to perform different vision tasks. This property is particularly undesirable during the
development and test phase of a vision system.
The main technologies used in vision chip fabrication are complementary metal-oxide semiconductor
(CMOS), charge-coupled device (CCD), bimetal CMOS (BiCMOS), and GaAs (MES-FET and HEMT), though
CMOS was exclusively used in the majority of the designs. Vision chips can be classified (93) into spatial (e.g.
94,95), spatiotemporal (e.g., 9697–98), and optical neurochip (e.g., Ref 99) groups.
Programmable Visual Microprocessors (CNNM-UM chips). Specific-purpose vision chips are non-
programmable cellular architectures. Since they implement only a specific functionality they require a top level
system for complex information processing. Similarly, all fully connected neural network chip realizations have
a common feature: they implement a single instruction only; thus the weight matrix is fixed when processing
12 CELLULAR ARRAYS

some input. Reprogramming (i.e., changing the weight matrix) is possible for some devices but takes longer
time (by orders of magnitudes) than the computation itself.
These observations motivated the design of the CNN-UM (58), a stored program nonlinear array computer.
The CNN-UM can also be viewed as a visual microprocessor especially when it is built with a focal plane
sensory array. Different analog VLSI implementations of CNN-UM chips and a comparison of their performance
characteristics can be found in Table 1. The first fully working implementation that can run analogic algorithms
is the 1995 mixed-signal version (it has an optical input) from Seville (62). This chip, embedded into the CNN
prototyping system (100), was used in various experiments validating CNN templates and algorithms. The
most promising is certainly the latest version of these implementations fabricated in 1998 (67) (see the last
column). It has a 64 × 64 CNN array with optical input, and in addition to the features shown in Table 1 it
allows the use of fixed-state map techniques, global logical lines, and ARAMs (analog random access memory)
(66) during the algorithm synthesis. This prototype already paves the road toward industrial applications.
There is always a gap between the system level design and chip implementations. Trying to synthesize
powerful algorithms that can keep up with the state-of-the art methods of signal-processing disciplines, the
engineer at the system level always faces the problem of hardware limitations and has to simplify the method-
ologies used. On the other hand, a VLSI designer would like to know the priority of the requirements motivated
by different applications. At the current stage, the need for higher-order (complex) cells, nonlinear interactions,
larger neighborhood size, and space-variant programming contradicts the requirement of higher resolution.
Designing the future generation of CNN-UM chips the cell area versus functionality trade-off will always be
one of the main issues with which to cope.
 CELLULAR ARRAYS 13

Fig. 5. Spatial edge (middle row) and spatiotemporal motion (bottom row) detection output from a “retinotopic” compu-
tation executed on a CNN-UM chip (input is shown in the top row). Simply reprogramming the array can test different
biological retina models.

Applications

In this section some applications based on cellular array architectures will be highlighted. Since these ar-
eas are very diverse the objective of this summary is only to show how various disciplines can profit from
having a programmable (reconfigurable) “visual” microprocessor equipped with both analog and logical com-
puting capabilities. It is stressed that the algorithmic flexibility connecting biology, physics, and chemistry
on these cellular architectures also fertilizes the engineering designs targeting industrial and other real-life
applications. Experimental results based on existing prototypes (63, 67) will also be demonstrated.
Biological Modeling: Revealing Adaptation and Plasticity. Cellular architectures have been ex-
tensively used in various biological modeling experiments (e.g., 2425262728–29) but probably retina modeling
is the only interdisciplinary research field that has significantly influenced the engineering designs. For in-
stance, most specific-purpose vision chips aim to reproduce some well-defined functionality (e.g., spatial edge
detection or spatiotemporal motion detection) of this “front end” of biological visual systems.
The retina is said to be the “approachable part of the brain” (101) and indeed, currently a large number
of morphological observations, pharmacological, and physiological measurements are at hand helping us to
understand the cells, synapses, and circuitry of this tiny neural processing layer. It is certainly due to its
enormous complexity and emerging computational capability that even nowadays the neural code sent to the
cortex is not fully understood. Vision chip design exploits the information learned about the structure and
some functionality of the retina, but usually there are radical differences comparing biological and silicon
retinas at the cell and synaptic levels. Also, the observed measured functional richness, the adaptation and
plasticity properties in the retina assume, in engineering terms, a very flexible re-programmability that is not
incorporated into these smart sensor architectures.
Theoretical research and implementation in the CNN field have evolved into a closer interaction with
retinal modeling experiments (25). Due to this fact the latest CNNU-UM chip (67) is capable of computing both
the spatial edge and spatiotemporal motion features of an image sequence (Fig. 5). Other functionality can
also be easily tested, i.e., simply by reprogramming this architecture, one can generate hypotheses on various
retinal models.
Retina modeling also motivated a new direction in CNN chip designs trading resolution for so-called
complex cells (higher-order cells with more complicated synapses) that can also be interpreted as having
multilayer CNN structures with simple cells (102). Just taking a glance at a simplified outer-retina model
14 CELLULAR ARRAYS

Fig. 6. A three-layer base model of the outer plexiform layer (OPL) in the retina. Each biological cell layer is mapped onto
a CNN layer that consists of first- or second-order (two mutually coupled first-order) cells. Some pathways and connections
are also indicated that still represent a controversial issue in neurobiology.

[(28), Fig. 6] that requires at least a three-layer cellular architecture, it is easy to understand why the physical
implementation of cellular arrays has made only the first steps toward a real neuromorphic and programmable
visual microprocessor.
Programmable Physics: Diffusion and Wave Models. The PDE-related diffusion-type CNN tem-
plate derived earlier could be used to emulate a diffusion mechanism on a CNN-UM chip (67). Starting from
an arbitrary initial condition (a gray-scale image) the linear heat diffusion results in a progressively low-pass-
filtered version of the original image [Fig. 7(a)]. Changing the value of the central term in the feedback matrix
(a0 = 3) and the bias value (z = 2.75) a nonlinear trigger-wave propagation can also be generated from an
arbitrary initial patch [Fig. 7(b)]. As it can be seen the direction of the propagation is reversible (it depends on
the sign of the bias value). These two simple cases, based on first-order cells, demonstrate how physics can be
easily programmed on a cellular architecture. More complicated wave phenomena can also be generated based
on second-order cells as shown in Fig. 7(c)–(f) (see further examples in 38 and 45).
Programmable Chemistry: Self-Assembly in Chemical Substances. There are several classes
of CNN templates (4041–42) capable of simulating self-assembly in chemical substances. In the following
experiments it will be shown how checkers, patches, stripes, and various combination of these spatial patterns
can be formed from random initial conditions on a CNN-UM chip (67) programmed by these templates (Fig. 8).

Cellular Computing in Engineering Designs. In this subsection the image-flow processing capabili-
ties of cellular architectures will be discussed. It is demonstrated how a cellular computer vision system builds
on the instructions derived during biological, physical and chemical modeling experiments. This is a radically
different approach to synthesizing a “computer vision” algorithm compared to traditional methods since it is
based on programmable receptive fields, transport mechanisms (diffusion and waves), and self-organization
phenomena.
A cellular computing system is capable of multidimensional information processing. The data can be
acquired either in the focal plane (through the on-chip sensors integrated with the cells of the system) or
transferred from other array sensor devices (e.g., a CCD camera). In this subsection two such engineering
designs based on cellular architectures and analogic cellular computing will also be shortly presented. In these
prototypes the flexibility of a recently designed CNN-UM chip (67) and hardware-software environment (100)
is exploited building a focal-plane and an online video-flow processing application.
Cellular Computer Vision. The architectures and physical implementation of cellular systems were
discussed in previous sections. Here, some key operators and the algorithmic aspects of cellular computing will
 CELLULAR ARRAYS 15

Fig. 7. Programmable physics on a cellular architecture based on first-order and second-order cells: (a) snapshots of a
controlled diffusion process, (b) snapshots of a reversed trigger-wave propagation, (c) initial patches for wave generation,
(d) traveling waves, (e) autowaves, (f) spiral waves.

be addressed. Figures 9, 10, 11 illustrate how biological, physical, and chemical models can be interpreted as
meaningful operators in image processing.
In Fig. 9 programmable receptive fields (edge and corner detection), wave-type computation (reconstruc-
tion and connected component detection) and spatial logic (XOR) is used to build up the analogic algorithm
solving an object classification problem. In this simple example [Fig. 9(a)] isolated objects that have no corners
should be identified marking the horizontal and vertical object extension (coordinates) along the image edges
[Fig. 9(g–h)]. The task is solved combining analog operations (either with local or global dynamics) with spatial
logic relying on a programmable cellular architecture with local memories.
Various filters can be constructed based on diffusion-type computation as illustrated in Fig. 10. Observe
in Fig. 10(b) the low-pass filtered and in Fig. 10(c) the band-pass filtered output of the test image given in Fig.
10(a). Self-organizing phenomena can also be exploited in image processing. By creating a halftone version
of a gray-scale image, an adaptive pattern-creating feature helps us to obtain a visually pleasing binary
representation of the original image as shown in Fig. 10(d).
The global dynamics of locally connected cellular arrays is a key property in building powerful image flow
processing algorithms. Operators derived from transport mechanisms allow us to combine controlled diffusion
16 CELLULAR ARRAYS

Fig. 8. Programmable chemistry on a cellular architecture pattern-creating self-organization phenomena: (b) checkers,
(c) patches, and (d) stripes formed from a random initial condition (a). A colorful combination of the basic motifs can also
be generated (e)–(g).

Fig. 9. Programmable receptive fields, wave-type computation, and spatial logic in analogic cellular image processing.
The example demonstrates the intermediate steps of an analogic algorithm: (a) original image; (b) result of edge detection;
(c) result of corner detection; (d) objects reconstructed from corners; (e) isolated object without corners obtained through
spatial logic; (f) edge of the detected object; (g) vertical extension of the detected object; (h) horizontal extension of the
detected object.

and waves within the analogic algorithmic framework and make it possible to solve sophisticated detection-
reconstruction problems. Such an example is shown in Fig. 11, tracking the contour of the left ventricle where
diffusion-type filters were used in noise suppression and trigger waves in boundary detection.
Focal-plane Object Classification. Ultrahigh frame-rate (exceeding 10,000 frame/s) image processing is
an unsolved problem with current digital systems of affordable price and size. Both the limited computational
 CELLULAR ARRAYS 17

Fig. 10. Diffusion-type computation and self-organization in analogic cellular image processing. (a) Original image; (b) the
output of a blurring low-pass filter realized through controlled diffusion mechanism; (c) the output of an edge enhancing
band-pass filter realized through diffusion mechanism and spatial arithmetics; (d) halftone (binary representation of a
gray-scale image) output obtained through adaptive pattern creating self-organization.

Fig. 11. Using transport (diffusion and wave) mechanisms in analogic cellular image processing. Top row: snapshots of the
human heart on an echocardiography sequence. The image-flow shows the spatiotemporal deformation of the left ventricle
(the largest heart chamber). Bottom row: detected contour of the left ventricle calculated by an analogic cellular algo-
rithm. Diffusion-type filters were used in noise suppression and trigger-waves in boundary detection. The spatiotemporal
consistency was ensured through inter-frame spatial logic operations.

power and the I/O bottleneck (when the image is transferred from the sensor to the processor) represent major
obstacles in digital systems.
Cellular neural or nonlinear network (CNN) technology offers a parallel and analogic (combined analog
and logic) approach to these problems. If a CNN chip is used as a focal-plane array, even a zero computational
load requirement is achievable (the processing is limited by the image acquisition only). The chip (63) acts
as a focal-plane visual microprocessor: it acquires image frames parallel through the optical input, transfers
them to the processor elements, and performs the analysis also in parallel. In 20 µs, approximately five analog
operations (CNN templates) and ten local logic operations can be completed. This makes it possible that even a
complex morphological decision can be performed on-chip within two subsequent frames at a 50,000 frames/s
operational speed.
The experimental setup of the focal-plane classification system is shown in Fig. 12(a). The CNN platform
that carries the chip is mounted on the back panel of a camera (only the optics is used, no shutter is required).
On a rotating disk different images are posted and during the experiment these images are projected onto the
chip through the lens system of the camera [see the images acquired by the on-chip sensor in Fig. 12(b)].
In the experiment objects are classified based on their local morphological features by a complex analogical
algorithm. In Fig. 13 the major subroutines of the algorithm are shown along with their measured on-chip time
performance (no transfer and display time included). This demonstration proves that the current CNN system
18 CELLULAR ARRAYS

Fig. 12. The ultra high-speed focal-plane array processor system: (a) the experimental setup, (b) the objects silhouettes
captured by the 20 × 22 CNN-UM chip.

Fig. 13. The flow chart of the object classification algorithm and the measured time performance on the 20 × 22 CNN-UM
chip. A binary-morphology-based analogic cellular algorithm ensures rotation and translation invariant detection.

is able to classify six different flying objects (hot-air balloons and airplanes) based on their silhouettes’ low-
resolution projections on the chip’s optical sensors at a speed of approximately 10,000 frames/s.
Online Video-flow Processing. In the last few years particle detection and classification in fluid flows
have received considerable interest among the applications requiring image processing at ultrahigh frame rates.
For instance, a sensory module capable of identifying the density of debris particles in the oil flow of various
engines would enable a cost-effective online monitoring of these systems (e.g., condition-based monitoring of
jet engines).
In these applications the CNN chip can be used either as a focal-plane array processor or a video-flow
processing visual microprocessor. In the latter case recent feasibility studies and experiments indicate that in
a demonstration, the prototype system detection and classification of the particles can be performed online on
a 64 × 64 CNN chip (67).
 CELLULAR ARRAYS 19

Fig. 14. The online video-flow processing system: (a) the experimental setup, (b) a typical image frame acquired by the
CCD camera, (c) identified marble superimposed onto the original image, (d) identified bubbles superimposed onto the
original image.

Fig. 15. The flow chart of the bubble-marble classification algorithm with the time requirement of the algorithm subrou-
tines on a 64 × 64 CNN-UM chip. The analogic algorithm is based on binary morphology and diffusion-type operators.

Figure 14(a) shows the experimental setup of the online video-flow demonstration. In a water tank
containing bubbles and marbles, a fast turbulent flow is generated. The task is to detect and separate the
marbles from air bubbles in each acquired image. A typical image acquired by the CCD camera can be seen in
Fig. 14(b), a detected marble in Fig. 14(c), and the identified bubbles in Fig. 14(d).
The algorithm consists of the following processing stages: (i) adaptive thresholding, in which all objects
are detected in the image field through a spatially adaptive thresholding, (ii) morphological prefiltering, in
which objects are compared to prototype objects to filter out single bubbles and bubble groups, also to classify
the remaining objects into different particle groups, (iii) object classification, such that in the last stage objects
are classified based on their size and morphology (and a simple statistics is calculated for different object
groups).
The on-chip time performance of the subroutines of the algorithm is summarized in Fig. 15 (no transfer
and display time included). The demonstration proves that with the current CNN system a morphology-based
complex algorithm can be executed during an online video-flow processing.

Summary

Various cellular array architectures that have been proposed for massively parallel computing were discussed.
It has been argued that though the physical laws are often described by PDEs, the abstract engineering
computing machine is rather a cellular structure that is discrete in space, continuous or discrete in time, and
is based on analog/discrete computing devices (processors).
20 CELLULAR ARRAYS

It has been shown that though historically rooted from cellular automata (and fully connected neural
networks) current implementation trends and biological modeling results justify the intensive research ef-
forts on the field of cellular nonlinear/neural networks. This is especially true when both array sensing and
computing are to be addressed within a unified framework. It has been stressed that in order to have a re-
configurable cellular computing array, stored programmability is a key issue in architecture design targeting
various application areas in engineering, biology, chemistry and physics.

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CSABA REKECZKY
TAMÁS ROSKA
Computer and Automation Institute of
the Hungarian Academy of Sciences
and Péter Pázmány Catholic
University
 CHEBYSHEV FILTERS 267

processing, where the signal is processed by a linear system

that changes the amplitudes and phases of these components,
but not their frequencies. In a simple form, this processing
can be used to let pass or to reject selected frequency bands,
ideally with no attenuation at the passbands and infinite at-
tenuation at the stopbands. This article discusses a class of
approximations to this kind of ideal filter, known as an Che-
byshev filter. It starts with a discussion on a technique for
the derivation of optimal magnitude filters, then discusses the
direct and inverse Chebyshev approximations for the ideal
filtering operator, ending with comments on extensions of the
technique. Tables with example filters are included.
The magnitude approximation problem in filter design con-
sists essentially of finding a convenient transfer function with
the magnitude satisfying given attenuation specifications.
Other restrictions can exist, such as structure for implemen-
tation, maximum order, and maximum Q of the poles, but
in most cases the problem can be reduced to the design of a
normalized continuous-time low-pass filter, which can be de-
scribed by a transfer function in Laplace transform. This filter
must present a given maximum passband attenuation (Amax),
between 웆 ⫽ 0 and 웆 ⫽ 웆p ⫽ 1 rad/s, and a given minimum
stopband attenuation (Amin) in frequencies above a given limit
웆r rad/s. From this prototype filter, the final filter can be ob-
tained by frequency transformations and by continuous-time
to discrete-time transformations in the case of a digital fil-
ter (1).
A convenient procedure for the derivation of optimal mag-
nitude filters is to start with the transducer function H(s) and
the characteristic function K(s). H(s), which can also be called
the attenuation function, is the inverse of the filter transfer
function, scaled such that min 兩H( j웆) ⫽ 1兩. K(s)is related to
H(s) by the equation

|H( jω)|2 = 1 + |K( jω)|2 (1)

This greatly simplifies the problem, because K( j웆) can be a

ratio of two real polynomials in 웆, both with roots located
symmetrically on both sides of the real axis, while H( j웆) is a
complex function. K(s) is obtained by replacing 웆 by s/j in
K( j웆) and ignoring possible ⫾j or ⫺1 multiplying terms re-
sulting from the operation. The complex frequencies where
K(s) ⫽ 0 are the attenuation zeros, and where K(s) ⫽ 앝 corre-
spond to the transmission zeros. If K(s) is a ratio of real poly-
nomials, K(s) ⫽ F(s)/P(s), H(s) is also a ratio of real polynomi-
als in s, with the same denominator, H(s) ⫽ E(s)/P(s), and
E(s) can be obtained by observing that for s ⫽ j웆 Eq. (1) is
equivalent to

H(s)H(−s) = 1 + K(s)K(−s) ) E(s)E(−s)

(2)
= P(s)P(−s) + F (s)F(−s)

Because E(s) is the denominator of the filter transfer function,

which must be stable, E(s) is constructed from the roots of the
polynomial P(s)P(⫺s) ⫹ F(s)F(⫺s) with negative real parts.
The desired transfer function is then T(s) ⫽ P(s)/E(s).

CHEBYSHEV FILTERS CHEBYSHEV POLYNOMIALS

Any signal can be considered to be composed of several sinus- Two important classes of approximations, the direct and in-
oidal components with different frequencies, amplitudes, and verse Chebyshev approximations, can be derived from a class
phases. Filtering is one of the fundamental methods for signal of polynomials known as Chebyshev polynomials. These poly-

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.
268 CHEBYSHEV FILTERS

Table 1. Chebyshev Polynomials Or, the attenuation in decibels is

n Polynomial A(ω) = 10 log{1 + [Cn (ω)]2 } (9)

0 1
1 x The parameter ⑀ controls the maximum passband attenua-
2 2x ⫺ 1 tion, or the passband ripple. Considering that when Cn(웆) ⫽
3 4x 3 ⫺ 3x ⫾1 the attenuation A(웆) ⫽ Amax Eq. (9) gives
4
5
8x 4 ⫺ 8x 2 ⫹ 1
16x 5 ⫺ 20x 3 ⫹ 5x =
p10 0.1A max −1 (10)
6 32x 6 ⫺ 48x 4 ⫹ 18x2 ⫺ 1
7 64x 7 ⫺ 112x 5 ⫹ 56x 3 ⫺ 7x
Figure 2 shows examples of the magnitude function 兩T( j웆)兩 in
8 128x 8 ⫺ 256x 6 ⫹ 160x 4 ⫺ 32x 2 ⫹ 1
9 256x 9 ⫺ 576x 7 ⫹ 432x 5 ⫺ 120x 3 ⫹ 9x
the passband and in the stopband obtained for some normal-
10 512x 10 ⫺ 1280x 8 ⫹ 1120x 6 ⫺ 400x 4 ⫹ 50x 2 ⫺ 1 ized Chebyshev low-pass approximations, with Amax ⫽ 1 dB.
11 1024x 11 ⫺ 2816x 9 ⫹ 2816x 7 ⫺ 1232x 5 ⫹ 220x 3 ⫺ 11x The magnitude of the Chebyshev approximations presents
12 2048x 12 ⫺ 6144x 10 ⫹ 6912x 8 ⫺ 3584x 6 ⫹ 840x 4 ⫺ 72x 2 ⫹ 1 uniform ripples in the passband, with the gain departing from
0 dB at 웆 ⫽ 0 for odd orders and from ⫺Amax dB for even
orders.
The stopband attenuation is the maximum possible among
nomials were first described by P. L. Chebyshev (2). The
filters derived from polynomial characteristic functions and
Chebyshev polynomial of order n can be obtained from the
with the same Amax and degree (4). This can be proved by as-
expression
suming that there exists a polynomial Pn(x) that is also
Cn (x) = cos(n cos−1 x) (3) bounded between ⫺1 and 1 for ⫺1 ⱕ x ⱕ 1, with Pn(x) ⫽
⫾Pn(⫺x) and Pn(⫹앝) ⫽ ⫹앝, which exceeds the value of Cn(x)
It is simple to verify that this expression corresponds, for for some value of x ⬎ 1. An approximation using this polyno-
⫺1 ⱕ x ⱕ 1, to a polynomial in x. Using the trigonometric mial instead of Cn(x) in Eq. (7) would be more selective. The
identity cos(a ⫹ b) ⫽ cos a cos b ⫺ sin a sin b, we obtain curves of Pn(x) and Cn(x) will always cross x times for ⫺1 ⱕ
x ⱕ 1, due to the maximum oscillations of Cn(x), but if Pn(x)
Cn+1 (x) = cos[(n + 1) cos−1 x] grows faster, they will cross another two times for x ⱖ 1 and
(4) x ⱕ ⫺1. This makes Pn(x) ⫺ Cn(x) a polynomial of degree n ⫹
= xCn (x) − sin(n cos−1 x) sin(cos−1 x)
2, because it has n ⫹ 2 roots, which is impossible since both
Applying now the identity sin a sin b ⫽ 
[cos(a ⫺ b) ⫺ are of degree n.
cos(a ⫹ b)] and rearranging, a recursion formula is obtained: The required approximation degree for given Amax and Amin
can be obtained by substituting Eq. (6) in Eq. (9), with
Cn+1 (x) = 2xCn (x) − Cn−1 (x) (5) A(웆r) ⫽ Amin and solving for n. The result, including a denor-
malization for any 웆p, is
For n ⫽ 0 and n ⫽ 1, we have C0(x) ⫽ 1 and C1(x) ⫽ x. Using
−1
Eq. (5), the series of Chebyshev polynomials shown in Table cosh γ
1 is obtained. n≥ −1
(11)
cosh (ωr /ω p )
The values of these polynomials oscillate between ⫺1 and
⫹1 for x between ⫺1 and ⫹1, in a pattern identical to a sta-
where we define the constant 웂 as
tionary Lissajous figure (3). For x out of this range, cos⫺1 x ⫽
j cosh⫺1 x, an imaginary value, but Eq. (3) is still real, in the

form 100.1A min − 1
γ = (12)
100.1A max − 1
−1 −1
Cn (x) = cos(n j cosh x) = cosh(n cosh x) (6)

For high values of x, looking at the polynomials in Table 1,

C1 C2 C3
we see that Cn(x) 앒 2n⫺1xn and grows monotonically. The plots
of some Chebyshev polynomials for ⫺1 ⱕ x ⱕ 1 are shown in
Fig. 1.

THE CHEBYSHEV LOW-PASS APPROXIMATION

This normalized Chebyshev low-pass approximation is ob- C4 C5 C6

tained by using

K( jω) = Cn (ω) (7)

The result is a transducer function with the magnitude given

by [from Eq. (1)]

Figure 1. Plots of the first six Chebyshev polynomials Cn(x). The
squares limit the region ⫺1 ⱕ x ⱕ1, ⫺1 ⱕ Cn(x) ⱕ 1, where the poly-
|H( jω)| = 1 + [Cn (ω)]2 (8)
nomial value oscillates.
 CHEBYSHEV FILTERS 269

The transfer functions for the normalized Chebyshev filters jω

can be obtained by solving Eq. (2). For a polynomial approxi- –1
mation, using P(s) ⫽ 1, from Eq. (7) it follows that cosh ( 1 sinh 1)
n

s  2 sinh ( 1 sinh
–1
1)
E(s)E(−s) = 1 + Cn (13) n
j π
π 2n
The roots of this polynomial are the solutions for s in n
π

s
s
 j n
Cn = cos n cos−1 =± (14)
j j  π
n
σ
Identifying
s
n cos−1 = a + jb (15)
j

it follows that ⫾j/ ⑀ ⫽ cos(a ⫹ jb)⫽ cos a cos jb ⫺ sin a

sin jb ⫽ cos a cosh b ⫺ j sin a sinh b. Equating real and
imaginary parts, we have cos a cosh b ⫽ 0 and sin a sinh b ⫽
⫿1/ ⑀. Since cosh x ⱖ 1, the equation of the real parts gives:
π
a= (1 + 2k), k = 0, 1, . . ., 2n − 1 (16)
2
Figure 3. Localization of the poles in a normalized Chebyshev low-
pass approximation (seventh order, in this case). The pole locations
|T( jω)|dB can be obtained as shown.
0 1
0
1 ω
3 and as for these values of a, sin a ⫽ ⫾1, the equation of the
5 imaginary parts gives
6
−1 1
4 b = ∓ sinh (17)

–1 2
By applying these results in Eq. (15), it follows that the roots
(a)
of E(s)E(⫺s) are
|T( jω)|dB
1 10 sk = σk + jωk k = 0, 1, . . ., 2n − 1
ω
0

π 1 + 2k 
1 1

−1
–1 σk = sin sinh sinh
2 n n  (18)
1

π 1 + 2k 
1 1

−1
ωk = cos cosh sinh
2 n n 

The roots sk with negative real parts (k ⱖ n) are the roots of

E(s). By the expressions in Eq. (18), it is easy to see that the
roots sk are located on an ellipse with vertical semi-axis cosh
(1/n sinh⫺1 1/ ⑀), horizontal semi-axis sinh (1/n sinh⫺1 1/ ⑀), and
foci at ⫾j. The location of the roots can be best visualized with
5 the diagram shown in Fig. 3 (3).

REALIZATION OF CHEBYSHEV FILTERS

These approximations were originally developed for realiza-

10
–100 tion in passive form, and the best realizations were obtained
as LC doubly terminated structures designed for maximum
(b) power transfer at the passband gain maxima. These struc-
Figure 2. Passband gain (a) and stopband gain (b) for the first nor- tures are still important today as prototypes for active and
malized Chebyshev approximations with 1 dB passband ripple. Ob- digital realizations, due to the low sensitivity to errors in ele-
serve the uniform passband ripple and the monotonic stopband gain ment values. At each attenuation zero, and the Chebyshev
decrease. approximations have the maximum possible number of them
270 CHEBYSHEV FILTERS
distributed in the passband, maximum power transfer occurs
between the terminations. In this condition, errors in the ca-
pacitors and inductors can only decrease the gain (5). This
causes zeros in the derivative ⭸兩T( j웆)兩/⭸L, C at all the attenu-
ation zeros, and keeps low the error in all the passband. Table
2 lists polynomials, poles, frequency, and Q of the poles, and
values for LC doubly terminated ladder structures, with the
structure shown in Fig. 4(a), for some normalized Chebyshev
low-pass filters. Note in the realizations that odd-order filters
have identical terminations, but even-order filters require dif-
ferent terminations, because there is no maximum power
transfer at 웆 ⫽ 0, since the gain is not maximum there. With
the impedance normalization shown, it is clear that the even-
order realizations have antimetrical structure (one side is the
dual of the other). The odd-order structures are symmetrical.
THE INVERSE CHEBYSHEV LOW-PASS APPROXIMATION
This normalized inverse Chebyshev approximation is the
most important member of the inverse polynomial class of ap-
proximations. It is conveniently obtained by using the charac-
teristic function obtained from
F( jω) γ γ ωn
K( jω) = = = n (19)
P( jω) Cn (1/ω) ω Cn (1/ω)
where ⑀ and 웂 are given by Eqs. (10) and (11). The polynomi-
als F(s) and P(s) are then
F (s) = γ (s/ j)n
(20)
P(s) = (s/ j) Cn ( j/s)
n
Ignoring ⫾j or ⫺1 multiplying factors in Eq. (20) and renor-
malizations, F(s) reduces to ⑀웂 sn, and P(s) to a Chebyshev
polynomial with all the terms positive and the coefficients in
reverse order. The magnitude characteristic of this approxi-
mation is maximally flat at 웆 ⫽ 0, due to the n attenuation
zeros at s ⫽ 0, and so is similar in the passband to a Butter-
worth approximation. In the stopband, it presents a series of
transmission zeros at frequencies that are the inverse of the
roots of the corresponding Chebyshev polynomial. Between
adjacent transmission zeros, there are gain maxima reaching
the magnitude of ⫺Amin dB. Without a renormalization, the
stopband starts at 1 rad/s, and the passband ends where the
magnitude of the characteristic function, Eq. (19), reaches ⑀:
1 1
ω p = −1 =
−1
 (21)
Cn (γ ) cosh n1 cosh γ
Odd-order filters present a single transmission zero at
infinity, and even-order filters end up with a constant gain
⫺Amin at 웆 ⫽ 앝. From Eqs. (1) and (19), the attenuation in
decibels for a normalized inverse Chebyshev approximation is
  2 
γ
A(ω) = 10 log 1 + (22)
Cn (1/ω)
The gains for some normalized inverse Chebyshev approxima-
tions are plotted in Fig. 5. A frequency scaling by the inverse
of the factor given by Eq. (21) was applied to make the pass-
band end at 웆 ⫽ 1.
The selectivity of the inverse Chebyshev approximation is
the same as the corresponding Chebyshev approximation, for
the same Amax and Amin. This can be verified by calculating the
ratio 웆p /웆r for both approximations. For the normalized Che-
byshev approximation, 웆p ⫽ 1, and 웆r occurs when ⑀Cn(웆r) ⫽
웂. For the normalized inverse Chebyshev approximation, 웆r ⫽
1, and 웆p occurs when (⑀웂)/Cn(1/웆p) ⫽ ⑀. In both cases, the
resulting ratio is 웆r /웆p ⫽ C⫺1
n (웂). Equation (11) can be used to
compute the required degree.
The transmission zero frequencies are the frequencies that
make Eq. (19) infinite:
Cn (1/ωk ) = cos(n cos−1 (1/ωk )) = 0 )
1
ωk =
π 1 + 2k
, k = 0, 1, . . ., n − 1 (23)
cos
2 n
The pole frequencies are found by solving Eq. (2) with F(s)
and P(s) given by Eq. (20):

s 2n
s 2n
j 2
E(s)E(−s) = (γ )2 + Cn (24)
j j s
The roots of this equation are the solutions of

j
Cn = ± jγ (25)
s
By observing the similarity of this equation to Eq. (14), the
roots of E(s)E(⫺s) can be obtained as the complex inverses of
the values given by Eq. (18), with ⑀ replaced by 1/(⑀웂). They
lie on a curve that is not an ellipse. E(s) is constructed from
the roots with negative real parts, which are distributed in
a pattern that resembles a circle shifted to the left side of
the origin.
The similarity of the passband response to the Butter-
worth response makes the phase characteristics of the inverse
Chebyshev filters much closer to linear than those of the
Chebyshev filters. The Qs of the poles are also significantly
lower for the same gain specifications.
REALIZATION OF INVERSE CHEBYSHEV FILTERS
The realization based on LC doubly terminated ladder struc-
tures is also convenient for inverse Chebyshev filters for the
same reasons mentioned for the direct approximation. In this
case, the passband sensitivities are low due to the nth-order
attenuation zero at s ⫽ 0, which results in nullification of the
first n derivatives of the filter gain in relation to all the reac-
tive elements at s ⫽ 0 and keeps the gain errors small in
all the passband. Stopband errors are also small, because the
transmission zero frequencies depend only on simple LC se-
ries or parallel resonant circuits. The usual structures used
are shown in Fig. 4(b).
Those realizations are possible only for the odd-order
cases, because those structures cannot realize the constant
gain at infinity that occurs in the even-order approximations
(realizations with transformers or with negative elements are
possible). Even-order modified approximations can be ob-
tained by using, instead of the Chebyshev polynomials, poly-
 CHEBYSHEV FILTERS 271

Table 2. Normalized Chebyshev Filters with Amax ⴝ 1 dB

Polynomials E(s)
n a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10
1 1.96523 1.00000
2 1.10251 1.09773 1.00000
3 0.49131 1.23841 0.98834 1.00000
4 0.27563 0.74262 1.45392 0.95281 1.00000
5 0.12283 0.58053 0.97440 1.68882 0.93682 1.00000
6 0.06891 0.30708 0.93935 1.20214 1.93082 0.92825 1.00000
7 0.03071 0.21367 0.54862 1.35754 1.42879 2.17608 0.92312 1.00000
8 0.01723 0.10734 0.44783 0.84682 1.83690 1.65516 2.42303 0.91981 1.00000
9 0.00768 0.07060 0.24419 0.78631 1.20161 2.37812 1.88148 2.67095 0.91755 1.00000
10 0.00431 0.03450 0.18245 0.45539 1.24449 1.61299 2.98151 2.10785 2.91947 0.91593 1.00000
Poles
n re/im 1 웆/Q 1 re/im 2 웆/Q 2 re/im 3 웆/Q 3 re/im 4 웆/Q 4 re/im 5 웆/Q 5
1 ⫺1.96523
2 ⫺0.54887 1.05000
0.89513 0.95652
3 ⫺0.24709 0.99710 ⫺0.49417
0.96600 2.01772
4 ⫺0.13954 0.99323 ⫺0.33687 0.52858
0.98338 3.55904 0.40733 0.78455
5 ⫺0.08946 0.99414 ⫺0.23421 0.65521 ⫺0.28949
0.99011 5.55644 0.61192 1.39879
6 ⫺0.06218 0.99536 ⫺0.16988 0.74681 ⫺0.23206 0.35314
0.99341 8.00369 0.72723 2.19802 0.26618 0.76087
7 ⫺0.04571 0.99633 ⫺0.12807 0.80837 ⫺0.18507 0.48005 ⫺0.20541
0.99528 10.89866 0.79816 3.15586 0.44294 1.29693
8 ⫺0.03501 0.99707 ⫺0.09970 0.85061 ⫺0.14920 0.58383 ⫺0.17600 0.26507
0.99645 14.24045 0.84475 4.26608 0.56444 1.95649 0.19821 0.75304
9 ⫺0.02767 0.99761 ⫺0.07967 0.88056 ⫺0.12205 0.66224 ⫺0.14972 0.37731 ⫺0.15933
0.99723 18.02865 0.87695 5.52663 0.65090 2.71289 0.34633 1.26004
10 ⫺0.02241 0.99803 ⫺0.06505 0.90245 ⫺0.10132 0.72148 ⫺0.12767 0.47606 ⫺0.14152 0.21214
0.99778 22.26303 0.90011 6.93669 0.71433 3.56051 0.45863 1.86449 0.15803 0.74950
Polynomials P(s)
n Multiplier a0
1 1.96523 1.00000
2 0.98261 1.00000
3 0.49131 1.00000
4 0.24565 1.00000
5 0.12283 1.00000
6 0.06141 1.00000
7 0.03071 1.00000
8 0.01535 1.00000
9 0.00768 1.00000
10 0.00384 1.00000
Doubly terminated LC ladder realizations
n Rg/Rl L/C1 L/C2 L/C3 L/C4 L/C5 L/C6 L/C7 L/C8 L/C9 L/C10
1 1.00000
1.00000 1.01769
2 1.63087 1.11716
0.61317 1.11716
3 1.00000 0.99410
1.00000 2.02359 2.02359
4 1.63087 1.73596
0.61317 1.28708 1.73596 1.28708
5 1.00000 1.09111
1.00000 2.13488 3.00092 1.09111 2.13488
6 1.63087 1.80069 1.87840 1.32113
0.61317 1.32113 1.87840 1.80069
7 1.00000 1.11151 1.17352 1.11151
1.00000 2.16656 3.09364 3.09364 2.16656
8 1.63087 1.82022 1.93073 1.90742 1.33325
0.61317 1.33325 1.90742 1.93073 1.82022
9 1.00000 1.11918 1.18967 1.18967 1.11918
1.00000 2.17972 3.12143 3.17463 3.12143 2.17972
10 1.63087 1.82874 1.94609 1.95541 1.91837 1.33890
0.61317 1.33890 1.91837 1.95541 1.94609 1.82874
272 CHEBYSHEV FILTERS

nomials obtained by the application, to the Chebyshev polyno- |T( jω)|dB

mials, of the Moebius transformation (4,6):
0 1
0 ω
x 2
− x2z1 kmaxπ
x →
2
; xz1 = cos (26) 10
1 − x2z1 2n 2
1

where kmax is the greatest odd integer that is less than the
filter order n. This transformation moves the pair of roots
–1
closest to the origin of an even-order Chebyshev polynomial
to the origin. If the resulting polynomials are used to generate
polynomial approximations, starting from Eq. (7), the results (a)
are filters with two attenuation zeros at the origin, which are |T( jω)|dB
realizable as doubly terminated ladder filters with equal ter- 1 100
minations, a convenience in passive realizations. If the same 0 ω
polynomials are used in inverse polynomial approximations, –1
starting from Eq. (19), the results are filters with two trans-
mission zeros at infinity, which now are realizable by doubly
terminated LC structures. The direct and inverse approxima- 1
tions obtained in this way have the same selectivity, slightly
smaller than in the original case.
Table 3 lists polynomials, poles, zeros, frequency and Q of 6
the poles, and LC doubly terminated realizations for some in-
verse Chebyshev filters. The filters were scaled in frequency
to make the passband end at 1 rad/s. The even-order realiza-
tions are obtained from modified approximations and are
listed separately in Table 4. The structures are a mix of the
two forms in Fig. 5(b). Note that some realizations are miss-
ing. These are cases where the zero-shifting technique for the
realization of LC doubly terminated ladder filters fails. For
inverse Chebyshev filters, and other inverse polynomial fil-
ters, there is a minimum value of Amin for each order that –100
makes the realization in this form possible (7). (b)

Figure 5. Passband gain (a) and stopband gain (b) for the first nor-
malized inverse Chebyshev approximations with Amax ⫽ 1 dB and
Amin ⫽ 50 dB. Observe the maximally flat passband and the uniform
Rg L2 Ln stopband ripple.

Rl Rl
C1 C3 Cn
OTHER SIMILAR APPROXIMATIONS
(a)
Different approximations with uniform passband or stopband
L2
ripple, somewhat less selective, can be generated by reducing
Rg the number or the amplitude of the oscillations in a Cheby-
shev-like polynomial and generating the approximations
Rl starting from Eqs. (7) or (19) numerically (8).
C1 C2 C3 Cn A particularly interesting case results if the last oscilla-
tions of the polynomial value end in 0 instead of ⫾1. This
creates double roots close to x ⫽ ⫾1 in the polynomial. In
Rg L1 L3 Ln
a polynomial approximation, the higher-frequency passband
minimum disappears, replaced by a second-order maximum
L2 close to the passband border. In an LC doubly terminated re-
Rl alization, the maximum power transfer at this frequency
causes the nullification of the first two derivatives of the gain
C2
in relation to the reactive elements, substantially reducing
the gain error at the passband border. In an inverse polyno-
(b) mial approximation, this causes the joining of the first two
Figure 4. LC doubly terminated ladder realizations for Chebyshev transmission zeros, as a double transmission zero, which in-
filters, in the direct form (a), and in the inverse form (b). These classi- creases the attenuation and reduces the error at the begin-
cal realizations continue to be the best prototypes for active realiza- ning of the stopband, allowing also symmetrical realizations
tions, due to their low sensitivity to errors in element values. for orders 5 and 7.
 CHEBYSHEV FILTERS 273

Table 3. Normalized Inverse Chebyshev Filters with Amax ⴝ 1 dB and Amin ⴝ 50 dB

Polynomials E(s)
n a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10
1 1.96523 1.00000
2 1.96838 1.98099 1.00000
3 2.01667 3.14909 2.51015 1.00000
4 2.19786 4.52937 4.90289 3.13118 1.00000
5 2.60322 6.42983 8.61345 7.26320 3.81151 1.00000
6 3.35081 9.35051 14.61162 14.91369 10.30744 4.54023 1.00000
7 4.64002 14.09440 24.72451 29.03373 24.18372 14.09633 5.30979 1.00000
8 6.82650 22.03426 42.29782 55.31092 52.89124 37.20009 18.68307 6.11268 1.00000
9 10.54882 35.60372 73.49954 104.6829 111.4815 90.07839 54.81844 24.10445 6.94337 1.00000
10 16.95789 59.19226 129.8094 198.2422 230.3472 207.4480 145.4877 77.89699 30.39330 7.79647 1.00000
Poles
n re/im 1 웆/Q 1 re/im 2 웆/Q 2 re/im 3 웆/Q 3 re/im 4 웆/Q 4 re/im 5 웆/Q 5
1 ⫺1.96523

2 ⫺0.99049 1.40299
0.99363 0.70823
3 ⫺0.61468 1.25481 ⫺1.28079
1.09395 1.02071
4 ⫺0.42297 1.18385 ⫺1.14262 1.25229
1.10571 1.39945 0.51249 0.54799
5 ⫺0.30648 1.13993 ⫺0.94418 1.23656 ⫺1.31018
1.09795 1.85969 0.79849 0.65483
6 ⫺0.23016 1.10962 ⫺0.75398 1.21506 ⫺1.28598 1.35770
1.08549 2.41056 0.95283 0.80576 0.43545 0.52789
7 ⫺0.17794 1.08768 ⫺0.59638 1.18959 ⫺1.14085 1.36871 ⫺1.47946
1.07303 3.05632 1.02930 0.99735 0.75619 0.59986
8 ⫺0.47425 1.16431 ⫺0.14101 1.07137 ⫺0.95398 1.34983 ⫺1.48710 1.55173
1.06334 1.22752 1.06205 3.79891 0.95496 0.70747 0.44316 0.52173
9 ⫺0.38185 1.14152 ⫺0.77805 1.31643 ⫺0.11413 1.05899 ⫺1.34453 1.56247 ⫺1.70623
1.07575 1.49471 1.06189 0.84597 1.05282 4.63922 0.79596 0.58105
10 ⫺0.63221 1.27960 ⫺0.31203 1.12193 ⫺0.09407 1.04944 ⫺1.13939 1.53032 ⫺1.72054 1.78611
1.11252 1.01201 1.07766 1.79777 1.04521 5.57772 1.02161 0.67155 0.47954 0.51906
Polynomials P(s)
n Multiplier a0 a2 a4 a6 a8 a10
1 1.96523 1.00000
2 0.00316 622.4562 1.00000
3 0.05144 39.20309 1.00000
4 0.00316 695.0228 74.56663 1.00000
5 0.03477 74.86195 19.34709 1.00000
6 0.00316 1059.620 494.9652 57.80151 1.00000
7 0.03463 133.9940 95.81988 19.57753 1.00000
8 0.00316 2158.727 2130.497 657.0734 64.84805 1.00000
9 0.03786 278.6600 354.3952 150.2380 23.58892 1.00000
10 0.00316 5362.556 8380.916 4584.365 1023.530 79.98165 1.00000
Zeros
n 웆1 웆2 웆3 웆4 웆5
1
2 24.94907
3 6.26124
4 7.97788 3.30455
5 3.74162 2.31245
6 6.92368 2.53424 1.85520
7 3.60546 2.00088 1.60458
8 7.29689 2.56233 1.71209 1.45144
9 3.88896 2.06927 1.53587 1.35062
10 8.08496 2.78589 1.78865 1.41948 1.28053
LC doubly terminated realizations
n Rg/Rl L/C 1 L/C 2 L/C 3 L/C 4 L/C 5 L/C 6 L/C 7 L/C 8 L/C 9 L/C 10
1 1.00000
1.00000 1.01769
3 1.00000 1.56153
1.00000 0.78077 0.01634 0.78077
5 1.00000 1.16364 1.30631
1.00000 0.37813 0.16071 1.62010 0.05468 0.47172
7 1.00000 0.72897 1.34370 0.96491
1.00000 0.09574 0.34265 1.32044 0.28905 1.32059 0.07972 0.30081
274 CHEBYSHEV FILTERS

Table 4. Normalized Even-order Modified Inverse Chebyshev Filters with

Two Transmission Zeros at Infinity, with Amax ⴝ 1 dB and Amin ⴝ 50 dB
Polynomials E(s)
n a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10
2 1.96523 1.98254 1.00000
4 2.12934 4.47598 4.86847 3.12041 1.00000
6 3.14547 9.02141 14.23655 14.65051 10.18872 4.51414 1.00000
8 6.32795 20.98707 40.68275 53.69811 51.69862 36.58972 18.48009 6.07949 1.00000
10 15.69992 56.17036 124.1801 191.3464 223.6989 202.6490 142.8395 76.84994 30.12162 7.76165 1.00000
Poles
n re/im 1 웆/Q 1 re/im 2 웆/Q 2 re/im 3 웆/Q 3 re/im 4 웆/Q 4 re/im 5 웆/Q 5
2 ⫺0.99127 1.40187
0.99127 0.70711
4 ⫺0.43134 1.18419 ⫺1.12886 1.23225
1.10284 1.37268 0.49409 0.54580
6 ⫺0.23626 1.11107 ⫺0.76275 1.20632 ⫺1.25806 1.32324
1.08566 2.35141 0.93457 0.79077 0.41016 0.52590
8 ⫺0.14421 1.07247 ⫺0.48399 1.16315 ⫺0.96075 1.33672 ⫺1.45079 1.50858
1.06273 3.71848 1.05767 1.20162 0.92940 0.69566 0.41357 0.51992
10 ⫺0.64341 1.27784 ⫺0.31781 1.12245 ⫺0.09573 1.05011 ⫺1.14584 1.51514 ⫺1.67803 1.73625
1.10404 0.99303 1.07652 1.76590 1.04574 5.48452 0.99132 0.66115 0.44586 0.51735
Polynomials P(s)
n Multiplier a0 a2 a4 a6 a8
2 1.96523 1.00000
4 0.16412 12.97454 1.00000
6 0.11931 26.36278 10.89186 1.00000
8 0.13145 48.13911 44.73326 12.54437 1.00000
10 0.16119 97.39855 147.0191 76.50032 15.68797 1.00000
Zeros
n 웆1 웆2 웆3 웆4
2
4 3.60202
6 2.69467 1.90542
8 2.71078 1.74464 1.46706
10 2.94484 1.82001 1.43081 1.28694
LC doubly terminated ladder realizations
n Rg/Rl L/C 1 L/C 2 L/C 3 L/C 4 L/C 5 L/C 6 L/C 7 L/C 8
2 1.00000 1.00881
1.00000 1.00881
4 1.00000 1.51207 0.05275 0.58997
1.00000 0.64094 1.46110
6 1.00000 0.87386 1.67233 0.13065 0.32187
1.00000 0.17880 0.31519 1.63514 1.05413
8 1.00000 0.67581 0.32023 1.34317 0.38303 1.12998 0.18178 0.16760
1.00000 0.32898 1.02594 1.21303 0.74862

Other variations arise from the shifting of roots to the ori-
gin. This is also best done numerically. Odd- (even-) order
polynomial approximations with any odd (even) number of at-
tenuation zeros at 웆 ⫽ 0, up to the approximation’s order (in
the last case resulting in a Butterworth approximation), can
be generated. The same polynomials generate inverse polyno-
mial approximations with any odd (even) number of transmis-
sion zeros at infinity.
In all cases, the Q of the poles is reduced and the phase is
closer to linear. Similar techniques can also be applied to el-
liptic approximations. For example, a low-pass elliptic ap-
proximation can be transformed into a Chebyshev approxima-
tion by the shifting of all the transmission zeros to infinity,
or into an inverse Chebyshev approximation by shifting all
the attenuation zeros to the origin. There are many variations
between these extremes.
BIBLIOGRAPHY
1. A. Antoniou, Digital Filters: Analysis, Design, and Applications,
New York: McGraw-Hill, 1993.
2. P. L. Chebyshev, Théorie des mécanismes connus sous le nom de
parallelogrammes, Oeuvres, Vol. I, St. Petersburg, 1899.
3. M. E. Van Valkenburg, Analog Filter Design, New York: Holt,
Rinehart and Winston, 1982.
4. R. W. Daniels, Approximation Methods for Electronic Filter De-
sign, New York: McGraw-Hill, 1974.
5. H. J. Orchard, Inductorless filters, Electronics Lett., 2: 224–225,
1996.
6. G. C. Temes and J. W. LaPatra, Circuit Synthesis and Design,
Tokyo: McGraw-Hill Kogakusha, 1977.
7. L. Weinberg, Network Analysis and Synthesis, New York:
McGraw-Hill, 1962.
 CHEMICAL LASERS 275

8. A. C. M. de Queiroz and L. P. Calôba, An approximation algo-

rithm for irregular-ripple filters, IEEE International Telecommu-
nications Symposium, Rio de Janeiro, Brazil, pp. 430–433, Sep-
tember 1990.

ANTÔNIO CARLOS M. DE QUEIROZ

Federal University of Rio de Janeiro

CHEMICAL INDUSTRY. See PETROLEUM INDUSTRY.

398 CIRCUIT STABILITY

CIRCUIT STABILITY

Stability is a property of well-behaved circuits and systems.

Typically, stability is discussed in terms of feedback systems.
Well-established techniques, such as Nyquist plots, Bode dia-
grams, and root locus plots are available for studying the sta-
bility of feedback systems. Electric circuits can be represented
as feedback systems. Nyquist plots, Bode diagrams, and root
locus plots can then be used to study the stability of electric
circuits.

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.
 CIRCUIT STABILITY 399

FEEDBACK SYSTEMS AND STABILITY vR(s) = –A(s)B(s) vT(s) = 1

Consider a feedback system such as the one shown in Fig. 1.

This feedback system consists of three parts: a forward block,
Summer Foward block
sometimes called the ‘‘plant,’’ a feedback block, sometimes
+
called the ‘‘controller,’’ and a summer. The signals vi(t) and vi(s) = 0 + A(s)
vo(t) are the input and output of the feedback system. A(s) is –
the transfer function of the forward block and B(s) is the
transfer function of the feedback block. The summer subtracts B(s)
the output of the feedback block from vi(t). The transfer func-
tion of the feedback system can be expressed in terms of A(s) Feedback block
and B(s) as Figure 2. Measuring the return difference: The difference between
the test input signal, VT(s), and the test output signal, VR(s), is the
Vo (s) A(s) return difference.
T (s) = = (1)
Vi (s) 1 + A(s)B(s)

Suppose that the transfer functions A(s) and B(s) can each be
expressed as ratios of polynomials in s. Then of the feedback system. Figure 2 shows how the return differ-
ence can be measured. First, the input, vi(t), is set to zero.
NA (s) NB (s) Next, the forward path of the feedback system is broken.
A(s) = and B(s) = (2) Figure 2 shows how a test signal, VT(s)  1, is applied and
DA (s) DB (s)
the response, VR(s)  A(s)B(s), is measured. The difference
between the test signal and its response is the return dif-
where NA(s), DA(s), NB(s), and DB(s) are polynomials in s. Sub- ference.
stituting these expressions into Eq. (1) gives The calculation
NA (s) return difference = 1 +A(s)B(s) =
DA (s) NA (s)DB (s) N(s) NA (s) NB (s) DA (s)DB (s) +NA (s)NB (s)
T (s) = = = 1+ =
NA (s) NB (s) DA (s)DB (s) + NA (s)NB (s) D(s) DA (s) DB (s) DA (s)DB (s)
1+
DA (s) DB (s)
(3)
shows that

where the numerator and denominator of T(s), N(s) and D(s),
are both polynomials in s. The values of s for which N(s)  0
are called the zeros of T(s) and the values of s that satisfy
D(s)  0 are called the poles of T(s).
Stability is a property of well-behaved systems. For exam-
ple, a stable system will produce bounded outputs whenever
its input is bounded. Stability can be determined from the
poles of a system. The values of the poles of a feedback system
will, in general, be complex numbers. A feedback system is
stable when all of its poles have negative real parts.
The equation
1 + A(s)B(s) = 0 (4)
is called the characteristic equation of the feedback system.
The values of s that satisfy the characteristic equation are
poles of the feedback system. The left-hand side of the charac-
teristic equation, 1  A(s)B(s), is called the return difference
Summer Foward block
+ is called the step response. The step response can be calcu-
vi(t) + A(s) vo(t)
Input – Output
signal signal
B(s)
1. The zeros of 1  A(s)B(s) are equal to the poles of T(s).
2. The poles of 1  A(s)B(s) are equal to the poles of
A(s)B(s).
Consider a feedback system of the form shown in Fig. 1
with
s+5 3s
A(s) = and B(s) = (5)
s2 − 4s + 1 s+3
The poles of the forward block are the values of s that satisfy
s2  4s  1  0 (that is, s1  3.73 and s2  0.26). In this case,
both poles have real, rather than complex, values. The for-
ward block would be stable if both poles were negative. They
are not, so the forward block is itself an unstable system. To
see that this unstable system is not well behaved, consider its
step response (1,2). The step response of a system is its zero
state response to a step input. In other words, suppose the
input to the forward block was zero for a very long time. At
some particular time, the value of input suddenly becomes
equal to 1 and remains equal to 1. The response of the system
lated by taking the inverse Laplace transform of A(s)/s. In
this example, the step response of the forward block is
step response = 5 + 0.675e3.73t − 5.675e0.27t

Feedback block
As time increases, the exponential terms of the step response
Figure 1. A feedback system. get very, very large. Theoretically, they increase without
400 CIRCUIT STABILITY

bound. In practice, they increase until the system saturates ber of encirclements of the point 1  j0 by the curve in the
or breaks. This is typical of the undesirable behavior of an A(s)B(s)-plane. Let
unstable system.
According to Eq. (3), the transfer function of the whole N = the number of encirclements, in the clockwise direction,
feedback system is of −1 + j0 by the closed curve in the A(s)B(s)-plane
Z = The number of poles of T (s) in the right half of the s-
s+5 plane
P = The number of poles of A(s)B(s) in the right half of the
T (s) = s2− 4s + 1
s+5 3s s-plane
1+ 2 ×
s − 4s + 1 s + 3
The Nyquist stability criterion states that N, Z, and P are
(s + 5)(s + 3) s2 + 8s + 15 related by
= 2 = 3
(s − 4s + 1)(s + 3) + (s + 5)(3s) s + 2s2 + 4s + 3
Z=P+N
The poles of the feedback system are the values of s that sat-
isfy s3  2s2  4s  3  0—that is, s1  1, s2  0.5  A stable feedback system will not have any poles in the right
j1.66 and s3  0.5  j1.66. The real part of each of these half of the s-plane so Z  0 indicates a stable system.
three poles is negative. Since all of the poles of the feedback For example, suppose the forward and feedback blocks of
system have negative real parts, the feedback system is sta- the feedback system shown in Fig. 1 have the transfer func-
ble. To see that this stable system is well behaved, consider tions described by Eq. (5). Then
its step response. This step response can be calculated by tak-
ing the inverse Laplace transform of T(s)/s. In this example, 3s2 + 15s 3s2 + 15s
A(s)B(s) = =
the step response of the feedback system is s3 − s2 − 11s + 3 (s − 3.73)(s − 0.26)(s + 3)
(7)
√
step response = 5 − 11.09e−t cos( 2t + 63◦ ) Figure 3 shows the Nyquist plot for this feedback system.
This plot was obtained using the MATLAB commands
In contrast to the previous case, as time increases et becomes
num=[0 3
15 0]; %Coefficients of the
zero so the second term of the step response dies out. This
numerator of A(s)B(s)
stable system does not exhibit the undesirable behavior typi- den=[1 -1 -11 3]; %Coefficients of the
cal of unstable systems. denominator of A(s)B(s)
nyquist (num,den)

STABILITY CRITERIA
Frequently, the information about a feedback system that is
most readily available is the transfer functions of the forward
and feedback blocks, A(s) and B(s). Stability criteria are tools
for determining if a feedback system is stable by examining
A(s) and B(s) directly, without first calculating T(s) and then
calculating its poles—that is, the roots of the denominator of
T(s). Two stability criteria will be discussed here: the Nyquist
stability criteria and the use of Bode diagrams to determine
the gain and phase margin.
The Nyquist stability criterion is based on a theorem in the
theory of functions of a complex variable (1,3,4). This stability
criterion requires a contour mapping of a closed curve in the
s-plane using the function A(s)B(s). The closed contour in the
s-plane must enclose the right half of the s-plane and must
not pass through any poles or zeros of A(s)B(s). The result of
Since A(s)B(s) has two poles in the right half of the s-plane,
P  2. The Nyquist plot shows two counterclockwise encircle-
ments of 1  j0 so N  2. Then Z  P  N  0, indicating
that the feedback system is stable.
Feedback systems need to be stable in spite of variations
in the transfer functions of the forward and feedback blocks.
The gain and phase margins of a feedback system give an
indication of how much A(s) and B(s) can change without
causing the system to become unstable. The gain and phase
0.8
0.6
0.4
0.2
Image axis

this mapping is a closed contour in the A(s)B(s)-plane. Fortu-

0
nately, the computer program MATLAB (5,6) can be used to
generate an appropriate curve in the s-plane and do this –0.2
mapping.
Rewriting the characteristic equation, Eq. (4), as –0.4

–0.6
A(s)B(s) = −1 (6)
–0.8
suggests that the relationship of the closed contour in the –1.4 –1.2 –1 –0.8 –0.6 –0.4 –0.2 0
Real axis
A(s)B(s)-plane to the point 1  j0 is important. Indeed, this
is the case. The Nyquist stability criterion involves the num- Figure 3. A Nyquist plot produced using MATLAB.
 CIRCUIT STABILITY 401

margins can be determined using Bode diagrams. To obtain

the Bode diagrams, first let s  j웆 so that Eq. (6) becomes
A circuit consisting of
resistors, capacitors, and +
A( jω)B( jω) = −1 +
vi(t) op amps RL vo(t)
–
The value of A( j웆)B( j웆) will, in general, be complex. –
Two Bode diagrams are used to determine the gain and
phase margins. The magnitude Bode diagram is a plot
of 20 log[兩A( j웆)B( j웆)兩] versus 웆. The units of Figure 5. A circuit that is to be represented as a feedback system.
20 log[兩A( j웆)B( j웆)兩] are decibels. The abbreviation for decibel
is dB. The magnitude Bode diagram is sometimes referred to
as a plot of the magnitude of A( j웆)B( j웆), in dB, versus 웆. The
The gain margin of the feedback system is
phase Bode diagram is a plot of the angle of A( j웆)B( j웆) ver-
sus 웆. 1
It is necessary to identify two frequencies: 웆g, the gain gain margin = (12)
A( jωp ) B( jωp )
crossover frequency, and 웆p, the phase crossover frequency.
To do so, first take the magnitude of both sides of Eq. (7) to
obtain The phase margin is

phase margin = 180◦ − (\ A( jωg ) + \ B( jωg )) (13)

A( jω)B( jω) = 1 (8)

Converting to decibels gives The gain and phase margins can be easily calculated using
MATLAB. For example, suppose the forward and feedback
20 log[ A( jω)B( jω) ] = 0 (9) blocks of the feedback system shown in Fig. 1 have the trans-
fer functions described by Eq. (3). Figure 4 shows the Bode
diagrams for this feedback system. These plots were obtained
Equation (8) or (9) is used to identify a frequency, 웆g, the gain
using the MATLAB commands
crossover frequency. That is, 웆g is the frequency at which
num=[0 3
15 0]; %Coefficients of the
A( jωg ) B( jωg ) = 1 numerator of A(s)B(s)
den=[1 -1 -11 3]; %Coefficients of the
Next, take the angle of both sides of Eq. (4) to denominator of A(s)B(s)
margin (num,den)
\(A( jω)B( jω)) = 180◦ (10)
MATLAB has labeled the Bode diagrams in Fig. 4 to show the
gain and phase margins. The gain margin of 1.331 dB indi-
Equation (10) is used to identify a frequency, 웆p, the gain
cates that a decrease in 兩A(s)B(s)兩 of 1.331 dB or, equivalently,
crossover frequency. That is, 웆p is the frequency at which
a decrease in gain by a factor of 0.858, at the frequency 웆p 
\ A( jωp ) + \ B( jωp ) = 180◦ (11) 1.378 rad/s, would bring the system the boundary of instabil-
ity. Similarly, the phase margin of 11.6 indicates that an in-
crease in the angle of A(s)B(s) of 11.6, at the frequency 웆g 
2.247 rad/s, would bring the system the boundary of insta-
Gm = –1.311 dB, ( = 1.378) Pm = 11.62 ( = 2.247) bility.
When the transfer functions A(s) and B(s) have no poles or
20
zeros in the right half of the s-plane, then the gain and phase
margins must both be positive in order for the system to be
Gain (dB)

–20

–40
10–2 10–1 100 101 102
+
Frequency (rad/s) NB
vi(t) + RL vo(t)
–
0
–
Phase (deg)

–90
–180
The rest of –
–270
the circuit +
–360
10–2 10–1 100 101 102
Frequency (rad/s) an op amp

Figure 4. Bode plot used to determine the phase and gain margins. Figure 6. Identifying the subcircuit NB by separating an op amp
The plots were produced using MATLAB. from the rest of the circuit.
402 CIRCUIT STABILITY

model of the op amp indicates that the op amp input and out-
put voltages are related by
+
NB
+ VB (s) = K(s)VA (s) (14)
vi(s) – RL vo(s)
–
The network NB can be represented by the equation




Vo (s) T11 (s) T12 (s) Vi (s)
= (15)
VA (s) T21 (s) T22 (s) VB (s)
+

vA(s) + v (s) = K(s) v (s)

– B A Combining Eqs. (14) and (15) yields the transfer function of
– the circuit

Vo (s) T (s)K(s)T21 (s)

T (s) = = T11 (s) + 12 (16)
Vi (s) 1 − K(s)T22 (s)
Figure 7. Replacing the op amp with a model of the op amp.
or

stable. As a rule of thumb (7), the gain margin should be
greater than 6 dB and the phase margin should be between
30 and 60. These gain and phase margins provide some pro-
tection against changes in A(s) or B(s).
STABILITY OF LINEAR CIRCUITS
The Nyquist criterion and the gain and phase margin can be
used to investigate the stability of linear circuits. To do so
requires that the parts of the circuit corresponding to the for-
ward block and to the feedback block be identified. After this
identification is made, the transfer functions A(s) and B(s) can
be calculated.
Figures 5–8 illustrate a procedure for finding A(s) and
B(s) (8). For concreteness, consider a circuit consisting of re-
sistors, capacitors, and op amps. Suppose further that the in-
put and outputs of this circuit are voltages. Such a circuit is
shown in Fig. 5. In Fig. 6 one of the op amps has been sepa-
rated from the rest of the circuit. This is done to identify the
subcircuit NB. The op amp will correspond to the forward
block of the feedback system while NB will contain the feed-
back block. NB will be used to calculate B(s). In Fig. 7, the op
amp has been replaced by a model of the op amp (2). This
Vo (s) T (s)(1 + K(s)T22 (s)) + T12 (s)K(s)T21 (s)
T (s) = = 11
Vi (s) 1 + K(s)T22 (s)
Equation (15) suggests a procedure that can be used to
measure or calculate the transfer functions T11(s), T12(s),
T21(s, and T22(s). For example, Eq. (15) says that when Vi(s) 
1 and VB(s)  0, then Vo(s)  T11(s) and VA(s)  T21(s). Figure
8 illustrates this procedure for determining T11(s) and T21(s).
A short circuit is used to make VB(s)  0 and the voltage
source voltage is set to 1 so that Vi(s)  1. Under these condi-
tions the voltages Vo(s) and VA(s) will be equal to the transfer
functions T11(s) and T21(s). Similarly, when Vi(s)  0 and
VB(s)  1, then Vo(s)  T12(s) and VA(s)  T22(s). Figure 9 illus-
trates the procedure for determining T12(s) and T22(s). A short
circuit is used to make Vi(s)  0 and the voltage source volt-
age is set to 1 so that VB1(s)  1. Under these conditions the
voltages Vo(s) and VA(s) will be equal to the transfer functions
T11(s) and T21(s).
Next, consider the feedback system shown in Fig. 10. (The
feedback system shown in Fig. 1 is part, but not all, of the
feedback system shown in Fig. 10. When D(s)  0, C1(s)  1
and C2(s)  1; then Fig. 10 reduces to Fig. 1. Considering the
system shown in Fig. 10, rather than the system shown in

+ +
NB NB
+ Vo(s) = Vo(s) =
Vi(s) = 1 – RL Vi(s) = 0 RL T12(s)
T11(s)
– –

+ +

VA(s) = T21(s) VB(s) = 0 VA(s) = T22(s) + VB(s) = 1

–
– –

Figure 8. The subcircuit NB is used to calculate T12(s) and T22(s). Figure 9. The subcircuit NB is used to calculate T11(s) and T21(s).
 CIRCUIT STABILITY 403

D(s)

+
+ +
vi(t) C1(s) + A(s) C2(s) + vo(t)

B(s) Figure 10. A feedback system that corresponds to

a linear system.

Fig. 1, avoids excluding circuits for which D(s) ⬆ 0, C1(s) ⬆ 1, As an example, consider the Sallen–Key bandpass filter (9)
or C2(s) ⬆ 1.) The transfer function of this feedback system is shown in Fig. 11. The transfer function of this filter is

Vo (s) C (s)A(s)C2 (s) Vo (s) 5460s

T (s) = = D(s) + 1 (17) T (s) = = 2 (19)
Vi (s) 1 + A(s)B(s) Vi (s) s + 199s + 4 × 106

or The first step toward identifying A(s) and B(s) is to separate

the op amp from the rest of the circuit, as shown in Fig. 12.
Vo (s) D(s)(1 + A(s)B(s)) + C1 (s)A(s)C2 (s) Separating the op amp from the rest of the circuit identifies
T (s) = = the subcircuit NB. Next, NB is used to calculate the transfer
Vi (s) 1 + A(s)B(s)
functions T11(s), T12(s), T21(s), and T22(s). Figure 13 corresponds
to Fig. 8 and shows how T12(s) and T22(s) are calculated. Anal-
Comparing Eqs. (16) and (17) shows that
ysis of the circuit shown in Fig. 13 gives

A(s) = −K(s) (18a)

0.259s2 + 51.6s + 1.04 × 106
B(s) = T22 (s) (18b) T12 (s) = 1 and T22 (s) = (20)
s2 + 5660s + 4 × 106
C1 (s) = T12 (s)
C2 (s) = T21 (s) (The computer program ELab, Ref. 10, provides an alterna-
D(s) = T11 (s) tive to doing this analysis by hand. ELab will calculate the
transfer function of a network in the form shown in Eq. (16)—
that is, as a symbolic function of s. ELab is free and can be
Finally, with Eqs. (18a) and (18b), the identification of A(s) downloaded from http://sunspot.ece.clarkson.edu:1050/
and B(s) is complete. In summary, 앑svoboda/software.html on the World Wide Web.)
Figure 14 corresponds to Fig. 9 and shows how T11(s) and
1. The circuit is separated into two parts: an op amp and T21(s) are calculated. Analysis of the circuit shown in Fig. 14
NB, the rest of the circuit. gives
2. A(s) is open-loop gain of the op amp, as shown in Fig. 7.
−1410s
3. B(s) is determined from the subcircuit NB, as shown in T11 (s) = 0 and T21 (s) = (21)
Fig. 9. s2 + 5660s + 4 × 106

R3 R1 R3 +
C2 vi(t) + R4
– vo(t)
+ C2
–
R1 – +
vi(t) +
– vo(t) R2 R5
R4 C1
––

C1 R2

R5
–
+
Rb

An op amp
Figure 11. A Sallen-Key bandpass filter. R1  R2  R3  R5  7.07
k, R4  20.22 k, and C1  C2  0.1 애F. Figure 12. Identifying the subcircuit NB by separating an op amp
from the rest of the circuit.
404 CIRCUIT STABILITY

example, when the op amp is a 애A741 op amp, then Ao 

200,000 and B  2앟 ⴱ 106 rad/s, so
R1 R3 +
Vi(s) = 1 + R4
– C2 Vo(s) = T11(s) 200, 000
– K(s) = −
s + 31.4
C1 R2 R5
Equation (18) indicates that A(s)  K(s) and B(s) 
T22(s), so in this example

200, 000

s2 + 51.6s + 1.04 × 106 
A(s) = and B(s) = 0.259
s + 31.4 s2 + 5600s + 4 × 106
+
NB
To calculate the phase and gain margins of this filter, first
VA(s) = T21(s) VB(s) = 0 calculate
_
51, 800(s2 + 51.6s + 1.04 × 106 )
A(s)B(s) =
s3 + 5974s2 + 5777240s + 1246 × 106
Figure 13. The subcircuit NB1 is used to calculate T11(s) and T21(s).
Next, the MATLAB commands
num=20000*[0 0.259 51.6 1040000];
Substituting Eqs. (20) and (21) into Eq. (16) gives %Numerator Coefficients

−1410s
 den=[1 5974 5777240 1256*10^6];
%Denominator Coefficients
K(s)
s2 + 5660s + 4 × 106 margin(num,den)
T (s) =
0.259s2 + 51.6s + 1.04 × 106  (22)
1 − K(s) are used to produce the Bode diagram shown in Fig. 15. Fig-
s2 + 5660s + 4 × 106 ure 15 shows that the Sallen–Key filter will have an infinite
gain margin and a phase margin of 76.5 when a 애A741 op
When the op amp is modeled as an ideal op amp, K(s) 씮 앝 amp is used.
and Eq. (22) reduces to Eq. (19). This is reassuring but only
confirms what was already known. Suppose that a more accu-
OSCILLATORS
rate model of the op amp is used. A frequently used op amp
model (2) represents the gain of the op amp as
Oscillators are circuits that are used to generate a sinusoidal
Ao output voltage or current. Typically, oscillators have no input.
K(s) = − (23) The sinusoidal output is generated by the circuit itself. This
B
s+ section presents the requirements that a circuit must satisfy
Ao
if it is to function as an oscillator and shows how these re-
quirements can be used to design the oscillator.
where Ao is the dc gain of the op amp and B is the gain-band-
To begin, recall that the characteristic equation of a circuit
width product of the op amp (2). Both Ao and B are readily
is
available from manufacturers specifications of op amps. For
1 + A(s)B(s) = 0

Suppose this equation is satisfied by a value of s of the form

s  0  j웆o. Then
R1 R3 +
◦
Vi(s) = 0 R4 A( jωo )B( jωo ) = −1 = 1e j180 (24)
Vo(s) = T12(s)
C2
–
In this case, the steady-state response of the circuit will con-
R5 tain a sustained sinusoid at the frequency 웆o (11). In other
C1 R2 words, Eq. (24) indicates that the circuit will function as an
oscillator with frequency 웆o when A( j웆o)B( j웆o) has a magni-
tude equal to 1 and a phase angle of 180.
As an example, consider using Eq. (24) to design the Wien-
NB bridge oscillator, shown in Fig. 16, to oscillate at 웆o  1000
+ rad/s. The first step is to identify A(s) and B(s) using the pro-
VA (s) = T22(s) + V (s) = 1
B
– cedure described in the previous section. In Fig. 17 the ampli-
– fier is separated from the rest of the network to identify the
subcircuit NB. Also, from Eqs. (14) and (18),

Figure 14. The subcircuit NB is used to calculate T12(s) and T22(s). A(s) = −K
 CIRCUIT STABILITY 405

Gm = Inf dB, () = (NaN) Pm = 76.51 () = (1961)

50
Gain (dB)

–50
101 102 103 104 105

Frequency (rad/s)
0

–90
Phase (deg)

–180

–270

–360 Figure 15. The Bode diagrams used to determine the

101 102 103 104 105 phase and gain margins of the Sallen–Key bandpass
Frequency (rad/s) filter.

Next, the subcircuit NB is used to determine B(s)  T22(s), as

R C shown in Fig. 18. From Fig. 18 it is seen that
1
∗R
Cs
1
K +R
+ T22 (s) = Cs =
1


∗R

1
RL Cs 1
 1
R+
R C vo(t)
1
+ R+
Cs 1+ R+
1

Cs1

+R Cs
–
Cs R∗
Cs

=
1
1

1
= 1
1
Figure 16. A Wien-bridge oscillator. 1+ R+ Cs + 3 + RCs +
Cs R RCs

R C
R C

+
+
R C R C
Vo(s) Vo(s) = T12(s)
– –

NB NB
+
K
+ + VA(s) = T22(s)
VA(s) VB(s) – +
– VB(s) = 1
– –

Figure 17. The amplifier is separated from the rest of the Wien- Figure 18. The subcircuit NB is used to calculate B(s)  T22(s) for
bridge oscillator to identify the subcircuit NB. the Wien-bridge oscillator.
406 CIRCUIT STABILITY

so 6

−K
A(s)B(s) = 4
1
3 + RCs +
RCs
2
Now let s  0  j웆o to get

Imag axis
−K 0
A( jωo )B( jωo ) = (25)
1
3 + jωo RC − j
ωo RC –2

The phase angle of A( j웆o)B( j웆o) must be 180 if the circuit is

to function as an oscillator. That requires –4

1 1
jωo RC − j = 0 ⇒ ωo = (26) –6
ωo RC RC –6 –4 –2 0 2 4 6
Real axis
Oscillation also requires that the magnitude of A( j웆o)B( j웆o)
Figure 19. A root locus plot produced using MATLAB. The poles of
be equal to 1. After substituting Eq. (26) into Eq. (25), this
A(s) are marked by x’s and the zeros of A(s) are marked by o’s. As K
requirement reduces to increases from zero to infinity, the poles of T(s) migrate from the poles
of A(s) to the zeros of A(s) along the paths indicated by solid lines.
K=3

That is, the amplifier gain must be set to 3. Design of the

oscillator is completed by picking values of R and C to make
pose that the forward and feedback blocks in Fig. 1 are de-
웆o  1000 rad/s (e.g., R  10 k and C  0.1 애F).
scribed by

THE ROOT LOCUS s(s − 2) s2 − 2s

A(s) = = 3 and B(s) = K
(s + 1)(s + 2)(s + 3) s + 6s2 + 11s + 6
Frequently the performance of a feedback system is adjusted
by changing the value of a gain. For example, consider the The root locus plot for this system is obtained using the
feedback system shown in Fig. 1 when MATLAB (5,6) commands

NA (s) num=([0 1 -2 0]);

A(s) = and B(s) = K (27) den=([1 6 11 6]);
DA (s)
rlocus(num, den)
In this case, A(s) is the ratio of two polynomials in s and This root locus plot is shown in Fig. 19. After the root locus
B(s) is the gain that is used to adjust the system. The transfer has been plotted, the MATLAB command
function of the feedback system is
rlocfind(num, den)
NA (s) N(s) can be used to find the value of the gain K corresponding to
T (s) = = (28)
DA (s) + KNA (s) D(s) any point on the root locus. For example, when this command
is given and the cursor is placed on the point where the locus
The poles of feedback system are the roots of the polynomial crosses the positive imaginary axis, MATLAB indicates that

D(s) = DA (s) + KNA (s) (29)

Suppose that the gain K can be adjusted to any value between x

0 and 앝. Consider the extreme values of K. When K 0,
D(s)  DA(s) so the roots of D(s) are the same as the roots of
DA(s). When K  앝, DA(s) is negligible compared to KNA(s).
Therefore D(s)  KNA(s) and the roots of D(s) are the same as +
the roots of NA(s). Notice that the roots of DA(s) are the poles
of A(s) and the roots of NA(s) are the zeros of A(s). As K varies +
vi(t) vo(t)
from 0 and 앝, the poles of T(s) start at the poles of A(s) and –
migrate to the zeros of A(s). The root locus is a plot of the –
paths that the poles of T(s) take as they move across the s-
plane from the poles of A(s) to the zeros of A(s).
A set of rules for constructing root locus plots by hand are Figure 20. A single device is separated from the rest of the network.
available (1,4,7,13). Fortunately, computer software for con- The parameter associated with this device is called x. The transfer
structing root locus plots is also available. For example, sup- function of the network will be a bilinear function of x.
 CIRCUIT STABILITY 407

× 104 then the transfer function of this Sallen–Key filter is

1

0.8 K(1414s)
T (s) =
s2 + (4 − K)(1414s) + 4 × 106
0.6 (32)
K(1414s)
= 2
0.4 (s + 5656s + 4 × 106 ) + K(−1414s)

0.2
As expected, this transfer function is a bilinear function the
Imag axis

0 gain K. Comparing Eqs. (30) and (32) shows that E(s)  0,

F(s)  1414s, G(s)  s2  5656s  4
105, and H(s) 
–0.2 1414s. The root locus describing the poles of the filter is
–0.4 obtained using the MATLAB commands

–0.6 G=([1 5656 4*10^6]);

H=([0 -1414 0]);
–0.8 rlocus(H,G)
–1 Figure 21 shows the resulting root locus plot. The poles move
–1 –0.5 0 0.5 1
Real axis × 104
into the right half of the s-plane, and the filter becomes unsta-
ble when K  4.
Figure 21. This root locus plot shows that the poles of the Sallen–
Key bandpass filter move into the right of the s-plane as the gain in-
creases. BIBLIOGRAPHY

1. R. C. Dorf and R. H. Bishop, Modern Control Systems, 7th ed.,

gain corresponding to the point 0.0046  j0.7214 is K 
5.2678. For gains larger than 5.2678, two poles of T(s) are in
the right half of the s-plane so the feedback system is un-
stable.
The bilinear theorem (12) can be used to make a connec-
tion between electric circuits and root locus plots. Consider
Fig. 20, where one device has been separated from the rest of
a linear circuit. The separated device could be a resistor, a
capacitor, an amplifier, or any two-terminal device (12). The
separated device has been labeled as x. For example, x could
be the resistance of a resistor, the capacitance of a capacitor,
or the gain of an amplifier. The bilinear theorem states that
the transfer function of the circuit will be of the form
Vo (s) E(s) + xF (s) N(s)
T (s) = = =
Vi (s) G(s) + xH(s) D(s)
Reading, MA: Addison-Wesley, 1995.
2. R. C. Dorf and J. A. Svoboda, Introduction to Electric Circuits,
New York: Wiley, 1996.
3. R. V. Churchill, J. W. Brown, and R. F. Verhey, Complex Vari-
ables and Applications, New York: McGraw-Hill, 1974.
4. S. M. Shinners, Modern Control System Theory and Design, New
York: Wiley, 1992.
5. R. D. Strum and D. E. Kirk, Contemporary Linear Systems using
MATLAB, Boston: PWS, 1994.
6. N. E. Leonard and W. S. Levine, Using MATLAB to Analyze and
Design Control Systems, Redwood City, CA: Benjamin Cum-
mings, 1995.
7. K. Ogata, Modern Control Engineering, Englewood Cliffs, NJ:
Prentice Hall, 1970.
8. J. A. Svoboda and G. M. Wierzba, Using PSpice to determine the
(30) relative stability of RC active filters, International Journal on
Electronics, 74 (4): 593–604, 1993.

where E(s), F(s), G(s), and H(s) are all polynomials in s. A
transfer function of this form is said to be a bilinear function
of the parameter x since both the numerator and denominator
polynomials are linear functions of the parameter x. The poles
of T(s) are the roots of the denominator polynomial
D(s) = G(s) + xH(s)
As x varies from 0 to 앝, the poles of T(s) begin at the roots of
G(s) and migrate to the roots of H(s). The root locus can be
used to display the paths that the poles take as they move
from the roots of G(s) to the roots of H(s). Similarly, the root
locus can be used to display the paths that the zeros of T(s)
take as they migrate from the roots of E(s) to the roots of
F(s).
For example, consider the Sallen–Key bandpass filter
shown in Fig. 11. When
9. F. W. Stephenson, RC Active Filter Design Handbook, New York:
Wiley, 1985.
10. J. A. Svoboda, ELab, A circuit analysis program for engineering
education, Comput. Applications in Eng. Education, 5: 135–149,
1997.
11. W.-K. Chen, Active Network and Feedback Amplifier Theory, New
York: McGraw-Hill, 1980.
(31)
12. K. Gehler, Theory of Tolerances, Budapest, Hungary: Akademiai
Kiado, 1971.
13. A. Budak, Passive and Active Network Synthesis, Prospect
Heights, IL: Waveland Press, 1991, Chap. 6.
Reading List
P. Gray and R. Meyer, Analysis and Design of Analog Integrated Cir-
cuits, 3rd ed., New York: Wiley, 1993, Chaps. 8 and 9.
A. Sedra and K. Smith, Microelectronic Circuits, 4th Ed., Oxford: Ox-
ford University Press, 1998, Chap. 8.

R4
R1 = R2 = R3 = 7.07 k, C1 = C2 = 0.1 µF, and K = 1 + JAMES A. SVOBODA
R5 Clarkson University
420 CIRCUIT TUNING

CIRCUIT TUNING

Circuit tuning refers to the process of adjusting the values of

electronic components in a circuit to ensure that the fabri-
cated or manufactured circuit performs to specifications. In
digital circuits, where signals are switched functions in the
time domain and correct operation depends largely on the ac-
tive devices switching all the way between their ON and OFF
states, tuning in the sense discussed in this chapter is rarely
necessary. In analog continuous-time circuits, however, sig-
nals are continuous functions of time and frequency so that
circuit performance depends critically on the component val-
ues. Consequently, in all but the most undemanding applica-
tions with wide tolerances, correct circuit operation almost
always requires some form of tuning. Naturally, components
could be manufactured with very tight tolerances, but the re-
sulting fabrication costs would become prohibitive. In prac-
tice, therefore, electronic components used in circuit design
are never or only rarely available as accurately as the nomi-
nal design requires, so we must assume that they are affected
by fabrication and manufacturing tolerances. Furthermore,
regardless of whether a circuit is assembled in discrete form
with discrete components on a printed circuit board (as a hy-
brid circuit), or in integrated form on an integrated circuit
chip, the circuit will be affected by parasitic components and
changing operating conditions, all of which contribute to inac-
curate circuit performance. Consider, for example, the re-
quirement of implementing as a hybrid circuit a time of 1 s
for a timer circuit via an RC time constant ␶ ⫽ RC with an
accuracy of 0.1%. Assume that R and C are selected to have
the nominal values R ⫽ 100 k⍀ and C ⫽ 10 애F, that inexpen-
sive chip capacitors with ⫾20% tolerances are used, and that
the desired fabrication process of thin-film resistors results in
components with ⫾10% tolerances. The fabricated time con-
stant can therefore be expected to lie in the range

0.68 s ≤ τ = 100 k(1 ± 0.1)10 µF(1 ± 0.2) ≤ 1.32 s

In other words, the ␶-error must be expected to be ⫾32%,

which is far above the specified 0.1%. Tuning is clearly neces-
sary. Because capacitors are difficult to adjust and accurate
capacitors are expensive, let us assume in this simple case
that the capacitor was measured with 0.05% accuracy as C ⫽
11.125 애F (i.e., the measured error was ⫹11.25%). We can
readily compute that the resistor should be adjusted
(trimmed) to the nominal value R ⫽ ␶ /C ⫽ 1 s/11.125 애F ⫽
89.888 k⍀ within a tolerance of ⫾45 ⍀ to yield the correctly

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.
 CIRCUIT TUNING 421

implemented time constant of 1 s with ⫾0.1% tolerances. Ob- n1

serve that tuning generally allows the designer to construct a
circuit with less expensive wide-tolerance parts because sub- C1 R2
sequent tuning of these or other components permits the er- R1
rors to be corrected. Thus, C was fabricated with 20% toler- –
ances but measured with a 0.05% error to permit the resistor V1 C2 n2 A
with fabrication tolerances of 10% to be trimmed to a 0.05% + V2
accuracy. Note that implied in this process is the availability
of measuring instruments with the necessary accuracy.
Tuning has two main purposes. Its most important func- Figure 2. Active RC bandpass filter.
tion is to correct errors in circuit performance caused by such
factors as fabrication tolerances such as in the preceding ex-
ample. Second, it permits a circuit’s function or parameters,
ner (manually or electronically) by an amount sufficient to
such as the cut-off frequency of a given low-pass filter, to be
overcome the consequences of fabrication tolerances, parasitic
changed to different values to make the circuit more useful or
effects, or other such factors.
to be able to accommodate changing operating requirements.
An example will help to illustrate the discussion and ter-
But even the best fabrication technology together with tuning
minology. Consider the simple second-order active band-pass
will not normally result in a circuit operating with zero errors;
circuit in Fig. 2. Its voltage transfer function, under the as-
rather, the aim of tuning is to trim the values of one or more,
sumption of ideal operational amplifiers, can be derived to be
or in rare cases of all, components until the circuit’s response
is guaranteed to remain within a specified tolerance range V2 b1 s
when the circuit is put into operation. Figure 1 illustrates the T (s) = =− 2
V1 s + a1 s + a0
idea for a low-pass filter. Examples are a gain error that is
1
specified to remain within ⫾0.05 dB, the cut-off frequency f c s (1)
of a filter that must not deviate from the design value of, say, R1C1
=−

f c ⫽ 10 kHz by more than 85 Hz, or the gain of an amplifier 1 1 1 1
s2 + + s+
that must settle to, say, 1% of its final value within less than R2 C1 C2 R1 R2C1C2
1 애s. As these examples indicate, in general, a circuit’s opera-
tion can be specified in the time domain, such as a transient We see that T(s) is a continuous function of the circuit compo-
response with a certain highest permissible overshoot or a nents, as are all its coefficients that determine the circuit’s
maximal settling time, or in the frequency (s) domain through behavior:
an input-output transfer function with magnitude, phase, or
delay specifications and certain tolerances (see Fig. 1). This 1 C + C2 1
b1 = ,a = 1 ,a = (2)
article focuses on the tuning of filters, that is, of frequency- R1C1 1 R2C1C2 0 R1 R2C1C2
selective networks. Such circuits are continuous functions of
components, described by transfer functions in the s domain, Just as in the earlier example of the RC time constant, the

;;;;
where tuning of design parameters (e.g., cut-off frequency,
bandwidth, quality factor, and gain), is particularly important
in practice. The concepts discussed in connection with filters
apply equally to other analog circuits. Obviously, in order to
tune (adjust) a circuit, that circuit must be tunable. That is,
its components must be capable of being varied in some man-
coefficients will not be implemented precisely if the compo-
nent values have fabrication tolerances. If these component
tolerances are ‘‘too large,’’ generally the coefficient errors will
become ‘‘too large’’ as well, and the circuit will not function
correctly. In that case, the circuit must be tuned. Further-
more, circuits are generally affected by parasitic components.
Parasitic components, or parasitics, are physical effects that

;;;;
;;
QQ

often can be modeled as ‘‘real components’’ affecting the cir-
cuit’s performance but that frequently are not specified with
sufficient accuracy and are not included in the nominal de-
sign. For instance, in the filter of Fig. 2, a parasitic capacitor
can be assumed to exist between any two nodes or between
Gain

any individual node and ground; also, real ‘‘wires’’ are not

;;;;
;;
QQ

ideal short circuit connections with zero resistance but are
resistive and, at high frequencies, even inductive. In the filter
of Fig. 2, a parasitic capacitor Cp between nodes n1 and n2
would let the resistor R2 look like the frequency-dependent
impedance Z2(s) ⫽ R2 /(1 ⫹ sCpR2). Similarly, real resistive
wires would place small resistors rw in series with C1 and C2
and would make these capacitors appear lossy. That is, the
Frequency capacitors Ci, i ⫽ 1, 2, would present admittances of the form
Figure 1. The shaded area in the gain vs. frequency plot shows the Yi(s) ⫽ sCi /(1 ⫹ sCirw). Substituting Z2(s) and Yi(s) for R2 and
operating region for a low-pass filter that must be expected based on Ci, respectively, into Eq. (1) shows that, depending on the fre-
raw (untuned) fabrication tolerances; the dotted region is the accept- quency range of interest and the element values, the presence
able tolerance range that must be maintained in operation after the of these parasitics changes the coefficients of the transfer
filter is tuned. function, maybe even its type, and consequently the circuit’s
422 CIRCUIT TUNING
performance. Similarly, when changes occur in environmental
operating conditions, such as bias voltages or temperature,
the performance of electronic devices is altered, and as a re-
sult the fabricated circuit may not perform as specified.
As discussed by Moschytz (1, Sec. 4.4, pp. 394–425), and
Bowron and Stevenson (2, Sec. 9.5, pp. 247–251), the opera-
tion of tuning can be classified into functional and determinis-
tic tuning. In functional tuning, the designed circuit is assem-
bled, and its performance is measured. By analyzing the
circuit, we can identify which component affects the perfor-
mance parameter to be tuned. These predetermined compo-
nents are then adjusted in situ (i.e., with the circuit in opera-
tion), until errors in performance parameters are reduced to
acceptable tolerances. The process is complicated by the fact
that tuning is most often interactive, meaning that adjusting
a given component will vary several circuit parameters; thus
iterative routines are normally called for. As an example, con-
sider again the active RC filter in Fig. 2. If its bandpass trans-
fer function, Eq. (1), is expressed in the measurable terms of
center frequency 웆0, the pole quality factor Q ⫽ 웆0 /⌬웆, the pa-
rameter that determines the filter’s bandwidth ⌬웆, and mid-
band (at s ⫽ j웆0) gain K as
1 ing iteration using functional tuning may be required because
s
R1C1
T (s) = −
 specifications as a result of further parasitic or loading effects
1 1 1 1
s2 + + s+
R2 C1 C2 R1 R2C1C2
ω0
K s
Q
=− ω0
s +s
2 + ω02
Q
These parameters are expressed in terms of the circuit compo-
nents and we arrive at the more meaningful and useful de-
sign equations
with C2 a free parameter. That there are more circuit compo-
nents than parameters is normal, so the additional ‘‘free’’ ele-
ments may be used at will, for example, to achieve practical
element values or element-value spreads (i.e., the difference
between the maximum and minimum of a component type,
such as Rmax ⫺ Rmin). Technology or cost considerations may
place further constraints on tuning by removing some compo-
nents from the list of tunable ones. Thus, in hybrid circuits
with thin- or thick-film technology as in the preceding exam-
ple, the capacitors will likely be fixed; only the two resistors
will be determined as in Eq. (5) from the prescribed circuit
parameters 웆0 and Q and the selected and measured capacitor
values. This choice leaves the midband gain fixed at the
value K ⫽ Q/(웆0C1R1). Precise deterministic tuning requires
careful measurements and accurate models and design equa-
tions that, in contrast to the idealized expressions in Eq. (5),
describe circuit behavior along with loss, parasitic, and envi-
ronmental effects. As we saw in Eq. (5), the equations that
must be solved are highly nonlinear and tend to be very com-
plex, particularly if parasitic components also are involved.
Computer tools are almost always used to find the solution.
Typically, automatic laser trimming is employed to tune the
resistors to the desired tolerances (e.g., 0.1%). A second tun-
the assembled circuit under power may still not meet the
that could not be accounted for in the initial deterministic
tuning step.
(3)
SENSITIVITY
We mentioned earlier that a filter parameter P depends on
the values ki of the components used to manufacture a cir-
cuit, P ⫽ P(ki), and that real circuit components or parts can
be realized only to within some tolerances ⫾⌬ki. That is, the
 √ values of the parts used to assemble circuits are ki ⫾ ⌬ki.
1 R2 C1C2 R C2 Clearly, the designer needs to know how much these toler-
ω0 = √ ,Q = ,K = 2 (4)
R1 R2C1C2 R1 C1 + C2 R1 C1 + C2 ances will affect the circuit and whether the resulting errors
can be corrected by adjusting (tuning) the circuit after fabri-
cation. Obviously, the parameter to be tuned and must de-
instead of Eq. (2). It is clear that varying any of the passive
pend on the component to be varied. For example, Q in Eq.
components will change all three filter parameters, so that
(4) is a function of the components R1, R2, C1, and C2, any one
expensive and time-consuming iterative tuning is required.
of which can be adjusted to correct fabrication errors in Q. In
However, functional tuning has the advantage that the ef-
general, the questions of how large the adjustment of a
fects of all component and layout parasitics, losses, loading,
component has to be, whether it should be increased or
and other hard-to-model or hard-to-predict factors are ac-
decreased, and what the best tuning sequence is are an-
counted for because the performance of the complete circuit
swered by considering the parameter’s sensitivity to compo-
is measured under actual operating conditions. In general,
nent tolerances. How sensitive P is to the component-value
more accurate results are obtained by basing functional
tolerances, that is how large the deviation ⌬P of the param-
tuning on measurements of phase rather than of magnitude
eter in question is, is computed for small changes via the
because phase tends to be more sensitive to component
derivative of P(ki) with respect to ki, ⭸P/⭸ki, at the nominal
errors.
value ki:
Deterministic tuning refers to calculating the needed value
of a component from circuit equations and then adjusting the
∂P(ki )
component to that value. We determined the resistor R ⫽ P = ki (6)
␶ /C ⫽ 89.888 k⍀ to set a time constant of 1 s at the beginning ∂ki
of this article in this manner. Similarly, from Eq. (4) we can
derive the three equations in the four unknowns R1, R2, C1, Typically, designers are less interested in the absolute toler-
and C2 ances than in the relative ones, that is,


Q 1 1 1 1 Q P k ∂P ki ki
R2 = + , R1 = ,C = (5) = i = SPk (7)
ω0 C1 C2 R2 ω02C1C2 1 KR1 ω0 P P ∂ki ki i k
i
 CIRCUIT TUNING 423

SPki is the sensitivity, defined as ‘‘the relative change of the error. To illustrate the calculations, let us apply Eq. (11) to
parameter divided by the relative change of the component,’’ 웆0 in Eq. (4). Using Eqs. (9) and (10), the result is

P/P ω0 R ∂ω0 R1 R ∂ω0 R2 C ∂ω0 C1 C2 ∂ω0 C2
SPk = (8) = 1 + 2 + 1 +
i ki /ki ω0 ω0 ∂R1 R1 ω0 ∂R2 R2 ω0 ∂C1 C1 ω0 ∂C2 C2
ω R ω R C ω C
= SR0 1
+ SR0 2
+ SCω p 1
+ SC0 2
A detailed discussion of sensitivity issues can be found in 1 R1 2 R2 1 C1 2 C2

many text books [see Schaumann, Ghausi, and Laker (3), 1 R1 1 R2 1 C1 1 C2
=− − − −
Chap. 3, pp. 124–196]. For example, the sensitivity of 웆0 in 2 R1 2 R2 2 C1 2 C2
Eq. (4) to changes in R1 is readily computed to be

1 R1 R2 C1 C2
=− + + +
2 R1 R2 C1 C2
ω R1 ∂ω0
SR0 = (12)
1 ω0 ∂R1

 (9)
R1 1 R2C1C2 1 The last expression gives insight into whether and how 웆0 can
= − =−
1/(R1 R2C1C2 )1/2 2 (R1 R2C1C2 )3/2 2 be tuned. Because the effects of the errors are additive, tun-
ing just one component, say R1, will suffice for given toler-
SR웆01 ⫽ ⫺0.5 means that the percentage error in the parameter ances of R2, C1, and C2 if ⌬R1 can be large enough. If we have
웆0 is one-half the size of the percentage error of R1 and oppo- measured the R2 errors at ⫺12%, and those of C1 and C2 at ⫹
site in sign (i.e., if R1 increases, 웆0 decreases). A large number 15% and ⫹10%, respectively, Eq. (12) results in
of useful sensitivity relations that make sensitivity calcula-

ω0 1 R1
tions easy can be derived [see, for example, Moschytz (1), Sec. =− − 0.12 + 0.15 + 0.10
ω0 2 R1
1.6, pp. 103–105, 1.5, pp. 71–102, and 4.3, pp. 371–393, or
 (13)
Schaumann, Ghausi, and Laker (3), Chap. 3, pp. 124–196]. R1
= −0.5 + 0.13
Of particular use for our discussion of tuning are R1

n)
SkP(k = nSP(k) , SP(αk) = SP(k) , indicating that R1 must be decreased by 13% to yield, within
k k k
√ (10) the linearized approximations made, ⌬웆0 앒 0. Inserting com-
1 P(k)
SP(1/k) = −SP(k) , and SkP( k)
= S ponents with these tolerances into Eq. (4) for 웆0 confirms the
k k 2 k result obtained.
To expand these results and gain further insight into the
where 움 is a constant, independent of k. The last two of these effects of tolerances, as well as beneficial tuning strategies
equations are special cases of the first one for n ⫽ ⫺1 and and their constraints, we remember that a transfer function
n ⫽ 1/2, respectively. The last equation generalizes the result generally depends on more than one parameter. Returning to
obtained in Eq. (9). Equations (7) and (8) indicate that, for the example of Fig. 2 described by the function T(s) in Eq. (3)
small differential changes, the parameter deviation caused by with the three parameters 웆0, Q, and K given in Eq. (4) and
a component error and, conversely from the point of view of applying Eq. (11) leads to
tuning, the change in component value necessary to achieve
a desired change in parameter can be computed if the sensi- ω0 ω R1 ω R2 ω C1 ω C2
tivity is known. = SR0 + SR0 + SC0 + SC0 (14a)
ω0 1 R1 2 R2 1 C1 2 C2
In Eqs. (6) and (7) we purposely used partial derivatives,
⭸P/⭸ki, to indicate that circuit parameters normally depend Q R1 R2 C1 C2
= SQ
R1 R
+ SQ
R2 R
+ SCQ + SCQ (14b)
on more than one component [see Eq. (4)], all of which affect Q 1 2 1 C1 2 C2
the accuracy of the parameter. To get a more complete picture K R1 R2 C1 C2
of the combined effect of the tolerances and to gain insight = SK
R1 + SK
R2 + SCK + SCK (14c)
K R1 R2 1 C
1
2 C
2
into the operation of tuning involving several parameters, to-
tal derivatives need to be computed. Assuming P depends on These equations can be expressed in matrix form as follows:
n components, we find [see Schaumann, Ghausi, and Laker
 
(3), Chap. 3, pp. 124–196] R1
   R 
ω0  1 
∂P ∂P ∂P  
P = k1 + k2 + · · · + kn  ω0  Sω 0 ω
SR0
ω
SC0
ω0  
SC  R2 
∂k1 ∂k2 ∂kn   R1 
   
 Q  
2 1 2
 Q 
 R2 
  SQ SQ SCQ 
 Q = SC    (15)
  1 2
R R
that is  2 1
 C1 
   
 K  SK SK SCK SC  C1 
K

P k ∂P k1 kn ∂P kn
R1 R 2 1 2  
 
= 1 + ··· + K  C2 
P P ∂k1 k1 P ∂kn kn
n (11) C2
k1 kn ki
= SPk + · · · + SPkn = SPk
1 k k n i k
1 i=1 i The sensitivity matrix in Eq. (15) [see Moschytz (1), Sec. 4.3,
pp. 376–393, or Schaumann, Ghausi, and Laker (3), Sec. 3.3,
indicating that the sum of all relative component tolerances, pp. 161–188], a 3 ⫻ 4 matrix in this case, shows how the
weighted by their sensitivities, contributes to the parameter tolerances of all the filter parameters depend on the compo-
424 CIRCUIT TUNING

nent tolerances. We see that adjusting any one of the circuit As can be verified readily, each component affects only one
components will vary all filter parameters as long as all the circuit parameter. Again, sensitivities to C2 are irrelevant be-
sensitivities are nonzero, which is indeed the case for the cir- cause C2 is fixed, and the effects of its tolerances can be cor-
cuit in Fig. 2. Thus, noninteractive tuning is not possible. To rected by the remaining components.
illustrate the form of the sensitivity matrix, we calculate for An important observation on the effects of tolerances on
the circuit in Fig. 2 circuit parameters and the resultant need for tuning can
 R  be made from Eq. (16). We see that the sensitivities of the
1 dimensionless parameters (parameters with no physical
 ω   R 
0   1  unit) Q and K to the two resistors and similarly to the two
−0.5 −0.5 −0.5 −0.5  
 ω0   R2  capacitors are equal in magnitude but opposite in sign.
   1 C1 − C2 1 C1 − C2   
  −0.5 −  R  Because dimensionless parameters are determined by ratios
 Q   0.5
2 C1 + C2 2 C1 + C2   2 
 =   of like components [see Eq. (4)], we obtain from Eq. (4)
 Q     C1 
   C1 C1   with Eq. (10)
  −1 −  C 
K 1  1 
C1 + C2 C1 + C2  
K  C  SQ
R
= −SQ
R
= SQ
R
= −0.5 and
2 1 2
C2 1 C1 − C2 (18)
(16) SCQ = −SCQ = SCQ = −
1 2 2 C1 + C2
Note that the first line of Eq. (16) is equal to the last part of
Thus, the tolerances of Q are
Eq. (12).
The tuning situation is simpler if the matrix elements


Q Q R1 R2 Q C1 C2
above the main diagonal are zero as was assumed for an arbi- = SR − + SC − (19)
Q R1 R2 C1 C2
trary different circuit in Eq. (17a):
 
R1 with analogous expressions obtained for the gain K [see the
    last line of Eq. (16)]. Thus, if the technology chosen to imple-
ω0  R1 
  ment the filter permits ratios of resistors and capacitors to be
 ω 0  S ω 0 ω 0   R 
  0 0 S  2 realized accurately (i.e., if all resistors have equal tolerances,
  R1 C2
 
 Q    R2  as do all capacitors), tuning of dimensionless parameters will
 = Q Q Q  
 Q   S S 0 S C2  
  C1  generally not be necessary. A prime example is integrated cir-
  1
R R2
 
  SK SK SCK SCK   cuit technology, where absolute value tolerances of resistors
 K  R1 R2  C1 
1 2   and capacitors may reach 20 to 50%, but ratios, depending
 
K  C2  mainly on processing mask dimensions, are readily imple-
C mented with tolerances of a fraction of 1%. As an example,
 R  2 assume that the circuit in Fig. 2 was designed, as is often the
1 (17a)
 ω    ω0  case, with two identical capacitors C1 ⫽ C2 ⫽ C with toler-
SR0 0 0  R1  SC
 1    2 ances of 20% and that R1 and R2 have tolerances of 10% each,
  
 R2  +  Q  C2 that is,
= S Q S Q
0  SC 
 R1 R2
  R2 

  2  C2
SKR1 SKR2 SCK   C 
 SCK C1 = C2 = Cn + C = Cn (1 + 0.2),
1 1 2
R1 = R1n + R1 = R1n (1 + 0.1), and (20)
C1
R2 = R2n (1 + 0.1)
Here the sensitivities to C2 are irrelevant because C2 is a free
parameter and is assumed fixed so that the effects of C2 toler- where the subscript n stands for the nominal values. From
ances can be corrected by varying the remaining elements. Eq. (19), we find
We see then that first 웆0 can be tuned by R1, next Q is tuned
by R2 without disturbing 웆0 because SR웆02 is zero, and finally K Q = [SQ
R
(0.1 − 0.1) + SCQ (0.2 − 0.2)]Q = 0
is tuned by C1 without disturbing the previous two adjust-
ments. Thus a sensitivity matrix of the structure indicated in That is, the quality factor Q, depending only on ratios of like
Eq. (17a) with elements above the main diagonal equal to zero components, is basically unaffected because all like compo-
permits sequential ‘‘noninteractive’’ tuning if the tuning order nents have equal fabrication tolerances. This result can be
is chosen correctly. Completely noninteractive tuning without confirmed directly from Eq. (4) where, for equal capacitors,
regard to the tuning order requires all elements in the sensi-  
tivity matrix off the main diagnonal to be zero as indicated 1 R2 1 R2n (1 + 0.1)
for another circuit in Eq. (17b): Q= = ≈ Qn (21)
2 R1 2 R1n (1 + 0.1)
   R 
ω0 1
 ω0   ω0   ω0   R1  Naturally, if R1 and R2 are selected from different manufac-
  SC SR 0 0   turing lots, or if R1 and R2 are from physically different fabri-
   
 Q  
2  1
  C    R  cation processes (such as a carbon and a metal-film resistor),
  − S Q  Q  2
 Q   C2  C = 
2 0 S 0   (17b)
  2  R2
 R
 2  tolerances cannot be assumed to be equal, Q errors are not
  K
SC 0 0 K
SC    zero, and tuning will be required.
 K  2 1 C  1
The situation is quite different for any dimensioned circuit
K C1 parameter, that is, a parameter with a physical unit (e.g., a
 CIRCUIT TUNING 425

frequency or time constant, or a voltage or a current). Such TUNING DISCRETE CIRCUITS

parameters are determined by absolute values of components,
as seen for 웆0 in Eq. (4). Absolute values, depending on physi- Whether implemented on a printed circuit board, with chip
cal process parameters e.g., resistivity, permittivity, or diffu- and thin- or thick-film components in hybrid form, by use of
sion depth, are very difficult to control and will usually suffer wire-wrapping, or in any other technology, an advantage of
from large process variations. Thus, for the component toler- discrete circuits for the purpose of tuning is that circuit ele-
ances in Eq. (20), sensitivity calculations predict from Eqs. ments are accessible individually before or after assembly for
(10) and (12) the realized center frequency error deterministic or functional adjusting. Thus, after a circuit is
assembled and found not to meet the design specifications,


1 R1 R2 C1 C2 the circuit components (most commonly the resistors or induc-
ω0 ≈ − + + + ω0 tors), can be varied until the performance is as required. All
2 R1 R2 C1 C2
(22a) the previous general discussion applies to the rest of the arti-
1
= − (0.1 + 0.1 + 0.2 + 0.2) = −0.3ω0 cle so we shall present only those special techniques and con-
2 siderations that have been found particularly useful or impor-
tant for passive and active filters.
that is, all individual component tolerances add to a ⫺30%
frequency error. Again, the validity of this sensitivity result
Passive Filters
can be confirmed directly from Eq. (4):
Discrete passive filters are almost always implemented as
1 1 lossless ladder circuits, that is, the components are inductors
ω0 = √ = √ L and capacitors C as is illustrated in the typical circuit in
R1 R2C1C2 C R1 R2
Fig. 3. These LC filters are designed such that the maximum
1
= √ signal power is transmitted from a resistive source to a re-
Cn (1 + 0.2) R1n R2n (1 + 0.1 + 0.1 + 0.01) sistive load in the frequency range of interest; a brief treat-
ω0n ω0n (22b)
ment can be found in Schaumann, Ghausi, and Laker (3),
≈ √ ≈
(1 + .02) 1 + 0.2 (1 + 0.2)(1 + 0.1) Chap. 2, pp. 71–123. As pointed out in our earlier discussion,
ω0n accurate filter behavior depends on precise element values so
= ≈ ω0n (1 − 0.24)
(1 + 0.32) that it is normally necessary to trim components. This tuning
is almost always accomplished via variable inductors whose
The difference between the exact result in Eq. (22b) and values are changed by screwing a ferrite slug (the ‘‘trimmer’’)
the one obtained via the sensitivity approach in Eq. (22a) into or out of the magnetic core of the inductive windings.
arises because the latter assumes incremental component Variable discrete capacitors are hard to construct, expensive,
changes whereas the former assumed the relatively large and rarely used.
changes of 10 and 20%. The center frequency 웆0 is approxi- LC filters have the advantage of very low sensitivities to
mately 25–30% smaller than specified and must be corrected all their elements [see Schaumann, Ghausi, and Laker (3),
by tuning. This can be accomplished, for example, by trim- Chaps. 2 and 3, pp. 71–196], which makes it possible to as-
ming the two resistors to be 27% smaller than their fabricated semble the filter using less expensive wide-tolerance compo-
values, that is, nents. This property is further enhanced by the fact that loss-
less ladders are very easy to tune so that large tolerances
of one component can be compensated by accurately tuning
R1 = R1n (1 + 0.1)(1 − 0.27) ≈ R1n (1 − 0.2),
another. For example, the resonant frequency f 0 ⫽ 1/ 兹LC of
R2 ≈ R2n (1 − 0.2) an LC resonance circuit has ⫾15% tolerances if both L and C
have ⫾15% tolerances; if then L is trimmed to ⫾0.5% of its
so that sensitivity calculations yield correct value for the existing capacitor (with ⫾15% toler-
ances), f 0 is accurate to within 0.25% without requiring any
narrower manufacturing tolerances. Without tuning, a 0.25%
ω0 ≈ −0.5(−0.2 − 0.2 + 0.2 + 0.2) = 0
f 0 error would require the same narrow 0.25% tolerance in

More exact deterministic tuning requires the resistors to be

trimmed to 24.2% smaller than the fabricated value as shown
in Eq. (23):
C1 C2

1 ω0n
ω0 ≈ √ = ⇒ ω0n R1 L1 L2 L3
Cn (1 + 0.2) R1n R2n (1 + 0.1)(1 − δ) 1.32(1 − δ)
(23) Vi Vo
+ n2 A +
C3 C4 C5 R2
where 웃 is the trimming change to be applied to the resistors
as fabricated. Equation (23) results in 웃 ⫽ 0.242. Of course,
웆0 tuning could have been accomplished by adjusting only one
Figure 3. Sixth-order LC low-pass filter. The filter is to realize a
of the resistors by a larger amount; we trimmed both resistors maximally flat passband with a 2 dB bandwidth of f c ⫽ 6 kHz, mini-
by equal amounts to maintain the value of their ratio that mum stopband attenuation 움s ⫽ 57.5 dB with transmission zeros at
determines Q according to Eq. (21), thereby avoiding the need 12 and 24 kHz. The nominal components are listed in Table 1. Note
to retune Q. that at dc the filter has ⫺20 log[R2 /(R1 ⫹ R2)] ⫽ 6.02 dB attenuation.
426 CIRCUIT TUNING
Table 1. LC Low-pass Filter (elements in mH, nF, and k⍀)
Components L1 C1 L2 C2
Nominal values 27.00 6.490 46.65 0.943 12.67 6.977 45.55 33.90 1.00 1.00
Performance fc ⫽ 6.0 kHz @ 움p ⫽ 8.03 dB; fz1 ⫽ 12.0 kHz, fz2 ⫽ 24.0 kHz, 움s ⫽ 57.5 dB
15% tolerance 31 7.5 52 1.1
values
Performance fc ⫽ 5.36 kHz @ 움p ⫽ 8.01 dB; fz1 ⫽ 10.3 kHz, fz2 ⫽ 20.7 kHz, 움s ⫽ 56.7 dB
untuned
Tuned values 23.5 7.5 40 1.1
Performance fc ⫽ 6.07 kHz @ 움p ⫽ 8.03 dB; fz1 ⫽ 12.0 kHz, fz2 ⫽ 24.0 kHz, 움s ⫽ 57.8 dB
tuned
both components, which is likely more expensive than a sim-
ple tuning step.
It is well known that lossless ladders can be tuned quite
accurately simply by adjusting the components to realize the
prescribed transmission zeros [see Heinlein and Holmes (4),
Sec. 12.3, pp. 591–604, and Christian (5), Chap. 8, pp. 167–
176]. Transmission zeros, frequencies where the attenuation
is infinite, usually depend on only two elements, a capacitor
and an inductor in a parallel resonant ciruit (see Fig. 3) with
the parallel tank circuits L1, C1 and L2, C2 in the series
branches of the filter, or alternatively with series LC reso-
nance circuits in the shunt branches. The resonant frequen-
cies f zi ⫽ 1/ 兹LiCi, i ⫽ 1, 2, of the LC tank circuits are not
affected by other elements in the filter, so that tuning is
largely noninteractive. As mentioned, the effect of the toler-
ances of one component, say C, are corrected by tuning L. It
is performed by adjusting the inductors for maximum attenu-
ation at the readily identified frequencies of zero transmission
while observing the response of the complete manufactured
filter on a network analyzer. Tuning accurancies of the trans-
mission zeros of 0.05% or less should be aimed at. Such tun-
ing of the transmission zeros is almost always sufficient even
if the circuit elements have fairly large tolerances [see Hein-
lein and Holmes (4), Sec. 12.3, pp. 594–604]. If even better
accuracy is needed, adjustments of those inductors that do
not cause finite transmission zeros, such as L3 in Fig. 3, may
need to be performed [see Christian (5), Chap. 8, pp. 167–
176]. For instance, consider the filter in Fig. 3 realized with
unreasonably large tolerances of ⫾15%, using the components
shown in Table 1. This places the two resonant frequencies at
10.3 and 20.7 kHz, with the minimum stopband attenuation
equal to only 56.7 dB; the 2 dB passband corner is reduced to
5.36 kHz. If we next tune the transmission zero frequencies
to 12 and 24 kHz by adjusting only the inductors L1 and L2 to
23.5 and 40 mH, respectively, the minimum stopband attenu-
ation is increased to 57.8 dB, and the 2 dB bandwidth of the
passband is measured as f c ⫽ 6.07 kHz (refer to Table 1).
We still note that when functional tuning is performed, the
filter must be operated with the correct terminations for
which it was designed [see Christian (5), Sec. 8.2, pp. 168–
173]. Large performance errors, not just at dc or low frequen-
cies, will result if the nominal terminations are severely al-
tered. For example, an LC filter designed for 600 ⍀
terminations cannot be correctly tuned by connecting it di-
rectly without terminations to a high-frequency network ana-
lyzer whose input and source impedances are 50 ⍀. Also, if
maintaining an accurate narrow passband ripple is impor-
L3 C3 C4 C5 R1 R2
14 8 51 38 1.05 1.05
14 8 51 38 1.05 1.05
tant, the tolerances of the untuned capacitors must not be
too large. Finally, we observe that the tuning properties of
passive LC ladders translate directly to active simulations of
these filters via transconductance-C and gyrator-C circuits,
which are widely used in high-frequency integrated circuits
for communications (see the following discussion).
Active Filters
Several differences must be kept in mind when tuning active
filters as compared to passive lossless filters, particularly to
ladders:
1. Active filters are almost always more sensitive to com-
ponent tolerances than LC ladders. Consequently, tun-
ing is always required in practice.
2. Tuning in active filters is almost always interactive;
that is, a filter parameter depends on many or all circuit
components as discussed in connection with the circuit
in Fig. 2 and the sensitivity discussion related to Eqs.
(15) and (16). Consequently, tuning active filters usu-
ally requires computer aids to solve the complicated
nonlinear tuning equations [see, for example, the rela-
tively simple case in Eq. (4)].
3. The performance of the active devices, such as opera-
tional amplifiers (op amps), and their often large toler-
ances almost always strongly affects the filter perfor-
mance and must be accounted for in design and in
tuning. Because active-device behavior is often hard to
model or account for, functional tuning of the fabricated
circuit is normally the only method to ensure accurate
circuit performance.
In discrete active filters constructed with resistors, capaci-
tors, and operational amplifiers on a circuit board or in thin-
or thick-film form, tuning is almost always performed by var-
ying the resistors. Variable resistors, potentiometers, are
available in many forms, technologies, and sizes required to
make the necessary adjustments.
Second-Order Filters. The main building blocks of active
filters are second-order sections, such as the bandpass circuit
in Fig. 2. Many of the tuning strategies and concepts were
presented earlier in connection with that circuit and the dis-
cussion of sensitivity. An important consideration when tun-
ing an active filter is its dependence on the active devices as
mentioned previously in point 3. To illustrate the problem,
 CIRCUIT TUNING 427

consider again the bandpass filter in Fig. 2. The transfer func- V1 T1 T2 Tn

tion T(s) in Eq. (1) is independent of the frequency-dependent ...
gain A(s) of the op amp only because the analysis assumed ω 1, Q1, K1 ω 2, Q2, K2 ω n, Qn, Kn
that the amplifier is ideal, that is, it has constant and very
large (ideally infinite) gain, A ⫽ 앝. In practice, T(s) is also a
function of A(s) as a more careful analysis shows:
Figure 4. Cascade realization of 2nth-order filter. The n second-or-
V der sections do not interact with each other and can be tuned inde-
T (s) = 2 pendently, that is, each section Ti can be tuned to its nominal values
V1 웆i, Qi, and Hi, i ⫽ 1, 2, . . ., n, without being affected by the other sec-
1 A(s) tions.
s
R1C1 1 + A(s)
=−  
1 1 1 1 1
s2 + + + s+ tuning is a main advantage of cascade implementations be-
R2 C1 C2 R1C1 [1 +A(s)] R1 R2C1C2 cause each section performs in isolation from the others so
(24) that it can be tuned without interactions from the rest of the
circuit. Remember, though, that each section by itself may
Evidently, for A ⫽ 앝, Eq. (24) reduces to Eq. (1), but finite require interactive tuning. Figure 4 shows the circuit struc-
and frequency-dependent gain can cause severe changes in ture where each of the blocks is a second-order section such
T(s) in all but the lowest-frequency applications. Consider the as the ones in Figs. 2 and 5. If the total filter order is odd,
often-used integrator model for the operational amplifier, one of the sections is, of course, of first order.
A(s) 앒 웆t /s, where 웆t is the unity gain frequency (or the gain- To illustrate this point, assume a fourth-order Chebyshev
bandwidth product) of the op amp with the typical value low-pass filter is to be realized with a 1 dB ripple passband
웆t ⫽ 2앟 ⫻ f t ⫽ 2앟 ⫻ 1.5 MHz. Using this simple model, which in 0 ⱕ f ⱕ 28 kHz with passband gain equal to H ⫽ 20 dB. The
is valid for frequencies up to about 10 to 20% of f t, and assum- transfer function is found to be
ing 웆t Ⰷ 웆, the transfer function becomes
T (s) = T1 (s) × T2 (s)
V
T (s) = 2 1.66ω02 1.66ω02
V1 = (26)
s2 + 0.279ω0s + 0.987ω0 s + 0.674ω0s + 0.279ω02
2 2
1
s
C1 R1 with 웆0 ⫽ 2앟 ⫻ 28,000 s⫺1 ⫽ 175.93 ⫻ 103 s⫺1 [see Schaumann,
≈−


1 1 1 1 1 Ghausi, and Laker (3), Sec. 1.6, pp. 36–64]. Let the function
s2 1 + + + s+
ωt C1 R1 R2 C1 C2 R1 R2C1C2 be realized by two sections of the form shown in Figure 5.
Assuming that the op amps are ideal, the transfer function of
(25)
the low-pass section is readily derived as
To get an estimate of the resulting error, let the circuit be V2 Kω02
designed with C1 ⫽ C2 ⫽ C ⫽ 10 nF, R1 ⫽ 66.32 ⍀ and R2 ⫽ = ω
V1 s2 + s 0 + ω02
9.55 k⍀ to realize the nominal parameters f 0 ⫽ 20 kHz, Q ⫽
Q
6, and K ⫽ 72. Simulation (or measurement with a very fast
1 (27)
op amp) shows that the resulting circuit performance is as α1 α2
C1 R1C2 R2
desired. However, if the filter is implemented with a 741-type =

op amp with f t ⫽ 1.5 MHz, the measured performance indi- 1 1 − α1 α2 1
s2 + s + +
cates f 0 ⫽ 18.5 kHz, Q ⫽ 6.85, and K ⫽ 76.75. Because of the C1 R1 C2 R2 C1 R1C2 R2
complicated expressions involving a real op amp, it is appro-
priate to use functional tuning with the help of a network If the op amp gain is modeled as A(s) ⫽ 웆t /s, 움i is to be re-
analyzer. Keeping C constant, the resulting resistor values, placed by
R1 ⫽ 68.5 ⍀ and R2 ⫽ 8.00 k⍀, lead to f 0 ⫽ 20 kHz and Q ⫽ αi αi
6.06. The midband gain for these element values equals K ⫽ αi ⇒ ≈ (28)
1 + αi /A(s) 1 + sαi /ωt
62.4 (remember from the earlier discussion that K for the
circuit in Fig. 2 cannot be separately adjusted if the capaci-
tors are predetermined).
V1 R1 C1
High-Order Filters. The two main methods for realizing ac- – R2
tive filters of order greater than two are active simulations A – V2
of lossless ladders and cascading second-order sections. We + A
mentioned in connection with the earlier discussion of LC lad- +
R0(α 1–1)
ders that tuning of active ladder simulations is completely
C2 R0(α 2–1)
analogous to that of the passive LC ladder: the electronic cir-
cuits that simulate the inductors are adjusted until the trans- R0
mission zeros are implemented correctly. It remains to dis- R0
cuss tuning for the most frequently used method of realizing
high-order filters, the cascading of first- and second-order sec-
tions. Apart from good sensitivity properties, relatively easy Figure 5. Two-amplifier active low-pass filter.
428 CIRCUIT TUNING
We observe again that the circuit parameters 웆0, Q, and gain
K are functions of all the circuit elements so that design and
tuning of each section will require iterative procedures, al-
though section 1 is independent of section 2 as just discussed.
Because there are six ‘‘components’’ (R1, R2, C1, C2, 움1, and
움2) and only three parameters, some simplifying design
choices can be made. Choosing C1 ⫽ C2 ⫽ C, R1 ⫽ R, and
R2 ⫽ k2R (and assuming ideal op amps), Eq. (27) leads to in
the expressions
1 1
ω0 = ,Q = , and K = α1 α2 (29)
kRC 1 rate reference, such as an external precision resistor Re to set
k + (1 − K)
k the value of an electronic on-chip transconductance to gm ⫽
The circuit is designed by first computing k from the given
values Q and K; next we choose a suitable capacitor value C
and calculate R ⫽ 1/(k웆0C). Finally, we determine the feed-
back resistors on the two op amps. Because only the pro-
duct 움1움2 is relevant, we choose 움1움2 ⫽ 움2 ⫽ K (i.e., 움 ⫽
兹K ⫽ 兹1.66 ⫽ 1.288). Working through the design equations
and choosing all capacitors equal to C ⫽ 150 pF (standard 5%
values) and R0 ⫽ 10 k⍀, results in (움 ⫺ 1)R0 ⫽ 2.87 k⍀ for
both sections: k ⫽ 0.965, R1 ⫽ 40.2 k⍀, R2 ⫽ 36.5 k⍀ for sec-
tion 1 and k ⫽ 1.671, R1 ⫽ 42.2 k⍀, R2 ⫽ 120.1 k⍀ for section
2. All resistors have standard 1% tolerance values. Building
the circuit with 741-type op amps with f t ⫽ 1.5 MHz results
in a ripple width of almost 3 dB, the reduced cut-off frequency
of 27.2 kHz, and noticeable peaking at the band-edge. Thus,
tuning is required. The errors can be attributed largely to the
5% capacitor errors and the transfer function changes as a
result of the finite f t in Eq. (28).
To accomplish tuning in this case, deterministic tuning
may be employed if careful modeling of the op amp behavior,
using Eq. (28), and of parasitic effects is used and if the un-
tuned components (the capacitors) are measured carefully
and accurately. Because of the many interacting effects in the
second-order sections, using a computer program to solve the
coupled nonlinear equations is unavoidable, and the resistors
are trimmed to their computed values. Functional tuning in
this case may be more convenient, as well as more reliable in
practice. For this purpose, the circuit is analyzed, and sensi-
tivities are computed to help understand which components
affect the circuit parameters most strongly. Because the sec-
tions do not interact, the high-order circuit is separated into
its sections, and each section’s functional performance is mea-
sured and adjusted on a network analyzer. After the perfor-
mance of all second-order blocks is found to lie within the
specified tolerances, the sections are reconnected in cascade.
TUNING INTEGRATED CIRCUITS
With the increasing demand for fully integrated microelec-
plementation method because fabrication tolerances and par-
asitic effects are generally too large for filters to work cor-
rectly without adjustment. Understandably, tuning in the
traditional sense is impossible when the complete circuit is
integrated on an IC because individual components are not
accessible and cannot be varied. To handle this problem, sev-
eral techniques have been developed. They permit tuning the
circuits electronically by varying the bias voltages VB or bias
currents IB of the active electronic components (transconduc-
tors or amplifiers). In the usual approach, the performance of
the fabricated circuit is compared to a suitably chosen accu-
1/Re, or to a reference frequency 웆r to set the time constant
to C/gm ⫽ 1/웆r. This approach is indeed used in practice,
where often the external parameters, Re or 웆e, are adjusted
manually to the required tolerances. Tuning can be handled
by connecting the circuit to be tuned into an on-chip control
loop, which automatically adjusts bias voltages or currents
until the errors are reduced to zero or an acceptable level [see
Schaumann, Ghausi, and Laker (3), Sec. 7.3, pp. 418–446,
and Johns and Martin (6), Sec. 15.7, pp. 626–635]. [A particu-
larly useful reference is Tsividis and Voorman (7); it contains
papers on all aspects of integrated filters, including tuning.]
Naturally, this process requires that the circuit is designed to
be tunable, that is, that the components are variable over a
range sufficiently wide to permit errors caused by fabrication
tolerances or temperature drifts to be recovered. We also
must pay attention to keeping the tuning circuitry relatively
simple because chip area and power consumption are at a pre-
mium. Although digital tuning schemes are conceptually at-
tractive, analog methods are often preferred. The reason is
the need to minimize or eliminate generating digital (switch-
ing) noise, which can enter the sensitive analog signal path
through parasitic capacitive coupling or through the sub-
strate, causing the dynamic range or the signal-to-noise ratio
to deteriorate.
Automatic Tuning
Let us illustrate the concepts and techniques with a simple
second-order example. Higher-order filters are treated in an
entirely analogous fashion; the principles do not change. Con-
sider the gm –C filter in Fig. 6, which realizes the transfer
function
g g g g
αs2 + s α m1 − β m2 + m0 m2
V0 C1 C2 C1C2
T (s) = = gm1 gm1 gm2 (30)
V1 s +s
2 +
C1 C1C2
with pole frequency and pole Q equal to
tronic systems, naturally, analog circuits will have to be  
placed on an integrated circuit (IC) along with digital ones. gm1 gm2 ωC C1 /C2
ω0 = ,Q = 0 1 = (31)
Of considerable interest are communication circuits where C1C2 gm1 gm1 /gm2
bandwidths may reach many megahertz. Numerous applica-
tions call for on-chip high-frequency analog filters. Their fre- Comparing Eq. (31) to Eq. (2) indicates that the filter parame-
quency parameters, which in discrete active filters are set by ters for this technology are determined in fundamentally the
RC time constants, are in integrated filters most often de- same way as for discrete active circuits: the frequency is de-
signed with voltage-to-current converters (transconductors), termined by time constants (Ci /gmi) and the quality factor, by
Io ⫽ gmVi, and capacitors (i.e., as 웆 ⫽ 1/ ␶ ⫽ gm /C). As discussed ratios of like components. Analogous statements are true for
earlier, filter performance must be tuned regardless of the im- the numerator coefficients of T(s). We can conclude then that,
 CIRCUIT TUNING 429

in principle, tuning can proceed in a manner quite similar to

the one discussed in the beginning of this article if we can PD
VR +
just develop a procedure for varying the on-chip components. + gmc
VC
To gain an understanding of what needs to be tuned in an gm PD –
integrated filter, let us introduce a more convenient notation –
that uses the ratios of the components to some suitably cho- C
sen unit values gm and C,
VB
To the main filter’s
gm transconductors Ic
gmi = gi gm , Ci = ciC, i = 1, 2, and ωu = (32)
C
Cc

where 웆u is a unit frequency parameter and gi and ci are the

dimensionless component ratios. With this notation, Eq. (30) Figure 7. Automatic control loop to set 웆u ⫽ gm /C via an applied ref-
becomes erence signal VR with frequency 웆R. The capacitor voltage equals
VC ⫽ VR(gm /j웆RC), which makes the control current Ic ⫽ gmcVR(1 ⫺

 gm /j웆RC). The operation is explained in the text.
g g g g
αs2 + s α 1 − β 2 ωu + 0 2 ωu2
V c1 c2 c1 c2
T (s) = 0 = g1 g1 g2 2 (33)
V1 s + s ωu +
2 ω ceptually, the block diagram in Fig. 7 shows the method (8).
c1 c1 c2 u The control loop equates the inaccurate unit frequency 웆u ⫽
gm /C to the accurate reference frequency 웆R in the following
Casting the transfer function in the form shown in Eq. (33) way: 웆R is chosen in the vicinity of the most critical frequency
makes clear that the coefficient of si is proportional to 웆un⫺i, parameters of the filter (the band-edge for a low-pass, mid-
where n is the order of the filter, n ⫽ 2 in Eq. (33); the con- band for a bandpass filter), where sensitivities are highest.
stants of proportionality are determined by ratios of like com- The transconductance gm to be tuned is assumed to be propor-
ponents, which are very accurately designable with IC tech- tional to the bias voltage VB, such that gm ⫽ kVB where k is a
nology. The same is true for filters of arbitrary order. For constant of proportionality with units of A/V2. gm generates
example, the pole frequency for the circuit in Fig. 6 is deter- an output current I ⫽ gmVR, which results in the capacitor
mined as 웆u times a designable quantity, 웆0 ⫽ 웆u兹g1 g2 /(c1c2). voltage VC ⫽ gmVR /( j웆RC). The two matched peak detectors PD
We may conclude therefore that it is only necessary to tune convert the two signals VR and VC to their dc peak values, so
웆u ⫽ gm /C, which, as stated earlier, as a ratio of two electri- that any phase differences do not matter when comparing the
signals at the input of gmc. The dc output current Ic ⫽
cally dissimilar components will have large fabrication toler-
gmcVR兵1 ⫺ [gm /( j웆RC)]其 of the control-transconductance gmc
ances. In addition, the electronic circuit that implements the
charges the storage capacitor Cc to the required bias voltage
transconductance gm depends on temperature, bias, and other
VB for the transconductance gm. The values gmc and Cc deter-
conditions, so that 웆u can be expected to drift during opera-
mine the loop gain; they influence the speed of conversion but
tion. It can be seen from Eq. (33) that 웆u simply scales the
are otherwise not critical. If the value of gm gets too large
frequency, that is, the only effect of varying 웆u is a shift of
because of fabrication tolerances, temperature, or other ef-
the filter’s transfer function along the frequency axis.
fects, Ic becomes negative, Cc discharges, and VB, that is gm ⫽
We stated earlier that tuning a time constant, or, in the
kVB, is reduced. Conversely, if gm is too small, Ic becomes posi-
present case, the frequency parameter 웆u, is accomplished by
tive and charges Cc, and the feedback loop acts to increase
equating it via a control loop to an external reference, in this
VB and gm. The loop stabilizes when VC and VR are equal, that
case a reference frequency 웆R such as a clock frequency. Con-
is, when gm(VB)/C is equal to the accurate reference frequency
웆R. The gmc –Cc combination is, of course, an integrator with
ideally infinite dc gain to amplify the shrinking error signal
at the input of gmc. In practice, the open loop dc gain of a
transconductance of 35 to 50 dB is more than adequate. Note
V2
that the loop sets the value of 웆u to 웆R regardless of the causes
– – – –
of any errors: fabrication tolerances, parasitic effects, temper-
V1 gm0 gm1 gm2 gm3 ature drifts, aging, or changes in dc bias.
+ + + + We point out that although the scheme just discussed only
varies gm, it actually controls the time constant C/gm, that is,
errors in both gm and C are accounted for. If one wishes to
β C1 control only gm, the capacitor C in Fig. 7 is replaced by an
(1– β )C1 (1– α )C2
accurate resistor Re, and the feedback loop will converge to
gm ⫽ 1/Re.
α C2
Notice that the feedback loop in Fig. 7 controls directly
only the transconductance gm (as does the frequency control
Figure 6. A general second-order transconductance-C filter. The cir- circuit in Fig. 8) such that the unit frequency parameter 웆u
cuit realizes arbitrary zeros by feeding the input signal into portions within the control circuit is realized correctly. The actual filter
웁C1 and 움C2 of the capacitors C1 and C2. is not tuned. However, good matching and tracking can be
430 CIRCUIT TUNING
f-VCO f control
EXOR LPF 1 LPF 2
VR
Vf
To main filter
PD K –
+ VQ
Q-VCO Q model PD
Q control
Figure 8. Dual-control loop-tuning system for tuning frequency pa-
rameters and quality factors of an integrated filter. Note that the
frequency loop converges always, but for the Q loop to converge on
the correct Q value, the frequency must be correct. Details of the
operation are explained in the text.
assumed across the IC because all gm cells are on the same
chip and subject to the same error-causing effects. This as-
sumes that the ratios gi defined in Eq. (32) are not so large
that matching problems will arise and that care is taken to
account for (model the effect of) filter parasitics in the control
circuit. The same is true for the unit capacitor C in the control
loop and the filter capacitors (again, if the ratios ci are not too
large). Consequently, the control bias current IB can be sent
to all the main filter’s transconductance cells as indicated in
Fig. 7 and thereby tune the filter. Clearly, this scheme de-
pends on good matching properties across the IC chip. Accu-
rate tuning cannot be performed if matching and tracking
cannot be relied upon or, in other words, if the gm –C circuit
in the control loop is not a good representative model of the
filter cells.
An alternative method for frequency tuning [see Schau-
mann, Ghausi, and Laker (3), Sec. 7.3, pp. 418–446, and
Johns and Martin (6), Sec. 15.7, pp. 626–635] relies on phase-
locked loops [see Johns and Martin (6), Chap. 16, pp. 648–
695]. The top half of Fig. 8 shows the principle. A sinusoidal
reference signal VR at 웆 ⫽ 웆R and the output of a voltage-
controlled oscillator ( f-VCO) at 웆vco are converted to square
waves by two matched limiters. Their outputs enter an EXOR
gate acting as a phase detector whose output contains a dc
component proportional to the frequency difference ⌬웆 ⫽ 웆vco
⫺ 웆R of the two input signals. The low-pass filter LPF 1 elimi-
nates second- and higher-order harmonics of the EXOR out-
put and sends the dc component to the oscillator f-VCO, lock-
ing its frequency to 웆R. Just as the gm –C circuit in Fig. 7, the
oscillator is designed with transconductances and capacitors
to represent (model) any frequency parameter errors of the
filter to be tuned so that, relying on matching, the filter is
tuned correctly by applying the tuning signal also to its gm
cells. The low-pass filter LPF 2 is used to clean the tuning
signal Vf further before applying it to the filter.
We saw in Eq. (33) that all filter parameters depend, apart
from 웆u, only on ratios of like components and are, therefore,
accurately manufacturable and should require no tuning.
This is indeed correct for moderate frequencies and filters
with relatively low Q. However, Q is extremely sensitive [see
Schaumann, Ghausi, and Laker (3), Chap. 7, pp. 410–486] to
small parasitic phase errors in the feedback loops of active
filters, so that Q errors may call for tuning as well, especially
as operating frequencies increase. The problem is handled in
much the same way as frequency tuning. One devises a model
(the Q-model in Fig. 8) that represents the Q errors to be
expected in the filter and encloses this model circuit in a con-
trol loop where feedback acts to reduce the error to zero. Fig-
ure 8 illustrates the principle. In the Q control loop, a Q-VCO
(tuned correctly by the applied frequency control signal Vf )
sends a test signal to the Q model that is designed to repre-
sent correctly the Q errors to be expected in the filter to be
tuned, and through a peak detector PD to an amplifier of gain
K. K is the gain of an accurately designable dc amplifier. Note
that the positions of PD and K could be interchanged in prin-
ciple, but a switch would require that K is the less well-con-
trolled gain of a high-frequency amplifier. The output of the
Q model goes through a second (matched) peak detector.
Rather than measuring Q directly, which is very difficult in
practice, because it would require accurate measurements of
two amplitudes and two frequencies, the operation relies on
the fact that Q errors are usually proportional to magnitude
errors. The diagram in Fig. 8 assumes that for correct Q the
output of the Q model is K times as large as its input so that
for correct Q the inputs of the comparator are equal. The dc
error signal VQ resulting from the comparison is fed back to
the Q model circuit to adjust the bias voltages appropriately,
as well as to the filter. In these two interacting control loops,
the frequency loop will converge independently of the Q con-
trol loop, but to converge on the correct value of Q, the fre-
quency must be accurate. Hence, the two loops must operate
together. The correct operation and convergence of the fre-
quency and Q control scheme in Fig. 8 has been verified by
experiments [see Schaumann, Ghausi, and Laker (3), Chapter
7, pp. 410–486] but because of the increased noise, power con-
sumption, and chip area needed for the control circuitry, the
method has not found its way into commercial applications.
BIBLIOGRAPHY
1. G. Moschytz, Linear Integrated Networks: Design. New York: Van
Nostrand-Reinhold, 1975
2. P. Bowron and F. W. Stevenson, Active Filters for Communica-
tions and Instrumentation. Maidenhead, UK: McGraw-Hill, Ltd.,
1979.
3. R. Schaumann, M. S. Ghausi, and K. R. Laker, Design of Analog
Filters: Passive, Active RC and Switched Capacitor. Englewood
Cliffs, NJ: Prentice-Hall, 1990.
4. W. E. Heinlein and W. H. Holmes, Active Filters for Integrated
Circuits. Munich: R. Oldenburg, 1974.
5. E. Christian, LC Filters: Design, Testing and Manufacturing. New
York: Wiley, 1983.
6. D. A. Johns and K. Martin, Analog Integrated Circuit Design. New
York: Wiley, 1997.
7. Y. Tsividis and J. A. Voorman, Eds., Integrated Continuous-Time
Filters: Principles, Design and Implementations. Piscataway, NJ:
IEEE Press, 1993.
8. J. F. Parker and K. W. Current, A CMOS continuous-time band-
pass filter with peak-detection-based automatic tuning. Int. J.
Electron., 1996 (5): 551–564, 1996.
ROLF SCHAUMANN
Portland State University
 CLIENT–SERVER SYSTEMS 431

CIRCULAR BIREFRINGENCE. See CHIRALITY.

CIRCULAR DICHROISM, MAGNETIC. See MAGNETIC
STRUCTURE.
CIRCULATORS, NUMERICAL MODELING. See NU-
MERICAL MODELING OF CIRCULATORS.
CLEAR WRITING. See DOCUMENT AND INFORMATION
DESIGN.
562 COMBINATIONAL CIRCUITS

COMBINATIONAL CIRCUITS

Combinational (combinatorial) circuits realize Boolean func-

tions and deal with digitized signals, usually denoted by 0s
and 1s. The behavior of a combinational circuit is memory-
less; that is, given a stimulus to the input of a combinational
circuit, a response appears at the output after some propaga-
tion delay, but the response is not stored or fed back. Simply
put, the output depends solely on its most recent input and is
independent of the circuit’s past history.
Design of a combinational circuit begins with a behavioral
specification and selection of the implementation technique.
These are then followed by simplification, hardware synthe-
sis, and verification.
Combinational circuits can be specified via Boolean logic
expressions, structural descriptions, or truth tables. Various
implementation techniques, using fixed and programmable
components, are outlined in the rest of this article. Combina-
tional circuits implemented with fixed logic tend to be more
expensive in terms of design effort and hardware cost, but
they are often both faster and denser and consume less
power. They are thus suitable for high-speed circuits and/or
high-volume production. Implementations that use memory
devices or programmable logic circuits, on the other hand, are
quite economical for low-volume production and rapid proto-
typing, but may not yield the best performance, density, or
power consumption.
Simplification is the process of choosing the least costly im-
plementation from among feasible and equivalent implemen-

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

tations with the targeted technology. For small combinational
circuits, it might be feasible to do manual simplification based
on manipulating or rewriting logic expressions in one of sev-
eral equivalent forms. In most practical cases, however, auto-
matic hardware synthesis tools are employed that have
simplification capabilities built in. Such programmed simpli-
fications are performed using a mix of algorithmic and heuris-
tic transformations. Verification refers to the process of ascer-
taining, to the extent possible, that the implemented circuit
does in fact behave as originally envisaged or specified.
A half adder is a simple example of a combinational circuit.
The addend, augend, carry, and sum are all single binary dig-
its or bits. If we denote the addend as A and the augend as
B, the Boolean function of carry-out Co and sum S can be writ-
ten as
Co = AB
S = A ⊕ B = AB + AB
The carry-out and sum functions can also be specified in the
form of a truth table with eight rows (corresponding to the
eight possible combinations of values for the three Boolean
inputs) and two columns in which the values of Co and S are
entered for each of the eight combinations.
The process of designing combinational circuits involves
certain levels of abstraction. For structured circuit implemen-
tation, the key is to find high-level building blocks that are
sufficiently general to be used for different designs. While it
is easy to identify a handful of elements (such as AND, OR,
and NOT gates) from which all combinational circuits can be
synthesized, the use of such simple building blocks reduces
the component count by only a modest amount. A more sig-
nificant reduction in component count may be obtained if each
building block is equivalent to tens or hundreds of gates.
A commonly used building-block approach is based on
array structures. Programmable logic devices (PLDs) are com-
posed of primitive gates arranged into logic blocks whose con-
nections can be customized for realizing specific functions.
Programmable elements are used to specify what each logic
block does and how they are combined to produce desired
functions. This fundamental idea is used in connection with
various architectures and fabrication technologies to imple-
ment a wide array of different PLDs.
IMPLEMENTATIONS WITH FIXED LOGIC
If the input-output behavior of the combinational circuit is
defined by means of a logic statement, then the statement can
be easily expressed in sum-of-products form using Boolean al-
gebra. Once in this form, its implementation is a relatively
straightforward task. In the following, we will consider the
A A
B D C D
C B
Not-and-or Nor-only
Figure 1. Realizing the Boolean function D ⫽ AB ⫹ BC by gate networks.
COMBINATIONAL CIRCUITS 563
implementation of combinational circuits using gate networks
and multiplexers. These are fixed (as opposed to programma-
ble) logic devices in the sense that they are used by suitably
interconnecting their input/output terminals, with no modifi-
cation to the internal structures of the building blocks.
Using Gate Networks
Let us begin with the Boolean function D defined as
D = AB + BC
where A, B, and C are input variables whose values can be
either 0 or 1. Direct implementation based on the preceding
expression would require three chips: one that contains in-
verters (such as 7404), one that contains two-input AND
gates (such as 7408), and one that contains two-input OR
gates (such as 7432). Rewriting the logic expression for D as
D = B(A + C )
reduces the number of gates from 4 to 3, but does not affect
the component or chip count discussed in the preceding.
By applying DeMorgan’s theorem, we can derive an equiv-
alent logic expression for our target Boolean function that can
be implemented using a single chip containing only NOR
gates (such as 7402).
D = B + (A + C)
Similarly, DeMorgan’s theorem allows us to transform the
logic expression into one whose implementation requires only
NAND gates:
D = (AB)(BC)
Figure 1 shows the three gate network implementations of D
using NOT-AND-OR, NOR, and NAND gates, as discussed
in the preceding. The output D of such a combinational gate
network becomes available after a certain delay following the
application of its inputs. With gate-level components, the in-
put-to-output delay, or the latency, of a combinational circuit
depends on the number and types of gates located on the
slowest path from an input terminal to the output. The num-
ber of gate levels is a rough indicator of the circuit’s latency.
Practical combinational circuits may contain many more
gates and levels than the simple examples shown in Fig. 1.
As combinational circuits are often placed between synchro-
nously clocked storage elements, or latches, the circuit’s la-
tency dictates the clock rate and, thus, the overall system
speed. One way to improve the computation rate, or
throughput, is to partition the gates into narrow slices, each
A
B D
C
Nand-only
564 COMBINATIONAL CIRCUITS

Latches

...

...

...

...

...
Inputs Outputs

Figure 2. Schematic of a pipelined combina-

tional circuit. Clock

consisting of only a few levels, and buffer the signals going
from one slice to the next in latches. In this way, the clock
rate can be made faster and a new set of inputs processed in
each clock cycle. Thus, the throughput improves while both
latency and cost deteriorate due to the insertion of latches
(see Fig. 2).
Today, digital implementation technologies are quite so-
phisticated and neither cost nor latency can be easily pre-
dicted based on simple notions such as number of gates, gate
inputs, or gate levels. Thus, the task of logic circuit imple-
mentation is often relegated to automatic synthesis or CAD
tools. As an added benefit, such tools can take many other
factors, besides cost and latency, into account. Examples of
such factors include power consumption, avoidance of haz-
ards, and ease of testing (testability).
Using Multiplexers
The application of discrete logic circuits becomes impractical
as our Boolean expression grows in complexity. An alterna-
tive solution might be the use of a multiplexer. To implement
the Boolean function with a multiplexer, we first expand it
into unique minterms; each of which is a product term of all
the variables in either true or complement form
D = AB(C + C) + (A + A)BC = ABC + ABC + ABC
With L input variables, there are 2L possible minterms, each
corresponding to one data line of a 2L-to-1 multiplexer. Figure
3 shows an 8-to-1 multiplexer and the logic expression for its
output. A 2L-to-1 multiplexer can be used to implement any
desired L-variable Boolean function by simply connecting the
input variables to its select lines, logic 1 to the data lines
corresponding to the minterms, and logic 0 to the remaining
data lines. The select inputs s2, s1, and s0, when viewed as a
3-bit binary number, represent an index i in the 0 to 7 range.
The value on data line xi is then chosen as the output.
To implement a Boolean function with more variables than
can be accommodated by a single multiplexer, we can connect
other multiplexers to the xi inputs to obtain a multilevel mul-
tiplexer realization. For example, to implement a 6-variable
function, we can expand it in terms of three of the variables
to obtain an expression similar to the one shown on the out-
put in Fig. 3, where the xi are residual functions in terms of
the remaining variables.
Figure 4 shows how the function D can be implemented by
an 8-to-1 multiplexer. We can view the single wire entering
each AND gate as representing multiple inputs. In effect, we
have an 8-bit memory whose hardwired data are interrogated
by the input variables; the latter information filters through
the decoder, which finds the corresponding data line and se-
lects it as the output.
With a multiplexer that can supply both the output D and
its complement D, we can choose to tie the minterms to logic
1 and the remaining data lines to logic 0, or vice versa. This,
again, is an application of DeMorgan’s theorem.
A 2L-to-1 multiplexer can be implemented as an L-level
network of 2-to-1 multiplexers. This becomes clear by noting
that a 2-to-1 multiplexer is characterized by the equation

s2 s1 s0 Y = sx0 + sx1

0 and that the output logic expression for the 8-to-1 multiplexer
x0
of Fig. 3, say, can be written as:
x1 1
Y = s2 ( s1 ( s0 x0 + s1 x1 )) + s1 ( s0 x2 + s0 x3 ))
x2 2 + s2 ( s1 ( s0 x4 + s0 x5 )) + s1 ( s0 x6 + s0 x7 ))
s2 s1 s0 x0 + s2 s1 s0 x1
x3 3 Another way to justify the preceding is to note that a 2-to-1
+ s2 s1 s0 x2 + s2 s1 s0 x3
Y
+ s2 s1 s0 x4 + s2 s1 s0 x5 multiplexer can act as a NOT, AND, or OR gate:
x4 4
+ s2 s1 s0 x6 + s2 s1 s0 x7
NOT: x0 = 1, x1 = 0 yields Y =s
x5 5
AND: x0 = 0 yields Y = sx1
x6 6 OR: x1 = 1 yields Y = s + x0

x7 7 We have just concluded our examination of a simple pro-

grammable logic device. The basic elements include a means
Figure 3. A multiplexer or selector transfers one of its ‘‘data’’ inputs to store data, a decoding function to retrieve data, and an
to its output depending on the values applied to its ‘‘select’’ inputs. association of data with logic values. In the case of a multi-
 COMBINATIONAL CIRCUITS 565

A B C A B C D

0 0 0
0
1
1
2
2
3
Y D 3
4
4
5
5
6
6
1 7 1
7
Figure 4. Realizing the Boolean function
Decoder
D ⫽ AB ⫹ BC by an 8-to-1 multiplexer.

plexer, the programmability is provided by manual wiring.
Slightly more complicated schemes use fuse or antifuse ele-
ments. A fuse is a low-resistance circuit element that can be
opened permanently by a relatively high surging current,
thus disconnecting its endpoints. An antifuse is the opposite
of a fuse; it is an open circuit element that can be made per-
manently low resistance. Both fuse and antifuse offer one-
time programmability (OTP). Once programmed, they cannot
be modified.
IMPLEMENTATIONS WITH MEMORY DEVICES
Multioutput Boolean functions can be implemented by several
multiplexers connected in parallel. However, it seems waste-
ful to have multiple decoders, especially when the number of
variables is large. Removing all but one of the replicated de-
coders in the multiplexers and making the hardwiring
changeable lead to a memory structure, as shown in Fig. 5.
This approach of logic being embodied in the memory content
A B C D1 D2 DN
...
...
...
Figure 5. The read path of a memory device goes through the ad-
dress decoder and the memory array. Such a device can be viewed as
a multiplexer with multiple outputs.
is the well-known table-lookup method for implementing
Boolean functions.
Table lookup is attractive for function evaluation as it
allows the replacement of irregular random logic structures
with much denser memory arrays. The input variables consti-
tute an address that sensitizes a word select line and leads to
the stored data in that particular word being gated out. As in
the case of the multiplexer, the values to be stored are related
to the minterms of the Boolean function. Thus, the content of
each memory column in Fig. 5 is the truth table of the associ-
ated output function.
Figure 6 shows the use of an 8 ⫻ 2 bit memory device to
implement a full adder. The full adder is a half adder aug-
mented with a single-bit carry-in Ci and is specified by the
Boolean functions
Co = AB + ACi + BCi
S = A ⊕ B ⊕ Ci = ABCi + ABCi + ABCi + A BCi
In general, memory cells can be classified in two major catego-
ries: read-only memory (ROM) (in some cases, read-mostly),
which is nonvolatile, and random-access memory (RAM)
(read-write memory is a better designation), which is volatile.
They are distinguished by: (1) the length of write/erase cycle
time compared with the read cycle time; and (2) whether the
data are retained after power-off. Programmability refers to
the ability to write either a logic 0 or 1 to each memory cell,
which in some cases must be preceded by a full or partial
erasure of the memory content (such as in EPROM and EE-
PROM). In this respect, PLDs are no different and actually
use some form of memory in their structures.
Strictly speaking, implementations of Boolean functions
based on such memory devices cannot be viewed as combina-
tional. Many PLDs are in fact sequential in nature. They be-
come combinational only because the clocked latches are by-
passed. However, the programming will never occur in
operation and, in some cases, is limited to a certain maximum
number of times during the life of the device. Thus, between
programming actions, even such latched or registered PLDs
behave as truly combinational circuits.
566 COMBINATIONAL CIRCUITS

A B C Co S

Inputs Minterms Outputs

A B Ci Co S 0 0
0
0 0 0 ABCi 0 0 0 1
1
0 0 1 ABCi 0 1
0 1
0 1 0 ABCi 0 1 2
1 0
0 1 1 ABCi 1 0 3
1 0 0 ABCi 0 1 0 1
4
1 0 1 ABCi 1 0 1 0
1 1 0 ABCi 1 0 5
Figure 6. Using memory to realize a full 1 0
1 1 1 ABCi 1 1 6
adder. The memory content on the right
1 1
is in one-to-one correspondence with the 7
truth table on the left.

It is noteworthy that in Fig. 5, the programmable elements
(memory cells) along each column are wire-ORed together. In-
tuitively, the programmable elements can also be placed in
the decoder so they are wired-ANDed together along each col-
umn. These and other variations lead to different building
blocks. Programmable logic array (PLA) and programmable
array logic (PAL) are two types of building blocks that are
universally used for implementing combinational circuits in
PLDs.
IMPLEMENTATIONS WITH PROGRAMMABLE LOGIC
The memory-based implementation of Fig. 5 has the essential
feature of array logic, that is, a regular array that is program-
mable. Array logic operates by presenting an address in the
data path to the memorylike structure. Decoding of this ad-
dress starts the process whereby a predetermined result is
extracted from the array. Because the result generated by
such an array depends on the content of the array, the Bool-
ean function can, in principle, be changed in the same way as
writing into a memory.
Using Programmable Logic Arrays
Instead of expanding the product terms into minterms ex-
haustively, we take advantage of ‘‘don’t care’’ conditions to let
the decoder select more than one row simultaneously. Pro-
grammable logic devices are organized into an AND array
and an OR array, with multiple inputs and multiple outputs.
The AND array maps the inputs into particular product
terms; the OR array takes these product terms together to
produce the final expression. Figure 7 shows a block diagram
for the array component.
Figure 8 shows a commonly used scheme for representing
the topologies of PLAs. The input variables x1, x2, . . ., xL and
their complements x1, x2, . . ., xL constitute the columns of the
AND array. The rows correspond to the product terms z1, z2,
. . ., zM in both the AND and OR arrays. The columns of the
OR array represent the Boolean functions y1, y2, . . ., yN in
sum-of-products form. The complexity of PLA is determined
by the number L of inputs, the number M of product terms,
and the number N of outputs. An L-input, M-product-term, N-
output PLA is sometimes referred to as an L ⫻ M ⫻ N device.
The number of product terms is often selected to be much
smaller than 2L (for example, M ⫽ 4L). There is a penalty for
this tremendous compression. Whereas a memory device with
its full decoder can generate any function of the input vari-
ables, the partial decoder of the PLA device generates a very
limited number of product terms.
Because of the severe limitation on the number of available
product terms, an aggressive two-level logic minimization

Inputs Outputs x1 x2 xL y1 y2 yN
... ...
... ...

z1

z2
AND array OR array
(AND plane) (OR plane)
...

...

zM
Product terms
x1 x1 x2 x2 xL xL
Figure 7. The basic logic array component consists of an AND array
Figure 8. A commonly used scheme for representing the topology of
and an OR array.
array logic explicitly shows its columns and rows. The cross-points
mark the locations of programmable elements whose states may be
changed through programming.

A B
Inputs Product Outputs a
A B Ci terms Co S
1 1 – AB 1 0
1 – 1 ACi 1 0
– 1 1 BCi 1 0
1 1 1 ABCi 0 1
1 0 0 ABCi 0 1
0 1 0 ABCi 0 1
0 0 1 ABCi 0 1
a These specify the connections in the OR
array rather than output logic values.
method is critical for effective utilization of PLAs. A conve-
nient way to describe a function for PLA realization is
through a personality matrix, which is a minor reformulation
of the truth table. Figure 9 shows an example for a full adder
and the corresponding PLA realization.
For the realization of Boolean functions PLAs are widely
used within integrated circuit designs. A distinct advantage
is that their regular structures simplify the automatic genera-
tion of physical layouts. However, only a few devices are
available as stand-alone parts for combinational circuit de-
sign. Currently available configurations include 16 ⫻ 48 ⫻ 8,
18 ⫻ 42 ⫻ 10, and 22 ⫻ 42 ⫻ 10 (by Philips Semiconductors).
Multilevel logic structures can be realized with PLAs ei-
ther by interconnecting several PLAs or by connecting certain
of the outputs to the inputs in a single PLA. As an example,
an 18 ⫻ 42 ⫻ 10 PLA can implement the parity or XOR func-
tion in two-level AND-OR form for no more than six inputs.
The reason is that the seven-input XOR function has 64 min-
terms which is beyond the capacity of the preceding PLA.
Consider the problem of implementing the nine-input XOR
function. One way is to divide the inputs into three groups of
three and separately realize 3 three-input parity functions us-
ing 9 of the inputs, 12 of the product terms, and 3 of the
outputs. The preceding three outputs can then be fed back to
three of the unused inputs and their XOR formed on one of
the available outputs by utilizing four more product terms.
Using Programmable Array Logic
A more common programmable solution is to use PALs. There
is a key difference between PLAs and PALs: PLAs have the
generality that both the AND and OR arrays can be pro-
grammed; PALs maintain the programmable AND array, but
simplify the OR array by hardwiring a fixed number of prod-
uct terms to each OR gate.
For example, the commercial PAL device 16L8 (which
means that the device has 16 inputs and 8 outputs, and it is
active low combinational) arranges the AND array in 32 col-
umns and 64 rows. Each AND gate has programmable con-
nections to 32 inputs to accommodate the 16 variables and
their complements. The 64 AND gates are evenly divided into
8 groups, each group associated with an OR gate. However,
there are only 7 AND gates connected to each OR gate and,
thus, each Boolean function is allowed to have at most 7 prod-
uct terms. The remaining one AND gate from each group is
COMBINATIONAL CIRCUITS 567
C Co S
Figure 9. A personality matrix defines
the inputs, product terms, and outputs of
a PLA.
connected to a tri-state inverter right after the OR gate, as
depicted in Fig. 10. The device shown in Fig. 10 actually has
10 inputs, 2 outputs, and 6 bidirectional pins that can be used
as either inputs or outputs.
There exists a fundamental trade-off between speed and
capacity in PLDs. It is fair to say that for devices with compa-
rable internal resources, a PLA should be able to implement
more complex functions than a PAL. The reason is that the
PLA allows more product terms per output as well as product-
term sharing; that is, outputs of the AND array can be shared
among a number of different OR gates. On the other hand,
the PLA will be slower because of the inherent resistance and
capacitance of extra programmable elements on the signal
paths.
In reality, NOR-NOR arrays may be used, instead of AND-
OR arrays, to achieve higher speed and density. (Transistors
are complementary, but the N-type is more robust than the
P-type and is often the preferred choice.) Consider the full
adder example. We can rewrite the Boolean functions as fol-
lows:
Co = A B + ACi + BCi
S = A ⊕ B ⊕ Ci = A BCi + ABCi + ABCi + ABCi
The inverted inputs and outputs preserve the original AND-
OR structure so the realization is equivalent, as shown in
Fig. 11.
As in the case of PLAs, we can use several PALs to imple-
ment logic functions that are too complex for the capabilities
of a single device. Feeding back the outputs into the array in
order to realize multilevel circuits is facilitated by the built-
in feedback paths (see Fig. 10). As an example, to implement
the 9-input XOR function using the PAL device 16L8 shown
in Fig. 10, we can divide the inputs into three groups of 3
and proceed as we did for the PLA implementation. The only
difference is that the feedback paths are internal and no ex-
ternal wiring is needed.
Other PLD Variants
Generic array logic (GAL) is a slight enhancement of PAL
that includes an XOR gate after each OR gate. The XOR gate
can be viewed as a controlled inverter that changes the out-
put polarity if desired. Given that y 丣 0 ⫽ y and y 丣 1 ⫽ y,
568 COMBINATIONAL CIRCUITS

1
0

19

7
2
8

18

15
3
16

17

23
4
24

16

31
5
32

15

39
6
40

14

47
7
48

13

55
8
56

12

63
9 11

0 3 4 7 8 11 12 15 16 19 20 23 24 27 28 31

Figure 10. Schematic diagram of the PAL device 16L8 known as its programming map. Loca-
tions to be programmed are specified by their numbers (11-bit integers in the range 0 to 2047,
composed of a 6-bit row number and a 5-bit column number).

A B Ci Co S In order to cover most designs, PLDs are organized to bal-
Figure 11. The implementation of a full adder in PAL using NOR
gates is equivalent to that using AND and OR gates. The figure as-
sumes that four product terms are tied to each sum term.
we can choose to implement a Boolean function directly or
generate its complement and then invert it. As an extreme
example, y ⫽ x1 ⫹ x2 ⫹ ⭈ ⭈ ⭈ ⫹ x16 cannot be implemented by
PAL16L8, but it can be easily realized by a similar device
that includes the aforementioned XOR gates through imple-
menting y ⫽ x1 x2, . . ., x16 and then complementing the re-
sult. It is therefore not surprising that most PALs now allow
one to control their output polarity through an XOR gate or
with a multiplexer that chooses the true or complement
result.
The ultimate in flexibility is provided by field-programma-
ble gate arrays (FPGAs) which consist of a regular array of
logic blocks with programmable functionalities and intercon-
nections. Figure 12 shows part of a generic FPGA component.
Each block can implement one or more simple logic functions,
say of four or five logic variables. The inputs to the block can
be taken from its adjacent horizontal or vertical signal tracks
(channels) and its output(s) can be routed to other blocks via
the same channels. The logic blocks of an FPGA store their
outputs in storage elements, thus making the result a sequen-
tial circuit. Combinational circuits can be implemented by
programmed bypassing of the storage elements.
Logic
block
Figure 12. Part of an FPGA, consisting of four rows and two columns
of logic blocks and their associated programmable interconnections
(channels). The upper left logic block has been configured to receive
three inputs from its upper and lower horizontal channels and to send
its output to the logic block at the lower right via a vertical and a
horizontal channel segment.
COMBINATIONAL CIRCUITS 569
ance speed and capacity within the constraints of fabrication
technologies. Because the assemblages of logic blocks are po-
sitioned where they are anticipated to be useful to each other,
such an approach is necessarily wasteful. There were once
expectations that PLDs could replace discrete components.
While this has not yet materialized, PLDs do indeed offer a
compact means of implementing Boolean functions that is
particularly attractive for rapid prototyping to evaluate possi-
ble improvements or to verify new ideas.
Reading List
Advanced Micro Devices, PAL Device Data Book, 1996.
J. W. Carter, Digital Designing with Programmable Logic Devices,
Englewood Cliffs, NJ: Prentice-Hall, 1997.
H. Flesher and L. I. Maissel, An introduction to array logic, IBM J.
Res. Develop., 19 (2): 98–109, 1975.
J. W. Jones, Array logic macros, IBM J. Res. Develop., 19 (2): 120–
126, 1975.
R. H. Katz, Contemporary Logic Design, Redwood City, CA: Benjamin/
Cummings, 1994.
Lattice Semiconductor, Introduction to GAL device architectures,
ISP Encyclopedia, 1996.
Philips Semiconductors, Programmable Logic Devices Data Hand-
book, 1993.
K. Tsuchiya and Y. Takefuji, A neural network approach to PLA fold-
ing problems, IEEE Trans. Comput.-Aided Des. Integr. Circuits
Syst., 15: 1299–1305, 1996.
BEHROOZ PARHAMI
DING-MING KWAI
University of California
COMBINATORIAL DESIGN THEORY. See THEORY OF
DIFFERENCE SETS.
COMBINATORIAL OPTIMIZATION PROBLEMS.
See GRAPH THEORY.
COMBINERS AND DIVIDERS, POWER. See POWER
COMBINERS AND DIVIDERS.
COMMERCE, ELECTRONIC. See ELECTRONIC DATA IN-
TERCHANGE.
COMMUNICATION CHANNEL NOISE. See NOISE
AND INTERFERENCE MODELING.
COMMUNICATION FOR LOCATING MOBILE US-
ERS. See PAGING COMMUNICATION FOR LOCATING MOBILE
USERS.
COMMUNICATION, INTERNATIONAL. See INTER-
NATIONAL COMMUNICATION.
COMMUNICATION, MILITARY. See MILITARY COMMU-
NICATION.
COMMUNICATION PROTOCOLS. See COMPUTER
COMMUNICATIONS SOFTWARE.
COMMUNICATIONS. See SPEECH, HEARING AND VISION.
COMMUNICATIONS, COMPUTER. See COMPUTER
NETWORKS.
COMMUNICATIONS, METEOR BURST. See METEOR
BURST COMMUNICATION.
570 COMPANDORS

COMMUNICATIONS, MULTIPLE USERS. See MULTI-

PLE ACCESS MOBILE COMMUNICATIONS.
COMMUNICATIONS SOFTWARE, COMPUTER.
See COMPUTER COMMUNICATIONS SOFTWARE.
COMMUNICATION THEORY. See INFORMATION
THEORY.
COMMUNICATION USING POWER LINES. See
POWER LINE COMMUNICATION.
COMPACT DISK READ ONLY. See CD-ROMS, DVD-
ROMS, AND COMPUTER SYSTEMS.
COMPACT MODELS. See NONLINEAR NETWORK ELE-
MENTS.
 COMPARATOR CIRCUITS 577

COMPARATOR CIRCUITS

Comparators are used to detect the sign of the difference be-

tween two analog signals x⫹(t) and x⫺(t), and to codify the
outcome of the detection through a digital signal y. This oper-
ation can be formulated as follows:

> EOH for x+ (t) > x− (t)
y= (1)
< −EOL for x+ (t) < x− (t)

where EOH and ⫺EOL are levels that guarantee correct logic
interpretation of the output signal, that is, y ⬎ EOH guaran-
tees that the output is unambiguously interpreted as a true
logic one (1D) by any digital circuit connected to the output
node, whereas y ⬍ ⫺EOL guarantees that the output is inter-
preted as a true logic zero (0D). The definition of these levels
is related to the concepts of logic restoration and digital noise

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.
578 COMPARATOR CIRCUITS
(a) y (b)
ESH ESH
(0,0) x (0,0)
–ΓL ΓH –ΓL
–ESL –ESL
Figure 1. Some useful extensions of the binary comparator concept.
margins that the interested readers will find in Ref. 1. In
many applications one of the inputs is a reference value, say
x⫺(t) ⫽ E, and the comparator function is to detect whether
the signal applied to the other input, say x⫹(t) ⫽ x(t), is larger
or smaller than such reference.
Comparators are classified according to the physical na-
ture of their inputs and output. The most significant struc-
tures for practical applications have voltage input and voltage
output and are called voltage comparators. Most of this article
is devoted to them. Others that are also of interest for the
newest class of current-mode circuits that have current-input
and voltage-output—current comparators—are also covered
in this article.
Another criterion for classifying comparators is their oper-
ation in the time domain. Continuous time (CT) comparators
operate asynchronously. They respond to input changes at
any time instant. The speed of change is limited only by the
intrinsic comparator response. On the other hand, discrete-
time (DT) comparators operate in synchronization with a
clock signal. They respond only at some prescribed time inter-
vals (called compare, or active, intervals), whereas others
(called reset, or strobe, intervals) are used to establish initial
conditions. In many applications synchronization is imposed
by system-level timing considerations. But, even when syn-
chronization is not mandatory, DT operation can be used for
error correction. On the other hand, although DT comparator
speed is limited by clock frequency, proper architectures en-
able operation in the video range and above. Overall re-
sponses faster than with CT comparators might even be
achieved through proper design.
Comparators are the basic building blocks of analog-to-dig-
ital converters. Hence they are crucial components for realiz-
ing the front-ends of the newest generations of mixed-signal
electronic systems (2). Mixed-signal systems are those which
combine analog and digital signals. Most modern electronic
systems are mixed-signal. They handle analog signals at the
input and output interfaces and perform most of the pro-
cessing, control, and memory tasks by using digital tech-
niques. Other comparator applications include such diverse
areas as signal and function generation (3), digital communi-
cations (4), or artificial neural networks (5), among others.
Because in these applications the prevalent trend is towards
microelectronic realizations, this article emphasizes those is-
sues related to the realization of comparators as integrated
circuit components. There are also a few extensions of the
basic comparator concept of Eq. (1) which further increase the
scope of comparator application. Figure 1 shows transfer
characteristics for some typical extensions, namely: the hys-
teresis comparator [Fig. 1(a)] (This device has memory. Once
y (c) y
(0,0)
x x
ΓH
the output is in the high state, it remains there whenever the
input remains larger than ⫺⌫L. On the other hand, once the
output is in the low state, it remains there whenever the in-
put remains smaller than ⌫H.), the window comparator [Fig.
1(b)], and the M-ary (multilevel) comparator [Fig. 1(c)] not
covered in this article.
COMPARATOR BEHAVIOR
Ideal Comparator Behavior
Figure 2(a) illustrates the ideal comparator operation, where
⫺ESL and ESH are saturation levels for the output signal. The
interval defined by these levels is usually wider than that de-
fined by the restoring logic level’s logic. According to Eq. (1)
the output is at the high logic state whenever the differential
input x(t) ⬅ x⫹(t) ⫺ x⫺(t) is positive, and at the low logic state
otherwise. Thus, the ideal transfer characteristic exhibits a
step transition at x ⫽ 0, as Fig. 2(a) illustrates. On the other
hand, ideally the transitions between the two output states
should happen instantaneously following any change of the
sign of x(t), also illustrated in Fig. 2(a).
Let us focus on voltage comparators. Ideal voltage compar-
ators have the following features:
• infinitely large voltage gain [equivalently, infinitely
small transition region between the output states, or the
capability of detecting infinitely small values of x(t)]
• zero input offset voltage (meaning that the transitions
occurs at x ⫽ 0)
• zero delay (meaning that changes in the sign of the ana-
log input voltage x(t) are transmitted instantaneously to
the output)
• infinitely large variation range for the common-mode in-
put voltage (meaning that the operation should depend
only on the input voltage difference, not on the value of
the positive and negative components despite how small
or large these components are)
• infinitely large input impedance and unlimited driving
capability at the output node
Correspondingly, ideal current comparators must have infi-
nitely large transimpedance gain, zero input offset current,
zero delay, infinitely large range for the common-mode input
current, zero input impedance, and unlimited driving capabil-
ity at the output node.
There is no practical voltage or current comparator circuit
capable of realizing all of these ideal features. Actual com-
 COMPARATOR CIRCUITS 579

y
y(t) ESH
ESH
EOH
x(t) = x+ (t) – x– (t)
t x
(0,0)
–EOL
–ESL –ESL

(a)

x(t)
EOS y y
EOH
EOS
–2∆s

(0,0) x (0,0) x
(0,0) t
–EOL
T1 T2 T3 T4 2∆s

(b) (c) (d)

y(t) y(t) y(t)

ESH
EOH

(0,0) (0,0) (0,0)

t t t

–EOL
–ESL
T1 T2 T3 T4 T1 T2 T3 T4 T1 T2 T3 T4

(e) (f) (g)

y(t)
ESH EOH EOH
EOH y(t) y(t)
x(t) ξD x(t)

(0,0) t t=0 t

TC
–EOL (0,0) t
TA
–ESL
T1 T2 T3 T4 TD Figure 2. (a) Ideal comparator operation.
(b)–(j) Illustrating static and dynamic er-
(h) (i) (j) rors in the comparator response.

parator behavior deviates from the ideal comparator illus-
trated in Fig. 2(a). Depending on how large the deviations
are, comparator circuits may qualify for some applications
and not for others. Thus, comparator users should quantify
the maximum allowed deviations through a proper set of spec-
ification parameters, and comparator designers should try to
fulfill these specifications when implementing a comparator
circuit.
Nonideal Comparator Behavior and Comparator Specification
Consider the input waveform shown in Fig. 2(b) whose sign
changes at the time instants T1, T2, T3, and T4. Figure 2(e)
shows the corresponding ideal output waveform. On the other
hand, Figs. 2(f)–(h) show erroneous waveforms. To under-
stand the causes and meaning of these errors, first let us as-
sume that the instantaneous transient response feature is re-
tained. Then the error sources are comparator finite gain and
580 COMPARATOR CIRCUITS
offset. First consider the effect of finite gain. It results in the
transfer characteristic of Fig. 2(c), whose transition region
(shaded in the figure) is not abrupt. Because the input values
inside this transition region are not large enough to drive the
output voltage to a logical state, their sign is not correctly
coded, as Fig. 2(f) shows. For simplicity, it has been assumed
that this transition region is symmetrical around the origin
(equivalently, the central piece of the transfer characteristic
is linear and EOH ⫽ EOL). However, in the more general case,
this symmetry constraint should be removed for proper
analysis.
Now consider the added influence of input offset voltage.
Figure 2(d) shows the transfer characteristics where the zero
crossing is shifted to EOS. Consequently, sign codification is
incorrect for all positive levels smaller than EOS ⫹ ⌬S, as illus-
trated in Fig. 2(g). Now assume that the gain is infinite and
the input offset is zero. Then errors may appear because the
intrinsic transient comparator response. Because the com-
parator takes a finite time to react to the input changes, the
comparator output may be unable to follow the fastest input
transitions, as illustrated in Fig. 2(h) for the input change
at T2.
The errors due to nonideal comparator behavior can be an-
ticipated through proper specification of the comparator reso-
lution and transient response (6). Resolution of the comparator
under static excitation is characterized by the following speci-
fication parameters,
• ⌬S (incremental static sensitivity) defined as the input in-
crease (decrease) needed to drive the output voltage to
EOH (⫺EOL) from the central point of the transfer charac-
teristics. This is closely related to the static gain kS 앒
(EOH ⫹ EOL)/(2⌬S). The larger this gain, the smaller ⌬S,
and hence the more sensitive the comparator. Rigorously
speaking and because EOH ⬆ EOL, two different incremen-
tal sensitivities should be defined, one for positive excur-
sions ⌬S⫹ and other for negative excursions ⌬S⫺. However,
for simplicity both are considered equal.
• EOS (input offset) defined as the input level required to
set the output voltage at the central point of the transfer
characteristics.
From these parameters, the comparator static resolution is
calculated as
ξS = |EOS | + S (2)
where the modulus is used because the offset is essentially
a random variable. For any input level inside the interval
[⫺␰S, ␰S] the comparator digital output state is uncertain. On
the other hand, any input level outside this interval is called
an overdrive. The overdrive variable measures how far from
this interval the actual input is: 兩xovd兩 ⫽ 兩x兩⫺␰S.
Parameters used to characterize the comparator transient
operation include the following:
• TD (delay time) defined as the time required for the com-
parator output voltage to emerge from a saturated state,
either at ESH or at ⫺ESL, and to start evolving to the other
after a falling/rising input edge among two overdrive lev-
els [see Fig. 2(i)]. A closely related figure is the TC (re-
sponse, or comparison time), which measures the time in-
terval between the falling/rising input edge and the
instant where the output reaches the corresponding re-
storing logic level [see Fig. 2(i)]. For completeness, the
rise TR and fall TF times might also be considered. As is
conventional in digital circuits, they are defined as the
time between 10% and 90% of the total output swing.
• TA (amplification time) defined as the time needed for the
output to reach a restoring logic level, starting from
steady state at the central point of the characteristics
and following the application of an overdrive with ampli-
tude ␰D ⫽ 兩EOS兩 ⫹ ⌬D [see Fig. 2(j)]. Generally this time
differs for positive and negative excursions. For simplic-
ity we assume full symmetry and calculate TA from the
following expression:
y(t)|t=T
EOH = y(t)|t=T = A
D ≡ k D D (3)
A D
It shows that the output value at t ⫽ TA is obtained by
multiplying the incremental input ⌬D by a number kD
that represents the equivalent dynamic gain featured
after a time TA. On the other hand, parameter ⌬D defines
the incremental dynamic sensitivity, and ␰D defines the
dynamic resolution, both functions of TA. When the out-
put waveform is monotonic and bounded and assuming
⌬D ⫽ ⌬S, Eq. (3) shows that kD ⬍ kS ᭙TA finite, and that
kD 씮 kS, for TA 씮 앝. It means that the dynamic resolu-
tion parameter ␰D is larger than the static one, that is ␰D
poses a stronger constraint on resolution than ␰S. On the
other hand, Eq. (3) highlights a tradeoff between resolu-
tion and speed, that is, the smaller TA, the smaller the
dynamic gain, and hence, the less sensitive the compar-
ator.
Because discrete-time comparators are driven to their central
point during the reset phase, the amplification time is partic-
ularly pertinent for them. It is complemented with the reset
time TR, defined as the time needed for the output to evolve
from a logic state to reach the steady state at the central
point.
Commonly, timing parameters for falling edges differ from
those for rising edges. To distinguish between rise and fall
parameters, an additional subscript, ‘‘r’’ for rising and ‘‘f ’’ for
falling, is used with TD, TC, TA, and TR. Thus, TAr denotes the
amplification time for a rising edge. On the other hand, be-
cause the output waveform depends on the input signal level,
this level should be indicated when specifying delay, compari-
son, and amplification times.
ONE-STEP VOLTAGE COMPARATORS
Concept and Circuits
Equation (1) and the transfer characteristics of Figs. 2(a), (c),
and (d) show that the voltage comparator function consists of
amplifying a voltage difference while it is transmitted from
input to output. There are several circuit architectures for
achieving this. Each one features different properties for
static and dynamic behavior. Figure 3(a) shows the symbol,
and Fig. 3(b) shows a first-order behavioral model for the sim-
plest architecture. Such a model is representative of a wide
 Gm(x) Co Go(y) y
ESH
slope( gm/go )
+ +
x + IB Gm(x) Go(y) x
– – y slopegm slopego
– – δm –ESL
x –ESL x
δm ESH
(a) (b) (c)

Node + Node – Node + Node –

∆i+ ∆i– ∆i+ ∆i–

x+ MNd MNd x– x+ BN BN x–

IB IB
MNB MNB

(d)

MP11 MP11 MP12 VBP

MP1 MP1 MP1 MP1

MP12
∆i+ ∆i– ∆i– ∆i+ y ∆i+ ∆i– MCP MCP
VCP
Node + Node – Node – Node +
Node + Node –
MN1 MN1 y
(e)

MCN MCN

(f) VCN
MN1 MN1

MP1 MP1 MPB

I y + y+ (g)
y–
IB
2
∆i+ ∆i– MP MPB MPB

x– y y
x+ x– IB
MNd MNd IB
MN x– MN

MNB MNB

(h) (i) (j)

Figure 3. One-step voltage comparators.

581
582 COMPARATOR CIRCUITS

Table 1. Model Parameters of One-Step CMOS Comparator Structures

Param. ➛
gm 웃m go Co
Structure
➛

冉 冊
CL ⫹
AOTAC IB 1 1 nNdWNdCGD0Nd ⫹
⫹
2 VANd VAPl nPlWPlCGD0Pl

冉 冊
CL ⫹
SOTAC IB 1 1 nNlWNlCGD0Nl ⫹
⫹
2 VANl VAPl2 nPl2WPl2CGD0Pl2

冪 冉冊 冪 冉冊
nNdIB 1 I 3B

冪2 n Nd
冉冊
웁0Nd W
L Nd
IB 2웁0Nd
W
L Nd
4VANlVACN
2
웁0CN W
nCN L CN
CL ⫹
FOTAC ⫹ nCNWCNCGD0CN ⫹
nCPWCPCGD0CP

冪 冉冊
1 I 3B
VAPIVACP 웁0CP W
2
nCP L CP

冉 冊
CL ⫹
FDPC IB 1 1 nNdWNdCGD0Nd ⫹
⫹
2 VANd VAPl nPlWPlCGD0Pl

2
웁0N W
N
冪n 冉冊
L N
IQ IQ 冉 1
⫹
1
VAN VAP
冊 CL ⫹
CInvC ⫹ nNWNCGD0N ⫹

冉冊
nPWPCGD0P
웁0P W
冪
Not
2 IQ
nP L P applicable

冉冊 冉 冊
CL ⫹
웁0,N W
InvC 2冪 nN L N
IB IB
1
⫹
1
VAN VAPB
nNWNCGD0N ⫹
nPBWPBCGD0PB

catalog of circuit implementations, using either BJTs or
MOSTs.
The model of Fig. 3(b) consists of connecting a transcon-
ductor and a resistor, plus a capacitor to represent the un-
avoidable parasitic dynamics, and obtains the voltage gain in
a single step, as the product of transconductance gm and resis-
tance ro ⫽ g⫺1o , so that kS ⫽ gmro ⫽ gm /go. It is shown at the
transfer characteristic of Fig. 3(c) where it has been assumed
that 兩웃m(gm /go)兩 Ⰷ (ESH, ESL) which is fulfilled by all well-be-
haved practical circuits.
The transconductor of Fig. 3(b) is commonly realized in
practice through a differential pair [Fig. 3(d)] shows realiza-
tions using MOSTs and BJTs, respectively) (7). With small
variations of the differential input voltage x ⫽ x⫹ ⫺ x⫺ around
the quiescent point (defined by x⫹ ⫽ x⫺ ⫽ 0), these pairs pro-
duce incremental currents ⌬i⫹ ⫽ ⫺⌬i⫺ ⫽ gm(x/2). On the other
hand, large values of x produce saturated transconductor
characteristics similar to those in Fig. 3(b). The resistor of
Fig. 3(b) is commonly built by using an active-load transistor-
based configuration. Figures 3(e)–(g) show three CMOS alter-
natives (7). By connecting each of these active loads to the
CMOS differential pair of Fig. 3(d), three one-step CMOS
comparator structures are obtained, called, respectively, AO-
TAC [Fig. 3(e)], SOTAC [Fig. 3(f)] and FOTAC [Fig. 3(g)]. For
purposes of illustration, the first three rows in Table 1 in-
cludes expressions for the pertinent model parameters of
and the zero-bias threshold voltage VT0 (see Appendix I for a
simplified MOST model).
Some practical one-step comparators provide a differential
output voltage given as the difference between the voltages at
the output terminals of symmetrically loaded differential
pairs. In such cases the differential-pair bias current (hence-
forth called tail current) must be controlled through feedback
circuitry to stabilize and set the quiescent value of the com-
mon-mode output voltage (8). Figure 3(h), where the common-
mode regulation circuitry has not been included, shows a
CMOS circuit realization called FDPC. The fourth row in Ta-
ble 1 shows the corresponding model parameter expressions.
In some applications it is also possible to use logic invert-
ers as one-step comparators. Figures 3(i) and (j) show two
CMOS examples (9), called CInvC and InvC, respectively. The
fifth and sixth rows in Table 1 contain their corresponding
model parameter expressions. These structures have only the
negative input x⫺ accessible, whereas the positive input x⫹ is
set to an internal reference given approximately by

β
β
P
(VDD − |VT0P |) + N
(VSS + VT0N )
x+ ≡ E ≈
nP

β
β nN
for CInvC
P
+ N

nn I P nN

these one-step comparators as functions of the transistor x+ ≡ E ≈ VSS + VT0N + N B

for InvC (4)
sizes, the large-signal MOST transconductance density 웁0, βN
 COMPARATOR CIRCUITS 583

This feature constrains the usefulness of these circuits as iso- tion limit, that is, as ⌬D 씮 ⌬S ⫽ EOH /kS. Because then it is not
lated comparators. They are used mostly as components of possible to assume TA Ⰶ ␶0, Eq. (6) cannot be approximated,
multistage comparator architectures. and the resolution for speed tradeoff is given by
 
Static and Dynamic Gain in One-Step Comparators

T  
  
k S D 1
The static resolution of the one-step comparator is given by D A
= EOH 
 E ln  (10)
τu 1 EOH 
OH 1−
EOH go k S D
ξS ≈ |EOS | + = |EOS | + EOH (5)
kS gm
Consider ⌬D 앒 ⌬S(1 ⫹ ⑀) with ⑀ Ⰶ 1. Equation (10) can be
Hence, it is limited by the input offset voltage and by the simplified to obtain a relationship between the static gain and
amount of voltage gain which can be realistically built into a the amplification time needed to obtain such limiting sensitiv-
single step. It depends on technology, circuit structure, and ity;
transistor sizes. The FOTAC can obtain up to around 105,
whereas the others obtain smaller gain values. For such me-
T 
1
dium-to-large gain values, say kS ⬎ 103, the static resolution
A
= A0 ln (11)
τu 
is basically constrained by the offset voltage, whereas the con-
straint imposed by the gain dominates for lower values of kS.
where for homogeneity with subsequent discussions, the
Now let us consider the dynamic resolution. Assume that
static gain has been renamed as A0. In the limit, as ⌬D 씮 ⌬S
the capacitor in the model of Fig. 3(b) is discharged at t ⫽ 0
and ⑀ 씮 0, TA 씮 앝.
and consider a unit-step excitation of amplitude ⌬D, such that
The time-transient performance of one-step comparators is
⌬D is in the linear transconductor region. The output wave-
illustrated through a typical example with kS ⫽ 2 ⫻ 103, ␶u ⫽
form is given by
10 ns and EOH ⫽ 1 V, such that ⌬D ⫻ TA 앒 10⫺8 Vs. Thus,
gm
t
 Co ⌬D ⫽ 10 mV requires from Eq. (9), that TA 앒 1 애s, and ⌬D ⫽
y(t) = D 1 − e− τ o , where τo ≡ (6) 1 mV requires from Eq. (10) that TA 앒 14 애s. On the other
go go
hand, if the static resolution limit has to be approached
⌬D must be larger than ⌬S for monotonic comparator re- within 1%, Eq. (11) yields TA 앒 92 애s.
sponses. Here it is assumed that ⌬D Ⰷ ⌬S, so that ⌬D(gm /go) Ⰷ
EOH. This means that the output reaches the restoring level Overdrive Recovery and Comparison
EOH in a small fraction of ␶o and, hence, Eq. (6) can be series- Time in One-Step Comparators
expanded and approximated to obtain the following expres-
sions for the output waveform and the amplification time: In CT applications, where comparators are not reset prior to
applying the input, characterization of the comparator tran-
 
gm t  t  sient requires calculating the delay and comparison times.
y(t)  D ≡  (7)
go τo t≤T D
τu t≤T For the purpose consider that the output is saturated because
A A
of an overdrive and that an opposite overdrive of amplitude
⌬D is applied at t ⫽ 0. Let us assume that y(0) ⫽ ⫺ESL. The
where ␶u ⬅ Co /gm is the unitary time constant of the amplifier.
model of Fig. 3(b) gives zero delay time TD and the following
From here and Eq. (3), the amplification time and dynamic
comparison time:
resolution, respectively, are given by


1 ESL

EOH 1+
TA = τu TC k S D
D = kS ln (12)
τu 1 EOH
1−
and k S D

EOH τu
ξD = |EOS | + ≈ |EOS | + EOH (8) For kS⌬D Ⰷ EOH and ESL and assuming EOH 앒 ESL, this equation
kD TA implies a resolution for speed tradeoff similar to that in Eq.
(9): ⌬D ⫻ (TC / ␶u) 앒 2EOH. On the other hand, in the worst case
which highlights a tradeoff between resolution and speed: when the comparator is used close to the static resolution

T  limit so that ⌬D 앒 ⌬S(1 ⫹ ⑀) with ⑀ Ⰶ 1, Eq. (12) can be simpli-
D A
≈ EOH (9) fied to give the following fundamental relationship between
τu static gain A0 and the comparison time required to attain such
limiting sensitivity:
The curve labeled N ⫽ 1 in Fig. 6(a) illustrates this tradeoff
for a typical EOH ⫽ 1 V. Because practical applications re-
T 
2
quire ⌬D Ⰶ EOH, this curve and Eq. (8) show that TA Ⰷ ␶u, C
= A0 ln (13)
meaning that the comparator is much slower than the under- τu 
lying voltage amplifier.
As ⌬D decreases, Eq. (9) shows that TA increases at the Assuming that A0 ⫽ 2 ⫻ 103 and ␶u ⫽ 10 ns, TC 앒 106 애s is
same rate. On the other hand, the comparator becomes in- needed to approach the resolution limit within 1%, slightly
creasingly slower as the input approaches the static resolu- larger than TA 앒 92 애s obtained from Eq. (11).
584 COMPARATOR CIRCUITS
OFFSET CANCELLATION IN ONE-STEP COMPARATORS
The Offset Problem
As already mentioned, the input offset voltage EOS poses an
important constraint on one-step comparator performance.
This nonideal feature reflects a lack of symmetry and has two
different components. Deterministic offset is caused by asym-
metries of the comparator circuit structure itself. For in-
stance, the FDPC structure of Fig. 3(h) is symmetrical,
whereas the AOTAC structure formed by connecting the MOS
differential pair of Fig. 3(d) and the active load of Fig. 3(e) is
asymmetric. Consequently, the output voltage at the quies-
cent point YQ is typically nonnull, thus making EOS ⫽ YQ /kS.
However, because YQ, in the worst case, is of the same order
of magnitude as EOH, the deterministic offset component
places a similar constraint on comparator resolution as on the
static gain, not significant enough to justify further consider-
ation. On the other hand, random offset contemplates asym-
metries caused by random fluctuations of the transistor tech-
nological parameters and is observed in asymmetrical and in
symmetrical structures. These fluctuations mismatch nomi-
nally identical transistors. The amount of mismatch is in-
versely proportional to the device area and distance between
them. Particularly, it has been observed that the threshold
voltage and the large-signal transconductance density of
MOSTs fluctuate with standard deviations given by (10),
αV2
σ 2 (VT0 ) ≈ T0
WL
and

β  αβ2
σ2 0
≈ 0
β0 WL
where W and L are the channel width and length, respec-
tively, 움V2 T0 and 움웁20 are technological constants, and ⌬웁0 /웁0 de-
notes percentage variations. There is at least one additional
term due to the separation between transistors, but this can
be attenuated through proper layout. On the other hand, typi-
cal characterization values for the parameters of Eq. (4) in a
0.5 애m technology are 움V2 T0 앒 10⫺5 V2애m2 and 움웁20 앒 10⫺4 애m2.
In the case of the MOST differential pair of Fig. 3(d), random
mismatches between the two transistors labelled MN1 render
their currents different for x⫹ ⫽ x⫺, and a voltage difference
given by


IB

β 
EOS |DP ≈ VT0Nd + 0 literature use either fully analog control loops or mixed
8βNd β0

β 
I 1 0 tween 40 애V and 120 애V over a 120⬚C temperature range
= VT0Nd + B
2 gm β0
has to be applied to equalize these currents. Another voltage
difference EOS兩AL has to be added to this to compensate for the
asymmetries in the active-load circuitry. In the case of the
AOTAC and the FDPC structures, this latter input offset
component is calculated as

β
IB

β 
EOS |AL ≈ VT0Pl Pl
+ 0
βNd 8βNd β0

β  Pl
(16)
βPl I 1
= VT0Pl + B 0
βNd 2 gm β0 Pl
to obtain 兩EOS兩 ⫽ 兩EOS兩DP ⫹ 兩EOS兩AL.
Equations (14), (15), and (16) suggest that EOS can be re-
duced through proper transistor sizing. However, these tech-
niques hardly obtain offsets less than a few millivolts, not
low enough for many practical applications. This drawback
is overcome by adding offset-cancellation circuitry, by which
residual offset values as small as 0.1 mV are obtained (11).
There are three basic approaches for offset cancellation; com-
ponent trimming; control through an auxiliary nulling port;
and dynamic correction.
Component trimming commonly refers to modifications of
some critical component geometries, for instance, through la-
ser or electron beam cutting, to compensate for the asymmet-
ries and thus minimize offset. Because such trimming is ap-
plied only once during the circuit life right after circuit
production, the adjustment must be stable to temperature
and circuit aging. Recently, techniques for nondestructive
trimming have been proposed that exploit the long-term ana-
log storage capabilities of floating-gate MOSTs (12,13).
Another common offset cancellation technique uses addi-
tional components controlled through a nulling port. Figure
4(a) illustrates this technique for the SOTAC comparator.
Note that a differential pair controlled by the voltages zos⫹
and zos⫺ has been added to the uncompensated structure
(drawn with solid black lines). Mismatch-induced current un-
balances are compensated for by setting these control voltages
and the transconductance of the additional differential pair
(14) such that
gmos (zos+ − zos− − EOS
os
) = EOS gm (17)
where Eos OS is the offset voltage of the offset-nulling differential
pair. For increased robustness under environmental changes,
the control voltages are generated through a control feedback
loop that monitors EOS and updates the control voltages until
this error is annulled. Figure 4(b) shows a conceptual block
diagram for this technique which implies two different op-
erating modes. During the calibration mode, switches labeled
Scal are ON and those labeled Scom are OFF. Thus the nulling
control voltage is generated by the control loop and stored in
memory. Then, during the comparison mode the circuit fea-
tures the comparator operation with reduced offset. Alterna-
tive implementations of the control loop reported in technical
Nd
(15) analog/digital control loops and feature offset voltages be-
Nd
(11,14,15). Although this offset cancellation technique in-
volves synchronization, careful design may enlarge the time
interval between calibration events to enable quasi-continu-
ous-time operation.
Self-adjusting comparators are not easy to design and are
area-intensive. Thus they are especially suitable for large cir-
 COMPARATOR CIRCUITS 585

Scom
+ +
y
Scal
x
MNOS
– –
zos– zos+
Scom
y Scal

x– MNd MNd x+
Memory Control

IBos IB

Timing
IBR

(a) (b)

y
x+ C ϕr
ϕr
xa– – MP
x–
y Eos x+ C ϕr
(0,0) ϕr
I+ + y
xa–
x– ϕa xa–
EOS
Eos ks MN
ϕa
Tca 1 + ks
ϕr x+
Tcr

(c) (d) (e)

VCH

C0V y
–VCL
x+
C xa– δm
x–
–
Ca– ∆ xa–
y t
I+
Eos
+
(
0,
Eosks
1 + ks ) TR

(f) (g)

x– –
ϕa x– –
ϕa
ϕr ϕr
x+ I+ + ϕ y
ϕa y x+ I+ + ϕr
Eos ϕa
Eos

(h) (i)

Figure 4. Offset cancellation in one-step voltage comparators.

586 COMPARATOR CIRCUITS
cuits where the correction circuitry is shared by many com-
parators.
Offset Compensation Using Dynamic Techniques
The Self-Biased Comparator Circuit. A simple, yet efficient
correction technique uses dynamic self-biasing to extract the
offset and offset storage to annul their influence (16,17). Fig-
ure 4(c) shows the corresponding circuit, consisting of an un-
compensated comparator (its offset has been represented
through a separate voltage source for enhanced clarity) plus
three clocked analog switches and a capacitor. The circuit re-
quires two nonoverlapping clocks, as indicated in the figure.
While ␸r is at the high-state and correspondingly ␸a is at
the low-state, switches controlled by the latter clock are ON,
and the others are OFF. Thus, the amplifier is shorted, and
hence its output voltage evolves toward a steady state xa⫺兩r ⫽
EOS(1 ⫹ k⫺1S )
⫺1
defined by the intersection of the amplifier
transfer characteristics and the bisecting line, as represented
in Fig. 4(d). Providing that the reset interval is long enough
for the transient to vanish, capacitor C is charged at a volt-
age vCr ⫽ x⫹ ⫺ xa⫺兩r. Note that for kS Ⰷ 1, xa⫺兩r 앒 EOS. Hence,
during the reset phase the negative plate of the capacitor
samples a voltage very close to the offset.
During the subsequent active time interval, ␸r goes low,
␸a goes high, and C keeps its charge because the current flow
is blocked. Thus, the comparator input xa ⬅ xa⫹ ⫺ xa⫺ evolves
to a steady state xa ⫽ EOS ⫺ (x⫺ ⫺ vCr) ⫽ EOS ⫺ xa⫺兩r ⫹ (x⫹ ⫺
x⫺) where the offset is substracted from its previous sample.
The following static resolution expression results:
|EOS | E |EOS | go
ξS ≈ + OH = + EOH (18)
1 + kS kS 1 + gm /go gm
which shows that the offset error is smaller by a factor 1 ⫹
kS than for uncompensated comparators, see Eq. (5).
This procedure of dynamically sampling the ‘‘central’’ point
of an inverting transfer characteristic during reset intervals
and substracting it from the input during active intervals can
also be applied to single-ended amplifiers. Figure 4(e) shows
the CInvC circuit which yields

E
 transient. It consists of a nonlinear part, where the transcon-
y ≈ k S x+ − x− + (19)
1 + kS
where E is the intrinsic reference voltage of the single-ended
amplifier, given by Eq. (4). Although the underlying amplifier
is single-ended, dynamic biasing renders it capable of hand-
ing a differential input which may be of interest for practical
applications.
Residual Offset and Gain Degradation in Self-Biased Compara-
tors. There are several second-order phenomena that modify
the voltage stored at node xa⫺ and consequently degrade the
static resolution of self-biased comparators. The most impor-
tant among them take place during the ON 씮 OFF transition
of the reset feedback switch, namely feedthrough of the clock
signal that controls this switch and injection of its channel
charge. They make the voltage stored at note xa⫺ exhibit a
step during this transition so that its value in the active
phase differs from that stored during the reset phase, that is,
xa⫺兩a 앒 xa⫺兩r ⫺ ⌬xa⫺. During the active phase this value also
continues degrading due to leakage current. Figure 4(f) is a
simplified model for evaluating all of these degradations. In
addition to the nominal capacitor C this model includes a par-
asitic capacitor between node xa⫺ and ground and another
parasitic capacitor between node xa⫺ and the feedback switch
control. Analysis using this model provides the following ex-
pression for static resolution:
Cov |q | |I | |EOS | E
ξS ≈ |VCH + VCL| + ch + leak t + + OH
C C C 1 + kS αC kS
(20)
|EOS | E
≡ |EOSd | + + OH
1 + kS αC kS
where 움C ⫽ C/(C ⫹ Cov ⫹ Ca⫺), qch is the charge built in the
switch channel while it is ON during the reset phase, and t is
measured from the instant when the ON 씮 OFF transition
happens. This expression shows the residual offset 兩EOSd兩 that
is not attenuated by comparator gain. If capacitance C is cho-
sen very small, this offset may become larger than the origi-
nal offset. Small values of this capacitance also may result in
small values of 움C, thus increasing the incremental sensitivity
[last term in Eq. (20)], and hence producing additional resolu-
tion degradation.
Transient Behavior and Dynamic Resolution in Self-Biased Com-
parators. The calculations for amplification time apply to the
active phase of self-biased comparators and show the resolu-
tion for speed tradeoff in Eq. (10) already discussed. On the
other hand, the transients during the reset phase arise from
another tradeoff related to the onset of an additional residual
offset component. The dynamic behavior within the reset
phase can be calculated using the model of Fig. 3(b). Two dif-
ferent transients are observed. First of all there is a very fast
charge redistribution transient, dominated by the ON resis-
tances of the switches. The output value y(0) at the end of
this transient, in the worst case, is equal to one of the satura-
tion levels. Let us assume that y(0) ⫽ EOH. From this value,
the output evolves toward the steady state at EOS(1 ⫹ k⫺1 S )
⫺1
through a second transient which is dominated by comparator
dynamics. Figure 4(g) provides a global view of this second
ductor is in the saturation region and y evolves from y(0) to
웃m with a fixed slew-rate 웃m / ␶u, followed by a linear segment
where the evolution is realized with time constant ␶ur ⫽ (C ⫹
Ca⫺ ⫹ Co)/(gm ⫹ go) 앒 C/gm ⬅ ␶u. Thus, the reset time needed
to reach a final value larger than the steady state by ⌬xa⫺ is
given by
EOH − δm

δm

TR ≈ τu + τu ln (21)
δm xa−
⌬xa⫺ remains as a residual offset after cancellation. For the
typical values of kS ⫽ 2 ⫻ 103, ␶u ⫽ 10 ns, EOH ⫽ 1 V and
웃m ⫽ 250 mV, Eq. (21) yields TR 앒 8.5 애s for a 1 mV residual
offset. This time is smaller than the amplification time (TA 앒
14 애s) required to obtain ⌬D ⫽ 1 mV from Eq. (10).
Offset Cancellation Through Storage at the Output Node.
Figure 4(c) employs offset storage at the comparator input
node. Alternatively, offset can be compensated for by storing
it at the output node. Such storage can be realized in either
 COMPARATOR CIRCUITS 587

the voltage or the current domain. Figures 4(h) and (i) show
the corresponding circuits.
MULTISTEP VOLTAGE COMPARATORS
Static and Dynamic Gain
The resolution for speed tradeoff of one-step voltage compara-
tors is improved by using a multistep architecture (18,19)
similar to the strategy used to enhance the voltage gain of
operational voltage amplifiers (20). Such a multistep architec-
ture consists of the cascade connection of several one-step
stages. These stages are different in the more general case. A
structure typically found in practice is a differential one-step
comparator at the front-end and single-ended inverters in the
rest of the chain, as shown in Fig. 5(b) (21). However, for im-
proved clarity in presenting the architectural principles, it
will be assumed that the cascade is formed of N identical
stages [see Fig. 5(a)], each having gain kS ⫽ gm /go and time
constant ␶o ⫽ Co /go. Hence the static resolution is given by

g N
o Offset Cancellation in Multistep Comparators
ξS ≈ |EOS | + EOH (22)
gm
where 兩EOS兩 is the offset of the front-end stage at the cascade.
Equation (22) shows that for a large enough value of N, the
static resolution becomes basically constrained by offset volt-
age, that is, the constraint due to static gain becomes negligi-
ble. Such a feature is specially important when the amplifiers
are realized through inverters, such as InvC and CInvC,
which have inherently low dc gain.
For the dynamic resolution, assume as for the one-step
case that offsets are null, that all capacitors are discharged
at t ⫽ 0, and that an input step of amplitude ⌬D is applied at
this instant. The output voltage Laplace transform is given
by

kS
N D
Y (s) = (23)
1 + sτo s
Assuming that ⌬D(gm /go)N Ⰷ EOH, TA Ⰶ ␶o, and hence Eq. (23)
simplifies Y(s) 앓 ⌬D /(sN⫹1␶uN). From here the output waveform
and TA, respectively, are given by
As for the one-step comparator [see Eq. (9)], Eq. (25) yields
TA ⬎ ␶u for the practical case where ⌬D ⬍ EOH. However, be-
cause of the potential dependence on N, the multistep archi-
tecture yields smaller values of TA for any ⌬D such that ⌬D ⬍
(EOH /2). For instance, for ␶u ⫽ 10 ns, EOH ⫽ 1 V and ⌬D ⫽ 10
mV, Eq. (24) yields TA 앒 141 ns for N ⫽ 2, TA 앒 65 ns for
N ⫽ 5, and TA 앒 67 ns for N ⫽ 8, smaller in all cases than
for the one-step.
Figure 6(a) depicts TA / ␶u as a function of ⌬D for different
values of N and EOH ⫽ 1 V. Figure 6(b) is an enlargement of
the previous diagram. It shows that for each ⌬D there is an
optimum value of N that minimizes TA. For ⌬D ⬎ (10⫺3 EOH)
this optimum number is given by (19),

E 
Nopt ≈ 1.1 ln OH
+ 0.79 (26)
D
For instance, for ⌬D 앒 (10⫺2 EOH), maximum speed is achieved
by using N ⫽ 6. Using either less or more stages in the cas-
cade yields slower operation.
Dynamic self-biasing can also be applied to cancel the offset
of multistage comparators. However, the high-order dynamics
preclude direct feedback connection of the overall output node
and the negative input. Unless compensation circuitry is
used, such direct feedback connection leads to instabilities,
similar to the problem found in two-stage op amps (7,20). In-
stabilities are avoided by making each stage store its own off-
set, as shown in Fig. 5(c). Thus, only residual offsets—see Eq.
(20)—generated at the different stages remain. However,
they are also attenuated through proper timing of the
switches used for self-biasing. The inset of Fig. 5(c) shows this
timing. Note that the stages are switched ON at different in-
stants, each one after the previous. Consequently, the resid-
ual offset of each stage is stored at the input capacitor of the
next stage while the latter remains grounded, and hence the
output remains unaltered. In this way only the residual offset
of the last stage 兩EOSdN兩 contributes to the output. Because this
offset is amplified only by the last stage itself, whereas the
signal is amplified by all of the stages, the following expres-
sion results for static resolution:

D 1 N |EOSdN | EOH
y(t) ≈ t ξS ≈ + (27)
τuN N! (αC kS ) N−1 (αC kS )N

and Overdrive Recovery and Delay Time

E 1/N in Multistep Voltage Comparators
TA ≈ τu OH
N! (24) Transient characterization of multistep comparators for CT
D applications requires calculating delay and comparison times.
The worst case happens when the initial condition is such
and the expressions for the dynamic resolution and the reso- that all stages are saturated due to an input overdrive ap-
lution for speed trade-off are plied and held for some instant t ⬍ 0 and then an opposite

τ N overdrive of amplitude ⌬D very close to the static resolution
ξD ≈ |EOS | + EOH N!
u
limit is applied at t ⫽ 0. Assume, as for the calculation of
TA comparison time in the one-step comparator, that y(0) ⫽ ⫺
ESL. During the transient evolution toward the steady-state,
and y(앝) ⫽ kSN⌬D, each stage remains saturated and hence latent,

T N while its input is smaller than ⫺ESL /kS. Figures 5(d) and 5(e)
D A
≈ N!EOH (25) show the transient waveforms for comparators with two and
τu three stages, respectively.
588 COMPARATOR CIRCUITS

+ k s, τu
+
x k s, τu
+
y1 k s, τu
– – +
1st y2
– k s, τu
+
2nd – +
3rd
– y
Nth –

(a)

MP MP
VBP
MP1 MP1

MCP MCP
VCP
∆i+ ∆i–
x+ x– y
MNd MNd
MCN MCN

VCN
MN1 MN1
IB
MNB MNB MN MN

x+ C ϕ r1
ϕ r0
– C ϕ r2
xa–
x– ϕrN
ϕa – C
y1 –
I+ + y2 xa–
y
EOS I+ +
EOS I+ +
EOS
(b)

ϕ r1
ϕa
Tca
ϕ r2 ϕ r0
Tcr

ϕrN

(c)

ESH
V02

EOH
V01
ESL/kS
t t
—ESL/kS

V01 V02 V03

—ESL
T1 T2 T1 T2 T3

(d) (e)

Figure 5. Multistep voltage comparators.

 COMPARATOR CIRCUITS 589

Comparative performance of the 10

Normalized amplification time Ta /τ u

comparator architectures N=2
103 9
Normalized amplification

8
2 N=3
10
N=1 R = 1.0 7
time Ta /τ u

N=2
101 6
N=5
5
N=5 R = 0.4 N=6
100 R = 0.2
4 N=4

10–1 3
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
Incremental dynamic sensitivity, V Incremental dynamic sensitivity, V
(a) (b)

xCM = – 0.5 xCM = – 0.0 xCM = – 0.5

20 30 20
18 25 18
Wrong output 16 Wrong output
16
20
14 14
15 12
12
10 10
10
8 5 8
6 0 6
–0.08 –0.04 0 0.04 0.08 –0.08 –0.04 0 0.04 0.08 –0.08 –0.04 0 0.04 0.08
(c)

Figure 6. Illustrating the resolution-speed tradeoff for different voltage comparators.

Two-Stage Comparator. First consider the two-stage compa- The comparison time is the instant at which y(t) ⫽ EOH:
rator whose waveforms are depicted in Fig. 5(d). The delay

time is that invested by the first stage in delivering the volt- ESL + EOH
age ⫺ESL /kS. Because the transient at node y1 is the first-order TC T k2S D
type, TD is mathematically expressed similarly to Eq. (12): ≈ D + kS 2 (31)
τu τu E
1 + 2 SL
k S D
ESL
1+
TD k S D Because ⌬D 앒 ⌬S and taking into account Eqs. (2) and (22),
= kS ln (28)
τu E kS2 ⌬D 앒 EOH. Thus, by assuming that EOH 앒 ESL,
1 + 2 SL
k S D
TD k
≈ kS ln S
τu 2
From t ⫽ TD, the second stage starts contributing to the volt-
age gain thus giving and

 TC T √ k √

1 ζ
1 ζ −
kS τu ≈ D + kS 2 ≈ kS ln S + 2 (32)
y(t) = k2S D − (ESL + k2S D ) 1 + e (29) τu τu 2
k S τu
By comparing this TC with an optimistic estimation of the cor-
where ␨ ⫽ t ⫺ TD. This equation is difficult to solve exactly. responding value for one-step architecture and assuming the
However, for our purposes it can be approximated by the first same overall static gain (A0 ⫽ kS for one-step; A0 ⫽ kS2 for two-
two terms of its power expansion: step),
  


1 2
y(t) ≈ −ESL +
(ESL + k2S D ) ζ
(30)
TC |two−step
TC |one−step
=
1 √
 2 + ln
A0
2
<1

(33)
2 k S τu 2 A 0
590 COMPARATOR CIRCUITS

It shows that the possibility of distributing the gain between This is confirmed through analysis of Fig. 7(a). Assuming
the two stages also gives faster operation in overdrive re- that both transconductors and the resistor Go(y) operate in-
covery. side their linear regions [see Fig. 3(b)] and defining 움F ⬅ 1 ⫺
(gmo /go),
Three-Stage Comparator. Now consider Fig. 5(e), corre-
gm gm −1
sponding to the three-stage comparator. The delay time now kS = = α (38)
has two components. The first TD1 is given by Eq. (28). The go − gmo go F
second is the time needed for the second-stage output to
reach ⫺ESL /kS and is calculated by using Eqs. (29) and (30): Let us consider that go ⬎ gmo, and hence 움F ⬎ 0. Equation (38)





shows that as gmo increases by approaching the go value, the
voltage gain also increases, thereby confirming the action of

 ESL ESL E 


 1+ k  − 3 SL 
 positive feedback. Because the incremental static sensitivity
TD T T k D
2 k S D
= D1 + D2 ≈ kS ln S D
+ 2 S ⌬S is inversely proportional to the static gain, such an effect
τu τu τu 
 ESL ESL 
 could be exploited to improve the resolution of one-step com-

 1+ 2 1+ 2 

 k S D k S D  parators, with no additional stages needed. In the limit for
(34) gmo 씮 go, kS 씮 앝, and hence ⌬S 씮 0. On the other hand, Eq.
(10) shows that for ␶u and ⌬D fixed, the speed of a one-step
From t ⫽ TD the third stage starts working so that after a comparator also increases with increasing kS. For instance,
power-series expansion, with ␶u ⫽ 10 ns, EOH ⫽ 1 V and ⌬D ⫽ 1 mV, Eq. (10) yields
TA 앒 47 애s for kS ⫽ 1010 and TA 앒 10 애s for kS ⫽ 11000.
(ESL + k3S D )

ζ
3 TC Figure 7(b) shows a circuit implementation of positive
y(t) ≈ −ESL + ⇒ feedback in one-step comparators. Figure 7(f) shows a CMOS
3! k S τu τu
 schematic for this implementation where
 E +E

TD



SL
k3S D
OH (35)
β0No

W 
≈ + kS 
3! gmo = 2 IBo
τu  E nNo L No
3 1 + 3 SL
k S D
and
Under assumptions similar to those for two-stages, namely,
I + IBo

1 1

kS3 ⌬D 앒 EOH and EOH 앒 ESL, the following expression is ob- go = B + (39)
tained for the comparison time as a function of the overall 2 VANl VAPl
gain A0 ⫽ kS3 :
Because of the positive feedback action, this circuit, as any
 
TC √ √
3
 ln(A0 ) √ √
3 other including positive feedback, for instance, Fig. 7(g), is
≈ kS [ln(kS ) + 2 + 3!] = 3 A0 + 2 + 3!
τu 3 very sensitive to random fluctuations of technological parame-
(36) ters, such as 웁0 in Eq. 39. Consequently, very small nominal
values of 움F should be avoided if this parameter must be kept
This can be easily generalized to N stages: positive in the presence of such fluctuations. In practice it is
  hard to guarantee robust operation with 움F 앒 0.01. A robust
TC  ln(A0 )  N √
m conservative value might be 움F 앒 0.1, which reduces ⌬S by a
≈ N A0 + m! (37) factor of 10 and improves the nominal speed by a factor
τu N m=2
around 4.7—not too much improvement. Actually, analysis of
Eq. (10) taking into account Eq. (38) shows that speed cannot
It shows that for the same static gain, equivalently, the same
be improved any further despite the value of 움F. The following
static incremental sensitivity ⌬S ⫽ EOH /A0, the comparison
section shows that much larger speed improvement is
time decreases with the number of stages, even in overdrive
achieved by allowing 움F to be negative, the counterpart being
recovery.
degradation of resolution.

VOLTAGE COMPARATORS WITH POSITIVE FEEDBACK
Using Partial Positive Feedback to Enhance the Voltage Gain
Consider the conceptual circuit of Fig. 7(a). In addition to the
conventional transconductor Gm(x) controlled by input volt-
age, this circuit contains another Gmo(y) controlled by output
voltage. The former injects a current proportional to x into
the output node, whereas the current injected by the latter is
a function of the output node voltage. Hence this new trans-
conductor is acting as a resistor. Its current enters the node
for positive values of y which means that its incremental re-
sistance is negative and, consequently, induces a positive
feedback action on the overall comparator operation.
One-Step Comparators with Global Positive
Feedback: The Onset of Hysteresis
Let us focus again on Fig. 7(a) and define 웁F ⫽ ⫺움F ⫽
(gmo /go) ⫺ 1. Consider 웁F ⬎ 0. This implies that gmo ⬎ go and
hence that the amount of negative feedback exercised by go is
smaller than the positive feedback due to gmo. The global feed-
back is hence positive. This has two major consequences on
comparator behavior:
• The time constant for small-signal variations around y ⫽
0 is negative. Consequently, the transient evolution from
this point follows an exponentially increasing law. In
particular, assuming that y(0) ⫽ 0 and that an input step
 COMPARATOR CIRCUITS 591

ic
y

Ca + + +
x
Gm(x) Gmo( y) Go( y) y
– – –
gm gmo

iC
(a) (b)

–3
–2
iC – gmx
–1 0 1 2 3
Gmo(x) –1 g
–ESL y Slope – gm ESH
Slope go IBo 0 o
ESH
– δ mo 1
–ESL y –ΓH ΓH
δ mo x
2
ESH
3
–ESL
Go(y)
Slope – (gmo – go) –3 –2 –1 0 1
Slope –
( ( gm –1
go β F

(d) (e)
(c)

MPI MPI
MPI MPI MPo
MNo MNo
y
y
MNd MNd MNd MNd x+
x– x+ x–

MNI
IBo IB
MNI
IBR
IBR

(f) (g)

x –
y
+

γ –1

y(t)
y
1 ΓH
EOH γ t
1 – γ /ks –ΓH

x x(t)

(i)
–EOL

(h)

Figure 7. Using positive feedback in one-step comparators.

592 COMPARATOR CIRCUITS
of amplitude ⌬D is applied at t ⫽ 0, the output waveform
is given by
gm −1

g
 edge x ⫽ ⌫H is not surpassed.
tβ F Co
y(t) = D β e o −1 (40)
go F
This exponentially increasing law enables much faster
operation than for conventional one-step and multistep
comparators.
• The large-signal comparator transfer characteristics are
multivalued. Hence, the comparator exhibits hysteresis
when operating in the CT mode with large-signal excita-
tions.
Let us focus on the second feature. Graphical analysis of Fig.
7(a) using the models of Fig. 3(b) yields the characteristics
drawn in solid black in Fig. 7(c). It displays iC ⫹ gmx as a
function of y, where iC is the current leaving the capacitor.
This figure shows that the capacitor sees a negative resis-
tance around y ⫽ 0—the reason why the time constant
around this point is negative. The figure also shows that the
global characteristic seen by the capacitor is multivalued. To
better understand why this latter feature leads to hysteresis,
let us consider x changing, and draw a family of iC versus y
curves with x as parameter. Figure 7(d) shows such a family
and Fig. 7(e) shows the corresponding y versus x comparator
transfer characteristic. Assume that x is such that the capaci-
tor sees the curve labeled 3 in Fig. 7(d). This curve intersects
the y axis only at y ⫽ ESH. Hence this is the steady-state out-
put as Fig. 7(e) shows. At the intersection points the current
through the capacitor is null and hence dy/dt ⫽ 0. These
points are equilibrium states where y(t) ⫽ cte and the circuit
may remain static (22). In practice the circuit actually re-
mains static provided that the slope of the io versus y curve is
positive around the point (stable equilibrium) and is not oth-
erwise (unstable equilibrium). Starting from any arbitrary
initial value of y, the circuit trajectory toward steady-state is
determined by the attraction exercised by stable equilibrium
points and the repulsion exercised by unstable equilibrium
points.
Now consider that x decreases such that the curve seen by
the capacitor changes sequentially from that labeled 2 to that
labeled ⴚ3. For x corresponding to curve 2, the circuit oper-
ates at the rightmost edge of the multivalued region:
go
H = δmo β (41)
gm F
and yields y 앒 ESH. For smaller x and until the other edge is
reached, the circuit operates inside the multivalued region
where there are two valid solutions. However, the output volt-
age remains positive. The reason is that this voltage is stored
in the capacitor and the capacitor charge remains unchanged
because at steady-state iC ⫽ 0. When x reaches the leftmost
edge of the hysteresis region, for x ⫽ ⫺⌫H, the capacitor sees
the curve ⴚ2, whose only valid solution is y ⫽ ⫺ESL. Conse-
quently, around this x value the output must jump from y ⫽
웃mo to y ⫽ ⫺ESL. The dynamics of such a jump are dictated by
the slopes of the different segments of the characteristic seen
by the capacitor. First, the output evolves from y ⫽ 웃mo to y
⫽ ⫺웃mo with negative time constant ␶ ⫽ ⫺(웁⫺1 F Co)/go. Then,
from y ⫽ ⫺웃mo to y ⫽ ⫺ESL the evolution is with positive time
constant ␶ ⫽ Co /go. Once on the bottom segment of the trans-
fer characteristics, the output remains negative while the
Obviously, the incremental static sensitivity of hysteretic
comparators is inherently smaller than ⌫H. Hence the onset
of hysteresis implies degradation of resolution. However,
small hysteresis is useful to avoid glitches in those applica-
tions where signals are embedded in a noisy environment.
This is illustrated in Fig. 7(i), which shows that by defining
the edges of the hysteretic characteristic equal or slightly
greater than the amount of the largest expected noise ampli-
tude, spurious glitches are avoided.
The circuits of Figs. 7(f) and 7(g) can be designed to have
hysteresis. Figure 7(h), where we assume 0 ⬍ 웂 ⬍ 1, shows
another hysteretic circuit that uses a single one-step compa-
rator and exploits the positive input terminal for positive
feedback. The figure also shows the cycle featured by the cir-
cuit, where the hysteresis region edges are set through proper
gain setting of the scaling block in the feedback path.
Discrete-Time Regenerative Comparators
The onset of hysteresis in positive-feedback comparators is a
consequence of capacitor memory. If comparators are made to
operate in discrete time and the memory is periodically elimi-
nated through resetting, hysteresis disappears (in practice
some hysteresis remains because of second-order phenom-
ena). As in any discrete-time (DT) comparator, a clock must
be used to control operation. In the clock-reset phase the com-
parator is disconnected from the inputs and driven to a cen-
tral point. Then, in the comparison phase, the input is applied
and a transient evolution happens toward one of the satu-
rated states. The qualitative issues for this behavior are illus-
trated in Fig. 8(a) for the circuit of Fig. 7(b). During the reset
phase the output is driven to the central point of Fig. 8(a),
P0, where y ⫽ 0. During the comparison phase, for x ⬎ 0, the
capacitor sees the bottom characteristics of Fig. 8(a) which
include three equilibrium points (see previous discussion of
intersection points): two stable, QL and QH, and the other un-
stable, Q0 (refer again to the previous discussion). Because
the capacitor charge cannot change instantaneously, the ini-
tial state is y ⫽ 0 corresponding to P⫹ on the characteristic,
which is located on the right-hand side of Q0. From P⫹ the
repulsion action exercised by Q0, precludes reaching the left-
hand stable equilibrium at QL, and the trajectory is attracted
toward the right-hand stable equilibrium at QH, where y ⫽
ESH. On the other hand, for x ⬍ 0, the central point pushes
the trajectory toward the equilibrium at QL, where y ⫽ ⫺ESL.
In both cases, dynamic evolution is realized with negative
time constants and hence at very high speed.
Except for the influence of second-order effects, the opera-
tion described is valid no matter how small the input signal
magnitude may be. Only the input sign is significant. It
means that DT positive feedback comparators can build infi-
nitely large dynamic gain—a feature not shared by one-step
or by multistep comparators whose maximum dynamic gain
is smaller than the static gain. This is confirmed by Eq. (40),
which shows that the output waveform is not bounded no
matter how small ⌬D may be.
DT positive-feedback comparators, usually called regenera-
tive comparators, are commonly built by cross-coupling a pair
of inverters to form a latch—a circuit structure often used as
 COMPARATOR CIRCUITS 593

C y+ – y–
x<0 xa–
x– y+ QH
P– ϕr ϕa
τ
ESH
QL Q0 Q0 QH x<0 x>0
y ϕr
–ESL P0 Q0 xa+ – xa–

P+ τ
ϕr ϕa y–
QL
x+
xa+
x>0
(a) (b) C (c)

MPB ϕa

ϕr ϕr ϕr
ϕa
MNS MNS MPB xa+ xa–
y+ y– y+ y–
y+ y–
x– xa– xa+ x+ ϕr

xa– xa+ xa+ xa–

y+
y– ϕa
MNB
MNB ϕa ϕa

(d) (e) (f) (g)

C
xa+ y+ y– xa–

gmin+ x+ g0+ Co+ (

gm+ y– –
EOS
2 ( (
gm– y+ +
EOS
2 ( Co– g0+ gmin– x–

(h)

ϕr
x– ϕ a1 xa– ∆i+ ∆i–
x+ y+ ϕr
ϕr C ϕ a2
MNd MNd x–
x+
y+ y–
ϕ a2
x+
ϕ a1 y–
ϕr
x– xa+
ϕr C ϕr

IB xa+ xa–
ϕr
ϕ a1 MNB MNB
ϕ a2
(j)
(i) ϕr
xa–
ϕa1 ϕ a2 y+
x+ C C
ϕr –
x– +
ϕa1
x– –
ϕr +
x+ C ϕ a2
y–
xa+
(k) C
ϕr

Figure 8. Regenerative comparators.

594 COMPARATOR CIRCUITS
a sense amplifier in dynamic RAMs (1). Figure 8(b) shows the
concept of a regenerative comparator based on a latch, where
the triangles in the feedback loop model delays in the trans-
mission of voltages around the loop. [This is a very crude
model. Correct modelling requires a nonlinear vectorial differ-
ential equation of at least second-order that takes into ac-
count impedances at the different nodes. Then the dynamic
has to be analyzed in the phase space (22).] The inverters
amplify the differential input xa⫹ ⫺ xa⫺ to obtain the saturated
differential output y⫹ ⫺ y⫺ according to the characteristics
drawn in solid black in Fig. 8(c). During the reset phase, the
circuit is driven to the central state Q0. During the active
phase, the differential input is applied, forcing an initial state
either at the right, x ⬎ 0, or at the left, x ⬍ 0, of Q0. From
this initial state, the action of positive feedback forces the out-
put to evolve either toward QH, for x ⬎ 0, or toward QL, for
x ⬍ 0, as illustrated by the gray line trajectories in Fig. 8(c).
Figures 8(d) to 8(g) show several CMOS latches reported
in the literature (23–27). For Figures 8(d) and 8(e) during the
reset phase, transistors MNB and MPB are OFF so that the
latch is disabled. Hence, nodes xa⫹ and xa⫺ are at a high-im-
pedance state and input voltages can be sampled at these
nodes. Transistors MNS in Fig. 8(d) are used for that purpose.
Then, the voltage difference is amplified when the latch be-
comes enabled during the active phase. Alternatively, the
nodes xa⫹ and xa⫺ are driven in the active phase with currents
obtained from the input voltages by transconductors, as illus-
trated in Fig. 8(k). This is the only excitation alternative for
Figs. 8(f) and 8(g).
The circuit of Fig. 8(h) is a small-signal, first-order model
of the latch behavior during the active phase. It corresponds
to the case where signals are applied through transconductors
and includes asymmetries between the two latch branches
and capacitive coupling between the two latch outputs. Such
coupling and asymmetries appear in practical circuits and are
responsible for significant errors observed in actual latch op-
eration (28). The circuit of Fig. 8(h) captures the latch dy-
namic in the following state equations:
dy+
(Co+ + Cc ) = − go+ y+ − gm+ y− + gm in+ x+
dt
E dy−
+ gm+ OS + Cc
2 dt
and
dy−
(Co− + Cc ) = − gm− y+ − go− y− + gm in− x−
dt (42)
E dy+
− gm− OS + Cc
2 dt
First assume full symmetry, equal positive and negative pa-
rameters, EOS ⫽ 0, and negligible capacitive coupling. Then,
the previous two equations can be substracted so that dynam-
ics are represented by a single differential equation:
d(y+ − y− )
Co = gm (y+ − y− ) − go (y+ − y− ) + gm in (x+ − x− )
dt
(43)
The first term on the right-hand side of this equation repre-
sents positive feedback, the second negative feedback, and the
last the input. Assume (gm /go) Ⰷ 1. Then, assuming that the
circuit is initialized at t ⫽ 0 such that y(0) ⫽ y⫹(0) ⫺ y⫺(0) and
that a differential input step of amplitude ⌬D ⬅ x⫹ ⫺ x⫺ is
applied at this instant, the differential output waveform can
be approximated as
gm in g
t Cm gm in t
y(t) ≡ y+ (t) − y− (t) ≈ D e o ≡ D e τu (44)
gm gm
A similar equation is found for those cases where the latch is
driven during the reset phase by establishing a voltage unbal-
ance y(0) ⫽ y⫹(0) ⫺ y⫺(0) ⬅ ⌬D. Then y(t) 앒 ⌬Det/ ␶u. From Eq.
(44) the following expression is found for the resolution for
speed tradeoff:

T     
D EOH gm
D A
 EOH ln (45)
τu EOH D gm in
Figure 6(a), where R ⬅ gm /gmin compares this tradeoff to that
given by Eq. (25) for multistep comparators. It shows that, as
already anticipated, regenerative comparators feature faster
operating speed despite the value of N.
Asymmetries in DT Regenerative Comparators:
Mixed Comparator Architectures
Spurious differential signals, coupling between the two latch
branches, and mismatches between their parameters pre-
clude correct amplification of small ⌬D values. Their influence
can be assessed by studying the equilibrium points of Eq.
(42), their eigenvalues, and their eigenvectors (22) which are
out of this article’s scope. On the other hand, the influence of
spurious random signals is a much harder problem.
Note from Eq. (42) that the influence of offset EOS between
two branches is similar to that observed in one-step and
multistep comparators, that is, ␰D 앜 兩EOS兩. It can be attenuated
through separate self-biasing of the two latch branches. The
circuit of Fig. 8(i) employs this strategy (29). Larger offset
attenuation is achieved by using capacitors, instead of just
wires, in the latch coupling branches of this circuit.
However, dissymmetries between transconductances gm⫹
and gm⫺ and between the capacitors Co⫹ and Co⫺ produce much
larger errors for regenerative comparators than for one-step
and multistep comparators. The amount of error depends on
the input signal common mode xCM, as Fig. 6(c) illustrates.
This figure shows the outcome of simulations realized using
Eq. (42) with realistic transconductance mismatches of 10%
and capacitive coupling of 30%. For zero common mode the
figure does not anticipate limitations on ⌬D. On the other
hand, as the common mode increases to half of the swing
range, 兩⌬D兩 has to be larger than 앒30 mV for correct codifica-
tion of the input signal polarity. This value increases up to
앒50 mV if 10% mismatches are considered for transconduc-
tances and capacitances. It imposes a strong constraint on
comparator resolution, not shared by either one-step or
multistep comparators.
This problem of regenerative comparators is overcome by
placing a preamplifier in front of the regenerative core. This
is actually the role played by transconductances gmin in Fig.
8(h), and resolution improvement is roughly proportional to
the ratio gmin /gm. Figure 8(j) shows an actual CMOS circuit
implementation of this concept (25). Alternatively, if the latch
is driven through voltages, a mixed comparator architecture
 COMPARATOR CIRCUITS 595

consisting of the cascade of a self-biased one-step comparator example of a practical current comparator belonging to the
and a self-biased latch can be used. Larger accuracy is former class (31), and Fig. 9(d) shows a corresponding exam-
achieved by making the latter a fully differential type, as ple for the latter (32). These two classes display quite differ-
shown in Fig. 8(k) (18,29). ent properties for dynamic resolution ␰D.

About the Resolution of Resistive-Input and

BASIC CURRENT COMPARATORS
Building Current Comparators from Voltage Comparators
As defined in the first Section, current comparators are used
to map the difference between two analog currents x⫹(t) and
x⫺(t) onto a digital voltage y, so that the state of the latter
codifies the sign of the former. The larger the transimpedance
gain kS, the smaller the incremental static sensitivity parame-
ter ⌬S, and the more sensitive the comparator under dc excita-
tion. Hence, the process of current comparator synthesis con-
sists essentially of finding circuit structures to obtain the
largest possible kS. One obvious architecture uses a large re-
sistor for current-to-voltage conversion and a buffer for output
voltage isolation [shown at the conceptual level in Fig. 9(a)].
Thus, the transimpedance gain is contributed only by the re-
sistor. For greater design flexibility, the buffer is replaced by
a voltage comparator that also contributes to kS. The front-
end current-sensing device can also be replaced by a more
general reactive impedance Za(s) (30), thus leading to the con-
ceptual architecture of Fig. 9(b).
For design purposes it is worth considering two extreme
cases for the architecture of Fig. 9(b), one where the sensing
device is dominated by the resistive component and one where
the capacitive component is dominant. Figure 9(c) shows an
Capacitive-Input Current Comparators
Obviously, the resolution of Fig. 9(b) depends on the sensing
device and on the voltage comparator structure. For compari-
son, consider the simplest case where the latter is realized
through a one-step architecture with dc gain gmRb and unitary
time constant ␶u ⫽ Cb /gm as shown at the conceptual level in
Fig. 9(e). Assume, as shown in Fig. 9(e), that an overdrive
current step of magnitude ⌬D is applied at t ⫽ 0 and that the
circuit is at its central point before applying the step. Routine
analysis obtains the following expression for the output volt-
age waveform:

δ0 δb

y(t) = gm Ra Rb D 1− e−t/δ a − e−t/δ b , t>0
δa − δb δb − δa
(46)
where ␶a ⫽ RaCa and ␶b ⫽ RbCb. From here the amplification
time TA and the incremental dynamic sensitivity ⌬D are calcu-
lated by using Eq. (3).
Consider the resistive-input case first. It yields Ra Ⰶ Rb
and Ca 앒 Cb. The resistance Ra and capacitance Ca in the in-
put stage of Fig. 9(e) model the parallel combination of the
nominal sensing elements and the parasitics from the driving
and amplifying stages. This means that in an optimum de-

Buffer
y
+ +
Za(s)
x+(t) x–(t) R = ks ya y
Ra Ca –
x+(t) x–(t)
–
(a)
(b)

x(t) y x(t) y

(d)
(c)

∆D y
+
Za(s)
0
t=0 ya Rb Cb
x+(t) x–(t) Ra Ca gm ya
–
Figure 9. Basic current comparator ar-
chitectures and exemplary CMOS imple-
(e) mentations.
596 COMPARATOR CIRCUITS

sign Ca is of the same order of magnitude as Cb and that the Hence, the static resolution parameter is given by
maximum attainable Ra value is limited by the device’s early
1

EOH + EOL

voltage, similar to what occurs for Rb. Therefore the time con- ζS ≡ |EOS | + S = |EOSa | + |EOSb| + (52)
stant of the input stage is much lower than that of the output Rc 2gm Rb
stage. Taking this into account and assuming t Ⰶ ␶b, Eq. (46)
is simplified to obtain where the larger Ra, the smaller ␰S. Actually, for ideal capaci-
tive input, where RaCI 씮 앝, Eq. (52) yields ␰S 씮 兩EOSa兩. Then,
1 Cb EOH τu EOH any input current x(t) such that 兩x(t)兩 ⬎ 兩EOSa兩, no matter how
D ≈ = (47) small 兩x(t)兩 ⫺ 兩EOSa兩 may be, is integrated by the input capaci-
RI TA gm Ra RI TA Ra RI
tor forcing the input of the voltage comparator to evolve so
that the sign of the input current is correctly coded.
which shows a direct dependence with the unitary time con- Now consider applications involving large currents. Analy-
stant of the voltage comparator and an inverse dependence sis of Eq. (47)–(49) shows that the resistive-input architecture
with TA, similar to that observed for one-step voltage compar- is faster whenever ⌬D ⬎ ⌬*D . Also, because the voltage varia-
ators. tions at the input node ya ⫽ x ⭈ Ra are smaller for resistive-
Now consider the capacitive-input case. The input node of input comparators, this structure can be expected to exhibit
this structure is the high-impedance type and hence, ␶a and smaller interstage loading errors and to perform better under
␶b are of the same order of magnitude. Taking this into ac- overdrive excitations.
count and assuming t Ⰶ ␶b, the dynamic resolution is calcu-
lated by making a Taylor expansion of Eq. (46) and keeping Multistep Current Comparators
the linear and the quadratic terms:
Multistep current comparators are implemented by cascading
τu τa CI EOH a current-sensing device to perform current-to-voltage conver-
∼ 1 C E
D = 2 2 b (Ca Ra CI ) OH ≈2 (48) sion, followed by a multistep voltage comparator. Analysis of
CI TA gm Ra CI TA2 Ra CI
such a structure yields the following expressions for amplifi-
cation time:
where ⌬DCI is directly proportional to the unitary time con-
!1/N
stants of the voltage comparator and the current sensing EOH
front-end and inversely proportional to the square of the am- TA  δu N! , for resistive input
D Ra RI
plification time. RI

Comparative analysis of Eqs. (47) and (48) shows a differ-

and
ent accuracy for speed tradeoff for each current comparator
architecture. The two architectures feature the same speed
!1/(N+1)
τa CI EOH (N + 1)!
(i.e., the same amplification time) for the following value of TA ≈ τu for capacitive input
the dynamic resolution parameter:  D τu Ra CI
CI
(53)
1 τu EOH Ra CI
∗D ≈ (49) Both architectures feature the same speed (i.e., the same am-
2 τa CI Ra RI Ra RI
plification time) for the following value of the dynamic resolu-
tion parameter:
Analysis of Eq. (49) using a feasible set of parameter values,
 
R N
namely ␶u ⫽ 10⫺8 s, ␶aCI ⫽ 10⫺7 s, EOH ⫽ 1 V, RaRI ⫽ 105 ⍀, and N! EOH a CI τu
RaCI ⫽ 106 ⍀, yields ⌬*D 앒 5 애A. For ⌬D ⬍ ⌬*D and because ⌬DCI ∗D ≈ (54)
(N + 1)N Ra RI Ra RI τa CI
앜 T⫺2A , capacitive-input architecture yields smaller TA than re-
sistive-input, where ⌬DRI 앜 T⫺1 A . This means that capacitive- Analysis of Eq. (54) using a feasible set of parameter values,
input architecture is faster for applications involving small namely, ␶u ⫽ 10⫺8 s, ␶aCI ⫽ 10⫺7 s, EOH ⫽ 1 V, RaRI ⫽ 105 ⍀,
input currents. RaCI ⫽ 106 ⍀, and N ⫽ 2 results in ⌬*D 앒 2.2 애A which is lower
The advantages of capacitive-input for small currents are than the dynamic resolution term obtained for the one-step
confirmed by calculating the static sensitivity ⌬S and the off- current comparator for the same parameters.
set 兩EOS兩. The former is inversely proportional to the dc trans-
impedance, given as the product of Ra and the dc voltage com-
parator gain. Thus, ADVANCED CURRENT COMPARATORS

The previous section shows that resistive-input and capaci-

1 EOH + EOL
S = (50) tive-input comparators are complementary architectures.
2 g m Ra Rb
This section presents improved architectures that combine
the advantages of these two basic schemes, namely, large sen-
On the other hand, the offset has two components: the input sitivity and reduced amplification time for low-current levels
current offset of the sensing device and the input offset of the and reduced input voltage excursion for large current levels.
voltage comparator attenuated by Ra. Thus,
Current Comparators with Nonlinear Current Sensing
|E |
|EOS | = |EOSa| + OSb (51) Figure 10(a) shows the conceptual block diagram of a current
Ra comparator where the linear resistor Ra of Fig. 9(b) is re-
 COMPARATOR CIRCUITS 597

Slope 1/Ra*
xR
a
+
xR +
a Slope 1/Ra
ya y –δ L
Ra ya
x+(t) x–(t) – (0,0) δ H
Ca
–

(a)
(b)

x(t) xR
a
P2
JH
t ya xN
x(t) –δ L
MP
A
xP MN
– JL P1 δH

(c)

xN (d)
MP MP
x(t) x(t)
A
B A B
xP
MN
MN

Figure 10. Current comparator with non-

(e) (f) linear current sensing.

placed by a nonlinear resistor ᑬa with the driving-point char- where it is assumed that ␶a ⬅ RaCa 앒 ␶b ⬅ RbCb and ␶*a ⬅
acteristics of Fig. 10(b). This characteristic has three seg- R*a Ca Ⰶ ␶b ⬅ RbCb. This results in the following design con-
ments. In the inner one, for low currents, the equivalent straint:
resistance Ra is very large, and the circuit behaves as a capac-
itive-input architecture. On the other hand, for large cur- δH
2
τa
> 2D EOH (56)
rents, the equivalent resistance R*a is much smaller and the Ra τu
circuit behaves as a resistive-input one.
To calculate the incremental dynamic sensitivity, consider where the incremental dynamic sensitivity is given by Eq.
that the voltage comparator has one-step architecture, similar (48). On the other hand, the formula for the static resolution
to Fig. 9(e). Following the application of a current step of am- parameter [Eq. (52)] remains valid.
plitude ⌬D, the input voltage evolves quasi-linearly with time In the more general case of an excitation between two over-
while in the inner segment of the nonlinear resistor and re- drive levels ⫺JL and JH, the dynamic evolution of the input
mains quasi-constant otherwise. Correspondingly, the output node also includes points in the outer segments of the nonlin-
voltage evolves quadratically with time during the first part ear resistor [see the dynamic route of Fig. 10(c)], and calculat-
of the transient and linearly afterward. To keep the speed ing the output waveform is not direct. However, neglecting
advantages of capacitive-input architecture, the restoring delays in the devices used to realize the nonlinear resistor,
logic level EOH should be reached during the first part of the the response time will be a monotonic function of the time
transient, that is, such that, invested for the input voltage to change from ⫺웃L to 웃H.
Hence,
 
TA Ca
ya (TA ) ≈  Ra < δ H TC = f (δ + δL ) (57)
τa D JH H

and where the exact functional relationship depends on the actual

voltage comparator used.
Figures 10(d) and 10(e) show simple CMOS nonlinear re-
1 TA2 sistor realizations. Both yield 웃L ⫽ 兩VTP兩 and 웃H ⫽ VTN. This
y(TA ) = EOH ≈  Ra (55)
2 τu τa D results in a rather large dead zone around 2V, and hence Eq.
598 COMPARATOR CIRCUITS

(57) anticipates rather poor response time. In the case of Fig.
10(e), the dead zone length can be reduced by biasing the
gates of MN and MP with different voltages, namely, VGN ⫽
VTN ⫺ 웃L and VGP ⫽ 兩VTP兩 ⫹ 웃H. This can be done with the
circuit of Fig. 10(f), which consists of two stacked complemen-
tary, first-generation current conveyors as originally proposed
by Smith and Sedra (33). The circuit is similar to the class
AB current amplifier proposed in Ref. (34) (see also Ref. 35
for an improved version). In any case, 웃H and 웃L should be
large enough to guarantee that the central region of the driv-
ing-point characteristics matches that of the voltage compara-
tor under global and local statistical variations of the techno-
logical parameters. Such a large central region length may
induce significant loading errors in operating the stage used
to drive the comparator (30). Besides, the aspect ratios of MN
and MP must be large enough to reduce R*a .
Current Comparators with Nonlinear Feedback
Figure 11(a) shows an improved architecture that reduces the
central region length. Contrary to Fig. 10(a), the voltage-mode
comparator of Fig. 11(a) does not operate in open loop but
uses the nonlinear resistor for negative feedback. There are
three different operating regions that correspond to the three
segments of the nonlinear resistor characteristic depicted in
Fig. 10(b). For small changes around the quiescent point
(x⫹ ⫽ x⫺ ⫽ 0), the equivalent resistance of the feedback resis-
tor is large, the voltage amplifier operates practically in open

x
Ra
Ra

A B

+ +

y
Ca ya
x+(t) x–(t) –
–
E

(a)

x
Ra
MN

Slope
( (
1 + A0
Ra
Slope
( (
1 + A0
Ra *
xN

E +
– ∆L x(t) y
y
∆H –
xp
MP

(b) (c)

IB
MP
xN
MP
E + xN
x(t) y +
E
– y
x(t)
xp –
xp
MN

MN
(d)
IB

Figure 11. Current-mode comparator us-

ing nonlinear feedback. (e)

loop, and the circuit preserves the capacitive-input feature
(the comparator input is the high-impedance type). For x⫹ ⬎
x⫺, voltage ya is pulled up and the amplifier decreases y. Thus,
the resistor enters in the rightmost segment of the character-
istic, allowing the input voltage to reach a bounded steady-
state (the input of the comparator is a low-impedance node).
A dual situation occurs for x⫹ ⬍ x⫺, where ya is pulled down
and y is high. Consequently, the comparator sees the charac-
teristics of Fig. 11(b), where, when E ⫽ 0,
δL
L =
1 + A0
and
δH
H = (58)
1 + A0
where A0 denotes the amplifier gain and ⫺웃L and 웃H are the
nonlinear resistor breakpoints. Note that the central region
length reduces as the amplifier gain increases. A negative
consequence of feedback is that the output signal becomes
clamped at ⫺웃L and 웃H, respectively. Hence, it may be neces-
sary to cascade an additional voltage comparator to restore
the logic level.
Figures 11(c) and 11(d) show practical CMOS realizations
of the nonlinear feedback current comparator. A common fea-
ture of these circuits is that the transition region of the non-
linear resistor tracks by construction that of the voltage am-
plifier, which means that the operation is insensitive to
mismatches and hence permits using minimum size transis-
tors. This is important because minimum transistors mean
minimum parasitic capacitances and hence reduced response
times.
In the case in Fig. 11(c), simple CInvC or InvC structures
can be used for the voltage comparator, thus leading to very
compact realizations. However, this structure has the draw-
back that the transient behavior is largely dominated by the
overlapping capacitance Cf which connects input and output
terminals of the voltage amplifier. Analysis obtains the fol-
lowing expression for comparison time (30):
A0 C where
TC ≈ (V + |VTP |) f (59)
1 + A0 TN JH
which implies that, although the high-resolution properties of
the capacitive-input architecture remain, the quadratic re-
sponse feature is lost due to the Miller effect created around
Cf , significant even for minimum size feedback transistors.
The circuit of Fig. 11(d), called a current steering compara-
tor, circumvents this problem by decoupling the amplifier in-
put and output nodes. Its static operation follows principles
similar to those used in the circuit of Fig. 11(c). When x(t) ⫽
0, transistors MP and MN are OFF and the circuit realizes
capacitive-input behavior. Positive currents integrate in the
input capacitor increasing the node voltage and consequently
decreasing y until the transistor MN becomes conductive, ab-
sorbing the input current and stabilizing the output. The
same occurs for negative currents, where MP is the conductive
transistor. For transient behavior, analysis shows, that under
COMPARATOR CIRCUITS 599
the same assumptions as for the circuit of Fig. 11(a), the re-
sponse time is given by (36),

2τ C
u s
TC ≈ (VTN + |VTP |) (60)
JH
where ␶u is the unitary time constant of the voltage compara-
tor and Cs is the input capacitance.
To conclude this section, Fig. 11(e) shows a circuit similar
to Fig. 11(c) where transistors MP and MN are swapped and
the feedback is positive, instead of negative. It operates as a
CMOS current Schmitt trigger where the positive and nega-
tive threshold values of the hysteretic characteristic are de-
fined by the lower and upper current sources, respectively.
APPENDIX I. SIMPLIFIED MOST MODEL
MOS transistors exhibit different operation depending on the
current and voltage levels. Throughout this article we consid-
ered only the MOST model under strong channel inversion,
and described its first-order behavior using a model with four
parameters, namely, zero-bias threshold voltage VT0, the slope
factor n, the intrinsic transconductance density 웁0, and the
equivalent Early voltage VA (37). Two subregions are consid-
ered within strong inversion:
• Triode (or ohmic) region. In this regime, the source and
drain voltages VS and VD remain below Vp ⫽ (VG ⫺
VT0)/n, where VG is the gate voltage (all voltages are re-
ferred to the local substrate). The drain current takes the
form
W  n 
ID = 2β0 VG − VT 0 − (VD + VS ) (VD − VS ) (61)
L 2
where W/L is the aspect ratio of the transistor.
• Saturation region. Assuming forward operation, this re-
gime is reached when VS ⬍ Vp ⬍ VD and the drain current
is given by

VD − Vp

ID = βN (VG − VT0 − nVS )2 1+ (62)
VA
β0 W
β≡
n L
ACKNOWLEDGMENT
This work has been partially supported by Spanish C.I.C.Y.T.
Project TIC96-1392-C02-02 (SIVA).
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1. L. A. Glasser and D. W. Dobberpuhl, The Design and Analysis of
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3. A. Rodrı́guez-Vázquez, M. Delgado-Restituto, and F. Vidal, Syn-
thesis and design of nonlinear circuits, in W. K. Chen (ed.), The
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Circuits and Filters Handbook, Boca Raton, FL: CRC Press, 1995,
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Reading List
G. Palmisano and G. Palumbo, Offset compensation technique for
CMOS current comparators, Electron. Lett., 30 (11): 852–854,
1994.
G. Palmisano and G. Palumbo, Offset-compensated low power current
comparator, Electron. Lett., 30 (20): 1637–1639, 1994.
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Signal Process., 43 (12): 785–790, 1996.
ANGEL RODRÍGUEZ-VÁZQUEZ
MANUEL DELGADO-RESTITUTO
JOSÉ M. DE LA ROSA
Institute of Microelectronics of
Seville
RAFAEL DOMÍNGUEZ-CASTRO
University of Seville
402 COUNTING CIRCUITS
COUNTING CIRCUITS
Counting circuits are found in a wide variety of electronic in-
strumentation and general digital computing systems. These
circuits are used to count events, to accumulate sums, to hold
pointers to memory instructions and data, and to perform
other similar functions which require iterative computations.
The term counter is most commonly used to refer to circuits
that perform counting functions and, more specifically, to
binary counters used in digital or hybrid digital/analog
systems.
An example of the use of a counting circuit can be seen in
a simple frequency meter. The input waveform is sampled
over a fixed interval. A counter is used to add up the number
of times that the signal increases above a certain threshold
voltage. If the sample interval is 1 s and the waveform is
sinusoidal, the counter contains the number of cycles per sec-
J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.
C1 C2 C3
I1 T Q T Q T Q
Figure 1. Simple binary counter. A three-bit counter will count from
0 to 7.
ond or the frequency of the signal. In typical simple meters,
this value is converted from its binary form stored in the
counter circuit to a binary coded decimal form used to drive a
set of light-emitting diode (LED) displays.
Digital counters are generally based on a series of binary
storage elements called flip-flops. A flip-flop element stores
either a binary 0 or 1. By logically connecting a set of flip-
flops, it is possible to represent related binary digits and thus
represent numbers.
An elementary binary counter can be constructed by con-
necting a set of T flip-flops as shown in Fig. 1. Each T flip-
flop changes the state of its output Q from 0 to 1 or vice versa
every time the T input changes from 1 to 0. The output wave-
form produced at each stage output C1 through C3 is shown
in Fig. 2. Output C1 represents the lowest-order binary digit
(called a bit), while C3 is the highest-order bit. By examining
the waveform, it can be seen that before the first 1 to 0 transi-
tion on the input I1 signal, the outputs represent the binary
value 000. After the first 1 to 0 transition on input I1, the
outputs represent the value 001. The second 1 to 0 transition
on I1 causes a 010, or binary 2, to be output by the counter.
Counting continues until the value 111 is reached. Once this
maximum counter value of 7 is reached, the next 1 to 0 transi-
tion on input I1 causes the outputs to change to 000 and the
counter begins counting up again.
Each successive stage of the counter in Fig. 1 changes
state, or counts, every second time the preceding flip-flop
changes state. The frequency of the waveform produced at
any output is half the frequency of the stage input. Each stage
is said to be a divide-by-two counter, and the overall effect of
the three-stage counter is to produce an output waveform that
has the frequency of the input waveform divided by eight. An
N-stage counter divides the frequency of the input waveform
by 2N. The binary values actually stored in an N-bit counter
actually range between 0 and 2N⫺1.
1
I1 0
C1
C2
C3
Figure 2. Binary counter output waveforms. The inherent delay in
each flip-flop stage delays the transition of the next higher-order
stage. In the worst case situation, the output of the highest-order
stage will be delayed by an amount proportional to the number of
stages.

Up
C1 And
Q Q
I1 T Or T Or
Q*
And
Dn
Figure 3. Three-bit up/down counter. Signals Up and Dn must remain constant during
counting.
The specific interconnection of the feed-forward or feed-
back signals within a counter determine its counting charac-
teristics. The counter shown in Fig. 3 is a 3-bit up/down
counter. Each time the I1 input line transitions from 1 to 0,
the counter changes states. When the input UP is a 1, the
counter counts up; when DN is a 1, the counter counts down.
Only one of the two inputs UP or DN may be at logic 1 any
particular time.
The counters shown in Figs. 1 and 3 are both said to be
asynchronous counters since each of the flip-flops in the
counters operates independent of a central clock. In fact, this
type of counter is generally referred to as a ripple counter,
indicating that the change of state of the overall counter actu-
ally transitions through the counter stage by stage rather
than having all flip-flops change state simultaneously. This
ripple effect can cause difficulties in systems that are meant
to be operated synchronously. For example, as the 3-bit ripple
counter transitions from state 111 to state 000, there is an
inherent delay of signals passing from one stage to the next.
The actual output signals transition from 111 to 110 to 100
and finally to 000. Although the intermediate values of 110
and 100 only last for a very short time, their appearance can
cause problems. For example, if a logic circuit is monitoring
the counter output for the state 110, a false signal will be
incorrectly generated for a short duration when the counter
transitions from 111 to 000.
For a ripple counter, the amount of delay involved in tran-
sitioning from one correct state to the next correct state is
dependent upon the delay of the individual flip-flops. Assume
that a T flip-flop exhibits a one-unit delay before a change in
the input signal effect the output signal. A 3-bit ripple
counter presents its worst-case delay behavior when the state
of the counter changes from 111 to 000 (or vice versa when
counting down). This worst-case delay amounts to a three-
unit delay. Although this may seem insignificant, when a
more typical counter like a 16- or 32-bit counter is considered,
the cumulative delay of 16 or 32 units can become very sig-
nificant.
C1 C2
And
Count T Q T Q
Clk
C C
COUNTING CIRCUITS 403
C2 And C3
Q
T
Q* Q*
And
A mechanism to relieve this potential error condition is to
design all of the counter flip-flops to be simultaneously trig-
gered by the same clock. That is, the outputs of all flip-flops
are directed to change at the same time under the control of
a single clock signal. This type of counter is called a synchro-
nous counter.
An example of a synchronous 3-bit binary counter is shown
in Fig. 4. The T flip-flops in this circuit change state if the T
input is 1 when the clock input C changes from a 1 to a 0.
The circuit counts input CLK pulses whenever the input
COUNT is 1. All outputs of this counter change in synchroni-
zation with the clock signal CLK. The disadvantage of this
type of counter is the additional logic gates that must be in-
cluded in the circuit. For an N-bit counter, each subsequent
stage N requires an additional logic gate which must have
N ⫺ 1 inputs.
The timing waveform for the synchronous counter of Fig.
4 is shown in Fig. 5. Notice that this waveform looks very
similar to that shown in Fig. 2. The difference is the lack of
ripple delay at each of the individual stage transitions.
Other variations on the basic counter scheme are found in
a wide variety of applications. Counters that are capable of
loading arbitrary starting values are typically used to keep
track of the sequence of instructions being executed in a digi-
tal computer. The ability to load a new starting value allows
the programmer to cause branching within a sequence of in-
structions. Some counters are configured to have arbitrary re-
set or terminal count values. This type of counter contains
external logic that loads a new starting value once a certain
termination count has been reached. Counters of this type are
called modulo-x counters, where x is the value representing
the terminal count. An example of this type of counter is one
which counts from 000 to 101, returns back to 000, and starts
counting again. The ability to reset a counter after a fixed
count sequence is quite handy when nonprogrammable hard-
ware is being used.
Counters are also frequently used to apply test vectors to
a digital circuit. A counter is loaded with an initial count, and
C3
T Q
Figure 4. Synchronous binary counter.
C
More logic gates are needed than in the
ripple counter.
404 CRITICAL PATH ANALYSIS

I1

C1

C2

C3

Figure 5. Synchronous 3-bit counter output waveforms. All outputs

change together after a short flip-flop delay.

a prescribed count sequence applies counter outputs to the

inputs to combinational circuits. The response of the combina-
tional circuit is monitored to determine if errors exist in the
behavior of the circuit. In this situation the counter is not
part of the operational circuit but is rather an ancilliary de-
vice which only comes into play during the circuit testing pro-
cedure. This type of counter must be designed and built to be
highly reliable since it becomes the key link in the testing
chain of an operational circuit.
Implementation of a counter is no different from the imple-
mentation of any other logic circuit. Good very large scale in-
tegration (VLSI) design practices dictate that the clocked
components (the flip-flops) be physically as close as possible
in order to minimize timing anomalies.

BIBLIOGRAPHY

W. I. Fletcher, An Engineering Approach to Digital Design, Englewood

Cliffs, NJ: Prentice-Hall, 1980.
R. J. Feugate, Jr. and S. M. McIntyre, Introduction to VLSI Testing,
Englewood Cliffs, NJ: Prentice-Hall, 1988.
R. L. Geiger, P. E. Allen, and N. R. Strader, VLSI Design Techniques
for Analog and Digital Circuits, New York: McGraw-Hill, 1990.
F. J. Hill and G. R. Peterson, Introduction to Switching Theory and
Logical Design, 3rd ed., New York: Wiley, 1981.
E. J. McCluskey, Logic Design Principles with Emphasis on Testable
Semicustom Circuits, Englewood Cliffs, NJ: Prentice-Hall, 1986.
D. A. Pucknell, Fundamentals of Digital Logic Design with VLSI Cir-
cuit Applications, Englewood Cliffs, NJ: Prentice-Hall, 1990.
N. Weste and K. Eshraghian, Principles of CMOS VLSI Design: A
Systems Perspective, Reading, MA: Addison-Wesley, 1985.

JOSEPH G. TRONT
Virginia Polytechnic Institute and
State University

COUPLERS. See DIRECTIONAL COUPLERS.

COUPLING MEASURES. See SOFTWARE QUALITY.
COVERAGE, INSURANCE. See INSURANCE.
CPM. See MINIMUM SHIFT KEYING.
CRITICAL CURRENT, SUPERCONDUCTING. See
SUPERCONDUCTING CRITICAL CURRENT.
434 CURRENT CONVEYORS

iY 0 0 0 vY
vX 1 0 0 iX
iZ 0 –1 0 vZ

Drain
iD vY iZ
Y
Gate CCII– Z
vG X
iS iX
Source
Figure 2. Comparison of a CCII⫺ and an ideal field effect transistor.

conveyed to Z. Node Z had a very high impedance. Applica-

tions of the CCI included current meters and negative imped-
CURRENT CONVEYORS ance converters (NICs). To increase the versatility of the cur-
rent conveyor, a second-generation current conveyor (CCII)
A current conveyor is an active circuit used to carry out ana- was introduced (2). This design was the same as the previous
log signal processing functions for many different types of ap- except that no current flowed through node Y. This design
plications. In general, this device has two inputs and n out- was introduced in 1968 and is described by the following hy-
puts; however, most applications involve a current conveyor

i 
0 
v 
brid matrix:
with two inputs and one output port, as illustrated in Fig. 1
(1). The current conveyor can be thought of as a basic design Y 0 0 Y
building block much like an operational amplifier. During vX = 1 0 0 iX (2)
work on his master’s thesis in 1966, Adel Sedra was devel-
iZ 0 ±1 0 vZ
oping a voltage-controlled waveform generator to be used as
part of a design of a programmable instrument for incorpora-
The current supplied to node X has either a positive or nega-
tion in a system for computer controlled experiments, when
tive polarity resulting in the CCII⫹ or CCII⫺, respectively.
he happened upon a novel circuit (2). He generalized the con-
The CCII⫺ can be thought of as an ideal field effect transistor
cept and developed the current conveyor, a circuit that conveys
(FET) where the gate ⫽ node Y, drain ⫽ node Z, and source
current from one port to another. His original design, now
⫽ node X. This relationship is illustrated in Fig. 2. Tradition-
called a first-generation current conveyor (CCI) is a three-port
ally, the current conveyor has been implemented using low-
device (with ports defined as X, Y, and Z) described by the
frequency bipolar transistors, FETs, or operational amplifiers

i 
0 
v 
following hybrid matrix:
(3–5). Two particular applications of the current conveyor are
1 0 active network synthesis and analog signal processing. Table
Y Y
1 (6) illustrates several networks useful in active network
vX = 1 0 0 iX (1)
synthesis. These circuit topologies are by no means the only
iZ 0 1 0 vZ way to implement these functions.
An important application is analog signal processing. Ta-
This circuit exhibited a virtual short circuit at node X, a vir- ble 2 (6) illustrates the use of current conveyors to carry out
tual open circuit at node Y, and the current supplied at X was five different signal-processing functions. For purposes of
analysis, it is much easier to relate the current conveyor to
two ideal one-port networks known as norators and nullators.
Iy
Vy Iz
Y NULLATOR–NORATOR CIRCUIT ANALYSIS AND ITS
Z Vz
Vx
APPLICATION TO CURRENT CONVEYOR DESIGN
X
Ix
(a)
There is good reason to discuss the design of current conveyor
circuits using nullator–norator design techniques. One of the
I z+ strongest motivations is that numerous papers and texts have
Iy Z 1+ V z+ Iz+ = –Iz– = –Ix been written that address circuit synthesis using these ideal
. . 1
Vy Y . . circuit elements (7–11). As a result, the use of this technique
Z N+ V z+ provides the designer with a wealth of information on design-
N
ZN–+1 V z– ing many types of active networks including negative imped-
Vx X . . N+1
. . ance converters, negative impedance inverters, positive im-
Ix Z M– V z–
M pedance inverters, and a myriad of other useful active
I z– networks. All that is required to use this information is a ba-
(b)
sic understanding of circuit analysis using the norator–
Figure 1. Current conveyor schematic definitions: (a) basic current nullator approach and an understanding of how to convert
conveyor and (b) multiple output current conveyor.  1996 IEEE. norator–nullator topologies into current conveyor topologies.

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.
 CURRENT CONVEYORS 435

Table 1. Application of Current Conveyors to Active Network Synthesis

Characterization Realization Using Current Conveyors
1 2 x
i1 i2
CC z
2-Port y
v1 v2
Realized

Voltage
2 CCII
controlled 0 0
1 G= 1 +
Voltage 0 1
source

Voltage g
controlled 0 0 CCII
2 Y= 2
g 0 1 —
Voltage
source

Current
1 CCII
controlled 0 0 2
3 H= 1 0 +
Current
source

Current 1 2
controlled CCII CCII
4 0 0
Z= — +
Voltage R 0 R
source

2 2
CCI CCII
5 INIC 0 1
G= + +
1 0
1 1

g2 g1
0 g1 CCII CCII
6 NIV Y= + +
g2 0
1 2

g g
0 g CCII CCII
7 Gyrator Y= — +
g 0
1 2

 1970 IEEE.

When analyzing active linear networks, several distinct
types of circuit elements are used. These include resistors,
capacitors, inductors, transmission lines, independent voltage
sources, independent current sources, dependent voltage
sources, and dependent voltage sources. The dependent volt-
age and current sources tend to be two-port networks that
associate a voltage or current from one port to a voltage or
current to the second port. Although analyzing circuits con-
taining these two-port networks is relatively straightforward,
the simultaneous solution of equations that usually results
from such analysis serves to reduce the designer’s intuition
about the circuit. The use of two ideal one-port network repre-
sentations known as nullators and norators can help to re-
store some of this lost intuition. Nullators and norators can
replace all dependent voltage and current sources in a net-
work so as to reduce the primitive elements in a linear net-
work to only one-port networks. This is a very powerful tech-
nique that can be used to gain insight into active network
synthesis (7–9). The properties of the nullator and norator
will now be introduced.
Definition 1. A nullator is a one port network with v1(t) ⫽
i1(t) ⫽ 0 defining the the voltage and current on its one port
(9).
Definition 2. A norator is a one port network with v1(t) ⫽
A1(t) and i1(t) ⫽ A2(t) defining the voltage and current on its
one port. The functions A1(t) and A2(t) are arbitrary, and thus
v1(t) and i1(t) are unconstrained resulting in a degree of free-
dom not found in any other one port network (9).
The schematic symbol used to describe the nullator and
norator are shown in Fig. 3. When carrying out nodal circuit
analysis of a circuit that has nullators and norators, Defini-
436 CURRENT CONVEYORS

Table 2. Application of Current Conveyors to Analog

Signal Processing

Realization Using Current Conveyor

x
CC z
Functional y
Element Function

R2
Current CCII I0
amplifier R1
I0 = (R1/R2)II +
Ii

C
Current CCII I0
differentiator dI1 R +
I0 = CR
dt
Ii

R
Current CCII I0
integrator C
I0 = 1
I1 dt +
CR
Ii

I1
Current I0
n I2 CCII
summer I0 = —• Id
i In +

R
Weighted R1 I0
n Rj I1 CCII
current I0 = —• Id R
i R +
summer
Rn
In

 1970 IEEE.

tions 1 and 2 can be easily applied when the node being ana-
lyzed has a norator or nullator connected to it. When a node
has a nullator connected to it, the voltage at that node is as-
sumed to be equal to the voltage at the other node of the nul-
lator; however, it is assumed that no current can flow through
the nullator. When a node has a norator connected to it, it is
assumed that current flows through the norator, but the volt-
ages on either node of the norator are determined by the rest
of the circuit. Similarly, the current through the norator is
determined by the rest of the circuit.
i1 i1
+ +
v1 v1
– –
Nullator Norator
v1 = i1 = 0 v1 = i1 arbitrary
Figure 3. Norator and nullator schematic representations.
Several equivalence properties of norators and nullators
that allow for network simplification will be described pres-
ently (9):
1. A series or parallel connection of ⫾Rs, ⫾Ls, ⫾Cs, and
at least one nullator is equivalent to a single nullator.
2. A series or parallel connection of ⫾Rs, ⫾Ls, ⫾Cs, and
at least one norator is equivalent to a single norator.
3. A series or parallel connection of ⫾Rs, ⫾Ls, ⫾Cs, and
at least one norator and at least one nullator is equiva-
lent to an open circuit or a short circuit, respectively.
4. A four-terminal circuit composed of two nullators and
two norators all of which have a single terminal tied to
one node is equivalent to a four-terminal network com-
posed of an uncoupled single nullator and a single
norator.
Another circuit element that is worth mentioning is the nul-
lor. The nullor is a two-port network, which is simply com-
posed of a nullator at one port and a norator at the second
port. Effectively, it is two uncoupled one-port networks. The
schematic symbol for this network is illustrated in Fig. 4. The
reason for its use is that many dependent current and voltage
sources can be expressed in terms of this unit. It is important

i1 i2
+ +
Port 1 Port 2
v1 v2
v1 = i1 = 0 v2 = i2 arbitrary
– –
Figure 4. Nullor schematic representation.
to note that the nullor can always be thought of as simply a
nullator and a norator and, therefore, provides no additional
insight into the analysis of a network. It is mentioned here
merely so that the reader will be familiar with the termi-
nology.
Given the matrix definition of the negative second-genera-
tion current conveyor (CCII⫺) from Eq. (2), an equivalent rep-
resentation for the CCII⫺ can be expressed in terms of a sin-
gle nullator and norator as illustrated in Fig. 5. The hybrid
matrices for these two circuits are equivalent. In summary,
any active network composed of nullators and norators in
pairs, as illustrated in Fig. 5, can be fabricated using CCII⫺
networks. This fact will prove to be a useful property for syn-
thesizing many types of active circuits.
As an example, two useful illustrations of the nullator–
norator design technique types will be discussed. First, the
impedance inverter is presented. Table 3 (10) illustrates five
different methods for carrying out voltage and current inver-
sion. It is important to note that these realizations do not
require a specific hardware realization. By looking for pairs
of norators and nullators, we can convert these circuits into
current conveyor circuits. Each topology will have its own spe-
cific performance benefit as explained in Ref. 10.
Another useful topology is shown in Fig. 6 and can be used
as a general impedance converter (GIC). Each of the branches
of the circuit can be a complex impedance. The relationship
that will hold between impedances is
Z1 Z3 Z5 = Z2 Z4 Z6
The way the network is used is to remove one of the complex
load impedances illustrated in Fig. 6 and solve for its value
in terms of the remaining five impedances. The relationship
in Eq. (3) will define the effective impedance at the circuit
port where the complex impedance was removed. This process
allows for the transformation of one of the five remaining load
impedances to an effective output impedance whose proper-
v1
i2 P1
v1
P1
CCII– P2
P3
P3
i3
i3
i3 = –i2
v1 = v3
Pi denotes the ith port
Figure 5. Nullator–norator representation of a CCII⫺.
CURRENT CONVEYORS 437
ties depend on the circuit elements used in the network, thus
the name general impedance converter (GIC). This type of cir-
cuit can be used as a positive impedance converter (PIC) or a
positive impedance inverter (PII). Another useful application
of this circuit is realization of a frequency-dependent negative
resistance (FDNR), sometimes called a D element or an E ele-
ment (9). These are very useful in active filter synthesis as
explained by Bruton (9). Filters can be synthesized using only
FDNRs and resistor elements. The D element has an imped-
ance Z ⫽ k/s2 where k is real and s is the complex frequency
variable of the Laplace transform. Similarly, the E element
has the form Z ⫽ ks2 where again k is real.
Note that pairs of norators and nullators from Fig. 6 can
be replaced with second-generation current conveyors. The
way in which these current conveyors can be realized in hard-
ware is the subject of the next section.
CURRENT CONVEYOR CIRCUIT ARCHITECTURE
Current conveyors can be built using either bipolar or metal
oxide semiconductor (MOS)–type transistors. Because the
majority of applications to date have focused on the second-
generation current conveyor, this type of current conveyor
will be addressed here. Another motivation for focusing on
the implementation of second-generation current conveyors is
that first- and third-generation current conveyors can be real-
ized using multiple output second-generation current con-
veyors (1,12). As mentioned earlier, a CCII⫺ can be thought
of as an ideal FET. Similarly, it can also be thought of as an
ideal bipolar transistor. In reality, FETs and bipolar devices
do not behave ideally, and thus more complex circuit imple-
mentations result in order to compensate for the imperfec-
tions of real devices. In the process of obtaining more ideal
performance, many devices may need to be combined in order
to model more closely the ideal behavior exhibited by an ideal
device. Implementation of CCIIs with bidirectional current
capabilities require the use of complementary devices (i.e.,
p–n–p and n–p–n bipolars or nMOS and pMOS FETs) (13).
It is difficult to fabricate an integrated circuit (IC) with iden-
(3) tically performing p–n–p and n–p–n devices. It is much eas-
ier to support complementary structures using MOS devices,
and thus many IC current conveyor designs are based on
MOS implementation. Figures 7 and 8 (13) illustrate CMOS
implementation of CCII⫹ and CCII⫺ current conveyors, re-
spectively. In Fig. 7 current is transferred to the output using
complementary current mirrors. To fabricate a CCII⫺ (Fig.
8), two additional current mirrors are required.
A new approach to designing current conveyors at micro-
wave frequencies has been proposed by Sinsky and Westgate
(14). This approach uses a GaAs monolithic microwave inte-
grated circuit (MMIC) to closely approximate the required hy-
brid matrix parameters of Eq. (2) over a specified band of mi-
crowave frequencies. This technique was developed to support
the design of tunable synthetic microwave circuit elements
using negative impedance converters (NICs) and positive im-
P2 pedance converters (PICs). Such circuits can be used to design
i2 tunable microwave filters and matching networks.
NOISE CONSIDERATIONS
In many applications, it is necessary to have a current con-
veyor that has good noise performance. Current mode circuits
438 CURRENT CONVEYORS

Table 3. Voltage and Current Inversion Using Nullators

and Norators

Type Voltage Inversion Current Inversion

V2 = —V1 I2 = I 1 —I2 = —I1 V2 = V 1

G1 G2

II R1 R2

V2 = —(R2/R1)V1 —I2 = I1 —I2 = —(G2/G1)I1 V2 = V 1

R1 R2

III G1 G2

V2 = —(R2/R1)V1 —I2 = I1 —I2 = —(G2/G1)I1 V2 = V 1

R1 R2 G1 G2

IV

V2 = —(R2/R1)V1 —I2 = I1 —I2 = (G2/G1)I1 V2 = V 1

V R1 R2 G1 G2

V2 = [1 — (R2/R1)]V1 I2 = I1 —I2 = [1 — (G2/G1)]I1V2 = V1

 1970 IEEE.

(such as the current conveyor) are candidates for use in low-

voltage analog signal processing because large current swings
can be obtained even with small voltage excursions. Unfortu- VDD
nately, for low-noise performance in such circuits, low-noise
bias circuitry, which tends to require higher voltages for the
required low-transconductance devices, is required. This pre-
sents a design challenge when trying to obtain low-noise, low-

iZ = –iX
Y +
Z
Z2 3
A(s) Z
X –

iX

Z1 Z4

Z
6 Z5 VSS

Figure 7. Positive second-generation current conveyor using MOS

Figure 6. Norator–nullator immitance converter/inverter topology. devices and OP amp.  IEE 1990.

voltage current conveyors. The problem of designing low-noise
current conveyors is best addressed by Bruun (1,12) who has
developed a way to look at the problem and drawn some im-
portant conclusions.
Ideal Current Conveyor Noise Analysis
To address noise issues in the CCI, CCII, and CCIII type cur-
rent conveyors, it is sufficient to analyze the multi-output
CCII current conveyor as shown by Bruun (1,12). The general
noise analysis requires addressing the multi-output current
conveyor illustrated in Fig. 1. Because this device has multi-
ple outputs, noise contributions cannot be modeled using only
an equivalent noise input voltage and current as done on con-
ventional amplifiers. The multiple outputs may have corre-
lated and uncorrelated noise contributions, and thus noise
sources must be assumed at each of the output ports as well
as the input ports. For more details on the mathematical for-
mulation of the noise for the multioutput second-generation
current conveyor, see Refs. 1 and 12. Because most applica-
tions simply require single output CCII⫹ or CCII⫺ current
conveyors, the noise modeling for this type of device will be
emphasized here. For an ideal two-input single-output sec-
ond-generation current conveyor whose input X terminal is
terminated in an impedance RX and whose Y input is termi-
nated in an impedance RY where RSX Ⰷ RSY, Bruun (1,12) has
shown that
dv2yeq 4kT
di2z = di2xeq + di2z eq + + df
R2SX RSX
where k is Boltzmann’s constant, T is the absolute tempera-
ture, and df is the frequency bandwidth considered (see Fig.
VDD
iZ = –iX
Y +
A(s)
X –
iX
VSS
Figure 8. Negative second-generation current conveyor using MOS
devices and OP amp.  IEE 1990.
CURRENT CONVEYORS 439
dv2yeq
Iy
+ –
Vy Y
Z
Ix
Vx X Iz
2 2 2
diyeq dixeq dizeq
Figure 9. Second-generation current conveyor with equivalent
noise sources.
9). The dominant source of error in this formulation is the
finite input and output impedances to the current conveyor.
CMOS Current Conveyor Noise Considerations
A detailed analysis of noise optimization for CMOS current
conveyors has been carried out by Bruun (1,12). For class A
designs, it was found that the optimal signal-to-noise ratio is
proportional to the maximum output terminal current (the Z
terminal of Fig. 1 is the output terminal). This is because the
output noise power of the current conveyor is proportional to
the bias current and the output signal power is proportional
to the square of the output terminal current. Interestingly,
the class AB-biased current conveyor can provide better per-
formance than the class A circuit because the output signal
swing is not limited by the bias current. In summary, the use
(4) of low-noise bias circuitry and current mirrors are essential
in the design of low-noise CMOS current conveyors.
CONCLUSION
The current conveyor is a very powerful building block that
can be used in a myriad of applications ranging from power
supply control circuits to the design of high-frequency active
filters. Despite the many different applications and imple-
mentations of this circuit, there is one important point to re-
member: the current conveyor is a fundamental building
block that can be used in circuit synthesis in much the same
way as the operational amplifier. It allows the circuit designer
to concentrate on a higher level of circuit functionality. The
current conveyor has the capability to revolutionize the cir-
cuit design industry in much the same way as the operational
amplifier has. With much interest in current mode circuits, it
Z is inevitable that the current conveyors time has finally come.
BIBLIOGRAPHY
1. E. Bruun, Noise Properties of CMOS Current Conveyors, IEEE
MTT-S Symp. Des., 1996, pp. 144–147.
2. A. Sedra, G. Roberts, and F. Gohh, The current conveyor: history,
progress, and new results, IEE Proc., Part G, 137 (2): 78–87,
1990.
3. R. Senani, Novel circuit implementation of current conveyors us-
ing an O.A. and an O.T.A., Electron. Lett., 16 (1): 2–3, 1980.
4. K. Pal, New inductance and capacitor flotation schemes using
current conveyors, Electron. Lett., 17 (21): 807–808, 1981.
440 CURRENT-MODE LOGIC

5. M. Higashimura and Y. Fukui, Novel methods for realising loss-

less floating immitance using current conveyors, Electron. Lett.,
23 (10): 498–499, 1987.
6. A. Sedra and K. Smith, A second-generation current conveyor
and its applications, IEEE Trans. Circuit Theory, CT-17: 132–
134, 1970.
7. R. Senani, Floating immittance realisation: Nullor approach,
Electron. Lett., 24 (7): 403–405, 1988.
8. R. Senani, New tunable synthetic floating inductors, Electron.
Lett., 16 (10): 382–383, 1990.
9. L. Bruton, RC-Active Circuits, Englewood Cliffs, NJ: Prentice-
Hall, 1980.
10. J. Braun, Equivalent NIC networks with nullators and norators,
IEEE Trans. Circuit Theory, CT-12: 441–442, 1965.
11. V. Pauker, Equivalent networks with nullors for positive immit-
tance inverters, IEEE Trans. Circuit Theory, CT-17: 642–645,
1970.
12. E. Bruun, Analysis of the noise characteristics of CMOS current
conveyors, Analog Int. Circuits Signal Process., 12: 71–78, 1997.
13. C. Ioumazou et al., Analogue IC design: The current-mode ap-
proach, London, UK: Peregrinus, 1990.
14. J. H. Sinsky and C. R. Westgate, A new approach to designing
active MMIC tuning elements using second-generation current
conveyors, IEEE Microw. Guided Wave Lett., 6 (9): 326–328, 1996.

JEFFREY H. SINSKY
Bell Laboratories—Lucent
Technologies
CHARLES R. WESTGATE
Johns Hopkins University

CURRENT-FEEDBACK AMPLIFIERS. See ANALOG INTE-

GRATED CIRCUITS.
CURRENT MEASUREMENT. See AMMETERS; ELECTRIC
CURRENT MEASUREMENT.
CURRENT-MODE CIRCUITS. See TRANSLINEAR CIR-
CUITS.
44 DC AMPLIFIERS
DC AMPLIFIERS
The term direct coupled amplifier, or dc amplifier, means di-
rect coupling between the amplifier and the input signal to
be amplified. Basically, a directly coupled amplifier has no
capacitive or inductive coupling between the input source and
the amplifier. Consequently, the dc amplifier, as opposed to
capacitively coupled or ac amplifiers, allows amplification of
continuous and low-frequency signals (1,2). Direct coupled
amplifiers appeared at the same time as amplifiers. But they
have performed better ever since, and with the introduction
of integrated circuits (ICs), it was possible to use a truly dif-
ferential input stage implemented from a pair of matched
transistors (2,3). Figure 1 illustrates the direct and capacitive
coupling amplifications with alternating current (ac) and di-
rect current (dc) input voltage sources. For proper operation,
it is necessary to have the same reference voltage level for the
amplifier and the input signal. In most cases the ground is
used as the reference.
A large number of applications require dc amplifiers to am-
plify low-frequency signals down to dc. They are, for example,
used in dc–dc voltage down converters in which it is neces-
sary to amplify a dc voltage reference (4). Directly coupled
amplifiers are also used in linear feedback loops to control
speed or position of dc motors. There are many measurement
transducers, such as temperature sensors, or load transduc-
ers used to measure weights. These exhibit a very low dc out-
put voltage and are often directly coupled to a high-gain dc
amplifier (2). Direct coupled amplifiers are predominantly
used in monolithic integrated circuits where using coupling
capacitors would necessitate a large and expensive silicon
area (1). In addition, at very low frequencies, dc feedback am-
plifiers are also preferred to ac coupled feedback amplifiers,
which can induce ‘motorboating’ or stability problems due to
the phase shift caused by several capacitive coupled stages
(2). Other high-speed applications, such as optical communi-
Direct
Rs coupling
A S(t) = A [V + e(t)]
(a)
ac e(t)
dc V V0
Capacitive
coupling
A S(t) = A [ + e(t)]
(b)
Figure 1. Different kinds of coupled amplifiers: (a) dc amplifier; (b)
ac amplifier using coupling capacitor.
J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.
cations, necessitate high-performance dc amplifiers with a
wide bandwidth (5).
The amplifier gain and the dc operating point depend on
multiple parameters, such as transconductance, load resistor
values, bias currents, and power supplies. Inherent fabrica-
tion process variation, thermal drifts, and component sensi-
tivity inevitably introduce amplification and biasing errors.
The predominant errors result from voltage and current off-
sets corresponding to the input voltage and input current
which must be applied to force the output voltage of the am-
plifier to zero.
Considering the high process sensitivity of transistor pa-
rameters, offsets, and thermal drifts, the use of a single tran-
sistor input stage to build a dc amplifier is unreasonable. In
contrast, an input stage built from a differential pair of
matched transistors allows considerable reduction of these ef-
fects. This is the case, for example, of voltage-feedback opera-
tional amplifiers (VFOA), usually called op-amps. So, a high-
gain voltage-feedback amplifier allows designing an accurate
dc amplifier. In this case, with a very low common mode rejec-
tion ratio (CMRR), the gain of the dc amplifier depends only
on the feedback ratio that can be easily kept invariable.
GENERAL SCHEMA FOR DC AMPLIFIERS
Basic dc Amplifiers
Figure 2 shows the building blocks of a classical dc amplifier.
It is composed of three main stages. The first block corre-
sponds to a differential input stage and is followed by a sec-
ond which consists of a high-gain voltage amplifier. The last
stage is a voltage follower. Usually, the dc amplifier is biased
between positive (Vcc) and negative voltages (Vee ⫽ Vcc).
Considering the various gain stages, the output voltage
VO in the case of Fig. 2 is given by
VO = AGV Vid (1)
This expression clearly shows the dependence of the amplifier
gain on the parameters A and GV. Because these parameters
are sensitive to process variation and thermal drift, amplifier
gain varies from one component to the other. The differential
+Vcc
Input Voltage gain
stage
Out
e+
Output
A Gv 1
e–
Differential
input stage Voltage follower
–Vee
Figure 2. Schema block for a dc amplifier showing the various
stages.
 DC AMPLIFIERS 45

R2 R2
R1
Dc input
e– e–
R1 Dc input AGV VI AGV
e+ e+
VO VO
VI
Figure 3. The two configurations for dc
feedback amplifiers: (a) noninverting am-
(a) (b) plifier; (b) inverting amplifier.

input stage behaves as a preamplifier, and it amplifies offset
and drift voltages and currents. Consequently, the character-
istics of this preamplifying stage define the performance and
limits of the dc amplifier. Another important parameter is the
input noise that also limits the minimum detectable signal.
In the next section describing the characteristics of the differ-
ential input stage, we show that its components have to be
well matched to obtain the smallest error signal possible.
Main Effects of Feedback Loop
The feedback loop is used mainly to prevent amplification
from the variation of the dc amplifier gain (AGV). Figures 3(a)
and 3(b) describe the feedback loop technique in both nonin-
verting and inverting amplifiers. In these cases, considering
a dc amplifier with infinite gain (AGV 씮 앝) and infinite input
resistance gain, the transfer functions VO /Vi is given as fol-
lows:
rents Ib1 and Ib2, so that their effects are negligible, then the
collector currents are given by (6–9)
IC1 = (αF I0 )/[1 + exp(−Vid /VT )] (3)
IC2 = (αF I0 )/[1 + exp(+Vid /VT )] (4)
In these equations 움F ⫽ ⫺(Ic /Ie)VBC⫽0 is the common-base for-
ward, short-circuit current gain. Thus the expression of the
differential output voltage of this stage can directly be de-
duced from Eqs. (3) and (4):
Vod = RC (IC2 − IC1 ) = −αF RC I0 tanh(Vid /2VT ) (5)
As a result, for 兩Vid兩 Ⰶ 2VT, the differential output voltage has
a 180⬚ phase difference with respect to Vid, and the amplifier
gain is given by A ⫽ Rc ⫻ I0 (as 움F 앒 1). In this way, A is
increased by increasing either the value of load resistors RC

VO

R
 or the bias current I0. Nevertheless, increasing I0 leads to a
rise in power consumption. However, the value of RC is artifi-
Noninverting amplifier = 1+ 2 (2a)
Vi R1 cially enlarged by using active loads (current mirrors), which
VO R are easier to fabricate in IC form than high-value resistors.
Inverting amplifier =− 2 (2b) Figure 5, which shows the variation of output voltage as a
Vi R1
function of Vid, illustrates the nonlinear effects that appear as
soon as 兩Vid兩 approaches 2VT. For an ideal differential stage,
When resistors R1 and R2 are accurate, this system consti-
this reveals that the output voltage Vod is zero for Vi1 ⫽ Vi2.
tutes an excellent directly coupled amplifier. Thus, this tech-
nique is a good solution for removing some of the shortcom-
Real Differential Stage
ings of the dc amplifier.
For a real differential stage implemented in IC form, the base
currents of Q1 and Q2, the component mismatches (amplifier
ANALYSIS OF THE BIPOLAR DIFFERENTIAL INPUT STAGE
dissymmetry), the equivalent input noise, and the thermal
In this section, the relationship between input and output
voltages is determined for an ideal stage implemented from
+Vcc
bipolar transistors. Then, the mismatch effects (offsets and
drift sensitivities) are analyzed for a real dc amplifier.
Rc2 Rc1
Ideal Differential Stage Ic1 Ic2
Vod
Figure 4 shows the schema of an ideal differential input stage Vo1 Vo2
(or emitter-coupled pair), implemented from bipolar transis- Ib1 Ib2
Q1 Q2
tors. Vid ⫽ Vi1 ⫺ Vi2 is the differential input voltage, and
Vod ⫽ Vo1 ⫺ Vo2 is the differential output voltage of the circuit. Vi1 Vi2
For an ideal amplifier, i.e., including perfectly matched ele-
ments, transistors Q1 and Q2 are assumed identical, and resis-
tors RC1 and RC2 have the same value of RC. I0
For forward-biased transistors Q1 and Q2 (i.e., Vbe Ⰷ VT;
VT ⫽ kT/q is the thermal voltage), the reverse saturation cur- –Vee
rents of the collector–base junctions can be ignored. Neglect-
ing the Early effect and assuming very low values for cur- Figure 4. Bipolar differential input stage using matched devices.
46 DC AMPLIFIERS

Perfectly matched equivalent to the ideal differential stage previously discussed,

stage with Vos and Ios connected on input.
Differential stage Input Offset Voltage. This voltage results principally from
with mismatches the dissymmetries between transistors Q1 and Q2: mis-
Vod matches in the base widths, in the base and collector doping
levels, and in emitter areas. It is also caused by mismatch in
collector resistors RC1 and RC2. By definition Vos is the ideal
equivalent generator voltage, which applied to the input,
+ α F I0 Rc drives the output voltage (Vod) to zero. Then Vos ⫽ Vbe1 ⫺ Vbe2
(Fig. 6).
Differential stages Perfectly matched Assuming that the relationship between the base-emitter
with mismatches stage
voltage and collector current for a forward biased transistor
is VBE ⫽ VT ln(IC /IS),
– 4VT – 2VT VS 2VT 4VT Vid
Vos = VT ln[(IC1 /IC2 )(IS2 /IS1 )] (6)

Now the saturation and collector currents can be written as

– α F I0 Rc IS1 ⫽ IS ⫽ IS2 ⫺ ⌬IS and IC2 ⫽ IC ⫽ IC1 ⫺ ⌬IC. In addition, with
RC1 ⫽ RC ⫽ RC2 ⫺ ⌬RC, which represents the resistor dissym-
metry,

Figure 5. Differential output voltage as a function of input voltage RC2 IC2 = RC1 IC1
showing the curves for matched and mismatched stages.
Finally, assuming that ⌬IS /IS Ⰶ 1 and ⌬RC /RC Ⰶ 1, Vos can be
drifts must be taken into account to determine the minimum described by
differential dc voltage detectable (amplifier sensitivity).

RC IS
Vos = VT + (7)
Base Input Bias Currents. The dc input bias currents (Ib1 앒 RC IS
Ib2 in Fig. 4, for Vod ⫽ 0) required for biasing the transistors
are taken from the driving generators connected to the in- Input Offset Current. This current results principally from
puts. Their value, Ibias ⫽ (Ib1 ⫹ Ib2)/2, is directly related to the the mismatched values of the current gains 웁 of Q1 and Q2.
design of the differential stage. A very low base current value When Vod is zero, Ios is defined by Ios ⫽ Ib1 ⫺ Ib2. Assuming
requires high current gain (웁). This can be obtained, for ex- that 웁1 ⫽ 웁 ⫽ 웁2 ⫺ ⌬웁, from the previous equations
ample, by using Darlington or super ⫺웁 transistors. It can this gives
also be noted that the influence of the base currents is re-

duced to the minimum, if both inputs are driven by genera- IC RC β
Ios = + (8)
tors with the same equivalent output resistance. β RC β

Component Mismatch Effects. All of the effects due to ampli- Now we can deduce that the offset current is directly propor-
fier dissymmetry can be characterized with only two continu- tional to the base input bias current. Then a low value for Ios
ous generators: a voltage generator (Vos) and a current gener- necessitates either a low I0 or a high 웁. High RC values also
ator (Ios). These two generators are discussed in the next reduce this unwanted current Ios.
paragraphs. Thus, as indicated in Fig. 6, the real amplifier is Thermal Drift. We define thermal drift as the variation of
component electrical parameters with temperature. So, for a
given differential amplifier design, the drift of Ib, Vos, and Ios
+Vcc characterizes the influence of temperature on the output volt-
age Vod. Thus, the drift of the bias current Ib determines the
Rc2 Rc1 output stability for different values of the driving generator
resistance. The thermal drift of Vos can be directly calculated
Ic1 Ic2
Vos Vod
from Eq. (7). Assuming that RC and IS are temperature-inde-
Vo1 Vo2 pendent,
Ib1 Ib2
Q1 Q2 dVos Vos
= (9)
Vi1 Vi2 dT T
Ios
Equation (9) shows a direct proportionality to Vos. Moreover,
I0 a low drift for Ios is necessary to obtain low output variation
when the internal resistances of the driving generators have
–Vee high values.
Long-Term Drift Variation. All of the previous values of drift
Figure 6. Mismatched differential stage. Equivalent circuit with a given by manufacturers are rigorously valid for fresh compo-
perfectly matched amplifier and offset voltage and current sources. nents, but drift changes as components age.
 DC AMPLIFIERS 47

Voltage Input Noise. Low-frequency input noise is an im-

Vod
portant limitation in precision dc application, as, for example,
instrumentation measurements. + R dI 0

ANALYSIS OF MOS DIFFERENTIAL PAIR I0

K
Now we analyze a differential stage implemented from MOS
I0 Vid
transistors to compare their performance to bipolar ones. – K

Ideal Input Stage

An NMOS source-coupled pair is shown in Fig. 7. We assume – R dI 0
that both M1 and M2 are matched transistors with equal
W/L ratios (W is the channel width and L is the channel
Figure 8. The dc transfer characteristic of the ideal source-coupled
length) and equal threshold voltage Vth. We neglect the body pair.
effect and the channel modulation length. The load resistors
Rd are assumed identical. As usual we suppose that the drain
current is related to the gate-source voltage Vgs and the
threshold voltage Vth by the well-known approximate square- Note that for the MOS differential pair, the Vid range for
law relationship Id ⫽ K(Vgs ⫺ Vth)2, where the gain factor K ⫽ linear operation depends on the biasing current I0 and the
1/2애Cox W/L (애 is the electron-mobility and Cox is the gate W/L ratio of the transistors. In contrast, for the bipolar dif-
capacitance per unit). From Kirchhoff ’s laws it follows that ferential pair this range is about 2VT and is independent of
the differential input voltage is given by Vid ⫽ Vi1 ⫺ Vi2 ⫽ transistor size and bias current. The gain of the source-cou-
兹Id1 /K ⫺ 兹Id2 /K, and at the source node, Id1 ⫹ Id2 ⫽ I0. Com- pled pair depends on bias current I0, load resistance Rd, and
bining these expressions yields (8) transistor dimensions (W/L). In contrast, the gain for the bi-
 s
V 2  polar differential pair depends only on the biasing current I0
I0  2 and load resistance Rc.
Id1 = 1 + KVid − id  (10)
2 KI0 I0 The dc transfer characteristic of the source-coupled pair is
shown in Fig. 8. When 兩Vid兩 ⬎ 兹I0 /K, either M1 or M2 is com-
 s
V 2  pletely turned off, and Vod is equal to RdI0. An increase in I0
I0  2 
Id2 = 1 − KVid − id
(11) increases the linear operating region, whereas an increase in
2 KI0 I0 the W/L ratio causes the opposite effect (8).

Consequently the differential output voltage Vod is expressed Real Input Stage
by
r 2I Technological Constraints. Until now we have studied the
behavior of the ideal MOS amplifier. A real differential pair
0
Vod = Rd (Id2 − Id1 ) = −Rd KVid − (Vid )2 (12) presents some dc errors that produce basic limitations for
K
many analog systems.
This expression is valid as long as both transistors M1 and In dc and low frequencies, the threshold voltage Vth and
M2 are in the saturated mode which is proved by 兩Vid兩 Ⰶ the gain factor K represent the predominant sources of static
兹I0 /K. When this condition is satisfied, the gain A of the dif- errors in a source-coupled pair (3). The deviations in the
ferential amplifier is given by Vod /Vid ⫽ Rd 兹2I0K. threshold voltage and the gain factor are due to technological
parameters. The difference in Vth between two matched tran-
sistors results mainly from differences in oxide thickness and
bulk doping. Actually the oxide thickness in VLSI MOS pro-
+Vdd
cessing is so reproducible that it has only a negligible effect
on Vth. Consequently, changes in substrate doping are the
Rd2 Rd1 principal source of threshold voltage mismatch Vth which is
typically 10 mV to 25 mV. The gain factor includes two pa-
Vod rameters, the factor K⬘ ⫽ 1/2애Cox and the gate dimensions W
Vo1 Vo2
and L. The changes in mobility in K⬘ depend on deviations in
M1 M2 bulk doping. Deviations in W and L result from photolithogra-
phy variations. The latter variations represent the main
Vi1 Vi2 source of deviations in the gain factor. The differences be-
tween the load resistances, whose typical values depend on
I0 size, also contribute to the dc errors in the source-coupled
pair (3).
– Vss The effects of mismatches on dc performance in MOS am-
plifiers are represented only by the input offset voltage due to
Figure 7. The NMOS source-coupled pair using matched devices. high impedance of the gate of MOS transistors (6).
48 DC AMPLIFIERS

Input Offset Voltage. As mentioned earlier, the input offset R2

voltage Vos is the input voltage required to force the differen-
tial output voltage to zero. Summing voltages around the
source loop in Fig. 9 gives Vos

I
I R1
– +
–
Vos = Vth1 − Vth2 + d1
− d2
K1 K2 Vo
R3
To make the differential output Vod exactly zero requires that +
Rd1Id1 ⫽ Rd2Id2. Using the last expression, we find that (3)
I0S


Vgs − Vth Rd K
Vos = Vth + − − (13)
2 Rd K

where the difference quantities are given by ⌬Vth ⫽ Vth1 ⫺

Figure 10. Schematic form of the feedback implementation including
Vth2, ⌬Rd ⫽ Rd1 ⫺ Rd2, and ⌬K ⫽ K1 ⫺ K2, and the average offset generators.
quantities are given by

Vth1 + Vth2 R + Rd2 K1 + K2

Vth = , Rd = d1 , and K = GENERAL CRITERION FOR IMPLEMENTING DC AMPLIFIERS
2 2 2

The offset voltage in Eq. (13) consists of two parts. One equals
the threshold voltage mismatch and the other contains mis-
matches in load resistances and gate dimensions. Note that
Vos mismatch depends on differences and also on biasing
points. When the transistors are biased at small values of
(Vgs ⫺ Vth), the influence of ⌬Rd and ⌬K becomes smaller. Con-
sequently, at weak inversion the main factor influencing the
input offset voltage is ⌬Vth.
The main difference between bipolar and MOS differential
stages is the mismatch in the threshold voltage. For a MOS
stage, this results in a constant offset component that is inde-
pendent of bias current. Consequently the MOS differential
stage displays a higher offset voltage than the bipolar pair.
Offset Voltage Drift. The drift of the input offset voltage of
a MOS differential pair is given by ⌬Vos /⌬T (8). Contrary to
the bipolar case, the offset voltage drift in MOS stages is not
directly correlated with the offset voltage.
The temperature drift of the offset value depends on varia-
tions of Vth and K. The variation of Vth is as high as some mV/
⬚C. But the changes in K are considerably larger because K
includes mobility.
+Vdd
Rd2 Rd1
Vos Vod
Vo1 Vo2
Comparison Between Bipolar and MOS Stages
Generally bipolar input stage amplifiers have much better
long-term stability than MOS devices can offer. Very good
matching between the input transistors is obtained with bipo-
lar differential pairs. Indeed for bipolar transistors the trans-
conductance parameters do not depend on both the area of
the transistor and the technology. In contrast, for MOS differ-
ential stages the transconductance is strongly dependent on
the W/L ratio and the fabrication processes. As a result bipo-
lar stages exhibit lower offset voltage and temperature drift.
In addition for the same value of the bias current, they will
be smaller than MOS to have the same value for the transcon-
ductance. Nevertheless bipolar stages exhibit large input bias
currents. In contrast, MOS input stages take advantage of a
high input impedance resulting in low offset current and low
bias current. This makes them ideal for portable systems and
micropower applications.
Feedback Loop Effects
Figure 10 shows the circuit that can be used to calculate the
output offset voltage of an amplifier in its usual feedback con-
figuration. This is valid for both the inverting and nonin-
verting amplifier configurations, shown in Fig. 3. The value
of R3 is assumed to be (R1 //R2) and to cancel the effects of the
bias current Ib.
Calculation gives

R2

Vo = − 1 + Vos + R2 Ios (14)
R1

M1 M2 This reveals that the coefficient of Vos can be expressed di-

rectly in terms of the closed loop gain. Consequently the input
Vi1 Vi2 offset voltage becomes preponderant for low values of R2.

I0 GENERAL TECHNIQUES USED TO REDUCE

DC ERRORS IN AMPLIFIERS
–Vss
As shown previously, dc offset limits numerous applications
Figure 9. The NMOS source-coupled pair with the dc offset voltage in linear IC. For example, offset voltage is a particularly im-
source. portant parameter for precision instrumentation amplifiers
 DC AMPLIFIERS 49

+Vcc +Vcc +Vcc +Vcc

External
Zener diode
variable
resistor

...

...
VO Current
injection

Q1 Q2
VO
Vi

Q1 Q2
Vi

–Vee

Figure 11. Conventional method for canceling dc offset voltage using

a variable resistor to adjust the collector resistors ratio.
–Vee

Figure 12. Zener-zap trimming technique. Zener diodes are placed

and for applications where rail-to-rail output signal swing is
required. In these latter cases, the dc offset reduces the dy-
namic range, which is, in turn, very restrictive when design-
ing in low-voltage technology (CMOS). Several techniques,
however, can be used to compensate for this nonideal effect.
Two ways to proceed are addressed in this section. We have,
on the one hand, what we call ‘‘offset trimming techniques’’
and, on the other, improved circuit designs tending to elimi-
nate the dc offset.
Various Adjustment Possibilities
Because the input differential stage generates the dc offset, it
is exclusively on this stage that any corrections need to be
performed. The emitter-coupled pair (or source-coupled pair)
analyzed previously, is the most commonly used input stage.
One solution for canceling the offset is to adjust the collector
resistor ratio (which should be equal to one) with an external
(out of chip) variable resistor, as shown in Fig. 11. This vari-
able resistor is controlled by a potentiometer which adjusts
its value for canceling the dc offset voltage. Thus Vod ⫽ 0
when Vid ⫽ 0. The well-known operational amplifier 741 uses
this technique to eliminate the dc offset which is typically
about 2 mV without correction. The offset drift is about 70
애V/⬚C. Moreover, this resistor adjustment can also be realized
with a laser beam. This automated process is performed di-
rectly on the wafer, and the laser adjusts the resistor size
on the chip. This has the possible disadvantage of being an
irreversible process. The precision operational amplifier
OPA177 from Burr–Brown combines both of these methods:
laser-trimming offset and an optional connection to an exter-
nal potentiometer. Then the offset achieved is about 10 애V,
and the drift is only 0.3 애V/⬚C.
Another nulling technique consists of replacing each of the
two load resistors Rc with several resistors in series. Then
each resistor is in parallel with Zener diodes, as shown in Fig.
in parallel with load resistors, and must be shorted with a current
injection to adjust the offset voltage to zero.
12. Injecting a current pulse into the diode permanently
shorts its parallel resistor. In practice the series resistors
have different values for refining the adjustment. In the OP-
07A from Precision Monolithic Inc., this ‘‘Zener-zap trim-
ming‘‘ technique reduces the offset voltage to 10 애V and the
drift to 0.2 애V/⬚C (9).
We demonstrated previously that in the bipolar, emitter-
coupled pair, the dc offset voltage and drift are given by Eqs.
(7) and (9). Thus in theory, if we null Vos, then the drift is also
nulled. In practice, however, introducing the potentiometer
creates a new drift factor, which cannot be eliminated simul-
taneously (10).
In conclusion it is important to see in these offset trimming
techniques that adjusting the resistors is performed at a sin-
gle fixed temperature. In consequence, for applications over a
wide range of temperature, the drift will be important (11).
In the next part we see more ways to improve the perfor-
mance when designing specific circuits to correct dc errors.
Vos Ibias
– +
Vi1 +
Ios/2 Vo
Vi2 –
Ibias
Figure 13. An amplifier with dc offset sources; input offset voltage
(Vos), and input offset current (Ios).
50 DC AMPLIFIERS

Amplitude
+Vcc +Vcc +Vcc Clock
Φ1 Φ1

Time
Vi Vo

Vo

Ib3
Ib3 ≈ Ib2 Time
Q4 Q3

I≈ 0
Vi1 Q1 Q2
Ib2 Vi2

Figure 16. Input, output, and clock signals in a basic autozero am-
plifier. The discontinuities in output signal must be eliminated with
a low-pass filter.
–Vee

Figure 14. A method for canceling the input bias current in a bipolar
differential pair. The base current of Q3 is mirrored to the base of
Q2. It reduces considerably Ibias current and Ios current.
Circuits with Improved Design
Correcting the dc Offset Current and Input Bias Current. We
can represent an amplifier with different offset sources as
shown in Fig. 13. The advantage of the MOS differential pair,
compared with the similar bipolar input stage, is the very low
(about 100 pA) input bias current (Ibias). In addition, the MOS
differential pair results in very low input offset current (Ios),
about 10 pA. The isolated gate of the MOS allows this charac-
teristic. Nevertheless, this advantage practically disappears
when diodes are included to protect the gates from electro-
static discharges. In the case of the bipolar differential pair,
the values of Ibias and Ios are directly proportional to the base
currents of the transistors, as explained previously.
A method for canceling the input bias current is shown in
Fig. 14. The base currents of Q2 and Q3 are practically identi-
cal because the same current flows through their collectors.
Then the base current of Q3 is mirrored to the base of Q2. The
same applies for Q4 and Q1. As a result, the Ibias current is
nulled, and Ias is considerably reduced. For example, using
this method, the precision operational amplifier OPA177 from
Burr–Brown provides 0.5 nA for Ibias and 0.1 nA for Ios.
Correcting the dc Offset Voltage. In this section we address
a widely used method for designing low-offset voltage and
low-drift amplifiers. This technique, based on the ‘‘autozero’’
concept (AZ) (12), in addition, allows canceling low-frequency
noise (12,13). An AZ amplifier is shown in Fig. 15. This tech-
nique consists of sampling the dc offset of the amplifier and
subtracting it from the signal. The sample operations, more-
over, are performed with switched-capacitor circuits. This
brings us to the functioning of such a configuration. Two
phases are needed. In a first stage (⌽1), the switch shorts the
input, and the dc offset appears at the output. Then this
quantity is sampled, held by capacitor Cn, and applied at an
auxiliary nulling input (N), to eliminate it. In the second
stage (⌽1), the amplifier is ridded of the offset and is con-
nected back to the input signal for amplification. Figure 16
shows the input and output signals and the clock which
drives the nulling operations. It is easy to see that the output
V+ +
Main amp Vo
N
V– –
Φ1
C2

Φ2 Φ1
–

N Φ2
Φ1
+

C1

Figure 15. A basic autozero amplifier. The offset voltage is sampled,

held in capacitor Cn, and injected at a nulling input (N). This correc- Figure 17. Continuous time autozero amplifier using a main ampli-
tion is controlled by a clock (⌽). fier and a basic auto-zero amplifier.
 DC AMPLIFIERS 51

Table 1. Integrated Circuits Used for dc Applications and Main Characteristics at 25ⴗC
Input Offset Input Bias Input Offset
Designation Manufacturer Function Voltage Voltage Drift Current Current
LM741C National Semiconductor op amp 2 mV 80 nA 20 nA
OP07A PMI ultra low offset op amp 10 애V 0.2 애V/⬚C 0.7 nA 0.3 nA
AD708S Analog Devices ultra low offset op amp 5 애V 0.1 애V/⬚C 0.5 nA 0.1 nA
OPA177F Burr–Brown Precision op amp 10 애V 0.3 애V/⬚C 0.5 nA 0.1 nA
ICL7650 Maxim Chopper 0.7 애V 10 nV/⬚C 1.5 pA 0.5 pA
LTC1100ACN Linear Technology Chopper op amp 1 애V 5 nV/⬚C 2.5 pA 10 pA
TLC2652AM Texas Instrument Chopper op-amp 0.5 애V 3 nV/⬚C 4 pA 2 pA

signal displays discontinuities due to phase ⌽1. Hence it must
be low-pass filtered to reduce continuity of the signal. Note
that the clock frequency must have at least twice the signal
frequency to fulfill the Shannon criterion. Consequently this
reduces the application of autozero amplifiers to the low-fre-
quency domain.
Nevertheless, some applications require continuous time
amplification. In these cases the amplifier should not be dis-
connected from the input signal. An improved schema is pro-
posed in Fig. 17: the ‘‘continuous time AZ amplifier’’ or ‘‘chop-
per amplifier.’’ Generally designed with MOS transistors,
such amplifiers incorporate two amplifiers internally, a main
amplifier and an AZ amplifier. Two phases are needed to de-
scribe the operation. During the first phase (⌽1), the AZ amp
corrects its own offset, as addressed previously. Then, during
the second phase (⌽2), the offset-free AZ amplifier senses the
main amplifier’s offset, stores this value in capacitor C2, and
applies it at the nulling input of the main amplifier. Because
the offset is constantly corrected even during temperature
variations, chopper amplifiers feature very good performance.
For instance, the LTC110 precision chopper instrumentation
amplifier from Linear Technology reduces the offset voltage
to typically 1 애V and the drift to 5 nV/⬚C. Therefore such
amplifiers are very useful for precision applications. Table 1
lists the main dc characteristics at 300 K of different amplifi-
ers used for dc operation (9,14–16).
OTHER AVAILABLE IMPLEMENTATIONS
Dc amplifiers can also be designed from basic building blocks
other than operational amplifiers. Various possible implemen-
tations and their particularities are addressed in this section.
Their typical dc input errors are listed in Fig. 18. This figure
also displays the errors of classical IC amplifiers.

1,00E-01
High-speed bipolar
EL2211
1,00E-02 Current feedback O.A

FET / CMOS LT1206

AD509
EL2166C
Input offset voltage, Vos (V)

AD549
1,00E-03 EL2165C EL2165C
TLC2272 Bipolar O.A
AD820

TLC2252 Inst O.A TLE2021 AD829

1,00E-04 AD795 OPA627
INA2128
OPA77

Chopper INA101SM
1,00E-05 OPA177
TLC2654C

1,00E-06
TLC2654C

1,00E-07
1,00E-14 1,00E-13 1,00E-12 1,00E-11 1,00E-10 1,00E-09 1,00E-08 1,00E-07 1,00E-06 1,00E-05 1,00E-04
Input bias current, Ib (A)

Figure 18. Typical voltage and current offsets for various IC amplifier families.
52 DC AMPLIFIERS

Vi1 +
R2
A2

–
RB R1
–

RA A1 Vo
+
RB R1
R2
–
A2

Vi2 +

Figure 19. Instrumentation amplifier.

Instrumentation Amplifiers tions are realized as shown in Fig. 3. But in that case the
output voltage is given by
Such integrated amplifiers incorporate three operational am-
plifiers in a single chip (1,7). Matched resistors obtained with
Vo = −ZT × i− (17)
laser trimming are also included to cancel typical dc errors.
The resulting circuit is shown in Fig. 19. A1 is connected as a
with ZT ⫽ RT储CT which is the output impedance at port Z of
difference amplifier. A2 and A⬘2 are in a noninverting configu-
the CCII. The CFOA exhibits higher bandwidths than classi-
ration. Thus the output voltage is given by
cal operational amplifiers. Indeed the bandwidths are propor-
R2

2RB
 tional to 1/R2CT (R2 is the feedback resistor in Fig. 3). The
Vo = (Vi1 − Vi2 ) 1+ (15) slew rate is also greatly increased (about 1000 V/애s). Never-
R1 RA
theless, dc errors are particularly prevalent in CFOA designs.
So, the amplifier gain can be easily adjusted with RA con- The dissymmetries between the inputs imply that their bias
nected out of chip. currents do not match or cancel.

Current Feedback Operational Amplifiers High-Speed Operational Amplifiers

In current feedback operational amplifiers (CFOA) also called
transimpedance op-amps, the input cell is different from that
used in voltage-feedback op-amps (VFOA) (see Figs. 4 and 7)
(17). This cell is basically a second-generation current con-
veyor (CCII) as shown in Fig. 20, which is commonly de-
The input stage of high-speed operational amplifiers is gener-
ally identical to the one of classical op-amps. Their output is
nevertheless constituted from the difference between two out-
put currents. This improves the speed and bandwidth to the
detriment of input errors.

iy 
0 
vy
scribed by the following matrix relation:

0 0
vx = 1 0 0 × ix (16)
iz 0 1 0 vz
+
+
Figure 21 represents the equivalent electrical circuit for a I =o
CFOA (17–21). The inverting and noninverting configura- 1

1 Vo
Rx
Y 1 Z ZT
I– = ix –
ix
Rx Ix Rz
Ix
X

Figure 20. Equivalent macromodel of the second generation cur- Figure 21. Current feedback operational amplifier obtained from a
rent conveyor. second generation current conveyor and a voltage follower.
 DC–DC POWER CONVERTERS 53

CONCLUDING REMARKS AND PROSPECTIVE DEVELOPMENTS
In this article we have inspected the mismatches and drift
effects on the performance of dc amplifiers implemented from
op-amps. Bipolar and MOS differential inputs stages have
successively been analyzed. NPN and NMOS transistors have
only been considered above. Nevertheless differential ampli-
fiers can also be implemented from PNP or PMOS elements.
In these cases note that PNP transistors exhibit lower 웁 val-
ues and the mobility of PMOS transistors is about three
times smaller.
The general criterion to consider for implementing dc am-
plifiers and the most commonly used techniques to reduce dc
errors have been investigated.
As indicated, dc amplifiers can also be designed from other
available building blocks: Traditionally all these dc amplifier
implementations use voltage input signals. Rushing into the
opening created by the introduction of the CFOA, another de-
sign approach could consist in using current input signals in
place of voltages.
Second-generation current conveyors can be driven from
current signals and these could certainly be used advanta-
geously in designing dc amplifiers.
16. D. Soderquist, The OP-07 ultra low offset voltage op amp; A bipo-
lar op amp that challenges choppers, eliminates nulling, applica-
tion note 13 in Precision Monolithics Inc. Linear and Conversion
Applications Handbook, 1986.
17. C. Toumazou, F. J. Lidgey, and D. G. Haigh, Analog IC Design:
The Current Mode Approach, London: Peter Peregrinus, 1990.
18. A. Fabre, O. Saaid, and H. Barthelemy, On the frequency limita-
tions of the circuits based on 2nd generation current conveyors,
Analog Integrated Circuits Signal Process., 7: 113–129, 1995.
19. A. Fabre, Gyrator implementation from commercially available
transimpedance operational amplifiers, Electron. Lett., 28: 263–
264, 1992.
20. A. D. Wang, The Current-feedback op amp, a high-speed building
block, in Applications Handbook, Tucson, AZ: Burr–Brown, 1994.
21. B. Harvey, Current feedback op-amp limitations: a state of the
art review, Conf. Proc. Int. Symp. Circuits Syst., 1993.
ALAIN FABRE
FABRICE SEGUIN
HOUNAIDA ZOUAOUI ABOUDA
Université de Bordeaux I
HERVE BARTHELEMY
Institut Supérieur d’Electronique de
la Méditerranée

BIBLIOGRAPHY
DC CONVERTERS. See HVDC POWER CONVERTERS.
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York: Oxford Univ. Press, 1998.
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3. R. Laker and W. M. C. Sansen, Design of Analog Integrated Cir-
cuits and Systems, New York: McGraw-Hill, 1994.
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LP digital, IEEE Int. Symp. Circuits Syst., Hong-Kong, 1996–
1999.
5. S. Kimura, Y. Imai, and Y. Miyamoto, Direct-coupled distributed
baseband amplifier ICs for 40-Gb/s optical communication, IEEE
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erationnels, 2nd ed., Arcueil, France: Thomson-CSF, Tome 1,
1974.
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Hill, 1988.
8. P. R. Gray and R. G. Meyer, Analog Integrated Circuits, 2nd ed.,
New York: Wiley, 1984.
9. D. A. Johns and K. Martin, Analog Integrated Circuit Design, New
York: Wiley, 1997.
10. Anonymous, Low Drift Amplifiers, National Semiconductor, Lin-
ear Brief 22, June 1973.
11. Robert J. Widlar, Reducing DC Errors in Op-Amp, Santa Clara,
CA: National Semiconductor, Technical Paper 15, December
1980.
12. C. C. Enz and G. C. Temes, Circuit techniques for reducing the
effects of op-amp imperfections: Autozeroing, double sampling,
and chopper stabilisation, Proc. IEEE 84: 1584–1614, 1996.
13. G. Erdi, Chopper versus bipolar op amps; an unbiased compari-
son, design notes n⬚ 42 in Application Handbook, 1993, volume
II, Milpitas, CA: Linear Technology, 1993.
14. Analog Devices, Linear Product Data Book, Norwood, MA, 1990.
15. Analog Devices, Amplifier Applications Guide, Norwood, MA,
1992.

DATA ACQUISITION AND CONVERSION
Data acquisition and conversion pertain to the generation of
signals from sensors, their conditioning, and their conversion
into a digital format. In this article we describe typical sen-
sors that generate signals and examples of data converter to-
pologies suitable for sensor interfaces. We restrict ourselves
to integrated implementations of sensors and sensor interface
circuits. In particular, we target sensors and sensor interfaces
that are compatible with CMOS fabrication technologies.
This article is organized as follows. First, we describe some
examples of sensors and sensor interfaces; then we describe
some sample data converter topologies. After that, we provide
two complete design examples.
SENSORS
Sensors are devices that respond to a physical or chemical
stimulus and generate an output that can be used as a mea-
sure of the stimulus. The sensed inputs can be of many types:
chemical, mechanical, electrical, magnetic, thermal, and so
on. The input signal sensed by the sensor is then processed
(amplified, converted from analog to digital, etc.) by some sig-
nal conditioning electronics, and the output transducer con-
verts this processed signal into the appropriate output form.
The primary purpose of interface electronics is to convert the
sensor’s signal into a format that is more compatible with the
electronic system that controls the sensing system. The elec-
tric signals generated by sensors are usually small in ampli-
tude. In addition to this, sensors often exhibit errors, such as
offsets, drift, and nonlinearities, that can be compensated for
with the correct interface circuitry. Analog elements have
been improved substantially to achieve high speed and high
accuracy; however, for many applications digital is still the
preferred format. The sensors yield a wide variety of electric
output signals: voltages, currents, resistances, and capaci-
tances. The signal conditioning circuitry modifies the input
signal into a format suitable for the follow-on data converter.
Figure 1 shows the system architecture for a sensor–
actuator-based control system. The sensor(s) senses the exter-
nal physical and chemical parameters and converts them into
an electrical format. The sensed data are processed and digi-
tized using integrated circuitry and transmitted to the host
controller. The host uses this information to make the appro-
priate decisions, and information is fed back to the external
environment through a set of actuators (1). These micropro-
cessor-based controllers have revolutionized the design and
use of instrumentation systems by allowing system operation
to be defined in software, thus permitting a substantial in-
crease in signal-processing and user-interface features. In
general, a power supply is also connected to these blocks but
is not explicitly shown in Fig. 1. If a sensor can provide a
signal without a power supply, it is referred to as a self-gener-
ating sensor.
493
J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.
Integrated sensors are used in many applications, includ-
ing automotive, manufacturing, environmental monitoring,
avionics, and defense. In the past few years, integrated sen-
sors that monolithically combine the sensor structure and
some signal-processing interface electronics on the same sub-
strate have begun to emerge. By combining microsensors and
circuits, integrated smart sensors increase accuracy, dynamic
range, and reliability and at the same time reduce size and
cost. Some examples of semiconductor sensors are pressure
sensors used in pneumatic systems, magnetic sensors used
in position control, temperature sensors used in automotive
systems, chemical sensors used in biological diagnostic sys-
tems, and acoustic emission sensors used in structural diag-
nostics.
In the next two sections we illustrate the use of sensors
and sensor interfaces with the two most common types of sen-
sors: resistive and capacitive sensors. We then describe two
complete sensor systems that include an acoustic emission
sensor and a temperature sensor.
Resistive Sensors
Sensors based on the variation of electric resistance are called
resistive sensors. They can be further classified according to
the physical quantity that they measure: thermal, magnetic,
optical, and so on.
A potentiometer is a simple resistance measurement device
in which the resistance is proportional to its length. However,
the linearity of a potentiometer is limited because its resis-
tance is not perfectly uniform. The resistance value also drifts
with temperature. Applications of potentiometers are in the
measurement of linear or rotary displacements.
Another simple and commonly used resistive sensor is the
strain gauge, which is based on the variation of the resistance
of a conductor or semiconductor when subjected to a mechani-
cal stress. The variation in the resistance of a metal is given
(2) by
R = R0 (1 + G
) (1)
where R0 is the resistance when there is no applied stress, G
is the gauge factor, and ⑀ is the strain. There are a number of
limitations on strain gauges, such as temperature depen-
dence, light dependence, and inaccuracies in the measure-
ment of a nonuniform surface; but in spite of these limita-
tions, they are among the most popular sensors because of
their small size and linearity.
Some of the applications of the strain gauge are in measur-
ing force, torque, flow, acceleration, and pressure. Figure 2
shows a micromachined piezoresistive cantilever beam used
as a strain gauge sensor. Strain gauges are capable of de-
tecting deformations as small as 10 애m or lower.
A resistance temperature detector (RTD) is a temperature
detector based on the variation in electric resistance. An in-
crease in temperature increases the vibrations of atoms
around their equilibrium positions, and this increases the re-
sistance in a metal: Thus there is a positive temperature coef-
ficient of resistance. The complete temperature dependence
494 DATA ACQUISITION AND CONVERSION
Control parameters Sensed parameters
Actuators Sensors
Driver Amp
DAC ADC
Microcomputer control
Higher-level control
Figure 1. Overall system architecture of a sensor–actuator control
system.
can be expressed (2) as
R = R0 (1 + α1 T + α2 T 2 + · · · + αn T n ) (2)
where T is the temperature difference from the reference and
R0 is the resistance at the reference temperature.
The main advantages of these sensors are their high sensi-
tivity, repeatability, and low cost. There are some limitations
too. Firstly, to avoid destruction through self-heating, the
RTD cannot measure temperatures near the melting point of
the metal. Secondly, the change in temperature may cause
physical deformations in the sensor. Additionally, for each
metal there is only a small range over which the RTD is lin-
ear. The most common metals used for RTDs are platinum,
nickel, and copper.
Thermistors are also temperature-dependent resistors but
are made of semiconductors rather than metals. The tempera-
ture dependence of the resistance of a semiconductor is due to
the variation in the available charge carriers. Semiconductors
have a negative temperature coefficient, as the resistance is
inversely proportional to the number of charge carriers. The
Figure 2. Micromachined piezoresistive cantilever beam used as a
strain gauge sensor.
temperature dependence of thermistors is given (2) by



1 1
RT = R0 exp B − (3)
T T0
where T0 is the reference temperature, R0 is the resistance at
T0, and B is the characteristic temperature of the material,
which itself is temperature-dependent. The limitations and
advantages of a thermistor are similar to those of a RTD, ex-
cept that the thermistor is less stable. There are many types
of thermistors available, and each type has its own applica-
tions. The foil and bead types are suitable for temperature
measurement, whereas the disk and rod types are suitable for
temperature control. Some of the applications of thermistors
are in the measurement of temperature, flow, level, and time
delay. Two simple applications of thermistors are discussed
below.
Light-dependent resistors, or LDRs, are devices whose re-
sistance varies as a function of the illumination. LDRs are
also known as photoconductors. The conductivity is primarily
dependent on the number of carriers in the conduction band
of the semiconductor material used. The basic working of the
photoconductor is as follows. The valence and conduction
bands in a semiconductor are quite close to each other. With
increased illumination, electrons are excited from the valence
to the conduction band, which increases the conductivity (re-
duces the resistance). The relation between resistance and op-
tical radiation or illumination is given (2) by
R = AE −α (4)
where A and 움 are process constants, R is the resistance, and
E is the illumination.
An important limitation of LDRs is their nonlinearity.
Also, their sensitivity is limited by fluctuations caused by
changes in temperature. Finally, the spectral response of
LDRs is very narrow and primarily depends on the type of
material used.
Some of the most common LDRs are made of PbS, CdS,
and PbSe. Some applications of LDRs are shutter control in
cameras and contrast and brightness control in television re-
ceivers.
Measurement Techniques for Resistive Sensors. Various mea-
surement techniques can be used with resistive sensors. The
basic requirement for any measurement circuitry is a power
supply to convert the change in resistance into a measurable
output signal. In addition, it is often necessary to custom-
build interface circuits for some sensors. For example, we may
be required to add a linearization circuit for thermistors.
Resistance measurements can be made by either the de-
flection method or the nulling method. In the deflection
method the actual current through the resistance or the volt-
age across the resistance is measured. In the nulling method
a bridge is used.
The two-readings method is a fundamental approach to re-
sistance measurement. A known resistance is placed in series
with the unknown resistance as shown in Fig. 3. The voltage
is then measured across each of them. The two voltages can
 DATA ACQUISITION AND CONVERSION 495

θ1
RK VK CS CI
Vref p
V θ1
θ2
–
Cref + ADC
CI
RU VU
Vref n
θ1
θ2

Figure 3. Two-readings method for resistance measurement. Figure 5. Capacitive sensor interface.

be written as The Wheatstone bridge can also be used for deflection mea-
surement. In this case, instead of measuring the change
V needed to balance the bridge, the voltage difference between
VK = R (5)
RK + RU K the bridge outputs is measured or the current through the
center arm is measured. This method is shown in Fig. 4.
V
VU = R (6) When the bridge is completely balanced (i.e., x ⫽ 0), k is de-
RK + RU U fined as follows:

where V is the supply voltage, VK and RK are the known volt- R1 R

age and resistance, and VU and RU are the unknown voltage
and resistance. Thus from the above equations RU can be writ-
ten as follows:
VU
RU = RK
VK
A similar method is the voltage divider, in which the un-
known resistance is once again calculated from known volt-
ages and resistances. It is easier to resolve small voltage
changes for low voltages than it is for high voltages. Thus to
measure small changes in resistance, another voltage divider
is placed in parallel to the one with the sensor. The parallel
voltage dividers are designed to give the same voltage for no
input. Thus the signal obtained by taking the difference be-
tween their output signals is totally dependent on the mea-
sured signal. This method of measuring small changes using
parallel voltage dividers is called the Wheatstone bridge
method (2–5). A simple Wheatstone bridge measurement
method is shown in Fig. 4.
The Wheatstone bridge is balanced with the help of a feed-
back system, which adjusts the value of the standard resistor
until the current through the galvanometer is zero. Once this
is done, the value for R3 is given by
R2
R3 = R4
R1
Thus the resistance R3 is directly proportional to the change
required in R4 in order to balance the circuit.
R1 R2
V
G many applications CS0 can be 5 to 10 times larger than the
R4 R3 = R0(1+x)
Figure 4. Simple Wheatstone bridge measurement method.
k= = 2 (9)
R4 R0
Thus the voltage difference between the outputs can be writ-
ten as follows.
(7)
R3 R4
 kx
V0 = V − =V (10)
R2 + R3 R1 + R4 (k + 1)(k + 1 + x)
The maximum sensitivity for very small changes in x is ob-
tained when k ⫽ 1.
Capacitive Sensors
Recently capacitive sensor have gained popularity. They gen-
erally exhibit lower temperature sensitivity, consume less
power, and provide an overall higher sensor sensitivity with
higher resolution than resistive sensors. For these reasons
they have begun to show up in areas where resistive sensors
were the norm. They are used in many applications such as
pressure sensors and accelerometers. Capacitive sensors typi-
cally have one fixed plate and one moving plate that responds
to the applied measurand. The capacitance between two
plates separated by a distance d is given by C ⫽ ⑀A/d, where
⑀ is the dielectric constant and A is the area of the plate. It is
easily seen that the capacitance is inversely proportional to
(8) the distance d.
For capacitive sensors there are several possible interface
schemes. Figure 5 shows one of the most common capacitive
sensor interfaces. The circuit is simply a charge amplifier,
which transfers the difference of the charges on the sensor
capacitor CS and the reference capacitor Cref to the integration
capacitor CI. If this interface is used in a pressure sensor, the
sensing capacitor CS can be written as the sum of the sensor
capacitor value CS0 at zero pressure and the sensor capacitor
variation ⌬CS(p) with applied pressure: CS ⫽ CS0 ⫹ ⌬CS(p). In
full-scale sensor capacitance variation ⌬CS(p)max; the reference
capacitor Cref is used to subtract the nominal value of the sen-
sor capacitor at half the pressure range, which is Cref ⫽
CS0 ⫹ ⌬CS(p)max /2. This ensures that the transferred charge is
496 DATA ACQUISITION AND CONVERSION
the charge that results from the change in the capacitance.
This results in a smaller integration capacitor and increased
sensitivity.
This type of capacitive interface is insensitive to the para-
sitic capacitance between the positive and negative terminals
of the opamp, since the opamp maintains a virtual ground
across the two terminals of the parasitic capacitor. This type
of interface is also much faster than most other capacitive
interfaces; its speed of operation is determined by the opamp’s
settling time. This technique also allows for the amplifier’s
offset and flicker noise to be removed very easily by using
correlated double sampling or chopper stabilization. The reso-
lution of this interface is in most cases limited by kT/C noise
and charge injection due to the switches.
There are a number of other sensor types, and two more
will be discussed later in this article. However, we first de-
scribe the most common data converters that are used as part
of sensor interfaces.
DATA CONVERTERS
The analog signals generated and then conditioned by the sig-
nal conditioning circuit are usually converted into digital
form via an analog-to-digital converter (ADC). In general,
most of the signals generated by these sensors are in the low
frequency region. For this reason, certain data converter to-
pologies are particularly well suited as sensor interface sub-
blocks. These include the charge redistribution implementa-
tion of the successive approximation converter, along with
incremental and sigma–delta converters (6). In the following
subsections we shall briefly describe successive approxima-
tion (incremental) and sigma–delta converters. Incremental
and sigma–delta converters are very similar and the details
of the former are later described extensively as part of a sam-
ple system design.
Successive-Approximation Converter
A block diagram for the successive approximation converter
is shown in Fig. 6. The successive approximation topology re-
quires N clock cycles to perform an N bit conversion. For this
reason, a sample-and-held (S/H) version of the input signal is
provided to the negative input of the comparator. The compa-
rator controls the digital logic circuit that performs the binary
search. This logic circuit is called the successive approxima-
tion register (SAR). The output of the SAR is used to drive
the digital-to-analog converter (DAC) that is connected to the
positive input of the comparator.
Vin S/H –
Successive approximation
Control
register
+
DAC
N bit output
Figure 6. Successive approximation converter: block diagram.
During the first clock period the input is compared with
the most significant bit (MSB). For this, the MSB is temporar-
ily raised high. If the output of the comparator remains high,
then the input lies somewhere between zero and Vref /2 and
the MSB is reset to zero. However, if the comparator output
is low, then the input signal is somewhere between Vref /2 and
Vref and the MSB is set high. During the next clock period the
MSB-1 bit is evaluated in the same manner. This procedure
is repeated so that at the end of N clock periods all N bits
have been resolved.
The charge-redistribution implementation of the succes-
sive approximation methodology is the most common topology
in metal–oxide–semiconductor (MOS) technologies (7). The
circuit diagram for a 4 bit charge redistribution converter is
shown in Fig. 7. In this circuit the binary weighted capacitors
兵C, C/2, . . ., C/8其 and the switches 兵S1, S2, . . ., S5其 form the
4 bit scaling DAC. For each conversion the circuit operates as
a sequence of three phases. During the first phase (sample),
switch S0 is closed and all the other switches S1, S2, . . ., S6
are connected so that the input voltage Vin is sampled onto all
the capacitors. During the next phase (hold), S0 is open and
the bottom plates of all the capacitors are connected to
ground, i.e., switches S1, S2, . . ., S5 are switched to ground.
The voltage Vx at the top plate of the capacitors at this time
is equal to ⫺Vin, and the total charge in all the capacitors is
equal to ⫺2CVin. The final phase (redistribution) begins by
testing the input voltage against the MSB. This is accom-
plished by keeping the switches S2, S3, . . ., S5 connected to
ground and switching S1 and S6 so that the bottom plate of
the largest capacitor is connected to Vref . The voltage at the
top plate of the capacitor is equal to
Vref
Vx = − Vin (11)
2
If Vx ⬎ 0, then the comparator output goes high, signifying
that Vin ⬍ Vref /2, and switch S1 is switched back to ground. If
the comparator output is low, then Vin ⬎ Vref /2, and S1 is left
connected to Vref and the MSB is set high. In a similar fashion
the next bit, MSB-1, is evaluated. This procedure is continued
until all N bits have been resolved. After the conversion pro-
cess the voltage at the top plate is such that

Vref V V V

Vx = −Vin + b3 + b2 ref + b1 ref + b0 ref (12a)
21 22 23 24
V
− ref < Vx < 0 (12b)
24
where bi is 0 or 1 depending on whether bit i was set to zero
or one, and LSB is the least significant bit.
One of the advantages of the charge-redistribution topol-
ogy is that the parasitic capacitance from the switches has
little effect on its accuracy. Additionally, the clock feed-
through from switch S0 only causes an offset, and those from
switches S1, S2, . . ., S5 are independent of the input signal
because the switches are always connected to either ground
or Vref . However, any mismatch in the binary ratios of the
capacitors in the array causes nonlinearity, which limits the
accuracy to 10 or 12 bits. Self-calibrating (8) techniques have
been introduced that correct for errors in the binary ratios of
the capacitors in charge redistribution topologies. However,
these techniques are fairly complex, and for higher resolu-

S0
C C C C
2 4 8 8
S1 S2 S3 S4
Vin
Vref S6
tions sigma–delta converters are the preferred topology. We
now briefly describe sigma–delta converters.
Sigma–Delta Data Converters
Oversampling converters sample the input at a rate larger
than the Nyquist frequency. If f S is the sampling rate, then
f S /2f 0 ⫽ OSR is called the oversampling ratio. Oversampling
converters have the advantage over Nyquist rate converters
that they do not require very tight tolerances from the analog
components and that they simplify the design of the antialias
filter. Sigma–delta converters (9) are oversampling single-bit
converters that use frequency shaping of the quantization
noise to increase resolution without increasing the matching
requirements for the analog components.
Figure 8 shows a block diagram for a general noise-shap-
ing oversampled converter. In a sigma–delta converter both
the ADC and DAC shown in Fig. 8 are single-bit versions and
as such provide perfect linearity. The ADC, a comparator in
the case of a sigma–delta converter, quantizes the output of
the loop filter, H1. The quantization process approximates an
analog value by a finite-resolution digital value. This step in-
troduces a quantization error Qn. Further, if we assume that
the quantization noise is not correlated to the input, then the
system can be modeled as a linear system. The output voltage
for this system can now be written as
Qn V H
V0 = + in 1
1 + H1 1 + H1
For most sigma–delta converters H1 has the characteristics of
a low-pass filter and is usually implemented as a switched-
capacitor integrator. For a first-order sigma–delta converter
H1 is realized as a simple switched-capacitor integrator, H1 ⫽
z⫺1 /(1 ⫺ z⫺1). Making this substitution in Eq. (13), we can
write the transfer function for the first-order sigma–delta
converter as
V0 = Vin z−1 + Qn (1 − z−1 )
+ style (10) modulator discussed above are required for filter
Vin Σ H1 ADC
– problem include the MASH and interpolative topologies (6).
DAC
Figure 8. Figure for a general noise-shaping oversampled converter.
DATA ACQUISITION AND CONVERSION 497
+
C –
S5
Figure 7. Charge-redistribution implementation of
the successive approximation architecture.
As can be seen from Eq. (16) below, the output is a delayed
version of the input plus the quantization noise multiplied by
the factor 1 ⫺ z⫺1. This function has a high-pass characteristic
with the result that the quantization noise is reduced sub-
stantially at lower frequencies and increases slightly at
higher frequencies. The analog modulator shown in Fig. 8 is
followed by a low-pass filter in the digital domain that re-
moves the out-of-band quantization noise. Thus we are left
with only the in-band (0 ⬍ f ⬍ f 0) quantization noise. For
simplicity the quantization noise is usually assumed to be
white with a spectral density equal to erms兹2/f s. Further, if
the OSR is sufficiently large, then we can approximate the
root-mean-square (rms) noise in the signal band by
π

2 f 3/2
N f ≈ erms 0
(15)
0 3 fs
As the oversampling ratio increases, the quantization noise
in the signal band decreases; for a doubling of the oversam-
pling ratio the quantization noise drops by 20(log 2)3/2 앒 9 dB.
Therefore, for each doubling of the oversampling ratio we ef-
fectively increase the resolution of the converter by an addi-
tional 1.5 bits.
Clearly, H1 can be replaced by other, higher-order func-
tions that have low-pass characteristics. For example, in Fig.
9 we show a second-order modulator. This modulator uses one
forward delay integrator and one feedback delay integrator to
(13) avoid stability problems. The output voltage for this figure
can be written as
V0 = Vin z−1 + Qn (1 − z−1 )2 (16)
The quantization noise is shaped by a second-order difference
equation. This serves to further reduce the quantization noise
at low frequencies, with the result that the noise power in
the signal bandwidth falls by 15 dB for every doubling of the
oversampling ratio. Alternatively, the resolution increases by
(14) 2.5 bits for every doubling of the oversampling ratio. In gen-
eral, increasing the order of the filter will reduce the neces-
sary oversampling ratio for a given resolution. However, for
stability reasons, topologies other than the simple Candy-
V0
orders greater than two. Topologies that avoid this stability
For low-frequency inputs, the white noise assumption for
the quantization noise breaks down. This results in tones
which reduce the effective resolution of lower-order sigma–
delta converters. Incremental converters utilize this observa-
498 DATA ACQUISITION AND CONVERSION
+
Vin Σ +
–
Figure 9. Modulator for second-order
oversampled converter.
tion to simplify the low-pass filter that follows the sigma–
delta converter. Details for the incremental converter are dis-
cussed below.
We now consider two system design examples. The first is
an acoustic emission sensor system and the second is a tem-
perature measurement system.
SYSTEM DESIGNS EXAMPLES
We illustrate the sensor and sensor interface scenario with
two examples. The first uses a piezoelectric acoustic emission
sensor interfaced with a charge amplifier and a data con-
verter. The second describes an integrated temperature
sensor.
Acoustic Emission Sensing System
Acoustic emission sensors are microsensors that are used for
the detection of acoustic signals. These devices use elastic
acoustic waves at high frequencies to measure physical,
chemical, and biological quantities. Typically, integrated
acoustic sensors can be made to be extremely sensitive and
also to have a large dynamic range. The output of these sen-
sors is usually a frequency, a charge, or a voltage.
The piezoelectric effect is one of the most convenient ways
to couple elastic waves to electrical circuits. Piezoelectricity is
caused by the electric polarization produced by mechanical
strain in certain crystals. Conversely, an electric polarization
will induce a mechanical strain in piezoelectric crystals. As a
consequence, when a voltage is applied to the electrodes of a
piezoelectric film, it elongates or contracts depending on the
polarity of the field. Conversely, when a mechanical force is
applied to the film, a voltage develops across the film. Some
properties of a good piezoelectric film are wide frequency
range, high elastic compliance, high output voltage, high sta-
bility in wet and chemical environments, high dielectric
strength, low acoustic impedance, and low fabrication costs.
Piezoelectric materials are anisotropic, and hence their elec-
trical and mechanical properties depend on the axis of the
applied electric force. The choice of the piezoelectric material
depends on the application.
TSM SAW FPW APM
Top Top
;
;;
Side Side
Top
;
Side
Bottom
End
Side
Figure 10. Types of acoustic wave sensors.
Qn
+ + z–1 + V0
z–1
Crystalline quartz (SiO2) is a natural piezoelectric sub-
stance. Some other commonly used piezoelectric materials are
ferroelectric single-crystal lithium niobate (LiNbO3) and thin
films of ZnO and lead zirconium titanate (PZT). Recently, ad-
vances have been made in sensor technology with ultrasonic
sensor configurations such as the surface acoustic wave
(SAW) and acoustic plate mode (APM). In SAW devices the
acoustic waves travel on the solid surface, and in an APM
arrangement they bounce off at an acute angle between the
bounding planes of a plate. The main types of acoustic wave
sensors are shown in Fig. 10 (11).
Piezoelectric thin films are particularly well suited for mi-
crosensor applications that require high reliability and supe-
rior performance. When prepared under optimal conditions
piezoelectric thin films have a dense microstructure without
cracks and holes, good adherence, and good electrical proper-
ties. The three most popular materials used for thin films in-
clude ZnO (zinc oxide), AlN (Aluminum nitride), and PZT
(lead zirconium titalate). Deposition, sputtering, and sol–gel
are some of the methods used for preparing piezo films; the
choice depends on the material and substrate used. ZnO thin
films are prepared using laser-assisted evaporation and are
often doped with lithium. Such films have excellent orienta-
tion. AlN thin films maintain a high acoustic velocity and are
able to withstand extremely high temperatures. PZT thin
films have a much higher piezoelectric coefficient than ZnO
and AlN.
Recently, it has become possible to generate piezoelectric
thin films with extremely good properties through the sol–gel
process. This process consists of the following steps: synthesis
of a metal–organic solution, deposition of this solution by spin
coating, and a final heating that helps to crystallize the ce-
ramic film. A cross-sectional view of a thin film PZT sensor is
shown in Fig. 11. The advantages of thin film PZT sensors
include their small size, which allows them to be positioned
virtually anywhere, and their ability to operate at high fre-
quencies.
Measurement Techniques. The different modes of use for an
acoustic sensor are summarized in Fig. 12. Using either a res-
onator-transducer or a delay line, measurements can be made
Gold
PZT
Ti/Pt electrode
Poly
Nitride
Si
Figure 11. Cross-sectional view of a thin film PZT sensor.

Elastic wave propagation
Delay line Transducer
Passive Active Active Passive
device device device device
Measure Measure
phase Measure oscillation
f, Q, Zin
shift frequency
Figure 12. Different measurement techniques for acoustic sensors.
on the device itself or incorporated into an oscillator circuit.
There are basically two ways to implement this measurement
technique: active or passive. In the case of passive bulk-wave
resonators, we measure the resonant frequency to infer the
wavelength and hence the velocity. Likewise, for passive de-
lay lines the phase shift between the input and the output of
the transducer, which are separated by a known distance,
yields the velocity. On the other hand, for active resonators
or delay-line oscillators, the frequency can be directly mea-
sured with the help of a digital counter.
As an example, let us consider the complete design and
implementation of an integrated acoustic emission sensor
with low-power signal-conditioning circuitry for the detection
of cracks and unusual wear in aircraft and submarines.
Within a health and usage monitoring system, it is necessary
by some means, either directly or indirectly, to monitor the
condition of critical components, e.g., airframe, gearboxes,
and turbine blades. The overall aim is to replace the current
practice of planned maintenance with a regime of required
maintenance. Typical parameters used include stress (or
strain), pressure, torque, temperature, vibration, and crack
detection. In this example, acoustic emission sensors are used
for crack detection. The thin film piezoelectric sensor, coupled
to an aircraft component, senses the outgoing ultrasonic
waves from any acoustic emission event as shown in Fig. 13.
The magnitude of the output signal is proportional to the
magnitude of the acoustic emission event. For our example
design, the acoustic emission signal bandwidth varies from 50
kHz to approximately 1 MHz. Mixed in with the desired
acoustic emission signal is vibration noise due to fretting of
the mechanical parts. However, this noise is limited to about
100 kHz and is easily filtered out.
Due to the acoustic emission event, the piezoelectric sensor
generates a charge on the top and bottom plates of the sensor.
Ti–Pt
Output charge
or voltage 0.3 µ m to 1 µm PZT
TiO2–Ti–Pt
Si3N4
Si
Package
wear plate
Outgoing
ultrasonic waves
Acoustic emission event
Figure 13. Acoustic emission sensor.
DATA ACQUISITION AND CONVERSION 499
R2
R1
Vin –
V0
+
Figure 14. Voltage amplifier.
There are two basic methods of interfacing to this sensor. We
can use either a voltage amplifier (Fig. 14) or a charge ampli-
fier (Fig. 15).
In general, the charge amplifier interface provides a num-
ber of advantages. First, it is not affected by parasitic capaci-
tances at the input of the amplifier. Second, the output volt-
age at the piezoelectric sensor is very small. This is because
the piezoelectric material, PZT, that is used for its high piezo-
electric coefficient also has a very high dielectric constant. As
shown below, the output voltage is proportional to the charge
and inversely proportional to the dielectric constant:
Q Q eSA eSd
V = = = = (17)
C
A/d
A/d

[The output voltage can also be written in terms of the strain
S, the distance d, the electron charge e, and the dielectric
constant ⑀ as shown in Eq. (19) below.] For these and other
reasons the charge amplifier interface was selected for our
design example.
The charge amplifier circuit shown in Fig. 15 is in its sim-
plest form. The charge Q and capacitance CS are used to
model the sensor charge and sensor capacitance. The in-
verting terminal of the operational amplifier is a virtual
ground, and no charge flows into the operational amplifier in-
puts. Therefore, any charge that is generated across the sen-
sor has to flow into the feedback capacitance Cf . The output
voltage developed across the feedback capacitor is inversely
proportional to the value of this capacitance. The voltage gain
of the circuit is given by the ratio of CS to Cf , and hence, to
obtain high gain, Cf can be made much smaller than CS. This
basic topology has a number of limitations, including low-fre-
quency flicker noise of the amplifier, operational amplifier off-
set, and long-term drift. Traditionally, correlated double sam-
Cf
–
V0
+
Q Cs
Figure 15. Charge amplifier.
500 DATA ACQUISITION AND CONVERSION

Cf proportional to the square of the signal bandwidth and sen-

sor capacitance.
If, however, bipolar transistors are used to implement the
operational amplifier, the minimum power requirements is
– given by
V0
Q Cs
+ P = V I = V · 2π BW UTC (21)

V Here, UT is the thermal voltage, which is equal to 26 mV at

room temperature. From this equation it is clear that in the
case of bipolar transistors, the power is linearly proportional
gm to the signal bandwidth and sensor capacitance. This differ-
ence in the power consumption between bipolar and MOS im-
Figure 16. Modified charge amplifier circuit. plementations for a signal frequency of 1 MHz is shown in
Fig. 17. Here we note that the power consumption for both
MOS and bipolar implementations increases with increased
sensor capacitance. However, for very low frequencies, the
pling and chopper stabilization are used to remove low-
MOS devices can be operated in weak inversion (WI). In WI,
frequency noise and offset. However, as noted earlier, our sig-
MOS devices behave very similarly to bipolar devices, and
nal band does not include the frequencies from dc to 50 kHz,
hence the slopes for weak inversion and bipolar devices are
and our maximum signal frequencies are fairly high. There-
initially very similar. However, at higher frequencies MOS
fore, an alternative design topology shown in Fig. 16 was se-
devices are forced to operate in strong inversion and hence
lected to circumvent the problem.
consume more power for the same performance.
Here, low-frequency feedback is provided to reduce the ef-
Next, we consider the design tradeoffs in connection with
fects of offset, long-term drift, and low-frequency noise. In the
device noise.
modified circuit, a transconductor is connected in negative
feedback. The transfer function of the modified circuit is
given by Noise Analysis. The power spectral density for the wide-
band gate-referred noise voltage for MOS transistors is given
V0 (s) s · ( gm a − gm − Cf · s) by
=− (18)
Qin (s) Cs · Cf · s2 + s(Cs · gm + gm a · Cf ) + gm a · gm
8 kT
2
VnT = (22)
3 gm
In this equation, Cs is the sensor capacitance, Cf is the feed-
back capacitance of the operational amplifier, gma and gm are
the transconductances of the operational amplifier and the Here, k is Boltzmann’s constant, T is the temperature, gm is
transconductor. If the higher-order terms are neglected, then the transconductance. Likewise, for bipolar transistors the
Eq. (18) can be simplified to power spectral density for the wide band input-referred noise
voltage is given by
V0 (s)
=−
s
·
1
Cs · s
 (19) 2
VnT = 2qIC (23)
Qin (s) gm
1+
gm a
For both MOS and bipolar implementations the total rms
From Eq. (19) it is clear that the circuit has the characteris- input referred noise is independent of frequency and inversely
tics of a high-pass filter, that is, none of the low-frequency
noise or offsets affect the circuit performance.
Next, we perform a power analysis to analyze the effects 1
of different design tradeoffs. Both MOS and bipolar transistor
technologies are considered, and power and noise analysis
and design tradeoffs for both technologies are presented. MOS
0.1 SI
Power (mW)

Bipolar
Power Analysis. If MOS transistors in strong inversion (SI)
are used to implement the operational amplifier, then the
minimum power requirement is given by WI
0.01
V (2π BWC)2
P = VI = (20)
2K · W/L
0.001
where BW is the signal bandwidth, C is the sensor capaci- 20 40 60 80 100
tance, K is the transconductance factor, V is the output volt- Sensor capacitance (pF)
age, I is the supply current, and W/L is the aspect ratio of the Figure 17. Minimum power requirements versus sensor capacitance
transistor. From this equation it is clear that the power is for a MOS or bipolar design.

1000
RMS noise ( µV)
100
10
1 mentation a 10-bit fourth-order sigma–delta implemented as
1 10
Sensor capacitance (pF)
Figure 18. Noise power spectral density versus capacitance.
proportional to the sensor capacitance as shown in Fig. 18.
Here, we note that the ratio of the noise spectral density for
the MOS and the bipolar implementations is a constant equal
to four.
In summary we note that: For a MOS implementation the
power consumption is proportional to the square of the sensor
capacitance, whereas for a bipolar implementation it is lin-
early proportional to the sensor capacitance. On the other
hand, the input-referred noise for both the MOS and bipolar
implementations is inversely proportional to the sensor ca-
pacitance. Thus, there is a clear tradeoff between the mini-
mum power consumption and the maximum input-referred
noise. If the sensor capacitance is increased, then the input-
referred noise decreases, but the power increases, and vice
versa. Using the equation above, we can calculate the mini-
mum bound on the power requirements for our application.
For 10 bits of accuracy and a signal bandwidth of 1 MHz, the
minimum sensor capacitance size is 5 pF and the minimum
power consumption is around 500 애W.
Next, we provide some simulation and measurement re-
sults for our acoustic emission sensor system.
Results. Simulation and measurement results for the
charge amplifier with a sensor capacitance of 100 pF and a
feedback capacitance of 10 pF are shown in Fig. 19. For this
measurement, discrete versions of the sensor and feedback
25
20
15
Gain (dB)
10
Simulated
5 Measured
0 ADC
–5 CS = 100 pF, Cf = 10 pF
–10
101 102 103 104 105 106
Frequency (Hz)
Figure 19. Small-signal frequency response of the charge amplifier.
DATA ACQUISITION AND CONVERSION 501
capacitors were used. As expected, the signal band gain is
given by the ratio of the sensor to the feedback capacitance,
which is equal to 20 dB. Both measurement and simulation
results agree fairly well with this value. The primary differ-
ence between the measurement and simulation results is in
the low-frequency and high-frequency poles. It is expected
that this is largely a result of parasitic capacitances and pos-
sibly a lower realized transconductance in comparison with
the simulated value.
The charge amplifier circuit design just described converts
the sensor charge into a voltage. This amplified signal voltage
is then converted to digital form using an ADC. For our imple-
100 a MASH topology was used. The fourth-order topology was
used to keep the oversampling ratio low, as the signal fre-
quency is fairly high. Details of this implementation are not
included here; interested readers are referred to Ref. 6 for
more information.
Next, we describe a complete temperature sensor system.
Temperature Sensing System
In many control systems, temperature sensors are used as the
primary sensor. Additionally, as most electronic components
and circuits are affected by temperature fluctuations, temper-
ature sensors are often needed in microsensor systems to
compensate for the temperature variations of the primary
sensor or sensors.
Because integrated sensors can be manufactured on the
same substrate as the signal-processing circuitry, most recent
temperature measurement schemes concentrate on integrated
silicon temperature sensors. The resulting smart sensor is ex-
tremely small and is also able to provide extremely high per-
formance, as all the signal processing is done on chip before
the data is transmitted. This avoids the usual signal corrup-
tion that results from data transmission. The disadvantage of
the smart sensor is that since all the processing is done on
chip, it is no longer possible to maintain the signal prepro-
cessing circuits in an isothermal environment. The on-chip
sensor interface electronics must therefore be temperature-
insensitive or be compensated to provide a temperature-in-
sensitive output.
A smart temperature sensor is a system that combines on
the same chip all the functions needed for measurement and
conversion into a digital output signal. A smart temperature
sensor includes a temperature sensor, a voltage reference, an
ADC, control circuitry, and calibration capabilities. A block
diagram for a smart temperature sensor is shown in Fig. 20.
The use of p–n junctions as temperature sensors and for the
generation of the reference voltage signals has been reported
extensively (12,13). A bandgap voltage reference can be gener-
Temp.
sensor Digital
Bitstream Digital output
filtering
Reference
voltage
107
Control and calibration
Figure 20. Smart temperature sensor.
502 DATA ACQUISITION AND CONVERSION

Therefore, the difference between the two base–emitter volt-

V ages (⌬Vbe) is given by
Ic Vref = Vbe1 + G∆Vbe
nkT I I nkT R I
Vbe = Vbe1 − Vbe2 = ln 1 s2 = ln 2 s2 (25)
Vbe1 q I2 Is1 q R1 Is1
G∆Vbe
Vref
+ Vbe2 This voltage appears across R3. Since the same current that
PTAT cell flows through R3 also flows through R2, the voltage across R2
∆Vbe G ∆Vbe is given by
generator
Temperature R2 R nkT R I
VR = Vbe = 2 ln 2 s2 (26)
2 R3 R3 q R1 Is1
Figure 21. Principle of bandgap reference.

ated with the help of a few p–n junctions. The basic principle
for the operation of a bandgap voltage reference is illustrated
in Fig. 21.
The base–emitter voltage Vbe of a bipolar transistor de-
creases almost linearly with increasing temperature. The
temperature coefficient varies with the applied current, but is
approximately ⫺2 mV/⬚C. It is also well known that the dif-
ference between the base–emitter voltages of two transistors,
⌬Vbe, operated at a constant ratio of their emitter current den-
sities, possesses a positive temperature coefficient. At an
emitter current density ratio of 8, the temperature coefficient
of this PTAT (proportional to absolute temperature) source is
approximately 0.2 mV/⬚C. Amplifying this voltage (G⌬Vbe) and
adding it to a base-emitter voltage Vbe produces a voltage ref-
erence that is independent of temperature. Many circuits
have been developed to realize bandgap voltage references us-
ing this principle (14,15). A circuit diagram for one of the
early bandgap reference implementations is shown in Fig. 22
(16).
For an ideal operational amplifier, the differential input
voltage is equal to zero, so that resistors R1 and R2 have equal
voltages across them. Since the voltage across the resistors is
the same, the two currents I1 and I2 must have a ratio that is
determined solely by the ratio of the resistances R1 and R2.
The base–emitter voltage of a diode-connected bipolar tran-
sistor is given by Eq. (24) below, where T is the absolute tem-
perature of the junction, Is is the reverse saturation current,
Id is the current through the junction, k is Boltzmann’s con-
stant, q is the electronic charge, and n is a constant that de-
pends on the junction material and fabrication technique. To
see this, we write
nkT I + Is nkT I
Vbe = ln d ≈ ln d
q Is q Is
as desired.
The output voltage is the sum of the voltage across R1 and
the voltage across Q1. Since the voltage across R1 is equal to
the voltage across R2, the output voltage is equal to
R2 nkT R I
Vout = Vbe1 + ln 2 s2 = Vbe1 + G Vbe (27)
R3 q R1 Is1
Therefore, this circuit behaves as a bandgap reference, where
the gain factor G is set by the ratios R2 /R3, R2 /R1, and Is2 /Is1.
In many designs R2 ⫽ R1 and Is2 ⫽ 8Is1. Since the reverse
saturation current Is is proportional to the emitter area, to
make Is2 ⫽ 8Is1 we let the emitter area of Q2 be 8 times as
large as the emitter area of Q1.
The operational amplifier’s input-referred voltage offset is
the largest error source in this type of voltage reference. This
voltage offset is highly temperature-dependent and nonlinear,
making an accurate calibration of such a reference virtually
impossible. It is therefore necessary to use some type of offset
cancellation technique such as autozero or chopper stabiliza-
tion (17).
Another source of error is the nonzero temperature coeffi-
cient of the resistors. Usually on-chip resistors are used, in
the form of polysilicon resistors or well resistors. Both of these
resistor implementations tend to occupy very large amounts
of chip area if low power is desired. Low-power implementa-
tions demand the use of large-value resistors, which unfortu-
nately require large areas. Though well resistors have a much
larger resistivity than polysilicon resistors, they also have a
very nonlinear temperature coefficient, which makes for dif-
ficult calibration.
(24)
θ1 θ1

C2 θ2 θ2 C2

+
R1 R2 Vref
C3 θ2 –
+
Vref
–
I1 I2
θ1 CF
R3
1× 8×
CT CT
Q1 Q2
Gnd
Figure 23. A switched-capacitor implementation of the bandgap ref-
Figure 22. Example bandgap voltage reference circuit. erence.
 DATA ACQUISITION AND CONVERSION 503

S6
CB
Vin
S1 CA
Vref – II Digital
S2 S5 + ai Up– output
S4 + down
S3 – counter

S1 to S1
Switch control
logic
Figure 24. Incremental ADC.

A solution to these problems is to use switched-capacitor
circuits to implement the resistors in the voltage reference
circuit. A switched-capacitor implementation makes offset re-
moval simple and also reduces the power consumption, as the
area occupied by large-value switched-capacitor resistors is
significantly smaller than the area occupied by continuous-
time resistors. In fact, the area occupied by switched-capaci-
tor resistors is inversely proportional to the value of the resis-
tance desired. Another advantage is that the temperature co-
efficient of on-chip poly–poly capacitors is much smaller than
that of on-chip resistors, making design and calibration eas-
ier. A switched-capacitor implementation of the bandgap volt-
age reference is shown in Fig. 23.
The structure of this voltage reference is similar to the one
shown in Fig. 22, except that the continuous time resistors
have been replaced by switched-capacitor resistors, and ca-
pacitors CT and CF have been added. The switched capacitors
emulate resistors with an effective resistance value given by
1 ture sensor system involves some additional circuitry. Since
Reff =
f CC
where f C is the clock frequency of the switch. The feedback
capacitor CF is designed to be very small and is added to en-
sure the operational amplifier is never in an open-loop mode
of operation. The capacitors located in parallel with the diodes
act as tank capacitors to ensure that current is constantly
supplied to the diodes. The output of this voltage reference
can similarly be calculated and is given by
C3 nkT C I
Vref = Vbe1 + ln 1 s2 = Vbe1 + G Vbe
C2 q C2 Is1
which is the desired bandgap voltage reference.
Most temperature-sensing devices also use the difference
between two diodes (⌬Vbe) as the sensing element of the sys-
tem. Since the temperature coefficient of ⌬Vbe is small (앒0.2
mV/⬚C), it is almost always amplified to a much larger value
(앒10 mV/⬚C) for increased sensitivity. Since we already have
an amplified value of ⌬Vbe in the voltage reference (G⌬Vbe), all
that needs to be done is to subtract Vbe1 from the voltage refer-
ence to obtain an amplified value of ⌬Vbe. If more sensitivity
is needed, the additional amplification can be incorporated in
the ADC by simply adjusting the capacitor ratio of CA and CB
as shown in Fig. 24. Additionally, the subtraction of Vbe1 from
the voltage reference can be easily accomplished with the cir-
cuit shown in Fig. 25, where Vin1 is the output of the voltage
reference, Vin2 is equal to Vbe1, and VG is the negative input of
the operational amplifier in the follow-on data converter. Dur-
ing clock cycle ␪1 the capacitor C is charged to the input volt-
age Vin2. During clock cycle ␪2, the charge (Vin1 ⫺ Vin2)/C is
transferred. This circuit effectively does the voltage subtrac-
tion that is needed to obtain the amplified temperature-de-
pendent output voltage (G⌬Vbe).
Incorporating the voltage reference and temperature-sens-
ing circuitry shown in Figs. 23 and 25 into a smart tempera-
(28)
switched capacitors are already being used for the voltage ref-
erence and the sensing circuitry, it makes sense to use
switched-capacitor technology for the ADC. A simple ADC
that utilizes oversampling techniques is the incremental con-
verter (18). The advantage of this data converter topology,
shown in Fig. 24, is its low power consumption, small area,
and insensitivity to component mismatch. Additionally, in
comparison with sigma–delta converters the postquantization
digital low-pass filter is much simpler. It consists of just an
up–down counter instead of a more complicated decimation
filter. Unfortunately, the first-order incremental ADC has a
(29)
relatively long conversion time, making this converter suit-
able only for very slow signals such as temperature.
The first-order incremental ADC shown in Fig. 24 is com-
posed of a stray-insensitive switched-capacitor integrator, a
comparator, switch control logic, and an up-down counter. A
four phase nonoverlapping clock as shown in Fig. 26 consti-

Vin2 θ1
θ1 C
VG θ2
θ2
θ3
Vin1
θ2 θ1
θ4

Figure 25. Switched-capacitor subtraction circuit. Integration period

Figure 26. Four-phase nonoverlapping clock.
504 DATA ACQUISITION AND CONVERSION

θ1 θ1

C2 θ2 θ2 C2
+ VRef
C3 θ2 –

θ1 CF

Q1 Q1
CT CT

S6
CB
S1 CA
+ VI Digital
S2 S5 + ai Up– output
S4 – down
–
counter
Vbe1
Ssub
S1 – S6 Switch control
logic

Figure 27. Smart temperature sensor circuit.

tutes an integration period. The integrator output voltage is Also during ␪4, the integrator output voltage VI[i, 4] is given
designated by VI[i, j], where i corresponds to the current inte- by
gration period and j to the clock cycle (1, 2, 3, or 4).
During clock cycle ␪1, S1 and S4 are closed, charging CA to CA
the input voltage Vin. During ␪2, S3 and S5 are closed, transfer- VI [i, 4] = VI [i, 1] + (V − aiVref ) (30)
CB in
ring the charge that was stored on CA to CB. At the end of the
charge transfer from CA to CB the comparator output is de-
The final N bit output code, denoted by Dout, that results from
noted by
the up–down counter is obtained by evaluating the quantity

1 if VI [i, 2] > 0
ai = 1 n
−1 if VI [i, 2] < 0 Dout = a (31)
n i=1 i
During ␪3, S4 is closed, and if:
Here n is the number of integration periods, and is a function
ai = 1, S3 is closed of the resolution that is required of the ADC.
ai = −1, S2 is closed The complete smart temperature sensor is shown in Fig.
27. The subtraction circuit of Fig. 25 is incorporated into the
During ␪4, S5 is closed, and if: ADC by simply adding switch Ssub. The only difference in the
operation of the incremental converter shown in Fig. 27 from
ai = 1, S2 is closed
the one shown in Fig. 24 is that now during ␪2, S3 is not closed
ai = −1, S3 is closed but instead Ssub is closed.

1.4 0.85

1.35 0.80
0.75
Vref – Vbel (V)

1.3
Vref (V)

0.70
1.25
0.65
1.2
0.60
1.15 0.55
1.1 0.50
220 240 260 280 300 320 340 360 380 220 240 260 280 300 320 340 360 380
Temperature (K) Temperature (K)
Figure 28. Measurement results for the (a)
voltage reference, (b) the temperature sensor. (a) (b)

Figure 29. Measurement results for the analog-to-digital converter.
The calibration of this system is done in two steps. First
the voltage reference is calibrated by adjusting the ratio of
C3 and C2; next the amplified sensor voltage is calibrated by
adjusting the ratio of CA and CB. Adjusting the ratios of the
capacitors is done with the use of a capacitor array that is
controlled digitally. The output is an N bit digital word.
In Fig. 28 we show measurement results for the voltage
reference and final temperature output. For these results a
first-pass design of the circuit in Fig. 27 was used. This design
was not completely integrated and included external resistors
to obtain gain. We expect final integrated results to behave
similarly. Figure 28(a) shows the reference voltage obtained
as a sum of a Vbe and an amplified ⌬Vbe as described in Eq.
(29). The x axis shows the temperature in kelvin and the y
axis shows the measured output reference voltage in volts.
The measured value is fairly close to the expected value ex-
cept for some small experimental variations. We suspect
these variations are a result of the length of time used to
stabilize the temperature between temperature output mea-
surements. The graph in Fig. 28(b) shows the output voltage,
which is Vref ⫺ Vbe. As expected, this voltage varies linearly
with temperature. Figure 29 shows the expected 1 bit output
stream (ai shown in Fig. 24) of the sigma–delta converter be-
fore the digital low-pass filter. This output corresponds to an
input voltage equal to one-eighth of the reference voltage.
We have provided detailed designs for two complete data
acquisition systems, namely an acoustic emission sensor sys-
tem and a smart temperature sensor system. We provide both
measurement and simulation results to show their perfor-
mance.
CONCLUSION
In this article we have provided brief descriptions of data ac-
quisition and data conversion systems. In particular, we pro-
vided some general descriptions of integrated capacitive and
resistive sensors. This was followed by descriptions of two of
the most common data converter topologies used in sensor
interface systems, namely successive approximation and
sigma–delta. Finally, these were followed by detailed descrip-
tions of two complete acquisition systems. The first system
was based on a piezoelectric acoustic emission sensor inter-
faced to a charge amplifier and data converter. The second
DATA ACQUISITION AND CONVERSION 505
system was a smart temperature sensor. As feature sizes con-
tinue to decrease and integrated sensor technologies progress,
it is likely that extremely smart and high-performance sys-
tems will be integrated on single chips. Additionally, signifi-
cant reduction in power and area as a result of smaller fea-
ture sizes will make such systems ubiquitous.
BIBLIOGRAPHY
1. W. Gopel, Sensors in Europe and Eurosensors: State-of-the-
art and the science in 1992, Sensors Actuators A, 37–38: 1–5,
1993.
2. R. Pallás-Areny and J. G. Webster, Sensors and Signal Condition-
ing, New York: Wiley-Interscience, 1991.
3. K. Najafi, K. D. Wise, and N. Najafi, Integrated Sensors, in S. M.
Sze (ed.), Semiconductor Sensors, New York: Wiley, 1994.
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wood, MA: Analog Devices, 1980.
5. R. J. van de Plassche, J. H. Huijsing, and W. M. C. Sansen, Ana-
log Circuit Design—Sensor and Actuator Interfaces, Norwell, MA:
Kluwer, 1994.
6. R. Harjani, Analog to digital converters, in Wai-Kai Chen (ed.),
The Circuits and Filters Handbook, New York: IEEE/CRC
Press, 1995.
7. J. L. McCreary and P. R. Gray, All-MOS charge redistribution
analog-to-digital conversion techniques—part I, IEEE J. Solid-
State Circuits, 10: 371–379, 1975.
8. H. S. Lee, D. A. Hodges, and P. R. Gray, A self-calibrating 15
bit CMOS A/D converter, IEEE J. Solid-State Circuits, 19 (6):
813–819, 1984.
9. F. Wang and R. Harjani, Design of modulators for oversampled
converters, Norwell, MA: Kluwer, 1998.
10. J. C. Candy and G. C. Temes (eds.), Oversampling Delta–Sigma
Data Converters—Theory, Design and Simulation, New York:
IEEE Press, 1992.
11. S. M. Sze (ed.), Semiconductor Sensors, New York: Wiley, 1994.
12. A. Bakker and J. Huijsing, Micropower CMOS temperature sen-
sor with digital output, IEEE J. Solid-State Circuits, SC-31 (7):
933–937, 1996.
13. G. Meijer, An IC temperature transducer with an intrinsic refer-
ence, IEEE J. Solid-State Circuits, SC-15 (3): 370–373, 1980.
14. S. Lin and C. Salama, A Vbe(T) model with applications to band-
gap reference design, IEEE J. Solid-State Circuits, SC-20 (6):
1283–1285, 1985.
15. B. Song and P. Gray, A precision curvature-compensated CMOS
bandgap references, IEEE J. Solid-State Circuits, SC-18 (6): 634–
643, 1983.
16. K. Kuijk, A precision reference voltage source, IEEE J. Solid-
State Circuits, SC-8 (3): 222–226, 1973.
17. C. Enz and G. Temes, Circuit techniques for reducing the effects
of op-amp imperfections: Autozeroing, correlated double sam-
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18. J. Robert and P. Deval, A second-order high-resolution incremen-
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KAVITA NAIR
CHRIS ZILLMER
DENNIS POLLA
RAMESH HARJANI
University of Minnesota
506 DATA ANALYSIS

DATA ACQUISITION SYSTEMS. See MICROCOMPUTER

APPLICATIONS.
 DELAY CIRCUITS 127

A delay circuit shifts an input signal in time by a specific

magnitude. In other words, the output of a delay circuit is a
replica of the input, occurring a specific length of time later.
In many situations arising in practice, the specifications (com-
ing from magnitude or bandwidth, for example) are better
met by cascading identical delay circuits. A delay line is so
obtained. Other applications require generating a number of
shifted replicas at arbitrary intervals. This is generally done
by taps placed at the output of every stage of a delay line,
and then a tapped delay line is obtained.
According to this definition, the class of circuits which
must be considered ranges from the most simple resistance-
capacitance (RC) stages to finite impulse response (FIR) or
infinite impulse response (IIR) filters able to delay a discrete-
time signal by a magnitude which is not a multiple of the
sampling interval. Given this wide circuit scope, there is in
consequence a possible overlap with the contents of other arti-
cles in this Encyclopedia. In order to minimize this overlap,
the design and implementation of some of these circuits will
be more extensively treated than others.
The article is structured in two well-differentiated sec-
tions, as the continuous-time and the discrete time ap-
proaches are dealt with separately. Each section has been or-
ganized in several subsections. In both cases we address
mathematical modelling, system implementation, and circuit-
level implementation issues. Continuous amplitude signals
(analog signals) and discrete amplitude signals (digital sig-
nals) have a very distinct nature and it is well established
that depending on the signal type, the implementation of de-
lay elements follows very different circuit approaches. In con-
sequence, we differentiate the analog and digital domain
when required.

CONTINUOUS-TIME APPROACH

Delay Models
The building of a device which delays a continuous-time sig-
nal, xc(t), by an amount, tD, as shown in Fig. 1, is conceptually
simple. There is nothing physically unreasonable with such a
device if tD is positive (the response occurs after the excita-
tion). If we only require that the response be a scaled (by k)
replica without distortion of the excitation occurring tD time
units later, we can define a linear operator, Lc, which yields
its output, yc(t), as:

yc (t) = Lc {xc (t)} = kxc (t − tD ) (1)

The delayed signal output response must be zero for 0 ⱕ t ⬍

tD because we analyze the behavior from t ⫽ 0 onward. In Eq.

DELAY CIRCUITS
y(t) = xc(t – tD)
There are two forms in which delays can appear in circuits. y(t) = xc(t)
First, there are inevitable delays associated with wiring and
physical devices, which are not at the invitation of the de-
signer. However, delays can also be included for very different
T
purposes and with distinct applications. In this article, we
shall describe the circuits or systems employed for generating t tD t
these intentional delays. We will refer to them with the ge-
neric term of delay circuits. Figure 1. Delaying a continuous-time signal.

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.
128 DELAY CIRCUITS

(1), k is a constant which represents amplification or attenua- functions for first- and second-order all-pass filters. Both fil-
tion, and perhaps polarity reversal. ters satisfy the amplitude condition: they have an amplitude
Delaying continuous-time signals can be considered in a of 1 for all frequencies. The group delay condition, is only par-
suitable transform domain provided by the Laplace trans- tially fulfilled: the associated group delay is only approxi-
form. The ideal transfer function of such a device can be eas- mately constant if (웆/웆0)2 Ⰶ 1 in a first-order all-pass filter,
ily derived as: with the specific properties of this function being controlled

∞
∞ by Q and 웆0 in a second-order all-pass filter. Hence, for band-
Yc (s) = yc (t)e−st dt = k xc (t − tD )e−st dt limited signals, all-pass filters can perform as delay sections.
0 0

∞ Two or more of these sections can be cascaded to obtain delay
Yc (s) = k xc (µ)e−s(µ+t D ) dµ where µ = t − tD lines. Delay lines using low-pass filters (first- or second-order
0 (2) follower-integrator sections) have also been proposed for spe-

∞
−st D −sµ −st D cific applications (2). For such lines, the response at high fre-
Yc (s) = ke xc (µ)e dµ = ke Xc (s)
0
quencies will decrease sharply, in a very steep way, but in the
Hid (s) = ke−st D range of application in which they are used, the group delay
is approximately constant in the same conditions as the all-
From Eq. (2), we obtain for ideal distortionless transmis- pass filters are.
sion that the transfer function Hid(s), is Hid(s) ⫽ ke⫺stD. This The field of filter design and implementation is the subject
condition is frequently more useful when expressed in the of many other articles in this work, so we do not deal with
frequency domain (웆-domain) by setting s ⫽ j웆. It gives the circuit and physical level implementation issues here. We
Hid( j웆) ⫽ (ke⫺stD)s⫽j웆 ⫽ ke⫺j웆tD, which expressed in terms of mod- will just mention that time constants depend on parameters
ulus 兩Hid( j웆)兩, and argument arg兵Hid( j웆)其 ⫽ ⌰id(웆) allows us to such as capacitors and transistors which are temperature-
obtain two properties for the transfer function: first, a con- and process-dependent; therefore, some extra circuitry is re-
stant modulus for all frequencies is required, and second, a quired to control the delay time. Solutions to this problem
phase shift depending linearly on the frequency, ⌰id(웆), is resort either to control the delay time by an external voltage
needed in order to provide a frequency-independent group de- or, more commonly, to locking it to an external reference fre-
lay ␶g(웆): quency.
|Hid ( jω)| = k constant
 Delay Circuits for Digital Signals
id (ω) = −ωtD linear with ω
A different point of view is taken in many applications that
τg (ω) = − ∂  (ω) = t constant
∂ω id D require delaying digital signals. These delay circuits are a key
component of phase locked loops (PLLs) and delay locked
Two models of delays are widely used for digital signals. Pure loops (DLLs), which find wide application in wireless and
delays shift the input signal in time by a specific magnitude communication circuits, high-speed digital circuits, disk drive
tD. This model corresponds to the mathematical operator in- electronics, and instrumentation, because a number of design
troduced at the beginning of this section. A second useful problems can be efficiently solved with them. The main prob-
model is the inertial delay. An inertial delay of magnitude tD lems that can be solved are jitter reduction, skew suppres-
shifts the input signal in time by tD and filters out pulses sion, frequency synthesis, and clock recovery. A different and
(both positive and negative) of duration less than tD. familiar application area is the control of the timing of a data
Delay Circuits for Analog Signals sampling or of a generation process. Very fine resolution is
often required in these types of applications. Very large-scale
A device implementing distortionless transmission condition integration (VLSI) automated test equipment and time mea-
cannot be a finite, lumped linear constant element network, surement systems for nuclear instrumentations are some ex-
because its transfer function is transcendental and not ratio- amples. Finally, another interesting application of these delay
nal in s. Ideal transmission lines have such transfer functions circuits is that of self-timed circuits. Following, a brief review
and they are described by partial differential equations. of the relevant issues and options for these delay circuits is
Hence physical realizations of ideal delay-transfer functions presented.
do exist, although not as networks. Neither pure nor inertial delays can be perfectly realized
Good approaches for devices implementing distortionless in the real world. A real inertial delay of magnitude tD, when
transmission, however, can be obtained, for example, with all- stimulated with pulses of width varying from tD ⫹ e to tD ⫺ e
pass filters (1). Table 1 shows the transfer and group delay for some small value e ⬎ 0, produces a continuum of wave-
forms between a pulse of width tD ⫹ e to no pulse at all. Real
Table 1. Transfer and Group Delay Functions for First- delays are often better modelled as combinations of the two
and Second-Order All-Pass Filters types (3). The introduced models produce output waveforms
Order Transfer Function Group Delay Function similar to the input waveforms. This is because both rising
and falling edges are propagated with the same delay. In
s ⫺ 웆0 2/웆0 practice, delay circuits which have different delays for each
First H(s) ⫽ ␶g(웆) ⫽
s ⫹ 웆0 1 ⫹ (웆/웆0)2
transition are useful for many applications. Also, there is an-
웆
s2 ⫺ 0 s ⫹ 웆20 other type of application for which only one transition polarity
Q 2 1 ⫹ (웆/웆0)2
Second H(s) ⫽ ␶g(웆) ⫽ is significant. The delay is then used to initiate events at arbi-
웆 Q웆0 1
s2 ⫹ 0 s ⫹ 웆20 [1 ⫺ (웆/웆0)2]2 ⫹ 2 (웆/웆0)2 trary times. The response to an input edge or pulse is a fixed-
Q Q
width pulse after a given time.

Vref –
+ Output
Ramp
Input generator Vramp
Input Vin
Vref
Vramp
Output
(a)
Input 1 2 3 .....
(c)
Input +
1 2 3 .....
Input –
(d)
Because of the impossibility of ideal delay elements, a set
of figures of merit (4) are used to specify delay circuits in ad-
dition to nominal delay:
1. Bandwidth or maximum usable input signal frequency
(In many cases it is not limited by the functional failure
of the delay but by the accuracy degradation due to
what is called history effects or pulse memory. The de-
lay of a signal edge is perturbed by the presence of other
edges in the recent past.)
2. Tolerance of nominal delay
3. Temperature coefficient of nominal delay
4. Voltage coefficient of nominal delay
5. Jitter or random variation in the delay of different
edges due to noise (It can be evaluated by maximum
error or by the standard deviation of errors.)
Basically, continuous digital signals can be delayed using
passive transmission lines which behave roughly as a pure
delay element, RC delays or logic gates. Transmission lines
can be used at the PC board and hybrid levels. Here, we focus
on delay circuits to be included with other elements within an
integrated circuit (IC). Figure 2 shows different generic ways
of realizing delays together with common ways of implement-
ing their building blocks. The ramp and comparator approach
is depicted in Fig. 2(a). A transition of the input signal makes
a voltage ramp, Vramp, start from a stable initial level. The
ramp and a control voltage, Vref , are applied to the inputs of
a high-speed comparator, which switches at a time propor-
tional to the control level. Fig. 2(b) shows a conventional RC-
delay circuit for implementing the approach just described.
When the input signal Vin rises, the node Ramp starts to dis-
charge through R1. The simplest method for delaying a digital
DELAY CIRCUITS 129
R2
Vref
R3
+
Ramp – Output
C1
R1
(b)
N –1 N
Output
Output – Figure 2. Generic schemes for delaying digital sig-
N –1 N
Output + nals: (a) The ramp and comparator approach; (b) con-
ventional RC delay element; (c) single-ended gate
chain; and (d) differential gate chain.
signal, an RC stage with input and output buffers, can be
viewed as a particular case of this generic scheme. The refer-
ence voltage is now the threshold voltage of the output buffer.
Another variation substitutes the comparator for a mono-
stable circuit.
Logic gates are an obvious and almost universally avail-
able delay medium. Chains of logic gates are widely applied
to delay signals as shown in Figs. 2(c) and 2(d). The nominal
delay depends both on the delay of each cell and on the num-
ber of stages. When single-end gates are the basic cell of the
chain, inverting gates are usually used in order to balance the
propagation time of rising and falling edges which can affect
the accuracy of the delay element. Differential circuits tech-
niques [Fig. 2(d)] are extensively used for several reasons.
First, differential gates achieve a high rejection of noise; sec-
ondly, they reduce edge dependency. In general, reduced
swing differential circuit techniques are a good choice because
they also allow maximize bandwidth. Finally, the functional-
ity of the basic delay cell can be other than that of a buffer,
depending on the application. For example, exclusive OR
(XOR) gates and latches have been used in pattern generation
and time measurements systems (5,6).
Programmable or adjustable delays, that is, delays de-
pending on one or more control inputs, are interesting for
many reasons. Devices that can satisfy a wide range of appli-
cations and that can be of manual or automatic calibration
are the main ones. Control inputs can be digital or analog.
The specification of these delays requires additional variables
such as range of available delays, resolution, tolerance and
stability of range, and linearity (4).
There are three different strategies for realizing controlla-
ble delays which are summarized in Fig. 3. The first one con-
sists of selecting one of several fixed delay paths between in-
130 DELAY CIRCUITS
Input Fixed delay
D1
Fixed delay
D2
(a)
Input
Input
Figure 3. Generic methods for realizing
variable delays: (a) Selectable path ap-
proach, parallel implementation; (b) se-
lectable path approach, serial implemen-
tation; (c) variable delay fixed path
approach; (d) delay interpolation.
put and output. Figures 3(a) and 3(b) show two possibilities.
Care must be taken to match the delays in all paths in the
selector logic. This can be critical if selectable delays differ
little or in certain applications. In the second approach [Fig.
3(c)], the physical path of the signal remains constant but its
delay is varied. A third approach, called delay interpolation,
uses two paths with different delays in parallel. The total de-
lay is an adjustable weighted sum of the delays of the two
paths as shown in Fig. 3(d).
In Fig. 3(c), the delay is tuned by the control input. The
Vref input of the ramp and comparator delay circuit can be
used as the control input in order to build a variable delay
element. This approach is popular because of its flexibility
and naturally linear response. A different strategy is used in
the circuit shown in Fig. 4(a) (2), where the control input,
Vctrl, affects the slew rate at node V1 instead of the triggering
voltage. Starting with Vout low, when Vin becomes active, cur-
rent Iin charges C1 until Vout triggers. The delay is inversely
proportional to Iin which depends on Vctrl. This element has
been used in an adaptative delay block which exhibits a high
pull-in frequency range partially because the transistor M1
operates in the subthreshold region (7).
In gate-based delay generators, control can be accom-
plished through capacitive tuning or resistive tuning of the
basic delay stages which form the chain. Figures 4(b)–4(e)
show different methods of implementing capacitive-tuned
variable-delay elements. These techniques vary the capaci-
tance at the output node. The generic circuit shown in Fig.
4(b) uses a voltage-controlled resistor to control the amount
of effective load capacitance seen by the driving gate. Figure
4(c) shows a metal oxide semiconductor (MOS) implementa-
tion of this approach (8,9). Transistor M2 has its source and
drain shorted together forming an MOS capacitor. The effec-
tive capacitance is larger as Vctrl increases and the resistance
Input Fixed Fixed
delay delay
MUX D1 D2 MUX
Output Output
Sel Sel
(b)
Variable delay
Output
Delay control
(c)
Fixed delay
D1
+
Fixed delay Output
D2
Weights' control
(d)
of transistor M1 is reduced. It can exhibit a poor linearity if a
wide delay range is required. Figure 4(d) employs a voltage-
controlled capacitor. This capacitor can be a reversed biased
p–n junction diode. A different option with digital control (10)
is depicted in Fig. 4(e). Node OUT is loaded by m pairs of
p–n load devices. When the ith enable line is low, the capaci-
tance load that the pair of devices present to node OUT is
minimal because inversion layer cannot be formed for any
voltage on OUT. When the ith enable line is high, the capaci-
tive load that the pair presents is maximal, because an inver-
sion layer can be formed under the gate of one or both of the
p–n devices.
Resistive tuning approaches use variable resistances to
control the current available to charge and discharge the
load capacitance. A classical example is the current-starved
inverter shown in Fig. 4(f). Voltage Vctrl controls the ON
resistance of transistor M1 and through a current mirror,
the transistor M2. Delay decreases as Vctrl increases,
allowing a large current to flow. A Schmitt trigger followed
by a buffer can be included to achieve fast rising and fall-
ing outputs (11). If a simple current mirror is used, the
delay is a very nonlinear function of the control voltage.
Moreover, its high gain coefficient (steep slope of delay
characteristic) makes it sensitive to noise on the control
voltage line. The linearity of the delay characteristic in the
current-starved inverter can be improved by using more
complex current mirror configurations (12).
Resistive tuning of differential delay elements is also pos-
sible. Other parameters such as the logic swing or dc gain are
controlled in addition to the effective load resistance. Figure
4(g) depicts the generic structure of a number of reported cir-
cuits (5,13–15). Clearly, the delay of the generic differential
gate can be changed with the voltage Vc1, since the effective
resistance of the load changes with this control voltage. Also,
 DELAY CIRCUITS 131

Vin
Iin V1
Vout
M1

Vctrl C1

Vbias

(a)

Vin Vout Vin Vout

Vctrl Vctrl

(d)
C1

(b)

Vin OUT

Vin Vout

M1
Vctrl Enable[1, m]

M2
m cells

(c) (e)

Differential gate

Vctrl
M2
Vc1
Load Load

Vin Vout Biasing

circuit
Vin+ Vin–

Vc2
M1
Vctrl

(f) (g)

Figure 4. Voltage-controlled variable delay elements: (a) Variation of the ramp-and-comparator

technique; (b) capacitive tuning using voltage-controlled resistor; (c) MOS implementation for
(b); (d) capacitive tuning using voltage-controlled capacitance; (e) digitally controlled MOS imple-
mentation for (d); (f) conventional resistive tuning circuit or current-starved inverter; (g) resistive
tuning of differential gates.
132 DELAY CIRCUITS

Vc2 can vary the delay of the gate as it adjusts the tail current. have a wide range and fine control of rising and falling delays.
The biasing circuit generates Vc1 and Vc2 from Vctrl. One of the Other schemes can be used to improve the resolution of a
two voltages, Vc1 or Vc2, may be nominally equal to Vctrl. The chain of delay elements, which is limited to the basic delay of
biasing block produces the appropriate value for the other one or two (if single-ended, inverting gates are used) of its
bias in order to control the parameters previously mentioned. stages. They include delay interpolation performing an analog
This can be done by implementing the replica biasing concept sum of consecutive taps. Precise delay interval generators
in which a copy of the delay cell, a differential amplifier, and with subgate resolution have been proposed based on a series
feedback are used. Also, the noise insensitivity of the delay of coupled ring oscillators (19) and using an array of similar
cell is improved with this technique, as the appropriate bias DLLs with a small phase shift between them (12).
voltage values are generated independently of supply voltage
variations. Finally, resistive tuning allows fully differential
DISCRETE-TIME APPROACH
approaches. That is, the control path is also differential. Par-
tially because of this feature, resistive tuning has been identi-
Delay Models
fied as the most suitable for implementing voltage-controlled
ocillators (VCOs) (16). Discrete-time signals are obtained by sampling a continuous-
An important consideration in designing accurate delay el- time signal at discrete times [Fig. 5(a)] or they are directly
ements is to compensate for variations in process, tempera- generated by a discrete-time process. Delaying a uniformly
ture, and supply voltage. Some of the delay circuits described sampled bandlimited (baseband) signal presents several ma-
use an RC time charge constant and generate delays almost jor differences when compared with the continuous time ad-
independent of MOS transistor characteristics. The delay de- dressed previously. If we simply convert Eq. (1) into discrete
viations due to these ambient and process conditions are time by sampling the continuous signal at time instants t ⫽
lower than those of a chain of single-ended conventional in- nT, where n is an integer and T is the sampling interval, then
verters (17). This sensitivity has been further reduced by we obtain:
making the charging current proportional to the reference
voltage, Vref (18). Thus, even if the reference voltage fluctuates y[n] = L{x[n]} = kx[n − D] (3)
as the result of supply-voltage, temperature, and device pa-
rameter variations, the current charging the capacitor com- If D is an integer (when tD is a multiple of the sampling inter-
pensates it, so the delay is constant. val), the output value is one of the previous signal samples,
In general, there are several ways to improve the stability
of delay circuits. Actions can be taken at different levels in
order to achieve the desired stability. In the architectural do-
main, a useful approach is to use adjustable delay elements y(t) = xc(t) x[n]
and continuously control them with a feedback mechanism.
Phase and delay locked loop techniques have been widely
used. For example, a DLL can be used to maintain the accu-
racy of a chain of delay elements through which a periodic T
signal (clock) is propagating (5,6,8,9). The effect of the DLL
approach is that two taps of the voltage-controlled delay line t n
(VCDL) driven by a clock reference are examined, and the (a)
delay element control voltage (Vctrl) is adjusted until the two
taps are in phase. Different delay values within the range y(t) = xc(t – tD)
of the delay elements can be maintained with different clock y(n) = x[n – D]
frequencies and different selections of the taps. This concept
has been applied to tuning in production, calibration, and ac-
tive delay regulation. In some cases, a pair of matched VCDLs
that depend on a common Vctrl are used. A feedback circuit
can make the delay of a reference chain match an external
time signal. The second line is the functional delay generator tD t D n
which is also stabilized. Physical design techniques which can (b)
reduce the effect of process and temperature gradients within
the chip, on-chip voltage, and temperature regulation and op-
timization of the gates for delay insensitivity can also be con- y[n] = x[n – D]
y(t) = xc(t)
sidered.
Noise is common to all electrical systems and it appears in
digital circuits primarily as timing jitter. Jitter can be re-
duced by careful application of the standard noise decoupling
and isolation techniques: guard rings, for example. Also, the
use of differential circuits and replica biasing circuits helps tD t n
(c) D
reduce the sensitivity to noise.
Delays can be combined in various ways in order to extend Figure 5. Delaying a discrete-time signal: (a) Sampling a continuous-
the range or the resolution. A serial connection of a selected- time signal at discrete times; (b) delaying a discrete-time signal by an
path delay and a constant-path variable-delay stage may integer D; (c) delaying a discrete-time signal by a noninteger D.
 DELAY CIRCUITS 133

and consequently, we have a delay of D samples [Fig. 5(b)]. and so, the ideal impulse response is obtained as:
But if D is not an integer, Eq. (3) has no formal meaning
because the output value would lie somewhere between two sin[π (n − D)]
samples, and it is impossible [Fig. 5(c)]. Other important dif- hid [n] = k for all n (6)
π (n − D)
ferences with the continuous time problem are related to the
necessity of clocking and the occurrence of aliasing effects.
In a similar way to the continuous-time case, delaying dis- The impulse response in Eq. (6) is now an infinitely long,
crete-time signal can be considered in a suitable transform shifted, and sampled version of the sinc function. We have
domain: the z-domain. An ideal transfer function in this do- here a fundamental difference with the continuous-time ap-
main can be obtained formally as: proximation problem. Causal continuous-time delays are al-

∞ ways causal and bounded input-bounded output (BIBO) sta-
Y (z) = k x[n − D] z−n ble whereas in the discrete-time problem for fractional sample
n=−∞ delays, neither of these properties hold: hid[n] is noncausal
∞
and is not absolutely summable. This noncausality makes it
Y (z) = k x[m] z−(m+D) where m = n − D impossible to implement it in real-time applications.
m=−∞ (4)
The output of the system for an input x[n] can be formally

∞
Y (z) = kz−D x[m] z−m = kz−D X (z) obtained as:
m=−∞

Hid (z) = kz−D

sin[π (n − D)]

y[n] = x[n] ∗ hid [n] = x[n] ∗ k
π (n − D)
which strictly holds only for integer values of D. The term ∞ (7)
sin[π (n − l − D)]
kz⫺D represents an ideal discrete-time delay system in the z- y[n] = k x[l]
domain, which performs the bandlimited delay operation at l=−∞
π (n − l − D)
the specified sampling rate.
As the specifications are usually given in the frequency do-
that is, input samples spread over all the discrete-time values
main, it is interesting to obtain the response frequency (Fou-
weighted by appropriate values of the sinc function. Results
rier transform) of the ideal delaying system we are concerned
obtained in Eq. (7) have important consequences: ideal frac-
with. It is determined from Eq. (4) by setting z ⫽ ej웆, where
tional delays are impossible to implement and any system in-
웆 ⫽ 2앟f T is the normalized angular frequency, which give us
tending to do an emulation of this delay must be alike to the
Hid(ej웆) ⫽ ke⫺j웆D. This system has constant magnitude re-
ideal response in some meaningful sense. Ideal fractional de-
sponse, linear phase, and constant group delay:
lays can be approached by using finite-order causal FIR or
|Hid ( jω)| = k constant IIR filters. An excellent tutorial on fractional delays can be
id (ω) = −ωD linear with ω, |ω| < π found in Ref. 20.
∂
τg (ω) = − id (ω) = D constant in the whole frequency
∂ω
band Unit Delay Circuits

with periodicity 2앟 in 웆 assumed.
The inverse Fourier transform of Hid(e j웆) is the impulse re-
sponse. In case of a delay D taking an integer value, the im-
pulse response is a single impulse at n ⫽ D: that is, hid[n] ⫽
k웃[n ⫺ D], where 웃[ ⭈ ] is the Kronecker delta function. The
system simply shifts (and scales by k) the input sequence by
D samples:
y[n] = x[n] ∗ hid [n] = x[n] ∗ kδ[n − D] = kx[n − D] (5)
When D is a noninteger value, appropriate values of y[n] on
the sampling grid must be found via bandlimited interpola-
tion. This problem has a straightforward interpretation as a
resampling process: the desired solution can be obtained by
first reconstructing the bandlimited signal, shifting it, and
finally resampling it.
To obtain the impulse response corresponding to a system
able to give us the frequency response required, we use the
inverse discrete-time Fourier transform:

π
1
hid [n] = H (e jω )e jωn dω for all n
2π −π id

π
k
hid [n] = e− jωD e jωn dω
2π −π
This section is mainly devoted to the implementation of the
z⫺1 term, identified in the previous section with the bandlim-
ited unit delay operation at the sampling rate we are inter-
ested in. This term is a basic block in the realization of any
discrete delay. In the case of integer delays, z⫺N can be imple-
mented by cascading N unit delay elements. In case of a frac-
tionary delay, this must be approximated by a filter whose
realization also needs these integer delays (besides arithme-
tic elements).
Analogous to the continuous-time case, approximations to
the implementation of the z⫺1 term depend on the type of ap-
plication we are interested in. Thus, digital and analog ap-
proximations will be treated separately.
Digital Implementations. Delays are realized using digital
storage devices or memory cells to store data during a sam-
pling period. There are different ways of implementing these
delay operators depending on both architectural and circuit
choices.
From an architectural point of view, a widely used ap-
proach for implement a delay line of N clock cycles employs a
shift register. A shift register is a linear array of storage de-
vices, such as flip-flops or latches, with the capability of exe-
134 DELAY CIRCUITS
Din .... Out
1D 1D 1D 1D
C1 C1 C1 C1
φ Q retains its previous value stored in the output capacitor,
(a)
Din 1D 1D 1D 1D
.... 1D 1D Out
C1 C1 C1 C1 C1 C1
φ1
φ2
(b)
Figure 6. Implementation of z⫺N with shift register: (a) one-phase
clock; (b) two-phase clock.
cuting right shifts of one position. Figure 6 shows shift regis-
ter structures for different clocking strategies. The one in Fig.
6(a), employs flip-flops as basic units in a one-phase clock
scheme. In Fig. 6(b), the architecture when using a two-phase
clock scheme and latches is shown. Data present at the Din
input of the registers (Fig. 6) will be available in the output
OUT after N cycles and so OUT[n] ⫽ Din[n ⫺ N] as required.
We briefly summarize the different available approaches
to the circuit realization of memory cells. An excellent treat-
ment can be found in Ref. 21. The memory cells can be imple-
mented as static or dynamic circuits. The first approach uses
positive feedback or regeneration. That is, one or more output
signals are connected to the inputs. A second approach uses
charge storage as a means of storing signal values. This ap-
proach, which is very popular in MOS designs, has the disad-
vantage that the charge tends to leak away in time. Thus,
there are restrictions on the sampling frequency used: it must
be high enough so that the state is not lost. Figure 7 shows
several CMOS memory cells suitable for register architec-
tures. Note that flip-flops suitable for one-phase register ar-
chitectures can be realized by cascading two latches operating
on complementary clocks, in what is called a master–slave
configuration.
The circuit depicted in Fig. 7(a) is a static latch. It consists
of a cross-coupled inverter pair. The extra transistors are
used to store the value of Din when the clock ␾ is high. Let us
consider the case when Q is high and D is zero: in this situa-
tion with ␾ high, and the appropriate sizing of transistors
M1, M2, and M3, Q is brought below the threshold of the in-
verter M5 –M8. Then, the positive feedback forces Q to be zero.
Although these latches have reduced noise margins and re-
quire careful design, they are small and can be very fast.
In Fig. 7(b) a pseudostatic latch is shown. The feedback
loop is closed when ␾ is high. In this mode, the circuit be-
haves as a biestable element. When the clock ␾ goes high, the
loop opens and the input value is stored in the internal capac-
itor. It is called pseudostatic because frequently ␾1 and ␾2, as
shown in the figure, are used to control the pass transistors in
order to avoid overlapping of both phases even if clock routing
delays occur. During ␾12 the circuit employs dynamic storage.
A fully dynamic approach is less complex, as illustrated in
Fig. 7(c). Only three transistors are required to implement a
latch. Possible variants for circuits in Figs. 7(b) and 7(c) in-
clude using complementary transmission gates instead of
NMOS pass transistors. Also, versions of these latches can be
built adding level-restoring devices, as illustrated in Fig. 7(d).
Figure 7(e) shows the C2MOS latch. This circuit operates
in two modes. With ␾ high, it is in the evaluation mode be-
cause it acts as an inverter (transistors M3 and M4 are ON).
With ␾ low it is in the hold or high-impedance mode and so
CL. This structure presents advantages over both the pseu-
dostatic and the fully dynamic latches. These two require the
availability of two nonoverlapping clocks (four if complemen-
tary transmission gates are used) for correct operation of a
cascaded configuration. Ensuring the nonoverlapping condi-
tion might involve making ␾12 large, which has a negative
impact on circuit performance, or generating the required
clocks locally, which increases area. The operation of a cas-
caded pair of C2MOS latches controlled by ␾1 and ␾2, respec-
tively, is insensitive to overlap as long as the rise and fall
times of the clock edges are small enough. The C2MOS latch
is useful for high speed as, in that case, it is hard to avoid
clock overlap.
Finally, memory elements with a single clock have also
been proposed. Figure 7(f) shows a single clock version of the
circuit depicted in Fig. 7(e). With ␾ high, it corresponds to a
cascade of two inverters and so it is transparent. With ␾ low,
no signal can propagate from its input to its output. This cir-
cuit is called a true single-phase clock latch (TSPC latch) and
is the basis for the TSPC logic design methodology. Figure
7(g) depicts a positive edge-triggered flip-flop built using p
versions of the TSPC latch in Fig. 7(f).
Another approach to implement a delay line is based on
a multiport random access memory (RAM) which is used to
simulate a shift register. The selection of the most convenient
technique (shift-register or multiport RAM memory) depends
on the application.
Analog Implementations. We must essentially consider two
approaches to analog discrete-time signal processing:
switched-capacitor (SC) and switched-current (SI) techniques.
Switched-capacitor techniques are extensively used in mixed-
mode designs and SC delay-stages circuits have found appli-
cations in the implementation of sampled analog filters based
on digital filter architectures as well as in the realization of
interpolators and decimators. The high-quality capacitors
needed are generally implemented using two polysilicon lay-
ers. Recently, the SI technique has appeared as an alternative
to SC techniques that is fully compatible with digital CMOS
standard processes. More details about these techniques can
be found in Refs. 22 and 23.
Switched-Capacitor Techniques. If SC techniques are em-
ployed, delay elements can be realized in a simple way: by
cascading two sample-and-hold (S/H) elements provided there
are complementary clocking phases. If the output is sampled
at the clock phase ␾1 and the input signal at the beginning of
the phase ␾1, then it is possible to use only one S/H element.
Figure 8(a) shows the simplest configuration of an S/H ele-
ment in which a voltage signal vin is sampled and held in a
linear capacitor Ch through the switch controlled by clock ␾.
Noise and unbalanced charge injection are the major sources
of error in this configuration, and some compensatory tech-
niques can be employed to reduce the switch-induced error.
The signal source can be isolated from the capacitor load
by using an op-amp as a voltage follower. Avoiding any
loading of the holding capacitor by an output circuit can be
realized in a similar way. Configurations following this idea
are sensitive to the offset voltages of the amplifiers. A feed-
 DELAY CIRCUITS 135

M5 M1

Q
Q

φ M6 M2 φ
M8 M4

Din M7 M3

(a)

Din Q φ1

φ2
φ φ 12
(b)
φ

M2

φ M4
Din Q Din Q Din Q

φ M3 CL
φ φ

M1
(c) (d) (e)

φ
Q Q

Din φ φ φ
φ
Din

(f) (g)

Figure 7. CMOS memory cells suitable for register architectures: (a) Static latch; (b) pseu-
dostatic latch; (c) fully dynamic latch; (d) fully dynamic latch with level restoring device; (e)
C2MOS; (f) TSPC latch; (g) positive edge-triggered TSPC flip-flop.

back loop around the hold capacitors can be used to reduce
this offset error, as shown in Fig. 8(b), where offset and
common mode error of the output follower are reduced by
the gain of the first op-amp. However, the offset of the first
op-amp appears at the output. Further improvements in
both speed and accuracy are obtained in the configuration
shown in Fig. 8(c), when the second op-amp is connected
as an integrator.
Figure 8(d) shows a configuration with an autozeroing fea-
ture which can be used to solve the problems related with the
offset voltage. This S/H circuit also has unity-gain and is off-
set free and parasitic capacitance insensitive. Another inter-
136 DELAY CIRCUITS

R φ Vout – Vout
+1 φ φ Ch
– + +
+ Vin + Vin – –
Vin + Vout
– Ch Ch

(a) (b) (c)

φ
φ φ
φ
φ Ch Ch2
–
φ V Vin φ φ φ V
out out
Vin A – +
+
Voff A=1–ε
+ Ch1
– Voff
Cs

(d) (e)

φ1 φ1

φ2 φ2

C1 CF φ1 φ1 C1 CF φ1
φ1 φ2
φ2 –
–
Vin A Vin A
+ Vout + Vout
φ2 φ2

C2 = C1 + CF
φ1
(f)
(g)

Figure 8. Switch capacitor configurations: (a) Elementary sample-and-hold (S/H) element; (b)
S/H amplifier configuration with feedback loop; (c) S/H amplifier configuration with integrator;
(d) offset and parasitic free unity gain S/H stage; (e) offset- and gain-compensated unity gain
S/H stage; (f) basic configuration S/H gain stage; (g) switch-induced error compensated S/H
gain stage.

esting configuration is shown in Fig. 8(e), where the voltage
amplifier has approximate unity-gain (⑀ denotes the gain er-
ror) and an auxiliary hold capacitor Ch2 is used to provide
compensation of the gain and the offset voltage of the ampli-
fier. Both structures use a technique usually known as corre-
lated double sampling (CDS): the offset voltage of the op-amp
is measured in one of the clock phases, stored in the capaci-
tors, and then substracted in the subsequent signal amplifi-
cation clock phase. This technique eliminates the offset volt-
age and additionally reduces the low-frequency 1/f noise and
the power supply noise. Switch-induced errors and other par-
asitic effects such as power supply noise and common-mode
signals can be drastically reduced by employing fully differen-
tial configurations.
These configurations provide unity gain. If an S/H stage
with arbitrary positive gain is required, we can resort to the
circuit shown in Fig. 8(f), which also uses the CDS technique.
Assuming there is an infinity op-amp gain, the circuit opera-
tion is as follows: During clock phase ␾1, it operates as a
unity-gain voltage follower (both inverting input and output
are short circuited). Capacitors CF and C1 are charged to the
offset voltage and to the input voltage minus the offset volt-
age, respectively. Next, during clock phase ␾2, the capacitor
C1 is discharged through CF, giving an output voltage which
is independent of the op-amp input offset voltage. Improve-
ments in eliminating the switch-induced voltage error at the
expense of doubling the total amount of required capacitance
can be obtained with the configuration shown in Fig. 8(g),
where CDS technique has been again applied. It adds an ap-
propriate network (capacitor C2 and switch controlled by ␾1)
to the noninverting input of the op-amps in order to cancel
the signal injected at the inverting terminal by the clock feed-
through. However, a switch-induced voltage error remains,
which is determined by the mismatching of the switches and
capacitors and the common mode rejection ratio (CMRR) of
the op-amp.
To obtain an analog delay line of N clock periods we only
need to connect in cascade N delay elements. The cascading
of delay elements transfers errors due to such effects as gain
mismatch, offset voltage, or clock feedthrough from stage to
stage, accumulating them and limiting the maximum possible
number of S/H stages in the cascade.
Another approach employs a parallel of N S/H elements
rather than a cascade implementation, as shown in Fig. 9.
It is composed of N channels, each one containing an S/H
stage with a unity gain buffer and an array of switches
controlled by the clock sequence shown in the figure. The
S/H stages sequentially sample the input signal and hold
 DELAY CIRCUITS 137

vin(nτ) φ1 φ1
+ 1 vin(nτ)
– φ2
vin(nτ – τ)
φ1 C1 φ3
. . vin(nτ – 2τ)
. φN .
. .
vin(nτ – (N – 1)τ)
φ2 φ1
1
φ2
φ2 C2 φ3 ...
.
. φN
.

. φ1
.
. φ2
τ
φN φ1 φ3
1
φ2
φN CN φ3 φN
.
. φN Figure 9. SC delay line and clock sequence
.
controlling it.

it for the next N clock cycles: thus, the errors are added
only once. Errors caused by the unity gain buffer are mini-
mized by connecting the S/H stages in a feedback loop of
a single time-sharing op-amp. Errors in the S/H stages are
greatly reduced because they are divided by the gain of the
op-amp. Errors due to the offset voltage and the finite gain
of the op-amp are not compensated but they likewise affect
all the outputs.
Switched-Current Techniques. In SI techniques, delay ele-
ments are simply made by cascading memory cells. Topologies
used for delay elements are included in one of two categories:
the current-mode track-and-hold (T/H) and the dynamic cur-
rent mirror. The current-mode T/H delay is shown in Fig.
10(a). A digital clock signal switches ON and OFF switch S,
which, when ON, shorts the gates of transistors T1 and T2,
and the circuit functions as a current mirror: with an input
iin applied to the drain of T1, the output iout tracks such input
current. When the switch is turned off, the gates of T1 and
T2 are disconnected, and the gate voltage of T1, corresponding
to the input current value in this moment, is sampled on
Cgs2. Voltage Vgs2 remains constant while the switch is open,
and so the output current is held at a constant value which
is the input current value in the instant when the switch
was opened.
An important drawback of this circuit refers to the exact
reproduction of the input current at the output: it depends
on the matching of the two transistors T1 and T2 and the
two bias current sources J1 and J2. This disadvantage is
solved by the second generation of memory cells, the dy-
namic current mirror or current copier, by using only one
transistor for both input and output of current, as ex-
plained in the following.
The conventional SI memory cell is shown in Fig. 10(b). It
can achieve current memory in the transistor T1 when driven
by the clock waveforms of Fig. 10(c). Its operation is as fol-
lows: on phase ␾1, switch S1 is closed and current iin adds to
the bias current J flowing into the circuit. Current J ⫹ iin
begins to charge the initially discharged capacitor Cgs1. As
Cgs1 charges, the gate-source voltage Vgs of T1 increases and
when it exceeds its threshold voltage, T1 conducts. Eventu-
ally, when Cgs1 is fully charged, all of the current J ⫹ iin flows
in the drain of T1. On phase ␾2, switch S1 is opened and the
end value of Vgs when ␾1 finishes is held on capacitor Cgs1 and
it sustains the current J ⫹ iin flowing in the drain of T1. As
the input switch is open and the output one closed, there is a
current imbalance which forces an output current, iout ⫽ ⫺iin,
to flow throughout phase ␾2.
A delay cell comprises two cascaded current memory cells
with the phase reversed on alternate memory cells. A delay
line of N clock periods could be generated by cascading N de-
lay cells (2N memory cells), as shown in Fig. 10(d). Another
approach uses an array of N ⫹ 1 memory cells in parallel, as
shown in Fig. 10(e). By using the clock sequence shown in the
figure, on clock phase ␾i, memory cell Mi acquires the input
current and memory cell Mi⫹1 releases its output, for i ⫽ 0,
. . ., N ⫺ 1. On phase ␾N, cell MN receives its input signal
and cell M0 delivers its output.
Actual operation of the basic memory cell deviates from
the ideal behavior due to transistor nonidealities which de-
grade the performance of the cell. Previous structures for the
delay line inherit these problems: if the memory cell has
transmission errors (which occur through conductance ratio
errors and charge injection errors) or signal-to-noise ratio er-
rors, then the serial solution increases both by a factor of
2N; in the other solution, errors are the same as those of the
memory cell, but two extra problems arising from the parallel
nature of the structure can be found. One problem comes from
unequal path gains and the other from nonuniform sampling.
The degree of importance of both problems is different: very
close path gains are obtained as transmission accuracy is not
achieved by component matching. Nonuniform sampling
could be carefully considered if the cell is used for the sample
and hold function. An additional drawback of that structure
results from leakage which discharges Cgs during the N clocks
between sampling and output.
Some of these error sources can be controlled by a precise
choice of transistor sizes and currents, in particular those
coming from mismatching, charge injection, conductance ra-
138 DELAY CIRCUITS

Vdd Vdd Vdd

J
φ2
J1 J2
φ1
iin iout iin iout

φ1 φ1 S1 φ1
T1 T2
S T1 φ2
Cgs2 Cgs1
T

(a) (b) (c)

Unit delay #1 Unit delay #N

J J J J
φ2 φ2
φ1 φ1 φ1
iin iout

φ1 φ2 φ1 φ2

M11 M12 MN1 MN2

(d)

Vdd

J J J
φ0 φN

φ1 φ0

iin iout
φN φN – 1

φ0

φ0 φ1 φN
φ1

φN T
M0 M1 MN

(e)

Figure 10. Switch current (SC) configurations: (a) Track-and-hold delay; (b) memory cell with
a single transistor; (c) clock waveforms; (d) serial delay line; (e) parallel delay line.

tios, settling, and noise. However, if we are interested in
achieving a performance in terms of precision, dynamic range,
and linearity, which is competitive with state-of-the-art SC
circuits, a different approach must be taken by resorting to
circuit techniques.
At present, main circuit techniques use either negative
feedback techniques or fully differential structures. Feedback
techniques are specially indicated to reduce conductance ratio
errors and increase dynamic range. Two groups can be consid-
ered depending on how negative feedback is applied in the
memory cell. The first one includes the op-amp and the
grounded-gate active memory cells, which use feedback to in-
crease the input conductance by the creation of a virtual earth
at the input. Op-amp option can make monotonic settling dif-
ficult to achieve, and this behavior is improved if the op-amp
is substituted by a grounded-gate amplifier. Conductance er-
ror improvement is similar but the dynamic range is a little
better than that of the basic memory cell. In the second group,
negative feedback is used to decrease the output conductance.
Monotonic settling is also achieved in simple and folded cas-
codes, but it may be necessary to use of compensation in regu-
lated cascode memory cells. More details can be found in
Ref. 22.
Fully differential structures are able to reduce errors com-
ing from charge injection and improve noise immunity. Com-
pared with basic cells of the same supply voltage and current,
much lower charge injection errors and similar bandwidth,
dynamic range, and chip area are obtained with fully differen-
tial cells designed with half-width transistors. Additionally,
any of the cascode variations previously cited may be used
with this approach.
Finally, if quiescent power consumption is a basic concern,
then the class AB SI technique can be indicated, because an
important reduction of it is obtained. Additionally, delay cells
using class AB memory cells are generated without duplicat-
ing the entire cell; instead the output of the first stage is sim-
ply cross-coupled to a second stage of memory cells. Simula-
tion results in some applications have shown how charge
injection can produce significant errors.
BIBLIOGRAPHY
1. K. Bult and H. Wallinga, A CMOS analog continuous-time delay
line with adaptative delay-time control, IEEE J. Solid-State Cir-
cuits, 23: 759–766, 1988.
2. C. Mead, Analog VLSI and Neural Systems, Reading, MA: Addi-
son-Wesley, 1989.
3. S. Unger, The Essence of Logic Circuits, 2nd ed., Piscataway, NJ:
IEEE Press, 1997.
4. R. Feldman and D. Rosky, A step-by-step guide to programmable
delays, Electron. Design, 39: 97–98, 100, 102–104, 107, 1991.
5. G. C. Moyer et al., The delay vernier pattern generation tech-
nique, IEEE J. Solid-State Circuits, 32: 551–562, 1997.
6. T. E. Rahkonen and J. T. Kostamovaara, The use of stabilized
CMOS delay lines for the digitization of short time intervals,
IEEE J. Solid-State Circuits, 28: 887–894, 1993.
7. S.-Ch. Liu and C. Mead, Continuous-time adaptive delay system,
IEEE Trans. Circuits Syst. II: Analog and Digital Signal Proc-
essing, 43: 744–751, 1996.
8. M. Bazes, A novel precision MOS synchronous delay line, IEEE
J. Solid-State Circuits, 20: 1265–1271, 1985.
DELAY SYSTEMS 139
9. M. G. Johnson and E. L. Hudson, A variable delay line PLL for
CPU-coprocessor synchronization, IEEE J. Solid-State Circuits,
23: 1218–1223, 1988.
10. M. Bazes, R. Ashuri, and E. Knoll, An interpolating clock synthe-
sizer, IEEE J. Solid-State Circuits, 31: 1295–1301, 1996.
11. D. K. Jeong et al., Design of PLL-based clock generation circuits,
IEEE J. Solid-State Circuits, 22: 255–261, 1987.
12. J. Christiansen, An integrated high resolution CMOS timing gen-
erator based on an array of delay locked loops, IEEE J. Solid-
State Circuits, 31: 952–957, 1996.
13. J. G. Maneatis, Low-jitter process-independent DLL and PLL
based on self-biased techniques, IEEE J. Solid-State Circuits, 31:
1723–1732, 1996.
14. M. Mizuno et al., A GHz MOS adaptive pipeline technique using
MOS current-mode logic, IEEE J. Solid-State Circuits, 31: 784–
791, 1996.
15. I. A. Young, J. K. Greason, and K. L. Wong, A PLL clock genera-
tor with 5 to 110 MHz of lock range for microprocessors, IEEE J.
Solid-State Circuits, 27: 1599–1607, 1992.
16. B. Razavi, Design of monolithic phase-locked loops and clock re-
covery circuits—A tutorial, in B. Razavi (ed.), Monolithic Phase-
Locked Loops and Clock Recovery Circuits: Theory and Design,
Piscataway, NJ: IEEE Press, 1996.
17. Y. Watanabe et al., A new CR-delay circuit technology for high-
density and high-speed DRAMs, IEEE J. Solid-State Circuits, 24:
905–910, 1989.
18. T. Tanzawa and T. Tanaka, A stable programming pulse genera-
tor for single power supply flash memories, IEEE J. Solid-State
Circuits, 32: 845–851, 1997.
19. J. G. Manneatis and M. Horowitz, Precise delay generation using
coupled oscillators, IEEE J. Solid-State Circuits, 28: 1273–1282,
1993.
20. T. I. Laakso et al., Splitting the unit delay, IEEE Signal Process.
Mag., 13: 30–60, 1996.
21. J. M. Rabaey, Digital Integrated Circuits: A Design Perspective,
Upper Saddle River, NJ: Prentice-Hall, 1996.
22. C. Tomazou, J. B. Hughes, and N. C. Battersby (eds.), Switched-
Currents, An Analogue Technique for Digital Technology, London:
Peregrinus, 1993.
23. R. Unbenhauen and A. Cichocki, MOS Switched-Capacitor and
Continuous-Time Integrated Circuits and Systems, Berlin:
Springer-Verlag, 1989.
JOSÉ M. QUINTANA
MARÍA J. AVEDILLO
Universidad de Sevilla
DELAY LINE. See DELAY CIRCUITS; PHASE SHIFTERS.
DELAYS. See CLOCK DISTRIBUTION IN SYNCHRONOUS
SYSTEMS.
378 DIFFERENTIAL AMPLIFIERS

DIFFERENTIAL AMPLIFIERS
AMPLIFICATION OF DIFFERENCE AND DC SIGNALS

Differential amplifiers represent a class of amplifiers, which

amplify the difference between two signals, including dc. To
obtain their desired characteristics, differential amplifiers
critically depend on component matching. Therefore, discrete
realizations, based on vacuum tubes or transistors, necessi-
tate careful component pairing, which is not just painstaking
for the design engineer, but also significantly raises the am-
plifier’s cost. In contrast, integrated circuit technology with
its inherent small relative component tolerances is particu-
larly suited for this application.
It is a well-known fact that the active elements used for
amplification are far from linear devices. To circumvent the
problems associated with the nonlinear input–output rela-
tionship, the amplifier circuit in a typical application is lin-
earized through the selection of a suitable operating point. An
example of an elementary single-stage amplifier is shown in
Fig. 1. While the circuit includes a bipolar transistor, it can
readily be adapted to MOS technology, or even vacuum tubes.
In Fig. 1, the input bias and dc level at the output are sepa-
rated from the desired input–output signals by means of cou-
pling capacitors Cci and Cco. The role of the emitter degenera-
tion resistor RO is to reduce the drift of the operating point.
Further, the decoupling capacitor CO counteracts the gain re-
duction associated with the insertion of RO. Obviously, the
presence of coupling and decoupling capacitors makes the cir-
cuit in Fig. 1 unsuitable for dc amplification. But, even at
low frequencies this amplifier is impractical, due to the large
capacitor values required, which, in turn, give rise to large
RC time constants and, consequently, slow recovery times
from any transient disturbances.
The requirement to avoid capacitors in low-frequency or dc
amplifiers leads to a mixing of the concepts of bias and signal.

VCC

RL

Vo
CCO
CCi
Vi

RO CO

Figure 1. Single-transistor amplifier.

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.
 DIFFERENTIAL AMPLIFIERS 379

through a combination of careful device matching, precise se-

lection of the amplifier’s bias and operating point, as well as
V1 A1 V3 V4 A2 V2
by a high common-mode rejection. While we have only consid-
ered differential output signals up to this point, in some in-
stances a single-ended output is desired. Equations (5) and
(6) can be rearranged as

1

1 1


Figure 2. Conceptual drawing of a differential amplifier. V3 = VoC + V = ACD + ADD ViD + ACC + ADC ViC
2 oD 2 2
(7)
A second characteristic of such amplifiers is the application of 1

1 1


symmetry to compensate for the drift of the active compo- V4 = VoC − V = ACD − ADD ViD + ACC − ADC ViC
2 oD 2 2
nents. An intuitive solution appears to lie in the use of two (8)
amplifiers, connected in a difference configuration, as illus-
trated in Fig. 2. For this circuit one can write the following One concludes that in the single-ended case all three ratios
equations: ADD /ACC, ADD /ACD, and ADD /ADC must be high, to yield the de-
sired result.
V3 = A1V1 (1)
Vacuum-tube-based differential circuits are not discussed
V4 = A2V2 (2) in this article, which is devoted solely to mainstream inte-
grated circuit technology, more specifically, bipolar junction
Assuming A1 approximately equal to A2, that is, A1 ⫽ A ⫹ ⌬/ and MOS field effect transistors. The next section provides an
2 and A2 ⫽ A ⫺ ⌬/2, yields in-depth analysis of the bipolar version of the differential
pair, also known as the emitter-coupled pair. The subsequent

V3 − V4 = A(V1 − V2 ) + (V + V2 ) (3) treatment of the MOS source-coupled pair adheres to a simi-
2 1 lar outline, with an emphasis on similarities, as well as im-
portant differences.
V3 + V4 = A(V1 + V2 ) + (V1 − V2 ) (4)
2

Clearly, when both amplifiers are perfectly matched or ⌬ ⫽ 0, BIPOLAR DIFFERENTIAL PAIRS (EMITTER-COUPLED PAIRS)
the difference mode is completely separated from the sum
mode. Upon further reflection, though, the difference ampli- Figure 3 depicts the basic circuit diagram of a bipolar differ-
fier of Fig. 2 is not really the solution to the amplification ential pair. A differential signal ViD is applied between the
problem under consideration. Indeed, in many instances, bases of two transistors, which, unless otherwise noted, are
small signals, which sit on top of large pedestal voltages, need assumed to be identical. The dc bias voltage Vbias and a com-
to be amplified. For example, assume A ⫽ 100, a difference mon-mode signal ViC are also present. The transistors’ com-
signal of 10 mV and a bias voltage equal to 10 V. The ampli- mon emitter node is connected to ground through a biasing
fier scheme of Fig. 2 would result in a 1 V difference signal,
in addition to a 1000 V output voltage common to both ampli-
fiers. It is clearly unrealistic to assume that both amplifiers VCC
will remain linear and matched over such extended voltage
range. Instead, the real solution is obtained by coupling the
amplifiers. The resulting arrangement is known as the differ-
ential pair amplifier.
In the mathematical description of the differential pair, IC1 RL RL IC2
four amplification factors are generally defined to express the + –
relationship between the differential or difference (subscript VO
D) and common or sum mode (subscript C) input and output
signals. Applied to the circuit in Fig. 2, one can write
Q1 Q2
V3 − V4 = VoD = ADDViD + ADCViC (5)
V3 + V4 = 2VoC = 2ACCViC + 2ACDViD (6) ViD

where ViD ⫽ V1 ⫺ V2 and ViC ⫽ (V1 ⫹ V2)/2. The ratio ADD /ACC
is commonly referred to as the amplifier’s common-mode re- ViC
jection ratio or CMRR. While an amplifier’s CMRR is an im-
portant characteristic, maximizing its value is not a design- IEE RO
+
er’s goal, in itself. Rather, the real purpose is to suppress Vbias
–
large sum signals, so that the two amplifiers exhibit a small
output swing and, thereby, operate indeed as a matched pair.
Furthermore, the ultimate goal is to avoid that the applica-
tion of a common-mode input signal results in a differential
signal at the output. This objective can only be accomplished Figure 3. Bipolar differential pair (emitter-coupled pair).
380 DIFFERENTIAL AMPLIFIERS

network, which, for simplicity, is represented by a single re- two transistors is almost completely cut off and for further
sistor RO. The amplifier output is taken differentially across increases in ViD the differential output signal eventually clips
the two collectors, which are tied to the power supply VCC, at ⫺움RLIEE. On the other hand, for small values of x, tanh
by means of a matched pair of load resistors RL. x 앒 x. Under this small-signal assumption,

Low-Frequency Large-Signal Analysis VoD αI

ADD = = − EE RL = −gm RL (13)
ViD 2VT
Applying the bipolar transistor’s Ebers–Moll relationship
with Vbe Ⰷ VT (where VT ⫽ kT/q is the thermal voltage) and
While the next subsection contains a more rigorous
assuming that both transistors are matched (i.e., the satura-
small-signal analysis, a noteworthy observation here is that,
tion currents IS1 ⫽ IS2), the difference voltage ViD can be ex-
under conditions of equal power dissipation, the differential
pressed as follows:
amplifier of Fig. 3 has only one-half the transconductance

I  value and, hence, only one-half the gain of a single transis-
ViD = Vbe1 − Vbe2 = VT ln C1
(9) tor amplifier. From Eq. (13) one furthermore concludes that,
IC2
when the tail current IEE is derived from a voltage source,
which is proportional to absolute temperature (PTAT), and
After some manipulation and substituting IC1 ⫹ IC2 ⫽ 움IEE (the a resistor of the same type as RL, the transistor pair’s
total current flowing through RO), one gets differential gain is determined solely by a resistor ratio. As
such, the gain is well controlled and insensitive to absolute
αIEE
IC1 =
−V  (10) process variations.
1 + exp iD An intuitive analysis of the common-mode gain can be car-
VT ried out under the assumption that RO is large (for example,
αIEE assume RO represents the output resistance of a current
IC2 =
V  (11) source). Then, a common-mode input signal ViC results only
1 + exp iD
in a small current change iC through RO and, therefore, Vbe
VT
remains approximately constant. With iC 앒 ViC /RO and VoC ⫽
⫺RLiC /2, the common-mode gain can be expressed as
where 움 is defined as 웁/(웁 ⫹ 1).
Since VoD ⫽ ⫺RL(IC1 ⫺ IC2), the expression for the differen- VoC R
tial output voltage VoD becomes ACC = ≈− L (14)
ViC 2RO

V 
−V 
exp iD
− exp iD
Combining Eqs. (13) and (14) yields
VoD = −αRL IEE
2VT
ViD

−V
2VT

exp + exp iD
(12) ADD
2V 2VT CMRR = ≈ 2gm RO (15)

VT  ACC
= −αRL IEE tanh iD
= −αRL IEE tanh x
2VT
Half Circuit Equivalents
From Eq. (12) one observes that the transfer function is quite Figure 4 illustrates the derivation of the common-emitter cir-
non-linear. When ViD ⬎ 2VT, the current through one of the cuit’s differential mode half circuit equivalent representation.

VCC
VCC VCC

RL RL RL RL

+ –
VoD
VoD/2 –VoD/2
+

ViD ViD/2 –ViD/2

Difference mode
Figure 4. Derivation of the emitter-coupled pair’s half circuit equivalent for difference signals.
 DIFFERENTIAL AMPLIFIERS 381

VCC
VCC VCC

RL RL RL RL
+

VoC
VoC VoC
–

ViC ViC

+
ViC 2RO 2RO 2RO 2RO

Sum mode
Figure 5. Derivation of the emitter-coupled pair’s half circuit equivalent for common-mode
signals.

For a small differential signal, the sum of the currents The combination of Eqs. (16) and (17) leads to
through both transistors remains constant and the current
through RO is unchanged. Therefore, the voltage at the emit- ADD rπ + rb + 2RSC + 2(β + 1)RO
CMRR = = ≈ 2gm RO (18)
ters remains constant. The transistors operate as if no degen- ACC 1
rπ + rb + RSD
eration resistor were present, resulting in a high gain. In sum 2
mode, on the other hand, the common resistor Ro provides
Consider the special case where RO models the output re-
negative feedback, which significantly lowers the common-
sistance of a current source, implemented by a single bipolar
mode gain. In fact, with identical signals at both inputs, the
transistor. Then, RO ⫽ VA /IEE, where VA is the transistor’s
symmetrical circuit can be split into two halves, each with a
Early voltage. With gm ⫽ 움IEE /2VT,
degeneration resistor 2RO, as depicted in Fig. 5.
αVA
CMRR = (19)
Low-Frequency Small-Signal Analysis VT
Figure 6 represents the low-frequency small-signal differen-
which is independent of the amplifier’s bias conditions, but
tial mode equivalent circuit wherein RSD models the corre-
only depends on the process technology and temperature. At
sponding source impedance. Under the presumption of room temperature, with 움 앒 1 and VA 앒 25 V, the amplifier’s
matched devices, CMRR is approximately 60 dB. The use of an improved cur-
rent source, for example, a bipolar transistor in series with
VoD rπ
ADD = = −gm RL (16) an emitter degeneration resistor RD, can significantly increase
ViD 1
rπ + rb + R the CMRR. More specifically,
2 SD
αVA

IEE RD

CMRR = 1+ (20)
With rb Ⰶ r앟 and assuming a low-impedance voltage source, VT VT
Eq. (14) can be simplified to ⫺gmRL as was previously derived
in Eq. (13). The low-frequency common-mode equivalent cir- For IEERD ⫽ 250 mV, the CMRR in Eq. (20) is eleven times
cuit is shown in Fig. 7. Under similar assumptions as in Eq. higher than in Eq. (19).
(16) and with RSC representing the common-mode source im- In addition to expressions for the gain, the emitter-coupled
pedance, one finds pair’s differential and common-mode input resistances can
readily be derived from the small-signal circuits in Figs. 6
VoC rπ and 7.
ACC = = −gm RL (17)
ViC rπ + rb + 2RSC + 2(β + 1)RO
RinD = 2rπ (21)

Upon substitution of 웁 ⫽ gmr앟 Ⰷ 1, Eq. (17) reduces to 1

RinC = rπ + RO (β + 1) (22)
⫺RL /2RO, the intuitive result obtained earlier in Eq. (14). 2
382 DIFFERENTIAL AMPLIFIERS

i RL
i1 RL RL i2

VoD VOD /2
rb1 rb2 rb
gm1vπ 1 gm2vπ 2 gm2vπ

rπ 1 vπ 1 rπ 2 vπ 2 rπ vπ

ViD ViD /2

RO (replaced by short circuit)

RSD RSD /2

Difference mode
Figure 6. Differential mode small-signal equivalent circuit for the emitter-coupled pair. The
complete circuit is on the left and the half circuit equivalent is on the right.

Taking into account the thermal noise of the transistors’ base hybrid-앟 small-signal model in Fig. 6, the differential gain
resistances and the load resistors RL, as well as the shot noise transfer function becomes frequency dependent. With Ri rep-
caused by the collector currents, the emitter-coupled pair’s to- resenting the parallel combination of (RsD /2 ⫹ rb) with r앟, and
tal input referred squared noise voltage per hertz is given by RC similarly designating the parallel combination of RL with
2
ViN 1

1
 ro, Eq. (16) must be rewritten as
= 8kT rb + + 2 (23) gm Ri RC N(s)
f 2gm g m RL ADD = − (24)
1 D(s)
R + rb
Due to the presence of base currents, there is also a small 2 sD
input noise current, which, however, will be ignored here and
in further discussions. where
sCµ
Small-Signal Frequency Response 1−
N(s) gm
= (25)
When the emitter-base capacitance C앟, the collector-base ca- D(s) 1 + s(Cπ Ri + Cµ Ri + Cµ RC + Cµ Ri RC gm + Ccs RC )
pacitance C애, the collector-substrate capacitance Ccs, and the
transistor’s output resistance ro are added to the transistor’s + s2 (Cπ Ccs Ri RC + Cπ Cµ Ri RC + CµCcs Ri RC )

i RL
i1 RL RL i2
VoC
rb1 rb2 rb

gm1vπ 1 VoC gm2vπ 2 gmvπ

rπ 1 vπ 1 rπ 2 vπ 2 rπ vπ
+

ViC
RO –

2RO
ViC 2RSc

RSC

Sum mode

Figure 7. Common-mode small-signal equivalent circuit for the emitter-coupled pair. The com-
plete circuit is on the left and the half circuit equivalent is on the right.
 DIFFERENTIAL AMPLIFIERS 383

One observes that Eq. (25) contains a right half-plane zero or

located at sz ⫽ gm /C애, resulting from the capacitive feed-
through from input to output. However, this right half-plane

R IS
 Vbe


zero is usually at a frequency sufficiently high for it to be VoO ≈− + L
RL IS exp
RL IS VT
ignored in most applications. Furthermore, in many cases,
R I  (31)
one can assume that D(s) contains a dominant pole p1 and a =− L
+ S
RL IC
RL IS
second pole p2 at a substantially higher frequency. If the dom-
inant pole assumption is valid, D(s) can be factored in the
following manner: Conversely, the output offset can be referred back to the
input through a division by the amplifier’s differential gain.



D(s) = 1−
s
1−
s
≈1−
s
+
s2
(26) VoO

R IS

p1 p2 p1 p1 p2 ViO = = VT L
+ (32)
−gm RL RL IS
Equating Eqs. (25) and (26) yields
The input referred offset voltage ViO represents the voltage,
which must be applied between the input terminals, in order
p1 = −
1
RC

1 R
 (27) to nullify the differential output voltage. In many instances,
Ri
Cπ + Ccs + Cµ 1 + gm RC + C the absolute value of the offset voltage is not important, be-
Ri Ri
RC

R
 cause it can easily be measured and canceled, either by an
auto-zero technique or by trimming. Rather, when offset com-
Cπ + Ccs + Cµ 1 + gm RC + C pensation is applied, the offset stability under varying envi-
1 Ri Ri
p2 = − ronmental conditions becomes the primary concern. The drift
RC (Cµ + Ccs ) CµCcs
Cπ + in offset voltage over temperature can be calculated by differ-
Cµ + Ccs
(28) entiating Eq. (32).

dViO V
The collector-base capacitance C애 in Eqs. (27) and (28) ap- = iO (33)
pears with a multiplication factor, which is essentially equal dT T
to the amplifier’s gain. This phenomenon is widely referred to
as the Miller effect. From Eq. (33) one concludes that the drift is proportional to
Rather than getting into a likewise detailed analysis, the the magnitude of the offset voltage, and inversely related to
discussion of the emitter-coupled pair’s common-mode fre- the change in temperature.
quency response is limited here to the effect of the unavoid-
able capacitor CO (representing, for instance, the collector- Input Offset Current. Since, in most applications, the differ-
base and collector-substrate parasitic capacitances of the ential pair is driven by a low-impedance voltage source, its
BJT), which shunts RO. The parallel combination of RO and input offset voltage is an important parameter. Alternatively,
CO yields a zero in the common-mode transfer function. Corre- the amplifier can be controlled by high-impedance current
spondingly, a pole appears in the expression for the amplifi- sources. Under this condition, the input offset current IiO,
er’s CMRR. Specifically, which originates from a mismatch in the base currents, is the
offset parameter of primary concern. Parallel to the definition
RO of ViO, IiO is the value of the current source, which must be
CMRR = 2gm (29)
1 + sCO RO placed between the amplifier’s open-circuited input terminals
to reduce the differential output voltage to zero.
The important conclusion from Eq. (29) is that at higher fre-
IC + IC I I

I β

quencies the amplifier’s CMRR rolls off by 20 dB per decade. IiO = − C ≈ C C
− (34)
β + β β β IC β

Dc Offset
The requirement of zero voltage difference across the output
Input Offset Voltage. Until now, perfect matching between terminals can be expressed as
like components has been assumed. While ratio tolerances in
integrated circuit technology can be very tightly controlled, (RL + RL )(IC + IC ) = RL IC (35)
minor random variations between ‘‘equal’’ components are un-
avoidable. These minor mismatches result in a differential
Eq. (35) can be rearranged as
output voltage, even if no differential input signal is applied.
When the two bases in Fig. 3 are tied together, but the tran-
IC RL
sistors and load resistors are slightly mismatched, the re- ≈− (36)
sulting differential output offset voltage can be expressed as IC RL

VoO = −(RL + RL )(IC + IC ) + RL IC Substituting Eq. (36) into Eq. (34) yields

V 
V 
= −(RL + RL )(IS + IS ) exp be
+ RL IS exp be
IEE

R β

VT VT IiO = − L
+ (37)
(30) 2β RL β
384 DIFFERENTIAL AMPLIFIERS
IiO’s linear dependence on the bias current and its inverse re-
lationship to the transistors’ current gain 웁, as expressed by
Eq. (37), intuitively make sense.
Gain Enhancement Techniques
From Eq. (13) one concludes that there are two ways to in-
crease the emitter-coupled pair’s gain, namely, an increase in
the bias current or the use of a larger valued load resistor.
However, practical limitations of the available supply voltage
and the corresponding limit on the allowable I ⴱ R voltage
drop across the load resistors, in order to avoid saturating
either of the two transistors, limit the maximum gain that
ViD
ViC
+
Vbias
–
Figure 8. Emitter-coupled pair with neg-
ative resistance load circuit, used to in-
crease the amplifier’s gain.
can be achieved by a single stage. This section introduces two
methods, which generally allow the realization of higher gain
without the dc bias limitations.
Negative Resistance Load. In the circuit of Fig. 8 a gain
boosting positive feedback circuit is connected between the
output terminals. The output dc bias voltage is simply deter-
mined by VCC, together with the product of RL and the
current flowing through it, which is now equal to (IE ⫹
IR)/2. However, for ac signals the added circuit, consisting
of two transistors with cross-coupled base-collector connec-
tions and the resistors RC between the emitters, represents
a negative resistance of value ⫺(RC ⫹ 1/gmc) where gmc ⫽
VCC
RL RL
+ –
VO
RC RC
IEE IR
 DIFFERENTIAL AMPLIFIERS 385

VCC

VO
+ –

RF
RF /2
RF

ViD

+
ViC VREF
–
RO IL IL IF IL
+
Vbias
–

Figure 9. Fully differential emitter-coupled pair with active current source loads and common-
mode feedback circuit.

움IR /2VT. The amplifier’s differential gain can now be expressed put terminal is similarly tied to a reference voltage VREF. The
as negative feedback provided to the pnp load transistors forces
an equilibrium state in which the dc voltage at the output
1 terminals of the differential pair gain stage are equal to
ADD ≈ −gm RL (38)
gmc RL VREF. The need for CMFB can be avoided in a single-ended
1−
1 + gmc RC implementation as shown in Fig. 10. Contrary to the low

VCC
Active Load. Another approach to increase the gain con-
sists of replacing the load resistors by active elements, such
as pnp transistors. Figure 9 shows a fully differential realiza-
tion of an emitter-coupled pair with active loads. The differen-
tial gain is determined by the product of the transconduc-
tance of the input devices and the parallel combination of the
output resistances of the npn and pnp transistors. Since
gm ⫽ IC /VT, ron ⫽ VAn /IC and rop ⫽ VAp /IC, the gain becomes VO

VAnVAp 1 VAnVAp
ADD = −gm =− (39)
(VAn + VAp )IC VT VAn + VAp

Consequently, the gain is independent of the bias conditions. ViD

The disadvantage of the fully differential realization with ac-
tive loads is that the output common-mode voltage is not well
defined. If one were to use a fixed biasing scheme for both ViC
types of transistors in Fig. 9, minor, but unavoidable mis-
matches between the currents in the npn and pnp transistors RO
will result in a significant shift of the operating point. The +
solution lies in a common-mode feedback circuit (CMFB), Vbias
–
which controls the bases of the active loads and forces a pre-
determined voltage at the output nodes. The CMFB circuit
has high gain for common-mode signals, but does not respond
to differential signals present at its inputs. A possible realiza-
tion of such CMFB circuit is seen in the right portion of Fig.
9. Via emitter followers and resistors RF, the output nodes are Figure 10. Single-ended output realization of an emitter-coupled
connected to one input of a differential pair, whose other in- pair with active loads.
386 DIFFERENTIAL AMPLIFIERS

CMRR of a single-ended realization with resistive loads, the Consequently,

circuit in Fig. 10 inherently possesses the same CMRR as a
differential realization since the output voltage depends on a g m RL
ADD ≈ − (42)
current differencing as a result of the pnp mirror configura- 1 + g m RE
tion. The drawback of the single-ended circuit is a lower fre-
quency response, particularly when low-bandwidth lateral In case gmRE Ⰷ 1,
pnp transistors are used.
RL
ADD ≈ − (43)
Linearization Techniques RE

As derived previously, the linear range of operation of the In comparison with the undegenerated differential pair,
emitter-coupled pair is limited to approximately ViD 앒 2VT. the gain is reduced by an amount gmRE, which is proportional
This section describes two techniques, which can be used to to the increase in linear input range. The common-mode gain
extend the linear range of operation. transfer function for the circuit in Fig. 11 is

Emitter Degeneration RL
ACC ≈ − (44)
2RO + RE
The most common technique to increase the linear range of
the emitter-coupled pair relies on the inclusion of emitter de-
For practical values of RE, ACC remains relatively unchanged
generation resistors, as shown in Fig. 11. The analysis of the
compared to the undegenerated prototype. As a result, the
differential gain transfer function proceeds as before, how-
amplifier’s CMRR is reduced approximately by the amount
ever, no closed-form expression can be derived. Intuitively,
gmRE. Also, the input referred squared noise voltage per Hertz
the inclusion of RE introduces negative feedback, which low-
can be derived as
ers the gain and extends the amplifier’s linear operating re-
gion to a voltage range approximately equal to the product of 2

ViN 1 1
REIE. The small-signal differential gain can be expressed as = 8kT rb + ( g2m R2E ) + 2 ( g 2m R2E ) + RE (45)
f 2 gm g m RL
ADD ≈ −GM RL (40)
This means that, to a first order, the noise too increases by
the factor gmRE. Consequently, even though the amplifier’s
where GM is the effective transconductance of the degenerated
linear input range is increased, its signal-to-noise ratio (SNR)
input stage. Therefore,
remains unchanged. To complete the discussion of the emitter
degenerated differential pair, the positive effect emitter de-
gm 1
GM = ≈ (41) generation has on the differential input resistance RinD and,
1 + g m RE RE to a lesser extent, on RinC should be mentioned. For the circuit
in Fig. 11,

RinD = 2[rπ + (β + 1)RE ] (46)

VCC
1 (β + 1)RE
RinC = rπ + + RO (β + 1) (47)
2 2

RL RL Parallel Combination of Asymmetrical Differential Pairs. A

second linearization technique consists of adding the output
+ – currents of two parallel asymmetrical differential pairs with
VO respective transistor ratios 1 : r and r : 1, as shown in Fig. 12.
The reader will observe that each differential pair in Fig. 12
is biased by a current source of magnitude IEE /2, so that the
RE RE power dissipation, as well as the output common-mode volt-
ViD
age, remain the same as for the prototype circuit in Fig. 3.
Assuming, as before, an ideal exponential input voltage–
output current relationship for the bipolar transistors, the fol-
ViC
lowing voltage transfer function can be derived:
RO
   
α ViD ln r ViD ln r
+
VoD = − IEE RL tanh − + tanh +
Vbias 2 2VT 2 2VT 2
– (48)

After Taylor series expansion and some manipulation, Eq.

(48) can be rewritten as

  3 
ViD 1 ViD
Figure 11. Bipolar differential pair with emitter degeneration resis- VoD = −αIEE RL (1 − d) + d− + ··· (49)
tors used to extend the linear input range.
2VT 3 2VT
 DIFFERENTIAL AMPLIFIERS 387

VCC Fig. 12 is 1/0.64 or 1.56 times higher than for the circuit
in Fig. 3. Combined with the nearly threefold increase in
linear input range, this means that the SNR nearly dou-
bles. The increase in SNR is a distinct advantage over the
RL RL
emitter degeneration linearization technique. Moreover, the
+ – linearization approach introduced in this section can be ex-
VO tended to a summation of the output currents of three,
four, or more parallel asymmetrical pairs. However, there
is a diminished return in the improvement. Also, for more
than two pairs the required device ratios become quite
1 r r 1
ViD large, and the sensitivity of the linear input range to small
mismatches in the actual ratios versus their theoretical val-
ues increases as well.
ViC
IEE /2 IEE /2 Rail-to-Rail Common-Mode Inputs and
Vbias
+ Minimum Supply Voltage Requirement
–
With the consistent trend toward lower power supplies, the
usable input common-mode range as a percentage of the sup-
ply voltage is an important characteristic of differential am-
plifiers. Full rail-to-rail input compliance is a highly desirable
Figure 12. Two asymmetrical emitter-coupled pairs with respective property. Particularly for low power applications, the ability
transistor ratios r : 1 and 1 : r. The collector currents are summed. If to operate from a minimal supply voltage is equally impor-
r is selected appropriately, the linear input range and SNR are in-
tant. For the basic emitter-coupled pair in Fig. 3, the input is
creased.
limited on the positive side when the npn transistors satu-
rate. Therefore,
where
1
ViC,pos = VCC − R I + Vb c ,forward

r − 1 2 2 L EE
(53)
d= (50)
r+1
If one limits RLIEE /2 ⬍ Vbc,forward, ViC,pos can be as high as VCC or
Equation (49) indicates that the dominant third harmonic dis- even slightly higher. On the negative side, the common-mode
tortion component can be canceled by setting d ⫽ 1/3 or r ⫽ input voltage is limited to that level, where the tail current
2 ⫹ 兹3 ⫽ 3.732. The presence of parasitic resistances within source starts saturating. Assuming a single bipolar transistor
the transistors tends to require a somewhat higher ratio r for is used as the current source,
optimum linearization. In practice, the more easily realizable
ratio r ⫽ 4 (or d ⫽ 9/25) is frequently used. When the linear ViC,neg > Vbe + Vce,sat ≈ 1 V (54)
input ranges at a 1% total harmonic distortion (THD) level of
the single symmetrical emitter-coupled pair in Fig. 3 and the
The opposite relationships hold for the equivalent pnp tran-
dual circuit with r ⫽ 4 in Fig. 12 are compared, a nearly
sistor based circuit. As a result, the rail-to-rail common-
threefold increase is noted. For r ⫽ 4 and neglecting higher-
mode input requirement can be resolved by putting two
order terms, Eq. (49) becomes
complementary stages in parallel. In general, as the input
ADD ≈ −0.64 gm RL (51) common-mode traverses between VCC and ground, three dis-
tinct operating conditions can occur: at high voltage levels
where gm ⫽ 움IEE /2VT as before. Equation (51) means that the only the npn stage is active; at intermediate voltage levels
trade-off for the linearization is a reduction in the differential both the npn and pnp differential pairs are enabled; finally,
gain to 64 percent of the value obtained by a single symmetri- for very low input voltages only the pnp stage is operating.
cal emitter-coupled pair with equal power dissipation. The If care is not taken, three distinct gain ranges can occur:
squared input referred noise voltage per hertz for the two par- based on gmn only; resulting from gmn ⫹ gmp; and, contributed
allel asymmetrical pairs can be expressed as by gmp only. Nonconstant gm and gain, which depends on

2
ViN 8kT

r 1 1
 the input common-mode, is usually not desirable for several
reasons, not in the least in case of phase compensation if
= + b
+ 2 (52)
f (0.64)2 5 2 gm g m RL the differential pair is used as the first stage in an opera-
tional amplifier. Fortunately, the solution to this problem
The factor rb /5 appears because of an effective reduction in is straightforward if one recognizes that the transconduc-
the base resistance by a factor (r ⫹ 1), due to the presence tance of the bipolar transistor is proportional to its bias
of five transistors versus one in the derivation of Eq. (23). current. Therefore, the only requirement for a bipolar con-
If the unit transistor size in Fig. 12 is scaled down accord- stant gm complementary circuit with full rail-to-rail input
ingly, a subsequent comparison of Eqs. (23) and (52) reveals compliance is that under all operating conditions the sum
that the input referred noise for the linearized circuit of of the bias currents of the npn and pnp subcircuits remains
388 DIFFERENTIAL AMPLIFIERS

VCC Equation (56) can be rearranged as

4IDD r 2I
1 W − ViD
2
RL IEE RL ID1 − ID2 = µCox ViD W = KpViD DD
− ViD
2

+ – 2 L µCox Kp
VO
L
(57)

where

IDD = ID1 + ID2 (58)

Hence, the relationship between the differential output and

ViD input voltages is

4IDD
1 W − ViD
2
ViC + VoD = −RL (ID1 − ID2 ) = − µCox RLViD W
VREF 2 L µCox
r 2I
–
L
= −Kp RLViD DD
− ViD
2
(59)
Kp

Figure 13. Complementary bipolar differential amplifier with rail-
to-rail input common-mode compliance.
constant. A possible implementation is shown in Fig. 13.
If ViC ⬍ VREF, the pnp input stage is enabled and the
npn input transistors are off. When ViC ⬎ VREF, the bias
current is switched to the npn pair and the pnp input
devices turn off. For RLIEE /2 ⬍ Vcb,forward,n the minimum re-
quired power supply voltage is Vbe,n ⫹ Vbe,p ⫹ Vce,sat,n ⫹
Vce,sat,p, which is lower than 2 V.
MOS DIFFERENTIAL PAIRS (SOURCE-COUPLED PAIRS)
As mentioned above, Eq. (59) is only valid as long as both
transistors are in saturation or
r 2I
ViD ≤ DD (60)
Kp
Similar to the bipolar case, Eq. (59) is quite nonlinear and the
output voltage eventually clips when one of the input transis-
tors is completely starved of current. However, unlike the
emitter-coupled pair, the linear operating range of the source-
coupled pair also depends on the bias current and device
sizes. Equation (60) indicates that the linear range of opera-
tion can be expanded by increasing IDD and/or reducing the
W/L ratio of the MOS devices.

The MOS equivalent of the emitter-coupled pair is the VCC

source-coupled pair. Since the analysis of both circuits is
generally quite similar, the discussion of the source-coupled
pair will be more concise with an emphasis on important
differences. ID1 RL RL ID2

Low-Frequency Large-Signal Analysis

VO
Figure 14 depicts the source-coupled pair with a resistive
load. When the MOS transistors are in the saturation region, M1 M2
their current–voltage relationship can be described by the
square law characteristic.
ViD
1 W
ID = µCox (Vgs − Vt )2 = Kp (Vgs − Vt )2 (55)
2 L ViC

IDD RO
Using Eq. (55) and assuming perfect matching, the differen-
+
tial input voltage can be expressed as Vbias
–

2ID1

2ID2 rI rI
ViD = Vgs1 − Vgs2 = W − W =
D1 − D2
µCox µCox Kp Kp
L L Figure 14. MOS differential pair (source-coupled pair) with re-
(56) sistive loads.
 DIFFERENTIAL AMPLIFIERS 389

Low-Frequency Small-Signal Analysis The current mismatch ⌬ID can be expanded as

An expression for the small-signal transconductance of the
source-coupled pair can be derived by taking the derivative of ID = (Kp + Kp )(Vgs − Vt − Vt )2 − Kp (Vgs − Vt )2
Eq. (57) with respect to the input voltage. ≈ −2Kp Vt (Vgs − Vt ) + Kp (Vgs − Vt )2
(64)
d(ID1 − ID2 ) Kp
gm = (61) = −gm Vt + I
dViD Kp D

W
2K I 
gm = µCox I = p DD = 2 Kp ID = 2Kp (Vgs − Vt ) Substituting Eqs. (62) and (64) into (63) yields
L DD
(62)
  
Kp RL ID
VoO = −gm RL − Vt + +
As was noted for the bipolar differential pair, the transcon- Kp RL gm

   (65)
ductance of the source-coupled pair is only equal to the trans- Kp RL (Vgs − Vt )
conductance of one of the input devices. However, in contrast = −gm RL − Vt + +
Kp RL 2
to the bipolar transistor, gm in Eq. (62) is only proportional to
the square root of the bias current. Due to gm’s dependence on
the mobility 애 and the threshold voltage Vt, stabilization of This output offset voltage can be referred to the input by di-
gm over temperature is not as straightforward as is the case viding Eq. (65) by the amplifier’s gain.
for bipolar. Furthermore, gm of the source-coupled pair is a
VoO (Vgs − Vt )

K RL

function of the device size and the oxide capacitance. p
ViO = = − Vt + + (66)
−gm RL 2 Kp RL
Dc Offset
As pointed out previously, small device mismatches are un- The input referred offset voltage Vio is the voltage, which
avoidable and they give rise to an offset voltage. Assuming must be applied between the open-circuited gate terminals
such small differences in the circuit of Fig. 14 where the in- to cancel the differential voltage across the output nodes.
puts are tied together, one can derive an expression for the Equation (66) indicates that ViO is directly related to the
output offset voltage as follows: mismatch of the threshold voltages. The second term in Eq.
(66) is reminiscent of Eq. (32) for the bipolar differential
VoO = −(RL + RL )(ID + ID ) + RL ID ≈ −RL ID − RL ID pair. However, since the multiplicative term (Vgs ⫺ Vt)/2 in
(63) Eq. (66) is usually much larger than its counterpart VT in

VCC

+ –
VO

ViD

ViC
+
RO IF VREF
+ –
Vbias
–

Figure 15. Fully differential source-coupled pair with active current source loads and common-
mode feedback circuit.
390 DIFFERENTIAL AMPLIFIERS
Eq. (32), one concludes that the source-coupled pair is in-
herently subject to a larger offset voltage. On the other
hand, the source-coupled pair has no input offset current
since there is no gate current.
Active Load
Source-coupled pairs are almost exclusively used in conjunc-
tion with active loads. Figure 15 illustrates a fully differential
realization, including a possible implementation of the re-
quired common-mode feedback circuit. Its operation is similar
to the bipolar version in Fig. 9. A single-ended circuit is
shown in Fig. 16.
Linearization
In addition to controlling the linear range of operation by
proper selection of bias current and device sizes, the tech-
niques discussed for the emitter-coupled pair can also be ap-
plied to the source-coupled pair. Figure 17 illustrates the ap-
plication of source degeneration. However, the degeneration
resistor is implemented by a MOS transistor, which operates
in the linear region by connecting its gate to an appropriate
control voltage VC. The differential pair’s gain can be adjusted
by varying VC. Similarly, the technique of multiple asymmet-
rical pairs in parallel can also be extended to the MOS
domain.
Rail-to-Rail Common-Mode Input Signals
As for the bipolar case, the highly desirable rail-to-rail input
voltage compliance can be obtained by a parallel combination
of NMOS and PMOS differential pairs. However, the realiza-
tion of a constant gm over the whole range of operation is not
as straightforward. One possible solution is to operate the
MOS differential pairs in the subthreshold region, where the
VCC
VO
ViD
ViC
RO
+ A. B. Grebene, Bipolar and MOS Analog Integrated Circuit Design,
Vbias
– New York: Wiley, 1984.
Figure 16. Single-ended output implementation of a source-coupled
pair with active current source loads.
VCC
VO
VC
ViD
ViC
IE /2 IE /2
+
Vbias
–
Figure 17. MOS differential pair with degeneration implemented by
a MOS transistor in the linear region.
exponential current–voltage relationship holds and, as in the
bipolar case, gm is only a function of the bias current. Many
circuits using MOS transistors in saturation require some
kind of matching between the NMOS and PMOS devices,
which is extremely difficult to achieve in mass production. Re-
search into new circuit techniques to circumvent this problem
continues and, judging by the numbers of recent papers on
the subject, constitutes an area of significant contemporary
academic interest.
BIBLIOGRAPHY
P. E. Allen and D. R. Holberg, CMOS Analog Circuit Design, Fort
Worth, TX: Holt, Rinehart and Winston, 1987.
G. A. De Veirman, et al., A 3.0 V 40 Mbit/s hard disk drive read
channel IC, IEEE J. Solid-State Circuits, SC-30: 788–799,
1995.
J. F. Duque-Carrillo, J. M. Valverde, and R. Pérez-Aloe, Constant-gm
rail-to-rail common-mode range input stage with minimum CMRR
degradation, IEEE J. Solid-State Circuits, SC-28: 661–666,
1993.
J. Fonderie, Design of Low-Voltage Bipolar Operational Amplifiers,
Delft: Delft University Press, 1991.
L. J. Giacoletto, Differential Amplifiers, New York: Wiley, 1970.
P. R. Gray and R. G. Meyer, Analysis and Design of Analog Integrated
Circuits, 2nd ed., New York: Wiley, 1984.
R. Hogervorst, et al., CMOS low-voltage operational amplifiers with
constant gm rail-to-rail input stage, Proc. IEEE Int. Symp. Circuits
Systems (ISCAS) : 1992, pp. 2876–2879.
J. H. Huijsing and D. Linebarger, Low-voltage operational amplifier
with rail-to-rail input and output ranges, IEEE J. Solid-State Cir-
cuits, SC-20: 1144–1150, 1985.
 DIFFERENTIATING CIRCUITS 391

C. Hwang, A. Motamed, and M. Ismail, Universal constant-gm input-

stage architectures for low-voltage opamps, IEEE Trans. Circuits
Syst.—I, 42: 886–895, 1995.
R. D. Middlebrook, Differential Amplifiers, New York: Wiley, 1963.
J. Schmoock, An input stage transconductance reduction technique
for high-slew rate operational amplifiers, IEEE J. Solid-State Cir-
cuits, SC-10: 407–411, 1975.
S. Sakurai and M. Ismail, Robust design of rail-to-rail CMOS opera-
tional amplifiers for low power supply voltage, IEEE J. Solid-State
Circuits, 31: 146–156, 1996.
J. O. Voorman, W. H. A. Brüls, and P. J. Barth, Bipolar integration of
analog gyrator and Laguerre type filters, Proc. ECCTD, Stuttgart,
108–110, 1983.
R. J. Widlar and M. Yamatake, A fast settling opamp with low
supply current, IEEE J. Solid-State Circuits, SC-24: 796–802,
1989.

GEERT A. DE VEIRMAN
Silicon Systems, Inc.

DIFFERENTIAL AMPLIFIERS. See INSTRUMENTATION AM-

PLIFIERS.
DIFFERENTIAL EQUATIONS. See ORDINARY DIFFEREN-
TIAL EQUATIONS.
DIFFERENTIAL EQUATIONS, ORDINARY. See ORDI-
NARY DIFFERENTIAL EQUATIONS.
DIFFERENTIAL PAIRS. See DIFFERENTIAL AMPLIFIERS.
DIFFERENTIAL RESISTANCE, NEGATIVE. See NEGA-
TIVE RESISTANCE.

DIFFERENTIATING CIRCUITS
Since the dynamics of systems comes through derivatives,
electronic circuits that perform differentiation are important
components both in theory and in practice. In the following
article we define differentiators, giving their transfer func-
tions from which some properties can be inferred. Highly ac-
curate voltage mode physical realizations in terms of op-amp
circuits, as well as current mode ones suitable for very large
scale integration (VLSI) realization, are given. Also included
are approximate ones in terms of simple resistor-capacitor
(RC) circuits appropriate for many control system applica-
tions. Since differentiators are not represented in terms of
standard state variables, we conclude with a semistate repre-
sentation.
DEFINITION
Here a differentiating circuit, also known as a differentiator,
is defined as an electronic circuit satisfying the law
du(t)
y(t) = D (1)
dt
where u( ⭈ ) is the input to the circuit, y( ⭈ ) is the output,
and D is the differentiator gain, usually taken to be a real
constant in time t. Because the differentiator is electronic,
we take u and y to be voltages or currents, though at times
one may wish to consider flux linkages or charge. According
J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.
DIFFERENTIATING CIRCUITS 391
to Eq. (1), ideally the differentiator is a linear system, map-
ping the input into the output linearly. If D is a constant,
then on taking the bilateral Laplace transform, L[ ⭈ ], of Eq.
(1) we obtain the system transfer function description,
H(s) ⫽ L[y]/L[u], in terms of the complex frequency variable
s ⫽ ␴ ⫹ j웆,
H(s) = Ds (2)
Evaluating this in terms of real frequency, 웆, we find that
H( jω) = jDω (3)
which shows that the differentiator introduces a constant
phase shift of 90⬚ and amplifies the input proportionally to
the frequency. This illustrates the difficulty one runs into
when practically using a differentiator since high-frequency
signals, which are often noise components, get greatly ampli-
fied compared to low-frequency signals, which most often are
the ones carrying intelligence, according to 兩H( j웆)兩 ⫽ D웆 (for
웆 ⱖ 0).
CIRCUIT IMPLEMENTATIONS
If the output is measured at the same terminals as the input,
then the device is a one-port differentiator; and in the case
where u is a voltage v and y is a current i, the differentiator
is equivalent to a capacitor so that the gain constant becomes
an equivalent capacitance, D ⫽ C, as illustrated in Fig. 1(a).
Figure 1(b) shows the dual case of an inductor.
For voltage mode circuits, differentiators are customarily
two-port devices constructed from operational amplifiers ac-
cording to the circuit of Fig. 2(a) (1, p. 10). In Fig. 2(a), u is a
voltage, vin, as is y, vout, and the gain constant is D ⫽ ⫺RC. If
an ideal op-amp is assumed, it is an infinite gain device with
a virtual ground input. Thus,
dvin (t)
vout (t) = −RC (4)
dt
It should be noted that achieving a gain D ⫽ ⫺RC near unity
in magnitude usually requires a large resistor; for example, if
C ⫽ 1 애F, then R ⫽ 1 M⍀.
y=i u=i
+ +
u=v C y=v L
– –
(a) (b)
Figure 1. (a) Capacitor as a differentiator. Here the input u equals
v and the output y equals i, which gives Y(s) ⫽ I(s) ⫽ CsV(s) in the
frequency domain. (b) Inductor as a differentiator. Here the input u
equals i and the output y equals v, which gives Y(s) ⫽ V(s) ⫽ LsI(s)
in the frequency domain.
392 DIFFERENTIATING CIRCUITS

C R VDD

+
M1 M3 M5

Vin –
OA
+ +
Vout
– –
iin C iout

Figure 2. Op-amp differentiator.

M2 M4 M6
For practical op-amps there are several points to consider.
One is that the op-amp gain is reasonably well approximated
by a one-pole model K(s) ⫽ K0 /(s ⫹ p1) so that the differentia-
tor transfer function becomes
VSS
−sRC
H(s) =
1
 s2 RC s(1 + RCp1 )
(5)
Figure 4. Current mode differentiator.
1− − +
K0 K0 K0

from which we see that as the frequency gets large the gain
drops toward zero according to K0 /s. Besides this sometimes
favorable behavior, there are also nonlinearities due to satu-
ration of the op-amp at the bias voltages and added noise due
to the transistors and resistors used in the construction of the
op-amp.
In some cases, such as derivative control, it is more eco-
nomical to use the RC circuit of Fig. 3, which gives an approx-
imate differentiator having the transfer function
sC
H(s) = (6)
1 + sRC
For frequencies lower than 웆p ⫽ 1/RC, this circuit approxi-
mates a differentiator reasonably well, and its gain satu-
rates at higher frequencies so that noise is not unduly am-
plified.
In terms of modern very large scale integration (VLSI) im-
plementations, it is most convenient to use current mode
structures. Figure 4 shows a current mode structure which
differentiates the signal component of the input using comple-
mentary metal oxide semiconductor (CMOS) transistors (2).
Here the input transistors M1 and M2 act as resistors to con-
vert the input current iin to a voltage which is applied to the
capacitor. The capacitor current, which is essentially the de-
rivative of this voltage, is transferred through the output cur-
rent mirror transistors M5 and M6, which can give an added
gain k. The analysis of the circuit proceeds by replacing all
transistors by their small-signal equivalent circuits incorpo-
C 141. Such an operation is automatically carried out in the
+ +
Vin R Vout
– –
Figure 3. RC ladder circuit.
rating their transconductances, gm. Ignoring their source to
drain conductances, the analysis gives the small-signal trans-
fer function as [2, Eq. (6)]
 
iout

−kC
 s
H(s) = = (7)
iin gm p + gmn 2sC
1+
gm p + gmn
where k is the current gain of the output current mirror tran-
sistors and gmn and gmp are the transconductances of the n
channel metal oxide semiconductor (NMOS) and p channel
metal oxide semiconductor (PMOS) transistors. Conse-
quently, the circuit makes a reasonably good current-in cur-
rent-out differentiator through the mid-megahertz frequency
range. Note that since the transistor transconductances de-
pend on the bias point of the transistors, it is important to
use a regulated voltage source to keep the direct current
bias stable.
NOISE AND SIGNAL SWING CONSIDERATIONS
When working with op-amp differentiators, it is important to
consider noise behavior. For this the noise sources are nor-
mally reflected into the input and then the output noise is
found by applying the equivalent noiseless amplifier to the
input noise sources with a good treatment given in Ref. 1, p.
PSpice noise analysis. A typical frequency response example
circuit is shown in Fig. 5(a) with its noise input, Fig. 5(b, top)
and noise output, Fig. 5(b, middle), along with the output,
Fig. 5(b, bottom), for a 1 mV input plus noise. In this circuit
a 701 op-amp is used and a reasonably small resistor is in-
serted in series with the differentiation capacitor to assist in
damping out the noise signal.
 DIFFUSION 393

+ V+
7
3
+ 10 V
V+ 6 –
Rin 100 Ω –
C1 1µ F 2 V– –10 V
–
Vin
4 V–
Direct current = 0 V +
+
Alternating current R1 1 MΩ
– out
= 1 mV

(a)

194.8 nV
. . .
. . .
. . .
194.6 nV
V(input noise)
10 mV
. . .
. . .
. . .

1.0 µ V
V(output noise)
10 V
. . .
. . . Figure 5. (a) PSpice circuit of a differenti-
. . . ator using 701 op-amp. (b) Response and
1.0 mV noise behavior in the frequency domain.
10 Hz 100 Hz 1.0 kHz 10 kHz 100 kHz The top curve represents the input noise,
V(out) Frequency the middle curve is the output noise, and
the bottom curve is the output response to
(b) an input voltage of 1 mV plus noise.

SEMISTATE EQUATIONS known to be less sensitive to noise compared to the conven-

tional op-amp differentiator.
Because the standard state-space equations do not exist for a
differentiator, we give a description of it in terms of semistate
BIBLIOGRAPHY
equations. These latter are equations of the form

dx 1. E. J. Kennedy, Operational Amplifier Circuits, Theory and Appli-

E = Ax + Bu (8) cations, New York: Holt, Rinehart and Winston, 1987.
dt
2. E. I. El-Masry and J. W. Gates, A novel continuous-time current
y = Cx (9) mode differentiator and its applications, IEEE Trans. Circuits
Syst. II, 43: 56–59, 1996.
which have the transfer function 3. M. E. Zaghloul and R. W. Newcomb, Semistate implementation:
Differentiator example, J. Circuits Syst. Signal Process., 5 (1):
H(s) = C(sE − A)−1 B (10) 171–183, 1986.

On choosing the semistate vector x ⫽ [x1, x2]T ⫽ [y, u]T, where ROBERT W. NEWCOMB
T denotes transpose, one can write LOUIZA SELLAMI
      University of Maryland at College
dx 0 D dx 1 0 0 Park
E = = x+ u = Ax + Bu (11)
dt 0 0 dt 0 1 −1
y = [1 0]x = Cu (12)
DIFFERENTIATION. See CALCULUS.
which gives DIFFRACTION. See BACKSCATTER; ELECTROMAGNETIC
 −1   WAVE SCATTERING.
−1 Ds 0
H(s) = [1 0] = Ds (13)
0 −1 −1

These semistate equations can be transformed via a linear

transformation into a form that is useful for circuit realiza-
tions based upon integrators (3). Op-amp integrators are
DIGITAL FILTERS
FILTERS, DIGITAL
DISCRETE-TIME FILTERS
Most phenomena in nature occur in continuous time, such
as temperature change, lifetime of a human being, wind
speed at a given location, and so on. As a result, if we intend
to design a system to interfere with or to measure a nat-
ural phenomenon, the system should be analog. A widely
used procedure to design systems with interaction with a
natural phenomenon is to convert some quantities from
the nature into electric signals. Electric signals, which are
represented by voltage or current, have a continuous-time
form. However, continuous-time signals are not suitable to
be processed using computer-type processors (digital ma-
chines), which are meant to deal with sequential computa-
tion involving numbers. Fortunately, many signals taken
from nature can be fully represented by their sampled ver-
sions, where the sampled signals coincide with the origi-
nal analog signals at predefined time instants. Let’s take
a real live example by supposing we are watching a movie
at home. If the movie is monotonous, we can pay atten-
tion to what is happening in the movie only from time to
time and still understand the story. On the other hand, if
the movie gives important information at short periods of
time, we can not miss it for a long time. In the latter case,
the director already made a tough sample of the story for
the viewer. In conclusion, if we know how fast the impor-
tant information changes, we can always sample and con-
vert the information in numbers for a fast enough digital
machine. Fortunately, the electronic technology is at our
side, by allowing very fast digital processors to be built at
a reasonable cost. This is one of the reasons the so called
digital filters, which are filters suitable to process sampled
signals implemented in digital machines, are replacing the
analog filters in a number of applications. Also, there are
a number of signals that are originally discrete-time, take
for example the stock-market daily financial indicators.
The rapid development of high-speed digital integrated
circuit technology in the last three decades has made dig-
ital signal processing not only a tool for the simulation of
analog systems but also a technique for the implementa-
tion of very complex systems. Digital signal processing has
found applications in many areas such as image processing,
multimedia systems, speech analysis and synthesis, mobile
radio, sonar, radar, biomedical engineering, seismology, and
modern communication systems.
The main advantages of digital systems relative to ana-
log systems are high reliability, ease of modifying the char-
acteristics of the filter, and low cost. These advantages mo-
tivated the digital implementation of many signal process-
ing systems, which were usually implemented with analog
circuit technology. In addition, a number of new applica-
tions became viable after the availability of the very-large-
scale integration (VLSI) technology. Usually in the VLSI
implementation of a digital signal processing system the
J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright © 2007 John Wiley & Sons, Inc.
concern is in reducing power consumption or area, or in
increasing the circuits speed in order to meet the demands
of high-throughput applications.
The digital filter is in general the most important tool
in most digital signal processing systems. The digital fil-
ter processes signals that are discrete in time and in am-
plitude, that is, signals occurring at distinct and usually
equidistant times that can assume a discrete set of am-
plitude values. In this article, we are primarily concerned
with linear, shift-invariant digital filters implemented us-
ing finite-precision arithmetic.
In practice, a digital filter is implemented using soft-
ware on a general-purpose digital computer or a digital sig-
nal processor (DSP), or by using application-specific hard-
ware usually in the form of an integrated circuit. In any
type of implementation, quantization errors are inherent
due to finite-precision arithmetic. In implementations for
specific applications there are techniques such as algo-
rithms and topologies for digital filters that allow us to
meet low-power, low-area, and/or high-speed specifications.
The quantization errors can be classified as follows:
Roundoff errors resulting when the internal signals like
the output of multipliers are quantized before or after
additions
Errors in the magnitude and phase response of the filter
caused by the use of finite wordlength for the repre-
sentation of the multiplier coefficients
Errors due to the representation of the input signal with
a set of discrete levels
The quantization errors described depend on the type of
arithmetic used in the actual implementation. If the digi-
tal filter is implemented on a general-purpose processor or
a DSP, floating-point arithmetic is usually available; there-
fore this type of arithmetic is the choice. On the other hand,
if the digital filter is implemented by means of application-
specific hardware or lower cost DSPs, fixed-point arith-
metic is usually the best choice because of its low complex-
ity in terms of silicon area for the hardware. In this article,
only fixed-point arithmetic is addressed.
DIGITAL FILTERS
In a digital filter represented in the block diagram of Fig.
1, the input signal x(n) is a sequence of numbers, indexed
by the integer n, which can assume only a finite number
of amplitude values. Such input sequence comes, most of
the time, from an analog (or continuous-time) signal x(t) by
periodically sampling it at the time instants t = nT, where
T is called the sampling interval. The output sequence y(n)
is the response of the digital filter when excited by the in-
put x(n), with the relationship between x(n) and y(n) rep-
resented by the operator H as
The most important class of digital filters is composed
by linear, time-invariant (LTI) and causal filters. A linear
digital filter is one whose response to a weighted sum of
input signals is equal to the same weighted sum of the
2 Discrete-Time Filters
Figure 1. Frequency response of the notch filter of Eq. (7) with r
= 0.9 and θ = π/4.
corresponding individual responses, that is,
for any sequences x1 (n) and x2 (n), and any arbitrary con-
stants α and β. A digital filter is said to be time invariant
when its response to an input sequence is always the same,
independent of the time instant when the input is applied
to the filter (assuming that the filter is always operating
under the same initial conditions); that is, if H[x (n)] = y(n),
then
for all integers n and n0 . A causal digital filter is one whose
response does not depend on the future values of the exci-
tation signal. Therefore, for any two input sequences x1 (n)
and x2 (n) such that x1 (n) = x2 (n) for n ≤ n0 , the correspond-
ing responses of the digital filter (with same initial condi-
tions) are identical, that is,
An LTI digital filter is completely characterized by its
response to the unit sample or impulse sequence δ(n) (as-
suming it is initially relaxed). The impulse sequence is de-
fined as
and the filter response when excited by such a sequence is
denoted by h(n) and it is referred to as impulse response of
the digital filter. Observe that if the digital filter is causal,
then h(n) = 0 for n < 0. An arbitrary input sequence can
be expressed as a sum of delayed and weighted impulse
sequences; that is,
and the response of an LTI digital filter to x(n) can then be
expressed by
The summation in the last line of the above expression,
called the convolution sum, relates the output sequence of
a digital filter to its impulse response h(n) and to the input
sequence x(n). The convolution operation is represented by
By applying a change of variables in the summation of Eq.
(7), one can verify that the convolution operation is com-
mutative; that is, the output of a digital filter with impulse
response h(n) and input x(n) is also given by
Defining the z transform of a sequence x(n) as
the transfer function of a digital filter is the ratio of the z
transform of the output sequence to the z transform of the
input signal; that is,
Taking the z transform of both sides of the convolution ex-
pression of Eq. (9), that is,
and substituting variables (m = n − k),
the following relation among the z transforms of the output
Y(z), of the input X(z) and of the impulse response H(z) of
a digital filter is obtained:
Hence, the transfer function of an LTI digital filter is the z
transform of its impulse response.
SAMPLING RATE
Most of the signals encountered in science, such as speech,
biological signals, seismic signals, radar, and sonar, are
analog. To process them by a digital filter, they need to be
sampled and converted to digital by an analog-to-digital
(A/D) converter.
 Discrete-Time Filters 3

The sampling theorem states that a bandlimited analog The frequency response H(ej  ) is a periodic function of
signal x(t) whose highest frequency component is at the fre-  with period 2π; that is,
quency fmax can be exactly recovered from its sample values
x(n) at the time instants t = nT, if the sampling frequency
fs = 1/T is larger than twice fmax . The sampling rate 2fmax is
for any integer k. Thinking in terms of analog frequency
called the Nyquist rate. The original continuous-time sig-
(for sampled analog signals), the function H(e ja T ) is pe-
nal can be recovered from the sampled signal x(n) by the
riodic in a with period 2π/T = s . This periodicity is ex-
interpolation formula
plained by observing that continuous-time sinusoidal sig-
nals of frequencies a and a + ks result, when sampled,
in identical sequences. Therefore, both signals must pro-
duce the same output when processed by the same digital
with s = 2πfs . filter.
The recovery of an analog signal from its samples by In general, H(ej  ) is a complex-valued function, which
the above interpolation formula is impractical, because it can be expressed in polar form as
involves the summation of infinite duration functions and
the knowledge of future samples of the signal x(t) involved
in the summation. Practical circuits which convert back the
where |H(ej  )| and ∠H(ej  ) are called the magnitude re-
filtered signal to analog form are called digital-to-analog
sponse and phase response, respectively, of the digital filter.
(D/A) converters.
A large class of sequences can be expressed in the form
In general, if an analog signal x(t) is sampled with a
sampling frequency fs smaller than twice its maximum fre-
quency fmax , then distinct frequency components of x(t) will
be mixed, causing an undesirable distortion in the recov-
ered continuous-time signal referred to as aliasing. where

FREQUENCY RESPONSE
X(ej  ) is called the Fourier transform of the sequence x(n).
The response of an LTI digital filter to a complex exponen-
A sufficient but not necessary condition for the existence
tial (or complex sinusoid) of radian frequency , that is,
of the Fourier transform X(ej  ) is that the sequence x(n) is
x(n) = ej n for −∞ < n < ∞, is a complex exponential of
absolutely summable, that is,
the same frequency  with a possible complex amplitude
modification. Such property can be verified from the con-
volution expression of Eq. (9), where the output of a digital
filter with impulse response h(n) and excited by the com-
plex exponential of frequency  is given by Using the above Fourier representation, the input se-
quence can be written as the sum of the complex exponen-
tials ej n weighted by X(ej  )d. From the superposition
property of linear systems, the output of the digital filter
with frequency response H(ej  ) and with x(n) as input is
given by the corresponding sum of the responses to each
complex exponential, that is,

In the above expression, H(ej  ) describes the changes in

amplitude introduced by the digital filter to the complex
exponential input signal. Such function of  is called the
frequency response of the digital filter, and it corresponds
to the transfer function H(z) evaluated on the unit circle in
the z plane (|z| = |ej  | = 1).
Observe that if the complex sinusoidal sequence comes
from sampling an analog sinusoidal signal, the relation be-
tween the frequency of the discrete-time sinusoid  and the
frequency of the continuous-time analog sinusoid a is ob-
tained by making t = nT in the analog signal and equating
both signals, resulting in  = aT = a /fs . Hence, the digital
frequency is equivalent to the analog frequency normalized
by the sampling frequency, and, therefore, is always be-
tween −π and π if the sampling theorem is satisfied. The
low frequencies are the frequencies  close to zero, whereas
the high frequencies are the frequencies close to π, with 
= π corresponding to the Nyquist frequency (a = s/2 ).
Hence, each frequency component of the input sequence
x(n) is modified by the frequency response of the digital
filter at the corresponding frequency.
From Eq. (22) and from the definition of the Fourier
transform in Eq. (20), the frequency response of a digital
filter is the Fourier transform of its impulse response. From
Eq. (22), the Fourier transform of the output of a digital
filter is given by the product of the Fourier transforms of
the input and of the impulse response, that is,
Filters that select the low-frequency components of the in-
put signal are called low-pass filters; those that select only
high-frequency components of the input are called high-
pass filters; bandpass and bandstop filters keep and reject,
4 Discrete-Time Filters
Figure 2. (a) Frequency response of highpass filter of Eq. (8); (b)
Frequency response of comb filter of Eq. (9).
respectively, components in a frequency band in the inter-
val 0 ≤  < π. The ideal frequency responses of such filters
are illustrated in Fig. 2.
DIFFERENCE EQUATIONS
A large and important subclass of linear time-invariant
digital filters consists of the filters whose input and output
sequences satisfy an equation of the form
where ak and bm are constant coefficients. The above equa-
tion is referred to as an Nth order difference equation. For
a causal filter with input–output related by the above dif-
ference equation with coefficients scaled such that a0 = 1,
the present value of the output y(n) can be computed from
the N past output values and from the present and M past
input values by
In the particular case when ak = 0 for k = 1, . . . , N, the
digital filter implemented by the above equation is called
a nonrecursive filter, because there is no feedback from the
past output in the computation of its present value. When
there is feedback, that is, ak = 0 for at least one k for k
= 1, . . . , N, the filter implementation given by the above
difference equation is called recursive.
The computation of each output value by Eq. (25) re-
quires the storage of past samples of the input and output
sequences, the multiplication of these samples by the corre-
sponding coefficients of the difference equation, and the ad-
dition of the results of such multiplications. Therefore, the
calculation of y(n) can be represented in a block diagram
through the interconnection of the three basic elements,
with symbols shown in Fig. 3: the unit delay, the multi-
plier, and the adder. The unit delay is represented by z−1 ,
which is the transfer function associated with it. The block
diagram corresponding to Eq. (25) when there is feedback
(recursive implementation) is given in Fig. 4. Such filter
implementation is called a direct form I structure. Another
implementation of recursive digital filters which satisfies
Eq. (24) is based on the following pair of equations
The block diagram of the resulting implementation is
shown in Fig. 5 and is called a direct form II structure.
The direct form II realization requires a number of unit
delays (or memory locations) equal to the maximum value
of M and N. This value is the minimum number of delays
needed to obtain the output of the filter satisfying Eq. (24),
and, therefore, the direct form II structure is said to be
canonic.
The block diagram corresponding to the nonrecursive
case is shown in Fig. 6, where there is no feedback of the
past output values.
The transfer function of a system with input and output
related by a difference equation can be obtained by taking
the z transform of both sides of Eq. (24), that is,
where we have used the linearity property of the z trans-
form and the fact that the z transform of a delayed sequence
x(n − nd ) is given by z−nd X(z), where X(z) is the z transform
of x(n). Thus, from the above equation,
Therefore, the transfer function of a digital filter that satis-
fies Eq. (24) is a rational function of z; that is, it is given by a
ratio of polynomials in z, with the coefficients of such poly-
 Discrete-Time Filters 5

Figure 3. Frequency responses of a fourth-order elliptic filter

realized with the normalized lattice structure, with coefficients
quantized to 12, 8 and 6 bits.

nomials equal to the coefficients of the difference equation.

The values of z for which H(z) = 0 are called the zeros of the
transfer function of the digital filter, and are the roots of
the numerator polynomial of H(z). The roots of the denom-
inator polynomial of H(z) are called the poles of the digital
filter’s transfer function, and are the values of z for which
H(z) is infinite. The transfer function H(z) can be written
in terms of its poles pk and zeros zm as

The above factored form of H(z) can be useful for estimating

the frequency response of a digital filter from its zeros and
poles. From Eq. (16), the frequency response of a digital
filter is equal to its transfer function evaluated on the unit
circle in the z plane, that is, at z = ej  . Representing the
differences (z − zm ) for z = ej  in the z plane by the vectors
Cm and the differences (z − pk ) for z = ej  by the vectors Dk ,
we can express the magnitude and phase of the frequency
response by

Figure 4. Recursive implementation of a digital filter obtained

from the difference equation given in Eq. (25) (direct form I struc-
and ture).

with transfer function

where |Cm | and |Dk | represent the magnitudes of the vec-

tors Cm and Dk , and ∠Cm and ∠Dk represent the angles of
the vectors Cm and Dk as related to the real axis measured
counterclockwise, respectively.
Figure 7 illustrates the pole–zero diagram as well as
the vectors defined above for the second-order digital filter
One can observe that for frequencies  near the zeros,
|H(ej  )| will be very small since the zeros are close to
the unit circle and the vectors from the zeros to ej  will
have small magnitudes. The phase response, ∠H(ej  ), will
6 Discrete-Time Filters
Figure 5. Canionic recursive implementation obtained from the
pair of difference equations given in Eq. (26) (direct form II struc-
ture).
Figure 6. Nonrecursive implementation of a digital filter from
the difference equation given in Eq. (25) with ak = 0 for k = 1, . . . ,
N.
Figure 7. Geometric frequency response evaluation from the
poles and zeros of the transfer function H(z) of Eq. (32).
change by almost π rad near the zeros frequencies. For fre-
quencies close to the poles, there will be a peak in |H(ej  )|,
and ∠H(ej  ) will change by almost −π rad. Such frequency
response estimation can be verified in the plots of the mag-
nitude and phase responses shown in Fig. 8.
Figure 8. Frequency response of the digital filter with transfer
function H(z) given in Eq. (32).
FINITE IMPULSE RESPONSE FILTERS
A digital filter whose impulse response is of finite dura-
tion (i.e., it is zero outside a finite interval) is called a finite
impulse response (FIR) filter. From the convolution expres-
sion of Eq. (9), the output of a causal FIR filter with h(n) =
0 for n < 0 and for n > M is given by
Comparing the above expression with the output of the dif-
ference equation given in Eq. (25), we can observe that the
output of an FIR filter can be obtained by the nonrecursive
implementation of Fig. 4 with the multipliers bm equal to
the impulse response samples h(m). Usually FIR filters are
implemented nonrecursively, even though recursive imple-
mentations of FIR filters are also possible resulting in a
reduction in the number of multipliers in some cases.
The transfer function of an FIR filter has the form
which has all of its M poles at z = 0. Hence, an FIR filter
is characterized by the locations of the zeros of its transfer
function.
A simple example of an FIR filter is the moving average
filter, whose output is the average of the present and the
 Discrete-Time Filters 7

last M samples of the input sequence; that is,

The transfer function of an FIR filter satisfying one of the
above conditions with M even is

The impulse response of this system is

and with M odd is

and its transfer function is given by

where the ± signs in the above equations represent the +

sign for symmetric impulse responses satisfying Eq. (42)
and − for antisymmetric impulse responses as in Eq. (43).
The frequency responses corresponding to the above trans-
fer functions with z = ej  can be written in the form
The zeros of H(z) are at zm = ej [2πm/(M +1)] for m = 1, . . . , M.
From the first line of the above equation, the output of this
system can be obtained by the nonrecursive implementa-
for symmetric impulse responses, and
tion of Fig. 6 with coefficients bm = 1/(M + 1), for m = 0,
. . . , M. The second line of the above expression suggests a
recursive implementation such as that of Fig. 4, with the
nonzero coefficients given by a1 = −1, b0 = 1, and bM+1 = for antisymmetric impulse responses, with R() being a
−1. real-valued function of . For M even, the corresponding
FIR filters are specially useful for implementing linear- group delay M/2 is an integer, and R() is given by
phase transfer functions, that is, transfer functions H(z)
such that

for a symmetric impulse response, and

The response of a linear-phase digital filter to a complex
sinusoid of frequency  is given by

for an antisymmetric impulse response, where h(M/2 ) = 0

which for α integer is in the latter case. For M odd, M/2 is not an integer, resulting
in a group delay that does not correspond to an integer
number of sampling periods. R() is given by

Hence, the phase modification introduced by the linear

phase filter in the sinusoidal input signal corresponds to a
constant delay that is independent of . From the super-
for a symmetric impulse response, and
position property of LTI systems, an arbitrary signal x(n)
filtered by a linear phase filter will have all its frequency
components delayed by the same amount α. Defining the
group delay of a filter as
for an antisymmetric impulse response.
An FIR filter with antisymmetric impulse response
presents a zero at z = 1 for M even or odd, and a zero
at z = −1 for M even, as can be seen from Eqs. (44) and
a linear phase filter with phase response as in Eq. (38) has
(45). Therefore, FIR filters with antisymmetric impulse re-
a constant group delay α.
sponses cannot implement lowpass filters. Also, such fil-
An FIR filter with linear phase response can be easily
ters cannot implement highpass filters when M is even.
obtained by imposing one of the symmetry conditions below
An FIR filter with symmetric impulse responses and M odd
on the impulse response of the filter:
presents a zero at z = −1 and, therefore, cannot implement
highpass filters. The other zeros of a linear-phase FIR filter
H(z) are such that if zm is a zero of H(z), so is 1/z∗ m .
or An FIR filter can be designed truncating the infinite im-
pulse response of an ideal filter hideal (n) through the multi-
plication of hideal (n) by a finite length sequence w(n) called
8 Discrete-Time Filters

window. Other FIR filter design methods are based on op- stop filters are, respectively,
timization techniques, such as the Remez exchange algo-
1 − z−2
rithm, which minimizes the maximum deviation of the fre- HBP (z) = k (3)
quency response of the filter from a prescribed specifica- 1 − 2r cos θz−1 + r2 z−2
tion. Such design methods can be found elsewhere (1). and
1 − 2 cos θz−1 + z−2
HBS (z) = k (4)
INFINITE IMPULSE RESPONSE FILTERS 1 − r2 z−2
with |r| < 1 for stability. The parameters r and θ determine,
Filters with infinite-length impulse responses are called in- respectively, the passband width and the center frequency
finite impulse response (IIR) filters. The output of an IIR fil- of the passband/stopband.
ter is obtained by a recursive implementation, such as the Some special IIR filters are allpass, notch, and comb fil-
direct-form structures shown in Figs. 4 and 5. The direct- ters. The allpass filters are useful for phase equalization,
form structures have high sensitivity to coefficient vari- and are characterized by having unity magnitude response
ations, especially when implementing transfer functions for all frequencies, i.e.,
with poles clustered close to the unit circle.
Other IIR filter structures, which present lower sensi- |HAP (e jω )| = 1, for all ω (5)
tivity than the direct form, are based on the implemen- The transfer function of an N-th order allpass filter is of
tations of the filter transfer function H(z) in a factored the form:
form. In the cascade structure, H(z) is factored as a prod-
N
ak z−N+k A(z−1 )
uct of first- and/or second-order transfer functions, which HAP (z) = ±
k=0
N
= ±z−N (6)
are implemented separately by either one of the direct- k=0
ak z−k A(z)
form structures of Figs. 4 and 5 and connected in cascade. 1 − jφ
The parallel structure is based on the implementation of Observe that if z0 = re jφ is a pole of HAP (z), z−1
0 = e
r
H(z) when expressed as a sum of first- and/or second-order will be a zero of HAP (z).
transfer functions, obtained by partial fraction expansion The notch filters are bandstop filters with very narrow
of H(z). The wave and lattice realizations, both presenting rejection band. They are useful in eliminating narrowband
low sensitivities, will be introduced in this article. noise, such as the 60-Hz power-line interference. A typi-
As opposed to FIR filters, IIR filters have poles in lo- cal second-order notch transfer function has zeros over the
cations other than the origin of the z plane. To guarantee unity circle and poles close to it, with same angles ± θ, i.e.,
stability of an IIR filter, that is, that an input of bounded
amplitude results in a bounded output sequence when pro- 1 − 2 cos θz−1 + z−2
HN (z) = (7)
cessed by the filter, the poles of H(z) must lie inside the unit 1 − 2r cos θz−1 + r2 z−2
circle in the z plane (1). The design of an IIR filter consists with |r| < 1. Figure 1 shows the frequency response of the
of finding the coefficients or the poles and zeros of the trans- π
notch filter of Eq. (7) with r = 0.9 and θ = .
fer function, such that the frequency response of the filter 4
satisfies a given specification. Some IIR filter design tech- Comb filters find application in pitch detection of speech
niques use established analog filter approximation meth- signals and cancellation of periodic interferences, among
ods with the application of a transformation technique to others. Their frequency responses are periodic with period
2π
the analog transfer function or impulse response to obtain , where M is a positive integer. The transfer function of a
the digital transfer function. One of such transformations M
comb filter can be obtained from a single passband trans-
is the bilinear transformation, where the variable s in the fer function H(z) by substituting zM for z, that is, HC (z)
transfer function of the analog filter is replaced by = H(zM ). For example, the high-pass filter with transfer
function given by
1 − z−1
HHP (z) = 0.25 (8)
Other design techniques for IIR filters are based on opti- 1 + 0.5z−1
mization methods, such as the quasi-Newton method de- and frequency response illustrated in Fig. 2(a), generates
scribed elsewhere (1). the 8-band comb filter with transfer function
Examples of first-order IIR low-pass and high-pass fil- 1 − z−8
ters are, respectively, HC (z) = HHP (z8 ) = 0.25 (9)
1 + 0.5z−8
1 + z−1 Its frequency response is shown in Fig. 2(b).
HLP (z) = k (1)
1 − αz−1
and WAVE DIGITAL FILTERS
−1
1−z
HHP (z) = k (2) The designer of filters, regardless of the implementation
1 − αz−1 technology, is usually interested in finding structures with
with |α| < 1 for stability. The constant k determines the low sensitivity to coefficient variations. In digital filter de-
filter gain, while the parameter α controls the passband sign the low sensitivity implies small effect on the over-
width. Examples of second-order IIR bandpass and band- all transfer function when the values of the coefficients
 Discrete-Time Filters 9

deviate from their ideal values. As a result, the coeffi-

cients of a low-sensitivity digital filter can be implemented
with short wordlengths without violating the prescribed
specifications. Also, coefficients with short wordlengths are
cheaper, faster, and simpler to implement. It is possible to
show that low-sensitivity realizations usually generate low
Figure 9. General representation of a generic one-port network.
roundoff noise.
It is well known from classical analog circuit theory
that doubly terminated lossless filters have zero sensitiv- magnitude truncation is applied to quantize suitable sig-
ities of the transfer function with respect to the lossless nals inside the wave digital filter structure, no zero-input
components at frequencies at which the maximal power limit cycles can be sustained. Also, as will be discussed in
is transferred to the filter load. For filter approximations the section on quantization effects, the wave digital filters
with equiripple characteristics in the passband, such as are free of overflow limit cycles when simple overflow non-
Chebyshev and elliptic filters, there are several frequen- linearities are employed such as saturation arithmetic.
cies in which maximal power transfers to the load. Because The wave digital filters are also adequate to analog sys-
the ripple values are small in the passband, the sensitiv- tems simulation, such as power systems, due to their topo-
ities remain small over the frequency range consisting of logical equivalence with their analog counterparts.
the passband. As a result, several methods have been pro- An analog one-port network, see Fig. 9, can be described
posed attempting to imitate the behavior of the doubly ter- in terms of wave characterization as
minated lossless filters.
The simplest and most widely used method of transfor-
mation of a transfer function from the Laplace (s-domain)
to the z-transform domain is the bilinear transformation where a and b are the incident and reflected voltage wave
[see Eq. (52)]. This transformation is the one used to estab- quantities, respectively, and R is the port resistance as-
lish the correspondence between the analog prototype and signed to the one-port network. The value of the port re-
the wave digital filter. The bilinear transformation keeps a sistor is chosen appropriately to simplify the one-port re-
frequency domain correspondence between the analog and alization. In the frequency domain the wave quantities are
digital filters. The direct simulation of the internal quanti- A and B which are given by
ties, such as voltages and currents, of the analog prototype
in the digital domain leads to delay-free loops. A delay-free
loop does not contain any delay, and as such cannot be com-
puted sequentially since all node values in the loop are ini- In the equations above, we notice that the voltage waves
tially unknown (1). The values of the previous nodes must consist of a linear combination of the voltage and current
be known before we start computing any value in the loop. of the one-port network.
Alternative transformations can be tried; however, practice Consider now the case where the one-port impedance
has shown that it is desirable to use the bilinear transfor- consists of a single element. That is, Z(s) = csl , where l = 0
mation. As a solution a linear combination of voltage and for a resistor, l = 1 for an inductor, l = −1 for a capacitor,
current are used in the transformation from continuous to and c is a positive constant. Since
the discrete-time domain.
It is well known that any analog n-port network can
be characterized by using the concepts of incident and re-
flected waves quantities known from scattering parameter from Eq. (54), one can easily deduce the ratio between the
theory (5). Through the application of wave characteriza- reflected and incident voltage waves as follows:
tion, and the use of the bilinear transformation, digital fil-
ter realizations can be obtained from passive and active
filters as first proposed by Fettweis (6, 7). By this means,
analog filters can be converted in digital filter structures By applying the bilinear transformation, that is, by substi-
that are free from delay-free loops. The name wave dig- tuting
ital filter derives from the fact that wave quantities are
used to represent the internal analog circuit signals in the
simulation in the digital domain. The possible wave quan-
tities are voltage, current or power quantities. The choice of the digital realization of the one-port network is obtained.
power waves leads to more complicated digital realizations, However, the choice of the port resistance is crucial to ob-
whereas the choice between voltage and current waves is tain a simple realization, where in the present case the
irrelevant. Traditionally, voltage wave quantities are the choice is
choice in the open literature.
Another advantage of the wave digital filters imitating
doubly terminated lossless filters is their inherent stability
under linear conditions (i.e., infinite precision arithmetic) For the capacitor, the port resistor is chosen as R = T/2C,
as well as in the nonlinear case where the signals are sub- where T is the sample period and C is the value of the
jected to quantization. In the real-life nonlinear case, if capacitor, leading to a digital realization of the wave ratio
10 Discrete-Time Filters
Figure 10. Wave digital realization of the main one port ele-
ments.
−1
as B/A = z . For the resistor the choice is R = R, where R
is the resistor value and the resulting digital realization is
B/A = 0. Finally, the inductor is simulated by B/A = −z−1 if
R = 2L/T, where L is the inductor value. Figure 10 depicts
the realization of some important one-port elements.
Similarly an analog N-port network can be described in
terms of wave characterization as
for i = 1, . . . , N, where the parameters Ai and Bi are the in-
cident and reflected voltage wave quantities, respectively,
and Ri is the resistance of port i.
The main multiport elements required in the wave digi-
tal filter realization are the adaptors. The adaptors guaran-
tee that the current and voltage Kirchoff laws are satisfied
at the series and parallel interconnections of ports with
different port resistances.
Consider the interconnection of two elements with port
resistances given by R1 and R2 , respectively, as shown in
Fig. 11(a). The wave equations in this case are given by
Figure 11. (a) Parallel connection of two ports. (b) Realization of
two-port adaptor.
Because V1 = V2 and I1 = −I2 , we have that
If we eliminate V1 and I1 in the above equations we have
where α = (R1 − R2 )/(R1 + R2 ). A realization for the two-
port adaptor is depicted in Fig. 11(b). It should be noted
that there are other realizations for the two-port adaptor.
The same approach can be extended to derive the three-
port series and parallel adaptors. The parallel interconnec-
tion of three ports is shown in Fig. 12(a), where we have
V1 = V2 = V3 , I1 + I2 + I3 = 0, and Gi = 1/Ri . The digital
realization of the parallel adaptor has internal multipliers
whose coefficients are given by
Because α1 + α2 + α3 =2, one of the required multiplier
coefficients can be eliminated. With the definition above,
after a few manipulations one can show that a possible set
of relations between the incident and reflected waves is
given by
The realization corresponding to these equations is shown
in Fig. 12(b).

Figure 12. (a) Parallel connection of three ports. (b) A possible
realization of a three-port parallel adaptor. (c) Interconnection be-
tween two adaptors. (d) Realization of a reflection-free three-port
parallel adaptor α2 = 1 − α1 .
If two adaptors are connected directly, a delay-free loop
appears between the adaptors as shown in Fig. 12(c). A so-
lution to this problem is to constrain one of the coefficients
of the adaptor to be equal to one, for example α3 = 1. In this
case, the adaptor equations are given by
where since α1 + α2 = 1, one of the required multiplier
coefficients can also be eliminated. The realization of the
reflection-free is depicted in Fig. 12(d), where it can be ver-
ified that there is no direct path between A3 and B3 . As
a consequence, the reflection-free property of port three is
key to allow the connection between adaptors.
Discrete-Time Filters 11
Figure 13. (a) Series connection of three ports. (b) A possible
realization of a three-port parallel adaptor. (c) Realization of a
reflection-free three-port series adaptor.
The series interconnection of three ports is shown in
Fig. 13(a), where we have V1 + V2 + V3 = 0 and I1 = I2 = I3 .
The equations related to the series adaptor are derived by
following the same procedure used for the parallel adaptor.
The resulting equations are
where
for i = 1, 2, 3. The realization corresponding to these equa-
tions is shown in Fig. 13(b). The reflection-free series adap-
tor can be generated by considering β3 = 1.
As an illustration, consider the third-order elliptic low-
pass analog filter depicted in Fig. 14(a). The corresponding
wave-digital realization is shown in Fig. 14(b), where the
multiplier coefficients of the adaptors are calculated as fol-
12 Discrete-Time Filters
Figure 14. (a) LC doubly-terminated ladder; element values: C1
= C3 = 0.968F, C2 = 0.085F , L = 1.058H, R1 = R2 = 1 . (b) A possible
wave digital realization. Notice that there are other choices for the
position of the reflection-free ports. The sampling period is T = 1⁄4
s.
lows:
because
following similar procedure for the remaining elements we
have
LATTICE FILTERS
The general transfer function we aim to realize using the
lattice structure is described by
In the lattice construction, we first concentrate in the re-
alization of the denominator polynomial through an order-
reduction strategy. Define the polynomial
We calculate a reduced order polynomial as
where
Note that the first and last coefficients of DN (z) are 1 and
aN,N , whereas the first and last elements of the polynomial
zBN (z) are aN,N and 1, respectively. This strategy to achieve
the order reduction turns the polynomial DN−1 (z) monic
(i.e., with the leading coefficient equal to one).
By induction, this procedure can be repeated as de-
scribed in the following equations:
for j = N, N − 1, . . . , 0, where zB0 (z) = D0 (z) = 1.
The pair of equations above leads to a convenient rela-
tion given by:
Assuming that we can implement the desired denomi-
nator using the recursion above, it is required that we im-
plement the numerator polynomial as well. The convenient
way to form the desired numerator is to apply weights to
the polynomials zBj (z) such that:
where the tap-coefficients are calculated through the fol-
lowing order-reduction recursion:
for j = M, M − 1, . . . , 1, and v0 = b0,0 .
The overall transfer function of the lattice structure is
The recursive lattice realization derives from Eqs. (75) and
(78) in a simple way. Let us consider that the relations
represented in Eq. (75) divided by DN (z) (due to the re-
cursive structure) is implemented through a two-port net-
work. Starting with zB0 (z)/DN (z) = D0 (z)/DN (z) = 1/DN (z),
the structure of Fig. 15(a) results. Figure 15(b) depicts a
realization for the two-port network.
There are some properties related to the lattice realiza-
tion that are worth mentioning. If DN (z) has all the roots

Figure 15. (a) General lattice digital filter structure. (b) The two-multiplier realization of the two-
port network. (c) The single-multiplier realization of the two-port network. The plus and minus signs
indicates that two different realizations are possible. The choice of these signs can vary from section
to section aiming the reduction of the quantization noise at the filter output. (d) The normalized
section for the lattice structure.
inside the unit circle the lattice structure will have all coef-
ficients aj,j with magnitude less than one. Otherwise H(z)
represents an unstable system. The straightforward sta-
bility test turns the lattice realization useful to implement
time-varying filters. Also in the lattice realization, the poly-
nomials zBj (z) for j = 0, . . . , M, form an orthogonal set; this
feature justifies the choice of these polynomials to form the
desired numerator polynomial NM (z).
The overall transfer function of the lattice realization
will not change if any kind of internal scaling is applied to
the internal signals in the following way:
where the numerator coefficients have to be scaled accord-
ing to v̄j = vj /kj , with k̄j = kj kj−1 ··· k1 . Each coefficient ki is
the individual scaling factor applied to the lattice section i.
With this possibility, we can derive a more economical two-
port network using a single multiplier as shown in Fig.
15(c).
Another important realization for the two-port network
results when the scaling parameters ki are chosen such
that the polynomials zB̄j (z) become orthonormal. The ap-
propriate scaling can be easily derived by induction if we
recall that zB0 (z) = A0 (z) = 1. Since
Discrete-Time Filters 13
a polynomial with unit norm results [i.e., zB̄1 (z)] if we mul-
tiply zB1 (z) by k1 = 1/ 1 − a1,1
2
. Identically, we can easily
show that
Because zB̄1 (z) has
unit norm, zB2 (z) will have unit norm if
we choose k2 = 1/ 1 − a2,2
2
. Following a similar procedure,
we can show that
 the appropriate value for the scaling fac-
j
tor j is kj = 1/ 1 − a1, j . After a few manipulations of Eqs.
(76) and (80), we can show that the two-port section of the
normalized lattice is as depicted in Fig. 15(d). The most
important feature of the normalized lattice realization is
that all its internal nodes have unit energy leading to an
automatic scaling in the L2 norm sense. This explains the
low roundoff noise generated by the normalized lattice re-
alization as compared with the other forms of the lattice
realization.
QUANTIZATION EFFECTS IN DIGITAL FILTERS
The choice of a digital filter structure for a given application
is based on evaluating the performance of known struc-
tures and choosing the most suitable one. The effects of
quantization are important factors to be considered when
assessing the performance of digital filter structures.
14 Discrete-Time Filters

Figure 16. Model for the noise generated after a multiplication.

Quantization Noise
A number with modulus less than one can be represented
in fixed-point arithmetic as follows: Figure 17. Digital filter including scaling and the relevant trans-
fer functions for scaling, noise analysis and sensitivity calculation.

where b0 is the sign bit and b1 b2 b3 ··· bb represents the mod- A figure of merit usually employed in evaluating the
ulus of the number using a binary code. The most widely performance of digital filters is the relative power spectral
used binary code is the two’s-complement representation density (RSPD) of the output noise in decibels given by
where for positive numbers b0 = 0 and for negative num-
bers b0 = 1. The fractionary part of the number, called x2
here, is represented as
The RPSD eliminates the dependence of the output noise
on the wordlength. Hence the RPSD is a measure of the
extent to which the output noise depends upon the internal
structure of the filter.
In floating-point a number is represented as
Another useful performance criterion to evaluate the
roundoff-noise generated in digital filters is the noise gain
or the relative noise variance (1, 2) given by
where xm is the mantissa and c is the number exponent,
with ½ ≤ |xm | < 1. In floating-point arithmetic, the man-
tissa must be quantized after every multiplication and ad-
dition, whereas in fixed-point arithmetic quantization is
required only after multiplications. The main advantage
of the floating-point representation is the large dynamic
range, while fixed-point representations are easier to im-
plement. Our discussion from now on concentrates in the
fixed-point implementation.
where we used the relation
A finite-wordlength multiplier can be modeled in terms
of an ideal multiplier followed by a single noise source e(n)
as shown in Fig. 16. If the product quantization is per-
formed by rounding and the signal levels throughout the The input signal quantization is similar to product
filter are much larger than the quantization step q = 2−b , it quantization and can be represented by including a noise
can be shown that the power spectral density of the noise source at the input of the digital filter structure.
source ei (n) is given by
Granularity Limit Cycles
On many occasions, signal levels in a digital filter can be-
come constant or very low, at least for short periods of
which means that ei (n) represents a zero mean white-noise
time. Under such circumstances, the noise signals become
process. Also, we can consider that in practice ei (n) and ej (n
highly correlated from sample to sample and from source to
+ l) are statistically independent for any value of n or l (for
source. This correlation can cause autonomous oscillations
i= j). As a consequence the contributions of different noise
called granularity limit cycles.
sources can be accounted for separately using the principle
Limit-cycles oscillations can occur in recursive digital
of superposition.
filters implemented with rounding, magnitude truncation
In a fixed-point digital-filter implementation, the power
(where the magnitude of the number is reduced aiming the
spectral density of the output noise is given by
decrease of its energy), and other types of quantization.
In many applications, the presence of limit cycles can be
a serious problem. Thus, it is desirable to eliminate limit
cycles or to keep their amplitude bounds low.
where Pe (ej  ) = σ 2 e , Gi (z) are the transfer functions from For wave and lattice digital filters and some second-
each multiplier output [gi (n)] to the output of the filter as order structures, the stability under finite precision arith-
shown in Fig. 17. The wordlength, including sign, is b + 1 metic can be proved by means of the second method of Lya-
bits and K is the number of multipliers of the filter. punov. Magnitude truncation is applied to quantize suit-

Figure 18. Digital filter including quantizers at the delay inputs.
able signals inside the structure such that a defined posi-
tive definite pseudoenergy function is proved to be a Lya-
punov function.
The concept of pseudoenergy function can be applied
to show how to eliminate zero-input limit cycles in some
digital filter structures, for example, in wave, lattice, and
state-space digital filter structures. The basic strategy is
to apply magnitude truncation to the state variables of the
digital filter, namely the delay inputs. An interesting result
(11) establishes how constant-input limit cycles can also be
eliminated in digital filters in which zero-input limit cycles
can be eliminated.
In a recursive filter implemented with fixed-point arith-
metic each internal loop contains a quantizer in order to
keep the wordlength limited. Assuming that the quantiz-
ers are placed at the delay input (i.e., at the state variables
as shown in Fig. 18), we can describe the digital filter, in-
cluding the quantizers, using the state–state formulation
as follows:
where [·]Q indicates the quantized value of [·], A is the state
matrix, b is the input vector, c is the output vector, and
d represents the direct connection between the input and
output of the filter.
Given that the digital filter has a state matrix with
eigenvalues inside the unit circle such that
where G is an N × N diagonal positive definite matrix, and
û is any N × 1 vector. Then, the granular zero-input limit
cycles can be eliminated if the quantization is performed
through magnitude truncation. In this case, the quadratic
energy function given by
is used as Lyapunov function.
Overflow Limit Cycles
Overflow limit cycles can occur when the magnitude of
the internal signals exceed the available register range.
To avoid the increase of the signal wordlength in recur-
sive digital filters, overflow nonlinearities must be applied
to the signal. Overflow nonlinearities influence the most
significant bits of the signal causing severe distortion. An
Discrete-Time Filters 15
Figure 19. Regions allowed for the overflow nonlinearities in or-
der to guarantee freedom from overflow limit cycles.
Figure 20. A second-order digital filter including a granularity
and overflow quantizer.
overflow can give rise to self-sustained, high-amplitude os-
cillations known as overflow limit cycles.
A digital filter structure is considered as free of overflow
limit cycles or to have a stable forced response if the error,
which is introduced in the filter after an overflow, decreases
with time in such a way that the output of the nonlinear
filter (including the quantizers) converges to the output of
the ideal linear filter (10).
A digital filter that is free of zero-input limit cycles, ac-
cording to the condition of Eq. (92), is also forced-input sta-
ble if the overflow nonlinearities are in the shaded regions
of Fig. 19. Figure 20 illustrates a digital filter realization
incorporating a quantizer implementing rounding for the
granular quantization and saturation arithmetic for the
overflow nonlinearity.
In the presence of input signal, overflow can occur in any
digital filter structure. As a consequence, input signal scal-
ing is required to reduce the probability of overflow to an
acceptable level. Ideally, signal scaling should be applied
so as to ensure that the probability of overflow is the same
at each internal node of the digital filter, to maximize the
signal to noise ratio in fixed-point implementations.
The choice of two’s complement arithmetic leads to a
simplified scaling technique, where only the multiplier in-
puts require to be scaled. Specifically, in this type of num-
ber representation the addition of two or more numbers
will be correct independently of the order in which they
are added even if overflow occurs in a partial summation,
as long as the overall sum is within the available range of
representable numbers. In this scaling technique a scaling
multiplier is used at the input of the filter section as illus-
trated in Fig. 17. We know that the signal at the multiplier
16 Discrete-Time Filters
input is given by
where c is the convergence region common to Fi (z) and U(z).
The constant λ is usually chosen on the basis of the Lp
norm of the transfer function from the filter input to the
multiplier input Fi (z), depending on the known properties
of the input signal. The Lp norm of Fi (z) is defined as

for each p ≥ 1, such that 2π 0 |Fi (ej  )|p d ≤ ∞. In general
the following expression is valid
for p, q = 1, 2 and ∞.
The scaling ensures that the amplitudes of multiplier
inputs are bounded by a number M when |u(n)| ≤ M. There-
fore, to ensure that all multiplier inputs are bounded by M,
we must choose λ as follows
which means that
where K is the number of multipliers in the filter section.
The norm p is usually chosen to be infinity or 2. The L∞
norm is used for input signals that have some dominating
frequency component, whereas the L2 norm is most com-
monly used for random input signal. Usually, the scaling
coefficients are powers of two, provided they satisfy the
overflow constraints. In this way, the scaling parameters
can be implemented by simple shift operations.
In case of modular realizations such as cascade or par-
allel realizations of digital filters, optimum scaling is ac-
complished by applying one scaling multiplier per section.
Coefficient Quantization
During the approximation step the coefficients of a digital
filter are calculated with high accuracy. If these coefficients
are quantized, the frequency response of the realized dig-
ital filter will deviate from the ideal response. In fact, the
quantized filter may even fail to meet the prescribed spec-
ifications. The sensitivity of the filter response to errors in
the coefficients is highly dependent on the type of structure.
This fact led to the development of low-sensitivity digital
filter realizations such as the wave and lattice.
Several sensitivity criteria exist to evaluate the effect of
the variation of a coefficient value on the digital filter trans-
fer function. In this article, the sensitivity of the transfer
function H(z) with respect to variations in the multiplier
constant mi is defined as
The variation in the magnitude response of the digital
filter due to the variations in the multiplier coefficients are
approximated by
where mi , i = 1, 2, . . . , K, are the multiplier coefficients of
the digital filter. If we consider that the multiplier coef-
ficients were rounded and that the errors introduced are
statistically independent, the variance of the error in each
coefficient is given by
where b is the number of fractionary bits.
With the assumptions above the variance of |H(ej  )| is
given by
If we assume that |H(ej  )| has a Gaussian distribution, it
is possible to estimate the probability of |H(ej  )| as less
or equal to xσ|H(e j )| . The equation below estimates the
number of bits that are required in the fractionary part for
a given digital filter to meet a given modulus specification.
where ρ() is the tolerance on the magnitude response
given in the specifications Hd (ej  ).
Example:
An elliptic bandpass filter was designed satisfying the
following prescribed specifications:

Maximum ripple in the passband: 1 dB.

Minimum attenuation in the stopband: 30 dB.

Passband frequency range: 2880 to 3120 Hertz.

Stopband frequency edges: 2450 and 3550 Hertz.

Sampling frequency: 10000 Hertz.
The resulting filter has order four.
In order to access the coefficient quantization effects of
a given realization, the fourth-order elliptic filter was im-
plemented utilizing a normalized lattice structure. The co-
efficients of the lattice are displayed in Table 1. These coef-
ficients are then quantized to 12, 8 and 6 bits, respectively.
The resulting transfer functions are depicted in Figure 3.
As can be observed the transfer functions for 8 and 6 bits
deviate substantially from the desired one, whereas 12 bits
leads to acceptable results.
A procedure widely used in practice to evaluate the de-
sign of digital filters with finite-coefficient wordlength is to
design the filters with tighter specifications than required,
quantize the coefficients, and check if the prescribed spec-
ifications are still met.

Figure 21. (a) Full adder; (b) bit-parallel; (c) bit-serial adder; (d) serial/parallel multiplier.
Table 1. Normalized Lattice Coefficients
ajj vj
0 −0.31382198601433 0.01451571512296
1 −0.98733578085783 0.01127246045032
2 −0.30596231306686 −0.01164209398292
3 −0.85033475836150 −0.00464776905230
4 – 0.03432034632233
DIGITAL FILTER IMPLEMENTATION
Digital filters can be implemented by software in general-
purpose computers, in digital signal processor (DSP) chips,
or by hardware in special-purpose logic circuits. Although
software implementations allow rapid prototyping and
flexibility in testing and modifying the filter characteris-
tics, special-purpose hardware implementations allow for
higher-speed and lower-consumption performances.
A software implementation consists of generating the
program code corresponding to the digital filter structure
being implemented, in a high-level language or directly
in assembly language. A compiler then generates a set of
instructions to the processor from the code. Because, in
general-purpose computers the instructions are executed
sequentially, the speed of the digital filter becomes limited
Discrete-Time Filters 17
by the execution time of each instruction. Digital signal
processor chips are specially designed to execute very effi-
ciently sum-of-product operations, which are the main com-
putations required in the implementation of digital filters
and of other digital processing algorithms, as can be seen
in Figs. 4, 5, 6, 14, and 15. The efficient implementation
of the multiply-and-accumulate operation, as well as the
high-degree of parallelism with which the instructions are
executed in a DSP, result in a relatively high input–output
throughput rate.
A hardware implementation consists in the design and
integration of a digital circuit, specified in terms of logical
gates. Advances as well as reduction in costs of integrated
circuit technologies have made special-purpose hardware
implementations of digital filters even more attractive
for high-speed real-time applications and/or for large pro-
duction quantities. Besides providing higher-speed and
lower-power consumption, hardware implementations us-
ing VLSI (very-large-scale integration) technologies per-
mit to include in a single chip not only a digital filter but
a whole signal processing system. Arithmetic operations
required in the implementation of digital filters can be
performed either in bit-serial or in bit-parallel form. The
bit-parallel implementation of arithmetic operations uses
18 Discrete-Time Filters

a basic element the full-adder shown in Fig. 21(a), which 9. A. H. Gray, Jr. and J. D. Markel. A normalized digital filter
adds the two input-bits a and b, and the carry-in bit c, structure. IEEE Trans. Acoust. Speech Signal Process., ASSP-
resulting in a sum bit and an output carry bit. The sum 23: 268–277, 1975.
of two (b + 1)-bit numbers, A and B, in bit-parallel arith- 10. T. A. C. M. Claasen, W. F. G. Mecklenbräuker, and J. B. H. Peek.
metic can be implemented by connecting (b + 1) full-adders, On the stability of the forced response of digital filters with
one for each bit, as shown in Fig. 21(b), where ai and bi overflow nonlinearities. IEEE Trans. Circuits Syst., CAS-22:
692–696, 1975.
represent the ith bit of A and B, respectively, with ab and
bb corresponding to the least significant bits (LSB). A bit- 11. P. S. R. Diniz, and A. Antoniou. More economical state-space
digital filter structures which are free of constant-input limit
parallel implementation for the product of two numbers
cycles. IEEE Trans. Acoust. Speech Signal Process., ASSP-34:
A and B uses a full-adder for the partial sum of each bit
807–815, 1986.
product ai bk , requiring about b(b + 1) full-adders. Reduc-
tion in chip area can be achieved by using bit-serial arith-
PAULO S. R. DINIZ
metic. In such an implementation approach, the bits are
MARIANE R. PETRAGLIA
processed one at each clock period, with the LSB treated
Federal University of Rio de
first. A bit-serial adder is shown in Fig. 21(c), where D rep-
Janeiro, Rio de Janeiro,
resents a one-bit delay (or a flip-flop) and CLR is set to zero
Brazil
during the processing of the LSB. A serial/parallel imple-
Federal University of Rio de
mentation of a multiplier (for B > 0) is shown in Fig. 21(d),
Janeiro, Rio de Janeiro,
where A is treated in bit-parallel form, whereas B is pro-
Brazil
cessed in bit-serial form. More details and other implemen-
tations of bit-serial, bit-parallel, and serial/parallel arith-
metics can be found elsewhere (4). A different hardware im-
plementation approach of digital filters, called distributed
arithmetic, uses a look-up table to obtain partial results of
the required sum-of-products. Such approach uses memory
(corresponding to the look-up table) to replace most of the
circuitry required to implement the computations.
The execution speed of the operations as well as the
degree of parallelism associated to the digital filter im-
plementation determine the maximum sampling rate for
which the filter can operate. To increase this maximum
rate, block processing algorithms have been proposed,
where a block of output samples is calculated using a block
of input samples. There is a delay in the production of the
output samples in such algorithms, which might not be tol-
erable in some real-time applications. More details of block
processing algorithms are given elsewhere (2, 3).

BIBLIOGRAPHY

1. P. S. R. Diniz, E. A. B. da Silva, and S. L. Netto. Digital Sig-

nal Processing, System Analysis and Design. Cambridge, UK:
Cambridge, 2002.
2. A. Antoniou. Digital Signal Processing. New York, NY: Mc-
Graw Hill, 2006.
3. S. K. Mitra. Digital Signal Processing. New York, NY: McGraw
Hill, 3rd Edition, 2005.
4. L. Wanhammer. DSP Integrated Circuits. New York, NY: Aca-
demic Press, 1999.
5. V. Belevitch. Classical Network Theory. San Francisco, CA:
Holden-Day, 1968.
6. A. Fettweis. Digital filters structures related to classical filters
networks. Archiv. fur Elektronik und Ubertragungstechnik, 25:
79–89, 1971.
7. A. Fettweis. Wave digital filters: theory and practice. Proc.
IEEE, 74: 270–327, 1986.
8. A. H. Gray, Jr. and J. D. Markel. Digital lattice and ladder filter
synthesis. IEEE Trans. Audio Electroacoust., AU-21: 491–500,
1973.
518 DIGITAL-TO-ANALOG CONVERSION
DIGITAL-TO-ANALOG CONVERSION
FUNDAMENTALS OF D/A CONVERSION
All electrical signals in the real world are analog in nature,
and their waveforms are continuous in time. However, most
signal processing is done numerically in a sample data form
in discrete time. A device that converts a stream of discrete
digital numbers into an analog waveform is called a digital-
to-analog converter (DAC). One familiar example of a DAC
application is the CD player. Digital bits, 1s and 0s, stored in
the CD represent the electrical music waveform sampled in
discrete time. DACs inside CD players convert the digital
data stream read from optical discs into an audible sound
waveform. DACs are used as stand-alone devices or as sub-
blocks of other systems, such as analog-to-digital converters
(ADCs), and cover the frequency spectrum from subsonic to
microwave frequencies. Some examples of the systems in
which DACs play an integral role are TV monitors, graphic
display systems, digital voice/music/video systems, digital
servo controllers, test systems, waveform generators, digital
transmitters in modern digital communications systems, and
multimedia systems (1).
DAC Resolution
The basic function of a DAC is the conversion of a digital
number into an analog level. An N-bit DAC generates a dis-
crete analog output level, either voltage or current, for every
digital input word. The maximum range of the DAC is set by
the reference voltage or current. In mathematical terms, the
output of an ideal voltage DAC can be represented as
 
bN b b2 b
V0 (Di ) = + N−1 + · · · + N−1 + N1 Vr (1)
2 22 2 2
where Vr is a reference voltage setting the output range of the
DAC and bNbN⫺1 ⭈ ⭈ ⭈ b1 is the binary representation of the in-
J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.
put digital word Di. bN is the most significant bit (MSB), and
b1 is the least significant bit (LSB). The digital-to-analog
(D/A) conversion is a linear mapping of the input digital word
to the analog output. Although purely current-output DACs
are possible, voltage-output DACs are more common.
Because digital numbers are limited in length, the number
of different possible DAC output levels depends on the num-
ber of bits used to form digital input word. For example, a
DAC with two-bit digital word can have four possible outputs.
A digital number of 00 represents one possible output,
whereas 01, 10, and 11 each represents a different distinct
output. That is, the total number of the output levels of a
DAC using an N-bit long digital input word is 2N. Therefore,
the step size between the outputs created by two adjacent dig-
ital input words is Vr /2N. This value represents the minimum
voltage that can be resolved by an N-bit DAC. The resolution
of a DAC is defined as the minimum resolvable output step,
but the number of bits used for the digital input word is also
quoted as resolution. In a strict sense, it is impossible to rep-
resent an analog waveform accurately with any limited num-
ber of discrete levels. However, real applications are limited
either by noise or by other system requirements and need no
finer resolution than necessary. For example, a video signal
digitized with 8-bit resolution is sufficient for the current
video standard, whereas CD players use 16 bit data to repro-
duce music.
Static and Dynamic Performance
An ideal N-bit voltage DAC generates 2N discrete analog out-
put voltages for digital inputs varying from 000 . . . 0 to 111
. . . 1 as illustrated in Fig. 1(a) for the ideal 4 bit DAC exam-
ple. In the unipolar case, the reference point is the lowest
output of the range when the digital input D0 is 000 . . . 0.
However, in the bipolar case or in differential DACs, the ref-
erence point is the midpoint of the full scale when the digital
input is 100 . . . 0, whereas 000 . . . 0 and 111 . . . 1 repre-
sent the most negative and most positive DAC input ranges,
respectively. An ideal DAC has a uniform step size and dis-
plays a linear transfer characteristic with a constant slope.
However, in reality, the DAC transfer characteristic is far
from being ideal as shown in Fig. 1(b). First, typical DACs
have variance in step size and a curvature in the transfer
characteristic measured in terms of differential and integral
nonlinearities (DNL and INL), respectively. In addition, the
overall transfer curve shifts up or down, and the slope is dif-
ferent from the ideal one. The former is defined as offset er-
ror, and the latter as gain error.
DAC performance is limited by two factors. One is the
static linearity in representing digital numbers with a finite
number of discrete output levels, and the other is the dynamic
accuracy in the transition from one level to another. The D/A
conversion process is illustrated in Fig. 2(a) with time-domain
waveforms on the left and frequency spectrums on the right.
Figure 2(b) shows the sampled digital waveform and its spec-
trum repeating at multiples of the sampling frequency f s. Be-
cause the impulse response does not exist in the analog do-
main, the ideal D/A conversion is a sample-and-hold
operation as shown in Fig. 2(c). It is still assumed that the
DAC output is fast enough to make a step response. This sam-
ple-and-hold process exhibits a frequency response of a
(sin x)/x function. If this sample-and-held waveform is low-
 DIGITAL-TO-ANALOG CONVERSION 519

Vr Vr

INL
Analog output

Analog output
Offset
Vr Vr
2 2 DNL

1 LSB
Gain error

0 0
0000 1000 1111 0000 1000 1111
Digital input Digital input
(a) (b)

Figure 1. DAC transfer characteristics: (a) ideal case and (b) nonideal case.

Time Frequency

(a)

Time Frequency
fs

(b)

Time Frequency
fs

(c)

Figure 2. D/A conversion process: (a) input and its spectrum, (b) sampled data and its spectrum,
and (c) sample-and-held DAC output and its spectrum.
520 DIGITAL-TO-ANALOG CONVERSION
P(Q x)
1
∆
Qx
– ∆ ∆
2 2
Figure 3. Density function of the quantization noise.
pass filtered, the original signal is restored except for a gain
droop resulting from the (sin x)/x function. In practice, the
DAC output cannot change instantaneously, and real DACs
are designed to settle exponentially from one level to another.
Therefore, the dynamic performance depends heavily on the
actual implementation.
Signal-to-Noise Ratio
The lower bound in DAC resolution is set by the step size of
the minimum incremental amount of the DAC output. Ideally
this finite step size of the DAC output appears as a random
noise in the D/A conversion. It is similar to the quantization
noise of the A/D conversion process. The random noise can be
modeled as an ideal DAC with an additive random noise
source between values of ⫺Vr /2N⫹1 to Vr /2N⫹1 as illustrated in
the probability density function of Fig. 3, where ⌬ is Vr /2N.
Estimating the noise as the difference between the actual in-
put and the nearest level, the noise Qx(n) lies between
 
− ≤ Qx (n) ≤
2 2
as shown in Fig. 3. Then the average noise power ␴2 can be
calculated as
 /2
x2 2
σ2 = dx =
−/2  12
The signal-to-noise ratio (SNR) is defined as the power ratio
of the maximum signal to the inband uncorrelated noise. Be-
cause the maximum signal power is Vr2 /8, the well-known re-
lation of the noise is derived using Eq. (3) as
 
3×2 2N
SNR = 10 × log ≈ (6.02N + 1.76) dB
2 increases. The condition for monotonicity requires that the
If the number of bits increases by one, noise is lowered by
about 6 dB.
The SNR accounts for inband uncorrelated noise only. In
reality, the DAC transfer characteristic is not linear, and the
nonlinearity in the D/A conversion process appears as har-
monics or intermodulation components in the DAC output.
Considering nonlinearity, DAC performance is more accu-
rately defined using the total signal-to-noise ratio (TSNR) or
sometimes referred to as the signal-to-noise-and-distortion ra-
tio (SNDR). For an ideal DAC without nonlinearity, noise is
limited only by quantization, and SNDR should be identical
to SNR. In some applications such as generating complex
spectrums in wireless radio-frequency (RF) systems, the in-
termodulation from DAC nonlinearity is the most critical is-
sue because strong interfering tones produce inband spurious
components and degrade the inband SNR. The DAC perfor-
mance for such applications is often measured as spurious-
free dynamic range (SFDR), which is the ratio of the maxi-
mum signal component and the largest spurious component.
The INL is the key design factor for low SFDR applications.
DNL and INL
The fundamental limit of the DAC performance is SNR, but
it is more likely that DAC performance is limited by spurious
and harmonic components. The DAC nonlinearity can be mea-
sured by DNL and INL. DNL is a measure of deviation of
actual step size from the ideal size. Similarly, INL is defined
as a measure of deviation of the midpoint of the actual step
from the midpoint of the ideal step. DNL and INL are indica-
tors of how ideal a DAC is and can be defined in an N-bit
voltage DAC as
V0 (Di+1 ) − V0 (Di ) − Vr /2N
DNL(Di ) = (5)
Vr /2N
V0 (Di ) − i × Vr /2N
INL(Di ) = (6)
Vr /2N
for i ⫽ 0, 1, . . ., 2N ⫺ 1. DNL and INL are normalized to the
ideal one LSB step, and the largest positive and negative
numbers for both DNL and INL are usually quoted to specify
the static performance of a DAC.
Several different definitions of INL may result depending
on how two endpoints are defined. The two endpoints are not
(2) exactly 0 and Vr because of the offset and gain errors ex-
plained in Fig. 1(b). In most DAC applications, the offset and
gain errors resulting from the nonideal endpoints do not mat-
ter, and the integral linearity can be better defined in a rela-
tive measure using the straight-line linearity concept rather
than the endpoint linearity in the absolute measure. The
(3) straight line can be defined as two endpoints of the actual
DAC output voltages or as a theoretical straight line adjusted
to best fit the actual DAC output characteristic. The former
definition is sometimes called endpoint linearity, whereas the
latter is called best-straight-line linearity.
Monotonicity
A DAC is monotonic if its output increases as the digital input
(4)
derivative of the transfer function never change sign and that
the DNL be better than ⫺1 LSB. Monotonicity of a DAC is
important in all DAC applications, but it is a necessity in
such applications as digital control and video. The worst DNL
and INL in binary-weighted DACs usually appear at a major
transition point. The major transition point is the point at
which the MSB changes in the digital input such as between
011 . . . 1 and 100 . . . 0. If the MSB weight is smaller than
the ideal value (1/2 of the full range), the analog output
change can be smaller than the ideal step Vr /2N when the
MSB changes. If the decrease in the output is larger than one
LSB, the DAC becomes nonmonotonic. The similar nonmono-
tonicity can take place when switching the second or lower
MSB bits in binary-weighted multibit DACs.

Monotonicity is inherently guaranteed if an N-bit DAC is
made of 2N elements for thermometer decoding. However, it
is impractical to implement high-resolution DACs using 2N
elements because the number of elements grows exponen-
tially as N increases. For high-resolution DACs, four different
ways of achieving monotonicity exist. They are using the
slope-type approach, the multilevel segmented DAC ap-
proach, calibration, and the interpolative oversampling tech-
nique. The first one is to use a linear voltage ramp and to
control the time to stop digitally so that accurate voltage pro-
portional to the digital word can be obtained. Oversampling
interpolative DACs also achieve monotonicity by converting a
pulse-density modulated bitstream into analog waveform.
The slope-type DAC has a limited use in digital panel meters
and in other slow measurement uses, and it is not covered
here. However, the calibration and oversampling approaches
are covered in separate sections.
DAC ARCHITECTURES
Resistor-String DAC
A resistor string made of 2N identical resistors is a straight-
forward voltage divider. Switching the divided reference volt-
ages to the output makes a DAC as shown in Fig. 4, which
uses a 3-bit binary tree decoder. Because it requires a good
switch, the stand-alone resistor-string DAC is easier to imple-
ment using metal-oxide-semiconductor (MOS) technologies.
Resistor strings are widely used as an integral part of the
flash ADC. One major drawback of using it as a stand-alone
DAC is that the DAC output resistance depends on the digital
input word and switch on-resistance. This nonuniform set-
tling time constant problem can be alleviated either by adding
low-resistance parallel resistors or by compensating for MOS
switch overdrive voltages (2). The code-dependent settling has
no effect on the DAC performance when used as an ADC sub-
block.
Film resistors such as Tantalum, Ni–Cr, or Cr–SiO used
in bipolar process exhibit very good matching of above the 10-
1 2 3 4
V V V V
8 r 8 r 8 r
0 1 0 1
0 1
0 1
Figure 4. Resistor-string DAC.
DIGITAL-TO-ANALOG CONVERSION 521
bit level with low voltage and temperature coefficients. How-
ever, in the MOS process, such high-quality resistors are not
available. Either diffusion or undoped poly resistors are used,
and the achievable matching accuracy is below 8-bit level
with one-order higher voltage and temperature coefficients
than those of film resistors in bipolar process. Although resis-
tors are carefully laid out using large geometry, matching of
resistors in integrated circuits is still limited by the mobility
and resistor thickness variations. Differential resistor DACs
with large feature sizes are reported to exhibit higher match-
ing accuracy at the 11 to 12 bit level.
A resistor-string DAC is inherently monotonic and exhibits
good DNL, but it suffers from poor INL. For higher INL, trim-
ming or adjustment techniques are needed, but it is impracti-
cal to apply them to all 2N resistor elements. A very practical
method to improve the INL of the resistor-string DAC is to
use on-chip unity-gain buffers and to adjust voltages at inter-
mediate taps of the resistor string using conventional trim-
ming techniques. For this, the buffers require high open-loop
gain, low output resistance, large current driving capability,
and wide bandwidth for accurate and fast setting. The more
taps that are adjusted, the better integral linearity obtained.
An added benefit of this INL trimming method is the reduced
RC time constant due to the voltage sources applied to the
adjustment taps.
Binary-Weighted Current DAC
Although the resistor-string DAC is simple to make for a
small number of bits, the complexity grows exponentially as
the number of bits increases. Binary-ratioed elements are
simpler to use for a large number of bits. One of the simplest
DAC architectures using the binary-weighted current sources
is shown in Fig. 5 (3). It is the most popular stand-alone DAC
architecture in use today. In bipolar technology, transistors
and emitter resistors are ratioed with binary values as
shown. In MOS technology, only ratioed transistors are used
as in, for example, a video random-access-memory (RAM)
DAC that is made up of simple PMOS differential pairs with
5 6 7
V V V
8 r 8 r 8 r 8 r
Vr
0 1 0 1
b1 = 1
0 1
b2 = 0
b3 = 1
+
Out
–
522 DIGITAL-TO-ANALOG CONVERSION

–
Out
+

bN bN bN–1 bN–1 b3 b3 b2 b2 b1 b1

Ir Ir Ir Ir Ir
2 4 2 N–2 2 N–1 2N

Vb

×2 N–1 ×2 N–2 ×4 ×2 ×1

2R 4R 2N–2R 2N–1R 2 NR

Figure 5. Binary-weighted current DAC.

binary-weighted tail currents. Although MOS DACs exhibit 8
bit level matching using 10 to 20 애m device size, bipolar
DACs are known to have above 10-level matching using thin-
film resistors. The current sources are switched on or off ei-
ther by means of switching diodes or differential pairs as
shown. The output current summing is done by a wideband
transresistance amplifier, but in high-speed DACs, the output
current is used directly to drive a resistor load.
Although binary weighting reduces circuit complexity, the
number of transistors and resistors still grows exponentially
because a unit component is repeatedly used for good match-
ing. This complexity problem is alleviated using another type

Io

–
Out
Id +

bN bN bN – 1 bN – 1 b3 b3 b2 b2 b1 b1

Ir Ir Ir Ir Ir
N–2 N–1
2 4 2 2 2N

2R 2R 2R 2R 2R

R R R R 2R
–Vr
A B C D
Figure 6. R–2R DAC.

2 N – 1C 4C 2C C +
bN bN b3 b3 b2 b2 b1 b1
–Vr
of current-ratioed DAC known as R–2R DAC shown in Fig. 6.
The R–2R network consists of series resistors of value R and
shunt resistors of value 2R. Each shunt resistor 2R has a sin-
gle-pole double-throw electronic switch that connects the re-
sistor either to ground or to the output current summing
node. The operation of the R–2R ladder network is based on
the binary division of current as it flows down the ladder. At
any junction of series resistor R, the resistance looking to the
right side is 2R. Therefore, the input resistance at any junc-
tion is R, and the current splits equally into two branches at
the junction because it sees equal resistances in both direc-
tions. The advantage of the R–2R ladder method is that only
two values of resistors are used, greatly simplifying the task
of matching or trimming and temperature tracking. Also, for
high-speed applications, relatively low-valued resistance can
be used for even more savings in the chip area. The major
disadvantage of this architecture is the nonmonotonicity and
high nonlinearity due to poor matching in fabricated resis-
tors. The R–2R DAC is a multiplying DAC (MDAC) that has
an output proportional to the product of the reference voltage
and the digital input word.
Binary-Weighted Capacitor-Array DAC
Capacitors made of double-poly or poly-diffusion in the MOS
process are known to be very accurate passive components
comparable to film resistors in the bipolar process both in the
matching accuracy and voltage and temperature coefficients.
The binary-weighted capacitor-array DAC is shown in Fig. 7.
The DAC is made of a parallel capacitor array of N capacitors
with a common top plate (4). Unlike DACs using resistors and
currents, the capacitor-array DAC is based on a dynamic
charge redistribution principle. Therefore, it is not convenient
to use it in continuous-time applications, and for stand-alone
applications, a resettable feedback amplifier periodically
charging the top plate of the array and an output S/H or deg-
litcher are needed. The capacitor array is known to give a 10-
bit level matching for this use. The matching accuracy of the
capacitor in MOS technology depends on the geometry sizes
of the capacitor width and length and the dielectric thickness.
As a stand-alone DAC, the top plate of the DAC is pre-
charged either to the offset of the feedback amplifier or to the
DIGITAL-TO-ANALOG CONVERSION 523
Reset
2 NC
–
Out
Figure 7. Binary-weighted capacitor-
array DAC.
ground. One extra smallest C is not necessary for DAC as
shown in Fig. 7, but as a subblock of an ADC, it is needed to
make the total capacitance of 2NC. Because the top plate is
connected to the summing node, the top plate parasitic capac-
itance has a negligible effect on the DAC performance. The
capacitor-array DAC requires two-phase nonoverlapping
clocks for proper operation. Initially, all capacitors should be
charged to ground. After initialization, depending on the digi-
tal input, the bottom plates are connected either to ⫺Vr or to
ground. Then the output is the same as given by Eq. (1). Like
the R-2R DAC, the capacitor-array DAC can be used as an
MDAC.
Monotonic Segmented DACs
As discussed in the previous section, a DAC system is greatly
simplified using a binary-weighted DAC and binary input
word, but monotonicity is not guaranteed. For monotonicity,
the DAC needs to be thermometer-coded. Three examples of
thermometer-coded DACs are shown in Fig. 8 for resistor,
current, and capacitor-array DACs. Their operation is the
same except for the thermometer-coded input. Because each
segment is individually represented by a unit element, the
DAC output should increase as a new unit element is
switched in as the thermometer-code input increases by one.
This guarantees monotonicity, but the problem is an exponen-
tial increase in the complexity as the number of bits in-
creases.
Applying a two-step conversion concept, a monotonic DAC
can be made using coarse and fine DACs. The fine DAC di-
vides the next MSB segment into fine LSBs. Two examples of
the monotonic-segmented approach exist. One is a combina-
tion DAC, and the other is the most widely used next-segment
approach. Because it is difficult to achieve fine resolution us-
ing one DAC, both approaches use two separate DACs. The
R ⫹ C combination DAC uses two different DAC types to
achieve two-level D/A conversion as shown in Fig. 9. The
MSB resistor-string DAC supplies the reference voltages to
the LSB capacitor-array DAC. When the top plate is initial-
ized, all capacitor bottom plates are connected to the higher
voltage of the next segment of the resistor-string DAC. Dur-
ing the next clock phase, the bottom plates of capacitors are
524 DIGITAL-TO-ANALOG CONVERSION

R R R R R R R
Vr

0 1 2 3 2N – 3 2N – 2 2N – 1

Thermometer-
coded N bits

+
Out
–

(a)

–
Out
+

0 1 2 3 2N – 3 2N – 2 2N – 1
Thermometer-
I I I I I I I coded N bits

(b)

Reset

2 NC

–
Out
C C C C C C C +

0 1 2 3 2N – 3 2 N– 2 2N – 1

Thermometer-
coded N bits

Figure 8. Thermometer-coded monotonic

DACs: (a) resistor, (b) current, and (c) ca- –Vr
pacitor arrays. (c)

selectively connected to the lower voltage of the segment if
the digital bit is 1 but stay switched to the higher voltage if
0. This segmented DAC approach guarantees inherent mono-
tonicity as far as the LSB DAC is monotonic within its resolu-
tion. However, INL is still poor because the MSB is set by
the resistor string. Fully differential implementation of this
architecture is known to benefit from the lack of the even-
order nonlinearity and to achieve high INL.
The same idea used in the R ⫹ C combination DAC can be
implemented using two DACs of the same type. A segmented
DAC with total N bits is shown in Fig. 10. For monotonicity,
the MSB M bits are selected by a thermometer code, but one
of the MSB current sources corresponding to the next seg-
ment of the thermometer code is divided by a current divider
for the fine LSBs. As in the R ⫹ C capacitor array, the fine
DAC divider should have a monotonicity of N ⫺ M bits. Al-
though monotonicity is guaranteed with modest matching re-
quirement, it is still limited in INL due to the limited match-
ing accuracy in the MSB. This segmented current DAC, with
and without trimming, is the most widely used DAC archi-
tecture.
DAC CONVERSION ACCURACY
DAC performance is directly affected by static linearity and
dynamic settling. The former is limited by the matching accu-
 DIGITAL-TO-ANALOG CONVERSION 525

Reset

2 NC
Vr

R –
Out
2 N – 1C 4C 2C C +

bN bN b3 b3 b2 b2 b1 b1

R
Thermometer-coded
M MSBs Figure 9. R ⫹ C combination monotonic
DAC.

racy of passive or active components, and the latter is limited
by nonideal settling. When a DAC is used in the feedback
path of an ADC, the DAC linearity also affects the ADC lin-
earity. In ADC applications, the number of bits per stage is
determined by how many bits are resolved in the DAC, de-
pending on ADC architecture. However, the dynamic DAC
settling requirement in ADCs is less stringent than those
used as stand-alone devices. As explained in Fig. 2, stand-
alone DACs should settle either infinitely fast or purely expo-
nentially in making transitions from one level to another.
Because fast settling is not possible except for extremely low-
speed DACs, most DAC output should settle exponentially
with a well-defined time constant. Main sources for nonideal
dynamic settling errors are slew, glitch, and clock jitter.
Element Matching
Mismatch between elements occurs because of parasitic ele-
ments, uncertainties in the size of drawn shapes, and other
varying process parameters. There is typically about ⫾0.2%
mismatch between two resistors of the same value drawn
with a length of 10 to 20 애m. For similar reasons, capacitors

–
Out
+

Binary N–M bits

÷2 ÷4 ÷2N–M ÷2N–M

N–M bit current divider

Thermometer coded M bits

Ir Ir Ir Ir Ir
2M 2M 2M 2M 2M

Segments Next Segments

to output segment dumped

Figure 10. Two-level segmented monotonic DAC.

526 DIGITAL-TO-ANALOG CONVERSION

15

Time
Number of occurrences

10

(a)

5
Time

0 (b)
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07
Figure 12. DAC transient errors: (a) settling and (b) slew.
DNL (LSB)

20
one value to another is an exponential function. High-speed
18 DACs usually have a current output, and the output is usu-
ally terminated with a 50 or 75 ⍀ low-impedance load. There-
16 fore, the current output DAC can be designed so that the out-
put may settle exponentially with a fixed time constant.
Number of occurrences

14
However, for voltage output DACs, either a transconductance
12 amplifier or a sample-and-hold amplifier is used as a buffer
amplifier. In general, all amplifiers slew to a certain degree if
10 a large transient signal is suddenly applied to the input. Fig-
8 ure 12 shows two waveforms with transient errors resulting
from exponential settling and slew limiting.
6 In the exponential-settling case, the transient error de-
fined by the shaded area is proportional to the height of the
4 jump. This implies that any single time-constant settling does
2 not produce any nonlinearity error. In reality, amplifiers set-
tle with multiple poles although one of them is dominant. To
0 see this effect, consider a two-pole settling case. The transient
0 0.5 1 1.5 2 2.5
error can be calculated as follows:
INL (LSB)
 
τ12 τ22
Figure 11. Simulated DNL and INL of a 12-bit DAC with 0.1% com- Transient error = h + (7)
ponent matching. τ1 − τ2 τ2 − τ1

where ␶1 and ␶2 are the two time constants. As in the single

and transistors also show mismatch due to process variations. time-constant case, the transient error is a linear function of
The effect of component mismatch appears as static nonline-
arity. Because of statistical randomness of the process varia-
tion, the mismatch effect on the DAC performance can be bet- 75
ter understood using statistical Monte Carlo analysis. Figure
11 show the distribution characteristics of DNL and INL of a 70
12-bit segmented DAC with 1% random mismatch in current
sources and the next-segment divider. The 12 bits are parti- 65
SNDR (dB)

tioned into four thermometer-coded MSBs and binary-

weighted 8-bit LSBs. The x-axes for both graphs are in units 60
of LSB, whereas the y-axes represent the total number of oc-
currences out of 100 samples. The segmented DAC architec- 55
ture guarantees monotonicity regardless of the amount of
50
mismatch in the elements. There exist many samples with
INL greater than 1 LSB, but no DNL exceeds 1 LSB. 45
0.5 1 1.5 2 2.5
Slew and Settling Normalized slew rate
The output of a DAC is a sampled step waveform held con- Figure 13. SNDR degradation of a 12-bit DAC due to limited slew
stant during a word clock period. The ideal transition from rate.
 DIGITAL-TO-ANALOG CONVERSION 527

0.6

0.4
Magnitude (V)
0.2

– 0.2

– 0.4

500 1000 1500 2000 2500 3000 3500 4000

(a)

0.1

0.08
Magnitude (V)

0.06

0.04

0.02

0
0 10 20 30 40 50 60 70 80 90 100
(b)

SNR = 75.44 dB SDR = 80.17 dB SNDR = 74.18 dB

0

-20

-40
Magnitude (dB)

-60

-80

–100

–120
0 100 200 300 400 500 600 700
(c)

Figure 14. 12 bit DAC output with two poles: (a) time waveform, (b) its detail, and (c) its FFT.

h, and the preceding result implies that the two-pole settling where Tc is the clock period (5). For a given distortion level,
generates only linear errors and will not affect the DAC lin- the minimum slew rate is given. Any sinusoidal waveform
earity. has a maximum slew rate of 웆0V0 at the zero-crossing point.
However, in the latter slew-limited case, the area is pro- Therefore, if a DAC has a slew rate much higher than this
portional to h2. From the simple slewing distortion model, the maximum slew rate, the DAC output will exhibit negligible
worst case harmonic distortion (HD) when generating a sinus- slew-limited distortion. The summary plot of the SNDR vs.
oidal signal with a magnitude V0 with a limited slew rate of slew rate of a 12 bit DAC example is shown in Fig. 13, where
S is the x-axis unit is normalized to the maximum slew rate of the
sinusoidal waveform. As expected from Eq. (8), the SNDR is
ωTc proportional to the slew rate. Figures 14 and 15 show the
sin2
HDk = 8 2 × V0 , k = 1, 3, 5, 7, . . . (8) simulated output spectrums of a 12-bit DAC for two cases.
πk(k2 − 4) STc One is the two-pole settling case, and the other is the slew-
528 DIGITAL-TO-ANALOG CONVERSION

0.6

0.4

Magnitude (V)
0.2

– 0.2

– 0.4

500 1000 1500 2000 2500 3000 3500 4000

(a)

0.1

0.08
Magnitude (V)

0.06

0.04

0.02

0
0 10 20 30 40 50 60 70 80 90 100
(b)

SNR = 71.55 dB SDR = 56.55 dB SNDR = 56.42 dB

0

–20

–40
Magnitude (dB)

–60

–80

–100

–120
0 100 200 300 400 500 600 700
(c)

Figure 15. 12 bit DAC output with slew limit: (a) time waveform, (b) its detail, and (c) its FFT.

limited case. As predicted in Fig. 13, the SNDR of the former
case stays high at 74 dB, whereas the latter case suffers from
lower SNDR of 56 dB. The harmonics of the input increase
drastically in the slew-limited case.
One more nonideal factor that contributes to the settling
of a DAC is the parasitic capacitance. The parasitic capaci-
tance of the current sources shifts the poles to display a code-
dependent time constant. As a result, the dominant pole of
a DAC varies according to input digital words. Because the
parasitic capacitances are additive, the higher output levels
where more current sources are switched on can exhibit a
slower settling time than that of lower output levels.
Glitch and Clock Jitter
Ideally, all bits of the digital input word should switch at the
same time so that any change in the digital word can be re-
flected in the analog output waveform simultaneously. How-
ever, even with the use of an input data latch to synchronize
the digital word, different data paths cause a slight variation

MSB switches on early
MSB switches off late
Time
MSB switches on late
MSB switches off early
(a)
Time
Clock jitter
(b)
Figure 16. Effects of (a) MSB glitch and (b) clock jitter.
in the switching time of the digital bits. This phenomenon
causes a glitch in the output and affects the performance of
the DAC. For example, at the major code transition in a bi-
nary-weighted DAC, the digital word changes from 011 . . .
1 to 100 . . . 0. If all bits change simultaneously, then the
output should increase exponentially by one LSB step. How-
ever, due to the slight time differences between switching of
the digital bits, there may be an instance where the MSB bit
switches on before the rest of the digital bits turn off, thus
creating the appearance of the digital word 111 . . . 1 even
momentarily. This will cause a positive spike in the output as
shown in Fig. 16(a). Similarly, there may be an instance when
the MSB switches on after the remaining digital bits turn off,
thus creating the appearance of digital word 000 . . . 0. This
will cause a downward trough in the output as shown. The
same glitch occurs when the MSB switches off.
Obviously this situation is the worst case. A more realistic
glitch spike and its effect on the output spectrum is shown in
Fig. 17 where 5% glitch is simulated for the same 12-bit DAC
with a sinusoidal input. The frequency spectrum of the output
with glitches exhibits an elevated noise floor. Although a few
techniques such as segmented antisymmetric switching have
been proposed to alleviate the glitch problem, an easier solu-
tion is to employ a sample-and-hold amplifier at the DAC out-
put as a deglitcher. The basic idea of deglitching is to keep
the DAC in the hold mode until all the switching transients
have settled. If the deglitcher is faster than the DAC, the slew
rate limitation may improve. However, if the slew rate of the
deglitcher is of the same order as the DAC, the slew distortion
will still exist, now as an artifact of the deglitcher.
Another major source of conversion error is the nonideal
clock jitter. The glitch results from the switching time differ-
ence of digital bits while the clock jitter results from the ran-
domness of the clock edge itself. The clock jitter generates
errors as explained in Fig. 16(b). The right signal at the
wrong time is the same as the wrong signal at the right time.
DIGITAL-TO-ANALOG CONVERSION 529
Even if the output waveform is correctly generated from the
input word, the timing error will raise the noise floor of the
DAC. If the jitter has a Gaussian distribution with a root-
mean-square jitter of ⌬t, the worst-case SNR resulting from
this random word clock is
2π f t
SNR = −20 × log √ (9)
M
where f is the signal frequency and M is the oversampling
ratio. The timing jitter error is more critical in reproducing
high-frequency components. In other words, to make an N-bit
DAC, an upper limit for the tolerable word clock jitter is

1 2M
Jitter < (10)
2πB2N 3
The simulated spectrum of a 12 bit DAC with 5% clock jitter
is shown in Fig. 18. The effect is about the same as the glitch
case. Figure 19 shows the SNDR of the same 12 bit DAC as
functions of glitch and clock jitter percentages of the sampling
period. It clearly demonstrates that the SNDR decreases as
both glitch and clock jitter effects become more significant.
HIGH-RESOLUTION TECHNIQUES
The current trend of high resolution at high frequencies has
stimulated many innovative DAC developments. Although
there may be numerous approaches in making high-resolu-
tion DACs, only two distinctive approaches need special men-
tioning. They are the monotonic segmented approach and the
oversampling interpolative approach. The former is exclu-
sively used for high-speed DACs, but the oversampling ap-
proach is dominant at low-speed applications such as for in-
strumentations, digital audio, and digital communication
channels. For high-resolution DACs, bipolar and bipolar-
CMOS (BiCMOS) DACs are superior to bulk complementary
MOS (CMOS) counterparts in speed. In nonoversampling
DACs, linearity of more than 12 b requires resolution-enhanc-
ing methods such as trimming, dynamic matching, and elec-
tronic calibration.
Trimming
Component matching is limited by many variations in physi-
cal dimensions and process parameters. The effect of random
size variation is reduced using physically large dimension.
Careful layout using common centroid or geometric averaging
can also reduce the process gradient effect. However, it is pos-
sible to further improve component matching by trimming on
the wafer in a post-fabrication process. Resistor value can
be either laser trimmed (6), Zener-zapped (7), or electroni-
cally controlled by switches using programmable read-only-
memory (PROM) and erasable PROM (EPROM). The laser-
trimming and the Zener-zapping processes are nonreversible.
The long-term stability of trimmed resistors is a major con-
cern, although electronical trimming using EPROM can be re-
peated.
The laser-trimming method involves using a focused laser
beam to melt away part of the resistors to change their val-
ues. The precision required in the process and the irreversibil-
ity of the process make this option expensive. Because laser
530 DIGITAL-TO-ANALOG CONVERSION

0.6

0.4

Magnitude (V)
0.2

– 0.2

– 0.4

500 1000 1500 2000 2500 3000 3500 4000

(a)

0.14

0.12
Magnitude (V)

0.1

0.08

0.06

100 110 120 130 140 150 160 170 180 190 200
(b)

SNR = 56.09 dB SDR = 56.33 dB SNDR = 53.20 dB

0

–20

–40
Magnitude (dB)

–60

–80

–100

–120
0 100 200 300 400 500 600 700
(c)

Figure 17. 12 bit DAC output with 5% glitch: (a) time waveform, (b) its details, and (c) its FFT.

trimming is continuous, very accurate measurement tools are
needed to detect low levels of mismatch. The Zener-zapping
method creates a resistor of desired value by inserting a se-
ries of small incremental resistors and by selectively by-
passing them. Zener diodes connected in parallel with resis-
tors are melted with short current pulses over hundreds of
milliamperes. Fusible aluminum links are also used in this
discrete trimming technique. Like laser trimming, the Zener-
zapping method is also irreversible and requires precision
equipment to measure matching errors. Furthermore, the sta-
bility of the trimmed values over a long period of time is still
in question. The new trend is toward a more intelligent solu-
tion that involves the ability to recalibrate on demand by
moving the error measurement process on-chip.
Dynamic Matching
The idea of dynamic matching is to improve the matching ac-
curacy by time-averaging two component values (8). Figure
20 explains how the dynamic-matching technique can be ap-
plied to current dividers. Assume that two current sources are
mismatched by ⌬. By commuting the two currents I1 and I2 at
 DIGITAL-TO-ANALOG CONVERSION 531

0.6

0.4

Magnitude (V)
0.2

– 0.2

– 0.4

500 1000 1500 2000 2500 3000 3500 4000

(a)

0.1

0.08
Magnitude (V)

0.06

0.04

0.02

0
0 10 20 30 40 50 60 70 80 90 100
(b)

SNR = 57.11 dB SDR = 60.05 dB SNDR = 55.33 dB

0

–20

–40
Magnitude (dB)

–60

–80

–100

–120
0 100 200 300 400 500 600 700
(c)

Figure 18. 12 bit DAC output with 5% jitter: (q) time waveform, (b) its detail, and (c) its FFT.

high speed to two new output ports with a 50% duty, the mis-
match error ⌬/2 will be modulated by the high clock fre-
quency. If these are lowpass filtered, the average current I
will come out of the two terminals. This dynamic matching
can be generalized for a large number of matching compo-
nents using the butterfly-type randomizer as shown in Fig. 21
for the four-element matching case. The switches are con-
trolled so that the four outputs can be the average of the four
currents. In this case, the modulating frequency is half of the
clock frequency. For matching a large number of elements,
this fixed pattern noise moves to lower frequencies. To reduce
this pattern noise, the clock frequency should be raised or the
lowpass filters should have a sharper cutoff slope. A more so-
phisticated randomizer selects the switching path randomly
with an equal probability to each output terminal using a
pseudorandom number generator. This general randomizer
can distribute mismatch errors over a wider frequency range.
At least an order of magnitude improvement is achieved using
the dynamic matching element method.
An alternative concept to dynamic matching is to replicate
current or voltage unit element. The idea is to copy one mas-
ter voltage or current repeatedly on voltage or current sam-
532 DIGITAL-TO-ANALOG CONVERSION

80 1,2,3,4
1 LPF 1+2+3+4
75

70 2,3,4,1
2 LPF 1+2+3+4
SNDR (dB)

65
3,4,1,2
60 3 LPF 1+2+3+4
55
4,1,2,3
4 LPF 1+2+3+4
50

45 Figure 21. Butterfly-type randomizer.

0 1 2 3 4 5 6 7 8 9 10
Glitch (%)
(a)

80 is limited to N bits, it is equivalent to having passive compo-

nents matching of N bits. Note that voltage and current sam-
75 pling schemes alone are not sufficient enough to make a high-
70 resolution DAC. This approach is generally limited to creating
SNDR (dB)

MSBs for segmented DACs or for multistep ADCs. The

65 amount of time required to copy one master source repeatedly
60 but accurately makes it impractical for high-speed DAC appli-
cations.
55

50
Electronic Calibration
45
0 1 2 3 4 5 6 7 8 9 10 Calibration is another alternative to the trimming and dy-
Jitter (%) namic matching methods. It has become an intelligent elec-
(b) tronic solution preferred to the factory trimming process. The
electronic calibration predistorts the DAC transfer character-
Figure 19. SNDR vs. (a) glitch and (b) clock jitter. istic so that the DAC linearity can be improved. DAC nonline-
arity errors are measured and stored in memory. Later dur-
plers so that the sampled ones can be used to ratio elements. ing normal operation, these errors are subtracted from the
The voltage is usually sampled on the holding capacitor of DAC output. Error subtraction can be done either in the ana-
sample-and-hold amplifier, and the current is sampled on the log domain or in the digital domain. Calibration methods dif-
gate of the MOS transistor (9). This sampling method is ulti- fer from one another in the measurement of nonlinearity er-
mately limited by sampling errors. If the sampling accuracy rors. The most straightforward method is a direct code-
mapping technique. All DAC code errors must be measured
and stored in ROM. This method is limited because it re-
I I quires precision measurements and large digital memory. A
more robust way of calibrating a DAC electronically is self-
calibration. This incorporates all the calibration mechanisms
LPF and hardware on the DAC as a built-in function so that users
can recalibrate whenever calibration is necessary.
∆
I– ∆ Self-calibration is based on the assumption that the seg-
I1 I2 I+
2
2 mented DAC linearity is limited by the MSB matching so that
I1 I
only errors of the MSBs can be measured, stored in memory,
and recalled during normal operation. There are two different
φ1 φ2
methods of measuring the MSB errors. In one method, indi-
vidual binary bit errors, usually appearing as component mis-
I2 I match errors, are measured digitally (10). The total error,
I+∆
I– ∆ 2 which is called a code error, is computed from individual-bit
2 errors depending on the digital code during normal conver-
I+ ∆ I– ∆ sion. The other method measures segment errors and accu-
2 2
mulates them to obtain code errors. Because code errors are
stored in memory, there is no need for the digital code-error
computation during normal operation (11). The former re-
Figure 20. Dynamic matching of two currents and modulated two quires less digital memory, whereas the latter requires fewer
currents. digital computations.

+ the current difference as shown in Fig. 23. The calibration
V1 R1
Calibration
– DAC
Up/
+ down
V2 R2
– with a few widely spaced levels and interpolating values be-
Figure 22. Resistor ratio calibration scheme.
Two examples of DAC ratio measurements are conceptu-
ally explained in Figs. 22 and 23. In the resistor ratio mea-
surement of Fig. 22, the voltage across the two resistors is
sampled on the capacitors, and the comparator is nulled. Dur-
ing the next cycle, the capacitor bottom plates are connected
to the center point to sense the difference of V1 and V2. The
comparator decision will move the center tap connected to the
fine calibration DAC. This capacitive sensing is limited by the
capacitor-matching accuracy between C1 and C2. To average
out this capacitor mismatch error, the same measurement can
be repeated with C1 and C2 swapped. The final center tap is
Calibration DAC
Up/
down
I1 I2
Figure 23. Current ratio calibration scheme.
DIGITAL-TO-ANALOG CONVERSION 533
set to the average of the two tap values obtained with the two
measurements. The same principle can be applied to measure
DAC measures I1 first using the up/down converter and
moves on to measure I2. The difference between the two mea-
surements is the current mismatch error.
INTERPOLATIVE OVERSAMPLING TECHNIQUE
All DACs have a discrete output level for every digital input
word applied to their input. Although digital numbers can
grow easily, generating a large number of distinct analog out-
put levels is a difficult task. The oversampling interpolative
DAC achieves fine resolution by covering the signal range
tween them. Rapid oscillation between coarse output levels is
controlled so that the average output may represent the ap-
plied digital word with reduced noise in the signal band (12).
This process is a tradeoff between speed and resolution. The
oversampling idea is to achieve high resolution with less accu-
rate component matching and has been most widely used to
make DACs that need high resolution at low frequencies.
The interpolative oversampling DAC architecture is shown
in Fig. 24. A digital interpolator raises the word rate to a
frequency well above the Nyquist rate for oversampling. The
interpolated data stream is applied to a digital truncator to
shorten the word length. This data stream of shorter words,
usually a one-bit stream, is converted into analog waveform
at the oversampling rate. This oversampled output has a low
truncation error in the signal band, and the out-of-band trun-
cation noise is filtered out using analog low-pass filter (LPF).
Figure 25 illustrates this oversampling D/A conversion
process.
The sampling rate upconversion for this is usually done
using two upsampling digital filters. The first filter, usually a
two to four times oversampling FIR filter, shapes the signal
band for sampling rate upconversion and equalizes the pass-
band droop resulting from the (sin x)/x filter for higher-rate
oversampling. The truncator is made of a feedback system
called a delta-sigma modulator that pushes the truncation er-
ror out to high frequencies while passing the signal band un-
attenuated. Using a linearized model, the z-domain transfer
function of the general digital truncator shown in Fig. 24 is
H(z) 1
V0 (z) = V (z) + E(z) (11)
1 + H(z) i 1 + H(z)
where E(z) is the truncation error. The loop filter H(z) is cho-
sen so that the truncation error may be high-pass filtered
while the input signal is low-pass filtered. The order of noise
shaping depends on the order of H(z).
The oversampling effect begins to appear when the
oversampling ratio is larger than 2. The noise of the Nth-or-
der loop is suppressed by 6N ⫹ 3 dB for every doubling of the
sampling rate, providing N ⫹ 0.5 extra bits of resolution.
Therefore, the dynamic range achievable by oversampling is
Dynamic range ≈ (6N + 3)(log2 M − 1) dB (12)
where M is the oversampling ratio between the sampling fre-
quency and twice the signal bandwidth. For example, a sec-
534 DIGITAL-TO-ANALOG CONVERSION
M M
Digital Interpolation
in filter, K
fs fs
K
M + M+1
Σ H(z)
–
Figure 24. Interpolative oversampling DAC system.
ond-order loop with 256 times oversampling gives a dynamic
range of over 105 dB, but the same dynamic range can be
obtained using a third-order loop with only 64 times oversam-
pling.
Digital Truncator
A noise-shaping delta-sigma modulator for digital truncation
can be built in many different ways. The simplest three exam-
ples are shown in Fig. 26. The first-order loop shown in Fig.
26(a) outputs only N MSBs out of M ⫹ 1 bits from the inte-
grator output. The remaining truncation error of M ⫺ N ⫹ 1
is fed back to the digital integrator along with the input.
Therefore, the output of the first-order modulator becomes
Y (z) = z−1 X (z) − (1 − z−1 )E(z)
This implies that the input appears at the output just de-
layed, but the truncation error in the integrator loop is high-
pass filtered with one zero at dc.
In general, first-order designs tend to produce correlated
idling patterns and require a high oversampling ratio to sup-
press inband truncation noise effectively. By increasing the
order of the error transfer function, the inband truncation er-
ror can be suppressed with steeper-slope high-pass filter. The
standard second-order modulator can be implemented as
shown in Fig. 26(b) using a double integration loop. The out-
put of the second-order modulator becomes
−2 −1 2
Y (z) = z X (z) + (1 − z ) E(z)
This second-order modulator is vastly superior to the first-
order one both in terms of the oversampling ratio and the
improved randomness of the idling patterns. However, even
the second-order loop is not entirely free of correlated fixed
patterns in the presence of small constant inputs. If loop or-
der is higher than 3, fixed pattern noise does not exist. High-
order modulators can be implemented using the same method
as in the standard filter design (13).
N << M
usually N = 1
N
Truncation DAC Analog
Analog
loop LPF
fs out
M+1 N
Digital
truncator
N
Another variation of the high-order modulator is the cas-
cading method (14). Rather than using error feedback, modu-
lators can be cascaded to reduce the truncation noise in the
same way. Figure 26(c) shows a second-order cascade modula-
tor example. The truncation error E1 of the first modulator is
modulated again using another first-order modulator. If the
truncation error of the second modulator is E2, the outputs of
the two modulators Y1 and Y2 become
Y1 (z) = z−1 X (z) − (1 − z−1 )E1 (z) (15)
Y2 (z) = z−1 E1 (z) − (1 − z−1 )E2 (z) (16)
respectively. The two outputs are added after they are
multiplied by z⫺1 and 1 ⫺ z⫺1, respectively. Then the final out-
(13) put becomes
Y (z) = z−2 X (z) − (1 − z−1 )2 E2 (z) (17)
This is the same second-order modulator output given by
Eq. (14). The problem with the cascading approach is that
the output word is always longer than 2, even though two
cascaded modulators have one-bit output (N1 ⫽ N2 ⫽ 1).
That is, the higher-order noise shaping is possible with
cascading, but error occurs in the output D/A conversion.
The multibit output DAC requires the same accuracy as
conventional DACs.
One-Bit Switched-Capacitor DAC/Filter
(14) Digital processing for modulation and filtering is not limited
in accuracy. However, all oversampling DACs are followed by
an analog DAC and an analog low-pass filter, and DAC per-
formance depends entirely on the rear-end analog compo-
nents. The idea of oversampling to alleviate the component-
matching requirement for high resolution does not apply to
multibit DACs. Therefore, most oversampling DACs are de-
signed with one-bit output. It is true that a continuous-time
low-pass filter can convert the one-bit digital bitstream into
an analog waveform, but it is difficult to construct an ideal
 Frequency
(a)

···
Frequency
fs fs
K
(b)

Frequency
fs

(c)

Frequency
fs

(d)

Frequency
fs

(e)

Frequency
fs

(f)

Frequency
fs

(g)

Frequency
(h)

Frequency
(i)

Figure 25. Oversampling D/A conversion: (a) input spectrum, (b) sampled spectrum, (c) interpo-
lation filter, (d) interpolated spectrum, (e) noise-shaped spectrum, (f) sample-and-hold frequency
response, (g) sample-and-held spectrum, (h) low-pass filter, and (i) DAC output.

535
536 DIGITAL-TO-ANALOG CONVERSION

M + M+1 M+1 N
X Σ z–1 Y

+
E
M–N+1

(a)

M + + + + E N
X Σ Σ z–1 Σ Σ z–1 Y

– + – +

M+2 M+4
2

N
(b)

M + N1 Y1 +
X Σ z–1 z–1 Σ Y

+ M – N1 + 1 +
E1

+
N2 Y2
Σ z–1 1– z–1
+
E2

M – N1 + N2 + 2

(c)

Figure 26. Digital truncators: (a) first-order loop, (b) second-order loop, and (c) cascaded archi-
tecture.

undistorted digital waveform without clock jitter. If the bit-
stream is converted into a charge packet, a high linearity is
guaranteed as a result of the uniformity of the charge pack-
ets. For this reason, most high-resolution oversampling DACs
are implemented using a switched-capacitor DAC/filter com-
bination as the rear-end.
A one-bit switched-capacitor DAC with one-pole roll-off can
be built as shown in Fig. 27(a) using two-phase nonoverlap-
ping clocks ␾1 and ␾2. The digital signal is fed on the bottom
plate of C2 by sampling Vr or ⫺Vr depending on the digital bit.
The end result is that a constant amount of charge C2Vr is
either added or subtracted from the integrator formed by C1
and the operational amplifier. Because the digital signal is
converted into a charge packet, the shape of the charge packet
is not important as far as the incremental or decremental
charge amount is constant. The use of the prime clocks is to
make switch feedthrough errors constant by turning off the
top plate switches slightly earlier than the bottom plate
switches. The bandwidth of the filter is set to f sC2 /(C1 ⫹ C2).
Operational amplifiers for this application should have high
dc gain and fast slew rate. Operational amplifiers start to
slew when an input voltage larger than its linear range is
applied. When the charge packet of the sampled reference
voltage is dumped onto the input summing node, it causes a
sudden voltage step at the summing node. This one-bit DAC/
filter configuration helps to reduce this voltage step because
charge is directly dumped on the integrating capacitor.
The shaped noise is out of band and does not affect the
inband performance directly. More precise filtering of the
shaped noise can be done with higher-order switched-capaci-
tor filters combined with the one-bit DAC. One second-order
filter combined with a one-bit DAC is shown in Fig. 27(b). It
is a second-order switched-capacitor biquad implementing the
low-pass function. In oversampling applications, even a one-
pole RC filter substantially attenuates high-frequency compo-
nents around f s, but higher-order continuous-time smoothing
filters can be used. Analog filters for this application are often
implemented using a cascade of Sallen–Key filters made of
emitter follower unity-gain buffers.
DAC APPLICATIONS
DAC architectures are mainly determined by the operating
speed. In general, D/A conversion rate is inversely propor-
tional to DAC resolution. DAC applications can range from 20
bits at a few tens of hertz to 6 bits at a couple gigahertz. The
most well-known applications are for 8 bit telephone voice,

±VREF
φ 1’ C2
φ1
C1 φ2
φ 2’
–
Out
+
(a)
φ 1’ φ 2’
– –
φ 1’ φ2 + +
±VREF
φ 2’
φ 1’
(b)
16 bit digital audio, 8 bit digital video, 8 to 12 bit waveform
generation and high-resolution graphics, 12 bit communica-
tion channel, and 8 to 14 bit wireless radio and cell site. As
discussed, two architectures stand out. They are oversam-
pling DAC at low frequencies and segmented DAC at high
frequencies. The former trades resolution for speed, but the
latter needs resolution-enhancing techniques for high linear-
ity because there is no room for speed to trade with reso-
lution.
The 8 bit pulse-coded modulation (PCM) within a fre-
quency band of 300 Hz to 3.4 kHz has been a standard since
the 1970s for the telephone voice channel. One thing to note
in the voiceband quantization is the use of the so-called 애-law
coding scheme so that low-level signals can be quantized more
finely than high-level signals. Because low-level resolution
approaches that of a 14 bit system, it is possible to maintain
constant SNR over a wide range of signal magnitude. Most
voiceband DACs have been made using capacitor-array DACs
and integrated in voiceband coder/decoder (CODEC) systems
using MOS processes.
No field places a higher premium on DAC performance
than digital audio. New multimedia applications have opened
up new audio DAC applications as set forth in the audio CO-
DEC standard AC’97 (1). The new standard covers bit rates
of 8, 11.025, 16, 22.05, 32, 44.1, and 48 kHz. Even the 16 bit
DIGITAL-TO-ANALOG CONVERSION 537
C2
φ 1’ φ1
C1
φ 2’ φ2
Out
φ2
φ1
Figure 27. Time switched-capacitor
DACs: (a) first order and (b) second order.
44.1 kHz digital audio standard set for CD in the 1980s is
now seriously challenged by many improved high-definition
CD (HDCD) standards. The new DVD (Digital Versatile Disc)
format has the capacity of high-resolution uncompressed 20
bit audio at a 98 kHz sampling rate. Video or movie systems
also rely heavily on digital sound. Digital surround sound sys-
tems such as Dolby AC-3, DTS (Digital Theater System), and
5.1 digital surround systems have already become household
names. R-2R or segmented current DACs with laser-trimmed
film resistors are used to make 18 to 20 bit extremely linear
DACs for digital audio. However, the oversampling technique
can meet the demanding performance requirements of digital
audio without trimming.
In the 1990s, digital video is leading the multimedia revo-
lution in modern digital communications. Compressed digital
video images are now accessible over computer networks from
anywhere and at anytime. A 2 h MPEG-encoded (Motion Pic-
ture Experts Group) compressed video can now be stored on
a 5 inch (12.7 cm) optical disc along with digital surround
sound channels. Digital satellite networks provide quality
digital video, and new HDTV (High-Definition TV) will even-
tually replace existing analog TV. All these are now possible
through digitization of video signals. Standard NTSC video
luminance signal covers about a 4 MHz bandwidth with color
subcarrier at 3.58 MHz. The standard video luminance signal
538 DIODES

is sampled with 8 bit resolution at 13.5 MHz, whereas color 16. B. J. Tesch and J. C. Garcia, A low-glitch 14-bit 100MHz D/A
signals are sampled at 6.75 MHz or lower depending on the converter. IEEE Bipolar/BiCMOS Circuits and Technology Meet-
video formats. As more digital signal processing is used, the ing, 1996.
trend is to use 10 bits. In the new HDTV, the sampling rate
is about five times higher at above 75 MHz. BANG-SUP SONG
DACs have become indispensable in the digital era. Digiti- University of Illinois
zation started from voiceband in the 1970s, digital audio in
the 1980s, and digital video in the 1990s is about to move into
intermediate frequency (IF) and RF for wireless telecommuni- DIGITAL VIDEO. See IMAGE SEQUENCES; MULTIMEDIA
cations systems. Digitizing the IF in digital wireless systems VIDEO.
makes it possible to perform data modulation and demodula-
DIGITAL WIRELESS COMMUNICATIONS. See CEL-
tion digitally in software. Low-spurious ADC and DAC are
LULAR RADIO.
key components that will enable this software programmable
radio environment. The architecture that can deliver both DIODE LASERS, MANUFACTURING. See LASER DESK-
TOP MACHINING.
high-resolution and high-speed performance is limited to the
segmented DAC. The current art estimated by recent works DIODE, RESONANT TUNNELING. See RESONANT TUN-
is projected to be 14 to 16 bits at low hundreds of megahertz NELING DIODES.
range depending on process with trimming (15,16). However,
the DAC performance envelope will be pushed out further as
new architectures and device processes evolve.

BIBLIOGRAPHY

1. Analog Devices, Creative Labs, Intel, National Semiconductors,

Yamaha, ‘‘Audio Codel ’97,’’ Rev. 1.03, Sept. 1996.
2. M. J. M. Pelgrom and M. Roorda, An algorithmic 15-Bit CMOS
digital-to-analog converter. IEEE J. Solid-State Circuits, SC-23:
1402–1405, 1988.
3. J. J. Pastoriza, K. Krabbe, and A. A. Molinari, A High-Perfor-
mance Monolithic D/A Converter Circuit. IEEE Int. Solid-State
Circuits Conf., Feb. 1970.
4. J. M. McCreary and P. R. Gray, All-MOS charge redistribution
analog-to-digital conversion techniques—Part I. IEEE J. Solid-
State-Circuits, SC-10: 371–379, 1975.
5. D. M. Freeman, Slewing distortion in digital-to-analog conver-
sion. J. Audio Eng. Soc., 25: 178–183, 1977.
6. R. B. Craven, An Integrated Circuit 12-Bit D/A Converter. Dig.
IEEE Int. Solid-State Circuits Conf., Feb. 1975.
7. D. T. Comer, A monolithic 12-bit DAC. IEEE Trans. Circuits Syst.,
CAS-25: 504–509, 1978.
8. R. J. Van de Plassche, Dynamic element matching for high accu-
racy monolithic D/A converters. IEEE J. Solid-State Circuits, SC-
11: 795–800, 1976.
9. D. W. J. Groeneveld et al., A self-calibration technique for mono-
lithic high-resolution D/A converters. IEEE J. Solid-State Cir-
cuits, SC-24: 1517–1522, 1989.
10. H. S. Lee, D. A. Hodges, and P. R. Gray, A self-calibrating 15-
bit CMOS A/D converter. IEEE J. Solid-State Circuits, SC-19:
813–819, 1984.
11. S. H. Lee and B. S. Song, Digital-domain calibration of multistep
analog-to-digital converters. IEEE J. Solid-State Circuits, SC-27:
1679–1688, 1992.
12. J. C. Candy and A. H. Huynh, Double interpolation for digital-to-
analog conversion. IEEE Trans. Commun., 34: 77–81, 1986.
13. W. L. Lee and C. G. Sodini, A Topology for Higher-Order Interpo-
lative Coder. Proc. Int. Symp. Circuits Syst., May 1987.
14. T. Hayashi et al., A Multistage Delta-Sigma Modulator without
Double Integration Loop. IEEE Int. Solid-State Circuits Conf.,
Feb. 1986.
15. D. Mercer, A 16-b D/A Converter with Increased Spurious Free
Dynamic Range, IEEE J. Solid-State Circuits, SC-29: 1180–
1185, 1994.
570 DIODE-TRANSISTOR LOGIC

and is thus not large enough to turn on DL and QO. Hence,

QO is cutoff and IRC ⫽ IC ⫽ 0. The output voltage can be found
by following dashed path 2 to obtain

VOUT = VCC − IRC RC = VCC = VOH

Input Low Voltage (VIL)

DIODE-TRANSISTOR LOGIC
The first transistor logic family was developed in the 1950s and
was named resistor transistor [bipolar junction transistor
(BJT)] logic (RTL). To improve upon RTL circuits of the past,
diode-transistor logic (DTL), was introduced based upon the de-
sign of preexisting circuits. As the name implies, circuits of the
DTL logic family utilize diodes and transistors in their design.
In 1964, a version of DTL was introduced in integrated cir-
cuit (IC) form that became the standard digital IC family of
that time. This line of DTL, marketed as the 930 series, is easy
to fabricate in IC form and was the standard digital IC for ap-
proximately 10 years after introduction in 1964. This family
was still in use in some military applications in the late 1980s.
In this article we describe the evolution of the DTL logic
family, describing in detail the operation and design of these
circuits. Several numerical examples are also included as an
aid to understanding. We begin with the basic inverter gate.
BASIC DTL INVERTER
Figure 1 shows the basic DTL inverter and its voltage trans-
fer characteristic. It should be mentioned that the primary
reason that DTL logic circuits were introduced was to over-
come the low fan-out of RTL for VOUT ⫽ VOH. From Fig. 1, note
that when VOH is the input voltage to a load gate, the input
diode D⬘I is reverse-biased and sinks only the reverse satura-
tion current, and this current is extremely small.
Output High Voltage (VOH)
For VIN low, the input diode DI is forward-biased as can be
seen by following dashed path 1 in Fig. 1. The voltage be-
tween the diodes is given by
Increasing VIN to the point where QO just turns on is achieved
when
VIN = VBE (FA) = VIL
where VBE(FA) is the B–E base-emitter forward active turn-
on voltage. The corresponding increase in VX is
VX = VIN + VD, I (ON) = VBE (FA) + VD (ON)
= VBE, O (FA) + VD, L (ON)
where VD(ON) is the diode turn-on voltage and both DL and
QO turn on (conduct) when QO is forward active. With QO for-
ward active, VOUT ⫽ VCC ⫺ ICRC and begins to reduce from
VCC for increases in VIN as IC,O increases.
Output Low Voltage (VOL)
Increasing VIN (and therefore VX) further will eventually
drive QO into saturation, giving
VOUT = VCE, O (SAT) = VOL
where VCE,O(SAT) is the B–E saturation voltage.
Input High Voltage (VIH)
Transistor QO enters saturation at VIN ⫽ VBE(SAT) ⫽ VIH
where VBE(SAT) is the B–E saturation voltage, which is
slightly larger than VBE(FA).
Since VX cannot increase any further, subsequent increas-
ing of VIN opens D1. Resistor RB must be chosen small enough
such that QO is in saturation when VX increases to

VX = VIN + VD, I (ON) < VD, L (ON) + VBE, O (FA) VX = VBE (SAT) + VD (ON)

VCC VOUT(V)
1 2
VOH = VCC
1 2
RC
RB 2
VOUT
1
DI DL
1 1
VIN QO
x
2

VOL = VCE (SAT)

VIN(V)
VIH = 0.8
VIL = 0.7

(a) (b)
Figure 1. Basic DTL inverter. (a) Circuit. (b) Voltage transfer characteristic.

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.
 DIODE-TRANSISTOR LOGIC 571

VCC ditional-level shifting diode also avoids the problem of QO

turning on before VIN reaches VBE(FA). The addition of DL2 in-
creases VIL and VIH by VD(ON) ⫽ 0.7 V.
RC
RB Discharge Path
VOUT The inclusion of RD and ⫺VEE at the base of QO provides a
DIA DL path for discharge of the stored base charge of QO, when
VINA QO switched from saturation to cutoff. This decreases the transi-
tion period and propagation delay time. The need for an addi-
DIB tional source voltage (and corresponding pin on the IC) can
VINB
be avoided by simply taking ⫺VEE to be ground and using a
smaller-valued resistance for RD.
Diode AND gate BJT inverter
Figure 2. Basic DTL NAND gate.
TRANSISTOR MODIFIED DTL

The logical NOT function is verified by examination of the
resulting voltage transfer characteristic of Fig. 1(b). Since
VIL and VIH differ only by VBE(SAT) ⫺ VBE(FA), the transition
width between output high and low logic states is quite
abrupt. The actual width can be obtained experimentally or
by circuit simulation with results quite close to these.
Basic DTL NAND Gate
Notice that addition of another input diode, as shown in Fig.
2, resembles a diode AND gate connected to a BJT inverter.
Indeed, the NAND function is inherently provided by the DTL
logic family by adding diodes in parallel at the input pointing
outward (OUT).
MODIFIED DTL
Additional Level-Shifting
Figure 3 shows a modified DTL inverter with an additional
level-shifting diode DL2 added in series with DL to shift the
logic level high-to-low transition by VD(ON) on the VTC input
voltage axis. This improves the low noise margin NML, while
still exhibiting an acceptable high noise margin NMH. The ad-
The fan-out of DTL circuits can be further improved by re-
placing the level-shifting diode DL2 with a BJT QL and split-
ting RB into two resistors, ␳RB and (1 ⫺ ␳)RB, whose sum is
RB, as in Fig. 4. When QL is on, it is self-biased to operate in
the forward-active region and is used in an emitter–follower
configuration. This circuit improves fan-out by QL, providing
more base-driving current to QO, allowing QO to sink more
current from an output load. If ␳ ⫽ 1, the base-collector junc-
tion of QL is shorted, causing QL to become a diode. The circuit
then reduces to the one in Fig. 3. The role of each element of
the DTL gate in Fig. 4 is summarized in Table 1. The state of
each diode and BJT is tabulated in Table 2.
Example 1. Voltage Transfer Characteristic of Transis-
tor Modified DTL. Determine the voltage transfer charac-
teristic (VTC) of the transistor modified DTL inverter in Fig.
4. Use VD(ON) ⫽ 0.7 V for the diodes and VBE(FA) ⫽ 0.7 V,
VBE(SAT) ⫽ 0.8 V, VCE(SAT) ⫽ 0.2 V for the BJTs, and VCC ⫽
5 V.
SOLUTION. The VTC for this improved DTL inverter is
found in a manner analogous to the method in the section

VOUT(V)
VCC
QO(OFF)
VOH
Edge of
conduction
RC
RB
VOUT
QO(\FA)
DI DL2 DL
VIN QO Edge of
saturation
Additional level RD
QO(SAT)
shifting diode VOL = VCE
–VEE (SAT) VIN(V)
VIH = 1.5
Discharge
path VIL = 1.4

(a) (b)
Figure 3. Modified DTL with diode DL2 and discharge path.
572 DIODE-TRANSISTOR LOGIC

VCC Table 2. State of Diodes and BJTs for Output High and
Low Levels
Element VOH VOL
DI On Cutoff
ρ RB 1.75 k⍀
RC 6 k⍀ QL Cutoff Forward active
DL Cutoff On
QO Cutoff Saturated
(1 – ρ )RB 2 k⍀
VOUT

VIN QL DTL NAND GATE

DL
QO Adding additional inputs to a DTL inverter, as in Fig. 5, pro-
vides a circuit that performs the NAND function. This can be
RD 5 k⍀ seen by observing when any or all inputs are low,

VX = VIN (low) + VD, I (ON)

< VBE, L (FA) + VD, L (ON) + VBE, O (FA)

Figure 4. Transistor modified DTL (930 series).

and QO is cutoff with

VOUT = VOH = VCC

entitled ‘‘Basic DTL Inverter.’’ For VIN low, QO is cutoff and
for VIN high, QO is saturated. Thus, When all inputs are high, VX is high, allowing QO to saturate
(provided that ␳RB is chosen properly) and
VOH = VCC = 5V
VOUT = VCE, O (SAT) = VOL
and
Thus, this basic DTL logic family provides the logical NAND
VOL = VCE, O (SAT) = 0.2 V operation.

Furthermore, QO turns on at
VIL = VBE, O (FA) + VD, L (ON)
+ VBE, L (FA) − VD, I (ON)
= 2VBE (FA) = 2(0.7) = 1.4V
and just enters saturation when
VIH = VBE, O (SAT) + VD, L (ON)
+ VBE, L (FA) − VD, I (ON)
= VBE (SAT) + VBE (FA)
= (0.8) + (0.7) = 1.5 V
DTL FAN-OUT
In determining the maximum fan-out for DTL logic gates, we
consider the case where VOUT ⫽ VOL for the driving gate. The
opposite case, where VOUT ⫽ VOH for the driving gate, reverse-
biases the input diodes of all load gates. Such gates sink very
little current and hence do not impose a current limitation on
fan-out. On the other hand, a low driving gate output voltage
is established with all driving gate inputs high, and fan-out
is limited for this situation.
VCC

Note that QL can never saturate because the voltage polarity

for the resistor (1 ⫺ ␳)RB maintains a negative VBC,L for QL.
ρ RB 1.75 k⍀
RC 6 k⍀
Table 1. Purpose of DTL Elements
Element Purpose (1 – ρ )RB 2 k⍀
VOUT
DI Input diode, limits IIH , and provides ANDing
␳ RB Limits IIL VINA QL
(1 ⫺ ␳)RB Self-biases QL DIA DL
QL Base-emitter level shifting for shift of transition width QO
and provides base driving current to QO VINB
DL Level shifting diode for shift of transition width DIB
RD 5 k⍀
RD Provides discharge path for saturation stored charge
VINi
removal from base of QO
DIi
QO Output inverting BJT and output low driver for current
sinking pull-down
RC Passive current sourcing pull-up
Figure 5. 930 Series DTL NAND gate.
 DIODE-TRANSISTOR LOGIC 573

VCC
IOL
N=
IIL

I'IL1
ρ RB 1.75 k⍀
RC 6 k⍀

I'IL2
VOL = V'IN N identical
(1 – ρ )RB 2 k⍀
load gates

VINA IOL
QL
I'ILN
DIA DL
QO
VINB
DIB
RD 5 k⍀
VINi
DIi
Figure 6. DTL NAND gate in output low
state driving N gates.

The maximum fan-out is obtained by determining how ual device and components in the output load gate have a
much output current IOL the driving gate can sink from multi- prime to distinguish the load gate components from the driv-
ple, identical output gates as depicted in Fig. 6. Since each ing gate components.
load gate will have the same input current IIL, from Kirch-
hoff ’s current law we obtain Input Low Current (IIL)
IIL is found by following dashed path 1 of Fig. 7, and then
NIIL = IOL
writing this current as the difference in voltage across the
resistors in series divided by the sum of the resistors.
or Hence,
IOL


N=

VCC − VD, I (ON) − VCE, O (SAT)
IIL IρRB = IIL =
ρR
B + (1 − ρ)R
B
VCC − VD (ON) − VCE (SAT)
To determine N, we use Fig. 7, which shows one of the load = = IRB
gates explicitly with VOUT ⫽ V⬘IN ⫽ VOL. Note that the individ- RB

V'CC
1

VCC 1
3 2
ρ R'B 1.75 k⍀ R'C 6 k⍀
3 2
1
ρ RB 1.75 k⍀ RC 6 k⍀ (1 – ρ )R'B 2 k⍀ V'OUT
I'IL1
3 2
VOL = V'IN 1 Q'L
(1 – ρ )RB 2 k⍀
1 I'IL2 D'IA D'L
Q'O
3 IOL
VIN QL 1
DIA DL R'D 5 k⍀
QO I'ILn

RD 5 k⍀ 2
1

Driving gate (output low state) Load gates (output high state)

Figure 7. Cascaded DTL gates for fan-out and power calculations.

574 DIODE-TRANSISTOR LOGIC

Output Low Current (IOL) Example 2. DTL Fan-Out. Calculate the fan-out for the
DTL inverter of Fig. 6 considering the circuit in Fig. 7 and
IOL is found by writing Kirchoff’s current law (KCL) at the
the subcircuit in Fig. 8. Let 웁F ⫽ 49, VBE(FA) ⫽ 0.7 V,
collector of QO where
VBE(SAT) ⫽ 0.8 V, and VCE(SAT) ⫽ 0.2 V for the BJTs and let
IOL = IC, O (SAT) − IRC VD(ON) ⫽ 0.7 V for the diodes. Also, use ␴OL ⫽ 0.85 for the
output low state and VCC ⫽ 5 V.
The current through RC is found by following dashed path 2
SOLUTION. Substituting these values directly into the de-
of Fig. 7, yielding
rived equations yields
VCC − VCE, O (SAT)
IRC = (5) − (0.7) − (0.2)
RC IIL = IρRB = = 1.09 mA
(3.75 k)
(5) − (0.2)
The collector current of QO(SAT) is obtained from IRC = = 800 µA
(6 k)
IC, O (SAT) = σOL βF IB, O (SAT) (5) − 2(0.7) − (0.8)
IE, L = = 1.60 mA
(0.467)(3.75 k)
where ␴OL is the saturation parameter, smaller for deeper sat- (0.8)
IRD = = 160 µA
uration (larger IB,O). However, for maximum fan-out, we con- (5 k)
sider operation at the edge of saturation where ␴ ⫽ 1 and IB, O = (1.60 mA) − (160 µA) = 1.44 mA
IC, O (SAT) = IC, O (EOS) = βF IB, O (EOS) IC, O = (0.85)(49)(1.44 mA) = 60 mA
IOL = (60 mA) − (800 µA) = 59.2 mA
To determine this quantitatively, we write KCL at the base (59.2 mA)
of QO to obtain N= = 54.3
(1.09 mA)
IB, O = IE, L − IRD
Hence, the fan-out of this DTL gate is 54. Note that IB,O ⫽
1.40 mA is indeed large enough to saturate QO.
where

VBE, O (SAT) DTL POWER DISSIPATION

IRD =
RD
The emitter current of QL is found by analyzing the portion of
the driver gate including VCC, ␳RB, (1 ⫺ ␳)RB, QL, DL, and QO
as redrawn in Fig. 8. Considering the base current of QL to be
zero, the current through ␳RB is equal to the emitter current
of QL and the emitter current of QL is
VCC − VBE, L (FA) − VD, L (ON) − VBE, O (SAT)
IE, L =
ρRB
To determine the average power dissipation of a DTL gate,
we first determine the currents being supplied by VCC for both
the high and the low output states. Notice that these currents
have already been obtained in the fan-out analysis of the pre-
vious section.
Output High Current Supplied [ICC(OH)]
For the output high state the input is low [i.e., VCE(SAT)], and
considering dashed path 3 in Fig. 7, we have

The following example indicates the use of these equations. VCC − VD (ON) − VCE (SAT)
IρRB (OH) = IIL =
RB

VCC Since QO is cutoff, IRC(OH) ⫽ 0, and

ICC (OH) = IρRB (OH)

ρ RB 1.75 k Ω Output Low Current Supplied [ICC(OL)]

For the low output state, the input is high, then
(1 – ρ )RB 2 kΩ IρRB (OL) = IE, L
VCC − VBE (FA) − VD (ON) − VBE (SAT)
DI ≡ open QL =
–
DL IDL
ρRB
VBE(FA) QO
– – – Additionally, the current through RC for this output low state
– VD(ON)
VBE(SAT) is simply
–
VCC − VCE (SAT)
IRC (OL) =
Figure 8. Portion of DTL driving gate. RC
 DIPOLE ANTENNAS 575

Thus,

ICC (OL) = IρRB (OL) + IRC (OL)

Average Power Dissipation [PD(avg)]

The average power dissipated is now found by substituting
into

ICC (OH) + ICC (OL)

PD (avg) = VCC
2
IρRB (OH) + IρRB (OL) + IRC (OL)
= VCC
2

Example 3. DTL Power Dissipation. Calculate the aver-

age power dissipation for the DTL gate in Example 2.

SOLUTION. Direct substitution of the values calculated in

Example 2 yields

(1.09 mA) + (1.60 mA) + (800 µA)

PD (avg) =
2
= 8.73 mW

Compared to metal–oxide–semiconductor (MOS) logic fami-

lies, this amount of power dissipation is quite large.

CONCLUSIONS

Although DTL logic circuitry can be fabricated quite conve-

niently in IC form, this family has many disadvantages and
was only used extensively prior to the introduction of TTL. In
the 1990s, there are numerous other logic families that offer
improvement in all aspects of operation.

BIBLIOGRAPHY

T. A. DeMassa, Electrical and Electronic Devices, Circuits and Instru-

ments, St. Paul, MN: West, 1989.
T. A. DeMassa and Z. Ciccone, Digital Integrated Circuits, New York:
Wiley, 1996.

THOMAS A. DEMASSA
Arizona State University
JOHN CICCONE
VLSI Technology, Inc.

DIGITAL FILTER SYNTHESIS
OVERVIEW OF THE PROBLEM
Direct digital synthesis is applied to problems in signal en-
hancing, such as the following case study: Assume that a
faulty tape recorder is used to record a critical message. Due
to all the hissing noises created by the tape and recording
systems, the message is unintelligible. In order to know the
message, it is imperative to improve the quality of the audio
signal. All the actions performed to attain that goal are said
to be intended to enhance the signal.
By extension, any effect that tends to reduce the quality of
data is called noise, and data are said to be corrupted by noise.
Data signals may originate not only from voice or audio, but
from many other sources such as radio and television, indus-
trial and medical instrumentation, statistical sampling, and
so on. In general, one strives to manipulate the corrupted sig-
nal and recreate the original data.
A significant feature of signal-enhancing problems is that
neither the desired data nor the corrupting noise can be
known exactly. In the example of the recorded message, one
must enhance the signal to get the message; the noise, in gen-
eral, is caused by random effects. At best, one may be able to
identify the signals as members of certain classes.
The enhancing considered in this article is based on the
concept of frequency-selective response and listening is an ex-
ample of this type of processing. The human (animal) ears are
frequency-selective in the following essential ways: (1) Sounds
of different frequencies are recognized as being different (e.g.,
a sound wave vibrating at 440 Hz is the note A, and one vi-
J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.
DIGITAL FILTER SYNTHESIS 475
brating at 494 Hz corresponds to the note B); (2) Ears are
sensitive to certain frequencies and completely deaf to others;
(3) Ears can discriminate between sounds regardless of their
relative loudness; that is, they can differentiate between the
A note played by a violin and the same note played by a trum-
pet, even if one is significantly louder than the other. The last
characteristic is an instance of frequency-selective processing.
Both instruments create a sound that is not a pure vibration
at 440 Hz, but has components that vibrate at frequencies
that are characteristic of each instrument. The vibration at
440 Hz is by far the strongest, allowing the ear to recognize
the note while the vibrations at other frequencies create an
aural perception unique to the instrument. The fact that loud-
ness is not significant indicates that the relative strength of
the vibrations is more important than the actual intensity.
Any sound can be viewed as a combination of basic sound
waves, each of a unique frequency and strength. The relative
strength becomes a signature that permits the identification
of a sound regardless of its level. One can characterize classes
of sounds by the form in which their strength is concentrated
at the various frequencies; and more significantly, one can
create or enhance sounds by adjusting the signal energy at
the various frequencies.
Frequency-Selective Enhancement
Frequency-domain analysis is a generalization of the repre-
sentation of sound waves as combinations of basic vibrations.
The Fourier transform is the mathematical tool used to deter-
mine how the energy of the signal is distributed at different
frequencies. Devices that have a frequency-selective behavior
are mathematically described by their frequency response. The
class of devices considered in this article are said to be linear
and time-invariant (1, pp. 46–54). For these systems the fre-
quency response is a complex-valued function which deter-
mines how the device responds to any linear combination of
sinusoids.
The statement that a continuous time system, also re-
ferred to as a filter, has a frequency response, H(2앟f), conveys
the following information: (a) The variable, f, corresponds to
the frequency in cycles per second (Hz), which is related to
the frequency measured in radians per second by the relation-
ship ⍀ ⫽ 2앟f. (b) H(2앟f) is a complex number with magnitude
兩H(2앟f)兩 and argument ␾(2앟f) ⫽ ⬔H. (c) If one applies as input
to this system the signal u(t) ⫽ cos 2앟ft, the output of the
system will be the sinusoid, y(t) ⫽ 兩H(2앟f)兩 cos[2앟ft ⫹
␾(2앟f)]. In an extreme case, if for some frequency, f 0, one has
兩H(2앟f 0)兩 ⫽ 0, then that particular frequency is completely
eliminated from the output of the system.
There are many practical signal-enhancing applications
which use frequency-selective processing based on an ideal
band-pass behavior. With the specified frequency range f l ⱕ
f ⱕ f h, the ideal device is given by

1; f l ≤ | f | ≤ f h
Hbp (2π f ) =
0; elsewhere
Standard variations of this ideal behavior are: ideal low-pass
filter ( fl ⫽ 0), high-pass filter ( fh ⫽ 앝), and a stop-band filter
(1 ⫺ Hbp(2앟f)). All ideal filters are unrealizable since, in the-
ory, they require complete knowledge of past, present, and
476 DIGITAL FILTER SYNTHESIS

future values of the input signal in order to operate. Creating
realizable filters which ‘‘approximate’’ the behavior of ideal
ones is still a very active research area.
In the early days of radio, telephony, and industrial instru-
mentation, all signals were converted into voltages or cur-
rents. All filtering was performed using analog components
such as resistors, inductors, and capacitors creating devices
known as passive filters. With the advent of electronics—in
particular, solid-state devices—it is now possible to emulate
and improve on the traditional passive filters. The new de-
vices require an external power supply and are referred to as
active filters.
There is a significant amount of literature dealing with the
design of the basic filters. The reader is referred to Ref. 2
(pp. 666–692) for designs based on analog filters, including
Butterworth, Tchebychev, elliptic, and Bessel filters. There
are also well-established computer-aided tools that only re-
quire from the user the specification of the frequency range
and the type of the filter desired, based on which, they deliver
a realizable filter which approximates the desired behavior
(3).
DIRECT DIGITAL DESIGN
Nowadays, it is possible to use computers to perform the re-
cording and enhancing of signals. Figure 1 establishes basic
notation by showing a block diagram for filtering a signal us-
ing two techniques. In the figure, the continuous time signal,
x(t), is to be enhanced (e.g., the voltage from the audio ampli-
fier going to the speakers). The block Analog Filter repre-
sents the conventional processing producing an enhanced sig-
nal, y(t). The block Sampling represents the physical process
of collecting the samples of the signal, x(t); the actual device
is an analog-to-digital converter (ADC). The sequence of val-
ues is modeled as a discrete time signal, xd[k]. If the sampling
process is ideal and the sampling period is T, then
constructed enhanced signal, yr(t) (4, pp. 91–99). An ideal, and
hence unrealizable, reconstruction uses the formula


∞
sin(π (t − nT )/T )
yr (t) = yd [k]
k=−∞
π (t − nT )/T
In practice, there are several efficient computational tech-
niques to create reconstructed signals that satisfactorily ap-
proximate this ideal behavior (see also Ref. 5, pp. 100–110;
Ref. 2, pp. 763–774).
The goal of direct digital synthesis is to define the numeri-
cal processing that must be done to the samples so that the
complete sequence sampling–digital filtering–signal recon-
struction creates desired enhancing effects on the signal.
Numerical algorithms designed to process the samples are
considered discrete time systems (the independent variable is
integer-valued). Conceptually, one can apply as input a dis-
crete time sinusoid and characterize the frequency-selective
behavior using a discrete frequency response. In this case, the
frequency response is a 2앟 periodic function of the discrete
frequency, 웆. The notation Hd(ej웆) is used to emphasize the
fact that the function is periodic. Knowledge of the discrete
frequency response permits, ideally, the complete determina-
tion of the numerical algorithm that is required. Using the
exponential Fourier series expansion (see Ref. 4, pp. 39–51)
one can write


∞
H(e jω ) = hn e jnω
n=−∞
 π
dω
hn = H(e jω )
−π 2π
The coefficients of the expansion, hn, define the impulse re-
sponse of the discrete time system. The enhanced digital sig-
nal values are computed either by using directly the convolu-
tion formula

xd [k] = x(kT )

∞
yd [k] = hn xd [k − n] (1)
n=−∞
The block Digital Filter corresponds to the numerical process
that will be applied to the samples of the input signal to pro- or by using an equivalent efficient numerical algorithm. No-
duce samples of the enhanced signal, yd[k]. It is said to be a tice that when
realization of a discrete time system. The block Reconstruct
represents the process used by the computer to create an ana- hn = 0; ∀n < 0
log signal from a sequence of numerical values, yd[k]. The de-
vice is called a digital-to-analog converter (DAC). A sound the value of yd[k] depends only on input samples, xd[m], where
card (in a computer) or a CD player performs such a recon- m ⱕ k. The algorithm is said to be causal and is suitable for
struction operation to produce sounds from the digits stored on-the-fly processing where the input samples arrive in real
in the computer or in the compact disc. The result is the re- time.

Analog
y(t)
filter

Signal

x(t)

Digital yr(t)
ADC filter DAC
xd[k] yd[k]
Figure 1. Analog and digital signal fil-
tering. Sampling Reconstruct
 DIGITAL FILTER SYNTHESIS 477

If the number of nonzero coefficients is finite, one has a
finite impulse response (FIR); otherwise it is infinite impulse
response (IIR). For this latter class of filters, the formula in
Eq. (1) is not an efficient algorithm and one must find an al-
ternative representation. A standard form suitable for real
time operation is the recursive expression
yd [k] + a1 yd [k − 1] + · · · + am yd [k − m]
= b0 xd [k] + · · · + bm xd [k − m]
However, it is known that some impulse responses, 兵hn其, do
not allow such a recursive representation, and there are no
general techniques to establish such a representation for a
given impulse response. The direct determination of a re-
cursive implementation with a desired frequency response is
still an open research problem. References 6 and 7 provide
partial results for the direct design of IIR filters.
Relating Continuous and Discrete Frequency Responses
sage is the goal, one may recognize sentences even if all fre-
quencies above 2 kHz are eliminated. Bandlimiting is thus a
viable technique to increase signal-to-noise ratio and would
be one of the techniques considered for recovering the mes-
sage in the opening case study. As an example, assume that
the voice signal needs to be enhanced by eliminating all fre-
quency components below f l ⫽ 60 Hz and above f h ⫽ 12,000
Hz. The signal is sampled at a frequency of f s ⫽ 44.1 kHz, or
(2) with a sampling period, T ⫽ 1/f s, which is the normal sam-
pling rate for storing music in compact discs.
An ideal analog filter to perform this operation is the filter

1; f l < | f | < f h
H(2π f ) =
0; elsewhere
To each of the frequencies, f l and f h, one associates the dis-
crete frequencies, 웆l ⫽ 2앟f lT, 웆h ⫽ 2앟f hT. One period of the
ideal discrete frequency response will be

It is possible to relate the continuous time frequency, f, to the 

1; ωl ≤ |ω| ≤ ωh
discrete time frequency, 웆. The procedure requires the devel- Hd (e ) =
jω

opment of a continuous time model for discrete time signals 0; elsewhere in [−π π]
and leads to the equation
Once the desired ideal frequency response is defined, one can
2π f T = ω, −π ≤ ω ≤ π use the Fourier series expansion to determine the coeffi-
cients, hn, of the impulse response. The result in this case is
This equation highlights two important issues in digital sig-
nal processing: (1) Under the ideal reconstruction scheme, the 
 1 (sin nω − sin nω ); n = 0
analog signal created from the samples cannot contain any
hn = πn
h l
frequencies above the frequency f N ⫽ 1/2T; that is, it is ban- 
0; n=0
dlimited. (2) If the original analog signal, x(t), contains fre-
quencies above the value 1/2T, it will not be possible to recre-
ate the analog signal from the samples; even the ideal It is clear from this expression that there are infinitely many
reconstruction will be different. This phenomenon is known nonzero values of hn and the convolution representation in
as aliasing, and the frequency, f N, is called the Nyquist fre- Eq. (1) is not efficient. Moreover, there are nonzero values of
quency in honor of H. Nyquist (8), who first stated the result hn for negative values of n, showing that the system is non-
in his Sampling Theorem (2, pp. 21–33). causal and cannot be implemented in real time. It is also ap-
The relationship has also been used to define discrete time parent that the values of hn get smaller and smaller as n in-
frequency responses when the desired continuous time re- creases. From a practical point of view, one could consider
sponse is known. In one approach (see Ref. 4, pp. 97–99), one that after a certain value N, they are zero. This effectively
period of the discrete frequency response is defined as follows: implies a truncation of the impulse response—that is, using
an FIR approximation. Once the response is truncated to a
ω finite number of terms, the problem of hn ⬆ 0 for n ⬍ 0, can
Hd (e jω ) = H(2π f ), f = |ω| ≤ π
2πT be solved by introducing a time delay in the computation of
the response (see Ref. 4, pp. 250–254).
This approach actually relates the discrete impulse response There are many situations where a simple truncation of
to samples of the continuous time frequency response. The the impulse response introduces a significant deterioration of
reader is referred to Ref. 4 (pp. 406–438) for techniques based performance (see Ref. 4, pp. 444–462). A simple and effective
on discretization of the transfer function. technique to overcome this is to perform the truncation by
In a simpler approach, the relationship between discrete- means of a smooth window function. The new coefficients of
and continuous-time frequency is used to define basic fre- the impulse response are given by
quency-selective responses for discrete-time systems. Differ-
ent techniques are used to determine a numerical processing ĥn = w(n)hn
algorithm which gives (approximately) the desired frequency
response.
An example of a window function is the generalized Hamming
window:
Example 1. In theory, the human ear can perceive frequen-
cies up to 20 kHz. For simple voice applications, one can pre- 
2π 
serve intelligibility with a much smaller bandwidth. The 
α + (1 − α) cos ;

 N

smaller the bandwidth, the larger the amount of noise that is 
N −1
 N−1
wH (n) = − ≤n≤ ,0 ≤ α ≤ 1
eliminated. For most applications this increases signal-to- 
 2 2


noise ratio; but if the bandwidth is made too narrow, then the 
message itself will be destroyed. If understanding the mes- 0; elsewhere
478 DIGITAL FILTER SYNTHESIS
If 움 ⫽ 0.54, the window is called a Hamming window; and if
움 ⫽ 0.5, it is called a Hanning window (see Ref. 9, pp. 92–93).
The computation of the impulse response coefficients can
be simplified to a great extent if one resorts to the discrete
Fourier transform (DFT), H(k), given by


N−1
H(k) = hn e − j(2π nk/N ) ; k = 0, 1, . . . , N − 1
n=0
The values, H(k), correspond to samples of the Fourier trans-
form for an N-periodic signal at the frequency points, 웆k ⫽
2앟k/N, where k ⫽ 0, 1, . . ., N ⫺ 1. For direct digital filter
design, one would proceed as follows:
1. Define the discrete frequency selective behavior that is
required.
2. Select the number, N, that determines the number of
coefficients, hn, to be used. This value is application de-
pendent and can be as low as 4 and as high as 256 or
more.
3. Determine the values of the desired discrete frequency-
selective response, H(k), at the frequencies, 웆k ⫽
2앟k/N, where k ⫽ 0, 1, . . ., N ⫺ 1.
4. Use the definition of the DFT as a system of algebraic
equations and solve for the values, hn. This operation is
the computation of the inverse DFT. The computation is
performed with high numerical efficiency using a vari-
ety of fast Fourier transform (FFT) algorithms (see Ref.
10, pp. 114–152).
Remark 1. Using the DFT algorithm to determine the im-
pulse response corresponding to a discrete frequency re-
sponse, H(ej웆), has the implicit assumption that the impulse
response is a periodic function. Therefore, there is an aliasing
effect in this approach. If hp(n) is the nth coefficient computed
using the DFT technique, its relationship to the exact coeffi-
cients, determined from the series expansion, is given by


h p (n) = h(n − mN)
m
The values h(k) are the exact values of the impulse response
computed using the Fourier series expansion. In practice, by
using a suitably large value of N, the aliasing effect can usu-
ally be neglected.
Remark 2. In principle, one can specify any frequency-selec-
tive behavior which may lead to coefficients, hn, that are com-
plex numbers. By placing constraints on the frequency re-
sponse, Hd(ej웆), one can guarantee that the coefficients will be
real numbers. Also, it is known that if the argument of the
discrete frequency response is a linear function of the discrete
frequency over the interval [⫺앟 앟]—linear-phase digital fil-
ters—one can obtain performances closer to the ideal using
fewer terms than nonlinear-phase filters.
It is significant that they cannot ensure that the best approxi-
mation is being used. Moreover, the techniques do not permit
the design of special, or customized, frequency-selective char-
acteristics. This section presents an overview of the extensive
literature on optimal digital filter design, which can be used
to define any type of filter. In this approach, the design is
transformed into a nonlinear optimization problem over a set
(3)
of parameters, or filter coefficients. The user must (a) specify
a merit index or cost function, which measures the quality of
a given solution and (b) specify possible constraints in the
optimization process. The various methods differ in the choice
of cost function and constraints.
If the desired frequency behavior is IIR, the problem can-
not be solved or implemented unless the filter can be put in
the form of a recursive equation such as Eq. (2). Even in this
case, the frequency response is a highly nonlinear function of
the coefficients, (al, bl), and a general solution to even a simple
optimization problem is not known. Several special cases
have been considered in the literature, and the readers are
referred to Refs. 6, 7, and 9 (pp. 75–293). The FIR case has
received much more attention because the frequency response
is a linear function of the coefficients. Moreover, FIR filters
have good numerical properties and can be easily imple-
mented, even if the number of coefficients (taps) is large.
A causal FIR filter with N taps has a frequency response


N−1
H(e jω ) = hk e − jkω
k=0
Let h ⫽ col兵h0, h1, . . ., hN⫺1其 be the vector of real-valued vari-
ables over which the optimization is performed. The desired
specification is given as an ideal, or desired, frequency re-
sponse, Hd(ej웆). A commonly used merit index is the Lp, 1 ⱕ
p ⬍ 앝, one which has the cost function of the form
 π
dω
h) =
J(h W (ω)|Hd (e jω ) − H(e jω )| p (4)
−π 2π
The function W(웆) is a weighting function used to assign dif-
ferent weights, corresponding to the relative importance of
different frequency ranges (e.g., zero on a frequency band of
no importance to the designer). The value of the exponent, p,
has a definite effect on the solution. If p ⫽ 1, all errors have
the same importance while p ⬎ 1 assigns increasingly more
significance to larger errors. The most common constraint is
the requirement of linear phase, which can be easily incorpo-
rated as a symmetry condition in the coefficients, leading to
standard canonical filter types (4, pp. 250–270).
Least-Squares Solution
The special case, p ⫽ 2, is called the least-squares method and
has a particularly simple analytical solution. Define
N = col{e− jkω ; k = 0, 1, . . ., N − 1}
 π 
OPTIMAL DIGITAL FILTER DESIGN T dω (5)
Q = 2Re W (ω)N N
−π 2π
The techniques described in the previous section are aimed  π 
dω
at determining a numerical algorithm that approximates the u = Re W (ω)N (6)
behavior of an ideal frequency-selective processing algorithm. −π 2π

where Re兵 ⭈ 其 indicates the real part of 兵 ⭈ 其, and ⍀TN denotes the
transposed (row) vector. The optimal solution is known to ex-
ist and is unique whenever the matrix, Q in Eq. (5) is nonsin-
gular. The expression for the solution is
h = Q−1 u (7)
The matrix, Q, is nonsingular for most practical cases of the
weighting function. For example, if W(웆) is piecewise con-
stant, it is sufficient to require that it be nonzero over at least
one interval (i.e., nontrivial). The trivial case, W ⬅ 1, leads to
Q ⫽ I and h ⫽ u.
In spite of the analytical solution, one normally uses nu-
merical algorithms to compute the solution. A popular algo-
rithm uses the conjugate gradient technique (11), which has
the advantage of being relatively simple to implement and
has a guaranteed convergence to the solution in a finite num-
ber of iterations.
A variation of the least-squares approach is presented in
Ref. 12. Here, instead of defining an ideal response, the au-
thors constrain the filter at specific frequencies and convert
the minimization into an eigenvalue problem.
The existence of a formula for the best filter makes the
least-squares method very popular. However, it has recog-
nized limitations: Because of the squaring operation, small
errors are given less importance and may exist over larger
frequency ranges than with other methods; and the merit in-
dex will accept large errors over small frequency ranges. As a
result, the approximations that are obtained may display
large peaks (overshoots) and less desirable soft transitions, as
opposed to the sharp transitions of ideal filters. The choice of
weighting function will have a significant effect on the final
solution obtained; but there are no established criteria for its
definition. Lawson (13) provided a significant link between
this method and the equiripple approach presented next. He
proved that the equiripple solution can be obtained as a least-
squares solution for some weighting function, and he devel-
oped an iterative algorithm to modify the weighting function.
The algorithm can be used to make the optimization less sen-
sitive to the choice of weighting function, or as a way to im-
prove on a given least squares solution.
Equiripple Solution
The worst-case design avoids the problems in the least-
squares method by minimizing the largest error. The cost
function in this case is
h ) = max W (ω)|Hd (e ) − H(e )|
J(h jω jω
(8)
−π ≤ω≤π
This case can be shown to be equivalent to the Lp case for
p ⫽ 앝. Only special cases of this cost function have known
solutions (14,15), the most important being the case where
the function W(웆) is piecewise constant and the FIR filter is
linear-phase. Using Tchebychev polynomials, it is possible to
give necessary conditions to characterize the optimal solution:
It alternates from maximum to minimum a known number of
times (which depends on the number of parameters); all max-
ima have the same value and so do all the various minima.
This characteristics give the solution the property called
equiripple. The case does not have an analytical closed-form
solution, but there are excellent numerical algorithms such
DIGITAL FILTER SYNTHESIS 479
as the Parks–McClellan technique (see Refs. 16 and 17).
Kootsookos et al. (18), considered the case, W(웆) ⬅ 1, and de-
veloped an algorithm based on the solution of a number of
related extension (Nehari) problems. Their algorithm com-
pares favorably with the exchange algorithm implemented by
Parks and McClellan, with the added advantages that linear
phase is not required and the algorithm is applicable to multi-
variable filters (filters which process several inputs at the
same time).
Extensions and Further Readings
The optimal design of IIR filters is an active area of research
with only partial results available. Least-squares techniques
have been applied to special forms, such as all pole systems
(see Ref. 4, pp. 701–725). Zhang and Ikawara (6) use the
worst-case criterion and reformulate the design problem as a
generalized eigenvalue problem.
Perhaps the strongest extension of the direct design of digi-
tal filters has been motivated by problem in computer vision
and image processing. For such application, the signals (im-
ages) are modeled as functions of two independent time vari-
ables and are referred to as multidimensional signals. Least-
squares design of FIR filters has been formulated and solved
(e.g., in Ref. 19). Theoretical results characterizing multidi-
mensional equiripple solutions are not complete, but some
practical results have been attained by using a modification
of Lawson’s algorithm (20).
The technical literature on digital filtering is vast. The
reader can find good lists of references in textbooks such as
Refs. 2 and 4 for conventional signals and Ref. 21 for multidi-
mensional signals.
BIBLIOGRAPHY
1. C.-T. Chen, System and Signal Analysis, 2nd ed., New York:
Saunders, 1994.
2. J. C. Proakis and D. G. Manolakis, Digital Signal Processing:
Principles, Algorithms, and Applications, 3rd ed., Englewood
Cliffs, NJ: Prentice-Hall, 1996.
3. J. N. Little and L. Shure, Signal Processing Toolbox for Use with
MATLAB娃, MA: The MathWorks, 1992.
4. A. V. Oppenheim and R. W. Schafer, Discrete-Time Signal Pro-
cessing, Englewood Cliffs, NJ: Prentice-Hall, 1989.
5. J. H. McClellan, R. W. Schafer, and M. A. Yoder, DSP First: A
Multimedia Approach, Englewood Cliffs, NJ: Prentice-Hall, 1998.
6. X. Zhang and H. Iwakura, Design of IIR digital filters based on
eigenvalue problem, IEEE Trans. Signal Proc., 44: 1325–1333,
1996.
7. L. B. Jackson, An improved Martinez/Parks algorithm for IIR
design with unequal number of poles and zeros, IEEE Trans. Sig-
nal Proc., 42: 1234–1238, 1994.
8. H. Nyquist, Certain topics in telegraph transmission theory,
AIEE Trans., 617–644, 1928.
9. L. R. Rabiner and B. Gold, Theory and Application of Digital Sig-
nal Processing, Englewood Cliffs, NJ: Prentice-Hall, 1975.
10. R. E. Blahut, Fast Algorithms for Digital Signal Processing, Read-
ing, MA: Addison-Wesley, 1985.
11. M. Minoux, Mathematical Programming: Theory and Algorithms,
New York: Wiley, 1986.
12. P. P. Vaidyanathan and T. Q. Nguyen, Eigenfilters: A new ap-
proach to least squares FIR filter design and applications includ-
480 DIGITAL MULTIMETERS

ing Nyquist filters, IEEE Trans. Circuit Syst., CAS-34: 11–23,

1987.
13. C. L. Lawson, Contribution to the theory of linear least maximum
approximation, Ph.D dissertation, University of California, Los
Angeles, 1961.
14. C. Charalambous, A unified review of optimization, IEEE Trans.
Microwave Theory Tech., MTT-22: 289–300, 1974.
15. C. Charalambous, Acceleration of the least pth algorithm for min-
imax optimization with engineering applications, Math. Program-
ming, 17: 270–297, 1979.
16. T. W. Parks and J. H. McClellan, Chebyshev approximation for
nonrecursive digital filters with linear phase, IEEE Trans. Circuit
Theory, CT-19: 189–194, 1972.
17. J. H. McClellan and T. W. Parks, Equiripple approximation of
fan filters, Geophysics, 7: 573–583, 1972.
18. P. J. Kootsookos, R. R. Bitmead, and M. Green, The Nehari shuf-
fle: FIR(q) filter design with guaranteed error bounds, IEEE
Trans. Signal Proc., 40: 1876–1883, 1992.
19. J. L. Aravena and G. Gu, Weighted least mean square design of
2-D FIR digital filters: general case, IEEE Trans. Signal Proc.,
44: 2568–2578, 1996.
20. Y. C. Lim et al., A weighted least squares algorithm for quasi-
equiripple FIR and IIR digital filter design, IEEE Trans. Signal
Process., SP-40: 551–558, 1992.
21. D. E. Dudgeon and R. M. Merserau, Multidimensional Digital
Signal Processing, Englewood Cliffs, NJ: Prentice-Hall, 1984.

JORGE L. ARAVENA
VIDYA VENKATACHALAM
Louisiana State University

DIGITAL HALFTONING. See HALFTONING.

DIGITAL IMAGE PROCESSING. See IMAGE PRO-
CESSING.
DIGITAL LOGIC. See BOOLEAN FUNCTIONS; NAND CIR-
CUITS; NOR CIRCUITS.
DIGITAL LOGIC BASED ON MAGNETIC ELE-
MENTS. See MAGNETIC LOGIC.
DIGITAL LOGIC CIRCUITS, FUNCTIONAL AND
CONFORMANCE TESTING. See LOGIC TESTING.
DIGITAL LOGIC DESIGN. See CARRY LOGIC.
DIGITAL MODULATION. See DIGITAL AMPLITUDE MODU-
LATION.
612 DISCRETE EVENT SYSTEMS
DISCRETE EVENT SYSTEMS
A discrete event system (DES) can be defined as a dynamic
system for which the state changes in response to the occur-
rence of discrete events. The discrete events take place at pos-
sibly irregular or unknown points in time (i.e., asynchro-
nously and nondeterministically) but are the result of
interactions within the system itself. The acronym DES, or
frequently DEDS (for discrete event dynamic systems), has
been used extensively in many different fields of mathematics
and applications to designate apparently widely different sys-
tems. Nevertheless, all these systems have in common the
property of being driven by events, rather than by time. The
conceptual structure of a DES is deceptively simple. It is a
system composed of multitudes of ‘‘jobs’’ that require various
services from a multitude of ‘‘resources.’’ The limited avail-
ability of the resources determines the interactions between
the jobs, whereas the start and the completion of the jobs, as
well as the changes of the resources, generate the events that
govern the dynamics of the system. But this conceptually sim-
ple model encompasses scores of event-driven, mostly human-
J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.
made, overwhelmingly complex systems: large international
airports, automated manufacturing plants, military logistic
systems, emergency hospital wards, offices, services and
spare parts operations of multinational companies, distrib-
uted computing systems, large communication and data net-
works, very large scale integrated circuits (VLSI), electronic
digital circuits and so on. Typical examples of events that can
trigger the response of a DES and the possible change of its
state are the arrival or the departure of a customer in a
queue, the arrival or the departure of a packet in the node of
a communication network, the completion of a task, the fail-
ure or the repair of a machine in a factory, the opening or the
closing of a switch in an electrical network, the pressing of a
key on the keyboard of a personal computer (PC), the ac-
cessing or the leaving of a resource, and so on.
System theory has traditionally been concerned with con-
tinuous variable dynamic systems (CVDSs) described by dif-
ferential equations, possibly including random elements. The
essential feature of CVDSs is that they are driven by time,
which governs their dynamics. The discrete-time systems, for
which the time instances are elements of a sequence, are de-
scribed by difference equations instead of differential equa-
tions, but they essentially belong to the CVDS approach as
long as their variables can take numerical values and are
time-driven. In most cases, the discrete-time systems can be
considered merely computational models, obtained by the
sampling of the continuous-time systems. The CVDS ap-
proach is a powerful paradigm in modeling real-world ‘‘natu-
ral’’ systems. Currently, CVDSs are the main objects of what
forms the core of our scientific and technical knowledge, rang-
ing from Galileo’s and Newton’s classical mechanics to rela-
tivist and quantum mechanics, thermodynamics, electrody-
namics and so on. CVDS models have also been highly
successful in most engineering fields to describe low- or me-
dium-complexity man-made systems and are still the main
objects of control theory.
With the continuous and rapid increase in complexity of
the systems to be modeled, analyzed, designed, and con-
trolled, especially of the human-made systems that include
computer and communication subsystems as essential compo-
nents, systems too complex to allow a classical CVDS descrip-
tion have emerged. For such systems, the variables attached
to the states and to the processes can have not only numerical
values, but also symbolic or logical values. This motivates the
interest in DESs in domains as different as manufacturing,
robotics, vehicular traffics, conveyance and storage of goods,
organization and delivery of services, and computer and com-
munication networks, with particular emphasis on database
management, computer operating systems, concurrent pro-
gramming, and distributed computing. In all these domains,
control is necessary to ensure the orderly flow of events in
highly complex systems. Significant efforts have been made in
the last two decades to develop a comprehensive framework to
handle DESs. The DES theory, even if still in its infancy
when compared to the differential/difference equations para-
digm underlying the CVDS theory, is fast growing at the con-
fluence of artificial intelligence, operations research, and con-
trol system theory. Notable among the various approaches
that have been used to represent DESs are the state ma-
chines and formal languages models (1–19), Petri nets (20–
29), timed marked graphs (30–33), Markov chains (34,35),
and generalized semi-Marcov processes (GSMP) (36,37).
 DISCRETE EVENT SYSTEMS 613

These models allowed the analysis of DES qualitative proper- of the events is relevant for these models. The untimed DES
ties, the quantitative evaluation of DES performances by models have been used for the deterministic qualitative anal-
methods as perturbation analysis (38–40) and likelihood ratio ysis of control issues such as the reachability of states
method (41,42), as well as progress in the design and control (18,58,59) or deadlock avoidance (23,60). Finite-state machine
of DESs. Even if a general theory of DESs does not yet exist, and Petri nets are the formal mechanisms mostly used for the
the previously mentioned partial approaches have provided representation of untimed DESs. Other untimed frameworks,
valuable concepts and insights and have contributed to the such as the trace theory, have also been explored. Neverthe-
understanding of the fundamental issues involved in the less, finite-state machines and their associated state transi-
analysis, design, and control of DESs. Discrete system simu- tion graphs are still the most widely used models because of
lation methods, algorithms, and software are now commer- their inherent simplicity and because they can be described
cially available for both qualitative behavior analysis and adequately by finite automata and regular languages. The
quantitative performance evaluation (43–57). simplest untimed DES model is a deterministic state-machine
Because of the complexity and the heterogeneity of the do- or automaton, called generator, described by the 4-tuple
main, as well as its fast growth, only some of the very basic
aspects will be presented in the rest of this article. The main G = (Q,
, δ, s) (1)
attention is focused on the modeling of DESs, which allows
one to grasp the basic features and the behavior of DESs.
where Q is the (countable) set of states of the system, ⌺ is the
Some elements of the control of DESs are presented, and
(countable) set of events, 웃 : Q ⫻ ⌺ 씮 Q 傼 兵⌳其 is the transition
some examples of DES application are given.
function, and s ⫽ q0 is the initial (start) state of the system.
By a reminiscence of the classical system theory, the set of
MODELS OF DISCRETE EVENT SYSTEMS states is sometimes called the state space, even if it does not
have the structure of a vector space, typical for the CVDSs.
The increased complexity of human-made systems, especially The function 웃 describes the transition from a state q 僆 Q to
as an effect of the widespread application of information tech- a new state q⬘ ⫽ 웃(q, ␴), in response to the occurrence of an
nology, has made the development of more detailed formal event ␴ 僆 ⌺. The symbol ⌳ denotes the null element, which
methods necessary to describe, analyze, and control processes
is used to indicate that the transition is not defined for some
observed in environments such as digital communication net-
pairs (q, ␴) 僆 Q ⫻ ⌺. For this reason, 웃 : Q ⫻ ⌺ 씮 Q is called
works and manufacturing plants. As opposed to the continu-
a partial function. It is convenient to designate by ⌺f(q) the
ous time-driven evolution of a CVDS [Fig. 1(a)], the evolution
set of all feasible events for a given state q, i.e., ⌺f(q) ⫽ 兵␴ 僆
of a DES is piecewise-constant and event-driven [Fig. 1(b)].
⌺兩웃(q, ␴) ⬆ ⌳其. As usual in the regular expressions formalism,
The state variables of a DES may have not just numerical
we denote by ⌺* the set of all finite strings of elements of ⌺,
values, but also symbolic or logical values, so that the set of
including the empty string ⑀. A sample path (trajectory) of a
states Q does not have the vector space structure typical for
DES, starting from the specified initial state q0 ⫽ s [see Fig.
CVDS. The elements qj 僆 Q, j 僆 ⺞, may be seen as labels
1(a)], is given by the state-(event-state) sequence q0␴1q1␴2,
attached to the various distinct states of the DES. The state
. . ., ␴nqn. The set of all (physically) possible such sequences
transitions may occur in response to the occurrence of discrete
events ␴k, belonging to a set of events ⌺ and taking place at is called the behavior B(G) of the generator G:
discrete time instances tk. From the point of view of the tim-
ing information, DESs can be classified into two main catego- B(G) = {q0 σ1 q1 σ2 , . . ., σn qn |n ∈ N∗ , 1 ≤ k ≤ n, qk = δ(qk−1, σk )}
ries: (1) untimed (logical) and (2) timed. (2)

Untimed Discrete Event Systems For a deterministic DES, the sample trajectory can be de-
Untimed or logical DES models ignore time as a variable that scribed equivalently by the event string 兵␴k其k⫽1,2,. . .,n, or by the
specifies the moments when the events occur. Only the order state string 兵qk其k⫽0,1,2,. . .n. In the formalism of regular lan-
guages, an event string corresponding to a sample trajectory
is called a word w built with the symbols ␴ taken from the
x(t) CVDS DES alphabet ⌺. Correspondingly, the set of all the (physically)
qn –1 possible words is called the language L(G) 傺 ⌺* generated by
State (state variable)

State (set of states)

Input = u(t) d
σ n –1 = α σn = γ G over the alphabet ⌺. Sometimes, the language is also called
c the behavior of the DES, or the behavior of its generator. In
σ2 = β q σ3 = γ
x·(t) = f(x, u, t) b
2 qn the framework of automata theory, an automaton is described
q1 q3 by a 5-tuple, which includes as a fifth element a set of marker
a states Qm 債 Q. A marker state usually represents the comple-
q0 σ1 = α tion of a task. This is not essential in this context, so it is
s ....
t t1 t2 t3 tn –1 tn deferred for the following section.
Time (time variable) Time (event sequence)
(a) (b) Example 1. Consider a DES generator G that models a sim-
Figure 1. Comparison of generic trajectories of continuous variable ple generic machine. The state set Q ⫽ 兵I, W, D,其 is composed
dynamic systems and of discrete event systems: (a) Example of an of the states: I—Idle, W—Working, and D—Down, whereas
illustrative one-dimensional CVDS trajectory. (b) Example of a DES the event set ⌺ ⫽ 兵S, C, B, R其 is composed of the events: S—
trajectory (움, 웁, 웂, 웃 僆 ⌺; a, b, c, d, s 僆 Q). Start of a task, C—Completion of the task, B—Breaking
614 DISCRETE EVENT SYSTEMS
I I2
S R2
R
C S1
W D
B
Figure 2. The transition graph of a simple generic machine model.
The system can be in the states: I—Idle, W—Working, and D—Down,
and the transitions are induced by the events: S—Start of a task,
C—Completion of the task, B—Breaking down, and R—Repair.
down, and R—Repair. Figure 2 shows the transition function
of the system. The states are designated by nodes, and the
events by oriented arcs connecting the nodes. The initial state
s ⫽ I is marked with an entering arrow. The language gener-
ated by G, i.e., the set of all the (physically) possible se-
quences of events is
L(G) = {, S, SD, SC, SCS, SCSD, SDR, SDRS, SDRSD, . . . }
which can be written in the formalism of regular expressions
as L(G) ⫽ (SC ⫹ SDR)*(⑀ ⫹ S ⫹ SD).
Example 2. Let us now consider the case of two machines of
the type given in Example 1 working in parallel. Each ma-
chine has a generator of the previously considered type. The
transition graphs of the two machines working as indepen-
dent entities are represented in Fig. 3. The system composed
of the two machines working in parallel, even without condi-
tioning each other, has the state set Q ⫽ Q1 ⫻ Q2 ⫽ 兵(I1, I2),
(W1, I2), (D1, I2), . . ., (D1, D2)其, the set of events ⌺ ⫽ ⌺1 傼
⌺2 ⫽ 兵S1, C1, B1, R1, S2, C2, B2, R2其, and the transition graph
shown in Fig. 4. The combinatorial growth in complexity of a
DES with the increase of the number of components is ob-
vious.
Since untimed models contain no quantitative timing in-
formation, they cannot be used to obtain performance mea-
sures involving time, such as holding times or event occur-
rence rates. Nevertheless, logical DES models have
successfully been used to represent and study qualitative as-
pects in areas such as concurrent program semantics, commu-
nicating sequential processes, synchronization in operating
systems, supervisory control, communication protocols, logical
analysis of digital circuits, and fault-tolerant distributed com-
puting and database protocols. The control theory of discrete
event systems has been initiated by Ramadge and Wonham
I1 I2
S1
C1
S2
C2
R1 W1 R2 W2
B1 B2
D1 D2
Figure 3. The transition graphs of two instances of the simple ma-
chine model in Fig. 2, operating independently.
W2 D2
B2
I1
C2 C1
C1 S1 R2 C1
S1
S1
S1
B2
W1
R1
C2 B1
R1 B1 R1 B1
R2
S1
B2
D1
C2
Figure 4. The transition graph of a system made up of the two in-
stances of the simple machine model shown in Fig. 2, operating as
elements of the system.
(see Refs. 16–19,61,62) in the framework of untimed DESs.
The analysis of an untimed DES model typically proceeds as
follows. By using some state transition structure (e.g., autom-
ata or Petri nets), a set of algebraic equations, or a logical
calculus approach, one specifies the set of all admissible event
trajectories, that is, enumerates all the sequences of events
that do not contradict various physical restrictions inherent
to the modeled system. On this basis, the behavior of the sys-
tem—usually expressed by the generated language L, that is,
by the set of all the possible finite sequences of events that
can occur in the system—is found as a strict subset of all
event orderings ⌺*. In the control context, one has to further
restrict the language so that each system trajectory has some
desired property such as stability (e.g., state convergence),
correct use of resources (e.g., mutual exclusion), correct event
ordering (e.g., data base consistency), desirable dynamic be-
havior (e.g., no deadlock/livelock), or the achievement of some
goal (e.g., distributed consensus).
The difficulties in applying logical DES models to real-life
size problems are caused by the computational complexity.
Even if problems like establishing controllability or designing
a supervisor to control the behavior of a DES are polynomially
decidable or polynomially solvable in the number of states of
the DES, the number of states itself grows in a combinatorial
manner when a complex system is built from simpler compo-
nent subsystems. As a consequence, the number of the states
of a logical DES increases exponentially with respect to the
system size. This motivates the efforts to state/event formal-
isms that have the capability to suppress the aspects of the
system description irrelevant in a given context. One mod-
ality is event internalization, or partial observation, which
leads to nondeterministic process behavior and, consequently,
to inadequacy of formal languages as models of behavior. The
complexity issues are also talked with by using modularity,
hierarchy, and recursivity when building the system descrip-
tions from the individual component features. Since all the
components of a complex process must interact and synchro-
nize when operating in parallel, a suitable mechanism for
communication and interaction between modules is an impor-
tant component of DES modeling.
Markov Chain Model of an Untimed DES. One way of model-
ing the random behavior of discrete event systems is by using

the Markov chain formalism. As pointed out earlier, the non-
deterministic behavior of a system can be the result of its
incomplete (partial) description. Either some of the events are
aggregated into complex events that can yield multiple out-
comes (event internalization) or the states of the system are
defined in a space of lower dimension than would be required
for their complete specification (hidden variables) so that the
states aggregate and actually correspond to classes of states.
Partial description can be necessary and desirable in order to
reduce the computational difficulties—to make complex sys-
tems tractable—or can result from incomplete knowledge
about the modeled system. On the other hand, randomness
can be an irreducible feature of some of the processes in the
system itself. The Quantum Mechanics approach is the first
example at hand. The problem of whether or not such built-
in randomness does exist is still open to philosophical debate.
From the engineering point of view, this is irrelevant because
the behavior of the system is similar in both cases.
A Markov chain model of a nondeterministic DES is de-
fined by the set of states Q and the transition probability ma-
trix PS ⫽ [PSij], where
1. PSij ⫽ P(qj兩qi), for i ⬆ j, is the conditional probability that
the system passes into the state qj 僆 Q, i.e., the proba-
bility of occurrence of event ␴ij ⫽ (qi, qj), provided that
the current state is qi 僆 Q.
2. PSij ⫽ 1 ⫺ 兺j⬆i PSij is the probability of remaining in the
state qi, which is the probability of occurrence of event
␴ii ⫽ (qi, qi), if ␴ii 僆 ⌺f, or the probability that no event
occurs in the state qi, if ␴ii 僆 ⌺f.
The probability that, starting from the initial state s ⫽
q(0) ⫽ qi, the system arrives after n steps into the state
q(n) ⫽ qj is denoted by PSij ⫽ P[q(n) ⫽ qj兩q(0) ⫽ qi]. Thus, the
entries of the transition probability matrix give the probabili-
ties of paths of length one:
P ijS = P[q(n + 1) = q j |q(n) = qi ]
Markov chains can be used to represent the ‘‘closed loop’’ be-
havior of a controlled DES. In this case, the probabilities of
the enabled transitions (events) are strictly positive, whereas
the probabilities of the disabled transitions are zero. The con-
trol of a DES modeled by a Markov chain consists thus in
changing the transition probabilities, according to the com-
mands issued by the supervisor, to achieve a certain control-
ling task.
Timed DES Models
Timed DES models were developed primarily to allow the
quantitative evaluation of DESs by computing performance
measures like holding times or event occurrence rates, which
imply counting events in a given time interval or measuring
the time between two specific event occurrences and obtaining
the appropriate statistics. The timed event trajectory of a
DES is specified by the sequence 兵␴k, tk其k僆N*, whereas the timed
state trajectory is 兵qk, tk其k僆N, where tk gives the moment of the
kth event occurrence. Significant analytical results have been
obtained in the special case of queuing theory. For the sys-
tems that do not satisfy the specific hypotheses of the queuing
theory, timed DES models have been studied by using simula-
DISCRETE EVENT SYSTEMS 615
tion and statistical analysis, which is computationally costly
and has little potential for real-time control. Both approaches
were used for the evaluation of performances related to re-
source contention and allocation, based on the oversimplifying
assumption that a manufacturing process can be described
adequately by using only timing considerations. For instance,
the problem of the yield percentage in semiconductor wafer
manufacturing is more closely related to the properties of the
materials and to the technological aspects than to resource
contention.
Another approach is based on the fact that sample paths
of parametric DESs contain a considerable amount of infor-
mation that allows to predict the behavior of the system when
the values of the parameters are perturbed. Both infinitesi-
mal perturbation analysis (IPA) and likelihood ratio (LR)
methodology have been used in conjunction with various gra-
dient-based stochastic optimization schemes. These tech-
niques yielded significant results in problems like routing in
communication networks or load balancing in distributed pro-
cessing systems.
In order to define a timed DES, a mechanism for generat-
ing the event time instance sequence 兵tk其k僆N has to be added
to the untimed model. This mechanism should also take into
account the randomness of the event lifetime ␶␴, ␴ 僆 ⌺. Cas-
sandras and Strickland (36) have introduced a model to study
the properties of the sample paths of a timed DES. The gener-
ator
G = {Q,
, δ, s, F} (3)
contains, in addition to the components of an untimed DES
[Eq. (1)], the event lifetime generator:
F = {Fσ (·), σ ∈
} (4)
which is a set of probability distribution functions (pdfs) asso-
ciated with the events.
The basic simplifying hypothesis is that all events are gen-
erated through renewal processes, i.e., each pdf F␴( ⭈ ) depends
only on the event ␴, not on other factors such as the states
before and after the event ␴ occurs and the count of how many
events of type ␴ have already occurred.
Figure 5 shows a typical sample path of a timed DES. In
the general case, the set of events ⌺ contains several types
of events and it is possible that for some states q there are
nonfeasible events ␴, i.e., ␴ 僆 ⌺f(q). In the simplest case,
when there is only one type of event in ⌺ and this event is
feasible for all the states in the path, the kth lifetime ␶k,i of
the event of type i characterized by the pdf Fi( ⭈ ) gives the
interval between two successive occurrences of the event
tk⫹1 ⫺ tk ⫽ ␶k,i where k ⫽ 1,2,. . .. A certain time instant t in
σ1 σ2 σk σ k+1
q0 q1 q2 qk–1 qk qk+1
t1 t2 tk t tk+1
τ k, j
xk,i yk,i
Figure 5. Generic sample path of a timed DES with one event type.
The moment t divides the kth lifetime ␶k,i of event of type i into the
age xk,i and the residual lifetime yk,i.
616 DISCRETE EVENT SYSTEMS

this interval, t 僆 [tk, tk⫹1], divides it into two parts that define with x1,i ⫽ 0. The event time instances are given by the time
the age xk,i ⫽ t ⫺ tk of the event i (the time elapsed since its Eq. (7)
most recent occurrence), and the residual lifetime yk,i ⫽ tk⫹1 ⫺
t ⫽ ␶k,i ⫺ xk,i of the event of type i (the time until its next tk+1,i = tk,i + min {τ j − xk, j } (11)
j=
f (q k )
occurrence). When several types of events are possible, the
next event occurrence is determined by the currently feasible
The model is similar to the one used by the min-plus dioid
event with the smallest residual lifetime ␴k⫹1 ⫽ arg min␴i僆⌺f(qk)
algebra approach presented in a later section of this article.
兵yk,i其, where yk,i is a random variable generated with
the pdf: Formal Languages and Automata DES Models

Hk,i (u, xk,i ) = P[ yk,i ≤ u|xk,i ] = P[τk,i ≤ xk,i + u|τk,i > xk,i ]
Fi (xk,i + u) − Fi (xk,i )
= the finite state set Q, the finite set of events ⌺, and the behav-
1 − Fi (xk,i )
The dynamic model of a timed DES, allowing the step-by-step
construction of a sample path, is thus given by
qk = δ(qk−1 , σk )
tk+1 = tk + min { yk, j }
σ j ∈
f (q k )
σk+1 = arg min { yk, j }
σ j ∈
f (q k )

xk,i + min { yk, j }; if σi ∈
f (qk ),
xk+1,i = σ j ∈
f (q k )
 whereas their concatenation is
0; otherwise
for k 僆 ⺞* and for initial conditions specified by some given
s ⫽ qo and t1 ⫽ min␴j僆⌺f(q0) 兵y1, j其, ␴1 ⫽ arg min␴j僆⌺f(q0) 兵y1, j其, and
x1,i ⫽ min␴j僆⌺f(q0) 兵y1, j其, where y1, j are random variables drawn
from Fj( ⭈ ) for all j. This stochastic dynamic model generates
a generalized semi-Markov process. For such processes, a
state is actually defined by two components: the discrete state
qk 僆 Q and the so-called supplementary variables xk,i (or,
equivalently, yk,i), for all i 僆 ⌺. A GSMP offers a convenient
framework for representing timed DESs. The deterministic
mechanism for the state transitions, defined here by the func-
tion 웃(q, ␴), can also be replaced by a probabilistic state tran-
sition structure. Even more than in the case of untimed
DESs, despite the conceptual simplicity of the dynamics, the
exhaustive analysis of a stochastic timed DES model can be
of prohibitive computational complexity, not only because of
the large number of states but also because of the nonlinear-
ity of the equations and the age-dependent nature of the pdfs
Hk,i(u, xk,i). On the other hand, if the dynamic equations are
seen as a sample path model, than the timed trajectories of
DES can be generated relatively simple when the lifetime dis-
tributions Fi( ⭈ ) are known for all i 僆 ⌺. This allows the use
of techniques like perturbation analysis (38) or the likelihood
ratio method (39,40) for performance evaluation, control, or
optimization purposes.
The stochastic model can be reduced to a deterministic one
if the lifetimes are considered to be constants for all i 僆 ⌺.
The residual lifetimes of events are determined by yk,i ⫽ ␶i ⫺
xk,i, for all i, k, whereas the event ages xk,i result from the state
equation

xk,i + min {τ j − xk, j }; if i ∈
f (qk )\{σk }
xk+1,i = j∈
f (q k )

0; otherwise
Formal Languages—Regular Expressions. Using the previous
notation, let the generator G of an untimed (logical) DES have
(5)
ior described by the set of all (physically) possible finite event
strings L(G) 傺 ⌺*, a proper subset of ⌺*—the set of all finite
strings built with elements of the alphabet ⌺, including the
empty string ⑀. In the formal language approach, let us con-
sider that each event is a symbol, the event set ⌺ is an alpha-
(6) bet, each sample event path w ⫽ ␴1␴2 . . . ␴n of the DES is a
word, and the (event) behavior L(G) is a language over ⌺. The
(7) length 兩w兩 of a word w (i.e., of a sample path) is the number
of symbols ␴ from the alphabet ⌺ (i.e., events) it contains. The
(8) length of ⑀ is zero.
Given two languages, L1 and L2, their union is defined by
σi = σk L1 + L2 = L1 ∪ L2 = {w|w ∈ L1 or w ∈ L2 } (12)
(9)
L1 L2 = {w|w = w1 w2 , w ∈ L1 or w ∈ L2 } (13)
The Kleene (iterative) closure of a language L is
L∗ = {w|∃k ∈ N and w1 , w2 , . . ., wk ∈ L so that
(14)
w = w1 w2 · · · wk }
The union, concatenation, and Kleene closure are regular op-
erators.
A string u is a prefix of w 僆 ⌺*, if there is some v 僆 ⌺* so
that w ⫽ uv. If w 僆 L(G), then so are all its prefixes. A prefix
is called proper if v 僆 兵⑀, w其.
The prefix closure of L 傺 ⌺* is
L = {u|uv ∈ L for some v ∈
∗ } (15)
A language L is prefix closed if L ⫽ L, i.e., if it contains the
prefixes of all its words.
The (event) behavior of a DES can be modeled as a prefix
closed language L over the event alphabet ⌺. In the following,
the main relevant propositions will be stated, but the proofs
will be omitted for briefness. We will write v*, u ⫹ v, and so
on, instead of 兵v其*, 兵u其 ⫹ 兵v其, when no confusion is possible.
A regular expression in L1, L2, . . ., Lm 傺 ⌺* is any expres-
sion in L1, L2, . . ., Lm containing a finite number of regular
operators. A language is called regular if it can be defined by
a regular expression in a finite set of symbols, i.e., events.
The set R of regular languages over an alphabet ⌺ is the
smallest set of languages satisfying:
1. ␾ ⫽ 兵 其 僆 R , 兵⑀其 僆 R ,
2. {a} ∈ R, for ∀a ∈
, (16)
(10)
3. ᭙A, B 僆 R , A 傼 B, AB, A* 僆 R .

Regular expressions are notations for representing the regu-
lar languages, constructed with these rules:
1. ␾, ⑀, and the elements of the alphabet ⌺ are regular
expressions.
2. If 움 and 웁 are regular expressions, then 움 傼 웁, 움웁, 움*
are also regular expressions.
Obviously, a regular expression can be considered itself a
word (a string of symbols) over the alphabet ⌺⬘ ⫽ ⌺ 傼 兵), (, ␾,
傼, *, ⑀其.
A language L(␰), represented by a regular expression ␰, is
defined by
1. L(␾) ⫽ ␾, L(⑀) ⫽ 兵⑀其,
2. L(a) ⫽ 兵a其, ᭙a 僆 ⌺,
3. L(α ∪ β ) = L(α) ∪ L(β ), (17)
4. L(움웁) ⫽ L(움)L(웁),
5. L(움*) ⫽ L(움)*.
It can be shown that a language is regular if it is represented
by a regular expression. The set of all the words constructed
with the symbols from an alphabet ⌺ ⫽ 兵␴1, ␴2, . . ., 움n其, in-
cluding the empty word ⑀, is represented by the regular ex-
pression ⌺* ⫽ 兵␴1 ⫹ ␴2 ⫹ ⭈ ⭈ ⭈ ⫹ ␴n其*. The set of all the non-
empty words constructed with symbols from ⌺ is given by the
regular expression ⌺⫹ ⫽ ⌺⌺*.
DES Deterministic Generators. Consider the generator of a
DES modeled by a finite deterministic state machine (automa-
ton) defined now by the 5-tuple
G = {Q, S, d, s, Qm } (18)
where Q is a (finite) state set, ⌺ is the (finite) alphabet recog-
nized by G, 웃: Q ⫻ ⌺ 씮 Q is the transition function, s ⫽ q0 is
the initial state, and Qm 債 Q is the set of marker states. For
sake of simplicity, we considered here ⌺f(q) ⫽ ⌺, ᭙q 僆 Q [see
comments on Eq. (1)]. As already mentioned, the marker
states have been introduced by Ramadge and Wonham (see
Ref. 16) to represent the completed tasks of a DES by the
state trajectories that end in (or contain a) marker state.
Therefore, along with B(G), the previously defined
unmarked behavior of a DES [Eq. (2)], we define the marked
behavior
Bm (G) = {q0 σ1 q1 σ2 , . . ., σn qn ∈ B(G)|qn ∈ Qm } (19)
which includes all the system trajectories that end in a
marked state, i.e., result in the accomplishment of a certain
task. Correspondingly, in addition to the language generated
by G, the subset L(G) 傺 ⌺* of all the (physically) possible
words generated by G over the alphabet ⌺,
L(G) = {w = σ1 σ2 , . . ., σn ∈
|q0 σ1 q1 σ2 , . . ., σn qn ∈ B(G)} (20)
we define the language marked or accepted by G, as the re-
stricted subset Lm(G) 債 L(G)
Lm (G) = {w = σ1 σ2 , . . ., σn ∈
∗ |q0 σ1 q1 σ2 , . . ., σn qn ∈ Bm (G)}
(21)
DISCRETE EVENT SYSTEMS 617
which is composed the words that start from the specified ini-
tial state s ⫽ q0, and lead to a marked state qn 僆 Qm. Because
the marked language Lm(G) is a subset of the language L(G),
so is its prefix closure [see Eq. (15)] Lm(G) 債 L(G), i.e., every
prefix of Lm(G) is also an element of L(G). A generator G is
called nonblocking if the equality Lm(G) ⫽ L(G) holds, mean-
ing that every word in L(G) is a prefix of a word in Lm(G). In
this case, every sample path of events in L(G) can be extended
to include a marker state or—in other words—can be contin-
ued to the completion of a task.
The links between the states q 僆 Q and the words w 僆
⌺* can be put on a more formal basis using the concept of
configuration. The configuration of a finite automaton is de-
fined by the ordered pair (q, w) 僆 Q ⫻ ⌺*, which makes up a
state q and a word w applied in this state.
A configuration (q⬘, w⬘) can be derived from a configura-
tion (q, w) by the generator G, the relation of which is denoted
by (q, w) 哫 *G (q⬘, w⬘), if there is a finite number k ⱖ 0 and a
sequence 兵(qi, wi)兩0 ⱕ i ⱕ k ⫺ 1其 so that (q, w) ⫽ (q0, w0), (q⬘,
w⬘) ⫽ (qk, wk), and (qi, wi), 哫 (qi⫹1, wi⫹1), for every i, 0 ⱕ i ⱕ
k, i.e., wi ⫽ ␴i⫹1 wi⫹1, qi⫹1 ⫽ 웃(qi, ␴i). Each word wi is composed
of the first symbol ␴i⫹1 and the remaining word wi⫹1, so that
the words in the sequence are related by
w = w0 = σ 1 w1 = σ 1 σ 2 w2 = · · · = σ 1 σ 2 · · · σ k wk = σ 1 σ 2 · · · σ k w
(22)
The execution of an automaton on a word w is (s, w) 哫 (q1,
w1) 哫 ⭈ ⭈ ⭈ 哫 (qn, ⑀), with
w = σ 1 w1 = σ 1 σ 2 w2 = · · · = σ 1 σ 2 · · · σ n (23)
For a deterministic automaton, each word w defines a unique
execution, thus a unique trajectory of the system.
Using this formalism, a word w is accepted or marked by
a generator (automaton) G if the execution of the automaton
on the given word leads to a marker state qn 僆 Qm:
∗
(q0 , w) → (qn , ); qn ∈ Qm (24)
G
The language Lm(G) accepted or marked by the automaton G
is the set of words accepted by G:
∗
Lm (G) = {w ∈
∗ |(q0 , w) → (qn , ); qn ∈ Qm } (25)
G
DES Nondeterministic Generators. A finite nondeterministic
state machine (automaton) is the 5-tuple
G = {Q,
, , s, Qm } (26)
where Q, ⌺, s ⫽ q0, Qm retain the meanings defined for deter-
ministic generators [Eq. (18)], whereas the evolution law is
given by the transition relation ⌬ 傺 Q ⫻ ⌺ ⫻ Q, which gener-
alizes the previously defined transition function 웃. For a given
state q 僆 Q, an event ␴ 僆 ⌺ can induce a transition of the
system to a state p 僆 Q, with (q, ␴, p) 僆 ⌬. The set of states
reachable in one step from the state q, after a transition in-
duced by the event ␴, is
Q(q, σ ) = {p ∈ Q|(q, σ , p) ∈ } (27)
618 DISCRETE EVENT SYSTEMS
The set ⌺f(q) of all feasible events for a given state q can be
expressed as

f (q) = {σ ∈
|∃p ∈ Q, (q, σ , p) ∈ } = {σ ∈
|Q(q, σ ) = ?}
(28)
The deterministic generator can be seen as a special case of
the nondeterministic generator with the property that, for all
q 僆 Q and ␴ 僆 ⌺, there exist at most one state p 僆 Q such
that (q, ␴, p) 僆 ⌬. In this case, a transition function 웃: Q ⫻ ⌺
씮 Q 傼 兵⌳其 can be defined such that 웃(q, ␴) ⫽ p 僆 Q, when
(q, ␴, p) 僆 ⌬, and 웃(q, ␴) ⫽ ⌳, when (q, ␴, p) 僆 ⌬, i.e., when ␴
僆 ⌺f(q).
It is convenient to extend further the definition of the evo-
lution law to a relation ⌬* 傺 Q ⫻ ⌺* ⫻ Q, by stating (q0, w,
qn) 僆 ⌬* if there exist the sequences 兵qk兩qk 僆 Q, k ⫽ 0, 1, . . .,
n其 and w ⫽ 兵␴k兩␴k 僆 ⌺, k ⫽ 1, 2, . . ., n其 僆 ⌺*, such that
(qk⫺1, ␴k, qk) 僆 ⌬, for all k ⫽ 1, 2, . . ., n.
Using the relation ⌬*, the language generated by G can be
expressed as
L(G) = {w ∈
∗ |∃q ∈ Q: (q0 , w, q) ∈ ∗ } (29)
and the language accepted or marked by G as the restricted
subset Lm(G) 債 L(G)
Lm (G) = {w ∈
∗ |∃qm ∈ Qm ; (q0 , w, qm ) ∈ ∗ } (30)
A configuration (q⬘, w⬘) is derivable in one step from the con-
figuration (q, w) by the generator G, the relation of which is
denoted by (q, w) 哫 G (q⬘, w⬘), if w ⫽ uw⬘, (i.e., the word w
begins with a prefix u 僆 ⌺*) and (q, u, q⬘) 僆 ⌬*.
A class of equivalent states is a set of states that have the
property that the system can pass from one state in the class
to another without the occurrence of any event, i.e., by transi-
tions on the empty word ⑀. The equivalence class E(q) of a
state q is defined as an equivalence class comprising the
state, q, i.e., the set of states reachable from the state q by
transitions on the empty word
∗ with indices lower than k. Then
E(q) = {p ∈ Q|(q, w) → (p, w)} = Q(q, ) (31)
G
Two generators G1 and G2 are called equivalent if L(G1) ⫽
L(G2).
For any nondeterministic finite generator G ⫽ 兵Q, ⌺, ⌬*,
q0, Qm其, it is possible to build formally an equivalent determin-
istic finite generator G⬘ ⫽ 兵Q⬘, ⌺⬘, 웃⬘, q⬘0, Q⬘m其, for which the
states are replaced with classes of equivalent states. Corre-
spondingly, the state set becomes the set of equivalence
classes Q⬘ 債 2Q (the set of the subsets of the state set Q), the
initial state is replaced by the set q⬘0 ⫽ E(q0) ⫽ Q(q0, ⑀) of
states in which the generator can be before any event occurs,
the transition function is defined by 웃⬘(q, ␴) ⫽ 傼p僆Q 兵E(p)兩᭚q
僆 q : (q, ␴, p) 僆 ⌬*其, and the set of marker equivalence classes
is Q⬘m ⫽ 兵q 傺 Q⬘兩q 傽 Qm ⬆ ␾其. The last equation shows that a
‘‘state’’ of G⬘ is a marker state if it contains a marker state
of G.
Regular Languages and Finite Automata Representation. As
stated earlier, regular expressions and finite automata are
formalisms adequate for representing regular languages, as
well as for representing the behaviors of DESs, which are
φ
σ
σ ∈Σ
Figure 6. Elementary automata that accept the languages corre-
sponding to the basic regular expression ␾, ⑀, and ␴ 僆 ⌺.
languages over some alphabets of events. The following prop-
ositions express the fundamental links between regular lan-
guages and finite automata:
• A language is regular if it is accepted by a finite automa-
ton.
• If a language can be constructed by a regular expression,
then it is accepted by a finite nondeterministic automa-
ton.
• For each basic regular expression ␾, ⑀, ␴ 僆 ⌺, there is an
automaton that accepts the corresponding language as
shown in Fig. 6.
• For each composed regular expression 움1움2, 움1 ⫹ 움2, 움*1 ,
an automaton accepting the same language can be built
based on the automata A1 and A2 that accept the lan-
guages described by 움1 and 움2, respectively: 움1 ⇔ A1 ⫽
兵Q1, ⌺, ⌬*1 , q(1)
0 , Qm 其, 움2 ⇔ A2 ⫽ 兵Q2, ⌺, ⌬*
(1)
2 , q0 , Qm 其. For
(2) (2)
instance, the automaton A corresponding to the regular
expression 움1움2 is 움1움2 ⇔ A ⫽ 兵Q, ⌺, ⌬*, q0, Qm其, where
Q ⫽ Q1 傼 Q2, ⌬ ⫽ ⌬1 傼 ⌬2 傼 兵(q, ⑀, q(2) 0 )兩q 僆 Qm 其, q0 ⫽
(1)
q 0 , Qm ⫽ Q m .
(1) (2)
Algorithm for Constructing the Marked Language of a Generator
G. Consider again the generator of a DES G ⫽ 兵Q, ⌺, ⌬, s,
Qm其, with the finite set of states Q ⫽ 兵q1, q2, . . ., qn其, where
the order is arbitrary. Let us find the language Lm(G) marked
by G, i.e., the set of words over the alphabet ⌺ that end in a
marker state [see comments on Eq. (30)].
Let us denote by R(i, j, k) the partial language made up of
the set of words allowing the transition from the state qi to
the state qj, passing either directly, or only through states

{w|(qi , w, q j ) ∈ ∗ }, i = j
R(i, j, 1) = (32)
{} ∪ {w|(qi , w, q j ) ∈ ∗ }, i = j
and the following recurrence relation holds:
R(i, j, k + 1) = R(i, j, k) ∪ R(i, k, k) ∪ R(k, k, k)∗ R(k, j, k),
k = 1, 2, . . ., n (33)
Choosing the initial state s ⫽ q1, the language Lm(G) marked
by G results:

Lm (G) = R(1, j, n + 1) (34)
q j ∈Q m
Both the partial languages R and the language Lm(G) are reg-
ular languages.
Example 3. Consider a simple DES, having the generator G
given by Eq. (26), with the state set Q ⫽ 兵q1, q2其, the event set
⌺ ⫽ 兵a, b其, the initial state s ⫽ q1, the set of marker states
 DISCRETE EVENT SYSTEMS 619

a b b x1
q1 q2
a
Figure 7. Transition graph of a simple determinist generator. The
initial state s ⫽ q1 is marked with an entering arrow, whereas the
marker state q2 is represented with a double circle.
Qm ⫽ 兵q2其, and the transition relation ⌬ ⫽ 兵(q1, ⑀, q1), (q1, a,
q1), (q1, b, q2), (q2, a, q1), (q2, ⑀, q2), (q2, b, q2)其, for which corre-
sponds the transition graph in Fig. 7. Using the relations (32)
and (33), the partial languages R(i, j, k), i, j, k ⫽ 1, 2, of G
listed in Table 1 can be computed successively. Thus, the lan-
guage accepted by G results:
L ∗ G) = R(1, 2, 3)
= [b ∪ ( ∪ a)( ∪ a)∗ b] ∪ [b ∪ ( ∪ a)( ∪ a)∗ b]
[ ∪ b) ∪ a( ∪ a)∗ b]∗ [( ∪ b) ∪ a( ∪ a)∗ b]
Max-Plus Algebra Representation of
Timed Discrete Event Systems
The max-plus (max, ⫹) algebra deals with a subclass of the
timed Petri nets, namely the timed event graphs. Originally,
Petri nets were introduced as nontimed logical models. Timed
Petri nets have been developed for modeling and performance
analysis, but were found less adequate for control purposes.
The theory of timed DES emerged from the combination of
the max-plus algebra framework with the system-theoretic
concepts. The trends of the research on the max-plus algebra
approach to DESs can be found in Ref. 23. Max-plus algebra
is a convenient formalism for the systems in which synchroni-
zation is a key request for event occurrence, including both
discrete events systems and continuous systems that involve
synchronization. Max-plus algebra adequately describes sys-
tems for which the start of an activity requires the completion
of all the activities that provide the inputs needed to perform
the considered activity. In such cases, maximization is the
basic operation. The complementary case is that of the sys-
tems in which an activity starts when at least one input be-
comes available. Minimization is the basic operation and the
min-plus algebra is the adequate algebraic structure. These
two limit cases correspond to the AND and OR operators from
the binary logic, respectively. In mixed systems, both types of
conditions can be present, and other related (usually isomor-
phic) dioid algebraic structures must be used. In the following
we will refer only to the max-plus case.
Aj1
Aif
xj xi
Ain
xn
k k+1
Figure 8. Section of a timed event graph showing only the edges
coming into the node attached to event i. Input variables xj(k); j ⫽ 1,
. . ., n give the moments when events j occur at step k, and the
weights Aij; j ⫽ 1, . . ., n of the edges correspond to the delays pro-
duced by the transport from j to i.
Consider the section of a timed event graph represented in
Fig. 8. Each node corresponds to a certain activity, whereas
the arcs coming into a node represent the conditions required
to initiate the activity attached to the node. An event i (e.g.,
the start of a process) occurs at step k ⫹ 1 in the moment
xi(k ⫹ 1) when all the input events (e.g., the end of the prereq-
uisite processes) have occurred at step k in the respective mo-
ments xj(k); j ⫽ 1, . . ., n, and have propagated from j to i
with the transport delays Aij; j ⫽ 1, . . ., n. The corresponding
discrete-time dynamic system model is given by the equa-
tions:
xi (k + 1) = max(Ai1 + x1(k) , . . ., Aij + x(k)
j
, . . ., Ain + xn(k) ),
(35)
i = 1, . . ., n
The analysis of this model is significantly simplified by the
max-plus algebra formalism.
The max-plus algebra (⺢max, 丣, 丢) is a dioid over the set
⺢max ⫽ ⺢ 傼 兵⫺앝其, where ⺢ is the set of real numbers.
The additive operation 丣 is the maximization
x ⊕ y = max(x, y) (36)
and the multiplicative operation 丢 is the usual addition
xy = x ⊕ y = x + y (37)
The neutral element e with respect to 丢 (the ‘‘one’’ element of
the structure) is 0, whereas the neutral element ⑀ with re-
spect to 丣 (the ‘‘zero’’ element of the structure) is ⫺앝, which
is also the absorbing element of the multiplicative operation:
a 丢 ⫺앝 ⫽ ⫺앝 丢 a ⫽ ⫺앝, ᭙a 僆 ⺢max. This dioid is not a ring
because, in general, an element of ⺢max has no inverse with
respect to 丣. One distinctive feature of this structure is the
idempotency of the addition:

x ⊕ x = x, ∀x ∈ Rmax

The matrix product AB ⫽ A 丢 B of two matrices of fitting

Table 1. Partial Languages of the Generator G in Example 1
sizes (m ⫻ p) and (p ⫻ n) is defined by
R(i, j, k) k⫽1 k⫽2

p
R(1, 1, k) ␧傼a (␧ 傼 a) 傼 (␧ 傼 a)(␧ 傼 a)*(␧ 傼 a) (A ⊗ B)ij = Aik ⊗ Bk j = max (Aik + Bk j ), i = 1, . . ., m;
R(1, 2, k) b b 傼 (␧ 傼 a)(␧ 傼 a)*b k=1,..., p
k=1
R(2, 1, k) a a 傼 a(␧ 傼 a)*(␧ 傼 a) j = 1, . . ., n
R(2, 2, k) ␧傼b (␧ 傼 b) 傼 a(␧ 傼 a)*b (38)
620 DISCRETE EVENT SYSTEMS

The matrix sum A 丣 B of two matrices of the same size (m ⫻ a path for which the initial and the final node coincide. In
n) is defined by the following, we will consider only elementary circuits, i.e.,
circuits that do not pass twice through the same node. The
(A ⊕ B)ij = Aij ⊗ Bij = max(Aij , Bij ), i = 1, . . ., m; j = 1, . . ., n length of a path (circuit) is defined as the number of edges in
(39) the path (circuit). The weight of a path (circuit) is defined as
the 丢 multiplication (i.e., the conventional sum) of the
The multiplication by a scalar a of a matrix A is defined by weights of all the edges in the path (circuit): w(i1 씮 i2 씮 ⭈ ⭈ ⭈
씮 ik) ⫽ Aikik⫺1 ⫹ ⭈ ⭈ ⭈ ⫹ Ai2i1. The average weight of a path is
(a ⊗ A)ij = a ⊗ Aij = a + Aij (40) its weight divided (in the classical way) by its length. For a
circuit, the average weight is sometimes called the circuit
With the formalism of the max-plus algebra, the equations of mean.
a time event graph become
Example 5. Examples of paths in the graph in Fig. 9 are

n
xi (k + 1) = Aij x j (k) i = 1, . . ., n (41)
j=1
1 씮 2 (length ⫽ 1, weight ⫽ 1, average weight ⫽ 1),
1 씮 2 씮 3 (l ⫽ 2, w ⫽ 3, aw ⫽ 1.5),
or, in matrix form, 1 씮 2 씮 3 씮 3 씮 2 (l ⫽ 4, w ⫽ 12, aw ⫽ 3).

x(k + 1) = Ax(k) (42) There are three (elementary) circuits in this graph:

where x(k) ⫽ [x(k) (k) T

1 , . . ., xn ] is the state vector at time k, and
1 씮 2 씮 1 (l ⫽ 2, w ⫽ 4, circuit mean ⫽ 2),
A ⫽ [Aij, i, j ⫽ 1, . . ., n] is the (n ⫻ n) system matrix. 2 씮 1 씮 2 (l ⫽ 2, w ⫽ 8, cm ⫽ 4),
The weighted graph corresponding to a square (n ⫻ n) ma- 3 씮 3 (l ⫽ 1, w ⫽ 3, cm ⫽ 3).
trix A is the triple G(A) ⫽ (N, E, ␸), where N is the set of n
nodes, E is the set of edges, each representing a nonzero entry A graph is strongly connected if there exists a path be-
of A, and ␸ : E 씮 N ⫻ N, with ␸(eij) ⫽ ( j, i), eij 僆 E if and only tween any two nodes of the graph. The matrix corresponding
if Aij ⬎ ⑀. The weight of the edge eij is Aij. In the following, to a strongly connected graph is called irreducible. For an ir-
only graphs for which there is at most one edge between any reducible matrix A, then is a permutation P such that PTA P
ordered pair of nodes, oriented from the first node to the sec- is an upper triangular matrix.
ond, will be considered.
Example 6. The graph in Fig. 9 is strongly connected.
Example 4. The graph in Fig. 9 corresponds to the system
matrix The power of a square matrix Ak is defined recursively by
 
 9  Ak = A ⊗ Ak−1 , k ∈ N∗ (43)
 
A = 1  6
where A0 ⫽ I is the identity matrix, which has (A0)ij ⫽ e if
 2 3 i ⫽ j, and (A0)ij ⫽ ⑀ if i ⬆ j. The entry (Ak)ij of the kth power
of a square matrix A equals the maximum weight for all the
Considering the state at step k given by the vector x(k) ⫽ paths of length k from node j to node i.
[3, 2, 1]T, the vector at step (k ⫹ 1) is A square matrix is aperiodic if there exists k0 僆 ⺞* such
  that (Ak)ij ⬆ ⑀ for all k ⱖ k0. Aperiodicity implies irreducibility
 9  3 because (Ak)ij ⬆ ⑀ means that there exists at least one path of
   length k from node j to node i with weight (Ak)ij. The reverse
x(k + 1) = Ax(k) = 1  6 2
 2 3 1 is not true.
   
(9 ⊗ 2) 11 Example 7. The matrix A corresponding to the graph in Fig.
   
= (1 ⊗ 3) ⊕ (6 ⊗ 1) =  7 9 is aperiodic with k0 ⫽ 4.
(2 ⊗ 2) ⊕ (3 ⊗ 1) 4
As in conventional algebra, if for a square matrix A there
exist a vector v ⬆ [⑀, ⑀, . . ., ⑀]T and a scalar ␭ such that
A path in a graph is a sequence of adjacent edges and nodes:
(i1, i2), (i2, i3), . . ., (ik⫺1, ik) ⬅ i1 씮 i2 씮 ⭈ ⭈ ⭈ 씮 ik. In general, A⊗v = λ ⊗v (44)
it is accepted that a path can pass twice through the same
node or through the same edge. A circuit is a closed path, i.e., then v is called an eigenvector of A, and ␭ is the correspond-
ing eigenvalue.

9 6 Example 8. It is easy to check that

     
x1 x2 x3 7 12 7
1 2 3      
A 3 =  8 = 5 3
Figure 9. Timed event graph corresponding to the system matrix in
e 5 e
Example 4.
 DISCRETE EVENT SYSTEMS 621

where A is the matrix corresponding to the graph in Fig. 9.
The vector v ⫽ [7 3 e]T is an eigenvector of A for the eigen-
value ␭ ⫽ 5.
Some very important properties of the eigenvalues and ei-
genvectors of irreducible matrices are stated next without
proof.
state is reached within a finite number of steps. The periodic
regime is determined only by the length and the average
weight of the critical circuit, which is the slowest circuit in
the system. If A is irreducible and the corresponding graph
has a unique critical circuit of length m and average weight
␭ (the eigenvalue of A), then A is asymptotically periodic with
period m, i.e., there exists a kA 僆 ⺞* such that

• Every square matrix has at least one eigenvalue.
• The eigenvalue is unique for an irreducible matrix.
• For an irreducible matrix, the eigenvalue equals the
maximum circuit mean taken over all circuits in the
strongly connected graph corresponding to the matrix.
Any circuit for which the circuit mean is maximum is called
a critical circuit.
Example 9. The critical circuit of the graph in Fig. 9 is 1 씮
2 씮 1, which has the maximum average weight over all cir-
cuits of the graph. This weight determines the eigenvalue
␭ ⫽ 5 of the matrix A.
Ak+m = λm Ak , for all k ≥ kA (48)
Example 11. For the matrix A considered in Example 4, the
length of the critical path m ⫽ 2, its average weight (the ei-
genvalue of A) is ␭ ⫽ 5, and kA ⫽ 4, so that A6 ⫽ 10 丢 A4.
Indeed, in the max-plus algebra 10 ⫽5 丢 5 ⫽ 52.
The max-plus algebra can thus be used to evaluate the per-
formance of timed discrete systems, in the asymptotic steady
state. For this purpose, the eigenvalue ␭ is the key parameter
of a system described by an irreducible matrix because ␭ de-
termines the speed in the periodic state. Usually, 1/ ␭ is re-
ferred to as the throughput of the system.

The matrix A⫹ is defined by Petri Nets Models


∞ Petri nets theory has been developed as a formalism able to
A+ = Ak (45) describe in a unified way systems that included computers,
k=1 programs, and a certain environment. Previously, the various
components of such systems had to be described in different
Each entry (A⫹)ij of the matrix gives the maximum weight for and unrelated formalisms: automata theory for the computer
all paths of arbitrary length from node j to node i. The length hardware, code in a sequential programming language for the
increases unboundedly, so that the matrix A⫹ diverges. For program, and narrative prose for the interaction of the pro-
an irreducible matrix A, with the eigenvalue ␭, a matrix A␭ is gram with the environment. From the three mentioned ele-
defined by ments, at most one—the program—is sequential so that the
capacity to deal with the characteristics of parallel systems
Aλ = λ−1 A (46)
was a basic request. The timed Petri nets have been intro-
duced in the late seventeen to quantitatively study the perfor-
meaning that (A␭)ij ⫽ Aij ⫺ ␭.
mances of parallel systems, especially referring to (1) concur-
The matrix A␭ has the remarkable property that
rence, the possibility that events occur independently; (2)

∞ 
n synchronization, the necessity that some events wait for the
A+
λ = Akλ = Akλ (47) others before they can occur; and (3) conflicts, the mutual ex-
k=1 k=1 clusion of some events. Petri nets have the advantage to have
a precise semantics and to allow the efficient use of algebraic
where n is the dimension of the square matrix A. As before,
techniques. The event graphs, which are adequate for model-
(A␭⫹)ij is the maximum weight for all paths of arbitrary length
ing collision-free synchronous systems, form a special class of
from node j to node i, in the directed graph corresponding to
Petri nets and can be described by linear equations when us-
A␭. The critical circuit in this graph has the weight e. A␭ has
ing max-plus algebra. An overview of Petri nets and of the
the same eigenvectors as A, but for the eigenvalue e. For any
concepts related to their properties can be found in the survey
node j in a critical circuit of A, the jth column of A␭⫹ is an
paper of Murata (26).
eigenvector of A (and of A␭).
Untimed Petri Nets. An untimed Petri net is defined by (S,
Example 10. For the matrix A considered earlier, the ma-
M0), where S describes the structure of the graph attached to
trix A⫹ diverges, but we can readily calculate A␭ and A␭⫹:
the net and M0 is the initial marking of the net.
    The structural part is characterized by the 5-tuple
 4  e 4 5
   
Aλ = −4  1 , A+λ = −4 e 1 S = (P, T, F, r, s) (49)
 −3 −2 −7 −3 −2
with P the (finite) set of places and T the (finite) set of transi-
The first two columns of A␭⫹ are eigenvectors of A for the ei- tions. The places P (customarily represented by circles) and
genvalue ␭ ⫽ 5. It happens that the third column is also an ei- the transitions T (drawn as bars) form the vertices of a graph.
genvector. The arcs of the graph are given by F 傺 P ⫻ T 傼 T ⫻ P. The
maps r : P ⫻ T 씮 ⺞* and s : T ⫻ P 씮 ⺞* give the (positive)
The asymptotic behavior of the systems described by irre- integer weights of the arcs going from the places toward the
ducible matrices is periodic. Remarkably enough, the steady transitions, and from the transitions toward the places, re-
622 DISCRETE EVENT SYSTEMS

p1 p3 p1 p3 set of markings reachable when starting from a marking M

1 1 and firing transitions is denoted by R(M). The rechability
2 3 2 3
p4 p4 problem—given M1 and M2, establish if M2 僆 R(M1)—is expo-
1 1 1 1 nentially decidable.
t t
p2 p5 p2 p5 A marking M is bounded if for any place p 僆 P the number
of tokens is bounded, i.e., there is a constant integer b 僆 ⺞*
(a) (b) such that M(p) ⬍ b, ᭙p 僆 P. A Petri net is bounded for a
Figure 10. Firing of a transition in a Petri net. (a) Transition t is given initial marking M0 if it is uniformly bounded for any
fireable because for ᭙p 僆 *t ⫽ 兵 p1, p2其, the markings exceed the M 僆 R(M0). A Petri net is safe if the bound is 1. A Petri net
threshold: M(p1) ⫽ 2 ⱖ r(p1, t) ⫽ 2 and M(p2) ⫽ 2 ⱖ r(p2, t) ⫽ 1. (b) is structurally bounded if it is bounded for any initial mark-
After the firing, the markings are M⬘(p1) ⫽ M(p1) ⫺ r(p1, t) ⫽ 0, ing M0. A Petri net is conservative if the number of tokens is
M⬘(p2) ⫽ 1, M⬘(p3) ⫽ M(p3) ⫹ s(t, p3) ⫽ 1, M⬘(p4) ⫽ 4, M⬘(p5) ⫽ 2. constant during the evolution of the system:

|M(p)| = |M0 (p)|, ∀M ∈ R(M0 )
spectively. It is customary to inscribe only the arcs with the p∈P p∈P
weights exceeding one, whereas the arcs without any inscrip-
tion have unit weight by default. Sometimes, edges with a Example 13. The Petri net in Fig. 10 is not conservative.
larger weight are represented by the corresponding number
A transition t in a Petri net is alive for a marking M 僆
of unit weight arcs in parallel. The places may contain zero
R(M0), if there exists M⬘ 僆 R(M) such that t is fireble under
or more tokens, usually drawn as black circles. A marking or
M⬘. A transition is structurally alive if it is alive for any ini-
‘‘state’’ of a Petri net is given by the distribution of the tokens
tial marking. A Petri net is (structurally) alive if all its transi-
at a certain moment: M : P 씮 ⺞, where M(p) gives the number tions are (structurally) alive.
of tokens in the place p 僆 P. The initial marking is given The incidence matrix of a Petri net is the 兩T兩 ⫻ 兩P兩 matrix
by M0. A with the elements
Given a transition t 僆 T, the input place set of t is defined
by Aij = s(i, j) − r( j, i) (55)
∗
t = {p ∈ P : (p, t) ∈ F} (50) The evolution vector uk at step k is a unipolar binary vector
of size 兩T兩
and the output place set, by:
u k = (1, 0, 1, . . ., 0, 0)T (56)
∗
t = {p ∈ P : (t, p) ∈ F} (51)
which has the entries one for the transitions that fire at step
Similarly, for a place p 僆 P, the input transition sets of p is: k and zero for the others.
∗
The net marking at step k can be described by a vector
p = {t ∈ T : (t, p) ∈ F} (52) Mk for which the evolution law is

whereas the output transition set is M k = M k−1 + A T u k ; k ∈ N∗ (57)

p∗ = {t ∈ T : (p, t) ∈ F} (53) A firing sequence 兵uk兩k ⫽ 1, 2, . . ., d其 is globally character-

ized by the firing vector
The dynamics of the Petri net is determined by the marking
M. A transition t is enabled on a marking M, if the number
d
x= uk
of tokens in each place p from which there is an arc toward
k=1
the transition t exceeds or at least equals the weight of the
arc, i.e., if M(p) ⱖ r(p, t) for all p 僆 *t. An enabled transition whereas the final marking is given by
may fire. When a transition t fires, the number of tokens in
the places p 僆 *t 傼 t* 傺 P changes. The number of tokens is M f = M0 + A T x (58)
decreased for each input place p 僆 *t with r(p, t) pieces and
increased with each output place p 僆 t* with s(t, p) pieces. where M0 is the initial marking, and Mf is the final marking.
Consequently, the marking of the network places p 僆 P
Example 14. Untimed Petri nets have been used for the vali-
changes from M(p) to M⬘(p), according to the rule
dation of communication protocols. The Petri net in Fig. 11

 ∗
M(p) − r(p, t), p ∈ t

M  (p) = M(p) + s(t, p), p ∈ t ∗ (54) Send message Receive message


M(p), otherwise Write Read
message message
Read Write
Example 12. Figure 10(a) represents a transition for which acknowledgment acknowledgment
the firing conditions are fulfilled. Figure 10(b) gives the mark-
ing resulted after the fire. Receive Send
acknowledge acknowledge

A marking M2 is reachable from a marking M1 if a se- Figure 11. Untimed Petri net model of a communication protocol
quence of transition firings leading from M1 to M2 exists. The with acknowledge of reception.
 DISCRETE EVENT SYSTEMS 623

shows such a protocol with acknowledge of reception. The sys- p p′ tp p′′

tem comprises cycles on the emitting and receiving parts. The
position of the tokens gives the state of the system, whereas
the actions are represented by the transitions. The sending σ p(n) σ p′(n) = 0 σ p′′(n) = 0
side waits for confirmation from the receiving part before pro-
σtp(n) = σp(n)
ceeding to the transmission of the next message. The receiv-
ing side is ready for a new message only after having sent out (a)
the acknowledgment for the preceding one. The arrival of the
next message can then trigger a new cycle for sending out
the confirmation. t t′ pt t′′

Timed Petri Nets. Timed Petri nets offer a general formal-

ism adequate for including a measure of time in the descrip- ϕ t(n) ϕ t′(n) = 0 ϕ t′′(n) = 0
tion of a DES. Petri nets are especially adequate to model σpt(n) = ϕ t(n)
concurrent or parallel discrete systems. A First In–First Out
(b)
(FIFO) discipline is usually adopted for all the places and all
the transitions. Time-related parameters are attached Figure 12. (a) Petri net comprising only timed transitions where the
to each process taking place in the net. If the nth token enters rest time of place p has been assigned as the duration of the equiva-
a place p at the moment u, it becomes ‘‘visible’’ for the transi- lent transition tp. (b) Dual case of a net comprising only timed places
tions in p* only after the moment u ⫹ ␴p(n), where ␴p(n) is where transition t has been replaced with place pt.
the rest time of the nth token in place p. An initial latency
time is also ascribed to each initial token in a place p. If
M0(p) ⱖ n, the nth token existing in place p at the initial
moment becomes available for the transitions in p* starting t 僆 T; vp(n), wp(n) is the entering and the release mo-
from a moment ␰p(n). The initial latency time is a special case ments, respectively, of the nth token in the place p 僆 P,
of the rest time and allows modeling the peculiarities of the
• The counters: xt(u), yt(u) is the number of times the tran-
initial phase, whenever necessary. Similarly, the nth fire of a
sition t 僆 T has started and ended, respectively, the fire
transition t started at a moment u, ends at moment u ⫹
at moment u; vp(u), wp(u) is the number of tokens enter-
␸t(n), where ␸t(n), is the duration of the nth firing of the tran-
ing and leaving, respectively, place p at moment u.
sition t. The tokens are taken from the input places of the
transition t and moved to the output places at the moment
u ⫹ ␸t(n). The following conventions are commonly accepted:
The time parameters have to satisfy certain natural re-
strictions:
• xt(0) ⫽ yt(0) ⫽ vp(0) ⫽ wp(0) ⫽ ⫺앝,
• All the rest times and transition durations must be non- • xt(n) ⫽ yt(n) ⫽ vp(n) ⫽ wp(n) ⫽ 앝, if the transition t never
negative ␴p(n) ⱖ 0, ␸t(n) ⱖ 0 for all p 僆 P, t 僆 T, and fires n times, or the place p never receives n tokens,
n 僆 N*. • xt(u) ⫽ yt(u) ⫽ wp(u) ⫽ 0 and vp(u) ⫽ M0(p) for u ⬍ 0.
• The initial latency times can be both positive and nega-
tive, but they are restricted by the weak compatibility
conditions that require that for each place p: (1) there For any transition t 僆 T, where n 僆 N*
exists no transition before the initial moment t ⫽ 0 so
that M0(p) retains its meaning of initial marking, (2) the yt (n) = xt (n) + ϕt (n) (60)
initial tokens in a place p are taken by the output transi-
tions in p* before the tokens supplied to p by the input The FIFO rule requires
transitions in *p.
wp (n) ≥ vp (n) + σp (n) for ∀p ∈ P, ∀n ∈ N ∗ (61)
A timed Petri net is thus defined by the n-tuple

TPN(S, M0 ,
, φ, ) (59)
where S is the structural part, M0 is the initial marking, ⌺ ⫽
兵␴p(n); n 僆 N*兩p 僆 P其 is the set of rest times, ␾ ⫽ 兵␸t(n); n 僆
N*兩t 僆 T其 is the set of transition durations, and ⌶ ⫽ 兵␰p(n);
n 僆 N*兩p 僆 P其 is the set of initial latencies.
Equivalent Petri nets having only timed transitions or only
timed places can be built, as shown in Fig. 12 (a, b).
The following state variables are defined to describe the
time evolution of a Petri net:
• The schedulers: xt(n), yt(n) is the beginning and the end
moments, respectively, of the nth fire of the transition
meaning that the order of the tokens are not changed at any
of the places, and
y t [ yt (n)] = x t [xt (n)] for ∀t ∈ T, ∀n ∈ N ∗ (62)
meaning that a transition cannot start its (n ⫹ 1)th fire before
ending the nth one.
A Petri net is called FIFO if all its places and transitions
observe the FIFO discipline. Usually, the stronger conditions
of constant rest times and constant transition durations are
used. The FIFO constrained can result from the structure of
network, without any hypothesis on the net temporizations.
624 DISCRETE EVENT SYSTEMS
Figure 13. Cyclic transition with structurally restricted FIFO be-
havior.
Example 15. The Petri net in Fig. 13 contains a cyclic transi-
tion which behaves FIFO for any sequencing of the firing.
Timed Petri nets can be used for quantitative performance
evaluation, e.g., when studying various queuing types. Most
classical networks like Jackson single classes, fork-join
queues, and token rings can be modeled with Petri nets,
whereas others like multiclass networks, Kelly networks, and
processor-sharing systems cannot.
Example 16. Figure 14 represents the Petri net models of
some classic types of queues. The Kendall notation is used to
describe a queue. The simplest queue, with any input process
(.), any distribution of the timings of the server (.), one server
(1) and an unlimited buffer (앝) is designated by ././1/앝.
Petri nets allow a unified treatment of a large class of sys-
tems, avoiding the usual case-by-case performance evalua-
tion. It has been shown that Petri nets with inhibitor edges
(i.e., with a special kind of edges from places to transitions,
which trigger the transitions only when the place is empty)
have the computing power of a Turing machine.
The Petri nets can be characterized both by basic qualita-
tive properties like stability, existence of a stationary state,
and the duration of the transient state and by performance
Que././1/•
...
(a)
Que././1/k
...
...
k 2 1
(b)
Que././2/•
...
(c)
Figure 14. Queue theory and Petri net models of some classic types
of queues: (a) Infinite buffer, single server; (b) Finite buffer, single
server; (c) Infinite buffer, double server.
tij ti
pi pij
pj
ph phj tj
thj th
(a) (b)
Figure 15. Special cases of Petri nets: (a) model of a state machine,
(b) model of an event graph.
parameters like throughput of a transition or average number
of tokens in a place. Petri nets include as special cases other
frequently used models like state machines, event graphs,
and free-choice nets. The following structural conditions de-
fine the mentioned special cases:
• A state machine is a Petri net for which
|∗ t| = |t ∗ | = 1; ∀t ∈ T (63)
i.e., each transition has exactly one input place and one
output place. As a consequence, between any two places
pi and pj there is at most one transition that would be
denoted by tij, with 兵 pi其 ⫽ *tij, 兵 pj其 ⫽ tij*, 兵tij其 ⫽ pi*傽*pj, as
shown in Fig. 15(a).
• An event graph is a Petri net with
|∗ p| = |p∗ | = 1; ∀p ∈ P (64)
i.e., each place has exactly one input transition and one
output transition. Correspondingly, between any two
transitions ti and tj, there is at most one place pij, with
兵ti其 ⫽ *pij, 兵tj其 ⫽ pij*, 兵 pij其 ⫽ ti*傽*tj, as shown in Fig. 15(b).
• A free-choice net is a Petri net for which
∀p ∈ P, |p∗ | > 1 ⇒ ∀t ∈ p∗ , |∗ t| = 1 (65)
meaning that if a place p has more than one output tran-
sition, than the place p is the only input place for each of
its output transitions. It results that a free-choice graph
contains substructures of the type shown in Fig. 16, so it
can model both synchronization [Fig. 16(a)] and choice
[Fig. 16(b)], but not both of them for the same process.
Free-choice machines include the state machines and the
event graphs, again as special cases. The event graphs
model only synchronization; they exclude choice. It has
(a) (b)
Figure 16. Special cases of Petri nets—the free-choice nets: (a) sub-
structures modeling synchronization, (b) substructures modeling
choice.
 DISCRETE EVENT SYSTEMS 625

been shown than an event graph is alive if each circuit ././1/•→././1/•

in the graph contains at least one token. In the opposite
case, the net will run into a dead lock after a finite num-
ber of firing instances. In a timed event graph, a place
containing k tokens can be replaced by k chained places,
each one containing exactly one token, interlaced with p1 t1 p2 t2
k ⫺ 1 transitions (Fig. 17). The rest time ␴p of the initial
(a)
place is attributed to one of the places in the chain, all
the other places and transitions having no delays.
././1/•→././1/•
Timed event graphs can be represented as linear systems
by using max-plus algebra. Because of the special structure
of a timed event graph, it is convenient to make the analysis
in terms of the transitions. Let us denote by xi(n) the start
moment of the nth firing instance of the transition ti, i ⫽ 1, p1 t1 p2 t2 p3 t3
. . ., k; k ⫽ 兩T兩, and by ●ti the set of the input transitions of
ti:
p5 p4
•ti = ∗ (∗ti ) = {t j |t j ⊂ ∗ p, ∀p ∈ ∗ ti } ⊂ T (66)
(b)
Consider the nth firing of a transition ti 僆 ●ti. Using the Figure 18. Chained queues: (a) no deadlocks, (b) after-service
equivalence in Fig. 16, the place pji 僆 P contains at most one deadlock.
token. If M(pji) ⫽ 0, then the token enables the nth firing of
ti; else if M(pii) ⫽ 1, it enables the (n ⫹ 1)th firing of ti. This
results in the equation The minimal solution of (71) is given by the linear recurrence
relation
x j (n + 1) > max{x j [n + 1 − M(p ji )] + ϕt + σ p ji } (67)
i
j∈•t i
x(n + 1) = A∗0 A1 x(n) (73)

where x ⫽ xj[n ⫹ 1 ⫺ M(pji)] is the start moment of the [n ⫹ Using the max-plus algebra framework, the equations of a
1 ⫺ M(pji)]th firing of the transition tj, x ⫹ ␸tj is the end mo- timed event graph become linear. As shown at Eq. (48), a re-
ment of this process, and xi ⫹ ␸tj ⫹ ␴pji is the moment the lation in the form of Eq. (73) determines a periodic stationary
transition ti is enabled by tj. solution. This means that event graphs have a cyclicity prop-
With the delay matrices A움, 움 ⫽ 0,1, defined by erty: after n firings of each transition, the marking returns
 exactly to the initial marking. However, this is only a formal
ϕt i + σ p ji , if ti ∈ •ti and M(p ji ) = α
(Aα )ij = (68) result valid in the firing event ordering scale, not in the time
 = −∞, otherwise scale. The nth firing for different transitions occurs at differ-
ent time moments xti(n) so that there exists no time period
Eq. (67) can be written in the matrix form which after the marking is repeated.

x(n + 1) ≥ A0 x(n + 1) ⊕ A1 x(n) (69) Example 17. Figure 18 presents two examples of chained
queues and their corresponding Petri net (event graph) mod-
With els. The systems contain each of two servers preceded by
queues. The example in Fig. 18(a), for which both queues

∞ 
k
A∗0 = Ai = Ai = I + A+
0 (70) have infinite buffers, has no deadlocks. The example in Fig.
i=0 i=0 18(b), exhibits an after-service deadlock. A client leaving the
first queue when the buffer of the second queue is full must
[see Eq. (45)], wait in place p2; consequently, the access of a new client to
the first service is denied.
A∗0 (I − A0 ) = A∗0 (I − A0 ) = I (71)

results. Relation (69) becomes CONTROL OF DISCRETE EVENT SYSTEMS

x(n + 1) ≥ A∗0 A1 x(n) (72) One major goal in studying DESs has been to devise methods
for controlling the trajectory of a system so as to reach a cer-
tain set of desired states, or to avoid some undesired states—
ϕ t1 ϕ t2 ϕ t1 ϕ t′ = 0 ϕ t′′ = 0 ϕ t2 including deadlocks or traps. As pointed out in the work of
σp σ p′ = 0 σp′′ = 0 σp Ramadge and Wonham (16–18), DESs fully qualify as objects
≡ for the control theory because they exhibit the fundamental
p p′ p′′ p features of potentially controllable dynamic systems. Actu-
t1 t2 t1 t′ t′′ t2
ally, a large part of the work performed in the DES domain
Figure 17. Equivalence of a place containing k tokens with k chained has been motivated by the search for proper techniques to
places each one containing exactly one token. control event sequences and to select the ones that comply
626 DISCRETE EVENT SYSTEMS
with various restrictions or optimization criteria. In the fol-
lowing, we will explore the basics of DESs control within the
framework of state machines and formal languages, as initi-
ated by Ramadge and Wonham. The events are considered
spontaneous and process-generated. The control consists of
forbidding the occurrence of some of the events so as to re-
strict the behavior of a system to avoid undesirable trajector-
ies. Automatic control is performed by means of another sys-
tem, which tests the controlled system and acts upon it
according to the available information. Thus, the set of events
⌺ can be partitioned into two disjoint subsets: ⌺u, containing
the uncontrollable events, and ⌺c, containing the controllable
ones. The control is provided by a supervisor or a discrete
event controller (DEC), which has the ability to influence the
evolution of the system by enabling and disabling the control-
lable events, i.e., by allowing or prohibiting their occurrence,
so as to perform a certain control task. Various control tasks
can be defined: (1) control invariance requires that a specified
predicate remains invariantly satisfied whenever initially sat-
isfied, meaning that the behavior of the system remains con-
fined within specified bounds, (2) region avoidance requires
that the system does not satisfy undesirable predicates when
traversing the state space, and (3) convergence requires that
the system to evolve toward a specified target predicate from
given initial conditions.
The main difficulty in modeling complex processes by
considering all the states and all the events is the combina-
torial explosion in the number of their states. A way to
keep the complexity manageable is to use event internaliza-
tion, or partial observation, which leads to nondeterministic
process behavior. Markov chain representation, or GSMP
models, can be used to describe complex DESs in a formal-
ism that has the capability to relax the requirement that
all states and all event sequences be explicitly in the model.
Other approaches to achieve an effective modeling are
based on the concept of modularity and hierarchy that lead
to structured models of lower complexity in comparison
with the case when all individual components are taken
directly into account.
Controllability and Reachability
Consider a DES modeled by the generator G ⫽ (Q, ⌺, ⌬, s,
Qm), where Q is the state space (an arbitrary set), ⌺ is the
event set (or the alphabet, a finite set), ⌬ is the evolution law
[a relation on Q ⫻ ⌺ ⫻ Q, which generalizes the transition
function, see comments on Eq. (26)], s ⫽ q0 is the start (initial)
state, and Qm 傺 Q is the set of marker states. As mentioned
before, the marker states were introduced by Ramadge and
Wonham to identify the ‘‘completed tasks.’’ The set of events
⌺ is partitioned into ⌺c, the set of controllable events, and
⌺u, the set of uncontrollable events, with ⌺ ⫽ ⌺c 傼 ⌺u, ⌺c 傽
⌺u ⫽ 0 兾.
A state q 僆 Q is called reachable from the initial state
s ⫽ q0, if there exists a path (q0␴1q1␴2 . . . ␴nqn) 僆 B(G), such
that qn ⫽ q, i.e., if there exists w ⫽ ␴1␴2 . . . ␴n 僆 ⌺*, such
that (q0, w, qn) 僆 ⌬*.
A state q 僆 Q is called controllable if there exists w 僆 ⌺*
and qm 僆 Qm, such that (q, w, qm) 僆 ⌬*.
Correspondingly, a generator is called reachable (controlla-
ble) if all the states q 僆 Q are reachable (controllable).
A generator is called trim if it is both reachable and con-
trollable.
A generator is called deterministic [see Eq. (18)] if for all
q 僆 Q and ␴ 僆 ⌺, there exist at most one state q⬘ 僆 Q such
that (q, ␴, q⬘) 僆 ⌬*. In this case, a transition (partial) function
can be defined such that q⬘ ⫽ 웃(q, ␴), as shown at Eq. (1) and
discussed at Eq. (26).
The control of a DES described by a generator G is pro-
vided through a control pattern 웂 : ⌺ 씮 兵0, 1其, defined such
that for a state ␴ 僆 ⌺c, 웂(␴) ⫽ 1 if ␴ is enabled and 웂(␴) ⫽ 0
if ␴ is disabled. For all ␴ 僆 ⌺u, 웂(␴) ⫽ 1 as these events can
not be disabled. The set of control patterns 웂 is denoted by ⌫
傺 兵0, 1其⌺.
For each control pattern, a new generator G(웂) ⫽ (Q, ⌺,
⌬웂, s, Qm) is obtained, where the controlled evolution relation
⌬웂 is defined by
∀q, q ∈ Q, ∀σ ∈
:
(q, σ , q ) ∈ γ ⇔ (q, σ , q ) ∈  and γ (σ ) = 1 (74)
The set of enabled events, also called the control input, for a
control pattern 웂 is given by

e (γ ) = {σ ∈
|γ (σ ) = 1} =
ce (γ ) ∪
u (75)
where the control pattern 웂 plays the role of the characteristic
function of the set.
As mentioned earlier, ⌺u 傺 ⌺e(웂), for any control pattern 웂.
The set of feasible events for a state q 僆 Q of the genera-
tor G(웂) is given by ⌺f(q) 傽 ⌺e(웂).
The set of all control inputs is

e () = {
e (γ )|γ ∈ } ⊆ 2
(76)
The control of G through ⌫ consists in choosing a specific 웂
when the system is in a certain state q 僆 Q, after a certain
sequence of events w 僆 L, according to the assumed control-
ling task.
The choice of a particular control pattern 웂 僆 ⌫ can be
considered itself an event, so that a controlled discrete event
system (CDES) with the generator
G() = (Q,
× ,  , s, Qm ) (77)
can be defined where the evolution law given by
[q, (σ , γ ), q] ∈  ⇔ (q, σ , q ) ∈ γ (78)
Example 18. For the single model of a machine shown in
Fig. 2, the control could consist of honoring or turning down
requests to start a new task and passing from idle (I) to work-
ing state (W), taking into account the history of machine evo-
lution.
The set ⌫ consist of two control patterns, namely 웂0, which
disables the requests
γ0 (S) = 0, γ0 (C) = γ0 (B) = γ0 (R) = 1
and 웂1, which enables the requests
γ1 (S) = γ1 (C) = γ1 (B) = γ1 (R) = 1
 DISCRETE EVENT SYSTEMS 627

For the system in Fig. 4 comprising two simple machines, the

control of one of the machines can be made dependent of the c2
2
state of the other (e.g., the second machine accepts requests m2 c3
only if the first one is down). 1
m2 m1

Supervision c1
0
In the standard control terminology, the generator G plays m6
c7
the role of the plant, the object to be controlled. The agent c4 m4
doing the controlling action will be called the supervisor. For- 3
mally, a supervisor over ⌫ is a pair c5 c6
m5 4
S = (T, ϕ) (79)
Figure 19. The cat-and-mouse maze. The cat starts from room 2; the
where T is a reachable deterministic generator T ⫽ (Q⬘, ⌺, ⌬, mouse starts from room 4. The cat and the mouse each use only the
s⬘0, Q⬘m) and ␸ : Q⬘ 씮 ⌫ is the map that specifies, for each state passages labeled c and m, respectively. Control the system by (mini-
q⬘ 僆 Q⬘ reached by the generator of the supervisor, what con- mally) forbidding some of the passages (except c7), to prevent the dan-
trol pattern 웂 ⫽ ␸(q⬘) must be applied to G(⌫). gerous encounter of the parties.
If the behavior of G(⌫) is used to determine the state of T,
a supervised generator results
by the control are not included in the transition structure
(G, S) = [Q × Q ,
, G,S , (s0 , s0 ), Qm × Qm ] (80)
of S.
• If s 僆 L(G, f), s␴ 僆 L(G) and ␴ 僆 f(s), then s␴ 僆 L(S).
where This condition ensures that a transition possible in G
and allowed by the control is included in the transitive
[(q1 , q1 ), σ , (q2 , q2 )] ∈ G,S structure of S.
 (81)
(q1 , σ , q2 ) ∈  and (q1 , σ , q2 ) ∈  and γ (σ ) = [ϕ(q2 )](σ ) = 1 An event ␴ can occur in G ⫻ S and produce the transition
(q, x) 씮 (q⬘, x⬘), only if ␴ is possible in both G and S, and
produces the transitions q 씮 q⬘ and x 씮 x⬘. This form of su-
The supervisor has authority only over controllable events.
pervision can be obtained from the state realization (S, ␸) by
The uncontrollable events ⌺f(q) 傽 ⌺u that may occur in a state
trimming the transition structure of S (16).
q of the plant are called disturbances (disturbing events).
Consider a DES for which the unsupervised (open loop) be-
Again, in standard control theory terminology T is the ob-
havior is given by a language L. One of the key issues is to
server, while ␸ implements the feedback, so that the super-
specify the properties of a sublanguage K 債 L that is achiev-
vised generator operates in closed loop. Various algorithms
able under supervision. Because the uncontrollable events
are given in the literature for the synthesis of supervisors
continue to occur even for the closed loop (supervised) system,
able to achieve different control tasks for deterministic or sto-
the prefix closure K of such a controlled language K has to be
chastic DESs.
invariant under the perturbation of the uncontrollable events.
The supervisor implements a map f: L(G) 씮 ⌫e specifying
On the other hand, as K is a restriction of L, not any words
for each observed string of events w 僆 L(G) the control input
in ⌺* containing uncontrollable events can occur, but only
⌺e(웂) ⫽ f(w) that must be applied to G. When designing a
those that are also generated in the open loop conditions (i.e.,
supervisor, the objective is to obtain a CDES that obeys the
that belong to L). It results that every word that belongs to L
control constraints imposed by the considered control task.
and is composed by a prefix string w 僆 K, followed by an
This means suppressing the undesirable sequences of events,
uncontrollable event ␴ 僆 ⌺u (i.e., every word of the form
while restricting as little as possible the overall freedom of
w␴ 僆 L), must also be a prefix string of K, i.e., w␴ 僆 K.
the system.
The behavior of the supervised generator is described by
the language L(G, f) defined by ⑀ 僆 L(G, f), w␴ 僆 L(G, f), if
and only if w 僆 L(G, f), ␴ 僆 f(w) and w␴ 僆 L(G). 2 2
c2
The marked language controlled by f in G is Lm(G, f) ⫽ m2
Lm(G) 傽 L(G, f), i.e., the part of the original marked language
1 c3 1 m1
that is allowed under the supervision. If Qm represents com- c1
pleted tasks, the language Lm(G, f) indicates the tasks that m3
c7 0 m6 0
will be completed under supervision.
The supervisor S can also be modeled as another DES c4
3 c6 3 m4
whose transition structure describes the control action on G.
The following requirements have to be satisfied: c5 m5
4 4

• If s 僆 L(G, f) then s 僆 L(S), and s␴ 僆 L(S) only if ␴ 僆 Figure 20. Generator models for the cat and for the mouse moving
f(s). This condition ensures that the transitions disabled independently in the maze of Fig. 19.
628 DISCRETE EVENT SYSTEMS
c 1, c 4, c 7, m 6
c 3, m 5
q′0 q′1
c 2, m 4
Figure 21. The generator of the supervisor for the cat-and-mouse
problem.
Thus, a language K 債 L 債 ⌺* is called controllable if
K
u ∩ L = K
Consider now a nonblocking DES with the behavior L(G) and
the marked behavior Lm(G). For any nonempty K 債 L, there
exists a supervisor f such that Lf ⫽ K if and only if K is a
prefix closed and controllable language. Similarly, for any
nonempty K 僆 Lm, there exists a supervision f such that
Lmf ⫽ K and the closed loop behavior is not blocking
if and only if K is controllable and Lm is closed (i.e., K 傽 Lm
⫽ K).
Thus it is possible to find a supervisor f so that Lf ⫽ K
when K is prefix closed and controllable. The proof of this
proposition (18) provides an algorithm for constructing the
state realization (S, ␸) of the supervisor f from a generator
of the controllable language K. For an arbitrary K 債 ⌺*,
the family of controllable sublanguages of K is nonempty
and closed under the set union and has a unique supremal
element K† under the partial order of subset inclusion. This
supremal sublanguage (which can be the empty language)
provides an optimal approximation of K by preserving the
restrictions imposed by K, but requiring a minimally re-
strictive control. Denote by P(⌺*) the set of all languages
over ⌺* (the power set of ⌺*), and define ⍀ : P(⌺*) 씮
P(⌺*) by
(J) = K ∩ sup[T : T ⊆
∗ , T = T, T
u ∩ L = J]
The supremal sublanguage K† is the largest fixpoint of ⍀, i.e.,
the largest language satisfying ⍀(J) ⫽ J. The iterations
K j+1 = (K j ), j = 0, 1, 2, . . ., with K0 = K
converge to K† after at most mn steps, where m and n are the
number of states of the generators of L and K, respectively.
Example 19. Consider the famous cat-and-mouse maze (Fig.
19) introduced by Ramadge and Wonham (16), and used as a
typical example of untimed DES control ever since (e.g., see
the attractive Ref. 15). The cat uses only the doors labeled
c1, . . ., c7, whereas the mouse uses only those labeled m1,
. . ., m6. The generator models for the cat and the mouse are
shown in Fig. 20. The state i for either of them corresponds
to the room it occupies, whereas the events correspond to the
transitions i 씮 j from one room to another. We assume that
Table 2. Mapping of Supervisor States to Control Patterns for the Cat-and-Mouse Maze Example
␴ c1 c2 c3 c4
␸ (q⬘0 ) ⫽ 웂0 1 1 1 1
␸ (q⬘1 ) ⫽ 웂1 1 1 0 1
door c7 is uncontrollable, ⌺u ⫽ 兵c7其, whereas all the other doors
can be opened or closed to control the movement of the cat
and the mouse. As shown earlier (see Figs. 3 and 4 at Exam-
ple 2), the joint generator model when composing the genera-
tors of two subsystems has the state set Q ⫽ Q1 ⫻ Q2, and
the event set ⌺ ⫽ ⌺1 傼 ⌺2. The problem is to find the control
scheme that leaves the greatest freedom of movement to both
parties but that ensures that they (1) never occupy the same
room simultaneously and (2) can always return to their initial
state, i.e., the cat in room 2 and the mouse in room 4. The
first condition forbids the states (i, i), while the second sets
(82)
the marker state set Qm ⫽ 兵(2, 4)其. To build the generator of
the controlled system, i.e., of the system obeying the con-
straints, the following pruning steps are performed on the
composed generator model for both the cat and the mouse:
1. Delete the forbidden states 兵(i, i)兩i ⫽ 0, 1, . . ., 4其, that
correspond to the cat and the mouse being in the same
room.
2. Eliminate the edges of the composed graph ending in
the forbidden states, i.e.,
c3 c6 m3
(2, 0) → (0, 0), (4, 0) → (0, 0), (0, 1) → (0, 0), (0, 3)
m6 c1 c7
→ (0, 0), (0, 1) → (1, 1)(3, 1) → (1, 1), (1, 2)
m2 c2 m1
→ (1, 1), (1, 2) → (2, 2), (2, 0) → (2, 2), (0, 3)
c4 c7 m5
→ (3, 3), (1, 3) → (3, 3), (3, 4) → (3, 3), (3, 4)
c5 m4
→ (4, 4), (4, 0) → (4, 4)
3. Discard the states reachable only from the previously
deleted states, i.e., the states (4, 3) and (2, 1).
4. Remove the states for which the output edges corre-
spond to uncontrollable events (⌺u ⫽ 兵c7其) and lead to
previously deleted states, i.e., the states (1, 3) and
(83)
(3, 1).
5. From the resulting graph retain only the trim part, con-
taining the reachable and controllable states.
(84) The supervisor can be further simplified by an aggregation
of technique. The result is a supervisor S ⫽ (T, ␸), where T is
given in Fig. 21, and the map ␸ is given in Table 2. The state
set Q⬘ of T is made up of only two states q⬘0, q⬘1. In the initial
state q⬘0 —when the cat is in room 2 and the mouse in room
4—all the transitions are enabled; in the state q⬘1 —when one
of the parties has left its initial room—the set of transitions
c3, c5, m1, and m5 are disabled. This actually isolates either
the mouse in room 4 (closing c5 and m5) when the cat is out of
room 2 or the cat in room 2 (closing c3 and m1) when the
mouse is out of room 4. It can be noticed that transitions c5,
c6, m1, m2, m3 can no longer occur for the controlled system,
being either directly forbidden, or impossible because of the
restrictions.
c5 c6 c7 m1 m2 m3 m4 m5 m6
1 1 1 1 1 1 1 1 1
0 1 1 0 1 1 1 0 1

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PAUL DAN CRISTEA

‘‘Politehnica’’ University of
Bucharest

DISCRETE EVENT SYSTEMS (DES). See DISCRETE

EVENT DYNAMICAL SYSTEMS.
DISCRETE HARTLEY TRANSFORMS. See HARTLEY
TRANSFORMS.
DISCRETE-TIME ANALOG CIRCUITS. See SWITCHED
CAPACITOR NETWORKS.

DISCRETE TIME FILTERS
A signal is defined as any physical quantity that varies with
the changes of one or more independent variables. Even that
J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.
DISCRETE TIME FILTERS 631
independent variable can be any physical value, for example
distance, it is usually refered to as ‘‘time’’. The independent
variable may be either continuous or discrete. If the indepen-
dent variable is continuous, the signal is called continuous-
time signal or analog signal. Most of the signals that we en-
counter in nature are analog signal, such as a speech signal.
The discrete-time signals are those for which the independent
variable is discrete. The amplitude of both the continuous-
and discrete-time signals may be continuous or discrete. Digi-
tal signals are those discrete-time signals for which the am-
plitude is discrete, and switched-capacitor signals are dis-
crete-time signals with continuous amplitude. Any operation
on a signal which is performed in order to obtain some more
desirable properties, such as less noise or distortion, is called
signal processing. A system which performs signal processing
is called a filter. Signal processing depends on used technol-
ogy and can be (1) analog signal processing (ASP) and (2) dis-
crete-time signal processing (DTSP). Prior to 1960, ASP was
mainly used; this means signals are processed using electrical
systems with active and passive circuit elements. ASP does
have some limitations such as (1) fluctuation of the compo-
nent values with temperature and aging, (2) nonflexibility, (3)
cost, and (4) large physical size. In order to overcome those
limitations, discrete-time technologies are introduced, such as
digital technology and switched-capacitor technologies. Digi-
tal technology, which gives many advantages over ASP [see
Kuc (1) for a more detailed analysis], needs to convert an ana-
log signal into a digital form. Processing the signal by digital
technology is called digital signal processing (DSP), and is a
special case of DTSP. In DSP, both amplitude and time are
discrete, unlike switched-capacitor processing where ampli-
tude is continuous.
DISCRETE-TIME SIGNALS AND SYSTEMS
A discrete-time signal (discrete signal) is defined as a function
of an independent variable n that is an integer. In many
cases, discrete signals are obtained by sampling an analog
signal (taking the values of the signal only in discrete values
of time). According to this, elements of the discrete signals
are often called samples. But this is not always the case.
Some discrete signals are not obtained from any analog signal
and they are naturally discrete-time signals. There are some
problems in finding a convenient notation in order to make
the difference between continuous-time and discrete-time sig-
nals, and various authors use different notations [see Rora-
baugh (2) for detailed analysis]. Recent practice, introduced
by Oppenheim and Schafer, 1989, (3) uses parantheses () for
analog signals and brackets [ ] for discrete signals. Following
this practice, we denote a discrete signal as 兵x[n]其 or x[n].
Therefore x[n] represents a sequence of values, (some of
which can be zeros), for each value of integer n. Although the
x-axis is represented as the continuous line, it is important to
note that a discrete-time signal is not defined at instants be-
tween integers. Therefore, it is incorrect to think that x[n] is
zero at instants between integers.
Discrete signals can be classified in many different ways.
If the amplitude of the discrete signal can take any value in
the given continuous range, the discrete signal is continu-
ously in amplitude, or it is a nonquantized discrete-time sig-
nal. If the amplitude takes only a countable number of dis-
crete values, the signal is discrete in amplitude or a quantized
632 DISCRETE TIME FILTERS
discrete-time signal. This signal is also called a digital signal.
If the signal has a finite number of elements, it is finite; oth-
erwise, it is infinite. Therefore, the finite signal is defined for
a finite number of index values n. Unlike an infinite signal,
which is defined for an infinite number of index values n and
can be: (1) right-sided, (2) left-sided, and (3) two-sided. The
right-sided sequence is any infinite sequence that is zero for
all values of n less than some integer value N1. The left-sided
sequence is equal to zero for all n more than some integer
value N2. The infinite sequence which is neither right-sided
nor left-sided is a two-sided sequence. According to their na-
ture, signals can be deterministic and random. The signals
where all values can be determined without any uncertainty
are deterministic. Otherwise, they are random and cannot be
described by explicit mathematical relationships but by using
the probability theory. We consider here deterministic signals
and systems. Schwartz and Shaw (4), Hayes (5), and Candy
(6) consider random discrete signals and systems. A discrete
signal is periodic if the values of the sequence are repeated
every N index values. The smallest value of N is called the
period. A continuous periodic signal does not always result in
a periodic discrete signal.
There are some basic discrete signals which are used for
the description of more complicated signals. Such basic sig-
nals are (1) unit sample, (2) unit step, and (3) complex expo-
nential sequences. Unit sample sequence is the finite se-
quence which has only one nonzero element at the index
n ⫽ 0,

1 n=0
δ[n] = (1)
0 otherwise
It plays the same role in the digital signal processing as the
unit impulse (delta function) plays in continuous-time signal
processing so that the characteristic of a discrete system can
be represented as the response to the unit sample sequence.
Any discrete signal can be presented as the sum of scaled
delayed unit sample sequences,
∞ pending on transformation a discrete-time system may have
x[n] = x[k] δ[n − k] (2)
k=−∞
Unit step sequence u[n] is the right-sided sequence which is
used to denote the start of any right-sided sequence and is
defined as

1 for n ≥ 0
u[n] = (3)
0 otherwise
Therefore, any sequence x[n], which is zero for n ⬍ N1, can be
written as
 the properties of the time-invariant system do not change the
x[n] n ≥ N1
x[n]u[n − N1 ] = (4)
0 otherwise
A complex exponential sequence is defined as
e jnω = cos(nω) + j sin(nω) (5)
By analogy with the continuous-time case, the quantity 웆 is
called frequency, and has a dimension in radians. We recall
that the frequency for the continuous signal has the dimen-
sion radians/sec. For this difference, several notations for the
frequency of the discrete signals and the continuous signals
are being used. The former is usually denoted as 웆 and the
latter as ⍀. Let the time axis t is divided into intervals
of the length T: t ⫽ nT. The axes of the discrete time signals
can be understood as obtained from the axis t by dividing
with T: n ⫽ t/T. Because the frequency and the time are in-
verse of each other, dividing in the time domain corresponds
to multiplying in the frequency domain. Therefore, the rela-
tion between continuous and discrete frequency is the
following:
ω = T (6)
Due to the different units of those two values, there are some
important distinctions between them. Continuous frequency
has the values ⫺앝 ⬍ ⍀ ⬍ 앝, and 웆 has only values from
0 to 2앟. All other values are repeated with the period 2앟.
Usually, the discrete frequencies are represented in the inter-
val
−π ≤ ω ≤ π (7)
As 웆 increases from 0 to 앟, oscillations become higher and
have a maximum at 웆 ⫽ 앟, and going from 앟 to 2앟, they be-
come slower. Therefore, 웆 ⫽ 앟 is the highest frequency, and
웆 ⫽ 0 and 웆 ⫽ 2앟 are the lowest frequencies. Figure 1 shows
how the sequence oscillates more rapidly with the increase of
the frequency from 0 to 앟 and more slowly with the increase
of the frequency from 앟 to 2앟.
A discrete-time system (or discrete system) is defined as
the transformation that maps an input sequence x[n] into an
output sequence y[n]:
y[n] = T{x[n]} (8)
where T兵 其 presents transformations, or the set of rules for
obtaining the output sequence from the given input one. De-
different properties. The most common properties are (1) lin-
earity, (2) time-invariance, (3) stability, (4) memoryless, and
(5) invertibilty. The system is linear if the response to a
scaled sum of the input sequences is equal to the sum of the
responses to each of the scaled input:
 
N
N
T ai xi [n] = a1 T{xi [n]} (9)
i=1 i=1
This relation is also known as the superposition principle.
The system is time-invariant if the shift of the input sequence
causes the same shift of the output sequence. In other words,
time:
T{x[n − n0 ]} = y[n − n0 ] (10)
The systems that are in the same time linear and time-invari-
ant are called linear time-invariant systems (LTI). The sys-
tem is causal if the values of the output sequence at any in-
dex n0 depend only on the values of the input sequence at
indexes n ⱕ n0. In other words, in a causal system the output
 DISCRETE TIME FILTERS 633

x[n] x[n]
ω = 0; ω = 2 π ω = π /4; ω = 7π /4

ω ω

Figure 1. The interpretation of high and low fre-

quencies for a dicrete-time sinusoisal signal. As 웆
x[n] x[n] increases from zero toward 앟 the sequence oscillates
ω = 3 π /4; ω = 5 π /4 ω =π
more and more rapidly and as 웆 increases from 앟
toward 2앟, the sequence oscillates more and more
slowly. Therefore the values of 웆 in the neighbor-
hood of 웆 ⫽ 0 are low frequencies (slow oscillations),
and those in the vicinity of 웆 ⫽ 앟 are high frequen-
ω ω cies (rapid oscillations). Due to the periodicity in
general the low frequencies are those in the vicinity
of 웆 ⫽ 2앟k, k ⫽ 0, 1, 2, . . . , and the high frequen-
cies are those in the vicinity of 웆 ⫽ 앟 ⫹ 2앟k, k ⫽ 0,
1, 2, . . . .

does not precede the input (i.e., it is not possible to get an output to any other input sequence may be related with the
output before an input is applied to the system). Noncausal unit sample response. In order to answer we use relation (2),
systems occur only in theory, and do not exist in this uni- and we obtain
verse. A causal system can be designed by introducing corre-  
sponding amounts of delay. The system is stable if a limited
∞

input always gives a limited output. If for a limited input, the y[n] = T{x[n]} = T x[k] δ[n − k] (13)
k=−∞
output is unlimited, the system is not stable. Therefore, the
output of an unstable system is infinite with nondecaying val-
ues. The system is memoryless if the output y[n] depends only If the system is linear, the superposition principle (9) can be
on the input at the same value n. The system is invertible if used, and therefore, the Eq. (13) can be written as
the input sequence may be uniquely determined by observing

∞
∞
the output. y[n] = T{x[k] δ[n − k]} = x[k]T{δ[n − k]} (14)
k=−∞ k=−∞
Time-Domain Description
From here, we obtain the relation for the linear system:
There are two main ways to describe discrete systems in the
time domain. The first one considers only the relation be-
∞
tween the input and the output of the system and is generally y[n] = x[k]hk [n] (15)
named the input-output analysis. The second one, besides the k=−∞
relation of the input and the output gives also an internal
description of the system, and it is named as a state-space where hk[n] depends on both k and n:
analysis. Both descriptions are useful in practice and are used
depending on the problem under the consideration (see Ref. hk [n] = T{δ[n − k]} (16)
7). A convenient way to present the behavior of the discrete
system is to put the unit sample sequence at the input. If the This relation is called the convolutional relationship. This
system is relaxed initially, equation can be simplified for the time-invariant system, us-
ing Eq. (10),
y[0] = 0 (11)

∞

the output y[n] would be the only characteristic of the system, y[n] = x[k]h[n − k] (17)
k=−∞
and it is called unit sample response or shortly impulse re-
sponse, and is denoted as h[n]:
This relation is called the convolution sum or convolution. It
h[n] = T{δ[n]} (12) completely describes the output of an LTI system for the
known input and for zero initial conditions. The operation
A discrete system which has the finite impulse response is convolution between sequences has its own signs *. Therefore,
called a finite impulse response (FIR) filter, and one with the the convolution (17) can be written as
infinite impulse response is known as an infinite impulse re-
sponse filter (IIR). The question which arises is whether the y[n] = x[n] ∗ h[n] (18)
634 DISCRETE TIME FILTERS
This operation is commutative and distributive [see Kuc (1)
for detailed analysis]. Proakis and Manolakis (7) explain the
computing of the convolution step by step. From the unit sam-
ple response, we may see some important characteristics of
the LTI system, such are stability and causality [see Orfan-
idis (8) for detailed analysis]. An LTI system is stable if and
only if this condition is satisfied:
∞
S= |h[n]| < ∞
n=−∞
FIR filter has a finite length of impulse response, and the
condition (19) shall always be satisfied, which means that an
FIR filter is always stable. An LTI system is causal if the next
condition is satisfied:
h[n] = 0, for n < 0
A natural question which may arise is if we can implement
digital filter by using the convolution. The answer depends on
whether the system is FIR or IIR. In the case of an FIR, the
convolution summation directly suggests how to implement
the filter. The problem arises for an IIR filter which has an
infinite impulse response since it requires an infinite number
of memory locations, additions, and multiplications. The solu-
tion is given by introducing the difference equations. Such a
difference equation describes an LTI system having any ini-
tial conditions unlike the discrete convolution that describes
the system in which all inputs and output are initially zero
(the system is initially relaxed). The difference equation is
often written in the form
Np
N
y[n] = bk x[n − k] − ak y[n − k]
k=−Nf k=1
where bk and ak are constant coefficients and Nf and Np are
integer values. The first summation contains past, present,
and future inputs, while the second one contains only past
outputs. The difference equation for FIR filter contains only
the first sum where we can recognize the convolution (17). If
the system is casual, it does not depend on the future values
of the input, and the difference equation has Nf ⫽ 0. The part
of the right side of the difference equation which involves past
outputs is called the recoursive part, and the other part is the
nonrecoursive one. The system which has only a nonrecour-
sive part is called the nonrecoursive filter. Otherwise, it is the
recoursive filter. In general, the computation of the output
y[n] at the index n of a recoursive filter needs previous out-
puts: y[n ⫺ 1], y[n ⫺ 2], . . ., y[0]. Therefore in this case, the
output must be computed in an order. As the difference, the
output of the nonrecoursive filter can be computed in any or-
der. An implementation of the casual LTI filter based on the
difference equation (21) and which is called direct form I is
presented in the Fig. 2. We see that the filter consists of an
interconnection of three basic elements: (1) unit delay, (2)
multiplier, and (3) adder. Direct form I is not optimal in the
sense that it uses a minimum number of delaying elements.
Proakis and Manolakis (7) describe different and more effi-
cient structures of discrete systems. Signal-flow graphs are
often used to describe the time-domain behavior of LTI sys-
tems [see Haykin (9) for a detailed analysis].
b0
x[n] Σ Σ y[n]
z–1 z–1
b1 –a1
(19)
z–1 z–1
bNp –aN
Figure 2. Direct form I realization of the causal LTI filter follows
directly from the difference equation and shows explicitly the delayed
values of input and output. (z⫺1 is interpreted as one-sample delay.)
(20)
A state-space approach considers that the output of the
system is the result of the actual input and the set of initial
conditions. This suggests that the system may be divided into
two parts. One part contains memory and describes past his-
tory, and the second one describes the answer to the actual
input. Following this approach, Antoniou (10) derived the
state space equations for the system of an order N in the ma-
trix-vector form
q[n + 1] = Aq[n] + Bx[n] (22)
y[n] = Cq[n] + Dx[n] (23)
where q[n] is the n-dimensional state vector at time n, and
x[n] and y[n] are the input and output sequences, respec-
(21) tively. The matrices A, B, C, and D, correspond to a particu-
lar realization of the filter.
Transform Domain Description
Frequency Domain. The sinusoidal sequences are usually
used in frequency-domain description of discrete signals and
systems because sinusoidal sequences have one useful charac-
teristic which is shown in Eq. (24):
y[n] = H(e jω )e jωn (24)
Therefore, if the sinusoidal sequence is applied to the LTI sys-
tem, the output is also a sinusoidal sequence with the same
frequency, multiplied with the complex value:
∞
H(e jω ) = h[k]e− jωk (25)
K =−∞
The sum in Eq. (25) presents Fourier transform of h[n] and is
named as frequency response, as it specifies response of the
system in the frequency domain. The frequency response, be-
ing the Fourier transform of the unit sample response, is a
periodic function with the period 2앟. Therefore, ‘‘low frequen-
cies’’ are those that are in the neighborhood of an even multi-
ple of 앟, and the ‘‘high frequencies’’ are those that are close to
an odd multiple of 앟. Equation (24) has also an interpretation
using the eigenvalue and eigenfunction. If an input signal
produces the same output signal but multiplied by a constant,

this signal is called eigenfunction, and the constant is the ei-
genvalue of the system. Therefore, the complex sinusoidal se-
quence is the eigenfunction, and H(ej웆w) is the corresponding
eigenvalue. Fourier transform of the unit sample response
h[n] exists only if the sum [Eq. (25)] converges, that is if the
next condition is satisfied:
∞
|h[n]| < ∞
k=−∞
The magnitude of H(ej웆), 兩 H(ej웆)兩, is called magnitude re-
sponse, and the argument of H(ej웆) is called phase response
and denoted as Arg兵H(ej웆)其. Therefore, we have
jω )}
H(e jω ) = |H(e jω )|e jArg{H (e
Frequency response can be expressed by its real and imagi-
nary part:
H(e jω ) = HR (e jω ) + jHI (e jω )
From here, the magnitude response and phase response can
be expressed as follows:
p

|H(e )| =
jω
HR2 + HI2 = H(e H (e )
jω
where H*(ej웆) is the complex-conjugate of H(ej웆).
 
HI (e jω )
Arg{H(e jω )} = arctg
HR (e jω )
Instead, the linear scale, magnitude characteristic is usually
plotted on the logarithmic scale.
|H(e jω )|db = 10 log10 |H(e jω )|2 = 20 log10 |H(e jω )|
In order to show better both the passband and the stop-
band characteristics, the log-magnitude response is plotted on
two different scales: one for the passband and the second one
for the stopband. For an LTI system with a real impulse re-
sponse, the magnitude and phase responses have symmetry
properties from which follows that the magnitude response is
an even function of 웆, and the phase response is an odd func-
tion of 웆.
Oppenheim and Schafer (3) show that the Fourier trans-
form of the output is the product of the Fourier transforms of
the input and the impulse response:
Y (e jω ) = H(e jω )X (e jω )
This expression explains why Fourier transform is so useful
in the analysis of LTI. As this expression shows, the operation
of convolution is replaced by a simpler operation of multiplica-
tion in the transform domain. This equation also shows that
the input spectrum is changed by the LTI system in both am-
plitude and the phase. The output magnitude is obtained as
the product of the input magnitude spectrum and the magni-
tude response:
|Y (e jω )| = |H(e jω )| |X (e jω )|
DISCRETE TIME FILTERS 635
The output phase is equal to the sum of the input phase and
the phase response:
Arg{Y (e jω )} = Arg{X (e jω )} + Arg{H(e jω )} (34)
Those changes can be either desirable or undesirable when
they are referred as to the magnitude and phase distortion.
(26) Generally, we may view the LTI as a filter, passing some of
the frequencies of the input signal and suppressing the oth-
ers. Filters are usually classified according to what frequen-
cies pass and to what frequencies suppress as: (1) lowpass, (2)
highpass, (3) bandpass, and (4) bandstop filters. The ideal fil-
ters have constant magnitude response (usually 1) in the
passband and zero magnitude characteristic in the stopband.
The magnitude characteristics of the different ideal filters are
(27)
shown in Fig. 3. Ideal filters have the linear phase in the
passband which means that the output is equal to the scaled
and delayed input. Therefore, linear phase causes only de-
laying of the input sequence, what is not considered as the
distortion and the linearity of the phase is the desirable char-
(28)
acteristic. The group delay is introduced as the measure of
the linearity of the phase
d[Arg{H(e jω )}]
∗
τ (ω) = −
dω
(35)
jω
(29)
The group delay can be interpreted as the time delay of the
signal components of the frequency 웆, introduced by the filter.
Filters with symmetric impulse response have linear phase
[see Oppenheim and Schafer (3) for detailed analysis]. Ideal
(30)
filters are not physically realizable and serve as the mathe-
matical approximations of physically realizable filters. As an
example, we consider in Fig. 4 the magnitude characteristic
of the physically realizable lowpass filter [see Ingle and Pro-
akis (11) for a detailed analysis].
(31)
Z-Domain. Z transform is a generalization of the Fourier
transform that allows us to use transform techniques for sig-
nals not having Fourier transform. It plays the same role in
discrete-time signals and systems as the Laplace transform
does in continuous-time signals and systems. Z transform of
the unit sample sequence is called system function:
∞
H(z) = Z{h[n]} = h[n]z−n (36)
n=−∞
The concept of a Z transform is only useful for such values
of z for which the sum [Eq. (36)] is finite. Therefore, for the
sequence h[n] it is necessary to define the set of z values for
(32) which
∞
|h[n]z−n | < ∞ (37)
n=−∞
This set of z values is called the region of convergency (ROC).
Many characteristics of a filter can be seen from ROC. For a
FIR filter, the number of elements in the sum [Eq. (36)] is
finite and, therefore, the problem of the existence of the Z
transform does not exist, and the ROC is all z-plane, except
the origin. Proakis and Manolakis (7) show that ROC for the
(33) right-sided sequence is given by 兩z兩 ⬎ R1, for the left-sided is
636 DISCRETE TIME FILTERS

H(e jω ) H(e jω )
Passband Passband

Stopband Stopband

ω ω
0 ωc π 0 ωc π
Low-pass filter High-pass filter

H(e jω ) H(e jω )
Passband Passband Passband

Figure 3. Magnitude characteristics of the differ-

Stopband Stopband Stopband
ent ideal frequency-selective filters. The ideal filters
pass without any attenuation all frequencies in the ω ω
0 ω1 ω2 π 0 ω3 ω4 π
passband and completely attenuate all frequencies
in the stopband. Bandpass filter Bandstop filter

given as 兩z兩 ⬍ R2, and for the two-sided sequence as R1 ⬍ Remember that Eq. (38) is valid for LTI systems. The system
兩z兩 ⬍ R2. function for an important class of LTI systems which are de-
The operation of convolution in the time-domain reduces scribed by the constant coefficients difference equation can be
to the most simple operation of multiplication in the expressed as the rational function and is expressed as the
Z-domain: ratio of polynomials in z⫺1. By taking the Z transform of Eq.
(21) and using that the delay by k samples in the time-domain
Y (z) = Z{y[n]} = Z{x[n] ∗ h[n]} = X (z)H(z) (38) corresponds to the multiplication by z⫺k, we have:
N p
where
Y (z) b z−k
k=Nf k
H(z) = = N (40)
X (z) = Z{x[n]} X (z) 1 + k=1 ak z−k
(39)
Y (z) = Z{y[n]}
[see Proakis and Manolakis (7) for detailed analysis]. The val-
ues of z for which H(z) become zero are called zeros, and the
values of z for which H(z) become infinity are called poles.
H(e jω ) The zeros are roots of the numerator N(z), and the poles are
roots of the denominators D(z). Both poles and zeros are
Passband named as the singularities of H(z). The plot of zeros and poles
1+ δ 1 in the z-plane is called a pole-zero pattern. Pole is usually
1 denoted by a cross ⫻ and the zero by a circle . We can write
the system function H(z) in the factoring form:
1+ δ 1
Np +N
f (1 − zk z−1 )
H(z) = KzNf k=1
N
(41)
k=1 (1 − pk z−1 )
Transition
band Stopband where zk and pk are the zeros and the poles, respectively, and
δ2 K is gain. Kuc (1) shows that each factor in the numerator of
Eq. (41) generates one zero at z ⫽ zk and one pole at z ⫽ 0;
ω each factor in the denominator generates one pole at z ⫽ pk
ωp ωs π
and one zero at z ⫽ 0; factor zNf generates Nf zeros at z ⫽ 0
and Nf poles at z ⫽ 앝. For the system function, the total num-
Figure 4. Magnitude specification of the physically realizable low-
pass filter. Instead of sharp transition between passband and stop- ber of poles is equal to the total number of zeros. If pole and
band, the transition band is introduced, and instead of a flat charac- zero are in the same location, they cancel each other. Complex
teristic, a small amount of ripples is tolerable: In the passband: 1 ⫺ singularities are always in the complex-conjugate pairs for
웃1 ⬍ 兩H(ej웆)兩 ⬍ 1 ⫹ 웃1, where 웃1 is the passband ripple. In the stop- the system presented by the difference equations with the
band: 兩H(ej웆)兩 ⬍ 웃2, where 웃2 is the stopband ripple. real coefficients.
 DISCRETE TIME FILTERS 637

Pole-zero pattern gives much useful information about the Ingle and Proakis (11) derive geometrical presentation of the
LTI system. From the pole–zero pattern, we can see whether phase response as
the filter is casual or not. For the casual filter, Nf ⫽ 0 and
Np +Nf
therefore there are no poles in the infinity. Besides causality,
the type of the filter can also be seen from the pole–zero pat- arg{H(e jω 0 )} = C + ((Np + Nf ) − N)ω0 + arg{(zk , z0 )}
tern. For an FIR filter, all singularities are only zeros (except k=1

poles at the origin and possibly in the infinity). Unlike a FIR

N (44)
filter, an IIR filter has zeros and poles or only poles. (Zeros − arg{(pk , z0 )}
k=1
are in the origin.) As the system function becomes infinity in
the poles, all poles must be outside the ROC. However, for
where C is equal 0 or 앟, depending if the real frequency re-
a casual right-sided sequence, ROC must be outside of the
sponse is negative or not. This expression can be interpreted
outermost pole (the pole having the largest absolute value).
as the sum of the constant linear with 웆 term and the nonlin-
Another useful characteristic about LTI which can be seen
ear term. We notice that the singularities in the origin do not
from the pole–zero pattern is the stability. The problem of
affect the magnitude response but affect the phase response.
stability is only addressed to the IIRs and, therefore, is con-
As shown in Eq. (43), the magnitude response will be equal
nected only with the position of poles. Kuc (1) shows that for
to zero at the points corresponding to the zeros on the unit
a causal IIR filter, all poles must be inside the unit circle. If
circle. Similarly, the poles that are close to the unit circle (re-
the pole is on the unit circle, the system is not stable.
membering that these cannot be on the unit circle for a stable
Oppenheim and Shafer (3) shows that Z transform is equal
LTI) give the peak value to the magnitude response. There-
to the Fourier transform on the unit circle:
fore, the singularities that are close to the unit circle domi-
nate the magnitude response, and they are called the domi-
H(e jω ) = H(z) z=e jω (42) nant singularities.

In this order, the frequency response belongs to the system

s-PLANE TO z-PLANE TRANSFORM
function evaluated on the unit circle. The magnitude response
at 웆 ⫽ 웆0 can be presented geometrically as the ratio of the
The s-plane to z-plane transform depends on the characteris-
distances between the zeros and the point z0 ⫽ ej웆0 on the unit
tic of the filter we want to preserve in the process of trans-
circle and the distances between poles and the point z0 ⫽ ej웆0,
forming an analog to a digital filter. The most used trans-
as it is shown in Fig. 5:
forms are impulse invariance transformation, where the
Np +N impulse response is preserved, and bilinear transform, where
f |(zk , z0 )| the system function is preserved.
|H(e jω 0 )| = K k=1
N
(43)
k=1 |(pk , z0 )|
Impulse Invariance Transformation
The unit sample response of a digital filter is obtained by
sampling the impulse response of the analog filter:
Im Z-plane
h[n] = hA (nT ) (45)
Unit circle
pk
e jω o = zo where T is the sampling interval. Using Eq. (6) between the
discrete and analog frequency, knowing that the frequency
points in s-plane are
ωo
Re s = jωT (46)
zk
and that those in the z-plane are

z = e jω (47)

we obtain the relation:

Figure 5. Geometric presentation of the Fourier transform in Z- z = esT (48)

plane along the unit circle. The magnitude response at 웆 ⫽ 웆0 can be
presented geometrically as the ratio of the distances between the From Eqs. (46)–(48), it follows that the part of the frequency
zeros zk and the point z0 ⫽ ej웆0 on the unit circle and the distances axis in the s-plane from 0 to 앟/T is mapped to the frequency
between poles pk and the point z0 ⫽ ej웆0. If the singularity is close to points on the unit circle from 웆 ⫽ 0 to 앟 in the z-plane. In a
the unit circle it is called dominant singularity, because the distances similar way, the frequency points from 0 to ⫺앟/T are mapped
from it to the neighborhood points on the unit circle are very small.
to the points on the unit circle from 웆 ⫽ 0 to ⫺앟. Expressing
Therefore the dominant zero decreases and the dominant pole in-
creases the magnitude characteristic at the corresponding frequency.
the complex value z in the polar form
For every dominant zero on the unit circle, the magnitude character-
istic is equal to the zero at the corresponding frequency. z = re jω (49)
638 DISCRETE TIME FILTERS

and the complex variable s, with real value ␴ and imaginary Rf Cf

value ⍀
Ri Ci
ν in – ν in –
s = σ + j (50) νo νo
+ +
we have the relation between r and the real value ␴
(a) (b)
r = eσ T (51)
Figure 6. Continuous-time amplifiers: (a) resistor based and (b) ca-
We have the next observations: (1) the transform from contin- pacitor based. The small signal voltage gain for the resistor and the
capacitor based amplifiers is ⫺Rf /Ri and ⫺Ci /Cf, respectively.
uous-time domain to the discrete-time domain is linear, (2)
the mapping is not one-to-one, but many-to-one and (3) the
frequency interval 0 to 2앟/T maps into the unit circle, and the
rely on the precision of the absolute value of both resistors
strips in the left side of the s plane of width 2앟/T are mapped
and capacitors. In integrated circuits, the tolerances of RC
inside the unit circle. The entire left side of the s-plane maps
products can be as high as ⫾30%. In the past, to overcome
into the unit circle, which means that the stable analog filter
this drawback, the resistors were adjusted by using laser
will result in a stable digital one. Due to the many-to-one
trimming techniques; this approach, however, increases the
mapping, the aliasing effect is present, and this is the main
cost of the system. In order to increase the precision of the
disadvantage of the impulse invariance transform.
filters, several techniques have been aroused; the main idea
is to replace the resistor by another device like a switched-
Bilinear Transform
capacitor or a switched-current. Switched-capacitor tech-
To overcome the aliasing limitation, the bilinear transform niques are discussed in this chapter.
could be used, as it presents a one-to-one mapping. The sys-
tem function H(z) is obtained from HA(s) by replacing the s by Basic Components of Continuous-Time Filters

2 z−1 Resistors, capacitors, and inductors are the main passive ele-
s= (52) ments of continuous-time filters. The operational amplifiers
T z+1
are other important elements for the implementation of ac-
tive RC filters. For the resistor, the voltage to current rela-
To find the mapping of the frequencies from ⍀ to 웆, we set
tionship is given by
s ⫽ j⍀ and use Eqs. (49) and (52)
1
1 + jT/2 1 + (t/2)2 e jarctg(T /2) i= v (56)
z=e jω
= = R
1 − jT/2 1 + (T/2) e− jarctg(T /2) (53)
= e2 jarctg(T /2) For the inductor, this relationship is

From here follows 1

i= v (57)
sL
ω = 2arctg(T/2) (54)
where s is the frequency variable j⍀. For the capacitor, the
For low frequencies, the transform is approximately linear, voltage-current relationship is given by
and for higher frequencies, the transform is highly nonlinear,
1
and frequency compression or frequency warping occurs. The v= i (58)
effect of the frequency warping can be compensated for by sC
prescaling or prewarping the analog filter before transform,
In the design of complex transfer functions, a basic function
which means to scale the analog frequency as follows:
is the voltage amplification; two structures are depicted in
2


T
 Fig. 6. The inband gain of the amplifiers is given by ⫺Rf /Ri
 = tg (55) and ⫺Ci /Cf , respectively. While the resistor based amplifier is
T 2
stable, the circuit of Fig. 6(b) is quite sensitive to offset volt-
[See Kuc (1) for a detailed analysis.] The whole left side of the ages due to the lack of dc feedback. Active filters are based
s-plane is mapped into the inside of the unit circle, and the on lossless integrators; the typical RC implementation of this
right side is mapped outside of the unit circle. Therefore, the block is shown in Fig. 7.
stable analog filter will result in the stable digital filter [see
Proakis and Manolakis (7) for detailed analysis].
Cf

DISCRETE-TIME ANALOG FILTERS Ri

ν in –
νo
+
During the 1960s and 1970s the analog integrated filters were
implemented by circuits based on resistors, capacitors, and
operational amplifiers; these are denominated RC active fil- Figure 7. Continuous-time integrator. Note that the operational am-
ters. The precision of RC filters depend on RC products which plifier operates in open loop for dc signals.
 DISCRETE TIME FILTERS 639

φ1 C φ1 φ1 C φ2 connected to a low impedance voltage source, and the other

ν1 ν2 ν1 ν2 one is connected to the input of an operational amplifier a
φ2 φ1 virtual ground. Hence, every clock period, in the case of the
φ2 φ2
inverting switched-capacitor resistor, the capacitor extract
charge equal to ⫺C(v1 ⫺ v2) or the charge C(v1 ⫺ v2) is injected
(a) (b) in the case of the non-inverting resistor. In average, the
Figure 8. Switched-capacitor resistors: (a) series and (b) parallel.
switched-capacitor simulated resistors are transferring
␾1 and ␾2 are two nonoverlapping clock phases. charges proportional to the clock period leading to the follow-
ing equivalent resistance

If the voltage gain of the operational amplifier, AV, is large
enough, the voltage at the inverting input, given by v0 /AV, is
very small, and this terminal can be considered as a virtual
ground; hence, the current flowing through the resistor is de-
termined by the value of both resistor and input voltage.
Since the input impedance of the operational amplifier is typi-
cally very large, the resistor current is injected to the capaci-
tor, and the output voltage becomes
 t
1
vo (t) = vo (t0 ) −
RiCf t0
The minus sign appears because the current is injected from
the virtual ground to the output node. As we are interested
in transfer functions, it is easier to manipulate the variables
in the frequency domain; therefore, the previous equation can
be expressed as follows
vo 1
=−
vi sRiCf
The differentiator can be implemented by using inductors in-
stead of capacitors or exchanging the role of the resistor and
capacitor in Fig. 7. Nevertheless, these approaches are im-
practical in most of the cases; the inductors are typically im-
plemented by using integrators as will be shown in the next
section. More details can be found in Refs. 12–15.
Building Blocks for Switched-Capacitor Filters
Herein after, it is assumed that the non-overlapping clock
phases are defined as follows:
1
Req ∼
= (62)
f ckC
where f ck is the frequency of the clock. Switched-capacitor
based resistors are the key elements for the design of
switched-capacitor filters; with these elements, voltage ampli-
fiers, integrators, resonators, filters, and other type of func-
tions can be implemented; more applications can be found in
Refs. 13, 15, 19–20. The simplest voltage amplifier is the cir-
cuit of Fig. 6(b); other voltage amplifiers are shown in Fig. 9.
vi (t) dt (59) Observe that Cf and Ci are sharing several switches. In Fig.
9(a), during the clock phase ␾2, the operational amplifier is
shortcircuited, and the capacitors are discharged. During the
next clock period, the input capacitor is charged to Ci vin, and
the current needed for this charge flows through the feedback
capacitor; therefore, the gain voltage becomes
vo C
=− i (63)
vin Cf
(60)
Note that the amplifier is available during clock phase ␾1. The
amplifier shown in Fig. 9(b) behaves as the previous one, but
the input signal is sampled at the end of the clock phase ␾2,
and the charge is injected during the next clock period. Ob-
serve that the injected charge is inverted; hence, the voltage
gain is
vo C
= i z−1/2 (64)
vin Cf
where: z⫺1/2 represents the half delay. Other voltage amplifi-
ers can be found in Refs. 13–15, 19–20.

φ1 (t) ⇒ nT − T/2 < t ≤ nT Switched-Capacitor Integrators

(61)
φ2 (t) ⇒ nT − T < t ≤ nT − T/2
In switched-capacitor circuits, the resistors are implemented
by a capacitor, four switches and two non-overlapping clock
frequencies; Fig. 8 shows the stray insensitive switched-ca-
pacitor simulated resistors. Typically, one of the terminals is
The parasitics-insensitive integrators allow the design of
high-performance analog integrated circuits. Biquadratic
based filters, ladder filters, and other type of filters are based
on active integrators. Switched-capacitor filters have the ad-
vantage that arranging the clock phases inverting and non-
inverting simulated resistors can be realized, as shown in Fig.

Cf φ1 Cf φ1

φ2 φ2

φ1 φ1 φ2 φ2 φ1 φ2
ν in – ν in – Figure 9. Switched-capacitor amplifiers available
νo νo
φ2 φ2 + φ1 φ2 + during clock phase ␾1 (a) inverting and (b) nonin-
verting. Because the operational amplifier is short-
circuited during ␾2, the output is available only dur-
(a) (b) ing the clock phase ␾1.
640 DISCRETE TIME FILTERS

Cf Cf

φ1 Ci φ1 φ2 Ci φ1
ν in – ν in –
Figure 10. Switched-capacitor integrators: (a) νo νo
inverting and (b) noninverting. The inverting φ2 φ2 + φ1 φ2 +
and noninverting integrators employ the series
and parallel switched-capacitor resistors, re-
spectively. (a) (b)

8. As a result of this, the design of systems can be further A similar analysis for the non-inverting integrator leads to
simplified. The inverting and non-inverting integrators shown the following transfer functions:
in Fig. 10 are an example of this advantage. For the imple- 
mentation of an RC noninverting integrator, an additional in- vo  C z−1/2
 = i (69)
verter is needed. vin φ Cf 1 − z−1
2
The inverting integrator operates as follows. During the 
clock phase ␾2, Ci is discharged while the output voltage re- vo  Ci z−1
= (70)
mains constant due to Cf ; the output voltage is then charac- vin φ Cf 1 − z−1
2
terized by the next equation

vo (t) = vo (nT − T ) (65) First-Order Filters

The amplifiers and integrators can be easily implemented by
In the next clock period, Ci extracts a charge equal to Ci vin; using switched-capacitor circuits; a general first order filter is
therefore, the charge distribution can be described by the fol- shown in Fig. 11. By using adequate equations, we can see
lowing expression that the z-domain output-input relationship is described, dur-
ing the clock phase ␾1, by the following expression:
Cf vo (t) = Cf vo (nT − T/2) − Ci vin (t) (66)
(1 − z−1 )Cf vo = −(1 − z−1 )Ci1 vin − Ci2 vin + z−1/2Ci3 vin − Cf 2 vo
If the output voltage is evaluated at the end of the clock
(71)
phase ␾1, and considering that v0(nT ⫺ T/2) is equal to
v0(nT ⫺ T), the z-domain transfer function will result in where the left hand side term represents the charge contribu-
 tion of Cf . The first right hand side term is due to capacitor
vo  C 1
=− i (67) Ci1. Note the term 1 ⫺ z⫺1 present in the non-switched capaci-
vin φ Cf 1 − z−1 tors; these terms appear as the injected or extracted charge
1
is the difference between the actual one minus the previous
Note that the output voltage can be sampled during the next clock period charge. The other terms represent the charge
clock period; then the output voltage is delayed by a half pe- contribution of the Ci2, Ci3, and Cf2, respectively. In order to
riod, leading to the following transfer function facilitate the analysis of complex circuits, it is convenient to
represent the topologies with the help of flow diagrams; see,

vo  C z−1/2 for example, Ref. 20. Note that the output voltage is feedback
 =− i (68) by the capacitor Cf2; this capacitor is considered in a similar
vin φ Cf 1 − z−1
2 way as the other capacitors. Solving the circuit, or equiva-
lently, arranging Eq. (71), the z-domain transfer function can
be found as
φ2 Ci3 Cf2 φ1 
v0  −(1 − z−1 )Ci1 − Ci2 + z−1/2Ci3
 =
Cf
 (72)
vin φ
φ1 φ2 1 (Cf + Cf2 ) 1 − z−1
Cf + Cf2
Cf
If the output voltage is sampled during ␾2 and assuming that
φ1 Ci2 φ1 vin changes neither during the transition ␾1 ⫺ ␾2 nor during
ν in – the clock phase ␾2, we can observe that the output of the first
νo order circuit becomes
φ2 φ2 +

v0 |φ = z−1/2v0 |φ (73)
2 1
Ci1

In the first-order filter of Fig. 11, we can note that all

Figure 11. General first-order switched-capacitor filter. Ci1, Ci2, and switches connected to the inverting input of the operational
Ci3 implement an amplifier, an inverting integrator, and a nonin- amplifier have been shared by several capacitors as all of
verting integrator, respectively. Cf2 implements a switched-capacitor them are connected to ground during ␾2 and to the opera-
resistor in parallel with C. tional amplifier during clock phase ␾1.
 DISCRETE TIME FILTERS 641

φ1 CR φ1
–
νo νo
φ2 φ2 +

C
L C

φ2 CR φ1
–
Figure 12. LC resonator: (a) passive and (b)
+ φ1 φ2 switched-capacitor implementation. The inductor
L is simulated by the switched-capacitor resistors,
the bottom operational amplifier and the bottom
(a) (b) capacitor C.

Active Resonator to component tolerances in the passband; see Refs. 14–17. A

general biquadratic filter is shown in Fig. 13. The z-domain
Ladder filters are based on LC networks, series and parallel
transfer function of the topology is given by
connected. While the capacitors are easily implemented in
metal-oxide-semiconductor technologies, the inductor must be A2 A5 z + (z − 1)(A1 A5 + A4 z) + A3 (z − 1)2
simulated by integrators and resistors. The inductor’s cur- H(z) = − 
2 − A (A + A ) + A  1 − A A 
rent-voltage relationship is given by Eq. (57). For a grounded (1 + A8 ) z2 − 5 6 7 8
z+ 5 6
1 + A8 1 + A8
resonator as shown in Fig. 12(a), the conductor’s current can
be generated from the output node and an integrator. The (76)
transfer function of an RC integrator is given by ⫺1/sRC; if
an integrator’s output is converted to current by a resistor, By using this structure, several transfer functions could be
and the resulting current is fed back to the node v0, the re- implemented, namely
sulting current is then given by vo /sR2C. Hence, the simulated
A1 = A3 = A4 = 0 Low-pass filter (LDI)
inductance results in
4A2 A5 = A3 , A1 = A4 = 0 Low-pass filter (Bilinear)
L = R 2C (74) A2 = A3 = A4 = 0 or
A1 = A3 = A4 = 0 Bandpass filter (LDI)
Figure 12(b) shows the switched-capacitor realization of the A2 = A3 = 0, A1 A5 = A4 Bandpass filter (Bilinear)
resonator. For a high sampling rate ( f ck Ⰷ frequency of opera-
A1 = A2 = A4 = 0 High-pass filter
tion), the switched-capacitor resistors can be approximated by
R ⫽ 1/f ckCR; for details, the reader may refer to Refs. 12–15,
In order to illustrate the design procedure, consider a second
19–20. According to Eq. (74), the simulated inductance is ap-
order bandpass filter with the following specifications:
proximately given by

1 C Center frequency 10 kHz

L= 2 C2
(75) Bandwidth 1 kHz
f ck R Clock frequency 60 kHz

Observe that in the LC implementation, similar integrators

have been used.
A7C2

HIGH-ORDER FILTERS A4C2

High-order filters can be synthesized by using several ap- φ1 A2C1 φ1 A3C2 φ1

A6C1
proaches; two of the most common are based on biquads and
the emulation of ladder filters. High-order filters based on bi- φ2 φ2 C1 φ2
C2
quadratic sections are more versatile, but ladder filters pres-
ν in φ 2 A5C2 φ 1
ent low sensitivity to components’ tolerances in the passband. – –
A1C1 + νo
φ1 φ2 +
Second-order Filters
Second order filters are often used for the implementation of A3C2
high-order filters; these filters are versatile in the sense that
the filter parameters like center frequency, bandwidth, and Figure 13. General second-order switched-capacitor filter. By choos-
dc or peak gain are controlled independently. A drawback of ing appropriated coefficients either lowpass, bandpass, highpass, or
the biquadratic filters is that they present high sensitivity notch filters can be implemented.
642 DISCRETE TIME FILTERS

i1 i3 i1 i3
V2 ν2
ν in νo ν in νo
R1 L1 L2
C1 C1 Y1 Y3
L2 C2 R1 Z2 Z4

Figure 14. Passive sixth-order bandpass filter:

(a) detailed RLC prototype and (b) simplified sche-
(b)
matic. The element values can be obtained from
well-known tables; see, for example, Ref. 12. (a)

The continuous-time bandpass filter has the following age and current Kirchhoff ’s laws. Although this topic is
form: treated in another chapter, here we consider an example to
illustrate the design procedure of switched-capacitor ladder
BWs filters. Consider a third order, normalized, lowpass filter. For
H(s) = (77)
s2 + BWs + ω02 the design of a bandpass filter, the low-pass to bandpass
transformation must be used; this transformation has the
where 웆0 is the center frequency, equal to 2앟f 0, and BW the form
filter bandwidth. In low Q applications, it is more precise to
prewarp the center frequency and the ⫺3 dB frequencies; this sbp ω02
slp ⇒ + (79)
prewarping scheme is discussed in (18). By using the bilinear BW sbp BW
transform, the prewarped center frequency is f 0 ⫽ 11.0265
kHz, and the ⫺3 dB frequencies are mapped into 10.37 kHz where BW and 웆0 are the bandwidth and center frequency of
and 11.7 kHz. Applying the s-domain to z-domain bilinear the bandpass filter, respectively. Observe that the inductor is
transform to the continuous-time bandpass filter, the follow- mapped into a series of another inductor and a capacitor,
ing z-domain transfer function is obtained: while the capacitor is transformed into another capacitor in
parallel with an inductor. The bandpass filter prototype and
BWT a simplified schematic are shown in Figs. 14(a) and 14(b), re-
2 spectively. The transformed elements are then given by
H(z) =
BWT

ω T 2
1+ + 0
LLP
2 2 L1 =
(z − 1)(z + 1) BW

ω T 2 
ω T 2 BW
BWT C1 =
 −2 + 2
0
 1− + 0 LLP ω02
 2  2 2 (80)
z +
2
 BWT

ω T 2 
z+
BWT

ω T 2 L2 =
BW
1+ + 0
1+ + 0
CLP ω02
2 2 2 2
(78) CLP
C2 =
BW
Using the prewarped values and equating the transfer func-
tion of the bilinear bandpass filter, Eq. (72) with appropriated Current i1 could be generated by the active circuit of Fig. 15.
conditions, and the previous equation, the capacitor ratios are By using circuit analysis, i1 could as well be obtained as
found: A1 ⫽ A4 ⫽ 0.04965, A5 ⫽ 1, A6 ⫽ 0.09931, A7 ⫽ 0.95034,
A8 ⫽ 0. 1
i1 = (vin − v2 ) (81)
R2QY11
Ladder Filters
Equating i1 of the passive realization with the simulated cur-
Active ladder filters are based on the simulation of the pas-
rent, the relationship between Y1 and Y11 can be determined
sive components of low-sensitive passive prototypes. The ac-
tive implementation of this type of filters is based on the volt- 1 1
Y1 = = 2 (82)
Z1 RQY11

RQ Y11
νin Z22 This expression means that the impedance Z1 is simulated by
the admittance Y11 multiplied by the factor RQ2 . For the band-
i1
−ν 2 pass filter, Z1 is the series of a resistor, an inductor, and a
RQ capacitor; this impedance can be simulated by the parallel of
RQ
ν2
similar elements. For grounded resonators, the capacitors are
connected to the operational amplifier, and the inductors are
simulated by using integrators and resistors, as previously
Figure 15. Active implementation of floating impedances. The ad- discussed. In the implementation of the 6th order bandpass
mittance Y11 is directly associated with the floating impedance Z1. filter, three resonators are being employed, one for each LC
Resistors RQ are scaling factors. resonator.
 DISCRETE TIME SYSTEMS DESIGN METHODS 643

BIBLIOGRAPHY

1. R. Kuc, Introduction to Digital Signal Processing, New York:

McGraw-Hill, 1988.
2. C. B. Rorabaugh, Digital Designer’s Handbook, New York:
McGraw-Hill, 1993.
3. A. V. Oppenheim and R. W. Schafer, Discrete-Time Signal Pro-
cessing, Englewood Cliffs, NJ: Prentice-Hall, 1989.
4. M. Schwartz and L. Shaw, Signal Processing: Discrete Spectral
Analysis, Detection, and Estimation, New York: McGraw-Hill,
1975.
5. M. H. Hayes, Statistical Digital Signal Processing and Modeling,
New York: Wiley, 1996.
6. J. V. Candy, Signal Processing: The Modern Approach, New York:
McGraw-Hill, 1988.
7. J. G. Proakis and D. G. Manolakis, Digital Signal Processing,
Principles, Algorithms, and Applications, 2nd ed., New York: Mac-
millan, 1992.
8. S. J. Orfanidis, Introduction to Signal Processing, Englewood
Cliffs, NJ: Prentice-Hall, 1996.
9. S. Haykin, Modern Filters, 2nd ed., New York: McGraw-Hill,
1990.
10. A. Antoniou, Digital Filters Analysis and Design, New York:
McGraw-Hill, 1979.
11. V. K. Ingle and J. G. Proakis, Digital Signal Processing Using
MATLAB V.4, Boston: PWS Publishing, 1977.
12. L. P. Huelsman and P. E. Allen, Introduction to the Theory and
Design of Active Filters, New York: McGraw-Hill, 1980.
13. P. E. Allen and E. Sanchez-Sinencio, Switched-Capacitor Circuits,
New York: Van Nostrand, 1984.
14. R. Gregorian, K. Martin, and G. C. Temes, Switched-capacitor
circuit design, Proc. IEEE, 71 (8): 941–966, 1983.
15. R. Gregorian and G. C. Temes, Analog MOS Integrated Circuits
for Signal Processing, New York: Wiley, 1986.
16. K. Martin, Improved circuits for the realization of switched-ca-
pacitor filters, IEEE Trans. Circuits Syst., 27 (4): 237–244, 1980.
17. E. Sanchez-Sinencio, J. Silva-Martinez, and R. L. Geiger, Biquad-
ratic SC filters with small GB effects, IEEE Trans. Circuits Syst.,
32 (10): 876–884, 1984.
18. K. R. Laker and W. Sansen, Design of Analog Integrated Circuits
and Systems, New York: McGraw-Hill, 1994.
19. Wai-Kai Chen (Editor-in-Chief), The Circuits and Filters Hand-
book, Boca Raton, FL: CRC Press, 1995.
20. D. A. Johns and K. Martin, Analog Integrated Circuit Design, New
York: Wiley, 1997.

JOSE SILVA MARTINEZ

GORDANA JOVANOVIC-DOLECEK
Instituto Nacional de Astrofisica,
Optica y Electronica, INAOE

DISCRETE-TIME FILTERS. See DIGITAL FILTERS.

682 DISTRIBUTED AMPLIFIERS

DISTRIBUTED AMPLIFIERS
DEFINITION AND STRUCTURE

The objective of this article is to present various aspects of

distributed amplifiers. Distributed amplifiers are, by defini-
tion, electronic amplifiers consisting of distributed circuit pa-
rameters. Distributed circuit is a transmission line circuit,
and the physical length is comparable to operating wave-
length. However, in practice, an amplifier system consists of
a number of discrete amplifiers associated with distributed
parameter circuits, often termed the distributed amplifier.
The latter amplifier is actually a pseudo-distributed amplifier.
In practice, the distributed parameter circuit often takes
the form of a transmission line. The circuit parameters, the
inductance, the capacitance, and the resistance are distrib-
uted throughout the transmission line. If the transmission
line is a conventional passive transmission line, the electrical
output power of the transmission line is either equal to or less
than the electrical input power, depending on the power loss
of the transmission line.
If the transmission line is active, then the output power is
greater than the input. In this case, the transmission line is
considered as an amplifier. This is a distributed amplifier.
For example, an ordinary optical fiber cable is a passive
transmission line for lightwaves. The output light of the opti-
cal cable is always less than the input light due to the cable
loss. However, an erbium-doped optical fiber cable is differ-
ent. The lightwave output of the cable is larger than the
lightwave input. The input lightwaves, which are electromag-
netic waves, are amplified. The erbium-doped optical fiber ca-

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

Active transmission line
Input Output
Active substrate
(a) Distributed amplifier
Discrete amplifiers
Input Output
Transmission line
(b) Pseudo-distributed amplifier
Figure 1. Generic configuration of distributed amplifiers. Signals to
be amplified are fed at the left terminal. The signals are amplified
during propagation on the line. The amplified signals exit from the
right. (a) Distributed amplifier. The amplifier consists of a continuous
active transmission line. (b) Pseudo-distributed amplifier. Lumped
amplifiers are periodically loaded on a passive transmission line.
ble is an active transmission line and it is one type of distrib-
uted amplifier. A schematic diagram of a generic distributed
amplifier is shown in Fig. 1(a). In this distributed amplifier,
the transmission line is continuously loaded by the continu-
ously distributed power-pumping active substrate.
In a pseudo-distributed amplifier, a number of discrete am-
plifiers are periodically loaded as shown in Fig. 1(b). The in-
put power is amplified by these discrete amplifiers. Therefore,
the output of the transmission line is greater than the input
power.
The objective of the distributed amplifiers is to obtain a
wide-frequency bandwidth with high amplification gain. The
operating frequency ranges comprise radiofrequency (RF), mi-
crowaves, and lightwaves. Depending on the operating fre-
quency range, the amplifier configurations differ significantly.
The transmission line can be a two-wire line, a coaxial line, a
waveguide, a microstripline, a coplanar waveguide, or an opti-
cal fiber cable.
The term distributed amplifier contrasts against the terms
discrete amplifier and lumped amplifier. A lumped amplifier
is represented in a block diagram as shown in Fig. 2. In a
lumped or discrete amplifier, point A is the input, point B is
the output, and the geometrical distance between points A
and B is negligibly small in comparison with the operating
wavelength. A distributed amplifier can also be represented
by a block diagram as shown in Fig. 2, but the geometrical
distance between actual point A and actual point B is compa-
rable to the operating wavelength.
A G B will be at resonance. In such cases, the frequency bandwidth
Figure 2. A block diagram representation of a discrete amplifier, a
lumped amplifier, or a distributed amplifier. A generic symbol of a
generic amplifier. G represents the gain of the amplifier. It can be the
voltage, current, or power gain. A is the input, and B is the output
terminal.
DISTRIBUTED AMPLIFIERS 683
Continuous Active Diode Distributed Amplifiers
Activated or properly biased tunnel diodes, Gunn diodes, and
varactor diodes are considered to be active diodes. When tun-
nel diodes and Gunn diodes are properly biased, these diodes
exhibit negative resistance. Ordinarily a resistance is posi-
tive. A positive resistance consumes electrical energy. A nega-
tive resistance generates electrical energy. Therefore, if the
amount of negative resistance is adjusted by material compo-
sition, configuration and the bias current, and if the circuit
impedance of the transmission line is properly adjusted, then
the active diode-loaded transmission line can amplify propa-
gating electromagnetic waves on the transmission line. One
possible biasing method is illustrated in Fig. 3(a). The trans-
mission line is most likely a microstripline or a coplanar cou-
pled waveguide. The microstripline is dc biased through an
RF choke. If the active substrate is a tunnel diode of long
degenerate or heavily doped pn junction, the properly forward
biased pn junction exhibits negative resistance by the tunnel
effect (1). If the active substrate is a long Gunn diode of prop-
erly doped n-type GaAs, the substrate exhibits negative resis-
tance by the carrier momentum transfer effect (2).
The negative resistance can also be created by a properly
biased and pumped long varactor diode junction. The varactor
diode is a reverse biased pn-junction diode. This is a variable
capacitance diode and the junction capacitance is varied de-
pending on the bias voltage across the diode. The junction
capacitance in the case of Fig. 3(b) is controlled by the dc bias
and the pump oscillator voltage launched on the microstrip-
line transmission line. Some varactor diodes work without dc
bias. For optimal results, the pump oscillator frequency f p is
approximately twice that of the signal frequency f s. When the
pump oscillator frequency and phase are properly adjusted,
the energy of the pump oscillator transfers to the signal
through the variable junction capacitance and the signal
waves are amplified as the waves propagate on the micro-
stripline. The amplifier that functions by using a junction ca-
pacitance is termed a varactor parametric amplifier (1). The
type of parametric amplifier shown in Fig. 3(b) is a traveling
wave varactor parametric amplifier. Because the junction ca-
pacitance is continuously distributed along the microstripline,
this is a distributed amplifier.
The pump oscillator wavelength and phase are adjusted.
The pumping waves are synchronized with the input signal
so that the junction capacitance of the varactor transmission
line is always minimum where the signal voltage wave travel-
ing is maximum.
Periodically Loaded Active Diode Distributed Amplifiers
A schematic diagram of a periodically loaded active diode mi-
crostripline distributed amplifier is shown in Fig. 4(a). The
active diodes are either discrete tunnel diodes or Gunn di-
odes. Periodicity L is usually less than a quarter wavelength
in order to avoid resonance. When the periodicity is made
equal to either a quarter or a half wavelength the amplifier
narrows. It then may become unstable and oscillate. Reso-
nance should therefore be avoided. One of the objectives of the
distributed amplifier is to obtain a wide frequency bandwidth.
Therefore it is safe to keep periodicity L at less than a quarter
of a wavelength. The diodes must be correctly dc biased in the
middle of the negative resistance region.
684 DISTRIBUTED AMPLIFIERS

Dc bias
supply
Microstripline

Microwave
Microwave RFC RF
RF input output

Active subtrate

Ground plate
Tunnel diode junction or
Gunn diode subtrate

(a)

Variable
phase-shifter
Microstripline
Microwave
RF
Microwave
input RFC RF
N
Figure 3. Continuous diode distributed amplifiers. output
Electromagnetic waves to be amplified are fed from the
left end, and amplified signals exit at right. (a) Continu- Varactor diode junction
ously loaded tunnel diode or Gunn diode transmission
line distributed amplifier. The entire transmission line P Ground plate
consists of a long and narrow section of tunnel diode fp fs Low-pass filter Low-pass filter
junction or Gunn diode active region. (b) Continuously
High-pass filter
loaded varactor diode transmission line parametric dis-
tributed amplifier. The entire section of the transmission Pump oscillator
line consists of a reverse-biased variable capacitance
PN junction. (b)

Periodicity
Microwave RFC Microwave
RF Microstripline RF
input L output

Ground plate Discrete diodes

(a)

Microstripline
Variable Microwave
phase- RF
shifter input Microwave
RFC RF
Figure 4. Periodically loaded active diode distributed output
L
amplifiers. (a) Periodically loaded active diode micros-
tripline distributed amplifier. A microstripline is peri- fp fs
odically loaded by active diodes with periodicity L. A
properly biased active diode is capable of amplifying
electromagnetic signals. (b) Periodically loaded active Ground plate LPF
HPF LPF Varactor
capacitive parametric distributed amplifier. A micro- diodes
stripline is loaded periodically by properly biased and Pump oscillator
pumped varactor diodes with periodicity L. Such varac-
tor diode acts as a lumped amplifier. (b)
 yy
;;
Coupled
waveguide
conducting
strips
Lumped
diodes
Dielectric substrate
Figure 5. An example of a coplanar coupled waveguide distributed
amplifier. This is an example of a case in which the transmission
line is a coplanar coupled waveguide. Lumped diodes are mounted on
it periodically.
A schematic diagram of a periodically loaded variable ca-
pacitance diode (varactor diode) parametric distributed ampli-
fier is shown in Fig. 4(b). As seen from the diagram, varactor
diodes are reverse biased by the dc bias supply and are
pumped by the pump oscillator. Pump frequency f p must be
approximately twice that of the signal frequency f s to be am-
plified. The pump wave on the line must be synchronized with
the signal wave. Synchronization is accomplished using a
variable phase shifter as shown in the pump oscillator circuit.
The pump oscillator power is transferred into the signal
through the varactor and the signal wave is amplified (1,2).
The varactor diodes are pumped so that when and where the
signal waves crest the junction capacitance becomes mini-
mum. This phasing amplifies the microwave signal voltage.
The transmission line can be a microstripline as shown in Fig.
4(b) or a coplanar coupled waveguide. An example of a copla-
nar coupled waveguide distributed amplifier is sketched in
Fig. 5. As seen from this figure, fabrication of a coplanar cou-
pled waveguide amplifier is easier than the microstripline
amplifiers.
Continuous Transistor Distributed Amplifiers
A schematic diagram of a continuous transistor distributed
;;
yy
amplifier is shown in Fig. 6. This is a field effect transistor
(FET) of long configuration. Line length must be greater than
the wavelength of the operating carrier signals. The micro-
wave input signals are fed into the coplanar coupled wave-
Intrinsic
;;
yy
semiconductor
Drain strip substrate
VD RFC
Output
– +
– +
Input
VG
Source strip Gate strip
Figure 6. A schematic diagram of a continuous transistor distrib-
uted amplifier. This is a case of an extremely long gate field effect
transistor. The length of the gate can be several wavelengths longer
than the operating wavelength. As the input signals propagate on the
gate-source line, the amplified output signals travel on the drain-gate
line. The amplified signals exit at the right.
;;;
yyy
DISTRIBUTED AMPLIFIERS 685
Drain-gate
Drain coplanar
Quarter + – dc coupled
wavelength supply waveguide
choke
;;;
yyy
Microwave
output
Microwave
input
L
Periodicity –
Discrete
transistors Gate-source +
Gate
(FET) coplanar
coupled dc
waveguide supply
Figure 7. A schematic diagram of a periodically loaded transistor
distributed amplifier. Discrete transistors are periodically loaded on a
coplanar coupled waveguide. The input signals fed on the gate-source
coplanar coupled waveguide are amplified as propagation on the line.
The amplified output appears on the drain-gate coplanar coupled
waveguide. The output propagates on the line and exits from the
right.
guide, which consists of the gate strip and the source strip. As
the input microwaves propagate along this input gate-source
coplanar coupled waveguide, the amplified signal waves ap-
pear on the drain-gate coplanar coupled waveguide. Then the
amplified microwaves exit at the end of the drain-gate copla-
nar coupled waveguide. The long transistor must be properly
dc biased as shown in Fig. 6.
Periodically Loaded Transistor Distributed Amplifiers
A schematic diagram of a periodically loaded transistor dis-
tributed amplifier is shown in Fig. 7. To be qualified as a dis-
tributed amplifier, the length of a coplanar coupled waveguide
must be longer than the wavelength of operating microwaves.
If the length is very short it indicates simple parallel opera-
tion of the transistors. The input microwave signals are fed
to the input of the gate-source coplanar coupled waveguide as
shown in Fig. 7. As microwaves propagate down the gate-
source waveguide, the amplified microwaves appear on the
drain-gate coplanar coupled waveguide. The amplified micro-
waves propagate toward the output and exit from there. The
coplanar coupled waveguides are periodically loaded by dis-
crete field effect transistors. Periodicity L must be less than
a quarter of a wavelength to avoid resonance. Otherwise,
n(␭l /2) ⬍ L ⬍ (2n ⫹ 1)(␭l /4) where ␭l is the transmission line
wavelength and n ⫽ 0, 1, 2, 3, . . ..
Thermionic Traveling Wave Distributed Amplifiers
A thermionic traveling wave amplifier, also called a traveling
wave tube amplifier (TWTA), is a vacuum tube (2). Electrons
are emitted from an electron gun into a vacuum as shown in
Fig. 8. The emitted electrons are pulled by the anode (a heli-
cal transmission line) and focused by the longitudinally ap-
plied dc magnetic flux B. The electron beam is shot through
the helix line and hits at an end-plate called an electron col-
lector. The electron collector collects used-up electrons. The
686 DISTRIBUTED AMPLIFIERS

Microwave Microwave lightwave is propagating in the fiber cable, the signal

input output lightwave is intensified by the emission of radiation from the
erbium atoms that are pumped by the lightwave (propagating
Electron RFC in the fiber cable) from the pump laser. The pump lightwave
gun B travels with the signal lightwave and pumps the energy into
the signal lightwaves through the stimulated emission of ra-
diation from erbium atoms. This particular optical fiber is
considered to be a distributed parameter transmission line
Va Electron Electron amplifier for propagating optical electromagnetic wave
beam collector
signals.

Figure 8. A schematic diagram of a thermionic traveling wave dis-

tributed amplifier. The pitch of the helical transmission line is ad- GENERAL GOVERNING EQUATIONS
justed so that the axial speed of microwave propagation on the line
is almost equal to the speed of the electron beam. Under this condi- Gain
tion, the kinetic energy of electrons is transferred into the traveling
microwaves on the line, and the propagating microwaves are am- A generic configuration of a distributed amplifier transmis-
plified. sion circuit is shown in Fig. 10. In this diagram, R is the se-
ries resistance per meter of the distributed amplifier, L is the
series inductance per meter of the distributed amplifier, ⫺G
helix transmission line is a distributed parameter transmis- is the negative conductance per meter of the distributed am-
sion line. The pitch angle of the helix transmission line, the plifier, and C is the capacitance per meter of the distributed
diameter of the helix, and the electron acceleration voltage amplifier. The amplification constant of this amplifier is (1),
are adjusted in such a way that the speed of the electron
beam is equal to the axial propagation speed of microwaves ω(CR − LG)
α=   1/2 [neper/m] (1)
on the helix transmission line. Then the kinetic energy of the
√
2 (ω2 LC + RG) + ω (CR − LG)
2 2
electron beam is transferred to the microwave energy on the
helical line through the distributed capacitance between +(RG + ω2 LC)2
the electron beam and the helical line. As the microwaves on
the line and the electrons in the beam travel together, the where G is the magnitude of the negative conductance param-
microwaves are amplified and exit from the output of the tube eter. In a distributed amplifier, if the propagating power in-
as shown in Fig. 8 (2). The helical transmission line can be crease per meter is ⌬P(W/m) and the propagating voltage in-
replaced by a meanderline or an interdigital transmission crease parameter is ⌬V(V/m), the magnitude of the negative
line (2). conductance per meter is G ⫽ 2⌬P/(⌬V)2 (S/m).
The phase constant of this amplifier is (1),
Fiber Optic Distributed Amplifiers
 2  
A schematic diagram of a fiber optic distributed amplifier is (ω LC +RG) + ω2 (CR−LG)2 + (ω2 LC +RG)2 1/2
shown in Fig. 9. The main part of this amplifier is a section β= √ [rad/m]
2
of erbium-doped optical glass fiber cable (3). As seen from this (2)
figure, if a lightwave of proper wavelength is pumped into the
fiber cable through a directional coupler from a pump laser, If the length of the active region of the amplifier is ᐉ m long
and the lightwave signal to be amplified is fed into the input then the voltage gain of the amplifier is
of the fiber cable through an isolator, then while the signal
A = α [neper] (3)
Optical
isolator Amplified The total phase shift across the active region of the amplifier
Input lightwave is
Lightwave
connector output
input
φ = β [radian] (4)

Output
Optical
connector
Pump isolator R L R L R L
laser
Directional Output
coupler Erbium doped
optical fiber
cable Input –G C –G C –G C

Figure 9. A schematic diagram of a fiber cable lightwave distributed

amplifier. Active part is a long section of erbium-doped fiber cable.
The erbium atoms are pumped by a light from the pump laser at left. Figure 10. An equivalent circuit of a generic distributed amplifier.
The input lightwave signals are amplified by the stimulated emission The negative conductance ⫺G generates energy and amplifies signals
of radiation from the pumped erbium atoms in the active fiber cable. which are traveling on this line.
 DISTRIBUTED AMPLIFIERS 687

Frequency Bandwidth where Ap is given by

In a generic distributed amplifier, the circuit parameters R, Ap =  2α (13)
L, C, and G, are functions of operating frequency f. Therefore,
the voltage gain of the amplifier is where 움ᐉ is given by Eq. (5).
A( f ) = α( f )
Noise Figure
(2π f )(C( f )R( f ) − L( f )G( f ))
= 
√ Noise figure F of an amplifier is given by definition (1)
2 ((2π f )2 L( f )C( f ) + R( f )G( f ))
 1/2 No
F= (14)
(2π f )2 (C( f )R( f ) − L( f )G( f ))2 KTBAp
+
+(R( f )G( f ) + (2π f )2 L( f )C( f ))2
(5) where No is the noise output of the amplifier (W). For a dis-
tributed amplifier, both the frequency bandwidth B and the
At the edge of the frequency bandwidth at a frequency f⬘, power amplification A are given by Eqs. (6) and (7), respec-
1 tively.
A( f  ) = √ A( f 0 ) (6)
2
Dynamic Range
where f 0 is the center frequency of the amplifier. Usually Eq. A range of input signal level in which the gain of the amplifier
(6) is at least the second-order equation of f⬘. One root is f⬘H, is constant is termed the dynamic range of the amplifier. Usu-
which is greater than f 0, and the other is f⬘L, which is less ally, the gain of an amplifier is less at an extremely small
than f 0. Then the frequency bandwidth is input signal level or at a large input signal level.
In semiconductor distributed amplifiers, thermionic dis-
 f = f H − f L (7)
tributed amplifiers, or even in fiber optic distributed amplifi-
ers, the values of L, C, R, and G are inherently functions of
Sensitivity operating signal levels ␯s. Therefore, in Eq. (1),
According to the IEEE Standard Dictionary of Electrical and
ω(C(νs )R(νs ) − L(νs )G(νs ))
Electronics Terms (4), sensitivity is defined as ‘‘the minimum α(νs ) = 
√
input signal required to produce a specified output signal hav- 2 (ω2 L(νs )C(νs ) + R(νs )G(νs ))
ing a specified signal to noise ratio.’’ This means that  1/2
ω2 (C(νs )R(νs ) − L(νs )G(νs ))2
Ps Ap So +
= (8) +(R(νs )G(νs ) + ω2 L(νs )C(νs ))2
KTBAp F No
(15)
where Ap is the power gain of an amplifier, K is the Boltz-
mann constant 1.38054 ⫻ 10⫺23 J/K, T is the absolute temper- If the gain constant in the linear region of the distributed
ature of the input circuit to the amplifier, B is the overall amplifier is 움0, then the power gain of the amplifier is
frequency bandwidth of the amplifier, Ps is the input signal
Ap0 = e2α 0  (16)
power, F is the noise figure of the amplifier, and So /No is the
signal-to-noise power ratio of the amplifier at the output.
Then, where ᐉ is the length of the active region of the distributed
amplifier. In a large signal level ␯s the gain will be com-
So pressed due to saturation and
Ps = KTBF (9)
No
Ap (νs ) = e2α (ν s ) (17)
As ‘‘a specified signal to noise ratio,’’ often
where 움(␯s) is given in Eq. (15).
So If the gain compression of ⫺n dB is chosen, then,
=1 (10)
No
A(νs )
is used for the definition of the sensitivity of the amplifier. −n[dB] = 10 log10 (18)
A0
Then, the sensitivity is
 or

Ps  = KTBF (11)
S o /No =1 n[dB] = 10 log10 e2{α 0 −α (ν s )}  (19)
For a distributed amplifier, the value of B is obtained using or
Eq. (7). The value of the noise figure F can be obtained from
the next section. Then the sensitivity is n[dB] = 8.686{α0 − α(νs )} (20)

 No
Ps  = (12) In practice, n ⫽ 1 is often chosen, and the value of the input
Ap
S o /No =1 voltage for n ⫽ 1 is termed the input signal voltage at 1 dB
688 DISTRIBUTED AMPLIFIERS

compression point. The 1 dB compression point input signal

voltage is then
L
1
α(νs ) = α0 − (21)
8.686
Rs C
Stability
As seen from Eq. (1), a generic distributed amplifier is inher-
–G Cj
ently stable. A controlling parameter in Eq. (1) is the magni-
tude of the negative conductance per meter G. Equation (1)
does not show any singularity due to the size of G within the
range of practical operation.
Figure 12. Equivalent circuit of a tunnel diode. This is for a pack-
aged diode properly biased. C is the package capacitance; L is the
PERIODICALLY LOADED ACTIVE lead inductance; Rs is the spreading resistance; Cj is the junction ca-
DIODE DISTRIBUTED AMPLIFIERS pacitance; and ⫺G is the negative conductance of the tunnel diode
packaged.
Periodically Loaded Tunnel Diode Distributed Amplifiers
In a periodically loaded tunnel diode disturbed amplifier, a At any diode in Fig. 4(a), half of the amplified power goes
number of discrete tunnel diodes are periodically loaded on back to the input and the other half of the amplified power
an RF transmission line as shown in Fig. 4(a). A generic volt keeps traveling toward the output. Thus, actual power gain
ampere curve of a tunnel diode is shown in Fig. 11. This is a of traveling waves toward the output is
plot of the diode current and the voltage across the diode.
1
When the diode is biased in a negative conductance region, A+ = (24)
the amount of the negative conductance is given by 2(1 − GD Z0 )

∂I If there are N diodes used in a distributed amplifier as shown

G= <0 (22)
∂V in Fig. 4(a), the total power gain of the amplifier is

In Fig. 12, an equivalent circuit of a discrete tunnel diode is 1

AT = (A+ )N = (25)
shown. In this figure, L is the lead inductance, Rs is the 2N (1 − GD Z0 )N
spreading resistance, CJ is the junction capacitance, Cp is the
package capacitance, and ⫺G is the negative conductance of after matching and tuning.
the tunnel junction created by the tunnel effect. With the help For the impedance matching and tuning, in addition to at-
of additional impedance matching components it is possible taching the impedance matching circuit components to the di-
to tune out the inductances and capacitances; under a ode mount, the adjustment of periodicity together with the
matched and tuned condition, the tunnel diode can be repre- diode biasing must be done properly.
sented by a negative conductance of magnitude GD.
The RF power gain due to a discrete negative conductance Periodically Loaded Gunn Diode Distributed Amplifiers
GD, which is matched to a characteristic impedance of the A volt-ampere characteristic of a generic Gunn diode is
transmission line Z0, is (3), shaped similarly to that shown in Fig. 11 except that the neg-
ative conductance is smaller than that of a tunnel diode. The
1
A= (23) negative conductance of a Gunn diode is created by the trans-
1 − GD Z 0 fer of the electronic momentum between a high electric field
domain and a low field domain in the bulk of a semiconductor
diode. The equivalent circuit of a Gunn diode is similar to the
∂I
<0 circuit shown in Fig. 12. Therefore, the principle of a periodi-
Tunnel ∂V
cally loaded Gunn diode distributed amplifier is similar to the
effect Negative principle of a periodically loaded tunnel diode distributed am-
I current conductance plifier. Then the power gain equation of a Gunn diode distrib-
region
uted amplifier, which consists of N Gunn diodes in the nega-
tive conductance GD and with the characteristics impedance
Z0, is
Diffusion
current 1
AT = (26)
2N (1 − GD Z0 )N
O V
Periodically Loaded Varactor Diode
Figure 11. Generic volt-ampere curve of a tunnel diode. Note that Distributed Parametric Amplifier
this volt-ampere curve does not follow Ohm’s Law. Note also the neg-
ative differential conductance at the mid-voltage region. This is a plot When discrete variable capacitance diodes (varactor diodes)
of the diode current versus the diode bias voltage relationship. are periodically mounted on a transmission line as shown in
 DISTRIBUTED AMPLIFIERS 689

Fig. 4(b), RF voltage is amplified by the parametric effect of where 웁e is the phase constant associated with the dc electron
the junction capacitance. The voltage gain across a single beam and
parametric capacitance diode is given by Ref. 2.
 βe ≡ ω/u0 (34)
νp Qi 
A= + Qs (27) 웆 is the operating angular frequency and u0 is the speed of
4(vo + vro )
the electrons in the beam. Term C in Eq. (33) is termed the
where ␯p is the pump voltage across the junction capacitance gain parameter (1,2) and is given by
of the varactor diode, vo is the magnitude of the contact poten-
Z0 Ia
tial barrier of the diode, vro is the dc reverse bias voltage, and C3 = (35)
Qi and Qs are the quality factors of the idler circuit and the 4Va
signal circuit per diode, respectively.
where Z0 is the characteristic impedance of the helical line,
Usually in a parametric amplifier, the idler frequency
Ia is the dc electron beam current, and Va is the acceleration
shown in Fig. 4(b) is
anode voltage of the traveling wave tube.
fi = fp − fs (28) If the length of the active interaction region on the helical
transmission line is ᐉ m long, then the voltage gain of this
and traveling wave tube is (2)
√
fp
2 fs (29) A = e( 3/2)Cβ e 
(36)

for a high gain (5). Then,

QUANTUM ELECTRONIC DISTRIBUTED AMPLIFIERS
Qi
Qs (30)
A quantum electronic distributed amplifier can be a continu-
Applying the same concept as was done in Eqs. (25) and ous configuration as shown in Fig. 9. If the signal to be ampli-
(26), the total voltage gain of an N-diode distributed paramet- fied is a lightwave, then this distributed amplifier is a travel-
ric amplifier is, after matching and tuning, ing wave laser. If the signal to be amplified is a microwave,
  N then this distributed amplifier is a traveling wave maser. For
νp Qi  a traveling wave maser, instead of the optical fiber cable, a
Aν T = + Qs (31)
4(vo + vro ) microwave transmission line continuously loaded with maser
material (such as a ruby or a rutile crystal) and a microwave
local pump oscillator instead of the pump laser, are used.
PERIODICALLY LOADED TRANSISTOR At any rate, the gain constant of a traveling wave maser
DISTRIBUTED AMPLIFIER or laser distributed amplifier is given by (9)
ω
Similar concepts of Eqs. (25), (26), and (31) are applicable to α= (37)
a periodically loaded discrete transistor amplifier. The tran- 2Qmo νg
sistors can be either junction transistors or field effect tran-
sistors (6–8). If the s-parameter of the discrete transistor where 웆 is the angular frequency of the signal to be ampli-
from the gate (or base) to the drain (or collector) is S21, then, fied, Qmo is the quality factor/meter of the active cable and vg
after impedance matching and tuning, the voltage gain of an is the group velocity of the signal in the cable. The quality
n-transistor distributed amplifier is given by factor Qmo is given by

Aν T = SN (32) Wso
21 Qmo = ω (38)
P

THERMIONIC DISTRIBUTED AMPLIFIERS
Thermionic distributed amplifiers are vacuum tubes that are
called traveling wave tubes. A schematic diagram of a generic
traveling wave tube is shown in Fig. 8. The principle of the
traveling wave tube distributed amplifier was already briefly
explained in this article. While microwaves travel along the
helical transmission line with the axial propagation speed ap-
proximately equal to the speed of electron beam, the kinetic
energy of the electron beam is transferred gradually into the
propagating microwaves in the transmission circuit; hence
the microwaves are amplified. The propagation constant of a
traveling wave tube is given by (1,2)
 √  
3 C
γ̇ = βe − C+ j 1+ (m−1 ) (33)
2 2
where Wso is the electromagnetic energy of the signal stored
per meter of the cable and ⌬P is the signal power loss per
meter of the cable.
The voltage gain of this continuously loaded distributed la-
ser or maser amplifier is
A =  ω/2Q mo ν g (39)
where ᐉ is the length of active part of the cable.
A quantum electronic distributed amplifier can be a peri-
odical loading configuration as shown in Fig. 13. A microwave
transmission line of a periodic structure is continuously
loaded with an activated maser crystal and placed in a rectan-
gular microwave waveguide. The pump power from a pump
oscillator is fed to the rectangular waveguide to activate the
maser crystal. The pumped-up maser crystal emits radiation
when stimulated by the input microwave signals.
690 DISTRIBUTED AMPLIFIERS

Microwave Microwave EXAMPLES OF DISTRIBUTED AMPLIFIERS

input output
RF Distributed Amplifiers
Periodicity In practice, at RFs of less than 300 MHz, a distributed ampli-
fier can be built using discrete components or surface mount-
Pump able discrete components (10). An example of such distributed
oscillator amplifiers is shown schematically in Fig. 14.
input
Discrete field-effect transistors (FETs) are sequentially ex-
cited through the gate delay line or the gate artificial trans-
Termination Waveguide Periodical
mission line and consist of Cg, 
Lg, Lg, Lgg, and Rg. These are
line
discrete components. The Cg is a dc blocking input coupling
Ruby maser crystal capacitor, Lg is an inductor to produce desired phase delay
Figure 13. A schematic diagram of a periodically loaded quantum between stages of the FET amplifiers, and Rg is the matched
electronic maser distributed amplifier. The ruby maser crystal is terminating resistor for the artificial transmission line. The
pumped by the pump oscillator input in the waveguide. Microwave idea is to generate RF traveling waves on the gate artificial
input signals are amplified by the stimulated emission of radiation transmission line. The Lgg is a stray inductance of the gate
from the pumped ruby maser crystal, while propagating down the lead. In most cases Lgg is negligibly small at most RF frequen-
meander line. The meander line is structured to lengthen the interac- cies. The terms Rs and Cs signify the source bias resistor and
tion time between the input signals and the stimulated emission of bypass capacitor and Ldd is the stray inductance of the drain
radiation. of the FET. By making the drain lead as short as possible, it
is possible to make Ldd negligibly small at RF frequencies.
The drain delay line or the drain artificial transmission
The voltage gain of the periodically loaded quantum elec- line is formed by Rd, Ld, and Cd. The Rd is an impedance
tronic distributed amplifier given by matched resistor to the drain artificial transmission line and
Ld is the phase delaying inductor between stages. The value
A =  ω/2Q mp ν g (40) of Ld must be determined so that the phase of waves on the
drain artificial transmission line synchronizes with the phase
is in principle similar to the case of continuously loaded quan- of waves on the gate artificial transmission line. The Cd is a
tum electronic distributed amplifier where Qmp is the quality dc blocking RF coupling capacitor to the output load. The
factor within the periodicity of the periodical structure. transistors are biased through a radio frequency choke (RFC)
and a decoupling capacitor.
Wsp
Qmp = ω (41)
P Microwave Distributed Amplifiers
where Wsp is the signal energy stored within the periodicity of A variety of microwave frequency distributed amplifiers have
the structure of the transmission line and ⌬P is the signal been built in the past (10–12). In microwave frequencies, the
power loss within the periodicity. distributed amplifiers take the forms of monolithically devel-

Vdd

RFC

1/2Ld Ld Ld 1/2Ld Cd

Matched
termination Rd RF
Ldd Ldd Ldd Output

Rs Cs Rs Cs Rs Cs
Lgg Lgg Lgg
Cg 1/2Lg

RF Lg Lg Lg Lg
input Rg

Matched
termination

Figure 14. A schematic diagram of an example of an RF distributed amplifier. The input signals
are successively and sequentially amplified by properly phased multistage FET amplifiers.

Vdd
RFC
Drain Microstripline
Rd
Ccg
Microwave Gate Microstripline
input
oped integrated circuits as shown in Fig. 15 (for example). As
is the case in Fig. 14, the microwave input signals to be am-
plified are fed to the gate microstripline with impedance-
matched terminating resistance Rg through a dc blocking cou-
pling capacitor Ccg. The gate of each FET, which is properly
biased, is sequentially excited. Amplified microwave drain
current propagates along the drain microstripline toward the
output and it is coupled out to the output circuit through a dc
blocking coupling capacitor Ccd. The drain microstripline is
terminated with an impedance matched resistor Rd. If the cir-
cuit is properly balanced, current traveling toward Ccd adds
in-phase, while current traveling toward Rd adds out-of-
phase. This amplifier is actually a ‘‘current combiner.’’ The
drain microstripline is biased through a RFC and a bypass
capacitor with VDD.
At best, a distributed amplifier has only half the efficiency
and requires twice the total gate width as a balanced ampli-
fier, for the same gain (13). Gain, it should be noted, can be
increased by adding more FETs—that is, by making it longer;
best efficiency can be achieved, however, by optimizing the
length. Once an optimal length is achieved, these distributed
amplifiers can be cascaded in order to achieve the prescribed
gain.
Because of losses in the amplifier, best performance can be
achieved by tapering the gate (14), so as to ‘‘pre-distort’’ the
applied gate voltage along the length of the amplifier, and aid
in maintenance of a more steady voltage applied to the effec-
tive gate. Higher power, large signal amplifiers have also
been designed and evaluated (15–19). Distributed amplifiers
are limited in the amount of power they deliver, generally
about 1 Watt (when using a 50 ⍀ transmission line). Low-
ering the impedance of the line can allow greater output pow-
ers but at the expense of a reduction in gain. Tapering the
drain line has been found (20,21) to increase efficiency by im-
proving the phasing of currents on the drain line.
Most microwave monolithic IC distributed amplifiers are
of extremely wide frequency band even though total gain is
not very high. They are also extremely compact. For example,
Kimura and Imai (11) monolithically integrated a seven-stage
distributed amplifier on a 1.5 mm ⫻ 2.5 mm integrated circuit
(IC) substrate and reported that the flat gain over the fre-
quency range 0 to 55 GHz with 6 dB noise figure was 9 dB.
DISTRIBUTED AMPLIFIERS 691
Cdd
Microwave
Output
Figure 15. A schematic diagram of a micro-
wave monolithic distributed amplifier. Both
Rg the gate and drain lines are microstriplines.
The gate line feeds the FET sequentially. On
the drain microstripline, the amplified sig-
nals are sequentially combined and propa-
gate out at right.
Lightwave Distributed Amplifiers
The actual configuration of a lightwave distributed amplifier
is shown in Fig. 9. These amplifiers are actually deployed to
boost lightwave signals for a long-haul lightwave signal
transmission such as in transoceanic lightwave cables. For
example, the lightwave input signal to be amplified is 1500
nm wavelength (3). The pump laser is a 980 nm solid-state
laser diode that feeds the pump power through a directional
coupler to the main cable. The directional coupler is a pair of
lightwave waveguides placed in proximity to each other so
that the lightwaves can couple one waveguide to another. The
end of the lightwave guide for the pump laser, which is the
primary waveguide of the directional coupler, is reflec-
tionlessly terminated using a lightwave absorbing component.
The pump-laser light is fed into the main lightwave wave-
guide, which is the erbium-doped optical fiber. The pump
laser light excites or pumps up the atoms of erbium to pre-
pare for emission of radiation at 1500 nm. When these
pumped up erbium atoms receive stimulating radiation of
1500 nm from the input lightwaves, these atoms emit radia-
tion at the same 1500 nm wavelength. This is a laser ampli-
fier. The emission of radiation continues as the input
lightwave travels in the erbium-doped optical fiber. The emit-
ted wave travels together with the stimulating lightwave. The
amplified lightwave exits the output connector. The pump
power is minimal at this point. It has been used in the ampli-
fication process. The signal output is taken out of the system
through a bandpass filter for the signal lightwave. Any resid-
ual pump lightwave is rejected at the filter. The lightwave
gain of 15 dB is reported for several meters-long erbium-
doped plastic optical fiber cable.
The amplifier cable can be praseodymium-doped fluoride
fiberglass cable with a wavelength of 1300 nm (3). The gain
of 40 dB for several meter-long cable length is reported (3).
CONTINUOUS DISTRIBUTED AMPLIFIERS
Continuous Active Diode Distributed Amplifiers
In Fig. 5, it is possible to monolithically develop a continuous
tunnel diode junction or Gunn effect diode contact between
the two strips of metallization by removing all discrete diodes
692 DISTRIBUTED AMPLIFIERS
and using an intrinsic semiconductor substrate instead of the
dielectric substrate. Then, if the conducting strips from the
coplanar waveguide are properly biased at the negative resis-
tance of the diode, the microwaves fed into one end of the
coplanar waveguide will be amplified by the distributed nega-
tive resistance as it travels along the coplanar waveguide and
the amplified microwave exits from the other end of the copla-
nar waveguide.
Continuous Transistor Distributed Amplifiers
A conceptual diagram of a continuous transistor distributed
amplifier is shown in Fig. 6. It is desirable that the length of
the microstrips must be longer than several wavelengths of
the transmission line wavelength. The transmission line
wavelength on the coplanar waveguide is smaller than the
free space wavelength and inversely proportional to the
square root of the effective relative permittivity of the sub-
strate in the gap between the conducting strips. For a semi-
conductor substrate, it is not uncommon that the effective rel-
ative permittivity is 10 or higher.
Continuous Parametric Varactor Diode Distributed Amplifier
A conceptual schematic diagram of a continuous parametric
varactor diode distributed amplifier is shown in Fig. 3(b). Us-
ing the same concept, an alternate method and more conve-
nient approach to the monolithic integrated circuit technology
is shown. Instead of using the microstripline as shown in Fig.
3(b), the configuration is changed to a coplanar waveguide as
shown in Fig. 5. A long junction varactor diode is monolithi-
cally developed flatly between the gap of a long parallel met-
allization strip of the coplanar waveguide.
Continuous Ferrimagnetic Distributed Amplifiers
Space between the long gap of metallization strips of either
the microstripline as shown in Fig. 3(b) or the coplanar wave-
guide as shown in Fig. 5, can be filled with a magnetized ferri-
magnetic material or a ferrite. This is a ferrimagnetic contin-
uous distributed amplifier (1,22). The nonlinear magnetism of
a ferrite makes the system a variable inductance parametric
amplifier when both the pump oscillator power and the signal
power are launched into the same transmission line. The
pump oscillator power then gradually transfers into the sig-
nals through the distributed nonlinear inductance of the fer-
rites as both the signals and the pump oscillator power travel
together along the ferrite loaded transmission line.
CONCLUSIONS
Distributed amplifiers are electrical transmission lines with
periodically or continuously loaded amplifiers. A feature of
distributed amplifiers is the wide frequency bandwidth. The
wide bandwidth amplifiers are capable both of having large
channel capacity and of handling extremely short or fast
pulses. Distributed amplifiers are useful for fast digital data
transmission systems of gigabit rates. Distributed amplifiers
can be made compact by the use of monolithic integrated cir-
cuit technology.
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ber 12–14, 1985.
22. P. K. Tien, Parametric amplification and frequency mixing in
propagating circuits, Jour. Appl. Physics, 29: 1347–1357, Septem-
ber 1958.
T. KORYU ISHII
Marquette University
 DISTRIBUTED DATABASES 693

DISTRIBUTED BATCH PROCESSING. See BATCH

CESSING (COMPUTERS).
54 ELLIPTIC FILTERS

ELLIPTIC FILTERS

An electrical filter will be defined as an electrical system that

can process electrical signals on the basis of the frequencies
composing that signal. This signal processing can affect both
the magnitude and phase of each individual frequency compo-
nent of the signal. For example, the output signal of an an-
tenna may represent an electrical signal that requires magni-
tude processing. The output signal of the antenna has a fairly
wide spectrum of frequencies, and yet we would like only a
small range of these frequencies, such as those centered

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.
 ELLIPTIC FILTERS 55

around our favorite radio station, for example, to be processed 2

for our listening pleasure. One solution is to use a band-pass
filter in one of the stages following the antenna. The circuit 1.8
would process that signal in such a way that the band of fre-
1.6
quencies containing the information from the station would
be passed, and the signals outside of that band would be re- 1.4
jected or would not pass through. Although this example is
very much simplified in comparison to what actually happens, 1.2

it nonetheless illustrates the general idea of filtering.
Because of a need to filter signals in a variety of ways,
several ‘‘standard’’ types of filters or signal processing
schemes have evolved. These are low-pass, high-pass, band-
pass, band-reject, and all-pass filters. Low-pass filters strive
to allow frequencies below some predetermined cutoff fre-
quency to pass, while rejecting those frequencies above the
cutoff frequency. High-pass filters strive to allow frequencies
above some predetermined cutoff frequency to pass, while re-
jecting those frequencies below the cutoff frequency. Band-
pass filters allow a band of frequencies to pass, while rejecting
frequencies outside of that band. Band-reject filters reject a
band of frequencies, allowing frequencies outside that band to
pass. The main objective of these four types of filters is to
process the signal’s magnitude as a function of frequency. The
all-pass filter lets all signals pass through, but selects a band
of frequencies for phase angle processing. The choice of filter
depends on the application.
Filter design can be broken down into two broad phases.
The first phase is the selection of a transfer function pos-
sessing the mathematical properties of filtering. A transfer
function describes the relationship between the input signal
and the output signal. We will use it in the sense that for a
given input signal, we will have a specific output signal. Since
filters process electrical signals according to the frequency
content, the transfer function for a filter is a function of s ⫽
j웆 ⫽ j2앟f, where 웆 is the frequency in radians/s and f is the
frequency in hertz.
The second phase of filter synthesis is realization of a cir-
cuit that possesses the same transfer function as the mathe-
matical function selected to do the filtering. The circuit may
be an analog, digital, or a mixed analog–digital circuit de-
pending on the application.
Magnitude
1
0.8
0.6
0.4
0.2
0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Frequency (radians/s)
Figure 1. The magnitude versus frequency plot of an ideal low-pass
filter transfer function shows that all frequencies of a signal below 1
rad/s are passed while those above 1 rad/s are rejected.
cessing, at the output of the filter at the same time. If the two
input signals add together to create a distinct response in the
time domain at the input, it may be important that they re-
construct together at the output to maintain the ‘‘shape’’ of
the input signal. Sometimes this is important, and sometimes
it is not. A deviation from the linear phase response results
in phase distortion. The functions shown in Figs. 1 and 2 are
normalized filters. That is, they have cutoff frequencies of 1
rad/s and maximum gains of 0 dB, or 1 V/V in the passband.
It is conventional to begin a filter design with a normalized
filter. This allows for a common starting point for all low-pass
filters, for example, and is also a convenient way of comparing
the characteristics of other different types of low-pass filter
0

–50
THE APPROXIMATION PROBLEM
–100
When filtering, engineers tend to think in terms of ideal fil-
ters. For example, when deciding to use a low-pass filter, the –150
Phase (deg)

engineer typically desires that all frequencies above a defined

cutoff frequency should be eliminated. An ideal low-pass –200
transfer function magnitude response with a cutoff frequency
–250
of 1 rad/s is shown in Fig. 1, and the ideal low-pass transfer
function phase characteristics are shown in Fig. 2. For the
–300
magnitude plot, all frequencies below 1 rad/s are passed, with
a gain of one, and all frequencies above 1 rad/s are rejected. –350
It is a ‘‘brick wall’’ function. It is intuitively obvious that this
is an ideal magnitude characteristic. The ideal phase charac- –400
teristic is not so intuitive. The important feature of the ideal
phase characteristics are not the values of the phase angle, –450
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
but that the phase response is linear. A transfer function that
Frequency (radians/s)
has linear phase characteristics means that separate signals
composed of two different frequencies applied at the same in- Figure 2. The ideal low-pass filter function phase characteristics
stant of time at the input of the filter will arrive, after pro- may be summarized as a linear phase response.
56 ELLIPTIC FILTERS
Magnitude
H these (1,2).
PBR
G tude function. Each of these were designed to optimize a prop-
A
Passband
Stopband SBR
0
0 ωp ωs
Frequency (radians/s)
Figure 3. PBR, SBR, A, passband, and stopband are ways of charac-
terizing an actual filter function’s magnitude versus frequency re-
sponse to that of an ideal response. For an ideal filter function,
PBR ⫽ SBR ⫽ 0 V/V and 웆s and 웆p are equal.
functions with each other. Moreover, numerous tables exist
that provide the coefficients or poles and zeros of filter trans-
fer functions. These tables provide information for normalized
filters. Since there is an infinite number of possibilities for
cutoff frequencies, it would be impractical, if not impossible,
to generate tables for all possible cases. Thus, the tables deal
only with the normalized case. It is trivial to scale a filter for
a desired cutoff frequency from the normalized frequency.
The first step in low-pass filter design is to find a transfer
function of s having the same characteristics as the transfer
function depicted in Fig. 1 and being realizable with a circuit.
Without having transfer function with an infinite number of
terms, it is impossible to devise a transfer function with those
characteristics. Hence, from this simple example arises the
approximation problem. That is, may we find a transfer func-
tion magnitude response that approaches that shown in Fig.
1? In general, the higher the order of the filter, the closer the
transfer function magnitude response will approach the ideal
case. However, the higher the order of a filter, the more com-
plex the design and the more components that are needed to
realize the transfer function. Thus, the concept of trade-offs
and compromises arise. In general, a set of filter specifications
must be determined before selecting the transfer function.
The specifications may viewed as how far the actual filter re-
sponse may deviate from the ideal response.
Since it is impossible to come up with an ideal transfer
function that is practically realizable, several terms have
been defined and have been accepted as convention that
allows the description of the deviation of a practical filter
function from the ideal filter function. These terms are de-
picted in Fig. 3 and may be referred to as filter specifications.
The specifications are: the passband, the stopband, the pass-
band ripple (PBR), the stopband ripple (SBR), and the stop-
band attenuation, A. PBR, SBR, and A are usually specified
in dB. There are three distinct regions. The passband is lo-
cated from 0 rad/s to 웆p rad/s. The second region is the stop-
band region located from 웆s to infinity. Lastly, the transition
region is composed of the range between 웆p and 웆s. Figure 3
should be interpreted as follows: Signals at or below 웆p will
have a gain of at least of G dB and at the most H dB, and
signals above 웆s will be attenuated by at least A dB or will
have a maximum gain of SBR dB. Note that (G–H) dB ⫽ PBR
in dB. Filter types other than low-pass filters have similar
specifications, and the reader is encouraged to investigate
Past research in network theory has resulted in several
classic mathematical approximations to the ideal filter magni-
erty of the filter function. The low-pass filter approximations
are usually of the form
1
|H( jω)|2 = (1)
1 +  2 T 2 (ω)
By replacing T(웆) with different functions, different approxi-
mations arise. The standard approximations to the ideal mag-
nitude response are the Butterworth Approximation, the
Chebychev Approximation, the Inverse-Chebychev Approxi-
mation, and the Elliptic Approximation. Each has strong
points and weak points. A fifth classic approximation worth
mentioning is the Bessel function. This approximation will
not be discussed, because it strives to approximate the ideal
phase response. This article will focus on the Elliptic Approxi-
mation.
THE ELLIPTIC APPROXIMATION
Before a mathematical discussion on the Elliptic Approxima-
tion is begun, it is useful to examine a plot of the magnitude
of an elliptic filter function. A fifth order elliptic filter low-
pass transfer function magnitude response is depicted in Fig.
4. The passband exists for 웆 ⱕ 웆p. The stopband exists for
웆 ⱖ 웆s. The passband and stopband may be characterized as
equiripple. That is, the amplitude oscillates between a maxi-
2
1.8
1.6
1.4
1.2
Magnitude
1
0.8
0.6
0.4
0.2
0
ωp ωs
Frequency (radians/s)
Figure 4. The magnitude characteristics of a fifth-order elliptic filter
show an equiripple passband and stopband, and at zero at 웆 ⫽ 앝.
 ELLIPTIC FILTERS 57

2 Table 1. Filter Comparisons

Filter Type Transition Region Linear Phase Properties
1.8
Butterworth Poor Good
1.6 Chebychev Good Poor
Elliptic Best Very poor
1.4

1.2
Butterworth
1 From this discussion, the main attribute of the elliptic filter
may be stated. That is, for a given filter order, it provides the
0.8
sharpest cutoff characteristics; and thus out of all three fil-
0.6 Elliptic ters, it best approximates the ideal low-pass magnitude func-
Chebychev
tion in terms of a sharp transition region. This is very impor-
0.4 tant if filtering is required for frequencies near each other, if
we would like to pass one of these signals, and reject another.
0.2
The compromise in using the elliptic filter is its very poor
0 phase characteristics.
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 The theory behind the mathematics of the elliptic filter is
Frequency (radians/s) complicated and is not suitable for this publication. Interested
readers may consult Refs. 2 and 3. A summary of the mathe-
Figure 5. The fifth-order elliptic function magnitude characteristics
show a much sharper transition from the passband to the stopband matics is discussed in this article.
than the Butterworth and Chebychev function characteristics. The general form of the elliptic filter magnitude squared
transfer function is given by Eq. (1). For the low-pass elliptic
filter function, T( j웆) is replaced with Rn( j웆). Rn( j웆) has two
mum and minimum throughout a fraction of each band. If the different forms: one for an even-order function and one for an
order of the filter is even, there are n/2 peaks in the pass- odd-order function. Rn( j웆) will be described for a normalized
band, and n/2 minimums or zeros in the stopband. If the or- low-pass filter. For the even-order case we have
der of the filter is odd, there are (n ⫺ 1)/2 peaks, plus one at
웆 ⫽ 0 in the passband. Also for the odd order case, there are 
n/2 2
ω − (ωs /ωi )2
(n ⫺ 1)/2 minimums or zeros, plus one at 웆 ⫽ 앝, in the Rn (ω) = M (2)
i=1
ω2 − ωi2
stopband.
In discussing the properties of the elliptic filter, it is impor-
tant to compare its characteristics with the other classic filter For the odd-order case we have
types. A comparison of fifth-order, low-pass, normalized, But-
terworth, Chebychev, and elliptic filter magnitude functions 
(n−1)/2
ω2 − (ωs /ωi )2
Rn (ω) = Nω (3)
is given in Fig. 5, and comparison of the phases is shown in
i=1
ω2 − ωi2
Fig. 6. From these comparisons, Table 1 may be generated.
M and N are normalization constants and are chosen so that
0 Rn(1) ⫽ 1. The 웆i are calculated for the even or odd case. For
the even case we have
–50
ωs
ωi = 
1  (4)
–100
(2i − 1)K
sn  ωs 
Elliptic
–150 n
Phase (deg)

–200
and for the odd case we obtain
Butterworth
–250
ωs
ωi = 
1  (5)
–300 Chebychev
sn  2iK ωs 
–350 n

–400
K(k) is the complete elliptic integral of the first kind and is
–450 defined as
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
π /2
Frequency (radians/s)
K(x) = (1 − k2 sin2 x)−1/2 dx (6)
Figure 6. The fifth-order elliptic function phase characteristics devi- 0

ate much farther from the desired ideal linear phase characteristics
than the Butterworth and Chebychev function characteristics. and sn is the Jacobian elliptic sine function.
58 ELLIPTIC FILTERS

The order of the filter function may be determined by of products of poles and zeros, depending on the type of real-
rounding up n to the nearest integer in the expression ization.

1
1 Because of the complexity of the calculations required to
K K find the transfer function, the usual method of finding H(s) is
n=
ω1s 
L1  (7)
usually either with a computer program or using one of the
numerous tables that have been generated and published
K K
ωs L (2,5).

where L is defined as


REALIZATIONS OF ELLIPTIC FILTERS

100.1 PBR − 1 There are an infinite number of possible synthesis algorithms

L= (8)
100.1 A − 1 that may be used. In this section we describe one.
The first step in elliptic filter design is to find a transfer
and PBR and A are in decibels. Lastly, function that will meet a set of specifications that have been
p determined from the application. The design usually begins
K  (k) = K( (1 − k2 )) (9) with specifying the passband frequency 웆p, PBR, 웆s, and A. If
filter tables are to be used, the frequencies of the filter speci-
When Rn(웆) is found, the substitution s ⫽ 웆/j is made, and fications must first be normalized. This is achieved by divid-
Rn(웆/j) may be inserted into Eq. (1). The poles of H(s)H(s*) ing 웆s and 웆p by 웆p. Other normalizations are possible. This
can be found. This is a standard synthesis technique (4). The results in a normalized passband frequency of 1, and a nor-
left half-plane poles and half of the zeros are selected and malized stopband frequency of 웆s /웆p. If a highpass filter is
combined to give the final form of the elliptic filter transfer desired, the specifications must be transformed further, by in-
function. For n even, we have verting 웆p to 1/웆p. Once the desired transfer function is deter-
mined, a method of realization is selected. The realizations

n/2 may be analog or digital. The analog realizations may be
(s2 + ωi2 ) passive or active. The choice depends on many practical is-
i=1
H(s) = H (10) sues (1).
a0 + a1 s + · · · + an−1 sn−1 + an sn
Passive Realizations
For the case of n odd, we obtain
Passive realizations utilize capacitors, inductors, and resis-

n−1/2 tors. The source and load resistances are considered part of
(s2 + ωi2 ) the realization. Systematic procedures exist for the synthesis
H(s) = H
i=1
(11) of passive filters to realize elliptic transfer functions. More-
a0 + a1 s + · · · + an−1 sn−1 + an sn over, normalized passive filters are available as part of table
look-up approaches (5). Examples of passive elliptic filters are
Note that the even-order transfer function given by Eq. (10) depicted in Fig. 7.
has no zeros at infinity while the odd-order transfer function Even-order passive realizations synthesized from Eq. (10)
of Eq. (11) has a single zero at infinity. It may be convenient will have negative elements because they do not have at least
to have the denominator in the form of coefficients or in terms a zero at infinity. This problem can be solved by shifting the

Rs

+
...
Vs + Rload Vout
–
–

1 2 3 n–1 n

(a)

Figure 7. Typical nth-order low-pass passive

+
elliptic filters are realized with inductors and ...
capacitors, and include the source and load re- Vs + Rload Vout
–
sistances. The circuit in (a) is for the odd-order
–
case and has n capacitors and (n–1)/2 induc-
tors. The circuit in (b) is for the even-order 1 2 3 n–2 n–1 n
case and has (n–1) capacitors and n/2 in-
ductors. (b)

C3
R1 R3 R4
C1 C2
+
Vs – R2 C4
highest frequency zero to infinity. The resulting elliptic func-
tion filter function will have a double zero at infinity and the
passive filter realization will now have positive elements but
unequal terminating resistances. This even-order elliptic
transfer function is known as case B, while the original even-
order transfer function given by Eq. (10) is called case A.
Equal terminating resistances can be obtained by shifting the
first maximum to the origin. The resulting even-order elliptic
transfer function is known as case C (2,5). The new filter func-
tions will be of the forms given by Eq. (12) for case B and Eq.
(13) for case C.

n/2
(s2 + ωBi
2
) ance of an inductor. Active inductors may be also be realized
i=2
HB (s) = H
b0 + b1 s + · · · + bn−1 sn−1 + bn sn

n/2
(s2 + ωCi
2
) Another active filter based on a passive realization scales
i=2
HC (s) = H
c0 + c1 s + · · · + cn−1 sn−1 + cn sn
The magnitude response in the case B and case C filter func-
tions are now slightly modified from the original type A.
One may ask if the passive realizations may utilize only
discrete elements. At the time of this writing, there is consid-
erable interest in fabricating on-chip or on-package inductors
in integrated circuit (IC) design. If progress on these induc-
tors continues at today’s present rate, it is not inconceivable
that passive synthesis could become commonplace in inte-
grated filter design.
Active Realizations
Elliptic filters may be synthesized with active RC filters. A
typical design procedure starts with dividing the elliptic filter
function into second-order sections. If the order of the filter is
odd, there will be one first-order section as well. All second-
order sections consist of complex conjugate poles and a pair
of zeros. An active filter stage may be used to create each
second-order stage. The active filter stages composing the sec-
ond-order stages are notch filters that allow for 웆z of the notch
to be different from 웆0 of the complex pole pair (not all notch
filters do). Once the filter is chosen, coefficients of the filter
are equated with coefficients of the active filter second-order
section. An example of such a filter section is shown in Fig. 8.
ELLIPTIC FILTERS 59
R5
– Vout
+
R6
Figure 8. A typical second-order stage used as
part of an active RC realization consists of an
operational amplifier, resistors, and capacitors
and is basically an active RC notch filter.
Once second-order sections have been synthesized, they may
be cascaded together to form the entire circuit. If a first-order
stage is used for an odd-order filter, a simple RC filter may
be added on. The first-order stage may also include a voltage
buffer. Active realizations may also be constructed using
switched-capacitor circuits.
Another popular method of elliptic filter synthesis is to
synthesize an active filter based on a passive realization. Gen-
erally, these types of filters replace inductors in the passive
circuit with simulated inductors. One type of simulated induc-
tor is composed of an active RC circuit configured so that the
impedance of the circuit takes the form of the input imped-
by transconductors and capacitors. Filters using this type of
(12) active inductor are called gm –C filters. They represent the
current state of the art in high-frequency active integrated
filter design using CMOS technology.
(13) the R’s, C’s, and L’s of a passive configuration by 1/s. The
resulting circuit contains capacitors, D elements, and resis-
tors. The D element is a two-terminal device with an imped-
ance of K/s2. Although the device doesn’t exist as a passive
element, active circuits may be synthesized that achieve an
input impedance having this form.
Digital Realizations
Many of the techniques of digital filter synthesis are analo-
gous to those used in analog filters. In particular, one of the
most systematic approaches to recursive digital filter design
is to first find a transfer function that meets specifications in
the analog domain, and then port it over to the digital do-
main. The transformation takes the transfer function from
the s domain into the z domain. The variable z plays the same
role in digital design that s plays in the analog domain. Often,
pre-distortion is applied, to account for errors the frequency
response that can occur in the transformation. The reader is
encouraged to consult Ref. 6 for more information on digital
filtering.
FREQUENCY AND MAGNITUDE SCALING
Frequently, a normalized design is the first step in filter real-
ization. A frequency-normalized filter is designed for a pass-
60 ELLIPTIC FILTERS
band frequency of 1 rad/s. A typical normalized realization
has component values on the order of ohms, farads, and hen-
ries. The design is then frequency scaled so the frequency nor-
malized response is shifted into place. That is, the passband
and stopband frequencies are transformed from normalized
values to the design values. The procedure is performed by
finding the scaling constant, 웆p, and replacing s with s/웆p in
the circuit. This results in new values for the capacitances
and inductances, while the values for resistances remain un-
changed. In circuit circumstances it may be desirable to fre-
quency scale the normalized transfer function first and then
do the circuit synthesis.
Frequency scaling usually results in values for capacitors
and inductors that are close to practical, but still not practi-
cal. Moreover, the impedances of the resistors remain un-
changed. The next step in denormalizing a normalized real-
ization is to impedance scale. Impedance scaling amounts to
multiplying each impedance by a specified constant. The con-
stant is picked so after scaling, the components have reason-
able values. If all impedances are scaled by the same factor,
voltage transfer function remains the same. With good selec-
tion of the constant, practical values may be achieved.
HIGH-PASS ELLIPTIC FILTERS
The discussions in the preceding sections treat low-pass ellip-
tic filters. There is little difference when discussing the prop-
erties of the high-pass elliptic filter.
The first step in high-pass filter design is to normalize
the high-pass parameters to the parameters that describe the
normalized low-pass filter. The parameters that describe
the high-pass are identical to the low-pass filter. One differ-
ence is that 웆s ⬍ 웆p. In general, a low-pass filter transfer func-
tion may be transformed into a high-pass transfer function by
a s to 1/s transformation. This simply means that everywhere
s appears in the transfer function, 1/s is substituted.
Once the normalized low-pass elliptic transfer function has
been determined and a normalized circuit has been synthe-
sized, a low-pass to high-pass transformation is applied. This
means that everywhere in the circuit, s is replaced with 1/s.
This results in capacitors becoming inductors, and inductors
becoming capacitors. If, in an active RC circuit for example,
inductors are not desired, the circuit may be magnitude
scaled by 1/s. This results in the inductors becoming resistors
and the resistors becoming capacitors.
Alternatively, if a normalized low-pass elliptic function has
been determined, it is possible to apply the s to 1/s transform
on the transfer function, resulting in a normalized high-pass
elliptic transfer function. It is now possible to synthesize a
circuit directly from this transfer function.
BANDPASS ELLIPTIC FILTERS
Bandpass filters may be classified as wideband or nar-
rowband. A wideband bandpass filter seeks to allow a wide
range of frequencies to pass with equal magnitude scaling,
ideally. A narrowband filter seeks to allow only one frequency,
or a very small band of frequencies, to pass. One definition of
narrowband versus wideband filters is given by Ref. 1. This
particular definition states that if the ratio of the upper cutoff
frequency to the lower cutoff frequency is greater than one
octave, the filter is considered a wideband filter.
Synthesis of wideband bandpass filters may be performed
by a cascade of a high-pass filter and a low-pass filter. The
lower bound of the definition of wideband results in the sepa-
ration of the high-pass and low-pass filters being such that
there is minimal interaction between the filters. If the ratio
is smaller than one octave, the cutoff frequencies are too close
together and the filters interact and must be treated as one
filter. Narrowband filters require different synthesis tech-
niques.
Like the high-pass filter functions, bandpass filter func-
tions may be synthesized from low-pass filter functions. This
is done by performing the transformation


1 s2 + ω02
s= (14)
BW s
on a normalized low-pass filter function, where 웆0 is the cen-
ter frequency and BW is the bandwidth of the filter. This
transform may also be used in the design of wideband band-
pass filters.
BANDREJECT ELLIPTIC FILTERS
Like bandpass filters, bandreject filters may also be classified
as wideband or narrowband. A wideband bandreject filter
seeks to block a wide range of frequencies while allowing fre-
quencies outside that band to pass with ideally equal magni-
tude scaling. A narrowband bandreject filter seeks to block
only one frequency or a very small band of frequencies. Like
the definition of narrowband versus wideband bandpass filter
definition, Ref. 1 gives a definition for narrowband versus
wideband bandreject filters. The definition is identical to that
of the bandpass filter.
Synthesis of wideband bandreject filters may be performed
by a cascade of a high-pass filter and a low-pass filter. The
lower bound of the definition of wideband results in the sepa-
ration of the high-pass and low-pass filters being such that
there is minimal interaction between the filters. If the ratio
is smaller than one octave, the cutoff frequencies are too close
together and the filters interact and must be treated as one
filter. Narrowband filters require different synthesis tech-
niques.
Bandreject filters may also be synthesized from normalized
low-pass filter functions by performing a transform of


s
s = BW (15)
s2 + ω02
on a normalized low-pass filter, where 웆0 is the center fre-
quency and BW is the bandwidth of the filter. This transform
may also be used in the design of wideband bandpass filters.
SUMMARY
Elliptic filters are a class of filters used to shape the magni-
tude of an electric signal. They may be used in applications
for any of the standard magnitude processing filters. In com-
parisons to other available filters, the elliptic filter provides
the sharpest transition from the passband to the stopband for
 EMERGENCY POWER SUPPLY 61

a given order. The magnitude response is equiripple in the

passband and the stopband. The drawback of the elliptic fil-
ters is very poor phase characteristics in comparison to other
filter types. Furthermore, evaluation of elliptic filter parame-
ters is considerably more difficult than other filter approxima-
tion functions due to the use of elliptic sine functions and el-
liptic integrals.

BIBLIOGRAPHY

1. A. B. Williams, Electronic Filter Design Handbook, New York:

McGraw-Hill, 1981.
2. L. P. Huelsman and P. E. Allen, Introduction to the Theory and
Design of Active Filters, New York: McGraw-Hill, 1980.
3. R. W. Daniels, Approximation Methods for Electronic Filter De-
sign, New York: McGraw-Hill, 1974.
4. A. Budak, Passive and Active Network Analysis and Synthesis,
reissue, Prospect Heights, IL: Waveland Press, 1991.
5. A I. Zverev, Handbook of Filter Synthesis, New York: Wiley, 1967.
6. E. P. Cunningham, Digital Filtering: An Introduction, Boston:
Houghton Mifflin Company, 1992.

Reading List
W.-K. Chen (ed.), The Circuits and Filters Handbook, Boca Raton, FL:
CRC Press and IEEE Press, 1995.
C. S. Lindquist, Active Network Design with Signal Filtering Applica-
tions, Long Beach, CA: Steward & Sons, 1977.

KENNETH V. NOREN
University of Idaho

EMBEDDING METHODS. See HIGH DEFINITION TELE-

VISION.
EMC, TELEPHONE. See TELEPHONE INTERFERENCE.
FEEDBACK AMPLIFIERS
AMPLIFIERS, FEEDBACK
Feedback is the process of combining a portion of the out-
put of a system with the system input to achieve modified
performance characteristics. Found in a multitude of en-
gineering applications, the process has become the foun-
dation of several disciplines, such as feedback control sys-
tems, feedback receivers, feedback oscillators, and feedback
amplifiers. It has become particularly pervasive in ampli-
fier design since the advent of transistors that can provide
high gain cheaply but cannot provide stable gain.
Negative feedback was originally applied by Harold S.
Black in 1927 at Bell Labs to valve (vacuum tube) am-
plifiers to reduce distortion. In 1957 Black’s work was de-
scribed by Mervin Kelly, president of Bell Labs, as one of the
two inventions of broadest scope and significance in elec-
tronics and communications is the first half of the century.
Negative feedback is the process of mixing an inverted por-
tion of the output of a system with the input to alter system
performance characteristics. The process of negative feed-
back has become especially important in linear amplifier
design and is characterized by several significant benefits:

The gain of the amplifier is stabilized against vari-
ation in the characteristic parameters of the active
devices due to voltage or current supply changes, tem-
perature changes, or device degradation with age.
Similarly, amplifier gain is stabilized within a group
of amplifiers that have active devices with somewhat
different characteristic parameters.

Nonlinear signal distortion is reduced.

The frequency range over which there is constant lin-
ear amplification (the midband region) is increased.

The input and output impedance of the amplifier can
be selectively increased or decreased.
It is a rare occurrence when benefits come without a
price. In the case of negative feedback, the aforementioned
benefits are accompanied by two primary drawbacks:

The gain of the circuit is reduced. To regain the losses
due to feedback, additional amplification stages often
must be included in the system design. Complexity,
size, weight, and cost may be added to the final am-
plifier design.

There is a possibility for oscillation. Should oscillation
occur, the basic gain properties of the amplifier are
destroyed.
This article considers the benefits of negative feedback
for amplifier design. Basic definitions are followed by a gen-
eral discussion of the properties of a feedback system. Am-
plifiers are divided into four categories of feedback topology,
and the specific properties of each topological type are de-
rived. While the discussions must focus on circuit analysis
techniques, a clear understanding of feedback in general,
and effects of circuit topology in particular, is a necessity
J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright © 2007 John Wiley & Sons, Inc.
Figure 1. Basic negative feedback topology.
for good feedback amplifier design.
BASIC FEEDBACK CONCEPTS
Electronic amplifiers are fundamentally characterized by
four properties:

The gain of the amplifier. Gain is defined as the ratio
of the output signal to the input signal. Each signal
may be either a voltage signal or current signal.

The range of frequencies over which the gain is essen-
tially constant: This range of frequencies is identified
as the midband region. It is bounded by the frequen-
cies at which the output power is halved: the high and
low 3 dB frequencies.

The midband input impedance. Defined as the ratio
of input voltage to input current.

The midband output impedance. Defined as the
Thévenin impedance seen at the amplifier output ter-
minals.
The application of feedback to an amplifier alters each of
these fundamental properties.
The basic topology of a feedback amplifier is shown in
Fig. 1. An input signal, Xi , enters a summing (or mixing)
junction, symbolized by a circular symbol. At the summing
junction, the feedback signal, Xf , is subtracted from the
input signal and the resultant signal, Xδ , is passed on to a
linear amplifier, shown as a triangular symbol, of gain, A.
The output of the linear amplifier, Xo , forms the output of
the feedback system. The rectangular symbol indicates a
feedback network that samples the output signal, scales it
by a feedback factor, f, and passes it forward to the input
of the system. Each signal can take the form of either a
voltage or a current and ideally travels only in the direction
of the indicated arrows. Subtraction of the two inputs at the
summing junction is the key factor in negative feedback
systems.
Feedback systems can be mathematically modeled with
a set of simple relationships. The output, Xo , of the ampli-
fier is related to the input signal, Xδ , by a linear amplifica-
tion factor (gain), A, often called the forward or open-loop
gain:
Since the quantities Xo and Xδ can be either voltage or cur-
rent signals, the forward gain, A, can be a voltage gain,
a current gain, a transconductance, or a transresistance.
Voltage gain is the ratio of output voltage to input voltage:
Similarly, current gain relates output and input currents.
Transresistance implies the ratio of an output voltage to
2 Amplifiers, Feedback
an input current: Transconductance is the ratio of an out-
put current to an input voltage. The feedback signal, Xf (a
fraction of the output signal, Xo ), is then subtracted from
the input signal, Xi , to form the difference signal, Xδ .
where f is the feedback ratio defining the relationship be-
tween Xf and Xo :
As is the case with the amplifier gain, the feedback ratio,
f, is either a ratio of voltages, a ratio of currents, a transcon-
ductance, or a transresistance. The product fA, called the
loop gain, must be a positive, dimensionless quantity to
have stable negative feedback. Thus it is necessary, for neg-
ative feedback, that the mathematical sign of f be the same
as that of A within the midband region. The input–output
relationship for the overall feedback system can be derived
from Eqs. (1) and (2):
The overall gain of the system, including the effects of feed-
back, is then written as
The overall feedback amplifier gain, Af , has the same di-
mensions as the forward gain, A. Equation (5) has special
significance in the study of feedback systems and is typi-
cally identified as the basic feedback equation. The denom-
inator of the basic feedback equation is identified as the
return difference, D, but is also commonly referred to as
the amount of feedback:
The return difference, for negative feedback systems,
has magnitude larger than unity (in the midband fre-
quency region) and is often specified in decibels:
The return difference quantifies the reduction in gain due
to the addition of feedback to the system. It also plays a
significant role in quantifying changes in frequency band-
width and input and output impedance. Specifically, the
high and low 3 dB frequencies are increased and decreased,
respectively, by approximately a factor of D; and the input
and output impedances are increased or decreased by a
factor of D depending on the sampling and mixing circuit
topologies.
The derivation of the basic feedback equation is based
on two basic assumptions:

The reverse transmission through the amplifier is
negligible (a signal at the output produces essentially
no signal at the input) compared to the reverse trans-
mission through the feedback network.

The forward transmission (left to right in Fig. 1)
through the feedback network is negligible compared
to the forward transmission through the amplifier.
In most feedback amplifiers, the amplifier is an active
device with significant forward gain and near-zero reverse
gain: The feedback network is almost always a passive net-
work. Thus, in the forward direction, the large active gain
will exceed the passive attenuation significantly. Similarly,
in the reverse direction, the gain of the feedback network,
albeit typically small, is significantly greater than the near-
zero reverse gain of the amplifier. In almost every elec-
tronic application, the aforementioned requirements for
the use of the basic feedback equation are easily met by
the typical feedback amplifier.
ANALYSIS OF FEEDBACK AMPLIFIER PROPERTIES
The analysis and design of electronic amplifiers is typi-
cally a multistep process. Complete, analytic characteri-
zation of an amplifier is a complex process whose results
are in a form that often masks the individual amplifier
properties. Amplifier designers therefore investigate the
amplifier gain, frequency response, and impedance proper-
ties separately, carefully balancing system requirements to
converge on a successful design. In addition to simplifying
the process, separate investigation of the amplifier proper-
ties often leads to greater insight into design improvement.
When a successful design is apparent, final fine-tuning is
accomplished with the aid of a computerized circuit sim-
ulator [i.e., System Program with Integrated Circuit Em-
phasis (SPICE)] and a breadboard prototype.
Essentially all of the drawbacks and benefits of feedback
systems can be investigated on a simple level by looking at
the properties of the basic feedback equation [Eq. (5)]. Gain
stabilization, the reduction in nonlinear signal distortion,
the increase in the frequency range over which there is lin-
ear amplification, the reduction in gain, and the possibil-
ity of oscillation all can be investigated on a simple level.
The change in the input and output impedances cannot
be investigated at this level: It is necessary to specify the
nature (voltage or current) of the input and output quanti-
ties and the circuit topology to investigate these impedance
changes.
Amplifier Gain
In the section on basic feedback concepts, it was shown
that feedback reduces amplifier gain by a factor of the re-
turn difference, D. While reduction of gain can be a signifi-
cant drawback, the ancillary gains are significant. Primary
among those benefits is the stabilization of the amplifier
gain against variation in the characteristic parameters of
the active devices. It is well known that the forward gain,
A, of an electronic amplifier is highly dependent on the pa-
rameters of the active devices contained within that ampli-
fier. These parameters are typically dependent on temper-
ature, bias conditions, and manufacturing tolerances. To
maintain consistent amplifier performance, it is desirable
to design amplifiers that are reasonably insensitive to the
variation of the device parameters.
The relationship between the differential change in gain
due to device parameter variation with and without feed-

back is obtained by differentiating Eq. (5):
Stable negative feedback amplifiers require that the return
difference have magnitude greater than unity:
Thus the absolute variation in gain is reduced by a factor
of the return ratio squared. Another measure of the change
in gain variation can be found by regrouping terms.
The factors in this equation more realistically describe the
benefits: Equation (10) demonstrates the change in the per-
centage of gain variation about the nominal value. It can
be seen that the percentage variation of the overall ampli-
fier gain, Af , is reduced by a factor of the return ratio when
compared to the percentage variation of the gain, A, of the
forward amplifier.
For example, a feedback amplifier is constructed with
an amplifier that is subject to a 3% variation in gain as its
fundamental forward-gain element and it is desired that
the feedback amplifier have no more than 0.1% variation
in its overall gain due to the variation in this element. The
necessary return difference to achieve this design goal can
be obtained as follows: Equation (10) is the significant re-
lationship in determining the gain variation:
The significant properties are
The minimum necessary return ratio is 30, more often iden-
tified as its decibel equivalent,
Equation (10) is extremely useful for small changes in am-
plification due to parameter variation but is inaccurate for
large changes. If the change in amplification is large, the
mathematical process must involve differences rather than
differentials:
To put this into the same format as Eq. (10), it is necessary
to divide both sides of the equation by A1f .
or
Amplifiers, Feedback 3
The results are similarly a reduction in gain sensitivity by
a factor of the form of the return difference.
The differential change in feedback amplifier gain due
to variation in the feedback ratio, f, can be obtained by dif-
ferentiating Eq. (5) with respect to the feedback ratio. Ap-
propriate mathematical manipulation leads to the desired
results:
It is easily seen that the percentage variation of the over-
all amplifier gain Af is approximately the same magnitude
(actually slightly smaller) than the percentage variation of
the feedback ratio, f. Since electronic feedback amplifiers
typically employ a feedback network constructed entirely
with passive elements (usually resistors), variation in the
feedback ratio can be kept relatively small through the uti-
lization of precision elements in the feedback network. In
good amplifier designs, the variation of amplifier gain due
to variability in the feedback network is usually of lesser
significance than that due to variability of the basic for-
ward amplifier gain.
Nonlinear Signal Distortion
Stabilization of gain with parameter variation suggests
that amplifier gain will be stabilized with respect to other
gain-changing effects. One such effect is nonlinear distor-
tion. Nonlinear distortion is a variation of the gain with
respect to input signal amplitude. A simple example of
nonlinear distortion is demonstrated in Fig. 2, in which
the transfer characteristic of a simple amplifier is approx-
imated by two regions, each of which is characterized by
different amplification, A1 and A2 . To this transfer charac-
teristic, a small amount of feedback is applied so that fA1
= 1, and the resultant feedback transfer characteristic is
shown. As can be seen easily, the overall feedback trans-
fer characteristic also consists of two regions with overall
amplification A1f and A2f . In this demonstration, the am-
plification ratios are:
Feedback has significantly improved the linearity of the
system and consequently has reduced the nonlinear distor-
tion. Larger amounts of feedback (increasing the feedback
ratio, f) will continue to improve the linearity. For this ex-
ample, increasing the feedback ratio by a factor of 5 will
result in a ratio of overall gain in the two regions of 1.067
(as compared to 1.5 previously). The saturation level of an
amplifier is not significantly altered by the introduction of
negative feedback. Since the incremental gain in satura-
tion is essentially zero, the incremental feedback difference
is also zero. No significant change to the input occurs and
the output remains saturated.
Another viewpoint on gain stabilization comes from a
limiting form of the basic feedback equation:
4 Amplifiers, Feedback
Figure 2. The effect on feedback on an amplifier transfer char-
acteristic.
For large return difference (D = 1 + Af) the overall gain
with feedback is dominated by the feedback ratio, f, and
therefore virtually independent of the forward gain, A, and
any variations in A.
Frequency Response
Typical linear amplifiers have a range of frequencies over
which the gain is essentially constant: This frequency
range is called the midband. As frequencies increase, the
performance parameters of an amplifier degrade. Simi-
larly, coupling and bypass capacitors internal to the am-
plifier, when present, will degrade low-frequency perfor-
mance. Using feedback to broaden of the frequency range
over which gain is relatively constant can be considered
a special case of the stabilization of gain due to variation
in amplifier performance characteristics. Feedback reduces
the effects of these frequency-dependent degradations and
thereby increases the frequency band over which the am-
plifier has stable gain.
A more exact description of the increase in the width of
the midband region can be obtained through a frequency-
domain analysis. It is common practice to use the frequen-
cies at which the output power is reduced by 50% (the high
and low 3 dB frequencies) as descriptors of the limits of the
midband region. Discussion focuses on the change in these
3 dB frequencies.
It can be shown that the basic forward amplifier gain,
A, is described as the midband gain, A0 , divided by a poly-
nomial in frequency (written as s or jω):
The locations of the first few poles of A(s) [or the zeroes of
P(s)] closest to the midband region are the dominant pre-
dictors of amplifier frequency response: Specifically, their
location controls the 3 dB frequencies.
The application of feedback to an amplifier alters the
gain expression through the basic feedback equation so
that the total gain, Af , is described by
Figure 3. Pole migration due to feedback.
The application of feedback to the basic forward amplifier
has the effect of vertically shifting the denominator polyno-
mial by a constant, fA0 (see Fig. 3). This shift upward causes
movement in the zeroes of the denominator, thereby chang-
ing the location of the poles of the frequency response. Any
movement of the poles nearest the region of constant gain
(the midband region) equates into a change in the width
of the midband region. Observation of the consequences of
the result in graphical format is a great aid to understand-
ing pole migration.
For example, when the high-frequency response is de-
scribed by a single pole p1 , Eq. (21) takes the form
It can be seen easily that the gain has been reduced by a
factor of the return difference, D, and the pole frequency
has been increased by the same factor. Similarly, if the low-
frequency response is described by a single pole, pL1 , the
pole frequency will be reduced (that is, divided by) by a
factor of D. Since, in single-pole systems, the 3 dB frequency
coincides with the pole frequencies, the high and low 3 dB
frequencies, ωH and ωL , are shifted by a factor of the return
ratio:
As the number of poles increases, description of the
bandwidth increases with the application of feedback in-
creases in complexity. When the high or low frequency re-
sponse can be described by two poles, the damping coeffi-
cient due to the application of feedback is function ratio of
the initial pole locations, k, and the return difference. The
damping coefficient can be calculated to be:
1+k 1+k
ζ=
= √ (19)
2 k(1 + f Ao ) 2 kD
where the k is defined as the ratio of the larger pole to the
smaller pole:
ω2H ω1L
kH = or kL = (20)
ω1H ω2L

This simple expression for the damping coefficient is a
particularly important result in that it can tell the circuit
designer the flatness of the frequency response in rela-
tion to the amount of feedback applied: a flat frequency
response requires critically or overdamped pole pairs (ζ ≥
0.707).
Once the damping coefficient is determined, the expres-
sion for the high or low 3 dB frequency shift with the ap-
plication of feedback takes a form similar to the single pole
case with an additional factor:
ω1L
ωH f = K(ζH , kH ) · D · ω1H or ωL f = , (21)
K(ζL , kL ) · D
where k is the ratio of the initial pole spacing (k ≥ 1), ζ is
the pole-pair damping coefficient, ω1H and ω1L are the poles
closest to the midband, and the factor, K(ζ, k), is given by:


2k ζ
K(ζ, k) = 1 − 2ζ 2 + (1 − 2ζ 2 )2 + 1
k+1
This relationship is shown in Fig. 4 for a variety of initial
√ ratios, k. In most amplifier applications, 0.9 <
pole spacing
K(ζ, k) < 2: some designers use a K(ζ, k) ≈ 1 as a first-
order approximation.
For amplifiers where the frequency response must be
described by more than two poles, the description of the
frequency shift is even more complicated. Fortunately, am-
plifiers with a high- or low-frequency response that is de-
scribed by more than two poles are reasonably modeled
by considering them to be two-pole systems (1). Equation
(26) adequately approximates the change in bandwidth for
these higher-order systems.
For example, an amplifier has a midband gain, A0 =
1000 and has frequency response described by one low-
frequency pole, fL = 10, and two high-frequency poles, fH1 =
10 kHz and fH2 = 100 kHz, and feedback is applied so that
the midband gain is reduced to A0f = 140. The new low and
high 3 dB frequencies can be determined as follows: The
return difference is the ratio of the two gains:
The low-frequency response is described by a single pole;
thus the low 3 dB frequency is changed by a factor of D:
The high-frequency response is described by two poles with
ratio, k.
ω2H f2H 10 MHz
k= = = = 10.
ω1H f1H 1 MHz
The damping coefficient for the two poles are found to be:
1+k 1 + 10
ζH =
= √ = 0.6508
2 k(1 + f Ao ) 2 10(7.14286)
Notice that the high poles of the feedback amplifier are
slightly underdamped and that there will be a small
“bump” (≈ 0.1 dB) in the frequency response as a result.
The high 3 dB frequency, fHf , is then found from K(ζ H , k),
Amplifiers, Feedback 5
D, and fl :
fHf = K(ζH , k)D f1 = (1.277)(7.4286)(1 MHz) = 9.12 MHz
The resultant frequency response plots are shown in Fig
5.
Input and Output Impedance
The input and output impedance of a feedback amplifier
can be selectively increased or decreased through the ap-
plication of feedback. As has been seen in the previous
sections, general discussions provide great insight into
many of the properties of feedback systems. To consider
the design of electronic feedback amplifiers, it is necessary,
however, to specify the details of the feedback sampling
and mixing processes and the circuits necessary to accom-
plish these operations. The sampling and mixing processes
have a profound effect on the input impedance, the output
(22) impedance, and the definition of the forward-gain quan-
tity that undergoes quantified change due to the applica-
tion of feedback. This subsection analyzes the various ide-
alized feedback configurations. The following section looks
at practical feedback configurations.
The mixing and the sampling processes for a feedback
amplifier utilize either voltages or currents. Voltage mixing
(subtraction) implies a series connection of voltages at the
input of the amplifier: Current mixing implies a shunt con-
nection. Voltage sampling implies a shunt connection of the
sampling probes across the output voltage: Current sam-
pling implies a series connection so that the output current
flows into the sampling network. Either type of mixing can
be combined with either type of sampling. Thus, a feedback
amplifier may have one of four possible combinations of the
mixing and sampling processes. These four combinations
are commonly identified by a hyphenated term: (mixing
topology)–(sampling topology). The four types are as fol-
lows:

Shunt–shunt feedback (current mixing and voltage
sampling)

Shunt–series feedback (current mixing and current
sampling)

Series–shunt feedback (voltage mixing and voltage
sampling)

Series–series feedback (voltage mixing and current
sampling)
The four basic feedback amplifier topologies are shown
schematically in Fig. 6. A source and a load resistance have
been attached to model complete operation. In each dia-
gram the input, feedback, and output quantities are shown
properly as voltages or currents. Forward gain, A, must be
defined as the ratio of the output sampled quantity divided
by the input quantity that undergoes mixing. As such it is a
transresistance, current gain, voltage gain, or transconduc-
tance. The feedback network, as described by the feedback
ratio (f), must sample the output quantity and present a
quantity to the mixer that is of the same type (current or
voltage) as the input quantity. As such it is a transconduc-
tance, current gain, voltage gain, or transresistance. Table
1 lists the appropriate quantities mixed at the input, the
6 Amplifiers, Feedback

Figure 4. High 3 dB frequency as a function of ζ and nonfeed-

back pole spacing.

Figure 5. An example of the effect of feedback on frequency re-

sponse.

output sampled quantity, the forward gain, and the feed-

back ratio for each of the four feedback amplifier topologies.
It is important to remember that the product, fA, must be
dimensionless and, in the midband region of operation, pos-
itive.
In the previous section, all benefits of feedback were
discussed except the modification of input and output
impedance. The specific definitions of the four feedback am-
plifier topologies allow for that discussion to begin here.
The mixing process alters the input impedance of a neg- Figure 7. Input and output resistance for shunt–shunt feedback.
ative feedback amplifier. Heuristically, one can see that
subtraction of a feedback quantity at the mixing junction
increases the input quantity necessary for similar perfor- Therefore, combining Eqs. (32) and (33) yields
mance. Thus, subtracting current (shunt mixing) requires
an increase in overall input current and decreases the in-
put impedance. Similarly, subtracting voltage (series mix-
ing) requires an increase in overall input voltage and in-
creases input impedance. The input resistance to feedback amplifier is the input re-
sistance of the forward-gain amplifier reduced by a factor
Shunt Mixing Decreases the Input Resistance. For the of the return difference. Shunt–series feedback amplifier
shunt–shunt feedback amplifier (Fig. 7), the voltage across input resistance is similarly derived (replacing RM by AI ).
its input terminals (arbitrarily identified as v) and the in- The same basic reduction in input resistance occurs:
put current, ii , are related by the feedback amplifier input
resistance, Rif :

Similarly, the forward-gain amplifier has input quantities

related by its input impedance, Ri :
The two input currents, ii and iδ , are related through the
forward gain and the feedback ratio:
Series Mixing Increases Input Resistance. For the
series–series feedback amplifier of Fig. 8, the voltage
across its input terminals, vi , and the input current
(arbitrarily identified as i) are related by the feedback
amplifier input resistance, Rif :

Figure 8. Input and output resistance for series–series feedback.
Similarly, the forward-gain amplifier has input quantities
related by its input impedance, Ri :
The two input voltages, vi and vδ , are related through the
forward gain and the feedback ratio:
Therefore, combining Eqs. (37) and (38) yields
The input resistance to feedback amplifier is the input re-
sistance of the forward-gain amplifier increased by a factor
of the return difference. Series–shunt feedback amplifier
input resistance is similarly derived (replacing GM by AV ).
The same basic reduction in input resistance occurs:
Amplifiers, Feedback 7
Figure 6. Feedback amplifier topologies.
(a) Shunt–shunt feedback. (b) Shunt–series
feedback. (c) Series–shunt feedback. (d)
Series–series feedback.
Resistors shunting the input, such as biasing resistors,
often do not fit within the topological standards of series
mixing. Thus, they must be considered separate from the
feedback amplifier to model feedback amplifier character-
istics properly using the techniques outlined in this and
other articles. Examples of such resistors are found in the
next section of this article.
The sampling process alters the output impedance of the
feedback amplifier. As was the case for shunt mixing, shunt
sampling decreases the output resistance: Series sampling
increases the output resistance.
Shunt Sampling Decreases the Output Resistance. For the
shunt–shunt feedback amplifier of Fig. 7, the output resis-
tance is measured by applying a voltage source of value,
v, to the output terminals with the input, ii , set to zero
value. A simplified schematic representation of that mea-
surement is shown in Fig. 9. In this figure, the forward-
gain amplifier has been shown with its appropriate gain
parameter, RM , and output resistance, Ro .
The output resistance of the feedback system is the ra-
tio,
The current, i, is calculated from Ohm’s law at the output
of the amplifier:
8 Amplifiers, Feedback
Figure 9. Schematic representation of shunt–shunt feedback for
output resistance calculations.
Figure 10. Schematic representation of series–series feedback
for output resistance calculations.
In the case where the input current has been set to zero,
Combining Eqs. (43) and (44) yields
The output resistance of the feedback amplifier is the out-
put resistance of the forward-gain amplifier decreased by a
factor of the return difference. Series–shunt feedback am-
plifier output resistance is similarly derived (replacing RM
by AV ). The same basic reduction in input resistance occurs:
Resistors that shunt the output terminals, such as a load
resistor, are considered as part of the feedback amplifier.
The forward-gain parameter (RM or AV ) must be calculated
in a consistent fashion with the consideration of these ele-
ments.
Series Sampling Increases the Output Resistance. For the
series–series feedback amplifier of Fig. 8, the output resis-
tance is measured by applying a current source of value,
i, to the output terminals with the input, vi , set to zero
value. A simplified schematic representation of that mea-
surement is shown in Fig. 10. In this figure, the forward-
gain amplifier has been shown with its appropriate gain
parameter, AV , and output resistance, Ro .
The output resistance of the feedback system is the ratio
The voltage, v, is given by
Since the input voltage, vi , has been set to zero value,
Combining Eqs. (48) and (49) yields
The output resistance is then given by
The output resistance of the feedback amplifier is the out-
put resistance of the forward-gain amplifier increased by a
factor of the return difference. Shunt–series feedback am-
plifier output resistance is similarly derived (replacing GM
by AI ). The same basic increase in input resistance occurs:
Resistances shunting the output, such as load resis-
tances, do not fit within the topological standards of series
sampling. Thus, they must be considered separate from the
feedback amplifier to model feedback amplifier character-
istics properly using the techniques outlined in this and
other articles. The forward-gain parameters, AI and GM ,
must be calculated excluding these resistances.
PRACTICAL FEEDBACK CONFIGURATIONS
Previous discussions of feedback and feedback configura-
tions have been limited to idealized systems and amplifiers.
The four idealized feedback schematic diagrams of Fig. 6
identify the forward-gain amplifier and the feedback net-
work as two-port networks with a very specific property:
Each is a device with one-way gain. Realistic electronic
feedback amplifiers can only approximate that idealized
behavior. In addition, in practical feedback amplifiers there
is always some interaction between the forward-gain am-
plifier and the feedback network. This interaction most of-
ten takes the form of input and output resistive loading
of the forward-gain amplifier. The division of the practical
feedback amplifier into its forward-gain amplifier and feed-
back network is also not always obvious. These apparent
obstacles to using idealized feedback analysis can be re-
solved through the use of two-port network relationships
in the derivation of practical feedback amplifier proper-
ties. Once amplifier gain and impedance relationships have
been derived, the utility of the two-port representations be-
comes minimal and is typically discarded.
Identification of the Feedback Topology
Feedback topology is determined through careful observa-
tion of the interconnection of the feedback network and

forward-gain amplifier. Shunt mixing occurs at the input
terminal of the amplifier. Thus, shunt mixing is identified
by a connection of feedback network and the forward-gain
amplifier at the input terminal of first active device within
the amplifier; that is,

At the base of a BJT for a common-emitter or common-
collector first stage

At the emitter of a BJT for a common-base first stage

At the gate of a FET for a common-source or common-
drain first stage, or

At the source of a FET for a common-gate first stage
Series mixing occurs in a loop that contains the input
terminal of the forward-gain amplifier and the controlling
port of the first active device. The controlling port of a BJT
in the forward-active region is the base-emitter junction:
A FET in the saturation region is controlled by the voltage
across the gate-source input port. Series mixing is charac-
terized by a circuit element or network that is both con-
nected to the output and in series with the input voltage
and the input port of the first active device.
Identification of the sampling is derived from direct ob-
servation of the connection of the output of the basic for-
ward amplifier and the feedback network. Shunt sampling
is typically characterized by a direct connection of the feed-
back network to the output node: Series sampling implies a
series connection of the amplifier output, the feedback net-
work, and the load. Two tests performed at the feedback
amplifier output can aid in the determination of sampling
topology:

If the feedback quantity vanishes for a short-circuit
load, the output voltage must be the sampled quantity.
Thus, zero feedback for a short-circuit load implies
shunt sampling.

If the feedback quantity vanishes for an open-circuit
load, the output current must be the sampled quan-
tity. Thus, zero feedback for an open-circuit load im-
plies series sampling.
After the topological type has been identified, each am-
plifier must be transformed into a form that allows for
the use of the idealized feedback formulations. This trans-
formation includes modeling the amplifier and the feed-
back network with a particular two-port representation
that facilitates combination of elements. Once the transfor-
mations are accomplished, the amplifier performance pa-
rameters are easily obtained using the methods previously
outlined. The particular operations necessary to transform
each of the four feedback amplifier topological types re-
quire separate discussion. Only the shunt–shunt topology
is discussed in detail: The other three topologies use simi-
lar techniques that lead to the results shown in Fig. 13 and
described in Table 2.
Shunt–Shunt Feedback: a Detailed Derivation. Figure
11 is a small-signal model representation of a typical
shunt–shunt feedback amplifier. In this representation,
the forward-gain amplifier and the feedback network have
Amplifiers, Feedback 9
been replaced by their equivalent y-parameter two-port
network representations so that parallel parameters can
be easily combined. A resistive load has been applied to
the output port; and, since shunt–shunt feedback ampli-
fiers are transresistance amplifiers, a Norton equivalent
source has been shown as the input. The forward-gain pa-
rameter of each two-port, y21 , is the transadmittance.
The basic feedback equation for a transresistance am-
plifier takes the form:
The application of the basic feedback equation to this cir-
cuit in its current form is not immediately clear. It is nec-
essary to transform the feedback amplifier circuit into a
form that allows for easy application of the basic feedback
equation, Eq. (53). Such a transformation must meet the
previously stated feedback requirements:

The forward-gain amplifier is to be a forward trans-
mission system only—its reverse transmission must
be negligible.

The feedback network is to be a reverse transmission
system that presents a feedback current, dependent
on the output voltage, to the amplifier input port.
While a mathematically rigorous derivation of the trans-
formation is possible, greater insight to the process comes
with a heuristic approach.
The two-port y-parameter representation, in conjunc-
tion with the shunt-shunt connection, is used to describe
the two main elements of this feedback amplifier so that
all the input port elements of both two-port networks are
in parallel. Similarly, all output port elements are in par-
allel. It is well known that circuit elements in parallel may
be rearranged and, as long as they remain in parallel, the
circuit continues to function in an identical fashion. Hence,
it is possible, for analysis purposes only, to move elements
conceptually from one section of the circuit into another
(from the feedback circuit to the amplifier circuit or the
reverse). The necessary conceptual changes made for the
transformation are as follows:

The source resistance, the load resistance, and all in-
put and output admittances, y11 and y22 , are placed
in the modified amplifier circuit. While inclusion of
the source and load resistance in the amplifier seems,
at first, counterproductive, it is necessary to include
these resistances so that the use of the feedback prop-
erties produces correct results for input and output
resistance (after appropriate transformations).

All forward transadmittances, y21 (represented by cur-
rent sources dependent on the input voltage, v1 ), are
placed in the modified amplifier circuit.

All reverse transadmittances, y12 (represented by cur-
rent sources dependent on the output voltage, vo ), are
placed in the modified feedback circuit.
10 Amplifiers, Feedback
Figure 11. Two-port realization of a shunt–shunt feedback ampli-
fier.
The dependent current source can be easily combined:
and
In virtually every practical feedback amplifier, the re-
verse transadmittance of the forward-gain amplifier is
much smaller than that of the feedback network (y12 a <
y12 f ) and the forward transadmittance of the feedback net-
work is much smaller than that of the forward-gain ampli-
fier (y21 f < y21 a ). Thus approximate simplifications of the
amplifier representation can be made:
and
The shunt–shunt feedback amplifier circuit of Fig. 11 is,
with these changes and approximations, thereby trans-
formed into the circuit shown in Fig. 12.
This transformed circuit is composed of two simple ele-
ments:

The original amplifier, with its input shunted by the
source resistance; the feedback network short-circuit
input admittance, y11 f , and its output shunted by the
load resistance; the feedback network short-circuit
output admittance, y22 f

A feedback network composed solely of the feedback
network reverse transadmittance, y12 f
It is also important to notice that the input resistance, Rif ,
of this circuit includes the source resistance, Rs . As such,
it is not the same as the input resistance of the true ampli-
fier, Rin . The input resistance of the true amplifier can be
obtained as
Similarly, the output resistance, Rof , of this circuit includes
the load resistance, RL : Similar operations may be neces-
sary to obtain the true output resistance of the amplifier.
The y-parameters of the feedback network can be ob-
tained:
where i2 is the current entering the output port of the feed-
back network (see Fig. 10). With the determination of these
two-port parameters, the circuit has been transformed into
a form that is compatible with all previous discussions. The
forward-gain parameter (in this case, GM ) of the loaded ba-
sic amplifier must be calculated, while the feedback ratio
has been determined from the two-port analysis of the feed-
back network:

In the case of totally resistive feedback networks, the
shunting resistances can be found in a simple fashion:

rin = (yf )−1 is found by setting the output voltage to
11
zero value, vo = 0, and determining the resistance from
the input port of the feedback network to ground.

rout = (yf )−1 is found by setting the input voltage to
22
zero value, vi = 0, and determining the resistance from
the output port of the feedback network to ground.
The feedback ratio, f, is simply the ratio of the feedback
current, if , to the output voltage when the input port of the
feedback network, vi , is set to zero value. All idealized feed-
back methods can be applied to this transformed amplifier,
and all previously derived feedback results are valid.
The other three feedback amplifier topologies can be
similarly analyzed using various two-port parameters for
analysis:

Shunt–series—g parameters

Series–shunt—h parameters

Series–series—z parameters
Such analysis leads to a characterization of the loading of
the basic forward amplifier as is described in Fig. 13. As
is the case with the shunt–shunt topology, individual ele-
ments within the feedback network may appear more than
once in the loaded basic forward amplifier equivalent cir-
cuit. Table 2 summarizes the analysis of feedback amplifier
properties.
STABILITY IN FEEDBACK AMPLIFIERS
Under certain conditions, feedback amplifiers have the pos-
sibility of being unstable. This instability stems from the
frequency-dependent nature of the forward gain of the ba-
sic amplifier, A, and the feedback factor, f. The frequency
dependency is exhibited in the changes in magnitude and
phase of the product, fA, as a function of frequency.
Instability can be visualized by studying the basic feed-
back equation as a function of frequency:
Amplifiers, Feedback 11
Figure 12. Redistributed shunt–
shunt realization.
It is important that an amplifier be designed so that stabil-
ity is present at all frequencies, not only those in the mid-
band region. If the product −f(jω)A(jω) approaches unity
at any frequency, the denominator of Eq. (61) approaches
zero value: The total gain of the amplifier approaches infin-
ity. This condition represents an output that is truncated
only by power supply limitations regardless of input mag-
nitude and is an unstable condition that is intolerable in
amplifiers. To avoid this instability, it is necessary to avoid
a simultaneous approach of |f(jω)A(jω)| = 1 and ∠f(jω)A(jω)
= ±180◦ . Since each pole can only provide a phase shift of
between 0 and −90◦ , the second condition is only possible
for amplifiers that have high- or low-frequency responses
described by three or more poles. Simultaneously satisfy-
ing both conditions can be avoided if the magnitude of fA is
always less than unity when the phase angle of fA is ± 180◦ .
Designers of feedback amplifiers typically verify that this
is the case through the use of amplifier frequency-response
plots.
Gain Margin and Phase Margin
A frequency-response plot of the loop gain, fA, for a typi-
cal amplifier is shown in Fig 14. The frequency at which
|f(jω)A(jω)| = 1 is identified as ωm and the frequency at
which ∠f(jω)A(jω) = −180◦ is identified as ωp . Since ωm =
ωp , it is apparent that this is a stable amplifier—that is, the
two instability conditions are not simultaneously met. It is,
however, important to ensure that the two conditions are
not met simultaneously with a margin of safety. The mar-
gin of safety is defined by the gain margin and the phase
margin of the feedback amplifier.
Gain margin is defined as the difference in the loop gain
magnitude (in decibels) between 0 dB (unity gain) and the
loop gain magnitude at frequency ωp :
Phase margin is the difference between the loop gain phase
angle at frequency ωm and −180◦ :
Each safety margin is shown in Fig. 14. It is common
to specify the design of feedback amplifiers with gain
and phase margins greater than 10 dB and 50◦ , respec-
tively. These margins ensure stable amplifier operation
12 Amplifiers, Feedback
Figure 14. Gain margin and phase margin.
over component parameter variation, temperature change,
and other variations found in typical amplifiers.
Compensation
Two fundamental techniques are available for ensuring
amplifier stability:

Reducing the midband loop gain, fA, of the amplifier

Adding a compensation network to the amplifier to
shape the loop gain frequency response so that the
phase and gain margins are positive and in an ac-
ceptable range
Careful design is required in each of these cases to ensure
stable amplifier operation over typical performance condi-
tions.
In many cases, decreasing the loop gain to achieve sta-
bility is not an acceptable design possibility. Additionally,
as is often the case in operational amplifier circuits, the
feedback ratio, f, may be determined by the user rather
than the amplifier designer and can range widely. In such
cases, compensation networks are added within the feed-
back loop of the amplifier to increase the gain and phase
margins. Such compensation networks add poles or a com-
Figure 13. Feedback network loading of
basic forward amplifier. (a) Shunt–shunt
feedback. (b) Shunt–series feedback. (c)
Series–shunt feedback. (d) Series–series
feedback.
bination of poles and zeros to the loop gain characteristic.
The most commonly used compensation techniques are as
follows:

Dominant pole compensation

Lag–lead (pole–zero) compensation

Lead compensation
Each technique modifies the gain and phase profiles of the
basic forward amplifier through pole and zero manipula-
tion.
In dominant pole compensation, the amplifier is mod-
ified by adding a dominant pole that is much smaller in
magnitude than all other poles in the amplifier gain func-
tion: Typically it is chosen so that the loop gain, fA, reaches
0 dB at the frequency of the next pole (the first pole of the
uncompensated amplifier). Consequently, the modified loop
gain falls below 0 dB before the nondominant poles shift
the total phase shift near 180◦ and the circuit is inherently
stable. Dominant pole compensation will typically result in
a phase margin of approximately 45◦ .
The location of the new compensation pole can be de-
termined by modeling the loop gain response with a single
pole and setting its value to 0 dB at the first pole of the
uncompensated amplifier:
Solving Eq. (64) for the compensation pole frequency, ωc ,
results in:
If the design goals of the feedback amplifier includes a
range of feedback ratios, the frequency of the compensa-
tion pole is determined by the maximum value of the feed-

back ratio. That is, ωc is chosen to be the smallest value
predicted by Eq. (65).
An example of dominant pole compensation is shown
in Fig. 15 in the frequency domain. For clarity, the gain
plots are represented by straight-line Bode approxima-
tions, while the exact phase plots are retained. The exam-
ple amplifier is described by a midband gain of 60 dB with
poles at 1 MHz, 5 MHz, and 50 MHz: the feedback ratio is
f = 0.1.
The possibility of feedback amplifier instability is fo-
cused at the frequency where |fA| = 1 or equivalently where
|A|dB = −20 log(f). For this particular three-pole example,
instability may occur at ωm ≈ 21 MHz. Here the phase mar-
gin is very small and negative (≈ −7◦ ). After compensation,
the focus is again centered where the gain plot (now com-
pensated) intersects the negated feedback ratio plot. The
addition of the compensation pole, ωc , shifts this intersec-
tion to the frequency of the first uncompensated pole, ωp1 .
For this example, the compensation pole is placed at 10
kHz and yields a phase margin of ≈43◦ and a gain margin
of ≈14 dB.
Dominant pole compensation reduces the open-loop
bandwidth drastically. Still, it is common in many circuits
with inherently large gain: Operational amplifiers com-
monly utilize dominant pole compensation.
Lead–lag (or pole–zero) compensation is similar to dom-
inant pole compensation with one major exception. In ad-
dition to a dominant pole, a higher-frequency zero is added.
This zero is used to cancel the first pole of the uncompen-
sated amplifier. The added dominant pole can then be cho-
sen so that the gain reaches 0 dB at the frequency of the
next pole (the second pole of the uncompensated amplifier).
Lead–lag compensation has a distinct bandwidth advan-
tage over dominant pole compensation.
The location of the new compensation pole can be de-
termined in a similar fashion to the method utilized under
dominant pole compensation with the exception that the
loop gain (without the first original pole) is to reach 0 dB
at the second pole of the uncompensated amplifier. Solving
Eq. (64) for the compensation pole frequency, ωc , results in:
As with dominant pole compensation, design goals includ-
ing a range of feedback ratios lead to the determination of
frequency of the compensation pole by the maximum value
of the feedback ratio. That is, ωc is chosen to be the smallest
value predicted by Eq. (66).
The previously described, uncompensated amplifier is
compensated with a lag–lead pole–zero pair and the fre-
quency domain results are displayed in Fig. 16. The possi-
bility of feedback amplifier instability is again focused at
the intersection of the gain and the negated feedback ratio
plots. After compensation, the focus is centered where the
gain plot (now compensated) intersects the negated feed-
back ratio plot. The addition of the compensation pole, ωc ,
and a zero at the first uncompensated pole, ωp1 , shifts this
intersection to the frequency of the second uncompensated
pole, ωp2 . The previously identified amplifier parameters
lead to a compensation pole at 50 kHz, a positive phase
Amplifiers, Feedback 13
margin of ≈48◦ , and a gain margin of ≈20 dB.
Lead compensation can lead to the largest bandwidth
of the three most common compensation networks. Here,
as in lead–lag compensation, a pole and a zero are added.
The zero is used to cancel the second pole of the uncom-
pensated amplifier, and the added pole is positioned at a
frequency higher than the zero. The objective is to reduce
the phase shift of the uncompensated amplifier at the fre-
quency where the loop gain reaches 0 dB (ωm ). Lead com-
pensation can be extremely effective in feedback amplifiers
where there are two or three dominant poles in the uncom-
pensated amplifier.
The previously described, uncompensated amplifier is
compensated with a lead pole–zero pair and the frequency
domain results are displayed in Fig. 17. After compensa-
tion, the focus is again centered where the gain plot (now
compensated) intersects the negated feedback ratio plot.
The addition a zero at the second uncompensated pole, ωp2 ,
and a high-frequency compensation pole, ωc , shifts this in-
tersection a frequency beyond the second uncompensated
pole, ωp2 . For this example, the high-frequency pole was
chosen at 500 MHz. This design choice leads to a positive
phase margin of ≈35◦ and a gain margin of ≈15 dB. Notice
that with lead compensation there is no significant reduc-
tion in the frequency response of the feedback amplifier.
A passive component circuit implementation of each of
the three compensation techniques is schematically shown
in Fig. 18. For the circuit of Fig. 18(a), the compensation
network component values are chosen so that
where Ao , Ro , and ωp1 are the midband gain, the output re-
sistance, and the first pole frequency, of the basic forward
amplifier, respectively. For the circuit of Fig. 18(b), the com-
pensation network component values are chosen so that
and
For the circuit of Fig. 18(c), the compensation network com-
ponent values are chosen so that
and
While the placement of a compensation network at the
output of the basic forward amplifier is an effective tech-
nique for feedback topologies with shunt sampling, other
placement may be necessary. In particular, connections at
the output of a feedback amplifier with series sampling
are not within the feedback loop and are therefore invalid.
In such cases, alternate placement of the compensation is
14 Amplifiers, Feedback

Figure 15. Bode diagram for a dominant pole compensated am-

plifier.

Figure 16. Bode diagram for a lag–lead compensated amplifier.

Figure 17. Bode diagram for a lead compensated amplifier.

necessary. One common placement intersperses the com-

pensation network between individual gain stages of the
amplifier. Similarly, it is possible to compensate a feed-
back amplifier within the feedback network rather than
the basic forward amplifier. Unfortunately, analysis of com-
pensation within the feedback network is often extremely
complex due to the loading of the basic forward amplifier
by feedback network components.
 Amplifiers, Feedback 15

J. W. Nilsson and S. Riedel, Electric Circuits, 7th. Ed., Prentice

Hall, New York, 2004.
S. Rosenstark, Feedback Amplifier Principles, New York: Macmil-
lan, 1986.
A. S. Sedra, K. C. Smith, Microelectronic Circuits, 5th. Ed., Oxford
University Press, New York, 2004.
D. L. Schilling, C. Belove, Electronic Circuits, 3rd ed., New York:
McGraw-Hill, 1989.
T. F. Schubert, Jr. E. M. Kim, Active and Non-Linear Electronics,
New York: Wiley, 1996.
R. Spencer and M. Ghausi, Introduction to Electronic Circuit De-
sign, Prentice Hall, New York, 2003.

THOMAS F. SCHUBERT Jr.

University of San Diego, San
Diego, CA

Figure 18. Compensation networks. (a) Dominant pole compen-

sation. (b) Lag–lead (pole–zero) compensation. (c) Lead compen-
sation.

BIBLIOGRAPHY

1. T. F. Schubert, Jr. A heuristic approach to the development

of frequency response characteristics in the design of feed-
back amplifiers, Proc. 1996 ASEE/IEEE Frontiers Educ. Conf.,
November 1996, pp. 340–343.

Reading List

H. W. Bode, Network Analysis and Feedback Amplifier Design, D.

Van Nostrand Company, Princeton, NJ, 1945.
F. C. Fitchen, Transistor Circuit Analysis and Design, Princeton,
NJ: Van Nostrand, 1966.
M. S. Ghausi, Electronic Devices and Circuits: Discrete and Inte-
grated, New York: Holt Rinehart and Winston, 1985.
P. R. Gray, R. G. Meyer, Analysis and Design of Analog Integrated
Circuits, 4th. Ed., John Wiley & Sons, Inc., New York, 2001.
D. H. Horrocks, Feedback Circuits and Op Amps, London: Chap-
man and Hall, 1990.
P. J. Hurst, A comparison of two approaches to feedback circuit
analysis, IEEE Trans. Educ., 35: 253–261, 1992.
J. Millman, Microelectronics, Digital and Analog Circuits and Sys-
tems, New York: McGraw-Hill, 1979.
J. Millman, C. C. Halkias, Integrated Electronics: Analog and Dig-
ital Circuits and Systems, New York: McGraw-Hill, 1972.
 FIR FILTERS, DESIGN 555

There are many common applications of FIR filters, in-

cluding

1. Differentiators: These filters have many uses in digital

and analog systems, such as the demodulation of fre-
quency modulated (FM) signals (1–6).
2. Decimators and interpolators: FIR filters appear in
multirate systems as interpolator or decimator filters
forming filter banks. Interpolators and decimators can
be implemented, for instance, by comb filters, which are
a special class of multiband filters, commonly used in
the demodulation of video signals (1–6).
3. Power spectrum estimation: This process is used in digi-
tal speech, sonar, and radar systems. The moving aver-
age (MA) estimator is an example of an FIR filter (7).
4. Wiener and Kalman filters: These filters have been used
for the estimation of signals of interest, and they both
can be interpreted as extensions of FIR filters (8).
5. Adaptive filters: These systems have been widely used
in communication, control, and so on. Examples of this
type of system include adaptive antennas, digital equal-
ization receivers, adaptive noise-canceling systems, and
system modelers. Adaptive FIR filters are widely em-
ployed because the adaptation of the filter’s coefficients
searches for a unique optimal solution and does not
cause instability in the transfer function, which is not
always true for adaptive IIR filters (8–10).
6. Wavelets: The wavelet transform has been used as an
orthogonal basis for decomposing signals in multireso-
lution layers. In image processing, it has been used for
compressing the image data. In this setup, FIR filters
have been normally employed as the basis function of
the wavelet transform (11).

FIR FILTERS, DESIGN PROPERTIES OF FIR FILTERS

Filtering is a method of signal processing by which an input An FIR filter, with an input x(n) and output y(n), can be char-
signal is passed through a system in order to be modified, acterized by the following difference equation
reshaped, estimated, or generically manipulated as a way to
y(n) = a(0)x(n) + a(1)x(n − 1) + · · · + a(N − 1)x(n − N + 1)
make it conform to a prescribed specification. In a typical ap-
plication, filters are a class of signal-processing systems that

N−1
= a(i)x(n − i) (1)
let some portion of the input signal’s frequency spectrum pass
i=0
through with little distortion and almost entirely cutting off
the undesirable frequency band. Digital filtering is a method where N is the filter length, a(n) (for 0 ⱕ n ⱕ N ⫺ 1) are the
by which discrete time sequences are filtered by a discrete coefficients of the causal linear time-invariant system, and
system. the input and output samples are taken at a discrete time
Finite-duration impulse response (FIR) filters are a class t ⫽ nT, n ⫽ 0, 1, . . ., with T as the sampling period. From
of digital filters having a finite-length sequence as output Eq. (1), we notice that the present output sample y(n) is
when an impulse is applied to its input. The details of the formed by the combination of the present x(n) and the past
FIR filtering method, its properties, and its applications will N ⫺ 1 input samples weighted by the filter’s coefficients in
be considered in the following pages. Analytical tools that en- order attain some desired response.
able us to perform the time and frequency analysis of FIR Alternatively, Eq. (1) can be written as the convolution be-
filters will be examined and, in addition, systematic proce- tween the input signal samples x(n) and the impulse response
dures for the design of these filters will be presented. sequence h(n) of the filter (1–6), that is,
There are advantages and disadvantages in using FIR fil-
ters as opposed to infinite-duration impulse response (IIR)

N−1
y(n) = h(n − i)x(n)
filters. FIR filters are always stable when realized nonre-
i=0
cursively, and they can be designed with exact linear phase, (2)
which is not possible with IIR filters. However, the approxi-

N−1
= h(i)x(n − i)
mation of sharp cutoff filters may require a lengthy FIR filter, i=0
which may cause problems in the realization or implementa-
tion of the filter. Clearly, then, h(n) equals a(n), for 0 ⱕ n ⱕ N ⫺ 1.
J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.
556 FIR FILTERS, DESIGN

Stability ficients to process complex signals. Despite these cases, we

concentrate our efforts here on the analysis and design of FIR
A digital system is said to be bounded input–bounded output
filters with real coefficients, without much loss of generality.
(BIBO) stable if and only if any bounded discrete time se-
The interested reader, however, may refer to (12,13).
quence applied to the system’s input yields a bounded output
sequence. Therefore, the BIBO stability criterion can be writ-
ten as (1–6) Linear Phase
In many applications, the design of a signal processing sys-
If |x(n)| < ∞, ∀n, then | y(n)| < ∞, ∀n tem with linear phase is desirable. Nonlinear phase causes
distortion in the processed signal, which is very perceptible in
For an FIR filter as expressed in Eq. (2), we obtain applications like data transmission, image processing, and so
  on. One of the major advantages of using an FIR filter is that
N−1 

 it can be designed with an exact linear phase, a task that
| y(n)| =  h(i)x(n − i)
 i=0  cannot be done with IIR filters. A linear-phase system does
not cause any distortion, only delay.
By using the well known Schwartz’s inequality, we get The frequency response of an FIR filter, as described in Eq.
(4), is given by


N−1
| y(n)| ≤ |h(i)x(n − i)|

N−1
i=0 H(e jω ) = h(n)e− jωn (6)
n=0


N−1
≤ |h(i)||x(n − i)|
i=0 The magnitude M(웆) and phase ␪ (웆) responses of the filter
are respectively defined as
As the BIBO criterion imposes,
M(ω) = |H(e jω )|
|x(n)| ≤ M < ∞, ∀n
and
we thus have
θ (ω) = arg [H(e jω )]


N−1

|y(n)| ≤ M |h(i)| (3) Im[H(e jω )]
= tan−1
i=0 Re[H(e jω )]

Since the filter’s coefficients are assumed finite, the right- where Im(.) and Re(.) represent the imaginary and real parts
hand side of Eq. (3) is always finite and so is 兩y(n)兩. This im- of a complex number, respectively. The expression in Eq. (6)
plies that an FIR filter is always stable since the linear sys- can also be written as
tem coefficients are finite.
Alternatively, we can test filter stability by identifying its

N−1
poles. The stability of any digital filter can also be verified by H(e jω ) = h(n)[cos(ωn) − j sin(ωn)]
checking the poles of its transfer function. A necessary and n=0
sufficient condition for BIBO filter stability is that all system
poles are inside the unit circle (1–6). In the case of an FIR Now, by assuming that h(n) is a sequence of real numbers,
filter, its transfer function is obtained as the phase response is given by
 N−1 


N−1
− n=0 h(n) sin(ωn)
H(z) = h(n)z −n
(4) θ (ω) = tan−1 N−1 (7)
n=0 n=0 h(n) cos(ωn)

which can be written as To obtain a linear-phase response, ␪ (웆) is constrained to be

of the form
H(z) = h(0) + h(1)z−1 + · · · + h(N − 1)z−(N−1)
h(0)zN−1 + h(1)zN−2 + · · · + h(N − 1) (5) θ (ω) = −ωτ0 (8)
=
zN−1
for ⫺앟 ⱕ 웆 ⱕ 앟, where ␶0 is the constant delay of the filter.
From Eq. (5), we see that an FIR filter of length N has N ⫺ 1 When using the results of Eq. (7) and Eq. (8), we get
poles, all located at the origin of the z-plane, and therefore, it  N−1 
is always stable. As will be seen later, an FIR filter can be −1 − n=0 h(n) sin(ωn)
tan N−1 = −ωτ0
realized nonrecursively and recursively. The stability of an n=0 h(n) cos(ωn)
FIR filter is guaranteed only when the realization is nonre-
cursive since the quantization of filter coefficients in a re- which can be written as
cursive realization with finite precision arithmetic may
cause instability. N−1
h(n) sin(ωn)
In some applications, like speech, image coding, and signal tan(ωτ0 ) = N−1
n=0
(9)
transmission, it is possible to use FIR filters with complex coef- n=0 h(n) cos(ωn)
 FIR FILTERS, DESIGN 557

Eq. (9) admits two solutions. The first is a trivial one when Type III. Length N odd and symmetrical impulse response
␶0 ⫽ 0, which implies h(n) ⫽ 웃 (n); that is, the filter’s impulse Type IV. Length N odd and antisymmetrical impulse re-
response is an impulse at n ⫽ 0. This solution has very little sponse
utility. The second solution is when ␶0 ⬆ 0, and thus, Eq. (9)
can be expressed as Examples of these four types of linear-phase FIR filters are
depicted in Fig. 1. When N is even, see Fig. 1(a) and Fig. 1(b),
N−1 we notice that the axis of symmetry is located between two
sin(ωτ0 ) n=0 h(n) sin(ωn)
= N−1 samples; that is, the constant delay ␶0 is not an integer value.
cos(ωτ0 ) h(n) cos(ωn)
n=0 Meanwhile, if N is odd, ␶0 is integer, and thus, the location of
the axis of symmetry is over a sample, as observed in Fig.
Consequently, 1(c) and Fig. 1(d). For N odd and an antisymmetrical impulse
response filter, the middle sample must be zero to satisfy this


N−1
h(n)[sin(ωn) cos(ωτ0 ) − cos(ωn) sin(ωτ0 ) = 0 symmetry, as seen in Fig. 1(d).
n=0 In some applications, the long delay associated with linear-
phase FIR filters is not allowed and then a nonlinear-phase
and accordingly, filter is required. An example of such filter is the filter with
minimum-phase distortion, the zeros of which are located


N−1
strictly inside the Z-domain unit circle. This class of filters
h(n) sin(ωn − ωτ0 ) = 0 (10) can be designed by starting from Type I and III (even sym-
n=0
metric) linear-phase filters as mentioned, for instance, in
The solution of Eq. (10) can be shown to be the following set (12,14,15).
of conditions Frequency Response
N−1 The four types of FIR linear phase filters defined before have
τ0 = (11a)
distinct frequency responses, as we shall see below.
2
h(n) = ±h(N − n − 1) (11b)
Type I. From Eq. (6) and having that h(n) ⫽ h(N ⫺ n ⫺ 1),
we can write the frequency response as
It turns out that different solutions are obtained depending
on the value of N being either even or odd, and depending on

N/2−1

the two possibilities as expressed by Eq. (11b), that is, sym- H(e jω ) = h(n)[e− jωn + e− jω(N−n−1) ]
n=0
metrical (even symmetry) or antisymmetrical (odd symmetry)
filters. Therefore, from the set of conditions defined by Eq. which can be written in the form
(11), it is practical to define four types of linear-phase FIR


N/2−1

N −1


N −1−2n


N −1−2n

filters, namely: H(e jω ) = h(n)e− jω 2 e jω 2 + e− jω 2
n=0
Type I. Length N even and symmetrical impulse response


 N/2−1


N −1 N − 1 − 2n
Type II. Length N even and antisymmetrical impulse re- = e− jω 2 2h(n) cos ω
sponse n=0
2

h(n) Axis of h(n) Axis of

symmetry symmetry

5
n n
0 5 0

(a) (b)

h(n) Axis of h(n) Axis of

symmetry symmetry

6
n n
0 6 0
Figure 1. Typical impulse responses for linear-
phase FIR filters: (a) Type I: N even, symmetric fil-
ter; (b) Type II: N even, antisymmetric filter; (c)
Type III: N odd, symmetric filter; (d) Type IV: N
(c) (d) odd, antisymmetric filter.
558 FIR FILTERS, DESIGN

Finally, letting for n ⫽ 1, . . ., (N ⫺ 1)/2, and b(0) ⫽ h(N ⫺ 1/2), we get

N 


 (N−1)/2
a(n) = 2h ≈ −n H(e jω ) = e− jω
N −1
2 b(n) cos(ωn) (14)
2
n=0
for n ⫽ 1, . . ., N/2, the last summation in the above equation
can be written as which is the desired result.



N −1


 N−2 Type IV. For this case, the frequency response is similar to
1
H(e jω ) = e− jω 2 a(n) cos ω n − (12) Type III, except that in Eq. (14) instead of cosine summations,
n=1
2
we have, as before, sine summations multiplied by ej앟/2; that
which is the desired result, having a pure delay term and an is,
even-symmetric amplitude term.


(N−1)/2
N −1 π
H(e jω ) = e− jω 2 ej2 b(n) sin(ωn) (15)
Type II. For this case, the frequency response is similar to n=0
Type I above, except that in Eq. (12) instead of cosine summa-
tions we have sine summations multiplied by j or, equiva- In this specific case, b(0) ⫽ h(N ⫺ 1/2) ⫽ 0.
lently, multiplied by ej(앟/2). Hence, Eq. (12) should be replaced In Table 1, we summarize the properties of the four types
by of linear-phase FIR filters, as given in Eq. (12–15).



N/2

1
 Locations of Zeros
− jω N 2−1 j(π /2)
H(e jω
)= e e a(n) sin ω n− (13)
n=1
2 The locations of zeros in the Z-plane for a linear-phase FIR
filter is highly restricted by the set of conditions defined by
Type III. By applying the even symmetry condition to Eq. Eq. (11). When N is even, by applying these conditions to the
(6) with N odd, we obtain transfer function in Eq. (4), we obtain

N − 1

N −1


(N−3)/2


N/2−1
 
H(e jω ) = h ≈ e− jω 2 + h(n)e− jωn H(z) = h(n) z−n ± z−(N−n−1)
2

N − 1

n=0 n=0

=h≈ e − jω N 2−1

N/2−1

N −1


N −1−2n


N −1−2n

2 = h(n)z− 2 z 2 ± z− 2 (16)
n=0



 (N−3)/2


N −1−2n  N −1−2n 
N −1 N −1 N/2−1

+ e− jω 2 h(n)e− jωn e jω 2
h(n) z 2 ± z− 2
n=0
n=0 =

N −1

z 2
The above equation can be written as



N − 1 where the positive sign applies for symmetrical filters and the
− jω N 2−1 negative sign for antisymmetrical filters. Now, by examining
H(e ) = e
jω
h≈
2 the numerator of Eq. (16), that is, the zeros of the transfer



(N−3)/2
 jω
N −1 −n
 function, we see that if we replace z by z⫺1, we obtain the
− jω N 2−1 −n
+ h(n) e 2 +e same or the negative numerator, respectively, for symmetri-
n=0 cal and antisymmetrical filters. In both cases, the positions of
the zeros are similar. Therefore, if the transfer function has
where h(N ⫺ 1/2) is the middle sample of the filter’s impulse a zero at point z ⫽ ␳ ej␪, it will also have a zero at point
response. The above equation can also be expressed as z ⫽ (1/ ␳)e⫺j␪, where ␳ is the magnitude, and ␪ is the phase of


N −1


N − 1 the mentioned zero. In such a case, the numerator of H(z) is
H(e jω ) = e− jω 2 h≈ said to have the mirror-image zero property with respect to
2


(N−3)/2

N − 1  the unit circle.
Similarly, for N odd we obtain the following transfer func-
+ 2h(n) cos ω −n
n=0
2 tion

N − 1 (N−3)/2 
N −1−2n 

N −1−2n 

Now, when replacing the variable n by (N ⫺ 1)/2 ⫺ n, we h + n=0 h(n) z 2 ± z− 2
2
obtain H(z) =

N −1


N −1



N − 1 z 2
(17)
H(e jω ) = e− jω 2 h≈
2

N − 1   where, as before, the positive sign applies for symmetrical fil-


(N−1)/2
ters and the negative sign for antisymmetrical filters. Also, in
+ 2h ≈ − n cos(ωn)
n=1
2 this case, we see that the numerator of H(z) has the mirror-
image zero property.
Letting Hence, the locations of the zeros of all four types of linear-

N − 1  phase FIR filters have the mirror-image common property.
b(n) = 2h ≈ −n This implies that the locations of zeros have the following pos-
2 sibilities:
 FIR FILTERS, DESIGN 559

Table 1. Characteristics of Linear-Phase FIR Filters

Type N h(n) H(e j웆) Coefficients

I even symmetrical e ⫺j웆 (N⫺1/2)

冘 N/2
a(n) cos 웆 n ⫺
1
冋 冉 冊册 冦 a(n) ⫽ 2h 앒 冉 冊
N
2
⫺n
n⫽1 2
n ⫽ 1, . . ., N/2

II even antisymmetrical e ⫺j웆 (N⫺1/2)e J(앟/2) 冘 N/2

冋 冉 冊册
a(n) sin 웆 n ⫺
1
冦 a(n) ⫽ 2h 앒 冉 冊
N
2
⫺n
n⫽1 2
n ⫽ 1, . . ., N/2

冉
N⫺1
冊
冦
b(n) ⫽ 2h 앒 ⫺n
2
III odd symmetrical e ⫺j웆 (N⫺1/2)
冘 (N⫺1)/2
b(n) cos(웆n) n ⫽ 1, . . ., (N ⫺ 1)/2

冉 冊
n⫽0
N⫺1
b(0) ⫽ h 앒
2

冉
N⫺1
冊
冦
b(n) ⫽ 2h 앒 ⫺n
2
IV odd antisymmetrical e ⫺j웆 (N⫺1/2)e j(앟/2) 冘 (N⫺1)/2
b(n) sin(웆n) n ⫽ 1, . . ., (N ⫺ 1)/2

冉 冊
n⫽0
N⫺1
b(0) ⫽ h 앒 ⫽0
2

1. Complex zeros located off the unit circle appear as a set 6. A type II linear-phase FIR filter must have a zero at
of four conjugate reciprocal zeros of the form z ⫽ 1. Thus, low-pass filters cannot be designed with
this type of filter.
1 jθ 1
z11 = ρe jθ , z12 = ρe− jθ , z13 = e , z14 = e− jθ 7. A type IV linear-phase FIR filter must have zeros at
ρ ρ both z ⫽ 1 and z ⫽ ⫺1. Therefore, either low-pass or
high-pass filters cannot be designed with this type of
2. Complex zeros located on the unit circle appear as a set filter.
of conjugate pairs of the form
Figure 2 depicts a typical plot of the zeros of a linear-phase
− jθ FIR filter.
z21 = e , z22 = e
jθ

3. Real zeros off the unit circle appear as a set real pairs FIR FILTER DESIGN
of the form
The complete design of FIR filters involves three distinct
1 stages, namely approximation, realization, and implementa-
z31 = ρ, z32 =
ρ

or z-plane
z13
1 z21
z31 = −ρ, z32 = −
ρ
z11
4. Real zeros on the unit circle appear in an arbitrary
number z42 z31 z41 z32

z41 = 1
z12
or
z14
z22
z42 = −1

The locations of zeros at points z ⫽ ⫾1 have additional

importance. By examining the transfer function at
these points, it turns out that
5. A type I linear-phase FIR filter must have a zero at
z ⫽ ⫺1. Hence, high-pass filters cannot be designed
with this type of filter.
Figure 2. Example of the locations of zeros of a linear-phase FIR
filter: In this case, z11, z12, z13, and z14 are four complex-valued zeros
that satisfy rule 1; the pair of complex zeros on the unit circle z21 and
z22 obey rule 2; the pair of real zeros z31 and z32 satisfy rule 3; real
zeros on the unit circle, like z41 and z42, may appear in any number,
obeying rule 4.
560 FIR FILTERS, DESIGN

tion. Approximation is the process by which a required set of x(n)

filter specifications yields a suitable transfer function with z–1 z–1 ... z–1
the desired filter characteristics. The realization process
translates the transfer function obtained in the approxima-
tion stage into a digital network. Implementation is the pro- h0 h1 h2 ...
cess that transforms this digital network into a specific piece hN – 1
of hardware or software code. Because they are easier to un-
derstand this way, we now analyze these tasks in their re-
verse order. +

Implementation
y(n)
An FIR filter is a digital system, the implementation of which
can be accomplished by means of dedicated hardware, general Figure 3. Direct-form realization of an FIR filter. Its derivation is
purpose hardware (e.g., digital signal processors), or com- straightforward following Eq. (18).
puter programs. Both hardware and software forms are suit-
able for processing real-time and nonreal-time signals. Dedi-
cated-hardware filters, however, tend to be much faster, thus nal y(n). Due to the chain of delay elements on the top of that
being able to process signals with higher frequency compo- diagram, this structure is also referred to as the tapped delay
nents and/or using high-order filters. The manufacturing line or transversal filter.
stage of these filters, however, can be a very cost- and time-
expensive process. In the other extreme, computer programs Linear-Phase Direct Form. As seen before, FIR filters with
are mainly used, although not restricted, to filter signals in a linear phase present a symmetrical or antisymmetrical trans-
nonreal-time fashion or to simulate the performance of practi- fer function. This fact can be used to halve the number of
cal systems. Generally speaking, filters implemented with multiplications needed to realize the filter. In fact, the trans-
digital signal processors (DSPs) represent a good compromise fer function of linear-phase FIR filters with length N even can
of cost and processing speed compared to the other two alter- be written as
natives.
Currently, the two most well-known families of DSPs are

N/2−1
 
H(z) = hn z−n ± z−(N−n−1)
the TMS320 from Texas Instruments and the DSP56000 from n=0
Motorola. Both families have DSPs that use fixed- or floating-
point arithmetic, parallel processing, clock-rates from tens to leading to the structure shown in Fig. 4.
hundreds of MHz, and cost in the range of a few dollars to Meanwhile, the transfer function of linear-phase FIR fil-
several hundred dollars. Today, DSPs are becoming increas- ters with length N odd can be written as
ingly cheaper and faster, and this process shows no indication
of slowing down. For this reason, one can only predict this

(N−3)/2
 
N − 1 
N −1 
type of implementation for FIR digital filters becoming more H(z) = hn z−n ± z−(N−n−1) + h ≈ z 2
n=0
2
and more popular in the future.
and is suitable to be realized by the structure shown in Fig.
Realization
5. In both of these figures, the plus sign is associated to the
For any given transfer function, there is a wide variety of
network structures that are able to translate the mathemati-
cal aspect of the transfer function into an equivalent digital x(n)
circuit. In this section, we show some of the most commonly z–1 z–1 ...
used forms for realizing an FIR transfer function (1–6).
+ + ... + z–1
Direct Form. As given in Eq. (2), the transfer function of
FIR filters with length N assumes the form +/– +/– +/–

z–1 z–1 ...

N−1
−n
H(z) = hn z (18)
n=0
h0 h1 ... h(N –1)/2
where hn is the filter coefficient, corresponding to the filter’s
impulse response h(n), for 0 ⱕ n ⱕ N ⫺ 1. The change in
notation, in this section, from h(n) to hn, is important to avoid +
confusion with adaptive filters and to yield a more natural
representation of other realizations. The most natural way to
y(n)
perform the operations in Eq. (18) is probably the direct form
shown in Fig. 3. This figure clearly depicts how, in this real- Figure 4. Direct-form realization of a linear-phase FIR filter with N
ization, each delayed value of the input signal is appropri- even: Type I and Type II filters. The reader should verify reduction
ately weighted by the corresponding coefficient hn and how on the number of multiplications in the order of 50% when compared
the resulting products are added to compose the output sig- to the general direct-form realization seen in Fig. 3.
 FIR FILTERS, DESIGN 561

x(n)
z–1 z–1 ... z–1

+ + ... +
+/– +/– +/–
z–1 z–1 ... z–1

h0 h1 ... h(N –3)/2 h(N –1)/2

Figure 5. Direct-form realization of a linear-phase FIR filter

+ with N odd: Type III and Type IV filters. The reader should
verify reduction on the number of multiplications in the order
of 50% when compared to the general direct-form realization
y(n)
seen in Fig. 3.

symmetrical impulse response, and the minus sign is associ-
ated to the antisymmetrical case, as included in Table 1. It is
important to notice that the linear-phase direct forms shown
here preserve this important characteristic even when the
filter coefficients are quantized, that is, are represented with
a finite number of bits.
Cascade Form. Any FIR-filter transfer function can be fac-
tored into a product of second-order polynomials with real co-
efficients; that is,
To obtain a useful relation between the lattice parameters
and the filter’s impulse response, we must analyze the recur-
rent relationships that appear in Fig. 8. These equations are
ei (n) = ei−1 (n) + ki ẽi−1 (n − 1) (20a)
ẽi (n) = ẽi−1 (n − 1) + ki ei−1 (n) (20b)
for i ⫽ 1, . . ., N ⫺ 1, with e0(n) ⫽ ẽ0(n) ⫽ k0x(n), and
eN⫺1(n) ⫽ y(n). In the z domain, Eq. (20) becomes


M
H(z) = b0 (1 + b1 j z−1 + b2 j z−2 ) (19) Ei (n) = Ei−1 (z) + ki z−1 Ẽi−1 (z)
j=1
Ẽi (z) = z−1 Ẽi−1 (z) + ki Ei−1 (z)
where M is the smallest integer greater or equal to (N ⫺ 1)/2.
If N is even, then the coefficient b2M is equal to zero. The block with E0(z) ⫽ Ẽ0(z) ⫽ k0 X(z) and EN⫺1(n) ⫽ Y(z).
diagram representing Eq. (19) is shown in Fig. 6. Notice how By defining the auxiliary polynomials, Hi(z) and H̃i(z), and
the second-order blocks appear in sequence, thus originating the auxiliary coefficients hm,i as:
the name of the cascade-form realization.

Ei (z)

i
Lattice Form. Figure 7 depicts the block diagram of an FIR Hi (z) = k0 = h z−m
lattice filter of length N, where e(m) and ẽ(m) are auxiliary E0 (z) m=0 m,i
signals that appear in lattice-type structures. This realization Ẽi (z)
is called lattice due to its highly regular structure formed by H̃i (z) = k0
concatenating basic blocks of the form shown in Fig. 8. Ẽ0 (z)

b0
x(n) y(n)
+ + ... +

z–1 z–1 z–1

b11 b12 b1M

z–1 z–1 z–1

b21 b22 b2M
Figure 6. Cascade-form realization of an
FIR filter. Its derivation is straightfor-
ward following Eq. (19).
562 FIR FILTERS, DESIGN

k0
x(n) y(n)
+ + ... ... +

k1 k1 k2 k2 ... kN – 1 kN – 1
Figure 7. Lattice-form realization of a
FIR filter. Its name results from the intri-
cate structure of each building block im- z–1 + z–1 + ... z–1 +
plementing Eq. (20).

we can demonstrate, by induction, that these polynomials characteristic. Consider, for instance, the moving average-fil-
obey the recurrence formulas (3) ter of length N

Hi (z) = Hi−1 (z) + ki z−i Hi−1 (z−1 ) (21a)

1 N−1
H(z) = z−n
H̃i (z) = z−i Hi (z−i ) N n=0
(21b)

As its name indicates, this filter determines, for each n, the

with H0(z) ⫽ H̃0(z) ⫽ k0 and HN⫺1(z) ⫽ H(z). Therefore,
1 Adding all N samples of the input signal at each time instant
Hi−1 (z) = [H (z) − ki z−i Hi (z−1 )]
1 − k2i i
and then, the reflection coefficients ki can be obtained from
the direct-form coefficients hi by successively determining the
polynomials Hi⫺1(z) from Hi(z), using Eq. (22), and making
average value of N consecutive samples of a given signal.
(22) n, however, can be a very time-consuming procedure. Fortu-
nately, the same computation can be performed recursively
using the previous sum if we subtract the past input sample
delayed of N cycles and add the present input sample. This
procedure is equivalent to rewriting the moving-average
transfer function as

ki = hi,i
for i ⫽ N ⫺ 1, . . ., 0.
To determine the filter’s impulse response from the set of
lattice coefficients ki, we use Eq. (21a) to determine the auxil-
iary polynomials Hi(z) and make
hi = hi,N
for i ⫽ 0, . . ., N ⫺ 1.
The direct, cascade, and lattice structures differ from each
other with respect to a few implementation aspects. In gen-
eral, the direct form is used when perfect linear-phase is es-
sential. Meanwhile, the cascade and lattice forms present bet-
ter transfer-function sensitivities with respect to coefficient
quantization, but their dynamic range may be an issue, as
their states can reach very high levels, forcing signal scaling
in fixed-point implementations (3,4).
Recursive Form. FIR filters are often associated to nonre-
cursive structures, as the ones previously seen here. However,
there are some recursive structures that do possess an FIR
1 z−N − 1
H(z) = (23)
N z−1 − 1
The realization associated to this filter is seen in Fig. 9, where
the recursive nature of its transfer function is easily observed.
Other FIR filters can also be realized with recursive struc-
tures that make use of some form of zero/pole cancellation,
as exemplified here. This procedure, however, is somewhat
problematic in practice, as the quantization of the filter coef-
ficients or of the filter internal signals can lead to a nonexact
cancellation, which can cause filter instability.
Frequency-Domain Form. The computation of the output
signal of an FIR filter in the direct form is performed as


N−1
y(n) = hi x(n − i)
i=0
If the input signal x(n) is known for all n, and null for n ⬍ 0
and n ⬎ L, a different approach to compute y(n) can be de-
rived based on the discrete Fourier transform, which is usu-
ally implemented through an efficient algorithm commonly
referred to as the fast Fourier transform (FFT) (16). Complet-

ei–1(n) ei(n) 1
+ N
x(n) y(n)
+
ki ki –

z–N z–1
e~i–1(n) ~
ei(n)
z–1 + Figure 9. Recursive-form realization of a moving-average filter. The
reader should be able to identify the feedback loop with the z⫺1 block
Figure 8. Basic block for the lattice realization in Fig. 7. that originates the transfer-function denominator term in Eq. (23).
 ;;;;
FIR FILTERS, DESIGN 563

minimum attenuation, and 웆p and 웆s are the passband and

stopband edges, respectively. Based on these values, we de-
fine

;;
1 + δp
1 + δ 
p
DBp = 20 log10 dB (23a)
1 – δp 1 − δp
 H(ω )

DBs = 20 log10 (δs ) dB (23b)

Bt = (ωs − ωp ) rad/s (23c)

δs Basically, DBp and DBs are the passband maximum ripple,

0 웃p, and the stopband minimum attenuation Sp, expressed in
ωp ω s π decibel (dB), respectively. Also, Bt is the width of the transi-
ω (rad/s) tion band, where no specification is provided.
We now analyze the methods most used to convert this
Figure 10. A typical set of specifications for a low-pass filter includes
typical set of specifications into a realizable transfer function.
definition of the maximum passband ripple 웃p, the minimum stopband
attenuation 웃s, as well as the passband and stopband edges 웆p and
웆s, respectively. Closed-Form Methods: The Kaiser Window. The most impor-
tant class of closed-form methods to approximate a given fre-
quency response using FIR filters is the one based on win-
ing these sequences with the necessary number of zeros (zero- dow functions.
padding procedure) and determining the resulting (N ⫹ L)- A discrete-time frequency response is a periodic function of
element FFTs of hn, x(n), and y(n), designated here as H(k), 웆, and, thus, can be expressed as a Fourier series given by
X(k), and Y(k), respectively, we then have

∞
H̃(e jω ) = h(n)e− jωn
Y (k) = H(k)X (k) n=−∞

and then, where

 π /2
y(n) = FFT−1 {FFThn ]FFT[x(n)]} h(n) =
1
H̃(e jω )e jωn dω
2π −π /2
Using this approach, we are able to compute the entire se-
quence y(n) with a number of arithmetic operations propor- By making the variable transformation z ⫽ ej웆, we have
tional to log2(L ⫹ N), per output sample, as opposed to NL, as
in the case of direct evaluation. Clearly, for large values of N

∞
H̃(z) = h(n)z−n
and L, the FFT method is the more efficient one. n=−∞
In the above approach, the entire input sequence must be
available to allow one to compute the output signal. In this Unfortunately, however, this function is noncausal and of in-
case, if the input is extremely long, the complete computation finite length. These problems can be solved, for instance, by
of y(n) can result in a long input-output delay, which is objec- truncating the series symmetrically for 兩n兩 ⱕ (N ⫺ 1)/2, with
tionable in several applications. For such cases, the input sig- N odd, and by multiplying the resulting function by z⫺(N⫺1)/2,
nal can be sectioned, and each data block processed sepa- yielding
rately using the so-called overlap-and-save and overlap-and-
add methods, as described in (3,4,16).

(N−1)/2

N −1

H̃(z) ≈ H(z) = h(n)z−n− 2 (24)
n=−(N−1)/2
Approximation
As mentioned before, the approximation process searches for This approach, however, results in ripples known as Gibbs’
the transfer function that best fits a complete set of specifica- oscillations appearing near transition bands of the desired
tions determined by the application in hand. There are two frequency response. An easy-to-use technique to reduce these
major forms of solving the approximation problem: using oscillations is to precondition the resulting impulse response
closed-form methods or using numerical methods. Closed- h(n) with a class of functions collectively known as window
form approaches are very efficient and lead to very straight- functions. There are several members of this family of func-
forward designs. Their main disadvantage, however, is that tions, including the rectangular window, the Hamming win-
they are useful only for the design of filters with piecewise- dow, the Hanning (von Hann) window, the Blackman window,
constant amplitude responses. Numerical methods are based the Adams window, the Dolph–Chebyshev window, and the
on iterative optimization methods, and, therefore, can be very Kaiser window. The rectangular window is essentially the ap-
computationally cumbersome. Nevertheless, numerical meth- proximation introduced in Eq. (24). Due to its importance, we
ods often yield superior results when compared to closed-form concentrate our exposition here solely on the Kaiser window.
methods, besides being useful also for designing FIR filters Explanation of the other window functions can be found in
with arbitrary amplitude and phase responses. (1–6,17).
A description of a low-pass filter is represented in Fig. 10, The most important feature of a given window function is
where 웃p is the passband maximum ripple, 웃s is the stopband to control the transition bandwidth and the ratio between the
564 FIR FILTERS, DESIGN

ripples in the passband and stopband in an independent man- 7. Finally, compute

ner. The Kaiser window allows that control and is defined as
(4):

N −1


(N−1)/2
H(z) = z− 2 [w(n)h(n)] z−n

 I0 (β )
n=−(N−1)/2
for |n| ≤ (N − 1)/2
w(n) = I0 (α) (25)
 High-pass, bandpass, or bandstop filters are designed in a
0 otherwise
very similar manner. A few variables, however, must be rede-
fined, as it is summarized in Table 2. For bandpass and band-
where 움 is an independent parameter, 웁 is given by stop filters, 웆p1 and 웆p2 are the passband edges with 웆p1 ⬍

 
2
웆p2, and 웆s1 and 웆s2 are the stopband edges with 웆s1 ⬍ 웆s2.
2n
β=α 1−
N−1 Numerical Methods. Numerical methods are often able to
approximate the required frequency response using lower or-
and I0(.) is the zeroth-order modified Bessel function of the der filter than their closed-form counterparts. The design of
first kind. FIR filters using numerical methods is dominated in the liter-
The ripple ratio resulting from the Kaiser window can be ature by the Chebyshev and the weighted-least-squares
adjusted continuously from the low value in the Blackman (WLS) approaches. The Chebyshev scheme minimizes the
window to the high value of the rectangular window by sim- maximum absolute value of a weighted error function be-
ply varying the parameter 움. In addition, the transition band- tween the prototype’s transfer function and a given ideal solu-
width can be varied with the filter length N. The most impor- tion. For that reason, Chebyshev filters are also said to satisfy
tant property of the Kaiser window is that empirical formulas a minimax criterion. The universal availability of minimax
are available relating the parameters 움 and N to any specific computer routines, has motivated their widespread use. The
values of ripple ratio and transition bandwidth. In that man- WLS approach, which minimizes the sum of the squares of
ner, given the definitions in Eq. (24), a filter satisfying these the weighted error function, is characterized by a very simple
specifications can be readily designed based on the Kaiser implementation. Its basic problem, however, results from the
window as (4,6): well-known Gibbs phenomenon which corresponds to large er-
ror near discontinuities of the desired response.
To understand the basic problem formulation of the nu-
1. Determine h(n) using the Fourier series, assuming an merical methods for approximating FIR filters, consider the
ideal frequency response transfer function associated to a linear-phase filter of length
N

1 for |ω| ≤ ωc
H̃(e jω
)=

N−1
0 for ωc ≤ |ω| ≤ π H(z) = h(n) z−n
n=0

with 웆c ⫽ (웆p ⫹ 웆s)/2

and assume that N is odd, and h(n) is symmetrical. Other
2. Choose 웃 as the minimum of 웃p and 웃s. cases of N even or h(n) antisymmetrical can be dealt with in
3. Compute DBp and DBs with that value of 웃 in Eq. (24a) a very similar way and are not further discussed here. The
and Eq. (24b), respectively. frequency response of such filter is then given by
4. Choose the parameter 움 as follows:
(N −1 )
 H(e jω ) = e− jω 2 Ĥ(ω)

0 for DBs ≤ 21


0.5842(DB − 21)0.4 + 0.07886(DB − 21) where
s s
α=

 for 21 < DBs ≤ 50 τ0




 Ĥ(ω) = a(n) cos(ωn) (26)
0.1102(DBs − 8.7) for DBs > 50
n=0

5. Choose the value of D as follows: with ␶0 ⫽ (N ⫺ 1)/2, a(0) ⫽ h(␶0), and a(n) ⫽ 2h(␶0 ⫺ n), for
 n ⫽ 1, . . ., ␶0.
0.9222 for DBs ≤ 21 If e⫺j웆␶0H̃(웆) is the desired frequency response, and W(웆) is
D = DBs − 7.95 a strictly-positive weighting function, consider the weighted
 for DBs > 21
14.36 error function E(웆) defined in the frequency domain as

and then select the lowest odd value of the filter length E(ω) = W (ω)[H̃(ω) − Ĥ(ω)] (27)
N such that
The approximation problem for linear-phase nonrecursive
ωs D digital filters resumes to the minimization of some objective
N≥ +1
Bt function of E(웆) in such a way that

6. Determine w(n) using Eq. (25). |E(ω)| ≤ δ

 FIR FILTERS, DESIGN 565

Table 2. Filter Definitions to Use With the Kaiser Window

Type Bt 웆c H(e j웆)

low-pass 웆p ⫺ 웆 s 웆c ⫽
웆p ⫹ 웆s
2 再
1, for F웆F ⱕ 웆c
0, for 웆c ⱕ F웆F ⱕ 앟

high-pass 웆 s ⫺ 웆p 웆c ⫽
웆p ⫹ 웆s
2 再
0, for F웆F ⱕ 웆c
1, for 웆c ⱕ F웆F ⱕ 앟
Bt
0, for F웆F ⱕ 웆c1

冦
웆c1 ⫽ 웆p1 ⫺
min [(웆p1 ⫺ 웆s1), (웆s2 ⫺ 웆p2)] 2
bandpass 1, for 웆c1 ⱕ F웆F ⱕ 웆c2
Bt
웆c2 ⫽ 웆p2 ⫺ 0, for F웆F ⱕ 앟
2
Bt
1, for F웆F ⱕ 웆c1

冦
웆c1 ⫽ 웆p1 ⫺
min [(웆s1 ⫺ 웆p1), (웆p2 ⫺ 웆s2)] 2
bandstop 0, for 웆c1 ⱕ F웆F ⱕ 웆c2
Bt
웆c2 ⫽ 웆p2 ⫺ 1, for F웆F ⱕ 앟
2

and then, Numerical Methods: The Chebyshev Approach. Chebyshev

filter design consists of the minimization over the set of filter
δ
|H(ω) − Ĥ(ω)| ≤ coefficients A of the maximum absolute value of E(웆); that is,
W (ω)
E(ω)∞ = min max [W (ω)|H̃ (ω) − Ĥ(ω)|]
By evaluating the error function defined in Eq. (27), with A 0≤ω≤π
Ĥ(웆) as in Eq. (26), on a dense frequency grid with 0 ⱕ 웆i ⱕ
앟, for i ⫽ 1, . . ., MN, a good discrete approximation of E(웆) With the discrete set of frequencies, in Eq. (28), this minimax
can be obtained. For practical purposes, for a filter of length function becomes
N, using 8 ⱕ M ⱕ 16 is suggested. Points associated to the
E(ω)∞ ≈ min max [W|H
H − UA
A|]
transition band are disregarded, and the remaining frequen- A 0≤ω i ≤π
cies should be linearly redistributed in the passband and
stopband to include their corresponding edges. Thus, the fol- If we refer to Fig. 10, the minimax method effectively opti-
lowing vector equation results mizes

E = W (H
H − UA
A) DBδ = 20 log10 min(δp , δs ) dB

where This problem is commonly solved with the Parks-McClellan

algorithm (18–20) or some variation of it (21,22). These meth-
E = [E(ω1 ) E(ω2 ) . . . E(ω MN )]T (28a) ods are based on the Reméz exchange routine, the solution of
W = diag[W (ω1 ) W (ω2 ) . . . W (ω MN )] (28b) which can be tested for optimality using the alternation theo-
rem as described in (18). An important feature of minimax
H (ω1 ) H̃(ω2 ) . . . H̃(ω MN )]
H = [H̃ T
(28c)
  filters is the fact that they present equiripple errors within
1 cos(ω1 ) cos(2ω1 ) ... cos(τ0 ω1 ) the bands, as can be observed in Fig. 11.
1 cos(ω2 ) cos(2ω2 ) ... cos(τ0 ω2 
 
U = .. .. .. .. ..  (28d)
 Numerical Methods: The Weighted-Least-Squares Ap-
. . . . .  proach. The weighted least-squares (WLS) approach mini-
1 cos(ω MN ) cos(2ω MN ) ... cos(τ0 ω MN ) mizes the function
 π  π
A = [a(0) a(1) . . . a(τ0 )] T (28e)
E(ω)22 = |E(ω)|2 dω = W 2 (ω)|H̃(ω) − Ĥ(ω)|2 dω
0 0
with M ⬍ M, as the original frequencies in the transition
band were discarded. For the discrete set of frequencies, in Eq. (28), this objective
The design of a lowpass digital filter as specified in Fig. 10, function is estimated by
using either the minimax method or the WLS approach, is
achieved making the ideal response and weight functions re- E(ω)22 ≈ E T E
spectively equal to
 the minimization of which is achieved with
1 for 0 ≤ ω ≤ ωp
H̃(ω) = A ∗ = (U T W 2U )−1U T W 2H
0 for ωs ≤ ω ≤ π
If we refer to Fig. 10, the WLS objective is to maximize the
and
passband-to-stopband ratio (PSR) of energies

1 for 0 ≤ ω ≤ ωp
E 
W (ω) = PSR = 10 log10
p
dB
δp /δs for ωs ≤ ω ≤ π Es
566 FIR FILTERS, DESIGN

0 implementation of the latter. As applied to the nonrecursive

digital-filter design problem, the L2 Lawson algorithm is im-
0.5
–10 plemented by a series of WLS approximations using a time-
varying weight matrix Wk, the elements of which are calcu-
0
–20
lated by (23)
–0.5 2
Wk+1 (ω) = Wk2 (ω)|Ek (ω)|
 H(ω ) (dB)

–30
–1
0 0.1 0.2 0.3 0.4 Convergence of the Lawson algorithm is slow, as usually 10
–40 to 15 WLS iterations are required in practice to approximate
the minimax solution. Accelerated versions of the Lawson al-
–50 gorithm can be found in (23–25).
FIR filters can be designed based solely on power-of-two
–60 coefficients. This is a very attractive feature for VLSI imple-
mentations, as time-consuming multiplications are avoided.
–70 This approach is a very modern research topic, and interested
0 0.5 1 1.5 2 2.5 3 readers are referred to (12,26,27).
ω (rad/s)

Figure 11. Equiripple bands (passband in detail) are typical for FIR BIBLIOGRAPHY
filters approximated with the Chebyshev approach.
1. L. R. Rabiner and B. Gold, Theory and Application of Digital Sig-
nal Processing, Englewood Cliffs, NJ: Prentice-Hall, 1975.
where Ep and Es are the passband and stopband energies, re- 2. J. G. Proakis and D. G. Manolakis, Introduction to Digital Signal
spectively; that is, Processing, New York: Macmillan, 1988.
 ωp
3. A. V. Oppenheim and R. W. Schafer, Discrete-Time Signal Pro-
cessing, Englewood Cliffs, NJ: Prentice-Hall, 1989.
Ep = 2 |Ĥ(ω)|2 dω
0 4. A. Antoniou, Digital Filters: Analysis, Design, and Applications,
 π 2nd ed., New York: McGraw-Hill, 1993.
Es = 2 |Ĥ(ω)|2 dω
ωs
5. L. B. Jackson, Digital Filters and Signal Processing, 3rd ed., Nor-
well, MA: Kluwer, 1996.
A typical lowpass nonrecursive digital filter designed with the 6. D. J. DeFatta, J. G. Lucas, and W. S. Hordgkiss, Digital Signal
WLS method is depicted in Fig. 12, where the large ripples Processing: A System Design Approach, New York: Wiley, 1988.
near the band edges are easily identified. 7. S. M. Kay, Modern Spectral Estimation, Englewood Cliffs, NJ:
In 1961, Lawson derived a scheme that performs a Chebys- Prentice-Hall, 1988.
hev approximation as a limit of a special sequence of weighted 8. S. S. Haykin, Adaptive Filter Theory, 2nd ed., Englewood Cliffs,
least-p (Lp) approximations with p fixed. The particular case NJ: Prentice-Hall, 1991.
with p ⫽ 2 thus relates the Chebyshev approximation to the 9. B. Widrow and S. Stearns, Adaptive Signal Processing, Engle-
WLS method, taking advantage of the substantially simpler wood Cliffs, NJ: Prentice-Hall, 1985.
10. P. S. R. Diniz, Adaptive Filtering: Algorithms and Practical Imple-
mentation, Norwell, MA: Kluwer, 1997.
0 11. G. Strang and T. Nguyen, Wavelets and Filter Banks, Wellesley,
MA: Wellesley-Cambridge Press, 1996.
0.5 12. S. K. Mitra and J. E. Kaiser (eds.), Handbook for Digital Signal
–10
Processing, New York: Wiley, 1993.
0
13. R. E. Crochiere and L. R. Rabiner, Multirate Digital Signal Pro-
–20
cessing, Englewood Cliffs, NJ: Prentice-Hall, 1983.
–0.5
14. R. Boite and H. Leich, A new procedure for the design of high
 H(ω ) (dB)

–30 order minimum phase FIR digital or CCD filters, Signal Process,
–1
0 0.1 0.2 0.3 0.4 3: 101–108, 1981.
–40 15. Y. Kamp and C. J. Wellekens, Optimal design of minimum-phase
FIR filters, IEEE Trans. Acoust. Speech Signal Process., ASSP-
–50 31: 922–926, 1983.
16. E. O. Brigham, The Fast Fourier Transform and Its Applications,
–60 Englewood Cliffs, NJ: Prentice-Hall, 1988.
17. J. W. Adams, A new optimal window, IEEE Trans. Signal Pro-
cess., 39: 1753–1769, 1991.
–70
0 0.5 1 1.5 2 2.5 3 18. T. W. Parks and J. H. McClellan, Chebyshev approximation for
ω (rad/s) nonrecursive digital filters with linear phase, IEEE Trans. Circuit
Theory, CT-19: 189–195, 1972.
Figure 12. Large errors near band discontinuities (passband in de- 19. J. H. McClellan, T. W. Parks, and L. R. Rabiner, A computer
tail) are typical for FIR filters designed with the weighted-least- program for designing optimum FIR linear phase digital filters,
squares approach. IEEE Trans. Audio Electroacoust., AU-21: 506–526, 1973.
 FIR FILTERS, WINDOWS 567

20. L. R. Rabiner, J. H. McClellan, and T. W. Parks, FIR digital filter

design techniques using weighted Chebyshev approximation,
Proc. IEEE, 63: 595–610, 1975.
21. J. W. Adams and A. N. Wilson, Jr., On the fast design of high-
order FIR digital filters, IEEE Trans. Circuits Syst., CAS-32:
958–960, 1985.
22. D. J. Shpak and A. Antoniou, A generalized Reméz method for
the design of FIR digital filters, IEEE Trans. Circuits Syst., 37:
161–173, 1990.
23. J. R. Rice and K. H. Usow, The Lawson algorithm and extensions
Mathematics of Computation, in press.
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ipple FIR and IIR digital filter design, IEEE Trans. Signal Pro-
cess., 40: 551–558, 1992.
25. R. H. Yang and Y. C. Lim, Efficient computational procedure for
the design of FIR digital filters using WLS technique, IEE Proc.-
G, 140: 355–359, 1993.
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design based upon an LMS criteria, IEEE Trans. Circuits Syst.,
CAS-30: 723–739, 1983.
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Syst., 1991, pp. 484–487.

SERGIO L. NETTO
GELSON V. MENDONÇA
Federal University of Rio de Janeiro
 FREQUENCY SYNTHESIZERS 775

FREQUENCY SYNTHESIZERS

Frequency synthesis is the engineering discipline dealing

with generation of a single or of multiple tones, all derived
from a common time-base, always a crystal oscillator.
Traditionally, frequency synthesis (FS) generated a single
tone with variable frequency or amplitude. There are new ap-
plications, especially for testing and simulation, that require
multitone generation and even arbitrary wave generation,
which relate to digital frequency synthesis. In the last two
decades, FS has evolved from mainly analog to a mix of ana-
log, radio-frequency (RF), digital, and digital signal pro-
cessing (DSP) technologies.
There are three major FS techniques:

1. Phase Lock Loop. Also known as indirect synthesis, the

most popular FS technique, based on a feedback mecha-
nism that enables simplicity and economics via digital
division and analog processing.
2. Direct Analog. An analog technique using multiplica-
tion, division, and mix-filtering, offers excellent signal
quality and speed.
3. Direct Digital. DSP method that generates and manip-
ulates the signal in the numbers (digital) domain and
eventually converts to its analog form via a digital to
analog converter.

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.
776 FREQUENCY SYNTHESIZERS
Table 1. Integrated Circuits Used in Phase Lock Loops
Fujitsu Semiconductors: MB15xx
National Semiconductors: 23xx
Philips: SA7025, SA8025, UMA1014
Motorola: MC145xxx
Plessey: SP55xx, SP56xx, SP88xx
Texas Instruments: TRF2020, 2050, 2052
Frequency synthesis is a mature technology yet evolving rap-
idly. The traditional analog designs are supplemented with
ever-increasing digital and DSP methods and technologies.
These allow a high level of integration, lower power, manufac-
turing uniformity (and thus yield uniformity), and low cost.
Though a novel technology only 20 years ago, FS and espe-
cially phase lock loop (PLL) are very popular, accessible, and
economical. Traditionally, FS started to enter the field of elec-
tronics as quite bulky and expensive instruments, using mul-
tiple crystals and complex analog processing functions such
as mixing, filtering, and division. Better architectures and
simpler designs have replaced these. Accelerating integrated
circuit (IC) technology and high-level integration silicon now
offer complete synthesizers, especially PLL and direct digital
synthesizers (DDSs) on a single chip and sometimes more
than one on a single dice.
In the engineering realm, all signals generated are ampli-
fied and filtered noise. There are no deterministic signals in
nature. The cardinal issue for FS is therefore how clean these
signals are and how close they come to a theoretical sin(웆t).
Such a theoretical signal will have all of its energy in a single
spectral line. In reality, signal spectra have a noise distribu-
tion caused by amplitude modulation (AM) noise and phase
perturbation, also known in FS as phase noise. Phase noise
can be described by its spectral properties, usually its noise
distribution designated in dBC/Hz, or its time equivalent,
also known as jitter. Spectral distribution L(fm) details the
exact spectral shape of the signal’s noise and is defined by the
single side-band energy level of the signal at a specific offset
from the carrier relative to the signal’s total energy. This de-
tailed technique has become the de facto method to describe
and characterize phase noise (see Fig. 1).
For example, a 1000 MHz signal with a spectral noise
characteristic of ⫺70 dBC/Hz (dB is used almost exclusively
because of the large ratios involved) at an offset of 1 kHz from
the carrier means that at 1 kHz from the carrier (either
1000.001 or 999.999 MHz), the single side-band noise power
contained in 1 Hz bandwidth is 10⫺7 compared with the sig-
nal’s total power. The function L(fm) that defines the noise
distribution spectrum is always measured in decibel of the
noise level. Note that the noise is part of the signal and that
the integral energy under the L(fm) curve is the signal total
power (Fig. 1).
Table 2. Integrated Circuits Used in Direct Digital Synthesis
Stanford Telecom: STEL-11xx and STEL-21xx
Analog Devices: AD7008, AD9830/9831, AD9720/9721
Sciteq Communications: SEI-432, SEI-631, DCP-1
L(fm)
AL 9.71 dBm
Attenuation 28 dB
10.00 dB/div Test complete
Sample
Center frequency
1.675 006 24 GHz
Loop
VCO
VCO
–70
Center 1.675 006 24 GHz Span 10.50 kHz
AB 110 Hz VB 300 Hz ST 2.773 fm
Figure 1. Phase noise of a typical synthesizer.
SYNTHESIZER PARAMETERS
Step Size
This is also known as resolution, and it measures the smallest
frequency increment the synthesizer can generate. As an ex-
ample, an FS used in a North American cellular phone
(AMPS—American Mobile Phone Service—standard), or
Time Division Multiple Access (TDMA), has 30 kHz resolu-
tion. In frequency modulation (FM) broadcasting radio, the
step is usually 100 kHz.
Phase Noise
This parameter was already mentioned before. The issue of
signal integrity, or otherwise the issue of the signal’s ‘‘cleanli-
ness,’’ is the major challenge for FS designers. Long-term
noise deals mainly with the accuracy, drift, and aging of the
crystal, and short-term noise deals with rapid phase fluctua-
tions.
Spurious Responses
These define the level of the discrete interferences, noise
sources that are periodic and therefore exhibit spectral lines
rather than a spectrum. These noise sources emerge from ra-
diation—for example, line spurious responses at 60 Hz
(US)—or from its multiples that always exist in the air and
power supplies, as well as from other radiated energy that
exists because of the enormous wireless traffic that is emerg-
ing and growing. Other sources are mixing products in the
radio or synthesizer, nonlinearities, and ground currents.
Switching Speed
This defines the amount of time it takes the synthesizer to
hop from a frequency F1 to another F2. This parameter is usu-
ally measured in two ways: by checking when the new fre-
quency settles to within a frequency tolerance (say within 5

kHz), or (a more strict requirement) by checking the time it
takes to settle to within a phase tolerance, in most cases to
within 0.1 radian. The phase settling requirement can be as
much as three to five times longer than the frequency set-
tling.
Phase Transient
This defines the way the signal’s phase behaves in transition
from frequency F1 to frequency F2. There are mainly three
ways to switch:
1. It might be a random parameter, so the phase is un-
known after switching.
2. The phase can switch continuously, meaning that when
switching from F1 to F2, there will be no disturbance in
the phase. Such switching requirements are necessary
when generating linear FM signals or minimum shift
keying (MSK) modulation, or other phase modulation
waveforms.
3. In the case of phase memory, if switched from F1 to F2
and then back to F1, the signal’s phase will be as if the
switching did not occur. This is useful in coherent detec-
tion radars and frequency hop communications.
Frequency Range
This defines the frequency band the FS covers.
Other Parameters
Other parameters are not unique to FS; among them are out-
put impedance, power flatness, size, power consumption, envi-
ronment, and the like.
The main tools used in FS are as follows: multiplication by
comb generation; addition and subtraction by mix and filter-
ing; and division (digital) and feedback for PLL. Another
cardinal principle in FS is as follows: Multiplication by N cor-
rupts phase noise and spurious by N2 or 20 log(N) dB. Divi-
sion improves by the same ratio.
SYNTHESIS TECHNIQUES
Direct Analog Synthesis
This method, the first to be used in FS, derives the signals
directly from the reference—as compared to PLL, which it
does indirectly. Direct analog uses building blocks such as
comb generators, mix and filter, and dividers as the main
tools. Many direct analog synthesizers use similar repeating
blocks for resolution. These blocks usually generate a 10 MHz
band in the ultrahigh frequency (UHF) range, in 1 MHz steps,
and after division (mostly by 10) they are used as an input
to the next similar stage. Every stage divides by 10, thereby
increasing the resolution arbitrarily by as many stages as the
designer chooses to use. Most direct analog synthesizers are
instruments and traditionally use binary coded decimal
(BCD) for control. This is losing importance because a com-
puter controls all modern applications.
Signals are therefore very clean because they are derived
directly from the crystal; however, complexity is high and res-
olution comes at a high price. Direct analog synthesizers also
achieve fast switching speed, limited mainly by filters propa-
FREQUENCY SYNTHESIZERS 777
gation delay. Speed ranges from ⬍1 애s to 50 애s. Because
there are no mechanisms to clean the signals at high offset
frequencies from carrier, their noise floor—where the phase
noise levels—is comparatively (to PLL) high.
Direct analog synthesizers are available from dc to 26
GHz, are usually quite bulky and expensive, exhibit excellent
phase noise and switching speed, and found applications in
communications, radar, imaging, magnetic resonance im-
aging, simulators, and ATE.
Direct Digital Synthesis (DDS)
DDS is a DSP technology based on the sampling theorem. The
principle of its operation is based on storing the digital values
of sine wave amplitude in memory, then flushing these sam-
ples out by addressing the memory with an indexer. The in-
dexer is always a digital accumulator, allowing the phase
ramp (memory address) to change its slope to any value (com-
pared with a counter that can index the RAM or ROM mem-
ory only by increments of 1).
As a consequence, the accumulator output can be interpre-
ted as a signal phase, 웆t (actually 웆nT, where T is clock time,
since it is sample data), with a variable slope given by the
accumulator control. For example, if a 32 bit binary accumu-
lator, which performs the function
Sn = Sn−1 + W (Sn is the output of sample n, W is the input)
(1)
is addressed with W ⫽ 0, the output will not change, signi-
fying direct current (dc) signal. However, if W ⫽ 1, the accu-
mulator will take 232 clock ticks to come back to its original
state. So a complete cycle of the phase from ␾ ⫽ 0 (accumula-
tor is 0) to 2앟 (accumulator is full) takes 232 ticks. Generally,
a DDS output frequency is given by
Fo = FckW/ACM (2)
where Fck is the clock frequency, W is the input control, ACM
is the accumulator size, and W ⬍ ACM/2.
For ACM ⫽ 232, Fck ⫽ 20 MHz, and W ⫽ 1, output fre-
quency is given by 0.00465 . . . Hz, which is also the synthe-
sizer resolution, its smallest step.
The read-only memory (ROM) output is connected to a dig-
ital-to-analog converter (DAC) which generates the analog
signal smoothed by the output filter (see Fig. 2). According to
the sampling theorem, the maximum output frequency is
Fck /2, also known as Nyquist frequency.
The various waveforms and modulation points are shown.
Because the accumulator output is the signal phase, phase
modulation can be applied; amplitude modulation can be ap-
plied at the output of the ROM, the amplitude point.
DDS is thus a numbers technology, related to frequency
only by the clock. The artifacts caused by sampling generate
many (mirror) frequencies as shown in the sampling theorem;
these are usually referred to as aliasing frequencies.
DDS offers simplicity, economy, integration, and very fast
switching speed. The digital nature of the technology offers
design flexibility and simplicity, low-cost manufacturing, and
very high density (small dice).
As sampled data, DDS suffers the common problems of
quantization. The level of accuracy determines the dynamic
range of the design, in most cases 10 to 12 bits. The most
778 FREQUENCY SYNTHESIZERS

Clock

Sine map Digital-to- Output

Phase

;;;;;;
Frequency Low-pass
accumulator in analog
control filter
ROM or RAM converter

(a) (b) (c) (d)

;;;;;;
On/off FM φM
Digital
AM
Analog
AM/FM/φ M

D/A Low-pass
Accumulator Memory converter Deglitcher filter
Frequency
control

Clock
Figure 2. Direct digital synthesizer block diagram and functionality.

significant weakness of DDS are limited bandwidth (clock fre- also known as indirect synthesis, is a negative feedback loop
quencies are in the 400 MHz for CMOS devices and 1500 structure that locks the phase of the output signal after divi-
MHz for GaAs) and spurious response. Spurious responses sion to the reference. Synthesis is simple because the variable
are generally limited to ⫺6D, where D is the number of bits counter (divider) N allows the generation of many frequen-
used in the DAC. Thus a 10 bit DDS (using a 10 bit DAC) cies Fo
usually be limited to ⫺60 dBC spurious responses. These spu-
rious responses are either periodicities generated in the quan- Fo = NFr (Fo = output frequency, Fr = reference) (3)
tization process or intermodulation products generated by the
DAC, the only analog part. As a rule of thumb, spurious per-
formance deteriorates with increased output frequency or oth-
erwise with decrease in samples per cycle. Arbitrary wave-
R2 C
form generators (AWGs) are a superset of DDS. These enable
the memory to be loaded with arbitrary wave samples, and
then they sequentially flush the wave samples out. AWGs R1 Active
found use in simulation and testing.

Phase Lock Loop

PLL is the technology of choice for generating radio frequen- R1
cies and microwave frequencies for radio applications. PLL,

R2
VCO
ϕo C
H(s) Kv /s
Passive
K dδϕ
Phase detector
1/N
δϕ = ϕ i – ϕ o/N

ϕi

Figure 3. Phase lock loop block diagram. Figure 4. Second-order loop circuits.

by changing the division ratio N. Changing N is made easy
by the use of dual modulus devices, capable of dividing by two
(and sometimes more) ratios. For example, 64/65 or 128/129
are very common.
PLL chips are available in a great variety, in low power
and very low cost, and include all the functionality necessary
with the exception of an external crystal, voltage controlled
oscillator (VCO) and loop filter (mainly resistors and capaci-
tors). Convenience, economy, simplicity, and ease of use made
PLL a household name used in television, radio, consumer
electronics, cellular phones, and Satcom terminals, practically
in almost any conceivable electronics radio (see Fig. 3).
When locked, PLL can be assumed to be a linear system,
and classical feedback theory can be applied for analysis. The
most common PLL structure is of second order, and there are
two poles in the transfer function denominator: one from the
VCO, with a Laplace domain transfer function given by Kv /s
(Kv is the VCO constant, phase is the integral of frequency)
and one from the loop filter having a memory device (capaci-
tor). The loop transfer function is given by
2ξ ωn s + ωn2
ϕo /ϕi (s) = (4)
s2 + 2ξ ωn s + ωn2
웆n is the natural frequency and ␰ is the damping, both bor-
rowed from classical control theory. 웆n and ␰ are given by (for
the active loop structure shown, Fig. 4)
ωn = (K/T1 N)0.5 and ξ = ωn T2 /2 (5)
T1 ⫽ R1C, T2 ⫽ R2C, K ⫽ KvKp /N, Kv (Hz/V), and Kp (V/radian)
are VCO and phase detector constants.
Overall performance is controlled by noise sources from
phase detector, divider, and other active components within
the loop bandwidth and by the VCO outside. Within the loop
FREQUENCY SYNTHESIZERS 779
bandwidth, VCO noise is suppressed by the loop. PLL noise
sources within the loop are multiplied by 20 log(N), which can
be very significant when N is large. Typical phase detector
noise is in the ⫺150 dBC/Hz range for well-designed circuits.
An advanced PLL technology known as fractional-n allows
lowering N and generating step size smaller than Fr (hence
fractional), thereby gaining phase noise performance. The
fractional principle requires dynamic changes in division ra-
tio N, thereby causing spurious signals, which are compen-
sated by either extra filtering, analog feed forward correction
(open loop), or digital waveshaping techniques.
BIBLIOGRAPHY
R. E. Best, Phase Lock Loops: Theory, Design and Applications, New
York: McGraw-Hill, 1984.
F. M. Gardner, Phaselock Techniques, New York: Wiley, 1980.
B.-G. Goldberg, Digital Techniques in Frequency Synthesis, New York:
McGraw-Hill, 1996.
V. Manassewitsch, Frequency Synthesizers: Theory and Design, New
York: Wiley, 1983.
B. Miller and B. Conley, A multiple modulator fractional divider,
IEEE Trans. Instrum. Meas., 40: 578–583, 1991.
U. L. Rohde, Digital PLL Frequency Synthesizers: Theory and Design,
Englewood Cliffs, NJ: Prentice-Hall, 1983.
R. C. Stirling, Microwave Frequency Synthesis, Englewood Cliffs, NJ:
Prentice-Hall, 1987.
J. Tierney, C. M. Radar, and B. Gold, A digital frequency synthesizer,
IEEE Trans. Audio Electroacoust., AU-19: 48–57, 1971.
BAR-GIORA GOLDBERG
Sciteq Electronics, Inc.
FRESNEL’S FORMULAE. See OPTICAL PROPERTIES.
632 HARMONIC OSCILLATORS, CIRCUITS

HARMONIC OSCILLATORS, CIRCUITS

In electronics a harmonic oscillator is an electronic circuit
that generates a sinusoidal signal. This signal can either be
a voltage, a current, or both. Harmonic oscillators are not re-
stricted to electronics. They can be found in many other disci-
plines. However, they always can be described by similar
mathematical equations. A very familiar harmonic oscillator
is the harmonic pendulum, which is found in many high
school physics textbooks. It is a mechanical system consisting
of a mass suspended by a fixed length thread. Figure 1 illus-
trates this. When mass m is slightly separated from its equi-
librium point (so that angle ␪ in Fig. 1 is sufficiently small)
and set free, the earth’s gravitational force will make it move
toward its resting point. When the mass reaches the resting
point it has gained some speed that will make it keep running
toward the other side of the equilibrium point, until it stops
and comes back. And so it will oscillate from one side of the
equilibrium point to the other. What happens is that by ini-
tially departing the mass from its equilibrium point, an exter-
nal agent is increasing its potential energy. When it is set
free the action of the earth’s gravitational force, together with
the constraint imposed by the fixed length thread, will gradu-
ally change this initial increase of potential energy into ki-
netic energy. At the equilibrium point all potential energy
supplied initially by the external agent is in form of kinetic
energy and speed is maximum. At the points of maximum
elongation the kinetic energy (and speed) is zero and the orig-
inal potential energy is recovered. The pendulum oscillates at
constant frequency and, if there is no friction, it keeps oscil-
lating indefinitely with constant maximum elongation or am-
plitude. However, in practice friction cannot be completely
suppressed. Consequently, in order to have a pendulum oscil-
lating permanently there must be a way of supplying the en-
ergy lost by friction.
In an electronic oscillator there is also a mechanism by
which energy of one type is changed into another type (energy
can also be of the same type but interchanged between differ-

Figure 1. The mechanical pendulum behaves as a harmonic oscilla-

tor in the limit of very small maximum angle deviations.

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.
 HARMONIC OSCILLATORS, CIRCUITS 633

The solution to this second order time domain differential

equation is

+ vC (t) = vC (0) cos(ωt) − iL (0) L/C sin(ωt) (5)
vC iL
– where vC(0) is the capacitor voltage at time zero, iL(0) is the
inductor current at time zero and 웆 is the angular frequency
of the resulting oscillation whose value is

1
Figure 2. An ideal capacitor connected in parallel with an ideal in- ω= √ (6)
ductor form a harmonic oscillator. LC

Using Eqs. (3), (5), and (6) in Eq. (1) results in


ent devices). Figure 2 shows a capacitor connected in parallel iL (t) = iL (0) cos(ωt) + vC (0) C/L sin(ωt) (7)
with an inductor. At equilibrium there is no voltage across
the capacitor and no current through the inductor. However, By means of basic trigonometric manipulations Eqs. (5) and
if by some means, an initial voltage (or equivalently, charge) (7) can be rewritten as
is supplied to the capacitor, its stored energy increases. The
inductor provides a path to discharge the capacitor so that a vC (t) = Vmax cos(ωt + ϕ)
current builds up through the inductor. However, by the time  (8)
the capacitor has zero charge the current flowing through the iL (t) = Vmax C/L sin(ωt + ϕ)
inductor is maximum and the inductor stores all the original
capacitor energy in the form of magnetic flux energy. The con- where,
sequence is that the current keeps flowing through the induc- 
tor, charging now the capacitor oppositely, until the current is Vmax = vC2 (0) + i2L (0)L/C
zero. If there are no resistive losses this process will continue  
i (0)  (9)
indefinitely: capacitor and inductor keep interchanging their ϕ = arctan L L/C
vC (0)
stored energies. The voltage across the capacitor will be si-
nusoidal in time, and so will be the current through the in-
ductor. The amplitude (or maximum elongation) of the voltage Equation (8) reveals that vC(t) and iL(t) have a phase shift of
oscillations is equal to the initial voltage supplied to the ca- 앟/2 radians. This is usually referred to as vC(t) and iL(t) being
pacitor. In practice both capacitor and inductor have resistive in quadrature, and the resonator in Fig. 2 as being a quadra-
losses, so that in order to keep the system oscillating indefi- ture resonator or oscillator. Note that the maximum oscilla-
nitely there must be a way of supplying the energy being lost. tion amplitudes (Vmax or Vmax兹C/L, respectively) depend on
the initial conditions vC(0) and iL(0) ⫽ ⫺C v̇C(0).
Usually, differential equations like Eq. (4) are not solved
IDEAL RESONATOR MATHEMATICAL MODEL directly in the time domain but in the frequency domain. For
this, let us take the Laplace transform of Eq. (4)
In Fig. 2 the capacitor voltage vC and its current iC are related
VC (s)
mathematically by the expression s2VC (s) − svC (0) − v̇C (0) + =0 (10)
LC
dvC
iC = C (1) where VC(s) is the Laplace transform of vC(t). Since iL(0) ⫽
dt
⫺C v̇C(0), Eq. (10) can be rewritten as
where C is the capacitor’s capacitance. For the inductor, its s 1 iL (0)
voltage vL and current iL are related by VC (s) = v (0) − 2 (11)
s2 + 1/LC C s + 1/LC C
diL
vL = L (2) Taking the inverse Laplace transform of Eq. (11) results in
dt Eq. (5). Usually in circuits, the initial conditions involved in
the Laplace transform are ignored and Eq. (10) is simplified
where L is the inductor’s inductance. Besides this, the circuit to
of Fig. 2 imposes the following topological constraints
1
vC = vL s2 + =0 (12)
(3) LC
iC = −iL
which has the following solutions
Solving Eqs. (1–3) yields
s1 = jω, s2 = − jω
2
d vC 1 1 (13)
+ v =0 (4) ω= √
dt 2 LC C LC
634 HARMONIC OSCILLATORS, CIRCUITS

Solutions s1 and s2 are called the poles of the system, and in
this case the two poles are complex conjugate and are purely
imaginary (their real part is zero). In circuits, people don’t
take the inverse Laplace transform to know the solution.
They know that if a system has a pair of purely imaginary
poles the signals have a sinusoidal steady state whose ampli-
tude depends on the initial conditions.
REAL RESONATOR MATHEMATICAL MODEL
is negligible and one can consider that the system has stopped
oscillating. Consequently, in practice, the circuit of Fig. 2 is
not useful for building an oscillator.
Imagine that somehow we could make RL or RC (or both)
negative, so that b ⬍ 0. A negative resistance behaves as an
energy source that replaces the energy dissipated by positive
resistances. In this case the poles would have a positive real
part and the amplitude of the oscillations
A(t) = Vmax e−bt/2 (20)

As mentioned earlier, the circuit of Fig. 2 is ideal. In practice would increase exponentially in time, assuming Vmax ⬆ 0 (due
there will always be resistive losses in the capacitor, in the to noise Vmax cannot be exactly zero all the time). This would
inductor, or in both. Either introducing a small resistance RL yield an oscillator with initial startup but that would be un-
in series with the inductor, a large resistance RC in parallel stable, because its amplitude would be ‘‘out of control.’’ What
with the capacitor, or both can model this. Solving such a circuit designers do to build oscillators with stable amplitude
circuit yields the following time domain differential equation is to make the term b in Eq. (18) depend on the instantaneous
oscillation amplitude A(t),
d 2 vC (t) dv (t)
2
+b C + ω2 vC (t) = 0 (14)
dt dt b(t) = b(A(t)) (21)

with and in such a way that b increases with A, b is negative for

A ⫽ 0 (to ensure initial startup), and b becomes positive above
1 R
b= + L a certain amplitude. This is called amplitude control. For in-
RCC L stance, assume that by adding some special circuitry to Fig.
(15)
1 + R /R 2 we are able to make
ω2 = L C
LC
b(A) = −b0 + b1 A (22)
The solution to Eq. (14) is
where b0 and b1 are positive constants (note that A is always
vC (t) = Vmaxe−bt/2 cos(ωo t + ρ) (16) positive). Initially, if A ⫽ 0, b ⫽ ⫺b0 is negative and the real
part of the poles is positive: amplitude A(t) increases exponen-
where 웆o2 ⫽ 웆2 ⫺ (b/2)2. Parameters Vmax and ␳ can be found tially with time. As A(t) increases b will eventually become
from the initial conditions vC(0) and v̇C(0), positive (poles with negative real part) and this will decrease
the amplitude A(t). The consequence of these two tendencies
vC (0) is that a steady state will be reached for which b ⫽ 0 and the
Vmax =
cos ρ amplitude is constant. Solving Eq. (22) for b ⫽ 0 yields the
 b  value of the steady state oscillation amplitude Ao,
v̇C (0) + vC (0) (17)
 2 
ρ = − arctan   b0
ωo vC (0) Ao = (23)
b1

However, circuit people prefer to solve Eq. (14) in the fre- Note that, as opposed to the ideal resonator, the steady state
quency domain by taking its Laplace transform, amplitude is independent of any initial conditions.
In general, a harmonic oscillator does not have to be a sec-
s2 + bs + ω2 = 0 (18) ond order system like the case of Eq. (14) or Eq. (18). It can
have any order. What is important is that it has a pair of
The solution to this equation provides the following poles complex conjugate poles whose real part can be controlled by
 the oscillation amplitude (so that the real part becomes zero
 2
b b b in the steady state), and that the rest of the poles (either com-
s1 = − + jω 1 − = − + jωo
2 2ω 2 plex conjugate or not) have negative real parts. The way b
 (19) depends on A does not have to be like in Eq. (22). Strictly
 2
b b b speaking, the conditions are
s2 = − − jω 1 − = − − jωo
2 2ω 2
b(A = 0) = −b0 < 0 for initial startup
which are two complex conjugate poles with a negative real b>0 for some A (24)
part. Circuit people know that when a system has a pair of db(A)
>0 for stable amplitude control
complex conjugate poles with a negative real part, the system dA
oscillates in a sinusoidal fashion with an amplitude that van-
ishes after some time. This is what Eq. (16) shows. The ampli- This will ensure stable oscillator operation. In what follows
tude of the oscillations A(t) ⫽ Vmaxe⫺bt/2 decreases exponen- we will concentrate on second order systems and will provide
tially with time. After a few time constants 2/b the amplitude two different ways of performing amplitude control.
 HARMONIC OSCILLATORS, CIRCUITS 635

AMPLITUDE CONTROL BY LIMITATION Rn

Iin
A very widely used method for oscillator amplitude control is
by limitation. This method usually is simple to implement, so
simple that many times it is implicit in the components used Vin
to build the resonator with initial startup. This makes practi- x2
cal circuits easy to build, although many times people don’t
understand the underlying amplitude control mechanism.
Let us consider the ideal resonator of Fig. 2 with an addi- (a)
tional resistor Rp in parallel to make it real. In order to assure
initial startup, let us put a negative resistor in parallel also. Vin +
Figure 3(a) shows a very simple way to implement one using Vo = 2 × Vin
–
a real (positive) resistor and a voltage amplifier of gain larger
than one (for example, two). Current Iin will be
R
V R
Iin = − in (25)
Rn

and the structure Resistor–Amplifier behaves as a grounded

(b)
negative resistor of value ⫺Rn. Figure 3(b) shows how to build
the amplifier using an operational amplifier and resistors. Rn
Connecting this negative resistor in parallel with a positive
one of value Rp ⫽ Rn ⫹ R⑀ (with R⑀ Ⰶ Rn), the equivalent paral-
lel resistance would be +
–
R2
Req =− n (26) Rn-R
R C L R
R

which is a very high but negative resistance. Connecting this

equivalent resistor in parallel with the ideal resonator of Fig.
2 provides an oscillator with initial startup. This is shown in (c)
Fig. 3(c).
Due to the fact that the operational amplifier’s output volt- Iin
age cannot go above its positive power supply VDD or below its
negative one VSS, the negative resistance emulator circuit just 2
described works as long as the amplifier output is below VDD Rn
and above VSS, or equivalently voltage Vin is between VDD /2 VSS /2
and VSS /2. It is easy to compute the current through Req as a Vin
function of Vin taking into account this saturation effect. Fig- R VDD /2
2 –
ure 3(d) shows the resulting curve. If VSS /2 ⱕ Vin ⱕ VDD /2 re- Rn Rn2
sistor Req behaves as a negative resistance of high value, but
if Vin is outside this range the slope of Iin versus Vin is that of
a positive resistance with much smaller value. In order to an- (d)
alyze what happens to the circuit of Fig. 3(c) when the oscil-
lating amplitude increases beyond VDD /2 or VSS /2 (whichever Figure 3. A real harmonic oscillator can be made by adding a nega-
is smaller) the concept of describing function can be used. tive resistor to a real resonator. (a) A negative resistor can be emu-
lated using a resistor and a voltage amplifier of gain greater than
unity. (b) Implementation of negative resistor using an operational
Describing Function amplifier and resistors. (c) Oscillator composed of capacitor inductor
and negative resistor. (d) Transfer characteristics of the negative re-
Figure 4 shows a sinusoidal signal x(t) applied to a nonlinear sistor implementation of (b).
element f(x) that outputs a distorted signal y(t). Signal y(t) is
no longer sinusoidal, but it is periodic. Consequently, a Fou-
rier series can describe it. The first (or fundamental) har- the first or fundamental harmonic only,
monic has the same frequency as the input sinusoid, while
the others have frequencies which are integer multiples of the y(t) ≈ N(A)x(t)
first one. If the block of Fig. 4 is used in a system such that x(t) = A sin(ωt)
the end signals will be approximately sinusoidal (like in a
2π /ω (27)
harmonic oscillator) then one can neglect all higher harmon- ω
N(A) = f (x(t)) sin(ωt) dt
ics of the Fourier expansion of y(t) and approximate it using πA 0
636 HARMONIC OSCILLATORS, CIRCUITS

x(t) where N(A) ⫽ ⫺R⑀ /Rn2 for A ⱕ VDD /2 and N(A) tends towards
2/Rn as it increases beyond VDD /2. Since N(A) is continuous
and monotonic, there will be a value of A (and only one) for
t which N(A) ⫽ 0. Let us call this value Ao. Note that Ao de-
pends only on the shape of the nonlinear function f( ⭈ ) of Fig.
3(d). Equation (29) is the equation of a resistor of value
Req ⫽ 1/N(A). For small values of A, Req ⫽ ⫺Rn2 /R⑀ (high resis-
tance but negative) and the oscillator possesses exponentially
increasing amplitude. When A increases beyond VDD /2, Req
y me
will become more and more negative until N(A) ⫽ 0. At this
point A ⫽ Ao, Req ⫽ 앝 and we have the ideal resonator. If A
x(t) y(t) increases further, Req becomes positive and the oscillator pre-
mc x sents exponentially decreasing amplitude. This represents a
stable amplitude control mechanism such that in the steady
me
state A ⫽ Ao and Req ⫽ 앝.

General Formulation
y(t)
In general, the block diagram of Fig. 5 describes a harmonic
oscillator with amplitude control by limitation, where H(s) is
a linear block (or filter) and f(x) is the nonlinear element re-
sponsible for the amplitude control. Applying the describing
t function method to the nonlinear block results in

y(t) = N(A)x(t) (31)

for a time domain description. For a frequency domain de-

scription it would be

Y (s) = N(A)X (s) (32)

Figure 4. A sinusoidal signal applied to a nonlinear element results,
in general, in a distorted output signal. On the other hand, input and output of the linear block or
filter are related in the frequency domain by

X (s) = H(s)Y (s) (33)

Note that this approximation makes y(t) to be linear with
x(t) so that the nonlinear block in Fig. 4 can be modeled by a Equation (32) and (33) result in
linear amplifier of gain N(A). Function N(A) is called the de-
scribing function of the nonlinear element f( ⭈ ). H(s)N(A) = 1 (34)
This approach is valid for any nonlinear function f( ⭈ ), but
If H(s) is a second order block it can be described by
let us consider only piece-wise linear functions, like in Figs. 3
and 4, with three pieces: a central linear piece of slope mc and a 1 s2 + a 2 s + a 3
two external linear pieces of slope me. When amplitude A is H(s) = (35)
s2 + a 4 s + a 5
small enough so that x(t) is always within the central piece
then N(A) ⫽ mc. When A increases beyond the central piece which together with Eq. (34) yields an equation of the form
N(A) will change gradually towards value me. In the limit of
A ⫽ 앝 the describing function will be N(A) ⫽ me. Computing s2 + sb + ω2 = 0
the first Fourier term provides the exact expression (let us
a1 − a2 N(A)
assume VSS ⫽ ⫺VDD for simplicity). If A ⱖ VDD /2 b=
1 − a1 N(A) (36)
   − a3 N(A)
   2 a
me − mc  −1 VDD V VDD ω2 = 5
N(A) = me − 2 sin + DD 1−  1 − a1 N(A)
π 2A 2A 2A
(28)
H(s)
and if A ⱕ VDD /2
Y(s) y(t) x(t) X(s)
N(A) = mc (29)
f(x)
Applying the describing function method to the nonlinearity
of Fig. 3(d) results in
Figure 5. A general block diagram of an oscillator with amplitude
control by limitation consists of a linear filter and a nonlinear ampli-
Iin = N(A)Vin (30) tude controlling element connected in a loop.
 HARMONIC OSCILLATORS, CIRCUITS 637

For small amplitudes N(A) is equal to some constant (for ex- C1 R1

ample n0) and Eq. (36) is called the characteristics equation.
It must be assured that b(A ⫽ 0) ⬍ 0. This is usually referred
to as the oscillation condition. For stable amplitude control it
should be v1 v2
k0

db(A)
>0 (37) C2 R2
dA

and 웆2 must be kept always positive for all possible values of

A. In practice, it is desirable to make in Eq. (35) a1 ⫽ a3 ⫽ 0, (a)
which will make 웆2 and b not be coupled through a common
parameter. This way the oscillation amplitude and frequency R1
C1
can be controlled independently.
v+
A Practical Example: the Wien-Bridge Oscillator
v1
+ v–
In a practical circuit it is not convenient to rely on inductors v2
because of their limited range of inductance values, high
price, and, in VLSI (very large scale integration) design, they C2 –
are not available unless one operates in the GHz frequency R2 Rm
range. But it is possible to implement the filter function of
Fig. 5 without inductors. The Wien-Bridge oscillator of Fig. 6
is such an example. Figure 6(a) shows its components: two
resistors, two capacitors, and a voltage amplifier of gain k0. (k0–1) Rm
Figure 6(b) illustrates an implementation using an opamp
and resistors for the voltage amplifier, and Fig. 6(c) shows its
piece-wise linear transfer characteristics. Using the describ-
(b)
ing function, the effective gain of the amplifier k(A) can be
expressed as a function of the sinusoidal amplitude A at
v2
node v1,
VDD

k(A) = k0 N(A) (38)

where k0N(A) is the describing function for the function in
Fig. 6(c) and is given by Eq. (28) with mc ⫽ k0, me ⫽ 0, and
the breakpoint changes from VDD /2 to VDD /k0. Consequently,
the frequency domain description of the circuit in Fig. 6(a) is
s2 + sb + ω2 = 0
1 1 k N(A) − 1
b= + − 0
R2C2 R1C1 R1C2 (39)
1 1
ω2 =
R1C1 R2C2
For initial startup it must be b ⬍ 0 for A ⫽ 0. The final ampli-
tude A0 is obtained by solving b(A0) ⫽ 0, and the frequency of
the oscillation is 웆 (in radians per second) or f ⫽ 웆/2앟 (in
hertz). Optionally, the diodes in Fig. 6(b), connected to voltage
sources v⫹ and v⫺, can be added to control the oscillation am-
plitude. These diodes change the saturation voltage VDD of
Fig. 6(c), and hence will modify the describing function N(A).
In general, when using amplitude control by limitation, a
practical advice is to make ⫺b0 as close as possible to zero but
without endangering its sign. This way the nonlinear element
will distort very little the final sinusoid, because it needs to
use only a small portion of its nonlinear nature to make b(A)
become zero. If ⫺b0 is too large the resulting waveform will
probably look more like a triangular signal than a sinuoidal
one.
k0
v1
–V
DD
(c)
Figure 6. The Wien-Bridge oscillator is an example of an oscillator
that does not require an inductor. (a) It consists of two resistors, two
capacitors, and a voltage amplifier circuit. (b) The voltage amplifier
can be assembled using an opamp and two resistors. (c) The resulting
voltage amplifier has nonlinear transfer characteristics.
AMPLITUDE CONTROL BY AUTOMATIC GAIN CONTROL
Let us illustrate the amplitude control by AGC (automatic
gain control) using an OTA-C oscillator. An OTA (operational
transconductance amplifier) is a device that delivers an out-
put current I0 proportional to its differential input voltage
Vin. Figure 7(a) shows its symbol and Fig. 7(b) its transfer
characteristics. The gain (slope gm in Fig. 7(b)) is called the
transconductance. This gain is electronically tunable through
voltage Vbias (depending on the technology and the design, the
tuning signal can also be a current). Using these devices, the
self-starting oscillator of Fig. 7(c) can be assembled. Note
that gm1, gm2, and C1 emulate an inductance of value L ⫽
638 HARMONIC OSCILLATORS, CIRCUITS

To assure initial startup Vb3 and Vb4 must be such that gm3 ⬎
+ I0 gm4. By making gm3 (or gm4) depend on the oscillation ampli-
Vin gm tude A, an AGC for amplitude control can be realized. This is
illustrated in Fig. 7(d) where the box labeled oscillator is the
–
circuit in Fig. 7(c), the box labeled PD is a peak detector, the
large triangle represents a differential input integrator of
time constant ␶AGC, the small triangle is an amplifier of gain
Vbias
m necessary for stability of the AGC loop, and the circle is a
(a) summing circuit. The output of the peak detector Apd(t) follows
(with a little delay) A(t), the amplitude of the sinusoid at V0.
I0
The error signal resulting from subtracting Apd and Vref is in-
ISS
tegrated and used to control gm4. If Apd ⬎ Vref gain gm4 will
gm Vin increase (making b positive, thus decreasing A), and if Apd ⬍
Vref gain gm4 will decrease (making b negative, thus increas-
ing A). In the steady state A ⫽ Apd ⫽ Vref and gm4 will automat-
–
ISS ically be adjusted to make b ⫽ 0. Note that Vref must be such
that the node voltages are kept within the linear range of
(b) all OTAs, otherwise amplitude control by limitation may be
taking place.
Vb3 OTA-C oscillators are convenient for AGC because their
gain can be adjusted electronically. In order to do this for the
+ – Wien-Bridge oscillator of Fig. 6, either a capacitor or a resis-
gm1 gm3 tor must be made electronically tunable (using a varicap or a
– + JFET). Also, OTA-C oscillators are interesting because they
Vbf V0
do not need resistors, and this is very attractive for VLSI in
CMOS technology where resistors have very bad electrical
+ – characteristics and a limited range of values.
gm2 gm4
C1 C2 +
– Stability of Automatic Gain Control Loop
An AGC loop for amplitude control, like the one in Fig. 7(d),
Vb4
presents a certain dynamic behavior which can be analyzed
(c) in order to (1) make sure it is a stable control loop and (2)
optimize its time response.
In Fig. 7(d) the peak detector output Apd(s) can be modeled
V0 as a delayed version of A(s),
Vbf Oscillator
Apd (s) = A(s)(1 − sτpd ) (41)
Vb4

m where Apd(s) and A(s) are the Laplace transforms of the small
signal components of Apd(t) and A(t), respectively. Signal
Apd Vb4(s) (the Laplace transform of small signal component of
+
PD
Vb4(t)), according to Fig. 7(d) satisfies

– Vref 1  
Vb4 (s) = (1 + smτAGC )Apd (s) − Vref (s) (42)
sτAGC
(d)

Figure 7. An oscillator with amplitude control by AGC can be made
easily with OTAs and capacitors (OTA-C). (a) An OTA delivers an
output current proportional to its differential input voltage. (b) It has
nonlinear transfer characteristics. (c) A self-starting OTA-C oscillator
can be made with four OTAs and two capacitors. (d) The amplitude
control by AGC requires an additional peak detector and integrator.
C1 /(gm1gm2), gm3 emulates a negative resistance of value R3 ⫽
⫺1/gm3, and gm4 emulates a positive one of value R4 ⫽ 1/gm4.
The characteristics equation of the OTA-C oscillator is
s2 + bs + ω2 = 0
g − gm3
b = m4
C2
gm1 gm2
ω =
2
C1 C2
and controls parameter b in Eq. (40). Let us assume that b(t)
follows instantaneously Vb4(t) so that
b(s) = αVb4 (s) (43)
Now what is left in order to close the control loop is to know
how the amplitude A(t) (or A(s) in the frequency domain) at
node V0 depends on b.
This dependence can easily be obtained from the time-do-
main differential equation (like Eq. (14)) in the following way:
assume b(t) is a time dependent signal that has small changes
around b ⫽ 0 and keeps A(t) approximately constant around
A0. Then the solution to V0(t) (or vC(t) in Eq. (14)) can be writ-
(40)
ten as
Vo (t) = A(t) cos(ωot + ϕ) (44)
 HARMONIC OSCILLATORS, CIRCUITS 639

where A(t) ⫽ A0 ⫹ a(t) and 兩a(t)兩 Ⰶ A0. Substituting Eq. (44)

into vC(t) of Eq. (14) yields the following coefficients for the
cos( ⭈ ) and sin( ⭈ ) terms, respectively, which must be identi-
s1 s2 sn
cally zero [if Eq. (44) is indeed a solution for Eq. (14)],
Digital ⋅⋅⋅
R2
bus
d 2 A(t) dA(t) A(t) 2r 2 2r 2 nr 2 nr
+ b(t) + b2 (t) =0
dt 2 dt 4 (45)
dA(t)
2 + A(t)b(t) = 0
dt
Figure 8. The frequency of the Wien-Bridge oscillator can be digi-
The first equation is not of much use, but from the second it tally controlled by replacing one of the resistors by a binarily
follows that weighted resistor array controlled through a digital data bus.

− 12 tt b(t )dt
A(t) = A(t0 )e 0 (46)
trolled capacitor (varicap) is needed. Digital control can easily
be implemented by using a binary weighted array of resistors
When the AGC loop is in its steady state A(t) ⫽ A0 ⫹ a(t) and
or capacitors that are switched in and out of the circuit by
the integral is a function that moves above and below zero
means of a digital bus. This is exemplified in Fig. 8 for resis-
but is always close to zero. Consequently, the exponential can
tor R2. Signals si are either 0 when the switch is open or 1
be approximated by its first order Taylor expansion resulting
when it is closed. This yields
in
! " ! "

1 1 1 n
si 1
1 t = + = dn (50)
A(t) ≈ A(t0 ) 1 − b(t) dt R2 r 2 n 2 i r
2 t0 i=1


t (47)
A(t0 ) t A
⇒ a(t) ≈ − b(t) dt ≈ − 0 b(t) dt where dn is a number that ranges from 1/2n to 1 in steps of
2 t0 2 t0 1/2n. Number dn is represented in binary format by the bits
兵snsn⫺1 . . . s2s1其.
In the frequency domain this is The OTA-C oscillator of Fig. 7 is much better suited for
analog or continuous control of frequency. If gm1 ⫽ gm2 and
A0 C1 ⫽ C2, the frequency is equal to 웆 ⫽ 2앟f ⫽ gm1 /C1. Since
A(s) ≈ − b(s) (48)
2s voltage Vbf in Fig. 7(d) controls simultaneously gm1 and gm2
(making them equal), this voltage can be used directly to con-
From Eqs. (41–43) and (48) a loop equation for the AGC con- trol the frequency of the VCO.
trol can be written
Whether a VCO is made with OTAs and capacitors, or with
Vref (s) resistors, capacitors, and opamps, or uses some other tech-
A(s) = nique, in general it turns out that the frequency does not have
s2 k1 + sk2 + 1
a linear dependence on the control voltage. In practical cir-
2τ (49) cuits it also happens that if the control voltage is maintained
k1 = AGC − mτAGC τpd
αA0 constant, the frequency may change over long periods of time
k2 = mτAGC − τpd due to temperature changes which cause device and circuit
parameters (such as transconductance and resistance) to
This equation represents a stable control system if the poles drift. Both problems can be overcome by introducing a fre-
have negative real part. This is achieved if k1 ⱖ 0 and k2 ⬎ 0. quency control loop.
Parameters k1 and k2 can also be optimized for optimum am-
plitude transient response (for example, after a step response
FREQUENCY CONTROL LOOP
in Vref (t)).
Figure 9(a) shows the basic concept of a frequency control loop
VOLTAGE CONTROLLED HARMONIC OSCILLATORS for VCOs. It consists of a VCO (for example, the one in Fig.
7(d)), a differential input voltage integrator, and a frequency
An oscillator whose frequency can be electronically controlled to voltage converter (FVC) circuit. Voltage VCO is now the ex-
is required in many applications. Such an oscillator is called ternal control of the VCO frequency. The FVC circuit delivers
a voltage controlled oscillator or VCO, although sometimes an output voltage VFVC that depends linearly on the frequency
the control parameter can also be a current. f of its input signal VOSC,
In the case of the Wien-Bridge oscillator of Fig. 6 the fre-
quency of oscillation 웆 is controlled by R1, R2, C1, and C2. VFVC = ρ f + VF0 (51)
Changing one or more of these parameters would enable ex-
ternal control of the frequency. In order to have an electronic Parameters ␳ and VF0 must be constants and should not de-
control there are two options: (1) continuous or analog control, pend on temperature or technological parameters that change
and (2) discrete or digital control. from one prototype to another. If such an FVC is available,
For analog control of the Wien-Bridge oscilator of Fig. 6 the circuit in Fig. 9(a) would stabilize at VFVC ⫽ VCO. According
either a voltage controlled resistor (JFET) or a voltage con- to Eq. (51), this means that the resulting oscillation fre-
640 HARMONIC OSCILLATORS, CIRCUITS

t0

VOSC Monostable u(t)

Vbf VOSC
VCO v(t)
+ – PD
go g0
Vref
– +
VFVC
– FVC C
+
VCO

(a) (b)

v(t)
u(t)

Figure 9. A frequency control loop can provide a linear dependence between tuning
voltage and VCO frequency, and can also make this dependence temperature and pro-
totype independent. (a) It can be made by adding a FVC and an integrator to a VCO.
t0
(b) The FVC can be made with a calibrated monostable, a reference voltage, a peak
detector, two OTAs, a capacitor, and a switch. (c) After a transient the FVC output T t
stabilizes to a steady state voltage which depends linearly on the input signal fre-
quency. (c)

quency f 0 depends on VCO as
VCO − VF0
fo =
ρ vm+1 =
which is linear and temperature independent.
A possible implementation with OTAs of the FVC is shown
in Fig. 9(b). It uses two OTAs of transconductance g0, a capac-
itor C, a peak detector, a switch, a temperature independent
voltage reference Vref , and a monostable triggered by the oscil-
lating signal VOSC. During each period T ⫽ 1/f of signal VOSC
the monostable delivers a pulse of constant width t0, which
must be temperature independent and well calibrated. Many
times it is convenient to add a sine-to-square wave converter
(and even a frequency divider) between VOSC and the mono-
stable. The circuit of Fig. 9(b) uses three components that are
not temperature independent and may vary over time and
from one prototype to another: the two OTAs and the capaci-
tor. However, provided that both OTAs have the same trans-
conductance (which is a reasonable assumption for VLSI im-
plementations), the resulting parameters ␳ and VF0 do not
depend on C nor g0. An example of the time waveforms of
u(t) and v(t) of Fig. 9(b) is shown in Fig. 9(c). During each
period T of VOSC the monostable is triggered once, turning the
switch ON during a time t0. While the switch is ON capacitor
C is charged by a constant current g0(Vref ⫺ v(t)), and when
the switch is OFF a constant current of value ⫺g0v(t) dis-
charges it. The output of the FVC v(t) changes from cycle to
cycle but is constant during each cycle. If vm is its value dur-
ing one cycle and vm⫹1 for the next one, it follows that
g0 (Vref − vm ) go vm+1
u(t + T ) = u(t) + to − (T − t0 )
C C
where u(t) is taken at one of the peaks: u(t) ⫽ vm and u(t ⫹
T) ⫽ vm⫹1. Consequently,
(52) vm (C − g0t0 ) + Vref g0t0
(54)
C + g0 (T − t0 )
In the steady state of the FVC vm⫹1 ⫽ vm. Applying this condi-
tion to Eq. (54) and calling VFVC the stabilized value of vm,
yields
Vreft0
VFVC = = Vref t0 f (55)
T
Consequently, the circuit of Fig. 9(b) implements a FVC with
␳ ⫽ Vref t0 and VF0 ⫽ 0, which both are temperature and proto-
type independent.
FURTHER CONSIDERATIONS
The different concepts and considerations mentioned so far
have been illustrated with practical circuits using either re-
sistors, capacitors, and opamps, or using OTAs and capaci-
tors. There are many other circuit techniques available that
can be used to implement the different blocks and equations
needed for stable harmonic oscillator circuits. Some of these
techniques could be continuous current mode, switched capac-
itor, switched current, digital circuit techniques, or even any
combination of these techniques.
Depending on the frequency range of the oscillator it may
be necessary to consider circuit parasitics that have not been
mentioned so far. For example, opams and OTAs both have
nonideal input and output impedances, leakage currents, and
most importantly gains which are frequency dependent. All
(53)
these parasitics result in modified characteristics equations.
 HARMONIC OSCILLATORS, CIRCUITS 641

A very sensitive parameter to parasitics is the oscillation con-
dition ⫺b0 required for initial startup. Since in practice it is
desirable to have ⫺b0 very close to zero but still guarantee its
negative sign, it is apparent that parasitics can result in ei-
ther very negative (resulting in very distorted sinusoids) or
positive (resulting in no oscillation) values. Each circuit tech-
nique has its own parasitics, and depending upon the in-
tended frequency range, they will have a different impact on
the final oscillator performance. Consequently, for good oscil-
lator design the dominant parasitics need to be well known
and taken into account.
Another interesting and advanced issue when designing
oscillators is distortion. Both amplitude control mechanisms,
limitation and AGC, are nonlinear and will introduce some

V0 –

Apd

CPD
Idischarge

V 01 –

Apd +

t
V0
–V01 –

(a) +

V0 –
V 02 –
+
+

–V0 –
–V02 –
+
+
Apd
Apd

CPD
Idischarge
CPD
Idischarge

Apd Apd

t t

V0 –V0

(b) (c)

Figure 10. Possible implementations for a peak detector: (a) One phase based (or half wave
rectifier based), (b) Two phase based (or full wave rectifier based), and (c) Four phase based
peak detector.
642 HARTLEY TRANSFORMS

degree of distortion. Is there a way to predict how much dis- where,

tortion will render an oscillator?
|xn | |x1 |
(60)
Distortion for Amplitude Control by Automatic Gain Control |yn | |y1 |
In an oscillator with AGC for amplitude control, like in Fig.
7(d), the element that introduces most of the distortion is the In general, this problem is solved numerically for a finite set
peak detector. Figure 10 shows examples of peak detectors of harmonics. Let N be the highest harmonic to be computed.
based on one-phase or half-wave [Fig. 10(a)], two-phase or Since f(x(t)) is also periodic, computing its Fourier series
full-wave [Fig. 10(b)], and four-phase [Fig. 10(c)] rectifying expansion yields that of y(t). Therefore, given a set of parame-
principles. For the four-phase case, either the oscillator ters for x(t) 兵x1, . . . xN, ␸2, . . . ␸N其 the set of parameters 兵y1,
should provide two phases with 앟/2 shift, or an additional in- . . . yN, ␾1, . . . ␾N其 for y(t) can be obtained this way. By
tegrator is needed. Peak detectors with more phases can be applying each component of y(t) (characterized by yn and ␾n)
implemented by linearly combining previous phases. Increas- to filter H(s) yields the corresponding component for x(t),
ing the number of phases in the peak detector results in
xn = yn |H( jnω0 )|
faster response [delay ␶pd in Eq. (41) is smaller for more (61)
phases] and less distortion. However, all phases have to pre- ϕn = φn + phase(H( jnω0 ))
sent the same amplitude, otherwise distortion will increase.
In practice, as the number of phases increases it becomes By iterating this procedure until all values xn, yn, ␸n, and ␾n
more difficult (due to offsets and component mismatch) to converge, the distortion of x(t)
keep the amplitude of the phases sufficiently equal. 
In the peak detectors of Fig. 10, whenever one of the N  2
xn
phases becomes larger than Apd it slightly turns ON its corre- THD(x) = (62)
n=2
x1
sponding P transistor injecting a current into CPD until Apd
increases sufficiently to turn OFF the P transistor. The dis-
or y(t)
charge current ensures that Apd will follow the amplitude of
the oscillations if it decreases. Increasing Idischarge results in 
N  2
faster response but higher distortion. Whatever peak detector yn
THD(y) = (63)
is used, waveform Apd(t) is not constant nor sinusoidal. It has n=2
y1
a shape similar to those shown in Fig. 10. Since Apd(t) is peri-
odic its Fourier series expansion can be computed, can be predicted.

∞
Apd (t) = A0 + an cos(nω0t + ϕn ) (56) Reading List
n=1
K. K. Clarke and D. T. Hess, Communication Circuits: Analysis and
The high-order harmonic components 兵a2, a3, . . .其 are those Design, Reading, MA: Addison-Wesley, 1978.
which contribute to distortion at node V0 [in Fig. 7(d)]. A. Gelb and W. Vander Velde, Multiple Input Describing Functions
Applying the filtering functions that go from node Apd, and Nonlinear System Design, New York: McGraw-Hill, 1968.
through Vb4, to V0 [Eqs. (41–43) and (48)] to these higher- E. J. Hahn, Extended harmonic balance method, IEE Proc. Part-G,
order harmonics provides their amplitudes at node V0, Circuits Devices Syst., 141: 275–284, 1994.
B. Linares-Barranco et al., Generation, design and tuning of OTA-C
αAo high-frequency sinusoidal oscillators, IEE Proc. Part-G, Circuits
|A0n | = |1 + jnω0 mτAGC ||1 − jnω0 τpd ||an | (57)
2τAGC n2 ωo2 Devices Syst., 139: 557–568, 1992.
E. Vannerson and K. C. Smith, Fast amplitude stabilization of an RC
The total harmonic distortion at the output of the oscillator is oscillator, IEEE J. Solid-State Circuits, SC-9: 176–179, 1974.
then defined as
BERNABÉ LINARES-BARRANCO

∞  2 A´ NGEL RODRÍGUEZ-VÁZQUEZ
A
THD(V0 ) = 0n (58) National Microelectronics Center
n=2
A0 (CNM)

Distortion for Amplitude Control by Limitation

This problem is computationally complicated but can be HARMONICS. See POWER SYSTEM HARMONICS.
solved by harmonic balance. Consider the general block dia-
gram of Fig. 5. In the steady state, periodic waveforms x(t)
and y(t) can be expressed by their respective Fourier series
expansions

∞
x(t) = x1 cos(ω0t) + xn cos(nω0t + ϕn )
n=2
(59)

∞
y(t) = yn cos(nω0t + φn )
n=1
J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering
Copyright
c 1999 John Wiley & Sons, Inc.

HYSTERESIS IN CIRCUITS
Hysteresis, in simple terms, is the tendency of a system to resist change. This tendency may be created in a
variety of ways, and so we may observe hysteresis in many diverse kinds of systems: electrical, mechanical,
physical, biological, and others. Once a system with hysteresis is in one state, it requires a suitable amount of
energy to overcome this tendency in order to move the system to another state. Hysteresis can also describe how
a system “remembers” a past response. This “memory” may be considered a storage of energy, like a capacitor
or inductor, but is really a form of dynamic tension.
Hysteresis is a nonlinear phenomenon. Thus, it cannot be described using simple linear operations (ad-
dition, subtraction, multiplication, differentiation, etc.). The mathematical description of hysteresis has been
an intense area of research in recent years. However, hysteresis has been known and understood by electrical
engineers for many years and in numerous forms: as a cause of energy loss and heating in the ferrite cores of
transformers, as a fundamental building block in the design of some electronic oscillators, and so on.

The Hysteresis Function

The hysteresis function can best be illustrated by comparison using the transfer functions shown in Fig. 1.
The input to each function is given on the horizontal x axis, and the output is given on the vertical y axis. The
curve in Fig. 1(a) is a simple piecewise linear transfer function with gain A = y/x = 2 limited above and below
by ±2. The three curves are identical, except that there exists a region in the domain of x for the curve in Fig.
1(b,c) for which there are two possible solutions in the range of y. In this example, the curve in Fig. 1(a) may
be expressed as

However, for the curve in Fig. 1(b), one must know something about the previous value of x in order to determine
the corresponding y:

The determination of y based on previous values of x is illustrated by the arrows in Fig. 1(b). If the first value
of x is larger than 2, then the output value of y begins at 2 and follows line segment A. If the following values
of x remain larger than −2, the resulting values of y follow the arrows around the curve to the left, along
1
2 HYSTERESIS IN CIRCUITS

Fig. 1. Comparison of (a) simple nonlinear transfer function with (b) positive hysteresis and (c) negative hysteresis. Note
that the directions of the arrows for (b) and (c) traverse the curve in opposite directions.

segments A and B. If, however, the value of x falls below −2, the resulting values of y will follow the arrows on
line segments C and D. This tracing of the hysteresis curve is known as positive hysteresis. There is one other
way to trace the curve, as shown in Fig. 1(c). This alternative path around the hysteresis curve is negative
hysteresis.
 HYSTERESIS IN CIRCUITS 3

Hysteresis in Ferromagnetism

Ferromagnetic materials include the elements iron (Fe), cobalt (Co), and nickel (Ni), and many of their alloys
and composites, as discussed by Plonus (1). The use of ferromagnetic materials in electrical and electronic
systems can be found in transformers, motors, generators, inductors, and the like (see Magnetic Materials and
Induction Motor Drives).

Hysteresis in Electronic Systems

In addition to ferromagnetic systems, electronic systems may also exhibit hysteresis. In these instances, there
are usually two major contributing features: upper and lower limits, such as power supply voltages, and a
positive feedback loop. Hysteresis can be used effectively in electronic systems as a building block in oscillator
design, as an input amplifier to help reject noise, or as a delay function.
Example: An Opamp Hysteresis Function. One simple hysteresis design using operational ampli-
fiers (see Operational Amplifiers) is given in Fig. 2. Note that opamp 1 and resistors R1 and R2 constitute the
actual hysteresis element. Resistor R2 connects the output of opamp 1 to its positive input. This large amount
of positive feedback will force the circuit voltage at vh to be either the positive supply voltage V D or the negative
supply voltage V S . If we sweep the input voltage vi , the hysteresis voltage vh will have the transfer function
shown at the top of Fig. 3. To find the values of input voltage vi for which the hysteresis voltage vh will switch,
we have

If we make V R = 0, the equation in Eq. (3) simplifies to

This gives for the upper and lower trip voltages V U and V L respectively

and for the hysteresis width V HW

Thus, the trip voltages for the hysteresis may be designed using a ratio of resistors and the power supply
voltages. However, it is usually undesirable to have a voltage in such a system that swings from rail to rail.
To prevent this we may use another opamp amplifier such that the hysteresis voltage vh is attenuated. This
is shown using opamp 2 at the top of Fig. 2. By making R3 much larger than R4 , the output voltage vo may
be designed so that its signal swing is well away from the power supply voltages, preventing the output of
the hysteresis from saturating any following stages. This attenuation is shown at the bottom of Fig. 3. Also
note that this second amplifier is in the inverting configuration. Thus the trip voltages for the hysteresis are
4 HYSTERESIS IN CIRCUITS

Fig. 2. An electronic hysteresis can be constructed using monolithic operational amplifiers. The opamp at the bottom of
the figure has positive feedback. The amplifier at the top is in the inverting configuration. The center of the hysteresis can
be adjusted using V R .

determined by V D , V S , R1 , and R2 , and the output limits are determined by V D , V S , R3 , and R4 . We may
construct an inverting hysteresis by exchanging V i with V R in Fig. 2.
Circuit Model. In some cases it is desirable to have a model of the hysteresis function for use in
a hierarchical design instead of a complete circuit, as shown by Varrientos and Sanchez-Sinencio (2). The
hysteresis function may then be modeled as shown in Fig. 4.
A circuit symbol for the hysteresis function is shown in Fig. 4(a). The underlying model is given in Fig.
4(b). The resistors ra and rb are used as a voltage divider, and resistor rd and capacitor cd constitute a high-pass
filter, such that the difference voltage va − vb is an all-pass filtering of the differential input voltage vp − vn .
This difference voltage is then converted to a current using the transconductance io . The transconductance
equation is given as

From this equation, one may note that this transconductance current io depends somewhat on the output
voltage vo across it, and that this dependence is positive. Therefore, the term vo − va is positive feedback. Also,
note that the term va − vb is a phase delay term, making the hysteresis element a function of the speed and/or
frequency of the input signal vp − vn . Generally, this is the case for practical implementations.
The resistor ro and capacitor co at the output of the hysteresis element help determine the rise and fall
times, or slew rate, of the output voltage. The diodes dn and dp and voltages vn and vp define the limits of the
output voltage. For this model, the voltages vn and vp also give the trip voltages, like those illustrated in Fig.
3. Finally, this circuit model can be described using the circuit simulator SPICE. An example appears in Fig.
5. In this example, the diode model used gives a near-ideal diode, clamping the limit voltages at 0.5 V and the
trip voltages at twice the limit voltages, or ±1 V.
 HYSTERESIS IN CIRCUITS 5

Fig. 3. The transfer functions for the opamp hysteresis in Fig. 2. The output of the first opamp will have the transfer
function shown at the top. Note that it has limits at the power supply voltages. After attentuation using the second opamp,
the transfer function will look like the trace at the bottom of the figure. The trip voltages are given by the first opamp, and
the output limits are given by the second opamp.

Higher-Order Hysteresis

As was mentioned in the introduction, a hysteresis element may be thought of as a single energy storage unit.
The amount of storage is determined by the width and height of the hysteresis. It is then possible to increase
the order of the system in which the hysteresis appears, for example, by increasing the number of hysteresis
storage elements. To do this, we may add other hysteresis elements in a given system, or we may increase
the number of storage elements in a given hysteresis element. This latter method of increasing the order of a
hysteretic element gives higher-order hysteresis. Hysteresis of this type has uses in complex nonlinear systems
such as chaotic oscillators (3) (see Chaos, Bifurcation, and their control).
6 HYSTERESIS IN CIRCUITS

Fig. 4. The hysteresis symbol (a) can be modeled using the simple nonlinear circuit (b) shown at the bottom of the figure.
All the components are linear except for the diodes dp and dn . The trip voltages and output limits are a function of vp and
vn .

Linear Combination. By combing several hysteresis elements linearly using inverting and/or summing
amplifiers, higher-order hysteresis functions can be derived (2). A block diagram of a general design approach
for higher-order hysteresis is given in Fig. 6. The approach begins with the design of trip values for each
hysteresis by determining a reference value to shift the hysteresis either left or right and then amplifying (or
attenuating) the hysteresis output of each element. Continuing, we may then combine the outputs of several
such elements to construct a composite hysteresis with many storage regions. By example, we may combine
two hysteresis elements shown in Fig. 2 to construct a composite hysteresis with two nonoverlapping storage
regions. This result is shown in Fig. 7. The value of ε gives the hysteresis width, δ is the distance of the center
of each width from the origin, and D is the magnitude of the limit.
Differential Hysteresis. In addition to linear combinations, complex hysteresis functions can also be
constructed using cross-coupled feedback and nonlinear combinations as shown by Varrientos and Sanchez-
Sinencio (2). One example appears as Fig. 8. This hysteresis element is comprised of two hysteresis elements
and two comparators referenced to a common ground. Because of the finite response of each amplifier, this
hysteresis composite will have two hysteresis regions. The result is similar to the transfer function given for
linear combinations in Fig. 7. Note that by increasing the limit voltages on the comparator elements, we also
vary the reference voltage for each hysteresis. The result is that each storage region reduces in width ε and
increases in distance δ from common ground.
 HYSTERESIS IN CIRCUITS 7

Fig. 5. This SPICE input file can be used to model the hysteresis shown in Fig. 4. The parameters given for the diode
model will make the diodes almost ideal.

Fig. 6. Higher-order hysteresis can be constructed using linear combinations of simpler hysteresis elements. Here the
elements are combined using amplifiers (multiplication) and summing nodes.

Mathematical Descriptions

Often, hysteresis is found in systems with steady-state sinusoidal solutions where the input to the hysteresis
is sinusoidal. The hysteresis, whether desirable or not, contributes to the solution, and as engineers we would
like to know the extent of the interaction between the linear and nonlinear portions of the system.
Describing Functions. One way of doing this is with the use of describing functions as shown by Gelb
and Vander Velde (4). A describing function is a nonlinear function in the steady-state s domain. Thus, we may,
using the describing function for a given nonlinearity, solve for the solution of a system using linear algebra.
Differential Model for Hysteresis. Often, however, we would like a time-varying, or transient, solution
for our system with hysteresis, where the s-domain description is not sufficient. In recent years, mathematicians
have been investigating the underlying fundamental dynamics of hysteresis as shown by Visintin (5). It remains
an active area of research because of the difficulty mathematicians and engineers have had in constructing
a sufficiently accurate differential expression for many types of common hysteresis, including the hysteresis
found in ferromagnetism.
8 HYSTERESIS IN CIRCUITS

Fig. 7. The transfer function of a second-order hysteresis function. Note that there are two hysteresis regions, one for
each simple hysteresis element. The value of D is the upper and lower limit, ε is the hysteresis width, and δ is the distance
from the center of each hysteresis width of the origin.

Fig. 8. Higher-order hysteresis can also be constructed using cross-coupling and nonlinear feedback. The output limits
of the comparators shown determine the width of the hysteresis and their offset from the origin.

However, several differential expressions exist. One of the most common is a variation on the differential
equation given by Rössler (6):

where x(t) is the time-varying input and y(t) is the output. The values of S and D are derived from the upper
and lower trip values; generally, S = 2.0/(V U − V L ) and D = SV L + 1.0. Loss in the hysteresis is due to a variety
of sources in practical systems and is modeled with the damping factor δ. The value of ε is small so that the
hysteresis response reaches its saturation quickly.
 HYSTERESIS IN CIRCUITS 9

Fig. 9. In CMOS design, is it possible to design hysteresis using currents as parameters? Here the upper and lower trip
input currents are determined by I1 and I2 .

Another popular hysteresis equation is the Bouc–Wen differential equation used by Wong, Ni, and Lau
(7):

where the quantities κ, β, γ, and n are system parameters that determine the shape and magnitude of the
hysteresis this equation produces. The parameters κ, β, and n are positive real numbers, and γ may be a positive
or negative real number. Typical values are κ = 1.0, β = 0.1, γ = 0.9, and n = 1.0.
Both of the equations above give hysteretic responses that are like those given for ferromagnetic materials
(see Magnetic Materials) and for the monolithic responses that follow. The difficulty in using such equations
is that, unlike the circuit model given above, they are sensitive to the speed of the input signal and will have
responses that vary widely for a given set of inputs. Generally, these equations work best with systems that
have well-behaved limit cycles as solutions, sinusoidal oscillations being one example .

Monolithic Implementations

In integrated circuit design, simple implementations of hysteresis elements can be constructed. One such
hysteresis element, proposed by Wang and Guggenbühl (8), is shown in Fig. 9. This hysteresis is performed
in the current mode, since the signals and the trip values are determined by currents rather than voltages. In
this circuit, the input current ii is mirrored through the current mirror M 5 , M 6 into the high impedance node
vo . If the input current ii is smaller than I1 , the voltage at vo will be near V D , turning on M 1 and turning off
M 2 . The total current flowing into vo from the current mirror M 3 , M 4 will now be I1 + I2 . Now, in order to lower
the voltage at vo , the input current ii must exceed I1 + I2 . Once this happens, the voltage at vo will be near V S ,
turning off M 1 and turning on M 2 , so that the current entering the node vo from the current mirror M 3 , M 4
will again be I1 . The upper and lower trip current values will be
10 HYSTERESIS IN CIRCUITS

Fig. 10. An input signal to a hysteresis element that is fast in comparison with the switching speed of the hysteresis will
cause the width of the hysteresis to increase. If the input signal is too fast, the phase of the hysteresis transfer function
will be inverted.

The hysteresis width IHW will be IH − IL = I2 . Thus the hysteresis is easily adjustable using only two currents,
and is independent of the power supply voltages. However, matching between the transistors of each current
mirror and the slew rate of the output node vo may be critical for fast-moving input signals.
Speed Tradeoffs. As was mentioned earlier, the width of the storage region of the hysteresis element
will be affected by the speed and/or frequency of the input signal. This is because every practical implementation
has practical limits to how fast a signal or node can move. These limits are a function of the voltage swing, load
and parasitic capacitances, and bias currents. These effects are modeled in the hysteresis circuit model given
in Fig. 4. A transient response of this hysteresis for 1 kHz sinusoidal signal is given in the top trace of Fig. 10.
If we keep the frequency of the input signal constant, but increase the value of the capacitance cd in Fig. 4,
we will increase the response time (phase delay) of the hysteresis. The effect will be to slow the hysteresis down
with respect to its input signal. The effect of increasing the response time is shown in the second trace of Fig.
10. Even though we have not changed the value of the trip or limit voltages vp and vn , we have, nonetheless,
increased the width of the hysteresis. Parasitic capacitances will have the same effect if we try to make the
hysteresis go faster than its fundamental limits will allow it to go. However, the effect can be even more drastic
if we increase the amount of phase delay even further. This is shown in the third trace in Fig. 10. Note that a
further increase in phase delay has caused the hysteresis to actually become inverted. Also note that the width
of the hysteresis is smaller than its design value. Here the input signal is so much faster than the hysteresis
circuit than the magnitude of the phase delay has changed the sign of the hysteresis element.
Another effect of fast signals is in the speed at which the output voltage can change from a low value to
a high value. This effect is shown in Fig. 12. We may note that as we increase the capacitance co in Fig. 4,
the slope of the output voltages begins to reduce in magnitude, decreasing the slew rate of the output voltage
swing. This effect is caused by additional capacitive loading at the output of the hysteresis. Compare this
with Fig. 10 and note that there the voltage transitions are very steep in comparison. Also note that the two
phenomena have a similar effect on the width of the hysteresis; for both, an increase in capacitance increases
the hysteresis width.
Example: A Relaxation Oscillator. As an example of hysteresis design, consider the relaxation os-
cillator in Fig. 11 (see Relaxation Oscillator). This oscillator works by charging and discharging the capacitor
C through R3 at the limit voltages at the output of opamp 1. Recognize that opamp 1 and resistors R1 and
 HYSTERESIS IN CIRCUITS 11

Fig. 11. A hysteresis-based relaxation oscillator. The first opamp is in the positive feedback configuration, and the second
opamp is a voltage buffer. Oscillations are caused by the charging and discharging of the capacitor.

Fig. 12. A large capacitance on the output of the hysteresis may cause it to slew. Large load capacitances will make the
width of the hysteresis increase.

R2 constitute a hysteresis element, that opamp 2 is in the voltage follower configuration, and that R3 and C
constitute an RC time constant.

BIBLIOGRAPHY

1. M. A. Plonus Applied Electromagnetics, New York: McGraw-Hill, 1978.

2. J. E. Varrientos E. Sanchez-Sinencio A 4-D chaotic oscillator based on a differential hysteresis comparator, IEEE Trans.
Circuits Syst. I, Fundam. Theory Appl., 45: 3–10, 1998.
12 HYSTERESIS IN CIRCUITS

3. T. Saito S. Nakagawa Chaos from a hysteresis and switched circuit, Phil. Trans. R. Soc. Lond. A, 352: 47–57, 1995.
4. A. Gelb W. E. Vander Velde Multiple-Input Describing Functions and Nonlinear System Design, New York: McGraw-Hill,
1968.
5. A. Visintin Differential Models of Hysteresis, Berlin: Springer-Verlag, 1994.
6. O. E. Rössler The chaotic hierarchy, Z. Naturforsch., 38a: 788–801, 1983.
7. C. W. Wong Y. Q. Ni S. L. Lau Steady-state oscillation of hysteresis differential model, J. Eng. Mech., 120: 2271–2298,
1994.
8. Z. Wang W. Guggenbühl CMOS current Schmitt trigger with fully adjustable hysteresis, Electron. Lett., 25: 397–398,
1989.

JOSEPH E. VARRIENTOS
Dallas Semiconductor Corporation
J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering
Copyright
c 1999 John Wiley & Sons, Inc.

IIR FILTERS
IIR or infinite-length impulse response digital filters have impulse responses of infinite length, which extend
over all time. FIR or finite-length impulse response filters do not. IIR filters are also called recursive filters,
or less frequently, ladder, lattice, wave digital, pole-zero, autoregression moving average (ARMA), and autore-
gression integrated moving average (ARIMA) filters. FIR filters are also called nonrecursive filters, as well as
moving average, delay line and tapped delay line, feedforward, all-zero, and transversal filters (1). From all
these names, we choose to classify digital filters as IIR or FIR.
Terms such as IIR are usually applied to digital filters rather than analog filters. Digital filters operate
in discrete time, and analog filters operate in continuous time (2). Digital filters are usually analyzed using
the z-transform (denoted Z[ ]), whereas analog filters are analyzed using the Laplace transform (denoted L[ ]).
There are very close analogies between the two filter types, and these are often exploited in design.
From a design standpoint, IIR and FIR filters compete with each other. IIR filters have many desirable
properties, which are listed in Table 1. Their design is easy if frequency transformations and other methods are
used. Well-known classical analog filters like Butterworth can be used. Low-order IIR filters can have gains
with sharp cut-off and high selectivity. IIR filters can be implemented using little storage, short delays, and a
small number of arithmetic computations.
IIR have several undesirable properties. They can be unstable. They are stable only if their poles lie inside
the unit circle (assuming causality). They can never have linear phase unlike FIR filters. They are generally
more difficult to design unless frequency transforms are used. Nevertheless, their desirable characteristics
generally far outweigh these undesirable properties, so IIR filters are the most widely used in industry.
IIR filters can be implemented using a variety of techniques. These are summarized in Table 2. The most
popular methods include numerical integration or digital transforms, several invariant time domain response
designs, and matched z-transform design. IIR filters can also be designed using FIR filter design techniques
(1).

Basic Description

A linear digital filter is characterized by its impulse response h(n). The impulse response relates the filter input
x(n) and output y(n) as

when the filter is time-invariant and ∗ represents the convolution operation. Taking the z-transform of both
sides gives

1
2 IIR FILTERS

If the filter is time-varying, then y(n) = h(n,m) ∗ x(m) and Y(z2 ) = H(z1 ,z2 )X(z2 ). In this case, h(n,m) and
H(z1 ,z2 ) are two-dimensional functions. Such digital filters will not be considered, but their analysis and design
is a direct extension of what will be presented here (3). The general time domain form [Eq. (1)] and frequency
domain form [Eq. (2)] of the digital filter are shown in Fig. 1.
IIR filters have transfer functions that can be expressed in the product form

The values of z where H(z) = 0 are called the zeros zk of the filter. The values of z where 1/H(z) = 0 are called
the poles pk of the filter. Any common terms in numerator and denominator are usually canceled out. The IIR
filter gain can also be expressed in the polynomial form
 IIR FILTERS 3

As mentioned before, based on the form of Eqs. (3) and (4), such digital filters are classified in two broad groups
as IIR when the denominator D(z) = 1 and FIR when D(z) = 1.
Rearranging Eq. (4) as Y(z) = H(z)X(z), taking the inverse z-transforms of both sides, and solving for x(n)
gives

This is the time-domain equation used to generate the filter output y(n) from the input x(n). Because feedback
of the output (or so-called recursion) depends upon bk , Eq. (5) makes it clear that the digital filter is recursive
when bk = 0 and nonrecursive when bk = 0. The characteristics of the digital filter are controlled by its gain
H(z) and impulse response h(n).
We first describe some of the overall filter properties based on H(z) and h(n). A digital filter is causal or
nonanticipatory if its impulse response is zero for negative time,
4 IIR FILTERS

Fig. 1. Block diagram of digital filter in (a) time domain form and (b) frequency domain form.

Most real-time filters are designed to be causal. Causality can also be tested using H(z) and the Paley-Wiener
criterion (1). Noncausal filters can often be made causal by delaying its impulse response and truncating its
negative time portion. This changes its gain H(z) very little if only a small portion is truncated.
Another important property is stability. A causal digital filter is stable if its impulse response decays to
zero as time approaches infinity,

Causality is easily tested by inspecting the poles of H(z). A causal digital filter is stable when all the poles
of H(z) lie inside the unit circle of the z-plane and any poles on the unit circle are simple or first-order. Most
digital filters are designed to be both causal and stable (4).
Digital filters are designed using frequency domain and time domain techniques. In the frequency domain
approach, an analog filter transfer function H(s) is directly converted into a digital filter transfer function H(z)
using some form of

g(z) is the desired digital transform. The resulting H(z) generally has frequency-domain and time-domain
responses that differ considerably from the analog filter responses from which they were derived.
A time-domain approach preserves a particular temporal response of the analog filter used to form the
digital filter as

where x(n) and y(n) are the sampled input and output, respectively, of the analog filter. Equivalently, H(z)
is the z-transform of h(n). When the sampling frequency f s = 1/T Hz is sufficiently high compared with the
stopband frequency of the analog filter, the frequency response characteristics are preserved. Otherwise, there
is noticeable aliasing distortion.
We should note a convention that is standard. The samples are taken at time t = nT. The input x(t) is
sampled to produce x(nT). To simplify notation, this is written in shorthand as x(n). This is true for all analog
filter variables when they are converted into digital filter variables.
 IIR FILTERS 5

Frequency-Domain Algorithms

Digital transforms directly convert an analog transfer function H(s) into a digital transfer function H(z) using

g(z) is the desired digital or discrete transform. The resulting H(z) generally has frequency-domain and time-
domain responses that differ considerably from those of the analog filter from which they were derived.
Only s-to-z mappings that map the imaginary axis of the s-plane onto the unit circle of the z-plane preserve
certain frequency-domain characteristics like the passband and stopband magnitude response ripples and
phase variations. Delay and time-domain responses are distorted.
Numerical Integration Transform Design. One especially simple way to obtain digital transforms
is to approximate continuous integrators by discrete integrators (5). Equating the continuous time transfer
function H(s) = 1/s to the discrete time equivalent H(z) = 1/g(z) results in s = g(z), which is the digital transform.
The digital transfer function H dmn (z) of the discrete integrator is chosen to equal

d is the number of zeros at the origin, m is the number of finite zeros including those at the origin, and n is the
number of finite poles in the z − 1 plane. The ak and bk are selected so that H dmn well approximates the transfer
function of an analog integrator H(s) = 1/s when z = e − sT =
∞ k = 0 (sT)k /k!. This method generates an infinite
number of digital transforms (1).
Some of them and others are listed in Table 3. We have selected the backward and forward Euler, bilinear,
modified bilinear, lossless, and optimum transforms. These transforms involve a constant C, which is adjusted
so that the analog frequency ω = 1 rad/s maps into any desired digital filter frequency B rad/s, and normalized
frequency BT radians or 360◦ f /f s degrees. The bilinear transform, denoted as H 011 , is perhaps the most popular
and widely used where

and C = tan(BT/2). This transformation maps the imaginary axis of the s-plane describing the analog filter unto
the unit circle of the z-plane describing the digital filter. Therefore, except for frequency warping, the magnitude
and phase characteristics of the analog filter are preserved exactly. The delay, which is the derivative of the
phase, changes as does the step response. Of the many transforms available, the bilinear transform is the most
widely used because it has the desirable mapping property just mentioned.
An important comment should be made. Causal and stable analog filters are not always mapped into
causal and stable digital filters using these transforms. The backward Euler, bilinear, and optimum transforms
do produce causal and stable filters, but the forward Euler and lossless transforms do not (1). When using
general transforms, the poles of H(z) should always be verified to be inside or on the unit circle (assuming
causality).
Other Filter Types. The transforms of Table 3 are usually used to map analog filter transfer functions
into digital filter transfer functions. If the analog filter is lowpass, these transforms produce a digital highpass
filter. If the analog filter is bandpass, the transforms produce a digital bandpass filter.
6 IIR FILTERS

However, they can also be used to convert analog lowpass filters to the other types directly. If the reciprocals
of s are used in Table 3, digital highpass filters are produced. If the transforms in Table 4 are used, digital
bandpass filters are produced directly. If the reciprocals of s are used in Table 4, then digital bandstop filters
are produced directly. Thus analog lowpass filters can be converted directly into any of these other filter types
by using Tables 3 and 4.
These other filters can be obtained by a simpler and more direct scheme. After a lowpass digital filter H(z)
is obtained, it can be converted into a highpass filter using H(−z) = H(zejπ ). It can be converted to a single-
sideband bandpass filter using H(zej ω0 T). Therefore, by simply rotating the pole-zero pattern of the lowpass
H(z) by θ degrees in the z-plane, other filter types can be obtained. These filters have the same arithmetic shape
but have different geometric shapes, the proper bandwidths, etc. The proper shape is always maintained by
using the transforms in Tables 3 and 4.
IIR FILTERS 7
8 IIR FILTERS

Time-Domain Algorithms

Time-domain algorithms preserve a particular temporal response of the analog filter used to form the digital
filter. Mathematically, the invariant time-domain transform uses

where h(n) is the sampled impulse response of the analog filter. Equivalently, H(z) is the z-transform of h(n)
(6). When the sampling frequency f s = 1/T Hz is sufficiently high compared with the stopband frequency of the
analog filter, the frequency response characteristics are preserved, and there is noticeable aliasing distortion.
Impulse-Invariant Transform Design. The impulse-invariant transform preserves the impulse re-
sponse h(t) of the analog filter (7). Setting the input to be an impulse as x(t) = U 0 (t) in Eq. (13) gives X(z) = 1/T
and

If the analog transfer function H(s) is band-limited to |ω| < ωs /2, then the digital filter has exactly the same
magnitude, phase, and delay responses of the analog filter for |ω| < ωs /2. Otherwise, the frequency responses
are not identical because aliasing occurs. Nevertheless, the impulse responses are identical at the sample
times.
Suppose that H(s) is causal. Its transfer function can be expanded as a partial fraction as

assuming N > M. The impulse response of the analog filter equals

Taking the z-transform of h(t) and multiplying by T gives the impulse-invariant digital filter gain as

Modified Impulse-Invariant Transform Design. An interesting alternative the impulse-invariant

transform is the modified impulse-invariant transform (8). For an analog transfer function H(s) = N(s)/D(s),
its poles were preserved but its zeros were not in Eq. (17). However, the zeros can also be preserved using the
 IIR FILTERS 9

following method. Express two new transfer functions as

which are all-pole low-pass filters. Their impulse-invariant response versions equal

Forming the ratio of these two transfer functions produces the modified impulse-invariant transform as

This is the product of the matched-z transform of the next section and a N 2 (z)/N 1 (z) compensator.
Because this method relies on closely approximating the frequency responses of both the numerator N(s)
and denominator D(s) of H(z) regardless of their orders, H(z) well approximates H(s) in ac steady state.
Matched-z Transform Design. One of the simplest design methods is the matched-z transform. It
uses the z-transform z = esT to map every analog pole −pk and every analog zero −zk into their equivalent
digital pole zp = e − pkT and zero zz = e − zkT , respectively. Using this approach, Eq. (15) maps as

We see that its transfer function has a related form to Eqs. (17) and (20). The impulse-invariant transform
Eq. (17) has the same denominator but a different numerator. The modified impulse-invariant transform Eq.
(20) has the same denominator and numerator but is multiplied by a compensator. The matched-z transform
does not preserve frequency-domain characteristics such as magnitude ripple and delay, nor does it preserve
time-domain responses. Its major advantage is ease of application.
Complementary Design. On a related topic, a complementary digital filter H c (z) can be obtained from
a digital filter H(z) using

The impulse responses of these two filters add to a step function U − 1 (n) so the responses are said to be
complementary. Therefore, these two filters maintain their time domain impulse response characteristics such
as delay and rise (fall) times, overshoot (undershoot), etc. If one filter is low-pass, its complementary filter
is high-pass. If one filter is bandpass, its complementary filter is bandstop. This is an especially convenient
approach because it generates an additional filter with little additional computational cost (1).
10 IIR FILTERS

Fig. 2. Magnitude gain response specification of (a) digital filters and (b) analog filters.

Filter Orders

Digital filters generally have frequency-domain specifications like that drawn in Fig. 2 where
f p = maximum passband frequency (Hz) for M p (dB) maximum ripple
f r = minimum stopband frequency (Hz) for M r (dB) minimum rejection
f s = sampling frequency (Hz) = 1/T seconds
These are usually converted to the normalized frequency form as where
ωp T = 360◦ f p /f s = maximum passband frequency in degrees
ωr T = 360◦ f r /f s = minimum stopband frequency in degrees
d = ωr T/ωp T = stopband/passband frequency ratio.
From such (M p ,M r ,r ) frequency specifications, the digital filter order n is determined from nomographs
using the following procedure. This can be easily done for classical analog filter transfer functions (like Butter-
worth and Chebyshev) combined with the digital transforms (like bilinear) discussed earlier (9).
Frequency Warping. Consider the bilinear transform of Table 3 and its associated frequency relation

where z = jω and s = jv (after some manipulation). The analog filter frequencies v = (0,1,∞) map into the digital
filter frequencies ωT = (0,BT,π). Therefore the bilinear transform compresses the high-frequency response of
the analog filter into frequencies approaching π radians in the digital filter. Thus the digital filter order will be
less than the analog filter order, or at most equal, using this transform.
Other transforms have other constants. For example, the Euler transforms have vT = sin(ωT) or ωT =
sin − 1 (vT). These transforms expand rather than compress the higher-frequency filter response. The digital
filter orders will be no less, and often greater, than the analog filter orders using the Euler transforms.
As the sampling frequency f s approaches infinity or the sampling interval T approaches zero, all properly
formulated discrete transforms produce digital filters whose transfer functions approach that of the analog
filter from which they were all derived. For example, the bilinear transform in Eq. (23) has frequencies that
 IIR FILTERS 11

are related as

so that ωT ∼= vT at low frequencies. Therefore, the low-frequency responses of all the digital filters and the
analog filter must be identical. However, as T increases from zero, this is no longer true, and the frequencies
begin to warp or diverge. In addition, for most transforms the locus of z no longer remains on the unit circle
as s moves up the imaginary axis. The frequency responses cannot remain similar, and considerable distortion
begins to appear. This does not occur with the bilinear transform whose locus remains on the unit circle.
To make this important point, we refer to Table 5. The various transforms are listed with their frequency
mappings for small ωT. Across the top of the table are listed percentage errors in the ωT/vT ratios ranging from
1 to 20%. Also listed are the digital frequencies ωT required for the error to be below this limit. For the bilinear
transform, normalized frequencies less than 43◦ will be warped less than 5%. For the Euler transforms, this
normalized frequency is reduced to 32◦ .
Analog Filter Nomographs. Analog filter nomographs are well-known and readily available (9).They
can be used directly to determine digital filter orders easily. The digital filter frequencies must be converted into
their equivalent or warped analog filter frequencies. The necessary frequency ratios listed in Table 6 must be
computed. These ratios are then entered onto the nomograph as shown in Fig. 3. The digital filter frequencies
d are converted into their corresponding analog filter frequencies a . These analog filter frequencies are then
transferred onto the nomograph as usual, and the analog filter order is determined.
Digital Filter Design Procedure. The design procedure for digital filters using discrete transform is
straightforward. It consists of the following steps (1):

• 1a.Select a suitable analog filter type (e.g., Butterworth, Chebyshev, elliptic).

• 1b.Choose a particular sn -to-z transform from Tables 3 and 4.
• 2.Determine the required analog filter order from the nomograph. Use Table 6.
• 3.Write the analog transfer function H(s) having unit bandwidth and the desired magnitude.
• 4.Compute the normalization constant and the discrete transform from Tables 3 and 4.
• 5.Compute the digital transfer function H(z) by substituting the sn -to-z transform of step 4 into the analog
transfer function H(s) of step 3.
• 6.Implement the transfer function using one of the realization techniques discussed later.
12 IIR FILTERS

Fig. 3. Use of analog filter nomograph for computing digital filter order.

Design Examples

Now that we have introduced and described IIR filters, presented their frequency- and time-domain algorithms,
and described their design procedure, we now will unify this using design examples. We will design a fourth-
order elliptic lowpass filter with 0.28 dB in-band ripple, a minimum of 40 dB stopband rejection, and a 1 kHz
 IIR FILTERS 13

bandwidth using a 10 kHz sampling frequency. Using tables, the analog transfer function equals

The scaling constant 0.1363 is selected so that the dc gain H(0) is −0.28 dB. The maximum in-band gain is
then 0 dB. Most digital filters are designed following the procedure [or some modified version (10)] described in
the previous section. We have chosen both the analog filter type (i.e., elliptic) and order (i.e., 4). Now we choose
the design method and will now demonstrate each of them as discussed previously (1).
Bilinear Transfer Design Example. We choose the bilinear transform of Table 3. Because the desired
0.28 dB bandwidth is 1 kHz and the sampling frequency is 10 kHz, the normalized digital filter bandwidth is
360◦ (1 kHz/10 kHz) = 36◦ . The necessary constant then equals C = tan(36◦ /2) = 0.3249 = 1/3.078. The bilinear
transform then equals
14 IIR FILTERS

Fig. 4. Multiple feedback (1F) realization of fourth-order elliptic digital filter.

Substituting this into the analog transfer function Eq. (25) produces the digital transfer function

The bilinear transform preserves the magnitude and phase response behavior of H(s) but with frequency
warping.
Impulse-Invariant Transform Design. The impulse-invariant transform preserves the impulse re-
sponse h(t) of the analog filter. Expressing the gain Eq. (25) as a partial fraction expansion gives

where sn = s/2π(1 kHz). Taking the inverse Laplace transform, sampling the resulting impulse response h(t)
at T = 1 ms, and z-transforming the result gives

This transform tends to maintain the frequency domain shaping of H(s) but with some aliasing.
 IIR FILTERS 15

Fig. 5. Cascade (1F) realization of fourth-order elliptic digital filter.

Modified Impulse-Invariant Transform Design. We express the numerator and denominator of the
analog filter Eq. (25) as separate transfer functions where

We convert these using the impulse-invariant transform to

Forming the ratio H 02 /H 01 gives the digital filter as

16 IIR FILTERS

Fig. 6. Parallel (1F) realization of fourth-order elliptic digital filter.

The modified impulse-invariant transform produces a digital filter that more closely approximates the magni-
tude response of the analog filter.
Matched-z Transform Design. The analog filter poles and zeros of Eq. (25) are converted to digital
filter poles and zeros using the z-transform z = esT . Converting the poles and zeros gives
 IIR FILTERS 17

Grouping these terms together, the digital filter transfer function equals

This method is simple and gives fairly good responses.

IIR Filter Realizations

To implement an IIR digital filter H(z) in either hardware or software, usually one of the structures listed
in Table 7 must be chosen. These structures are multiple feedback, cascade, parallel, lattice, ladder, analog
simulation, and wave. Because each form has many variations, a wide variety of implementations exist. To
conserve space, some of these implementation forms are now shown by examples but with no discussion. These
filter structures implement the fourth-order 0.28 dB elliptic digital filter whose H(z) is given by Eq. (25) as

The different realizations or structures result by expressing H(z) in different forms as will now be shown (1).
Multiple Feedback Structure. The multiple feedback structure uses H(z) in the summation form Eq.
(4) as

The constant 0.01201 can be included in the numerator as was done here or treated as an external multiplier.
(See Fig. 4.)
Cascade Structure. The cascade structure uses H(z) in the product form of Eq. (3) with biquads as

The poles and zeros are paired. Better performance is usually obtained by selecting pole-zero pairs separated
by a relatively constant distance. (See Fig. 5.)
18 IIR FILTERS

Fig. 7. Lattice realization of fourth-order elliptic digital filter.

Parallel Structure. The parallel structure uses H(z) in the partial fraction expanson form of Eq. (17)
with biquads as

Notice here the biquad does not use a z − 2 term but instead a 0.02864 constant. This reduces complexity. (See
Fig. 6.)
Lattice Structure. The lattice structure uses H(z) in a chain matrix product form. The process is
standard but lengthy and involves the simultaneous solution of equations. (See Fig. 7.)
Ladder Structure. The ladder structure uses H(z) in the continued fraction expansion or repeated long
division form as
 IIR FILTERS 19

Fig. 8. (a) Cauer 1 and (b) Cauer 2 ladder realizations of fourth-order elliptic digital filter.

for Cauer 1 (see Fig. 8a) and

for Cauer 2 (see Fig. 8b). The // denotes the repeated long division operation.
Analog Simulation Structure. The analog simulation structure uses tabulated RLC analog filters
which implement standard H(s). This ladder is put into flow graph form in which the L and C terms involve
1/s. These analog integrator terms are replaced by digital transforms as found in Table 3. This produces H(z)
structures. (See Fig. 9.)
Wave Structure. The wave structure of H(z) is a more complicated form of tabulated H(s) RLC ladders
(1).

IIR Filter Properties

Some of the most important digital filter properties are (1):

(1) Complexity Related to the total number of delays, multipliers, and summers.
(2) Cost Proportional to complexity.
(3) Speed/sampling rate Related to complexity.
(4) Memory Determined by the total number of delay elements and filter coefficients.
20 IIR FILTERS

Fig. 9. Analog filter simulation realization of fourth-order elliptic filter showing (a) RLC analog filter, (b) block diagram
equivalent, and (c) digital filter.

(5) Sensitivity of pole/zero locations Controlled by word length and arithmetic used in computations (fixed- or
floating-point).
(6) Data quantization, coefficient truncation, and product roundoff noise Determined by word length.
(7) Limit cycles Low-level oscillation that continues indefinitely as a result of quantization effects.
(8) Dynamic range Determined by word length, arithmetic used, and filter structure.

A digital filter requires addition, multiplication, and delay z − 1 elements. The complexity depends directly
upon the number of elements required. They are listed in Table 7. Complexity depends indirectly upon filter
type (low-pass, high-pass, etc.), the filter gain characteristic (Butterworth, etc.), and the arithmetic used for
computations. Table 7 shows that multiple feedback structures are the simplest and wave structures are the
most complex. Cost in the general sense is proportional to complexity.
Speed is determined by the speed of the adders, multipliers, and delay (write/read) operations. If these
three digital filter elements have about the same speed, then speed is proportional to total complexity. Parallel
processing techniques can be used to increase speed.
The memory requirements are dictated by the number of delay elements required (data storage) and the
number of filter coefficients used (the ak and bk ). Memory is minimized by using canonical forms having the
minimum number of z − 1 terms. Almost all the filter forms are canonical. The 3F and 4F multiple feedback
forms should be avoided because they require twice the number of delay elements.
The sensitivity of the pole–zero locations of the filter and its response depends upon the word length (i.e.,
finite word size and coefficient truncation) and the type of arithmetic used in the computations. Generally
floating-point arithmetic and long coefficient lengths produce the lowest sensitivity.
 IIR FILTERS 21

BIBLIOGRAPHY

1. C. S. Lindquist Adaptive & Digital Signal Processing with Digital Filtering Applications. Miami, FL: Steward & Sons,
1989.
2. A. V. Oppenheim A. S. Willsky Signals & Systems, 2nd ed., Chaps. 9–10. Englewood Cliffs, NJ: Prentice-Hall, 1997.
3. R. C. Gonzalez P. Wintz Digital Image Processing, 2nd ed. Reading, MA: Addison-Wesley, 1987.
4. S. J. Orfanides Introduction to Signal Processing, Chap. 3.5. Englewood Cliffs, NJ: Prentice-Hall, 1996.
5. J. G. Proakis D. M. Manolakis Digital Signal Processing, 3rd ed., Chap. 8.3. Englewood Cliffs, NJ: Prentice-Hall, 1996.
6. S. D. Stearns D. R. Rush Digital Signal Analysis, Chap. 11. Englewood Cliffs, NJ: Prentice-Hall, 1990.
7. A. V. Oppenheim R. W. Schafer Discrete-Time Signal Processing, Chap. 7.1. Englewood Cliffs, NJ: Prentice-Hall, 1989.
8. A. Antoniou Digital Filters: Analysis and Design, Chap. 7.4. New York: McGraw-Hill, 1979.
9. C. S. Lindquist Active Network Design with Active Filtering Applications. Miami, FL: Steward & Sons, 1977.
10. S. D. Stearns R. A. David Signal Processing Algorithms, Chap. 7. Englewood Cliffs, NJ: Prentice-Hall, 1988.

CLAUDE S. LINDQUIST
University of Miami

INTEGRATED CIRCUITS
The invention of the transistor in 1947 by William Shockley
and his colleagues John Bardeen and Walter Brattain at Bell
Laboratories, Murray Hill, NJ, launched a new era of inte-
grated circuits (IC). The transistor concept was based on the
discovery that the flow of electric current through a solid
semiconductor material like silicon can be controlled by add-
ing impurities appropriately through the implantation pro-
cesses. The transistor replaced the vacuum tube due to its
better reliability, lesser power requirements, and, above all,
its much smaller size. In the late 1950s, Jack Kilby of Texas
Instruments developed the first integrated circuit. The ability
to develop flat or planar ICs, which allowed the interconnec-
tion of circuits on a single substrate (due to Robert Noyce and
Gordon Moore), began the microelectronics revolution. The
substrate is the supporting semiconductor material on which
the various devices that form the integrated circuit are
attached. Researchers developed sophisticated photolithogra-
phy techniques that helped in the reduction of the minimum
feature size, leading to larger circuits being implemented on
a chip. The miniaturization of the transistor led to the devel-
opment of integrated circuit technology in which several hun-
dreds and thousands of transistors could be integrated on a
single silicon die. IC technology led to further developments,
such as microprocessors, mainframe computers, and super-
computers.
Since the first integrated circuit was designed following
the invention of the transistor, several generations of inte-
grated circuits have come into existence: SSI (small-scale in-
tegration) in the early 1960s, MSI (medium-scale integration)
in the latter half of the 1960s, and LSI (large-scale integra-
tion) in the 1970s. The VLSI (very large scale integration) era
began in the 1980s. While the SSI components consisted on
the order of 10 to 100 transistors or devices per integrated
circuit package, the MSI chips consisted of anywhere from
100 to 1000 devices per chip. The LSI components ranged
from roughly 1000 to 20,000 transistors per chip, while the
VLSI chips contain on the order of up to 3 million devices.
When the chip density increases beyond a few million, the
Japanese refer to the technology as ULSI (ultra large scale
J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.
INTEGRATED CIRCUITS 361
integration), but many in the rest of the world continue to call
it VLSI. The driving factor behind integrated circuit technol-
ogy was the scaling factor, which in turn affected the circuit
density within a single packaged chip. In 1965, Gordon Moore
predicted that the density of components per integrated cir-
cuit would continue to double at regular intervals. Amazingly,
this has proved true, with a fair amount of accuracy (1).
Another important factor used in measuring the advances
in IC technology is the minimum feature size or the minimum
line width within an integrated circuit (measured in microns).
From about 8 애m in the early 1970s, the minimum feature
size has decreased steadily, increasing the chip density or the
number of devices that can be packed within a given die size.
In the early 1990s, the minimum feature size decreased to
about 0.5 애m, and currently 0.3, 0.25, and 0.1 애m technolo-
gies (also called as deep submicron technologies) are becom-
ing increasingly common. IC complexity refers, in general, to
the increase in chip area (die size), the decrease in minimum
feature size, and the increase in chip density. With the in-
crease in IC complexity, the design time and the design auto-
mation complexity increase significantly. The advances in IC
technology are the result of many factors, such as high-resolu-
tion lithography techniques, better processing capabilities, re-
liability and yield characteristics, sophisticated design auto-
mation tools, and accumulated architecture, circuit, and
layout design experience.
BASIC TECHNOLOGIES
The field of integrated circuits is broad. The various basic
technologies commonly known are shown in Fig. 1. The inert
substrate processes, further divided as thin and thick film
processes, yield devices with good resistive and temperature
characteristics. However, they are mostly used in low-volume
circuits and in hybrid ICs. The two most popular active sub-
strate materials are silicon and gallium arsenide (GaAs). The
silicon processes can be separated into two classes: MOS (the
basic device is a metal oxide semiconductor field effect tran-
sistor) and bipolar (the basic device is bipolar junction tran-
sistors). The bipolar process was commonly used in the 1960s
and 1970s and yields high-speed circuits with the overhead of
high-power dissipation and the disadvantage of low density.
The transistor-transistor logic (TTL) family of circuits consti-
tutes the most popular type of bipolar and is still used in
many high-volume applications. The emitter-coupled logic
Basic technologies
Inert substrate Active substrate
Thin film Thick film Silicon Gallium arsenide
MOS Bipolar MESFET Bipolar
NMOS PMOS CMOS BI-CMOS TTL I2 L ECL
Figure 1. Overview of the basic technologies.
362 INTEGRATED CIRCUITS
(ECL) devices are used for high-speed parts that form the
critical path delay of the circuit. The MOS family of processes
consists of PMOS, NMOS, CMOS, and BiCMOS. The term
PMOS refers to a MOS process that uses only p-channel tran-
sistors, and NMOS refers to a MOS process that uses only n-
channel transistors. PMOS is not used much due to its electri-
cal characteristics, which are not as good as the n-channel
field effect transistors (FET), primarily since the mobility of
the n-channel material is almost twice compared to the mobil-
ity of the p-channel material. Also, the NMOS devices are
smaller than the PMOS devices, and thus PMOS do not give
good packing density.
CMOS was introduced in the early 1960s; however, it was
only used in limited applications, such as watches and calcu-
lators. This was primarily due to the fact that CMOS had
slower speed, less packing density, and latchup problems al-
though it had a high noise margin and lower power require-
ments. Thus, NMOS was preferred over CMOS, in general,
until the p-channel devices developed began to have similar
characteristics as the nMOS and both the p-channel and n-
channel transistors started delivering close to equal amounts
of currents with similar transistor sizes. In the 1980s and the
1990s, the need for lower power consumption was the driving
factor, and thus CMOS emerged as the leading IC technology
(2). The BiCMOS technology combines both bipolar and
CMOS devices in a single process. While CMOS is preferred
for logic circuits, BiCMOS is preferred for input/output (I/O)
and driver circuits due to its low input impedance and high
current driving capability.
Since the 1980s, efforts have been directed toward design-
ing digital ICs using GaAs devices. In many high-resolution
radar systems, space systems, high-speed communication cir-
cuits, and microwave circuits, the integrated circuits need to
operate at speeds beyond several gigahertz (GHz). In silicon
technology, it is possible to obtain speeds on the order of up
to 10 GHz using ECL circuits, which is almost pushing the
limits of the silicon technology. In GaAs technology, the basic
device is the metal semiconductor (Schottky gate) field effect
transistor, called the GaAs MESFET. Given similar condi-
Field oxide n+
Field oxide p+
Figure 2. Structure of n- and p-type
MOSFET.
tions, the electrons in n-type GaAs material travel twice
faster than in silicon. Thus, the GaAs circuits could function
at twice the speed than the silicon ECL circuits for the same
minimum feature size. The GaAs mateial has a larger band-
gap and does not need gate oxide material, as in silicon, which
makes it immune to radiation effects. Also, the GaAs material
has very high resistivity at room temperatures and lower par-
asitic capacitances, yielding high-quality transistor devices.
However, the cost of fabricating large GaAs circuits is signifi-
cantly high due to its low reliability and yield characteristics
(primarily due to the presence of more defects in the material
compared to silicon). The fabrication process is complex, ex-
pensive, and does not aid scaling. Also, the hole mobility is
the same as in silicon, which means GaAs is not preferable
for complementary circuits. Thus, the GaAs technology has
not been as successful as initially promised. Since CMOS has
been the most dominant technology for integrated circuits, we
examine the MOS transistor and its characteristics as a
switch in the next section.
THE MOS SWITCH
The MOSFET is the basic building block of contemporary
CMOS circuits, such as microprocessors and memories. A
MOSFET is an unipolar device; that is, current is transported
by means of only one type of polarity (electrons in an n type
and holes in a p type). In this section, we describe the basic
structure of MOSFETS and their operation and provide ex-
amples of gates built using MOS devices.
Structure
The basic structure of a MOSFET (n and p type) is shown in
Fig. 2. We describe the structure of an n-type MOSFET (3,4).
It consists of four terminals with a p-type substrate into
which two n⫹ regions are implanted. The substrate is a silicon
wafer that provides stability and support. The region between
the two n⫹ regions is covered by an insulator, typically poly-
silicon and a metal contact. This contact forms the gate of the
Gate oxide G
Poly gate
n+ Field oxide
Channel
S D
P-type substrate
NMOS structure NMOS symbol
Gate oxide G
Poly gate
p+ Field oxide
Channel
S D
N-type substrate
PMOS structure PMOS symbol

transistor. The insulating layer is required to prevent the flow
of current between the semiconductor and the gate. The two
n⫹ regions form the source and the drain. Due to the symme-
try of the structure, the source and the drain are equivalent.
The gate input controls the operation of the MOSFET. A bias
voltage on the gate causes the formation of a channel between
the n⫹ regions. This channel causes a connection between the
source and drain and is responsible for the flow of the current.
The MOSFET is surrounded by a thick oxide, called the field
oxide, which isolates it from neighboring devices. Reversal of
n and p types in the discussion will result in a p-type MOS-
FET. Typical circuit symbols for n-type and p-type MOSFETS
are also shown in Fig. 2.
Operation
When no gate bias is applied, the drain and the source behave
as two pn junctions connected in series in the opposite direc-
tion. The only current that flows is the reverse leakage cur-
rent from the source to the drain. When a positive voltage is
applied to the gate, the electrons are attracted and the holes
are repelled. This causes the formation of an inversion layer
or a channel region. The source and the drain are connected
by a conducting n channel through which the current can
flow. This voltage-induced channel is formed only when the
applied voltage is greater than the threshold voltage, Vt. MOS
devices that do not conduct when no gate bias is applied are
called enhancement mode or normally OFF transistors. In
nMOS enhancement mode devices, a gate voltage greater
than Vt should be applied for channel formation. In pMOS
enhancement mode devices, a negative gate voltage whose
magnitude is greater than Vt must be applied. MOS devices
that conduct at zero gate bias are called normally ON or
depletion mode devices. A gate voltage of appropriate polarity
depletes the channel of majority carriers and hence turns it
OFF.
Considering an enhancement mode n-channel transistor,
when the bias voltage is above the predefined threshold volt-
age, the gate acts as a closed switch between the source and
drain, the terminals of which become electrically connected.
When the gate voltage is cut off, the channel becomes absent,
the transistor stops conducting, and the source and the drain
channels get electrically disconnected. Similarly, the p-chan-
nel transistor conducts when the gate voltage is beneath the
threshold voltage and stops conducting when the bias voltage
is increased above the threshold. The behavior of the MOS
transistor as a switch forms the fundamental basis for imple-
menting digital Boolean circuits using MOS devices.
Output Characteristics
We describe the basis output characteristics (5,6) of a MOS
device in this subsection. There are three regions of operation
for a MOS device:
1. Cutoff region
2. Linear region
3. Saturation region
In the cutoff region, no current flows and the device is said to
be off. When a bias, Vgs, is applied to the gate such that Vg ⬎
Vt, the channel is formed. If a small drain voltage, Vds, is ap-
plied, drain current, Ids, flows from source to drain through
INTEGRATED CIRCUITS 363
Vgs1
Linear Saturation
region region
Ids
Vgs2
Vgs3
Vgs4
Vds
Figure 3. Output characteristics of a MOS transistor.
the conducting channel. The channel acts like a resistance,
and the drain current is proportional to the drain voltage.
This is the linear region of operation. As the value of Vds is
increased, the channel charge near the drain decreases. The
channel is pinched off when Vds ⫽ Vgs ⫺ Vt. An increase in
Vds beyond the pinchoff value causes little change in the drain
current. This is the saturation region of operation of the MOS
device. The output characteristics of n- and p-type devices is
shown in Fig. 3. The equations that describe the regions of
operation can be summarized as follows:
0 If Vgs ≤ Vt (cutoff)
Ids = k/2[2(Vgs − Vt )Vds − Vds
2
]
If Vg > Vt , Vds ≤ (Vgs − Vt ) (linear)
k/2(Vgs − Vt )2 If Vg > Vt , Vds > (Vgs − Vt ) (saturation)
where k is the transconductance parameter of the transistor.
A detailed analysis of the structure and operation of MOS
devices is described in Refs. 3, 5, 7, and 8.
CMOS Inverter
The basic structure of an inverter is shown in Fig. 4, and the
process cross section is shown in Fig. 5. The gates of both the
NMOS and the PMOS transistors are connected. The PMOs
transistor is connected to the supply voltage Vdd, and the
NMOS transistor is connected to Gnd. When a logical 0 is ap-
plied at the input Vin, then the PMOS device is on and the
output is pulled to Vdd. Hence the output is a logical 1. On the
other hand, when a logical 1 is applied at the input, then the
NMOS transistor is on and the output is pulled to the ground.
Hence we have a logical 0. The operating regions of the tran-
Vdd
In Out
GND
Figure 4. Circuit schematic of an inverter.
364 INTEGRATED CIRCUITS
;;;;;;;;;;
; ;;;;
VDD
;;; ;;
;;
;;
;
Polysilicon
Figure 5. Process cross section of an n-
well inverter. Metal (A1)
sistor are shown in Fig. 6. In region I, the n device is off and
the p device operates in the linear region. Hence the output
is pulled to Vdd. In region II, the n and p devices operate in
the linear and saturation region depending on the input volt-
age. In region III, the p device is cut off and the n device is
operating in the linear region. The output is pulled to the
ground. In region II, when both the transistors are on simul-
taneously, a short is produced between Vdd and Gnd. This ac-
counts for the short circuit power dissipation in CMOS logic.
Transmission Gate
Consider the device shown in Fig. 7, which represents an
NMOS or a PMOS device. By suitably controlling the gate
bias, the device can be made to turn on or off. It behaves
as an electrical switch that either connects or disconnects
the points s and d. An NMOS device is a good switch when
it passes a logical 0, and a PMOS is a good switch when it
passes a logical 1. In CMOS logic, both the NMOS and PMOS
devices operate together. In general, the NMOS transistor
pulls down the output node to logical 0, and the PMOS device
pulls up a node to logical 1. A transmission gate is obtained
by connecting the two in parallel, as shown in Fig. 8. The
Vdd
I II III
0
Vin
Figure 6. Operating regions of the transistor.
Input
Ground
Output
; ;
;
n well
p substrate
Field oxide p diffusion
Gate oxide n diffusion
control signal (say, g) applied to the n-type device is comple-
mented and applied to the p-type device. When g is high, both
the transistors are on and hence a good 1 or a 0 is passed.
When g is low, both the devices are off. This is also called a
complementary switch, or a C SWITCH (5).
NAND and NOR Gates
CMOS combinational gates are constructed by connecting the
PMOS and NMOS devices in either series or parallel to gener-
ate different logical functions. The structures for a two-input
NAND and NOR gate are shown in Fig. 9.
NAND Gate. The p devices are connected in parallel, and
the n devices are connected in series. When either of the in-
puts A or B is a logical 0, the output is pulled high to Vdd.
When both A and B are high, then the output is pulled to the
ground. Hence this structure implements the operation f ⫽
(A ⭈ B)⬘.
NOR Gate. Similarly, in the NOR gate, the p devices are
connected in series and the n devices are connected in paral-
lel. When either of the inputs A or B is a logical 1, then the
output is pulled to the ground. When both A and B are low,
then the output is pulled to Vdd. Hence this structure imple-
ments the operation f ⫽ (A ⫹ B)⬘. The p structure is the logi-
cal dual of the n structure. An n input NAND and NOR gate
can be constructed in a similar fashion.
Electrical equivalent
s MOS d s d
device
s d
g Appropriate gate bias
Figure 7. A MOS device as a switch.

g System-level specification and requirements
a b
g Verification
Figure 8. Transmission gate.
IC DESIGN METHODOLOGY
To design and realize VLSI circuits, several factors play key
roles. The goal of an IC designer is to design a circuit that
meets the given specifications and requirements while spend-
ing minimum design and development time avoiding design
errors. The designed circuit should function correctly and
meet the performance requirements, such as delay, timing,
power, and size. A robust design methodology has been estab-
lished over the years, and the design of complex integrated
circuits has been made possible essentially due to advances
in VLSI design automation. The various stages in the design
flow are shown in Fig. 10. The design cycle ranges from the
system-level specification and requirements to the end prod-
uct of a fabricated, packaged, and tested integrated circuit.
The basic design methodology is briefly described here, and
the various stages are discussed in detail in the followiing
sections using simple examples.
The first step is to determine the system-level specifica-
tions, such as the overall functionality, size, power, perfor-
mance, cost, application environment, IC fabrication process,
technology, and chip-level and board-level interfaces required.
There are several tradeoffs to be considered. The next step is
Vdd Vdd
B delays are considered and timing diagrams are derived to ver-
A B A converting the logic design modules into a circuit representa-
Out
Out
A
A B
B
Gnd Gnd
Two input NAND gate Two input NOR gate
Figure 9. Two-input NAND and NOR gate.
INTEGRATED CIRCUITS 365
Functional design and description
Architectural design
Logic design
Circuit design
Physical design
Fabrication
Testing
Figure 10. IC design methodology.
the functional design and description, in which the system is
partitioned into functional modules and the functionality of
the different modules and their interfaces to each other are
considered. The issues to be considered are regularity and
modularity of structures, subsystem design, data flow organi-
zation, hierarchical design approach, cell types, geometric
placements, and communication between the different blocks.
Once the functionality of the various modules is deter-
mined, the architectural design of the modules is pursued.
Many design alternatives are considered toward optimization.
This stage also includes the design of any hardware algo-
rithms to be mapped onto architectures. A behavioral-level
description of the architecture is obtained and verified using
extensive simulations, often with an iterative process. This
stage is critical in obtaining an efficient circuit in the end and
for simplifying the steps in some of the following stages. In
the logic design stage, the architectural blocks are converted
into corresponding gate-level logic designs, Boolean minimiza-
tion is performed, and logic simulation is used to verify the
design at this level. In some design flows, the circuit could be
synthesized from the logic level by using gate-level libraries
(this is referred to as logic synthesis). The logic design usually
includes a conventioinal logic design approach and a nontra-
ditional design, such as precharge logic. At this stage, gate
ify the synchronization of the various logic modules. The next
step is the circuit design stage, which essentially involves
tion. At this stage, the essential factors considered are clock-
ing, switching speeds or delays, switching activity and power
requirements, and other electrical characteristics (e.g., resis-
tance, capacitance).
The most complex step in VLSI design automation is the
physical design, which includes floorplanning, partitioning,
placement, routing, layout, and compaction. This process con-
verts the given circuit design or description into a physical
layout that is a geometric representation of the entire circuit.
Each step of the physical design by itself is complex and takes
significant amounts of iterations and time. The various types
of transistors, the interconnecting wires, and contacts be-
tween different wires and transistors are represented as dif-
ferent geometric patterns consisting of many layers placed ac-
366 INTEGRATED CIRCUITS
cording to several design rules that govern a given fabrication
technology and process. The floorplanning step involves
higher-level planning of the various components on the lay-
out. The partitioning step converts the overall circuit into
smaller blocks to help the other steps. It is usually impracti-
cal to synthesize the entire circuit in one step. Thus, logic
partitioning is used to divide the given circuit into a smaler
number of blocks, which can be individually synthesized and
compacted. This step considers the size of the blocks, the
number of blocks, and the interconnections between the
blocks and yields a netlist for each block that can be used in
the further design steps.
During the next step, which is the placement of the blocks
on the chip layout, the various blocks are placed such that
the routing can be completed effectively and the blocks use
minimum overall area, avoiding any white spaces. The place-
ment task is iterative in that an initial placement is obtained
first and evaluated for area minimization and effective rout-
ing possibility, and alternate arrangements are investigated
until a good placement is obtained. The routing task com-
pletes the routing of the various interconnections, as specified
by the netlists of the different blocks. The goal is to minimize
the routing wire lengths and minimize the overall area
needed for routing. The routing areas between the various
blocks are referred to as channels or switchboxes. Initially, a
global routing is performed in which a channel assignment is
determined based on the routing requirements, and then a
detailed routing step completes the actual point-to-point
routing.
The last step in the physical design is the compaction step,
which tries to compact the layout in all directions to minimize
the layout area. A compact layout leads to less wire lengths,
lower capacitances, and more chip density since the chip area
is used effectively. The compaction step is usually an inter-
active and iterative process in which the user can specify cer-
tain parameters and check if the compaction can be achieved.
The goal of compaction, in general, is to achieve minimum
layout area. The entire physical design process is iterative
and is performed several times until an efficient layout for
the given circuit is obtained.
Once the layout is obtained, design verification needs to be
done to ensure that the layout produced functions correctly
and meets the specifications and requirements. In this stage,
design rule checking is performed on the layout to make sure
that the geometric placement and routing rules and the rules
regarding the separation of the various layers, the dimensions
of the transistors, and the width of the wires are followed
correctly. Any design rule violations that occurred during the
physical design steps are detected and removed. Then circuit
extraction is performed to complete the functional verification
of the layout. This step verifies the correctness of the layout
produced by the physical design process. After layout verifi-
cation, the circuit layout is ready to be submitted for fabrica-
tion, packaging, and testing. Usually, several dies are pro-
duced on a single wafer and the wafer is tested for faulty dies.
The correct ones are diced out and packaged in the form of a
pin grid array (PGA), dual in-line package (DIP), or any other
packaging technology. The packaged chip is tested extensively
for functionality, electrical and thermal characteristics, and
performance. The process of designing and building an inte-
grated circuit (9) that meets the performance requirements
and functions perfectly depends on the efficiency of the design
automation tools.
CIRCUIT DESIGN
To create performance optimized designs, two areas have to
be addressed to achieve a prescribed behavior: (1) circuit or
structural design, and (2) layout or physical design. While the
layout design is discussed in a later section, this section fo-
cuses on the former.
A logic circuit must function correctly and meet the timing
requirements. There are several factors that can result in the
incorrect functioning of a CMOS logic gate: (1) incorrect or
insufficient power supplies, (2) noise on gate inputs, (3) faulty
transistors, (4) faulty connections to transistors, (5) incorrect
ratios in ratioed logic, and (6) charge sharing or incorrect
clocking in dynamic gates. In any design, there are a certain
paths, called critical paths, that require attention to timing
details since they determine the overall functional frequency.
The critical paths are recognized and analyzed using timing
analyzer tools and can be dealt with at four levels:
1. Architecture
2. RTL/logic level
3. Circuit level
4. Layout level
Designing an efficient overall functional architecture helps
to achieve good performance. To design an efficient architec-
ture, it is important to understand the characteristics of the
algorithm being implemented as the architecture. At the reg-
ister transfer logic (RTL)/logic level, pipelining, the type of
gates, and the fan-in and the fan-out of the gates are to be
considered. Fan-in is the number of inputs to a logic gate, and
fan-out is the number of gate inputs that the output of a logic
gate drives. Logic synthesis tools can be used to achieve the
transformation of the RTL level. From the logic level, the cir-
cuit level can be designed to optimize a critical speed path.
This is achieved by using different styles of CMOS logic, as
explained later in this section. Finally, the speed of a set of
logic can be affected by rearranging the physical layout. The
following techniques can be used for specific design con-
straints.
The various CMOS logic structures that can be used to im-
plement circuit designs are as follows:
1. CMOS Complementary Logic. The CMOS complemen-
tary logic gates are designed as ratioless circuits. In
these circuits, the output voltage is not a fraction of the
Vdd (supply) and the gates are sized to meet the required
electrical characteristics of the circuits. The gate con-
sists of two blocks, and n block and a p block, that deter-
mine the function of the gate. The p block is a dual of
the n block. Thus, an n-input gate will consist of 2n
transistors.
2. Pseudo-NMOS Logic. In this logic, the load device is a
single p transistor with the gate connected to Vdd (5,10).
This is equivalent to replacing the depletion NMOS load
in a conventional NMOS gate by a p device. The design
of this style of gate (11,12) involves ratioed transistor
sizes to ensure proper operation and is shown in Fig.

z
a Outputs
c
b Inputs
d
z = a⋅b + c⋅d
Figure 11. Pseudo-NMOS logic.
11. The static power dissipation that occurs whenever
the pull-down chain is turned on is a major drawback
of this logic style.
3. Dynamic CMOS Logic. In the dynamic CMOS logic
style, an n-transistor logic structure’s output node is
precharged to Vdd by a p transistor and conditionally
discharged by an n transistor connected to Vss (5). The
input capacitance of the gate is the same as the pseudo-
NMOS gate. Here, the pull-up time is improved by vir-
tue of the active switch, but the pull-down time is in-
creased due to the ground. The disadvantage of this
logic structure is that the inputs can only change during
the precharge phase and must be stable during the
evaluate portion of the cycle Figure 12 depicts this logic
style.
4. Clocked CMOS Logic. To build CMOS logic gates with
low power dissipation (13), this logic structure was pro-
posed. The reduced dynamic power dissipation is real-
ized due to the metal gate CMOS layout considerations.
The gates have larger rise and fall times because of the
series clocking transistors, but the capacitance is simi-
lar to the CMOS complementary gates. This is a recom-
mended strategy for ‘‘hot electron’’ effects, because it
places an additional n transistor in series with the logic
transistors (14).
z to p
n-logic
Inputs block
Clock
Figure 12. Dynamic CMOS logic.
INTEGRATED CIRCUITS 367
Weak p device
n-logic
block
Clock
Figure 13. CMOS-domino logic.
5. CMOS Domino Logic. This is a modification of the
clocked CMOS logic, in which a single clock is used to
precharge and evaluate a cascaded set of dynamic logic
blocks. This involves incorporating a static CMOS in-
verter into each logic gate (15), as shown in Fig. 13.
During precharge, the output node is charged high and
hence the output of the buffer is low. The transistors in
the subsequent logic blocks will be turned off since they
are fed by the buffer. When the gate is evaluated, the
output will conditionally go low (1–0), causing the
buffer to conditionally go high (0–1). Hence, in a cas-
caded set of logic blocks, each state evaluates and
causes the next stage to evaluate, provided the entire
sequence can be evaluated in one clock cycle. Therefore,
a single clock is used to precharge and evaluate all logic
gates in a block. The disadvantages of this logic are that
(1) every gate needs to be buffered, and (2) only nonin-
verting structures can be used.
6. NP Domino Logic (Zipper CMOS). This is a further re-
finement of the domino CMOS (16–18). Here, the dom-
ino buffer is removed, and the cascading of logic blocks
is achieved by alternately composed p and n blocks, as
is shown in Fig. 14. When the clock is low, all the n-
block stages are precharged high while all the p-block
stages are precharged low. Some of the advantages of
Clk –Clk Clk
blocks
n-logic p-logic n-logic
Inputs
block block block
Other p Other n
blocks blocks
Figure 14. NP-domino logic.
368 INTEGRATED CIRCUITS
Output Output
Clock
nMOS
Differential combinational
inputs network
Clock
Figure 15. Cascade voltage switch logic.
the dynamic logic styles include (1) smaller area than
fully static gates, (2) smaller parasitic capacitances, and
(3) glitch-free operation if designed carefully.
7. Cascade Voltage Switch Logic (CVSL). The CVSL is a
differential style of logic requiring both true and com-
plement signals to be routed to gates (19). Two comple-
mentary NMOS structures are constructed and then
connected to a pair of cross-coupled p pull-up transis-
tors. The gates here function similarly to the domino
logic, but the advantage of this style is the ability to
generate any logic expression involving both inverting
and noninverting structures. Figure 15 gives a sketch
of the CVSL logic style.
8. Pass Transistor Logic. Pass transistor logic is popular
in NMOS-rich circuits. Formal methods for deriving
pass transistor logic for NMOS are presented in Ref. 20.
Here, a set of control signals and a set of pass signals
are applied to the gates and sources of the n transistor,
correspondingly. From these signals, the truth table for
any logic equation can be realized.
9. Source follower pull-up logic (SFPL): This is similar to
the pseudo-NMOS gate except that the pull-up is con-
trolled by the inputs (21). In turn, this leads to the use
of smaller pull-down circuits. The SFPL gate style re-
duces the self-loading of the output and improves the
speed of the gate. Therefore, it shows a marked advan-
tage in high fan-in gates.
Using the various design styles, any circuit design can be
built in a hierarchical fashion. The basic gates are first built,
from which functional blocks like a multiplexer or an adder
circuit can be realized. From these basic blocks, more complex
circuits can be constructed. Once a design for a specific appli-
cation has been designed, the functionality of the circuit
needs to be verified. Also, other constraints, like the timing
and electrical characteristics, have to be studied before the
design can be manufactured. The techniques and tools to
achieve this are the subject of the next section.
SIMULATION
Simulation is required to verify if a design works the way
it should. Simulation can be performed at various levels of
abstraction. A circuit can be simulated at the logic level, the
switch level, or with reference to the timing. Simulation is a
critical procedure before committing the design to silicon. The
simulators themselves are available in a wide variety of
types (22).
Logic-Level Simulation
Logic-level simulation occurs at the highest level of abstrac-
tion. It uses primitive models of NOT, OR, AND, NOR, and
NAMD gates. Virtually all digital logic simulators are event
driven (i.e., a component is evaluated based on when an event
occurs on its inputs). Logic simulators are categorized ac-
cording to the way the delays are modeled in the circuit: (1)
unit delay simulators, in which each component is assumed
to have a delay of one time unit, and (2) variable-delay simu-
lators, which allow components to have arbitrary delays.
While the former helps in simulating the functionality of the
circuit the latter allows for more accurate modeling of the
fast-changing nodes.
The timing is normally specified in terms of an inertial de-
lay and a load-dependent delay, as follows:
Tgate = Tintrinsic + Cload × Tload
where
Tgate ⫽ delay of the gate
Tintrinsic ⫽ intrinsic gate delay
Cload ⫽ actual load in some units (pF)
Tload ⫽ delay per load in some units (ns/pF)
Earlier, logic simulators used preprogrammed models for the
gates, which forced the user to describe the system in terms
of these models. In modern simulators, programming primi-
tives are provided that allow the user to write models for the
components. The two most popular digital simulation systems
in use today are VHDL and Verilog.
Circuit-Level Simulation
The most detailed and accurate simulation technique is re-
ferred to as circuit analysis. Circuit analysis simulators oper-
ate at the circuit level. Simulation programs typically solve a
complex set of matrix equations that relate the circuit volt-
ages, currents, and resistances. They provide accurate results
but require long simulation times. If N is the number of non-
linear devices in the circuit, then the simulation time is typi-
cally proportional to Nm, where m is between 1 and 2. Simula-
tion programs are useful in verifying small circuits in detail
but are unrealistic for verifying complex VLSI designs. They
are based on transistor models and hence should not be as-
sumed to predict accurately the performance of designs. The
basic sources of error include (1) inaccuracies in the MOS
model parameters, (2) an inappropriate MOS model, and (3)
inaccuracies in parasitic capacitances and resistances. The
circuit analysis programs widely used are the SPICE pro-
gram, developed at the University of California at Berekely
(23), and the ASTAP program from IBM (24). HSPICE (25) is
the commercial variant of these programs. The SPICE pro-
gram provides various levels of modeling. The simple models
are optimized for speed, while the complex ones are used to
get accurate solutions. As the feature size of the processes is
reduced, the models used for the transistors are no longer

valid and hence the simulators cannot predict the perfor-
mance accurately unless new models are used.
Switch-Level Simulation
Switch-level simulation is simulation performed at the lowest
level of abstraction. These simulators model transistors as
switches to merge the logic-level and circuit-level simulation
techniques. Although logic-level simulators also model tran-
sistors as switches, the unidirectional logic gate model cannot
model charge sharing, which is a result of the bidirectionality
of the MOS transistor. Hence, we assume that all wires have
capacitance, since we need to locate charge-sharing bugs.
RSIM (26) is an example of a switch-level simulator with tim-
ing. In RSIM, CMOS gates are modeled as either pull-up or
pull-down structures, for which the program calculates a re-
sistance to power or ground. The output capacitance of the
gate is used with the resistance to predict the rise and the
fall times of a gate.
Timing Simulators
Timing simulators allow simple nonmatrix calculations to be
employed to solve for circuit behavior. This involves making
approximations about the circuit, and hence accuracy is less
than that of simulators like SPICE. The advantage is the exe-
cution time, which is over two orders of magnitude less than
for SPICE. Timing simulator implementations typically use
MOS-model equations or table look-up methods. Examples of
these simulators are in Ref. 27.
Mixed-Mode Simulators
Mixed-mode simulators are available commercially today and
merge the aforementioned different simulation techniques.
Each circuit block can be simulated in the appropriate mode.
The results of the simulation analysis are fed back to the
design stage, where the design is tuned to incorporate the
deviations. Once the circuit is perfected and the simulation
results are satisfactory, the design can be fabricated. To do
this, we need to generate a geometric layout of the transistors
and the electrical connections between them. This has been a
subject of intense research over the last decade and continues
to be so. The following section introduces this problem and
presents some of the well-known techniques for solving it.
LAYOUT
The layout design is considered a prescription for preparing
the photomasks used in the fabrication of ICs (5). There is a
set of rules, called the design rules, used for the layout; these
serve as the link between the circuit and the process engi-
neer. The physical design engineer, in addition to knowledge
of the components and the rules of the layout, needs strate-
gies to fit the layouts together with other circuits and provide
good electrical properties. The main objective is to obtain cir-
cuits with optimum yield in as small an area as possible with-
out sacrificing reliability.
The starting point for the layout is a circuit schematic. Fig-
ure 2 depicts the schematic symbols for an n-type and p-type
transistor. The circuit schematic is treated as a specification
for which we must implement the transistors and connections
between them in the layout. The circuit schematic of an in-
verter is shown in Fig. 4. We need to generate the exact lay-
INTEGRATED CIRCUITS 369
out of the transistors of this schematic, which can then be
used to build the photomask for the fabrication of the in-
verter. Generating a complete layout in terms of rectangles
for a complex system can be overwhelming, although at some
point we need to generate it. Hence designers use an abstrac-
tion between the traditional transistor schematic and the full
layout to help organize the layout for complex systems. This
abstraction is called a stick diagram. Figure 16 shows the
stick diagram for the inverter schematic. As can be seen, the
stick diagram represents the rectangles in the layout as lines,
which represent wires and component symbols. Stick dia-
grams are not exact models of the layouts but let us evaluate
a candidate design with relatively little effort. Area and as-
pect ratio are difficult to estimate from stick diagrams.
Design Rules
Design rules for a layout (28) specify to the designer certain
geometric constraints on the layout artwork so that the pat-
terns on the processed wafer will preserve the topology and
geometry of the designs. These help to prevent separate, iso-
lated features from accidentally short circuiting, or thin fea-
tures from opening, or contacts from slipping outside the area
to be contacted. They represent a tolerance that ensures very
high probability of correct fabrication and subsequent opera-
tion of the IC. The design rules address two issues primarily:
1. The geometrical reproduction of features that can be re-
produced by the mask-making and lithographical pro-
cess
2. The interaction among the different layers
Several approaches can be used to descibe the design rules.
These include the micron rules, stated at some micron resolu-
tion, and the lambda (␭)-based rules. The former are given as
a list of minimum feature sizes and spacings for all masks in
a process, which is the usual style for the industry. Mead-
Conway (29) popularized the ␭-based approach, where ␭ is
process dependent and is defined as the maximum distance
by which a geometrical feature on any one layer can stray
from another feature. The advantage of the ␭-based approach
is that by defining ␭ properly the design itself can be made
independent of both the process and fabrication house, and
the design can be rescaled. The goal is to devise rules that
are simple, constant in time, applicable to many processes,
standardized among many institutions, and have a small
number of exceptions for specific processes. Figure 17 gives
the layout of the inverter, with the design rules specified.
To design and verify layouts, different computer-aided de-
sign (CAD) tools can be used. The most important of these
are the layout editors (30), design rule checkers, and circuit
extractors. The editor is an interactive graphic program that
allows us to create and delete layout elements. Most editors
work on hierarchical layouts, but some editors, like Berekely’s
Vdd
Metal 2
Metal 1
In Out Poly
n diff
pdiff
Vss
Figure 16. Stick diagram of the inverter.
370 INTEGRATED CIRCUITS
Metal 1-pdiff via
;;;;;
;;;
p-type
transistor
Metal 1
Tub tie
VDD
;;;;;;
ntub
Poly
Metal 1
a a′
Metal 1-poly via
;;;
; ;
Metal 1-ndiff via
n-type ptub
transistor
;;;
Metal 1
Vss
Tub tie
Figure 17. Transistor layout of the inverter.
Magic tool (31), work on a symbolic layout. The latter include
somewhat more detail than the stick diagram but are still
more abstract than the pure layout. The design rule checker,
or DRC, programs look for design rule violations in the lay-
outs. Magic has an on-line design rule checking. The circuit
extractor is an extension of the DRC programs. While the
DRC must identify transistors and vias to ensure proper
checks, the circuit extractor performs a complete job of compo-
nent and wire extraction. it produces a netlist, which lists the
transistors in the layouts and the electrical nets that connect
their terminals.
Physical Design
From the circuit design of a certain application and the design
rules of a specific process, the physical design problem is to
generate a geometric layout of the transistors of the circuit
design conforming to the specified design rules. From this lay-
out, photomasks can be generated that will be used in the
fabrication process. To achieve this, the different modules of
the design need to be placed first and then electrical connec-
tions between them realized through the metal layers. For
instance, a two-layer metallization would allow the designer
to lay out metal both vertically and horizontally on the floor-
plan. Whenever the wire changes direction, a via can be used
to connect the two metal layers. Due to the complexity of this
problem, most authors treat module placement and the rout-
ing between modules as two separate problems, although they
are related critically. Also, in former days, when designs were
less complex, design was done by hand. Now we require so-
phisticated tools for this process.
Placement. Placement is the task of placing modules adja-
cent to each other to minimize area or cycle time. The litera-
ture consists of a number of different placement algorithms
that have been proposed (32–35). Most algorithms partition
the problem into smaller parts and then combine them, or
start with a random placement solution and then refine it to
reach the optimal. The modules are usually considered as
rectangular boxes with specified dimensions. The algorithms
then use different approaches to fit these boxes in a minimal
area or to optimize them to certain other constraints. For in-
stance, consider a certain number of modules with specific di-
mensions and a given area in which to fit them. This is simi-
lar to the bin-packing algorithm. After the placement step,
the different modules are placed in an optimal fashion and
the electrical connections between them need to be realized.
Routing. Once the modules have been placed, we need to
create space for the electrical connections between them. To
keep the area of the floorplan minimal, the first consideration
is to determine the shortest path between nodes, although a
cost-based approach may also be used. The cost is defined to
include an estimate of the congestion, number of available
wire tracks in a local area, individual or overall wire length,
and so on. Since the problem is a complex one, the strategy is
to split the problem into global or loose routing and local or
detailed routing. Global routing is a preliminary step, in
which each net is assigned to a particular routing area, and
the goal is to make 100% assignment of nets to routing re-
gions while minimizing the total wire length. Detailed routing
then determines the exact route for each net within the global
route. There are a number of approaches to both of these
problems.
Global Routing. Global routing (36) is performed using a
wire-length criterion, because all timing critical nets must be
routed with minimum wire length. The routing area itself can
be divided into disjoint rectangular areas, which can be classi-
fied by their topology. A two-sided channel is a rectangular
routing area with no obstruction inside and with pins on two
parallel sides. A switch box is a rectangular routing area with
no obstructions and signals entering and leaving through all
four sides (37). The focus in this problem is only to create
space between the modules for all the nets and not to deter-
mine the exact route. The algorithms proceed by routing one
net at a time, choosing the shortest possible path. Since there
is a lot of dependency among the nets, different heuristics are
used to generate the least possible routing space in which to
route the nets. Once space is created for all the nets, the exact
route of each net can be determined.
Detailed Routing. Detailed routing is usually done by either
a maze-search or a line-search algorithm. The maze-running
algorithm (38,39) proposed by Lee-Moore finds the shortest
path between any two points. For this, the layout is divided
into a grid of nodes, in which each node is weighted by its
distance from the source of the wire to be routed. The route
that requires the smallest number of squares is then chosen.
If a solution exists, this algorithm will find it, but an exces-
sive amount of memory is required to achieve this. In the line-
search algorithm, vertical and horizontal lines are drawn
from the source and the target, followed by horizontal or ver-
tical lines that intersect the original lines. This is repeated
until the source and target meet. There are also a number of
other heuristic algorithms that exploit different characteris-
tics of the design to generate optimal routing solutions. Ge-
netic algorithms and simulated annealing approaches to this
problem have gained importance in recent years.
An introduction to the various algorithms that have been
proposed for layouts can be found in Ref. 40. Once the layout

has been determined and the photomasks made, the circuit
can go to the fabrication plant for processing.
FABRICATION
The section describes the approach used in building inte-
grated circuits on monolithic pieces of silicon. The process in-
volves the fabrication of successive layers of insulating, con-
ducting, and semiconducting materials, which have to be
patterned to perform specific functions. The fabrication there-
fore must be executed in a specific sequence, which consti-
tutes an IC process flow. The manufacturing process itself is
a complex interrelationship of chemistry, physics, material
science, thermodynamics, and statistics.
Semiconducting materials, as the name suggests, are nei-
ther good conductors nor good insulators. While there are
many semiconducting elements, silicon is primarily chosen for
manufacturing ICs because it exhibits few useful properties.
Silicon devices can be built with a maximum operating tem-
perature of about 150⬚C due to the smaller leakage currents
as a result of the large bandgap of silicon (1.1 eV). IC planar
processing requires the capability to fabricate a passivation
layer on the semiconductor surface. The oxide of silicon,
SiO2, which could act as such a layer, is easy to form and is
chemically stable. The controlled addition of specific impuri-
ties makes it possible to alter the characteristics of silicon.
For these reasons, silicon is almost exclusively used for fabri-
cating microelectronic components.
Silicon Material Technology
Beach sand is first refined to obtain semiconductor-grade sili-
con. This is then reduced to obtain electronic-grade polysilicon
in the form of long, slender rods. Single-crystal silicon is
grown from this by the Czochralski (CZ) or float-zone (FZ)
methods. In CZ growth, single crystal ingots are pulled from
molten silicon contained in a crucible. For VLSI applications,
CZ silicon is preferred because it can better withstand ther-
mal stresses (41) and offers an internal gettering mechanism
than can remove unwanted impurities from the device struc-
tures on wafer surfaces (42). FZ crystals are grown without
any contact to a container or crucible and hence can attain
higher purity and resistivity than CZ silicon. Most high-volt-
age, high-power devices are fabricated on FZ silicon. The sin-
gle crystal ingot is then subjected to a complex sequence of
shaping and polishing, known as wafering, to produce start-
ing material suitable for fabricating semiconductor devices.
This involves the following steps:
1. The single crystal ingot undergoes routine evaluation of
resistivity, impurity content, crystal perfection size, and
weight.
2. Since ingots are not perfectly round, they are shaped to
the desired form and dimension.
3. The ingots are then sawed to produce silicon slices. The
operation defines the surface orientation, thickness, ta-
per, and bow of the slice.
4. To bring all the slices to within the specified thickness
tolerance, lapping and grinding steps are employed.
INTEGRATED CIRCUITS 371
5. The edges of the slices are then rounded to reduce sub-
stantially the incidence of chipping during normal wa-
fer handling.
6. A chemical-mechanical polishing (43) step is then used
to produce the highly reflective and scratch- and dam-
age-free surface on one side of the wafer.
7. Most VLSI process technologies also require an epitax-
ial layer, which is grown by a chemical vapor deposi-
tion process.
The most obvious trend in silicon material technology is
the increasing size of the silicon wafers. The use of these
larger-diameter wafers presents major challengers to semi-
conductor manufacturers. Several procedures have been in-
vestigated to increase axial impurity uniformity. These in-
clude the use of double crucibles, continuous liquid feed (CLF)
systems (44), magnetic Czochralski growth (MCZ) (44,45),
and controlled evaporation from the melt.
Epitaxial Layer
The epitaxial growth process is a means of depositing a single
crystal film with the same crystal orientation as the underly-
ing substrate. This can be achieved from the vapor phase, liq-
uid phase, or solid phase. Vapor phase epitaxy has the widest
acceptance in silicon processing, since excellent control of the
impurity concentration and crystalline perfection can be
achieved. Epitaxial processes are used for the fabrication of
advanced CMOS VLSI circuits, because epitaxial processes
minimize latch-up effects. Also in the epitaxial layer, doping
concentration can be accurately controlled, and the layer can
be made oxygen and carbon free. Epitaxial deposition is a
chemical vapor deposition process (46). The four major chemi-
cal sources of silicon used commercially for this deposition are
(1) silicon tetrachloride (SiCl4), (2) trichlorosilane (SiHCl3), (3)
dichlorosilane (SiH2Cl2), and (4) silane (SiH4). Depending on
particular deposition conditions and film requirements, one of
these sources can be used.
Doping Silicon
The active circuit elements of the IC are formed within the
silicon substrate. To construct these elements, we need to cre-
ate localized n-type and p-type regions by adding the appro-
priate dopant atoms. The process of introducing controlled
amounts of impurities into the lattice of the monocrystalline
silicon is known as doping. Dopants can be introduced selec-
tively into the silicon using two techniques: diffusion and ion
implantation.
Diffusion. The process by which a species moves as a result
of the presence of a chemical gradient is referred to as diffu-
sion. Diffusion is a time- and temperature-dependent process.
To achieve maximum control, most diffusions are performed
in two steps. The first step is predeposition (47), which takes
place at a furnace temperature and controls the amount of
impurity that is introduced. The second step, the drive-in step
(47), controls the desired depth of diffusion.
Predeposition. In predisposition, the impurity atoms are
made available at the surface of the wafer. The atoms of the
desired element in the form of a solution of controlled viscos-
ity can be spun on the wafer, in the same manner as the pho-
toresist. For these spin-on dopants, the viscosity and the spin
372 INTEGRATED CIRCUITS
rate are used to control the desired dopant film thickness.
The wafer is then subjected to a selected high temperature to
complete the predeposition diffusion. The impurity atoms can
also be made available by employing a low-temperature
chemical vapor deposition process in which the dopant is in-
troduced as a gaseous compound—usually in the presence of
nitrogen as a diluent. The oxygen concentration must be care-
fully controlled in this operation to prevent oxidation of the
silicon surface of the wafer.
Drive-In. After predeposition the dopant wafer is subjected
to an elevated temperature. During this step, the atoms fur-
ther diffuse into the silicon crystal lattice. The rate of diffu-
sion is controlled by the temperature employed. The concen-
tration of the dopant atoms is maximum at the wafer surface
and reduces as the silicon substrate is penetrated further. As
the atoms migrate during the diffusion, this concentration
changes. Hence a specific dopant profile can be achieved by
controlling the diffusion process. The dopant drive-in is usu-
ally performed in an oxidizing temperature to grow a protec-
tive layer of SiO2 over the newly diffused area.
Ion Implantation. Ion implantation is a process in which
energetic, charged atoms or molecules are directly introduced
into the substrate. Ion implantation (48,49) is superior to the
chemical doping methods discussed previously. The most im-
portant advantage of this process is its ability to control more
precisely the number of implanted dopant atoms into sub-
strates. Using this method, the lateral diffusion is reduced
considerably compared to the chemical doping methods. Ion
implantation is a low-temperature process, and the parame-
ters that control the ion implantation are amenable to auto-
matic control. After this process the wafer is subjected to an-
nealing to activate the dopant electrically. There are some
limitations to this process. Since the wafer is bombarded with
dopant atoms, the material structure of the target is dam-
aged. The throughput is typically lower than diffusion doping
process. Additionally, the equipment used causes safety haz-
ards to operating personnel.
Photolithography
Photolithography is the most critical step in the fabrication
sequence. It determines the minimum feature size that can
be realized on silicon and is a photoengraving process that
accurately transfers the circuit patterns to the wafer. Lithog-
raphy (50,51) involves the patterning of metals, dielectrics,
and semiconductors. The photoresist material is first spin
coated on the wafer substrate. It performs two important
functions: (1) precise pattern formation and (2) protection of
the substrate during etch. The most important property of the
photoresist is that its solubility in certain solvents is greatly
affected by exposure to ultraviolet radiation. The resist layer
is then exposed to ultraviolet light. Patterns can be trans-
ferred to the wafer using either positive or negative masking
techniques. The required pattern is formed when the wafer
undergoes the development step. After development, the un-
desired material is removed by wet or dry etching.
Resolution of the lithography process is important to this
process step. It specifies the ability to print minimum size
images consistently under conditions of reasonable manufac-
turing variation. Therefore, lithographic processes with sub-
micron resolution must be available to build devices with sub-
micron features. The resolution is limited by a number of
factors, including (1) hardware, (2) optical properties of the
resist material, and (3) process characteristics (52).
Most IC processes require 5 to 10 patterns. Each one of
them needs to be aligned precisely with those already on the
wafer. Typically, the alignment distance between two pat-
terns is less than 0.2 애m across the entire area of the wafer.
The initial alignment is made with respect to the crystal lat-
tice structure of the wafer, and subsequent patterns are
aligned with the existing ones. Earlier, mask alignment was
done using contact printing (53,54), in which the mask is held
just off the wafer and visually aligned. The mask is then
pressed into contact with the wafer and impinged with ultra-
violet light. There is a variation of this technique called prox-
imity printing, in which the mask is held slightly above the
wafer during exposure. Hard contact printing was preferred
because it reduced the diffraction of light, but it led to a num-
ber of yield and production problems. So the projection align-
ment and exposure system was developed, in which the mask
and wafer never touch and an optical system projects and
aligns the mask onto the wafer. Since there is no damage to
the mask or photoresist, the mask life is virtually unlimited.
VLSI devices use projection alignment as the standard pro-
duction method.
Junction Isolation
When fabricating silicon ICs, it must be possible to isolate the
devices from one another. These devices can then be con-
nected through specific electrical paths to obtain the desired
circuit configuration. From this perspective, the isolation
technology is one of the critical aspects of IC fabrication. For
different IC types, like NMOS, CMOS, and bipolar, a variety
of techniques have been developed for device isolation. The
most important technique developed was termed LOCOS, for
LOCal Oxidation of Silicon. This involves the formation of
semirecessed oxide in the nonactive or field areas of the sub-
strate. With the advent of submicron-size device geometries,
alternative approaches for isolation were needed. Modified
LOCOS processes, trench isolation, and selective epitaxial
isolation were among the newer approaches adopted.
LOCOS. To isolate MOS transistors, it is necessary to pre-
vent the formation of channels in the field regions. This im-
plies that a large value of VT is required in the field region, in
practice about 3 to 4 V above the supply voltage. Two ways to
increase the field voltage are to increase the field oxide thick-
ness and raise the doping beneath the field oxide. Thicker
field oxide regions cause high enough threshold voltages but
unfortunately lead to step coverage problems, and hence thin-
ner field oxide regions are preferred. Therefore, the doping
under the field oxide region is increased to realize higher
threshold voltages. Nevertheless, the field oxide is made 7 to
10 times thicker than the gate oxide. Following this, in the
channel-stop implant step, ion implantation is used to in-
crease the doping under the field oxide. Until about 1970, the
thick field oxide was grown using the grow-oxide-and-etch ap-
proach, in which the oxide is grown over the entire wafer and
then etched over the active regions. Two disadvantages of this
approach prevented it from being used for VLSI applications:
(1) Field-oxide steps have sharp upper corners, which poses a
problem to the subsequent metallization steps; and (2) chan-

nel-stop implant must be performed before the oxide is grown.
In another approach, the oxide is selectively grown over the
desired field regions. This process was introduced by Appels
and Kooi in 1970 (55) and is widely used in the industry. This
process is performed by preventing the oxidation of the active
regions by covering them with a thin layer of silicon nitride.
After etching the silicon nitride layer, the channel-stop dop-
ant can be implanted selectively. The process, has a number
of limitations for submicron devices. The most important of
these is the formation of the ‘‘bird’s beak,’’ which is a lateral
extension of the field oxide into the active areas of the device.
The LOCOS bird’s beak creates other problems as junctions
become shallower in CMOS ICs. The LOCOS process was
therefore modified in several ways to overcome these limita-
tions: (1) etched-back LOCOS, (2) polybuffered LOCOS, and
(3) sealed-interface local oxidation (SILO) (56).
Non-LOCOS Isolation Technologies. There have been non-
LOCOS isolation technologies for VLSI and ultra-large-scale
integration (ULSI) applications. The most prominent of these
is trench isolation technology. Trench technologies are classi-
fied into three categories: (1) shallow trenches (⬍1 애m), (2)
moderate depth trenches (1 to 3 애m), and (3) deep, narrow
trenches (⬎3 애m deep, ⬍2 애m wide). Shallow trenches are
used primarily for isolated devices of the same type and hence
are considered a replacement to LOCOS. The buried oxide
(BOX) (57) isolation technology uses shallow trenches refilled
with a silicon dioxide layer, which is etched back to yield a
planar surface. This technique eliminates the bird’s beak of
LOCOS. The basic BOX technique has certain drawbacks for
which the technique is modified.
Metallization
This subsection describes the contact technology to realize the
connections between devices, and how the different metal lay-
ers are connected to realize the circuit structure.
Contact Technology. Isolated active-device regions in the
single-crystal substrate are connected through high-conduc-
tivity, thin-film structures that are fabricated over the silicon
dioxide that covers the surface. An opening in the SiO2 must
be provided to allows contacts between the conductor film and
the Si substrate. The technology involved in etching these
contacts is referred to as contact technology. These contacts
affect the circuit behavior because of the parasitic resistances
that exist in the path between the metal to Si substrate and
the region where the actual transistor action begins. Conven-
tional contact fabrication involves the fabrication of a contact
to silicon at locations where the silicon dioxide has been
etched to form a window. It involves the following steps:
1. In regions where contacts are to be made, the silicon
substrate is heavily doped.
2. A window or contact hole is etched in the oxide that
passivates the silicon surface.
3. The silicon surface is cleaned to remove the thin native-
oxide layer that is formed rapidly when the surface is
exposed to an oxygen-containing ambient.
4. The metal film is deposited on the wafer and makes con-
tact with silicon wherever contact holes were created.
Aluminum is the most commonly used metal film.
INTEGRATED CIRCUITS 373
5. After depositing the metal, the contact structure is sub-
jected to a thermal cycle known as sintering or anneal-
ing. This helps in bringing the Si and metal into inti-
mate contact.
Al is desired as an interconnect material because its resis-
tivity, 2.7 애⍀-cm, is very low, and it offers excellent compati-
bility with SiO2. Al reacts with SiO2 to form Al2O3, through
which the Al can diffuse to reach the Si, forming an intimate
Al0Si contact. But using pure Al has certain disadvantages.
Since Al is polycrystalline in nature, its grain boundaries of-
fer very fast diffusion paths for the Si at temperatures above
400⬚C. Hence, if a large volume of Al is available, a significant
quantity of the Si can diffuse into Al. As a result, the Al from
the film moves rapidly to fill in the voids created by the mi-
grating Si, which leads to large leakage currents or electri-
cally shorting the circuit. This effect is referred to as junction
spiking (58). To prevent junction spiking, different techniques
are used:
1. Add approximately 1% of Si to Al.
2. Add a diffusion barrier to prevent Si from diffusing into
Al.
3. Decrease sintering temperature, but this increases con-
tact resistance.
4. Add a ‘‘barrier’’ metal to the contact hole (59).
Of these techniques, the most commonly used is the barrier
metal. The idea is to block or hinder Al from intermixing with
Si. There are three main types of contact barrier metallurgies:
(1) sacrificial barrier, (2) passive barrier, and (3) stuffed
barrier.
The use of Al has its own problems, the most important
being its high resistivity and electromigration. There is also
the problem with ‘‘hillock’’ formation. Hillocks are formed due
to the thermal expansion mismatch among Al, SiO2, and Si.
As the wafer is cooled, thermal expansion mismatch forms
stresses (usually compressive), which forms these hillocks.
Therefore, copper metallization has been gaining importance.
Copper is preferred over Al because it has a low resistivity
(1.2 애⍀-cm) and is resistant to electromigration. In fact, cop-
per is added in small quantities to Al to reduce the electromi-
gration problem of Al. However, there are some real problems
with copper that need to be addressed before it can replace Al:
1. Cu is a terrible contaminant in Si. It has a very high
diffusivity in Si and causes junction leakage, which de-
grades the gate oxide integrity (GOI).
2. Cu diffuses and drifts easily through SiO2. Hence, Cu
needs to be encapsulated for use in metallization.
3. Cu oxidizes to CuO easily.
4. The etch chemistry for Cu is highly contaminated, and
the wafers need to be held at higher temperatures.
Typical process steps involved in the fabrication of a 0.8
애m LOCOS n-well inverter are as follows:
1. Wafer: 1 ⫻ 1015 to 1 ⫻ 1016 CZ(p) with 具100典 crystal ori-
entation. Epitaxial layer required because of latch-up.
The thickness is 2 애m to 16 애m with 5 ⫻ 1015.
374 INTEGRATED CIRCUITS
2. Grown screen oxide layer, with the thickness in the
range 400 to 1000.
3. Expose the n-well photo on the wafer.
4. n-well ion implant. Use 1 ⫻ 1013 /cm2 phosphorous. The
voltage used is 60 keV to 2 MeV.
5. n-well drive-in. This step is carried out at 1050 to
1100⬚C for 2 to 6 h. This activates the dopant atoms.
The drive-in depth is around 1 애m to 10 애m.
6. Perform LOCOS process.
6.1. Strip wafer.
6.2. Pad oxide. Thickness is 100 to 400.
6.3. Pad nitride. Thickness is 1000 to 2000. LPCVD
silicon nitride is used.
6.4. Expose the diffusion photo on the wafer.
6.5. Etch the nitride layer.
6.6. Expose the block field (BF) photo. This is the in-
verse of the n-well photo and prevents the for-
mation of the parasitic transistors between adja-
cent transistors.
6.7. Field ion implantation. 1 ⫻ 1013 /cm2 boron at 60
keV.
6.8. Strip the BF and the resist layer.
6.9. Grow the field oxide. The thickness is about
4000 to 6000 of SiO2. The process used is a pyro
process at 900⬚ to 1050⬚C for 3 to 6 h.
6.10. Strip the pad nitride layer by dipping the wafer
in H3PO4.
6.11. Strip the pad oxide layer by dipping the wafer in
50 : 1 HF.
7. Grow a sacrificial oxide layer and strip it. The thick-
ness is about 600 to 1000. The sacrificial oxide layer
eats into the bare silicon, thus exposing fresh silicon
area on which the device can be grown.
8. Grow a sacrificial gate oxide layer. Here the thickness
is about 80 to 130. This layer protects the gate when
the VT implant is done.
9. VT implant. Two masks, one for the n region and one
for the p region, are used. The concentration is 1 ⫻
1011 to 1 ⫻ 1012 /cm2 at 5 to 30 keV.
10. Strip the sacrificial gate oxide layer using a 50 : 1 HF
solution.
11. Grow the gate oxide layer. Typical thickness is 80 to
130. The gate oxide layer is grown at 800 to 900⬚C for
20 min.
12. Polysilicon is deposited all over the wafer. LPCVD si-
lane is used at 620⬚C for a blanket deposition. The typ-
ical thickness is 2500 to 4000.
13. Polysilicon doping is done by ion implantation using
5 ⫻ 1015 phosphorous.
14. The polysilicon etch is a very critical photo/etch pro-
cess.
14.1. Polysilicon photo is exposed on the wafer.
14.2. Reactive ion etch (RIE) is used to etch the polysi-
licon.
14.3. The resist is stripped.
15. Diffusion processing
15.1. Mask the p⫹ regions.
15.2. Perform n⫹ source/drain ion implantation using
5 ⫻ 1015 /cm2 As75 at 40 keV. As is used because
it is slow and does not diffuse deep into the sili-
con substrate.
15.3. Perform n⫹ anneal at 900⬚C for 15 min to acti-
vate the dopant.
15.4. Strip the resist.
15.5. Mask the n⫹ regions.
15.6. Perform p⫹ source/drain ion implantation using
1 ⫻ 1015 /cm2 BF2 /B11 at 5 to 20 keV.
15.7. Source/drain anneal at 900⬚C for 30 min in an
oxidizing atmosphere. This is a rapid thermal
process.
15.8. Strip the resist off.
16. Interlevel dielectric. Boro-phospho silicon glass
(BPSG) is used because it flows well. Typical thickness
is 5000 to 8000. A 900⬚C reflow anneal is also per-
formed.
17. The contact photo is exposed on the wafer. This is criti-
cal to the layout density.
18. The contacts are etched using RIE.
19. After etching, the contact resist is stripped off.
20. Metallization. Ti barrier metallurgy is used. The ac-
tual contact is made with an alloy of Al/Cu/Si with
percentages 98%, 1%, and 1%, respectively. The Al
alloy is sputtered onto the wafer. The typical thickness
is about 1.2 애m.
21. The Metal-1 layer photo is exposed.
22. Metal-1 etch.
23. Strip resist.
24. Foaming gas anneal is performed to improve the mo-
bility of the electrons and relieve stress on the wafer.
The inverter is finally fabricated. Figure 5 describes the pro-
cess cross section of this inverter after the various steps have
been performed.
TESTING
Testing is a critical factor in the design of circuits. The pur-
pose of testing is to verify conformance to the product defini-
tion. To understand the complexity of this problem, consider
a combinational circuit with n inputs. A sequence of 2n inputs
must be applied and observed to test the circuit exhaustively.
Since the number of inputs are high for VLSI circuits, testing
the chip exhaustively is impossible. Hence, this becomes an
area of importance to circuit design. There are three main
areas that need to be addressed to solve this problem:
1. Test generation
2. Test verification
3. Design for testability
Test generation corresponds to the problem of generating a
minimum number of tests to verify the behavior of a circuit.
The problem of test verification, which is commonly gauged by
performing fault simulations, involves evaluating measures of
the effectiveness of a given set of test vectors. Circuits can
also be designed for testability.

Test Generation
Test generation (60) involves the search for a sequence of in-
put vectors that allow faults to be detected at the primary
device outputs. VLSI circuits are typically characterized by
buried flip-flops, asynchronous circuits, indeterminate states,
complex clock conditions, multiple switching of inputs simul-
taneously, and nonfunctional inputs. Due to these factors, an
intimate knowledge of the internal circuit details is essential
to develop efficient test strategies. The goal of a test genera-
tion strategy (61,62) is multifold: (1) chip design verification
in conjunction with the designer, (2) incorporation of the cus-
tomer’s specification and patterns into the manufacturing test
program, and (3) fault detection by fault simulation methods.
Test Verification
Test verification (63) involves calculating measures for how
efficient the test vectors for a given circuit are. This is often
accomplished by using fault models (64). Fault simulation re-
quires a good circuit simulator to be efficient and is hence
closely related to logic simulation and timing analysis. While
the logic simulator verifies the functionality of a design and
ensures that the timing constraints are met, the fault simula-
tor tells the designer if enough analysis has been performed
to justify committing the design to silicon. In fault simulation,
the true value of a circuit and its behavior under possible
faults is simulated. The fault model is a hypothesis based on
an abstract model of the circuit, conformed to some precise
real physical defects. To begin with, the simulator generates
a fault list that identifies all the faults to be modeled. Then a
set of test vectors is simulated against the fault-free and
faulty models. Those faults that cause an erroneous signal at
an output pin are considered as detected faults. Now the fault
coverage of the test vector set can be computed as the number
of faults detected over the total number of faults modeled.
The most widely used fault model is the single stuck-at
fault model. This model assumes that all faults occur due to
the shorting of a signal node with the power rail. A number
of faults can be detected by this model, but a major disadvan-
tage of this model is its assumption that all faults appear as
stuck-at faults. The limitations of this model have led to the
increased use of other models, like the stuck-open (65) and
bridging fault models (66). The former can occur in a CMOS
transistor or at the connection to a transistor. The bridging
faults are short circuits that occur between signal lines. These
represent a frequent source of failure in CMOS ICs. A major-
ity of the random defects are manifested as timing delay
faults in static CMOS ICs. These are faults in which the in-
creased propagation delay causes gates to exceed their rated
specifications. The statically designed circuits have a tran-
sient power supply that peaks when the gates are switching
and then settles to a low current value in the quiescent state.
The quiescent power supply current (67), known as IDDQ, can
be used as an effective test to detect leakage paths due to
defects in the processing. The measured IDDQ of a defect-free
CMOS IC is approximately 20 nA. Most physical defects will
elevate IDDQ by one to five orders of magnitude. Thus the IDDQ
testing approach can be used to detect shorts not detectable
by the single stuck-at fault model.
There are several other ways of applying logic and fault
simulation to testing:
INTEGRATED CIRCUITS 375
1. Toggle Testing. This is the cheapest, simplest, and least
time-consuming method of applying simulation to test-
ing. Toggle testing provides a testability measure by
tracking the activity of circuit nodes. From a set of vec-
tors, the method identifies those parts of the network
that exhibit no activity. Since the test vectors do not
affect these nodes, faults occurring here cannot be de-
tected by the fault simulator.
2. Fault Simulation of Functional Tests. The outputs of
the functional simulator can be used in the design pro-
cess as an effective design analysis tool. The lists of de-
tectable and undetectable faults generated by the simu-
lator can be used to locate problems in the design and
correct them. This results in substantial savings in de-
velopment and manufacturing.
3. Fault Simulation after New Test Vector Generation.
High-quality testing in a reasonable timeframe would
require an efficient test pattern generation system and
a fault simulator. Test vectors are first generated to de-
tect specific faults, and the fault simulator determines
the quality of the vector set. In this scenario, it becomes
important to fault simulate after every new test vector
is generated in order to catch multiple faults. Acceler-
ated fault simulation is faster than test pattern gener-
ation.
Design for Testability
Design for testability commonly refers to those design tech-
niques that produce designs for which tests can be generated
by known methods. The advantage of these techniques are (1)
reduced test generation cost, (2) reduced testing cost, (3) high-
quality product, and (4) effective use of computer-aided design
tools. The key to designing circuits that are testable are two
concepts, controllability and observability. Controllability is
defined as the ability to set and reset every node that is inter-
nal to the circuit. Observability is defined as the ability to
observe either directly or indirectly the state of any node in
the circuit. There are programs like SCOAP (68) that, given
a circuit structure, can calculate the ability to control or ob-
serve internal circuit nodes. The concepts involved in design
for testability can be categorized as follows: (1) ad hoc testing,
(2) scan-based test techniques, and (3) built-in self-test
(BIST).
Ad Hoc Testing. Ad hoc testing comprises techniques that
reduce the combinational explosion of testing. Common tech-
niques partition the circuit structure and add test points. A
long counter is an example of a circuit that can be partitioned
and tested with fewer test vectors. Another technique is the
use of a bus in a bus-oriented system for testing. The common
approaches can be classified as (1) partitioning techniques, (2)
adding test points, (3) using multiplexers, and (4) providing
for easy state reset.
Scan-Based Test Techniques. Scan-based approaches stem
from the basic tenets of controllability and observability. The
most popular approach is the level sensitive scan design, or
LSSD, approach, introduced by IBM (69). This technique is
376 INTEGRATED CIRCUITS
Inputs Outputs
Combinational
logic
Shift register
latches
Clocks Scan out
Figure 18. Level-sensitive scan design.
illustrated in Fig. 18. Circuits designed based on this ap-
proach operate in two modes—namely, normal mode and test
mode. In the normal mode of operation, the shift register
latches act as regular storage latches. In the test mode, these
latches are connected sequentially and data can be shifted in
or out of the circuit. Thus, a known sequence of data (control-
lability) can be input to the circuit and the results can be
shifted out of the circuit using the registers (observability).
The primary disadvantage of this approach is the increased
complexity of the circuit design and the increased external
pin count. The serial scan approach is similar to the LSSD,
but the design of the shift register latch is simplified to obtain
faster circuits. For most circuit designs, only the input and
output register need be made scannable. This technique
makes the designer responsible for deciding which registers
need to be scanned and is called the partial serial scan tech-
nique (70). The parallel scan (71) approach is an extension of
the serial scan in which the registers are arranged in a sort
of a grid, where on a particular column all the registers have
a common read/write signal. The registers that fall on a par-
ticular row have common data lines. Therefore, the output of
a register can be observed by enabling the corresponding col-
umn and providing the appropriate address. Data can also be
written into these registers in a similar fashion.
Built-In Self-Test. Signature analysis (72) or cyclic redun-
dancy checking can be used to incorporate a built-in self-test
module in a circuit. This involves the use of a linear feedback
shift register, as depicted in Fig. 19. The value in the register
will be a function of the value and number of latch inputs and
the counting function of the signature analyzer. The good part
of the circuit will have a particular number or signature in
the register, while the faulty portion will have a different
number. The signature analysis approach can be merged with
the level-sensitive scan design approach to create a structure
called a built-in logic block observation, or BILBO (73). Yet
another approach to built-in test is called a design for autono-
mous test, in which the circuit is partitioned into smaller
structures that are tested exhaustively. The partitioning
method involves the use of multiplexers. The syndrome test-
Q1 Q2 Q3
Clock
Figure 19. Linear feedback shift register.
ing method, in which all possible inputs are applied and the
number of 1’s at the outputs is counted, is also a test method
that requires exhaustive testing. The resultant value is com-
pared to that of a known good machine.
Other Tests
So far we have discussed techniques for testing logic struc-
tures and gates. But we need testing approaches at the chip
level and the system level also. Most approaches for testing
chips rely on the aforementioned techniques. Memories, for
instance, can use the built-in self-test techniques effectively.
Random logic is usually tested by full serial scan or parallel
scan methods. At the system level, traditionally the ‘‘bed-of-
nails’’ testers have been used to probe points of interest. But
with the increasing complexity of designs, system designers
require a standard to test chips at the board level. This stan-
dard is the IEEE 1149 boundary scan (74) architecture. ICs
that are designed based on this standard enable complete
testing of the board. The following types of tests can be per-
formed in a unified framework: (1) connectivity test between
components, (2) sampling and setting chip I/Os, and (3) distri-
bution and collection of built-in self-test results.
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Reading List
A. Mukherjee, Introduction to nMOS and CMOS VLSI Systems Design,
Englewood Cliffs, NJ: Prentice-Hall, 1986.
L. A. Glasser and D. W. Dobberpuhl, The Design and Analysis of VLSI
Circuits, Reading, MA: Addison-Wesley, 1985.
M. Annaratone, Digital CMOS Circuit Design, Norwell, MA:
Kluwer, 1986.
M. Shoji, CMOS Digital Circuit Technology, Englewood Cliffs, NJ:
Prentice-Hall, 1988.
D. A. Pucknell and K. Eshraghian, Basic VLSI Design: Systems and
Circuits, Sydney: Prentice-Hall of Australia Lt., 1988.
W. Wolf, Modern VLSI Design: A System Approach, Englewood Cliffs,
NJ: Prentice-Hall, 1994.
J. Schroeter, Surviving the ASIC Experience, Englewood Cliffs, NJ:
Prentice-Hall, 1992.
J. M. Rabaey and M. Pedram, Low Power Design Methodologies, Bos-
ton: Kluwer, 1996.
S. M. Kang and Y. Leblebici, CMOS Digital Integrated Circuits, New
York: McGraw-Hill, 1996.
C. Y. Chang and S. M. Sze, ULSI Technology, New York: McGraw-
Hill, 1996.
N. Sherwani, Algorithms for VLSI Physical Design Automation, Bos-
ton: Kluwer, 1993.
R. L. Gieger, P. E. Allen, and N. R. Strader, VLSI Design Techniques
for Analog and Digital Circuits, New York: McGraw-Hill, 1990.
L. J. Herbst, Integrated Circuit Engineering, London, Oxford Univer-
sity Press, 1996.
M. S. Smith, Application Specific Integrated Circuits, Reading, MA:
Addison-Wesley, 1997.

N. RANGANATHAN
RAJU D. VENKATARAMANA
University of South Florida
 INTEGRATING CIRCUITS 433

INTEGRATING CIRCUITS C
vI (t) R
Since inductors tend to be bulky and expensive (except for – vo (t)
applications at frequencies higher than approximately 1
iI (t) +
GHz), integrating circuits generally consist of a current signal
which is integrated onto a capacitor to form a voltage signal.
Cascading one integrating circuit to another requires that the
(a)
voltage signal be converted to a current signal. An integrating
circuit can be realized using an opamp, resistor, and capaci- VG C
tor. The input voltage is converted to an input current which
vI (t)
is directly proportional to the input voltage via Ohm’s Law.
G – vo (t)
This current is integrated onto the capacitor. The output volt-
age is produced at the output of the opamp. +
The major applications of integrating circuits are in filters,
slow analog-to-digital converters, and image sensor circuits.
(b)
Integrating circuits are the basic building blocks used to syn-
thesize frequency selective circuits, or filters. The complexity vI (t)
of the filter function, in terms of the number of poles, deter- io (t)
+ vo (t)
mines the number of integrating circuits that must be in- G
cluded in the circuit. A high precision but low speed technique –
for analog-to-digital conversion employs an integrating cir- Vg C
cuit, comparator, and a counter or timer. The integrating ca-
pacitor is charged for a specified amount of time by a current (c)
which is proportional to the input signal. The capacitor is dis-
Figure 1. Integrating circuits: (a) the inverting integrator, (b) the
charged by a fixed amount of current. The length of time re-
MOSFET-C integrator, and (c) the transconductance-C integrator.
quired to fully discharge the capacitor determines the value
of the input signal. Another major application of integrating
circuits is in image sensing circuits. Incident light is con- where vC(0) is the initial voltage stored on the capacitor. Note
verted to a photo-current which is integrated on a storage ca- that even a small dc input voltage will eventually result in an
pacitor for a specified length of time. The final voltage on the output voltage which is huge. A theoretically infinite output
capacitor is directly proportional to the photocurrent. voltage is prevented by the finite dc voltage supplies of the
Performance criteria for integrating circuits are cost and opamp.
dynamic range. In integrated circuits, cost is a nondecreasing The integrator time constant of the Miller integrator is
function of the silicon area occupied by the circuit and the RC, which has units of seconds.
power consumed by the circuit. We measure dynamic range
as the ratio of the largest to the smallest signal level that the The MOSFET-C Integrator
circuit can handle. A tradeoff exists between these perfor-
mance criteria; that is, the higher the dynamic range re- The MOSFET-C integrator is shown in Fig. 1(b). It is popular
quired, the higher the cost of the integrator. in integrated circuit design, where the amplifier, capacitor,
and resistance are fabricated on the same substrate. An MOS
transistor operating in the triode region acts like a voltage-
INTEGRATING CIRCUITS
controlled resistor, where the nominal conductance G ⫽ 1/R
has units of 1/⍀. Using the same analysis as for the Miller
There are several means of realizing the mathematical func-
integrator, we find that the integrating time constant is
tion of integration using only resistors, transistors, amplifi-
C/G. The two main advantages of the MOSFET-C integrator
ers, and capacitors. The function we want to synthesize is of
over the inverting integrator are: (1) an MOS transistor gen-
the form:
erally occupies less silicon area than an equivalent resistor,

t and (2) the conductance is tunable via the gate voltage VG.
vO (t) = A vI (t) dt + B (1) The latter property is particularly important in integrated
0
circuit design, where the tolerance on capacitors is approxi-
mately 10 to 50%.
The Inverting Integrator
The inverting integrator, also known as the Miller integrator, The Transconductance-C Integrator
is shown in Fig. 1(a). It is an inverting amplifier, where the The transconductance-C integrator is shown in Fig. 1(c). It
feedback element is the capacitor C. The input voltage, vI(t), consists of a transconductance amplifier which converts a dif-
is converted to a current iI(t) ⫽ vI(t)/R, since a virtual ground ferential input voltage to an output current via the relation
exists at the negative input terminal of the opamp. This cur-
rent is integrated on the capacitor, forming an output voltage iO = G(v+ − v− ) (3)
according to the relation,

t In Fig. 1(c), we note that v⫹ ⫽ vI(t), and v⫺ ⫽ 0 V. Thus, the
1 output current is equal to the input voltage times the conduc-
vO (t) = − vI (t) dt − vC (0) (2)
RC 0 tance. The current iO(t) is integrated on the capacitor, produc-

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.
434 INTEGRATING CIRCUITS

QR

C
C
r
– R
– r
+
vo (t) –
+
R1 R2 R3 +
C1
Figure 2. The feedforward Tow–Thomas vI (t)
two-integrator-loop biquadratic circuit.

ing the output voltage, vO(t). The integrator time constant is function is
the same as that for the MOSFET-C integrator, namely,  
C/G. The transconductance-C integrator is also used in inte- C1 1 1 r 1
s2 +s − + 2
grated circuit design. Compared to the MOSFET-C inte- VO (s) C C R1 RR3 C RR2
=− (4)
grator, the transconductance-C integrator has simpler cir- VI (s) 1 1
s2 + s +
cuits and is generally capable of operating at higher speeds. QCR C2 R2
On the other hand, the MOSFET-C integrator has a higher
maximum dynamic range at a given cost than the transcon- By a suitable choice of circuit components, Eq. (4) can be con-
ductance-C integrator. figured as a second-order low-pass, bandpass, high-pass,
notch, or allpass filter. Fourth and higher-order filter func-
Other Integrator Circuits tions are constructed by cascading two or more biquads to-
gether.
The switched-capacitor integrator employs a capacitor and at
least two MOS transistors operating as switches to emulate
Dual-slope Analog-to-digital Converter
the resistance R. A global clock signal, operating at a fre-
quency much higher than the bandwidth of the input signal, The dual-slope analog-to-digital converter (ADC) is a high-
turns the switches on and off at a rate which is inversely pro- precision but low speed ADC method. A block diagram is
portional to the effective resistance seen by the input. The given in Fig. 3(a). The dual-slope ADC consists of an inverting
switched-capacitor integrator is common in integrated circuit integrator, a comparator, a high-speed counter, and control
design. Tuning the integrator time constant is straightfor- logic. The charge on the capacitor is initially set to zero. Dur-
ward since it depends on the clock frequency and the ratio of ing the integration phase, the input voltage vI(t) is converted
capacitors. In integrated circuit design, the tolerance on the to an input current that is integrated on the capacitor C for a
ratio of capacitors can be lower than 1%. The cost of this de-
sign strategy is increased circuit complexity, power consump-
tion, and noise due to the global clock signal. C
If the input signal is a current, integration is easily S
vI (t) R
achieved using a single capacitor. During the reset phase of a
– vo (t) Comparator,
capacitor integrator, the capacitor voltage is set to a known VREF control logic,
initial voltage, typically either 0 V or VDD. During the integra- + and counter
tion phase, the input current is integrated on the capacitor to
produce an output voltage which is proportional to the input
current. This output voltage is typically buffered and scaled (a)
before it is sent off chip.

VDD
MAJOR APPLICATIONS OF INTEGRATOR CIRCUITS

Three major applications of integrator circuits are in filters,

dual-slope analog-to-digital converters, and image sensor cir- VSET
vo
cuits.
iI
The Biquadratic Filter C
The two-integrator-loop biquadratic circuit, or biquad, is used
to synthesize an arbitrary second-order filter function in s,
(b)
where s ⫽ j웆, and 웆 is the frequency in radians/s. The feedfor-
ward Tow-Thomas biquad is drawn in Fig. 2. It consists of two Figure 3. Two applications of integrating circuits: (a) a dual-slope
inverting integrators and an inverting amplifier. Its transfer analog-to-digital converter, and (b) a CMOS image sensor circuit.

fixed length of time. During the discharge phase, current de-
rived from a known reference voltage is used to discharge the
capacitor. The length of time, as measured in counts, required
to discharge the capacitor to 0 V is proportional to the input
voltage.
CMOS Image Sensor Circuits
CMOS image sensor circuits receive as input a photocurrent
which is proportional to the intensity of the incoming light.
The photocurrent is generated at a reverse-biased pn junction
in the silicon. A simplified diagram is shown in Fig. 3(b). A
description of its operation is as follows. The integrating ca-
pacitor is initially set to VDD. During the integrating time, the
photocurrent discharges the capacitor. The difference be-
tween VDD and the final voltage is proportional to the mean
value of the photocurrent.
PERFORMANCE CRITERIA
Two performance criteria that we consider are its cost, as
measured in its area and power dissipation, and dynamic
range. Other performance criteria may be relevant, such as
maximum bandwidth or minimum supply voltage.
Cost
In integrated circuit design, the cost of an integrator is a non-
decreasing function of the area and power consumption. In
this analysis, we assume that the technology is fixed; that is,
the designer is unable to change all the parameters of the
devices, except their size.
Area. The silicon area of an integrator is generally domi-
nated by the area of the capacitor. Define the capacitance per
unit area of a capacitor in a given fabrication technology as
COX, with units of F/m2. Then, the total area of the integrator
can be written as
C presence of two conductors, the noise level is found to be
A=ζ (5)
COX
where ␨ is an area factor that takes into account the portion
of silicon area used by the amplifier and conductor. This area
factor is always greater than unity.
Power. Static power consumption is the power supply volt-
age times the quiescent, or bias, current of the amplifier. Let
us denote the total amplifier bias current as IB, the positive
supply voltage as VDD, and the negative supply voltage as ⫺
VDD. Then the static power consumption is
PS = 2VDD IB (6)
Dynamic power consumption results primarily from the
charging and discharging of the integrating capacitance. In
most designs, dynamic power consumption is much larger
than static power consumption. The maximum dynamic
power consumption occurs when the capacitor is fully charged
and discharged with each cycle of the input signal. Let the
input signal have amplitude VDD and frequency f S. Then, the
INTEGRATING CIRCUITS 435
maximum dynamic power consumption is
PD = 4 f SVDD
2
C (7)
The factor 4 takes into account positive charging to VDD and
negative charging to ⫺VDD. Total power consumption is the
sum, PS ⫹ PD.
Dynamic Range
Dynamic range (DR) is defined as the maximum input level
the circuit can handle divided by the noise level. By level, we
mean the mean-square value of the input or output voltage.
Dynamic range is generally expressed in dB.
Noise. Sources of noise in the integrator are found in the
conductance and the amplifier. Thermal noise associated with
each element gives rise to a power spectral density that has
a flat frequency power spectrum with one-sided density
STH = 4kTRξ (8)
where k is Boltzmann’s constant, T is the absolute tempera-
ture, and ␰ the combined noise factors of the conductance and
amplifier. In general, ␰ is greater than unity.
Another major source of noise for integrators is 1/f, or
flicker, noise. Its power spectrum is proportional to the in-
verse of the frequency, hence, its name. Flicker noise becomes
dominant at low frequencies.
We now configure the integrator as a single-pole lowpass
filter by placing a conductance of value 1/R in parallel with
the capacitor. Its transfer function is given by
VO (s) 1
= (9)
VI (s) 1 + s/RC
Considering thermal noise only, the noise level at the output
is found by integrating the product of the power spectrum in
Eq. (8) and the square magnitude of the lowpass filter in Eq.
(9) over all positive frequencies. In order to account for the
kT
VN2 = 2 ξ (10)
C
The expression Eq. (10) shows that the noise level does not
depend on the value of the resistor, but primarily on the value
of the capacitory.
Distortion. The sources of distortion in the integrator are:
(1) the capacitor, (2) the amplifier, and (3) the conductance.
Linear capacitors are available in CMOS fabrication pro-
cesses suitable for analog and mixed-mode circuits. Linear ca-
pacitors are needed to obtain a high dynamic range inte-
grator. In addition, an amplifier which operates over the full
voltage supply range is necessary to achieve low distortion for
large amplitude input signals. If we suppose that the conduc-
tance is implemented using an MOS transistor operating in
the triode region, there will be some range of input voltages
over which the effective resistance is nearly constant. One
measure of distortion that is mathematically tractable is the
maximum deviation of the effective resistance, expressed as a
percent of the nominal value. Then, the linear range is de-
436 INTEGRO-DIFFERENTIAL EQUATIONS

fined as the continuous set of input voltages over which the
maximum deviation of the effective resistance is less than
d% of the nominal value, where d% is the amount of distor-
tion. Other distortion measures are possible, such as mean-
square error; however, they can be much more complex to
compute, as they may require knowledge of the input signal
and the circuit topology.
The highest achievable linear range is limited by the volt-
age supplies. As such, the maximum input and output ampli-
tude range for a sinusoidal signal is VDD. For an input signal
of maximum amplitude, the level is VDD2 /2. As a result, the
highest achievable dynamic range of the low-pass filter is
2 Design of Analog-Digital VLSI Circuits for Telecommunication and
VI2 CV DD
DR = = (11)
VN2 4kTξ
Cost Versus Dynamic Range
Here, we relate the cost of the integrator to its dynamic
range. If we only consider dynamic power dissipation as found
in Eq. (7), we see that
P / fs
DR = D (12)
16kTξ
cluded, then, that the MOSFET-C integrator can approach
the dynamic range maximum in Eq. (11), whereas the best
transconductance-C integrator is at least several dB lower.
BIBLIOGRAPHY
A. S. Sedra and K. C. Smith, Microelectronic Circuits, 4th ed., New
York: Oxford University Press, 1998.
P. R. Gray and R. G. Meyer, Analysis and Design of Analog Integrated
Circuits, 3rd ed., New York: Wiley, 1993.
Y. Tsividis, The MOS Transistor, New York: McGraw-Hill, 1988.
E. Vittoz, Micropower techniques, in J. Franca and Y. Tsividis (eds.),
Signal Processing, Englewood Cliffs, NJ: Prentice-Hall, 1994.
G. Groenewold, Optimal dynamic range integrators, IEEE Trans. Cir-
cuits Syst. I, Fundam. Theory Appl., 39: 614–627, 1992.
P. M. Furth and A. G. Andreou, A design framework for low power
analog filter banks, IEEE Trans. Circuits Syst. I, Fundam. Theory
Appl., 42: 967–971, 1995.
PAUL M. FURTH
New Mexico State University
ANDREAS G. ANDREOU
Johns Hopkins University

Both the numerator and the denominator in Eq. (12) have the
units of energy. Thus, the upper limit on the dynamic range
of the low-pass filter is directly proportional to the amount of
INTEGRATION. See CALCULUS.
energy dissipated in the integrator. For example, in order to INTEGRATION OF DATABASES. See DATABASE
achieve a dynamic range of 60 dB, we must dissipate at least DESIGN.

16 ⫻ 106 kT␰ J per cycle of the input signal.

We can rearrange Eq. (7) to solve for frequency of the input
signal, as in

PD
fS = 2 C
(13)
4VDD

Thus, for fixed power supply voltage and power consumption,

the input frequency is constrained by the size of the capacitor.
The lower the frequency of the input, the larger the area of
the integrating capacitor. Values of integrated capacitors
range from as low as 10 f F to as high as 1 nF; however, the
area penalty of the largest value is not amenable to mixed
analog/digital circuits.

Differential Signaling
Differential signaling is a technique used primarily in inte-
grated circuits to increase the maximum amplitude range of
the input and output signals by a factor of two. Differential
signaling has two other major benefits: even-order distortion
in the amplifier, conductor, and capacitor is cancelled, as are
common-mode sources of noise. The cost of using differential
signaling is increased circuit complexity, area, and static
power consumption due to common-mode feedback circuitry.
The MOSFET-C integrator is unable to take full advantage of
differential signaling since the capacitor must have a virtual
ground at one node. Thus, its maximum dynamic range is
given by Eq. (11). On the other hand, the transconductance-
C integrator can employ a differential signal across the capac-
itor. Notwithstanding, the transconductance-C integrator
cannot operate at the maximum input amplitude. It is con-
INTERMEDIATE-FREQUENCY AMPLIFIERS
INTERMEDIATE-FREQUENCY AMPLIFIERS FOR AM AND
FM
The intermediate-frequency (IF) amplifier is the circuitry
used to process the information-bearing signal between the
first converter, or mixer, and the decision making circuit,
or detector. It can consist of a very few or a great many
component parts. Generally, it consists of an amplifying
stage or device to provide gain and a band-pass filter to
limit the frequency band to be passed. The signal to be
processed can be audio, video, or digital, using Amplitude
Modulation, Frequency Modulation, Phase Modulation or
combinations thereof. Several examples are shown in Figs.
13 through 19.
IF amplifiers are also used in radio transmitters to limit
the occupied bandwidth of the transmitted signal. Certain
modulation methods create a very broad frequency spec-
trum which interferes with adjacent channels. Regulatory
agencies, such as the FCC, require that these out-of-band
signals be reduced below a certain permissible level, so
they must undergo processing through a bandwidth lim-
iting filter and amplifier.
For each application there are certain design restric-
tions or rules which must be followed to achieve optimum
results.
General IF Amplifier Functions and Restrictions
1. Image Rejection The mixer stages in a receiver con-
vert a frequency below or above the local oscillator
frequency to an IF frequency. Only one of these fre-
quencies is desired. The IF frequency must be cho-
sen so that undesirable frequencies or images are re-
moved by the RF amplifier filter and are rejected by
the mixer. This may mean that two or three differ-
ent IF frequencies must be used within the same re-
ceiver. The IF frequencies in common use range from
0 Hz to approximately 2.0 GHz.
2. Selectivity Selectivity is required to reject as much
as possible of any adjacent channel’s interfering sig-
nal. Generally this means obtaining a band-pass fil-
ter characteristic as close to that of the ideal filter
as possible to pass the necessary Nyquist bandwidth
(the baseband bandwidth from 0 Hz to the highest
frequency to be passed) without introducing harmful
amplitude or phase distortion.
3. Gain Gain is required to amplify a weak signal to
a useful level for the decision making circuit. This
gain must be provided by a stable amplifier that in-
troduces a minimum of noise, so as not to degrade
the receiver noise figure. All circuit input and output
impedances should be properly matched for optimum
power transfer and circuit stability.
4. Automatic Gain Control The amplifier gain must
vary automatically with signal strength so that the
decision making circuit receives a signal of as nearly
constant a level as possible. The stages of the IF am-
J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright © 2007 John Wiley & Sons, Inc.
plifier must not be overdriven or go into limiting until
after the last band-pass filter to prevent “splattering”
or broadening and distortion of the signal.
5. Linearity The amplifier must be linear to prevent dis-
tortion of the recovered information. AM receivers
should be linear in amplitude, whereas FM or PM
receivers should be linear in phase.
Selecting the IF Frequency
Image rejection and signal selectivity are the primary rea-
sons for selecting an IF frequency. Most currently manufac-
tured band-pass filters of the crystal or resonator type are
standardized so that the designer can obtain off the shelf
components at reasonable cost for these standard frequen-
cies. The standard AM broadcast receiver utilizes a 455
kHz IF filter because extensive experience has shown that
this rejects all but the strongest images. Assume that the
desired signal is at 600 kHz. A local oscillator operating
at 1,055 kHz has an image frequency at 1,510 kHz, which
the RF input filter easily rejects. Similarly, an FM receiver
operating at 90.1 MHz with an IF frequency of 10.7 MHz
has an image at 111.5 MHz, which is rejected by the RF
amplifier. A single IF frequency is used in both of these
cases. A receiver operating at 450 MHz requires two IF
frequencies obtained by using first and second mixers, as
in Fig. 16. The first IF amplifier may consist of a relatively
broadband filter operating at 10.7 or 21.4 MHz, followed
by a second converter and IF stage operating at 455 kHz.
The first IF filter is narrow enough to reject any 455 kHz
images, and the second IF filter is a narrowband filter that
passes only the desired signal bandwidth. If the 455 kHz
filter had been used as the first IF filter, the 450 MHz RF
filter, being relatively broad, would not have eliminated the
image frequency, which is 455 kHz above or below the local
oscillator frequency.
Television receivers use a video IF frequency of approx-
imately 45 MHz, because this allows a relatively broad RF
filter to pass the broadband TV signal, while still rejecting
the images. The video signal from the IF amplifier is AM
with an FM sound carrier riding on it. Television sound is
generally obtained from a beat, or difference frequency, be-
tween the video and sound carriers, which is at 4.5 MHz.
Satellite receivers use a broadband first IF frequency cov-
ering a frequency block from 900 MHz to 2.1 GHz. This is
done by a “Low Noise Block” converter (LNB). The second
mixer is tunable so that any frequency in the block is con-
verted to the second IF frequency, usually fixed at 70 or
140 MHz. The second IF frequency, which drives the detec-
tor, has a narrower bandwidth to reduce noise and reject
adjacent channel interference.
Crystal, ceramic resonator and SAW filters are mass
produced at relatively low cost for the frequencies men-
tioned previously, so that most consumer products employ
one or more of these standard frequencies and standard
mass produced filters.
Selectivity
Carson’s rule and the Nyquist sampling theorem, on which
it is based, state that a certain bandwidth is required to
2 Intermediate-Frequency Amplifiers
transmit an undistorted signal. The necessary bandwidth
for an AM signal is given as
Thus an AM broadcast receiver requires 10 kHz of band-
width to pass a 5 kHz = fm audio tone. In data transmission
systems, the frequency fm corresponding to the data rate fb ,
is given by fm = ½ fb . The data clock frequency is twice the
frequency of the data in ones and zeros. This means that a
baud rate fb of 9,600 bits per second requires a bandwidth
of 9.6 kHz.
For FM, the necessary bandwidth required for trans-
mission is given by
A 15 kHz audio tone (= fm ) and an FM transmitter devi-
ated with a modulation index of 5 requires 2 [15 + (15 ×
5)] = 180 kHz of bandwidth.
f is (5 × 15) and fm is 15
kHz. Narrow band FM (with a modulation index less than
0.7) is somewhat different in that the bandwidth actually
required is the same as that for AM because the higher
Bessel products are missing (Eq. 1).
These values are for “double-sideband” transmission.
Single-sideband transmission requires half as much band-
width. The required baseband bandwidth is the same as
the value for fm . This is also known as the “Nyquist band-
width,” or the minimum bandwidth that carries the signal
undistorted at the baseband.
Ideally the IF filter, or the baseband filter, need pass
only this bandwidth and no more. This requires an “ideal”
band-pass or low-pass filter, which does not exist, but is
approached by various means. The filter must be as nar-
row as conditions permit to reduce the noise bandwidth and
any adjacent channel interference, because noise power in-
creases linearly with increasing filter bandwidth.
Gain
The IF amplifier must provide sufficient gain to raise a
weak signal at the RF input to the level required, or de-
sired, by the decision making circuit or detector. This re-
ceiver gain varies from 0 up to 130 dB, most of which must
be provided by the IF amplifier. The RF amplifier and mixer
circuits preceding the IF amplifier generally provide 20 or
more dB of gain so that the IF amplifier generally con-
tributes little to the receiver noise figure. See “noise figure”
elsewhere in this article.
Gain is provided by an amplifying device, such as a tran-
sistor or vacuum tube (in older equipment). These devices
have complex input and output impedances that must be
matched to the filtering circuits for best power transfer,
stability, and lowest noise. Current practice is to use a
“gain stage” which consists of multiple amplifying devices
in an integrated circuit package. These packages contain
the mixer stages and detectors.
Automatic Gain Control
Receivers must respond to a wide range of input levels
while maintaining a nearly constant level at the detector or
decision making circuit. The user or operator does not wish
to manually adjust the gain to obtain a constant sound or
picture level when changing stations. This function is per-
formed by detecting the output level of the IF amplifier and
correcting it by a feed-back circuit that adjusts the level
to keep it as constant as possible. Because this detected
level varies rapidly, it is passed through a low-pass filter
(usually an RC pair) to integrate or slow down the changes,
then amplified by a dc amplifier, and applied to an IF ampli-
fier circuit or gain stage with variable gain characteristics.
Some receivers, such as those in an automobile, require
relatively rapid acting automatic gain control (AGC) cir-
cuits, whereas fixed receivers use a much slower AGC time
constant. Dual-gate, field-effect transistors use the second
gate to control the gain. Bipolar or single-gate, field-effect
transistors vary the gain by a bias voltage or current ap-
plied to the input terminal along with the signal. Special
integrated circuit gain stages for IF amplification are avail-
able, such as the Motorola MC 1350, which amplify and
provide a variable gain control function.
Band-Pass Filters for IF Amplifiers
Except for block conversions, which convert wide frequency
bandwidths, such as those used on satellite receivers, IF
amplifiers generally use a narrow band-pass or a low-pass
filter to limit the bandwidth to the Nyquist bandwidth.
Block conversion, on the other hand, uses a high-pass/low-
pass filter pair where the bandwidth to be passed is be-
tween the high and low cutoff frequencies.
The traditional band-pass filter requires a resonant el-
ement. Although the actual resonator may be a coil and
capacitor, ceramic resonator, or SAW filter, the principles
are basically the same. Digital filters which do not use
resonators have been employed more recently. These are
discussed later in brief. They are discussed in more detail
elsewhere in this encyclopedia.
The inductance/capacitor resonator was the first used,
and is still a comparison standard. Figure 1(a) shows a se-
ries resonant circuit and Fig. 1(b) shows a parallel resonant
circuit. These circuits pass a signal at the resonant peak
and reject a signal off resonance. Rs and Rp are naturally
occurring losses that reduce the circuit efficiency. Figure 2
shows the universal resonance curve which is applicable to
both series and parallel resonant circuits. It is important
to note that the signal rejection never goes to a zero level
in the area of interest, but reaches an asymptotic value of
about 0.2 or −15 dB. If it is necessary to reject a signal on
the shoulders of this curve by 60 dB, then four cascaded
stages of this filter must be used to obtain the necessary
rejection. Note also that there is a nonlinear phase shift
that reaches a maximum in the area of interest of about
±70◦ . When stages are cascaded, this phase shift is mul-
tiplied by the number of stages. A nonlinear phase shift
causes distortion in FM receivers.
A frequency f0 , at which the response of a parallel reso-
nant LC filter is a maximum, that is, the point at which the
parallel impedance is a maximum, is defined as a “pole.” A
frequency at which the impedance is a minimum, as in the
series LC circuit, is defined as a zero. Thus the previous as-
sumed four cascaded stages above constitute a four-pole fil-
ter, because it contains four resonant poles. The frequency

Figure 1. Series and parallel resonant circuits. Rp and Rs are
loads that reduce the efficiency of the circuit.
Figure 2. The “Universal Resonance Curve.” The phase change
is shown for series resonance. The phase reverses for parallel res-
onance. α = Q (Hz off resonance)/(Resonant frequency).
of resonance is given by Eq. (3). This is the frequency at
which Xc = 1/−jωC and XL = jωL are equal.
The bandwidth that an analog LC filter passes is altered
by the circuit efficiency, or circuit Q, given in Eqs. (4a),
(4b), and (4c). Generally the bandwidth is specified as the
bandwidth between the −3 dB points.
For simplicity in analyzing the following circuits, the Q
determining R is assumed to be a parallel resistance Rp
across the inductance.
The amplitude response of the resonant circuit is given
by Eq. (5a) and the phase response by Eq. (5b).
1 to the following stage, assumed to be an identical transis-
G( jω) = A( jω) =
1 + jQ(2
f/ fo )
Intermediate-Frequency Amplifiers 3
Figure 3. A typical transistor IF circuit with bandpass filter.
Q(2
f/ fo )
Tanϕ =
1
Figure 3 shows a typical IF amplifier stage used in ear-
lier transistor radios. In this circuit R p (the total shunt-
ing resistive load) is actually three resistances in parallel,
one the equivalent Rp of the coil itself (representing the
coil losses), another the input resistance of the following
stage, as reflected, and the third the output resistance of
the driving transistor, as reflected. It cannot be assumed
that the resulting coil Q and, hence, the selectivity of the
circuit is that of the unloaded coil and capacitor alone.
Dual-gate, field-effect transistors have the highest shunt-
ing resistance values, and bipolar transistors the lowest.
The gain is varied by increasing or decreasing the bias volt-
age Vb applied to the input terminal.
Manufacturers of amplifying devices often provide the
impedances, or admittances, of their products on their data
sheets. Formerly this was done in the form of h parameters.
The more common practice today is to provide the infor-
mation in the form of S parameters. These values can be
converted to impedances and admittances, but the manual
process is rather complicated. An easier method is to use
the various software programs (see references) to make the
conversion. Matrix algebra and “h” and “S” parameters are
discussed elsewhere in this article and also in references
(3, 4). Unfortunately, S parameters for band-pass filters are
rarely available.
Figure 4(a) shows the equivalent circuit of the transistor
as the tuned LC sees it. The transistor amplifies a current
which is passed through a relatively low driving resistance
Rs to the outside. At the same time, the attached LC sees
an equivalent shunting resistance Rc and capacitance Cc
which must be added in parallel to Rp , L, and C. The input
tor, has a relatively low shunting resistance Ri , and capac-
4 Intermediate-Frequency Amplifiers
Figure 4. (a) The equivalent circuit of a transistor amplifier. (b)
The equivalent circuit of Fig. 3 when all of the shunting loads are
included.
itance Ci which must be added. Unless the added capaci-
tances are large compared to the resonant C, they merely
add to it without greatly detuning the circuit. When tuned,
the total C plus L determine the frequency and the result-
ing total R p determines the Q of the LC circuit, hence the
bandwidth. Thus the complex components are tuned out,
and the remaining design problem consists of matching the
real or resistive part of the input and output impedances
to the best advantage.
The desired result is to couple the output of the driv-
ing stage to the input of the following stage with the least
loss by matching the differing impedances. An additional
desired result is to narrow the band of frequencies passed
by a filter. These objectives are accomplished by transform-
ing the input and output impedances to a higher or lower
shunting impedance that maintains the desired bandpass
characteristic of the filter. A low driving or load impedance
can be stepped up to a very high impedance which main-
tains the circuit Q at the desired value.
Impedance matching enables the designer to change the
actual impedance to a different apparent value which is op-
timum for the circuit. Figure 5 shows how impedances are
matched by transformer action. A transformer with a 3:1
turn ratio is shown as an example. The output impedance
relative to the input impedance is given by Eq. (6). Ni and
No are the input and output numbers of turns on the wind-
ing.
Thus 90  at the input is seen as 10  at the output. The
auto transformer [tapped coil in Fig. 5(b)] has the same
relationship.
When all of the reactances and resistances from the
tuned circuit and the transistor input and output, as mod-
ified by the step-up/step-down process of the impedance
Figure 5. Impedance step up or down using a transformer.
Figure 6. Impedance matching utilizing capacitors.
matching networks are added, the network in Fig. 4(b) re-
sults. To calculate the resonant frequency and circuit Q
from these reactances and resistances in parallel is compli-
cated unless they are converted to admittances. Software is
available at reasonable cost to perform these calculations.
See references.
Stock or mass produced IF transformers often do not
have the desired turns ratio to match the impedances. An
additional Z match circuit using capacitors enables the
available transformers to match almost any impedance.
This capacitor divider circuit is often used instead of a
tapped coil or transformer as shown in Fig. 6.
The formulas for calculating the matching conditions
with capacitors are more complex than those used for
transformer coupling, because there are more variables.
In this circuit Ri , is assumed to be lower than Rp . Although
Rp is the equivalent parallel resistance of the LC circuit in
Fig. 6, it could also be the reduced resistance or reflected
Rp2 at a transformer tap. N in these equations is equal
to the loaded resonator Q, or to a lower arbitrary value if
total shunting Rp is lowered by transformer action as in
equation (6) or if the component ratios become unwieldy.

Figure 7. Double-tuned circuits coupled together.
Equations (8) and (9) calculate the reactances of the two
capacitors. Note that NXL is the same as QXL . Starting
with a value of N = Q, find XC1 , then XC2 .
If Q is large in Eq. (7), the equations reduce to the ap-
proximate values in Eqs. (10) and (11). Unless Q is less than
10, these approximate equations are accurate enough for
general use. As an example, let Ri = 100  and Rp = 10,000
 with Q = 100. Then using Eq. (10), XC2 becomes 10 
and XC1 becomes 100 . C2 is approximately ten times as
large as C1 . Note the similarity of this ratio to Eq. (6). If a
transformer is involved, N becomes much smaller and the
full formulas Eqs. (7), (8), and (9) should be used.
Equations (7) through (9) apply for R1 < Rp , and N >
(Rp /R1 − 1)1/2 .
Double-Tuned Circuits
When two identical LC circuits are coupled together, as
in Fig. 7, a number of responses are possible as in Fig.
8. The amplitude response depends on the coupling coeffi-
cient K. Undercoupling results in a two-pole filter with the
sharpest selectivity. Critical coupling results in the nar-
rowest bandwidth with the highest gain. Transitional cou-
pling is slightly greater than critical coupling and results
in a flat topped response with a wider bandwidth. Over-
coupling results in a double-humped response with sharper
skirts and broad bandwidth. The coupling coefficient is cal-
culated using Eqs. (5a–d). Equation (12a) applies to mutual
inductive coupling and Eqs. (12b–d) to capacitive coupling.
Equation (12a) calculates the coupling coefficient for two
identical LC tuned circuits that are coupled together by
leakage inductance [Fig. 7(a)], often obtained by using
shielded coils with holes in the sides of the shield cans to
allow the magnetic fields to interact. The size of the hole
determines the value of the mutual inductance M. Because
this is difficult to control, a coupling capacitor is often used
as shown in Fig. 7(b,c). The critical coupling value is given
by Eq. (12(b)). The coupling coefficients for Fig. 7(b,c) are
given in Eqs. (12 c,d).
Intermediate-Frequency Amplifiers 5
Figure 8. The effects of various coupling coefficients.
The amplitude response curves in Fig. 8 do not yield any
information as to the phase shifts that take place through
the filter. In AM circuits, phase is generally of little concern,
and most attention is paid to the amplitude ripple and lin-
earity. In FM circuits, nonlinear phase shift, or a related
term “differential group delay,” becomes more of a problem
and efforts are made to keep the phase shift as linear as
possible. In data transmission circuits using phase mod-
ulation, any nonlinearity must be avoided. For these rea-
sons, the coupling coefficients are carefully adjusted, and
cascaded IF amplifier stages are used to get the desired
transfer function for the IF amplifier.
CASCADING IF AMPLIFIER STAGES AND FILTERS
All filtering actions between the RF receiver input and the
decision making circuit are parts of the IF amplifier band-
pass filter. Because the decision making circuit is at base-
band, or 0 Hz, all filtering before the decision making cir-
cuit is part of the IF bandpass filtering, which should be
treated as a whole.
A single LC circuit seldom has the desired bandpass
characteristic for an IF amplifier. Cascading IF amplifier
stages with differing coupling and Q values enables the
designer to obtain the desired transfer response. One com-
bination of LC filters uses an overcoupled, double-tuned
stage followed by a single tuned stage with a lower Q.
The result is a three-pole filter with relatively steep skirt
slopes. Cascading these stages results in filters with re-
sponses resembling Butterworth, Chebycheff, elliptical, or
equal-ripple filters which are noted for rejecting adjacent
channel interference. See Figs. 9 and 10.
When additional filtering is required at the baseband,
simple RC filters, low-pass LC filters, or digital FIR filters
are used. These and other filters are discussed in greater
detail elsewhere in this encyclopedia.
Crystal and Ceramic Filters
Figure 11(a) shows the equivalent circuit of a crystal or a
ceramic resonator. These devices have both a pole and a
zero whose frequencies are located relatively close to each
other. Quartz crystals have Q values from 2,000 to 10,000
or more depending on the mechanical loading of the crys-
6 Intermediate-Frequency Amplifiers
Figure 9. Two amplifier stages cascaded. The first stage is over-
coupled; the second stage with a lower Q is critically coupled.
Figure 10. The overall response of the two cascaded stages in
Fig. 9.
Figure 11. (a) The equivalent circuit of a crystal or ceramic res-
onator. (b) Two resonators are coupled together to form a bandpass
filter.
tal. Ceramic resonators usually have Q values between 100
and 400. The higher the Q, the narrower the filter band-
pass. When two of these devices are connected as shown in
Fig. 11(b), the result is a band-pass filter with steep skirts,
as in Fig. 12. These devices are always used in pairs to
make a two-pole filter, which then is combined in a single
container with other pairs to create a filter with as many as
eight or more poles. They usually have excellent adjacent
channel rejection characteristics.
Figure 12. The frequency response of the two-pole crystal res-
onator in Fig. 11(b).
When using these devices, care must be taken to care-
fully match the specified impedance. Any impedance mis-
match seriously alters the response curve of the filter. The
impedance matching techniques previously discussed en-
able the designer to obtain a very close match which op-
timizes the circuit performance. Typical input and output
impedances range from 50 to 4,000 . Crystal filter makers
often build in transformer or other tuned matching circuits
so that the user does not need to provide a matching circuit
outside the crystal filter.
Surface acoustic wave (SAW) filters utilize a crystal os-
cillating longitudinally with many fingers or taps placed
along the surface. They are made with very broad band-
pass characteristics, which makes them well suited for TV
IF amplifiers, spread-spectrum IF filters, and other uses re-
quiring wide bandwidths. They have losses which are typ-
ically about 8 to 20 dB, so they must have amplifiers with
adequate gain ahead of them if the receiver noise figure is
not to be degraded. They are not suitable for narrowband
or low-frequency applications.
Baseband IF Filtering
IF filters with specific response characteristics are some-
times very difficult to obtain, whereas the desired charac-
teristic is easily and inexpensively obtainable at the base-
band. This concept is often applied to transmitters where a
sharp cutoff filter is obtained with simple components, such
as the switched filter. An eight-pole equivalent at baseband
becomes a 16-pole filter at the modulation IF frequency. For
example, a sharp cutoff filter for voice with a 4 kHz audio
cutoff results in a bandpass filter 8 kHz wide at RF after
modulation, with the same sharp cutoff. The same cutoff
characteristics at RF are almost impossible to obtain in a
crystal filter, which is also very costly and beyond the bud-
get for a low-cost transmitter, such as a cordless telephone.
By using baseband filtering, a poor-quality RF filter that
rejects only the opposite image is used. Similarly, a wide-
band or poor-quality IF filter is used ahead of a detector
if the undesired signal components are filtered off later at
baseband by a sharp cutoff filter.
Switched capacitor filters are available as packaged in-
tegrated circuits that are used at baseband and some lower
IF frequencies. They have internal operational amplifiers
with a switched feedback capacitor, the combinations of
 Intermediate-Frequency Amplifiers 7

which determine the filter characteristics. Because they

depend on the speed of the operational amplifiers and the
values of the feedback capacitors, they seldom function
much above 100 kHz. They can be configured as Bessel,
Equal-ripple and Butterworth filters. Typical of this type
of filter are the LTC 1060 family manufactured by Lin-
ear Technology Corporation and the MAX274 from Maxim.
As Bessel type filters, they perform well out to about 0.7
times the cutoff bandwidth, after which the phase changes
rapidly and the Bessel characteristic is lost.
Digital signal processing (DSP) at baseband is widely
used to reduce the component count and size for baseband
filters in very small radio receivers, such as cordless and
cellular telephones. Almost any desired filter response is
obtained from DSP filters without inductances and capac- Figure 13. An integrated circuit with built-in IF amplifier that
itors which require tuning. FIR filters have a flat group comprises an almost complete AM radio.
delay response and are the best choice for FM or PM filter-
ing.

Amplifying Devices for IF Amplifiers

Transistors in one form or another are the standard for
IF amplifiers. The single, bipolar or field-effect transistor
(FET) used as an individual component, was formerly the
preferred device. For very high Q circuits, the dual-gate
FET performs best, because it is the most stable and offers
the lowest shunt resistance. Single-gate, FET devices often
have too much drain-to-gate capacitance for good stability.
Modern bipolar transistors usually have good stability, but
higher shunt resistances than dual-gate FETs. Stability is
discussed later in this section.
MMIC devices are stable and have good gain, but the
shunt impedance is too low for any bandpass filter except
a crystal filter matched to 50 .
The most recent practice for IF amplifiers is to use inte-
grated circuit blocks containing more than one transistor
in a gain stage. These are then packaged together in an in-
tegrated circuit with other circuit components to form an
almost complete radio. Integrated circuits of this type are
shown later.
Typical Consumer IF Amplifiers
Consumer radio and TV equipment is mass produced at
the lowest possible cost consistent with reasonable quality.
Manufacturers of integrated circuits now produce single-
chip IF amplifiers that are combined with mass produced
stock filters to produce a uniform product with a minimum
of adjustment and tuning on the assembly line. In the ex-
amples that follow, some circuit components inside and out-
side the IC have been omitted to emphasize the IF amplifier
sections.
Figure 13 shows a single-chip AM receiver that uses the
Philips TDA 1072 integrated circuit and ceramic IF filters
at 455 kHz. The input impedance of the ceramic filter is
too low to match the output impedance of the mixer, so
that a tuned matching transformer is used to reduce the
passed bandwidth and to match the impedances. The input
impedance of the IF amplifier was designed to match the
average impedance of the ceramic filters available. This
integrated circuit has a built-in automatic gain control that
keeps the received audio output level relatively constant at
Figure 14. An integrated circuit for FM use that comprises an
almost complete FM receiver.
250 mV as long as the input signal level to the chip exceeds
30 µV.
Figure 14 shows a single-chip FM radio based on the
NXP (Phillips) NE605 integrated circuit that uses ceramic
IF filters at 10.7 MHz. The input and output impedance
of the IF amplifier sections is approximately 1500  to
match the ceramic filter impedance, so that no matching
transformer is required. The audio output is maintained
constant at 175 mV for all signal levels at input levels from
−110 dBm to 0 dBm. An automatic frequency control (AFC)
voltage is obtained from the quadrature detector output.
AGC is available from all FM integrated circuits so that
the gain of the mixer and RF stages is controlled at a level
that does not allow these stages to be saturated by a strong
incoming signal. Saturation or nonlinearity before filtering
results in undesirable signal spreading. The NE605 has a
“Received Signal Strength Indicator” (RSSI) output which
is amplified and inverted if necessary to provide an AGC
voltage or current for the RF amplifier and Mixer.
Figure 15 shows a TV IF amplifier using the Motorola
(Freescale) MC44301/2 Video IF integrated circuit with a
SAW filter at 45 MHz. The SAW filter band-pass is ap-
proximately 6 MHz wide to pass the video and sound. The
circuit has both AFC and AGC features built in. Unlike
the IF amplifiers used for AM and FM audio broadcast
8 Intermediate-Frequency Amplifiers
Figure 15. An integrated circuit for a TV IF amplifier that detects
both the AM video and the FM subcarrier sound.
applications, the TV IF amplifier includes a phase-locked
loop and a synchronous detector which locks the frequency
of an internal oscillator to the IF frequency. This locked,
or synchronous oscillator output is then mixed with the
information-bearing portion of the signal to create a base-
band signal. This is one of a family of 0 Hz IF amplifiers
which are becoming more popular in radio designs, because
they permit most or additional signal processing at base-
band. In the TV case, the video and sound carriers are both
passed by the SAW filter. They beat together at 4.5 MHz in
the detector, providing a second IF stage with the sound in-
formation. This 4.5 MHz IF information is then filtered by
a ceramic filter approximately 50 kHz wide to remove any
video components, limited, and detected as a standard FM
signal to provide the TV sound. Then the video portion, con-
sisting of signals from 15 kHz to approximately 4.25 MHz,
is further processed to separate the color information at
3.58 MHz from the black and white information. The video
output level is detected to provide the AGC voltage.
The phase-locked oscillator, operating at the IF fre-
quency, also provides automatic frequency control to the
first mixer stage local oscillator.
Figure 16 shows a dual conversion receiver for commu-
nications utilizing the Motorola (Freescale) MC13135 inte-
grated circuit. When the receiver is operated at 450 MHz
or 850 MHz, as mentioned previously, single conversion IF
stages do not offer the necessary image rejection. This re-
ceiver is for narrowband AM or FM as opposed to wide-
band FM for entertainment purposes. The first IF filter is
a low-cost ceramic filter at 10.7 MHz. The second filter is
a multipole crystal or ceramic filter with a band-pass just
wide enough to pass the audio with a small FM deviation
ratio. Radios of this type are used for 12.5 kHz and 25 kHz
channel spacings for voice-quality audio. Analog cellular
telephones, aircraft, marine, police, and taxicab radios are
typical examples.
Direct Conversion and Oscillating Filters
Direct conversion converts the RF frequency directly to the
baseband by using a local oscillator at the RF frequency.
The TV IF amplifier with the detector circuit given in Fig.
15 illustrates some of the reasons. Conversion to baseband
occurs at the IF frequency or directly from the RF fre-
quency.
There is a noticeable trend in integrated circuit design
to utilize synchronous detection and restore the carrier by
a phase-locked loop, as in Fig. 15, or by regenerative IF am-
plifiers, to achieve several desirable features not obtainable
from classical circuits with square law detectors.
In the case of direct RF to baseband conversion, there
is no IF stage in the usual sense, and all filtering occurs at
the baseband. For this reason, direct conversion receivers
are referred to as zero Hz IF radios. Integrated circuits for
direct RF conversion are available that operate well above
2.5 GHz at the RF input.
It was discovered in the 1940s that the performance of
a TV receiver is improved by using a reconstructed syn-
chronous or exalted carrier, as occurs in the TV IF ampli-
fier described in Fig. 15. The carrier is reduced by vestigial
sideband filtering at the transmitter and contains undesir-
able AM signal components. By locking an oscillator to, or
synchronizing it with the carrier, and then using it in the
detector, a significant improvement in the received signal is
achieved. Before using circuits of this type, the intercarrier
sound at 4.5 MHz in earlier TV sets had a characteristic
60 Hz buzz due to the AM on the carrier. By substituting
the recovered synchronous carrier instead, this buzz was
removed. Figure 15 is an example.
The earliest direct conversion receivers using locked os-
cillators or synchronous detectors were built in the 1920s,
when they were known as synchrodyne or homodyne re-
ceivers. The theory is relatively simple. A signal from the
RF amplifier is coupled to an oscillator causing a beat or
difference frequency. As the frequencies of the two sources
come closer together, the oscillator is pulled to match the
incoming signal. The lock range depends on the strength of
the incoming signal. Then the two signals are mixed to pro-
vide a signal at the baseband, which is further filtered by
a low-pass filter. In this way, a relatively broad RF filter is
used, whereas the resulting AM signal bandwidth after de-
tection and baseband filtering is very narrow. The Q of the
oscillator tank circuit rises dramatically with oscillation,
so that Q values of 6,000 to 10,000 are not unusual and
selectivity is greatly improved. AGC is obtained from the
audio signal to maintain a constant input signal to insure a
good lock range. An undesirable characteristic is the whis-
tle or squeal that occurs between stations. Later receivers
used a squelch circuit to make the signal audible only after
locking occurred. High-quality receivers for entertainment
and communications, which use this principle have been
produced in the 1990s. They offer higher sensitivity, better
fidelity and more controlled response. Integrated circuits
for receivers of this type (direct conversion) are now being
produced for paging, direct broadcast TV, and for cellular
and cordless telephones. The MAX 2101 and MAX 2102
integrated circuits are typical examples.
Oscillating filters and phase-locked loops are similar in
principle. An IF frequency is applied to a phase/frequency
detector that compares the IF carrier frequency with
the oscillator frequency. An error voltage is created that
changes the oscillator frequency to match or become co-
 Intermediate-Frequency Amplifiers 9

herent with that of the incoming IF carrier frequency. In

some cases the phase-locked loop signal is 90◦ out of phase
with the carrier, so that a phase shifter is used to restore
the phase and make the signal from the oscillator coher-
ent with the incoming signal. See Figs. 15 and 19 where
phase-locked loops and phase shifters are employed.
Synchronous oscillators and phase-locked loops (PLL)
extend the lower signal to noise ratio, and they also have
a bandwidth filtering effect as well. The noise bandwidth
of the PLL filter is the loop bandwidth, whereas the actual
signal filter bandwidth is the lock range of the PLL, which
is much greater. Figure 17 shows the amplitude and lin-
ear phase response of a synchronous oscillator. The PLL Figure 17. The filtering effect of a synchronous oscillator used as
is not always the optimum circuit for this use because its a band-pass filter. The filter bandpass is the tracking range. The
noise bandwidth is limited by the Q of the oscillating circuit.
frequency/phase tracking response is that of the loop fil-
ter. The locked oscillator (6) performs much better than the
PLL because it has a loop bandwidth equal to the lock range
without sacrificing noise bandwidth, although with some
phase distortion. Some authors hold that the synchronous
oscillator and locked oscillator are variations of the PLL
in which phase detection occurs in the nonlinear region of
the oscillating device and the frequency-change character-
istic of the voltage-controlled oscillator (VCO) comes from
biasing of the oscillator. Both the PLL and the locked os-
cillator introduce phase distortion in the detected signal if
the feedback loop is nonlinear. A later circuit shown in Fig.
18 has two feedback loops and is considered nearly free of
phase distortion (5). This circuit has the amplitude/phase
response given in Fig. 17.
Phase-locked loops have been used for many years for
FM filtering and amplification. They are commonly used
with satellite communication links for audio and video
reception. A 74HC4046 phase-locked loop integrated cir-
cuit operating at 10.7 MHz (the FM IF frequency) is used
to make an FM receiver for broadcasting (7). The phase- Figure 18. Schematic diagram of a synchronous oscillating band-
locked loop extends the lower signal-to-noise limit of the pass filter.
FM receiver by several dB while simultaneously limiting
bandwidth selectivity to the lock range of the PLL. The
detected audio signal is taken from the loop filter. AM STEREO (C-QUAM)

AM stereo radio is another application of the phase-locked

oscillator at the IF frequency. AM Stereo radio depends on
two programs transmitted at the same time and frequency.
They arrive at the receiver detector circuitry through a

Figure 16. A dual conversion integrated circuit use for

high-frequency voice communications.
10 Intermediate-Frequency Amplifiers
Figure 19. An integrated circuit to detect AM Stereo (C-QUAM).
The L + R and L − R signals are in quadrature to each other.
common IF amplifier operating at 455 kHz. The normal
program heard by all listeners is the L + R program. The
stereo information (L − R) is transmitted at the same fre-
quency, but in quadrature phase to the L + R program.
Quadrature, or orthogonal transmission, is used because
the orthogonal channels do not interfere with one another.
Each program section requires a carrier coherent with its
own sideband data. The L + R program, which has a car-
rier, uses an ordinary square law detector or a synchronous
detector. This is the program heard over monaural radios.
To obtain the L − R program which is transmitted without
a carrier, a phase-locked loop is used at the IF frequency
to lock a voltage-controlled oscillator to the carrier of the L
+ R program. This carrier is then shifted 90◦ in phase and
becomes the carrier for the L + R segment. The output of
the PLL has the proper phase for the L − R detector, so that
phase shifting is not necessary. The L − R detector is a co-
herent or synchronous detector that ignores the orthogonal
L + R information. By adding, and inverting and adding,
the left and right channels are separated. Figure 19 shows
a simplified block diagram of the C-QUAM receiver.
The Motorola (Freescale) MC1032X series of integrated
circuits is designed for AM Stereo use. The MC10322 and
MC10325 have most of the components required, including
the IF amplifiers, for a complete AM Stereo receiver in two
integrated circuit packages.
Subcarriers
Subcarriers carry two or more signals on the same carrier.
They differ from the orthogonal signals used with C-QUAM
in that they are carried as separate signals superimposed
over the main carrier information, as in the video sound
carrier in Fig. 15. In Fig. 15, a frequency-modulated sub-
carrier at 4.5 MHz is carried on top of the main video sig-
nal information, which extends from 0 to 4.25 MHz. This
is an example of an AM/FM subcarrier. Nondigital satel-
lites utilize a frequency-modulated video carrier with as
many as 12 subcarriers at frequencies ranging from 4.5
MHz to 8.0 MHz. Normal FM Stereo broadcasting utilizes
a FM/AM subcarrier at 38 kHz to carry the L–R portion of
the stereo program. FM stations also frequently carry ad-
Figure 20. Neutralization or unilateralization of a transistor am-
plifier to prevent oscillation due to feedback.
ditional subcarriers at 67 and 92 kHz. These FM/FM sub-
carriers carry background music, ethnic audio programs,
and digital data.
To detect a subcarrier, the signal is first reduced to the
baseband, then a band-pass filter is used that separates
only the subcarrier frequencies. Then the subcarrier fre-
quencies are passed to a second detector which is of the
proper type for the subcarrier modulation. This is seen in
Fig. 15 where a 4.5 MHz filter is used. This is followed by
a limiter and quadrature detector as is appropriate for an
FM signal. In the case of a 67 kHz FM/FM subcarrier, the
filter is 15 kHz wide at 67 kHz. Detection is accomplished
by a discriminator, quadrature detector, or PLL.
Cellular and Cordless Telephones
Analog cellular telephones employ the circuits shown in
Figs. 14 and 16. Digital telephones utilizing GMSK also
use these circuits. Digital telephones using QAM or PSK
employ circuits similar to that used for C-QUAM with dig-
ital filtering and signal processing instead of audio filter-
ing at the baseband. The PLL for digital receivers is a more
complex circuit known as the “Costas Loop,” which is neces-
sary to restore a coherent carrier for digital data recovery.
Some cellular phones are dual mode, that is, they trans-
mit and receive analog voice or digital GMSK modulation
using circuits similar to Figs. 14 and 16.
Neutralization, Feedback, and Amplifier Stability
Earlier transistors and triode vacuum tubes had consider-
able capacitance between the output element (collector or
plate) and the input side of the device. (See Fig. 4.) Feed-
back due to this capacitance is multiplied by the gain of
the stage so that enough signal from the output was often
coupled back to the input to cause the stage to oscillate un-
intentionally, as opposed to the planned oscillation of the
locked oscillator, synchronous oscillator, or PLL. To prevent
this, feedback of an opposite phase was deliberately intro-
duced to cancel the undesired feedback. A neutralized IF
amplifier is shown in Fig. 20. Transistors and integrated
circuits made since 1985 are rarely unstable and generally
do not require neutralization unless seriously mismatched.
A solution better than neutralization is usually to improve
the matching of the components and the circuit layout.

By carefully controlling the feedback, a regenerative IF
amplifier that operates on the verge of oscillation can be
constructed. This greatly increases the Q of the tuned cir-
cuit, thus narrowing the IF bandwidth. Circuits of this type
were once used in communications receivers for commer-
cial and amateur use where they were called Q multipliers.
The maximum stable gain (MSG) achieved from a po-
tentially unstable amplifier stage without neutralization
is obtainable from S parameters and is calculated from
Eq. (13). This equation assumes that the input and output
impedances are matched and that there is little or no scat-
tering reflection at either the input or output. The stability
factor K, usually given with the S parameters, must be >1.
A failure to match the impedances can result in an unsta-
ble amplifier, but does not necessarily do so. A higher gain
is obtained, but at the risk of instability.
The most frequent cause of amplifier instability or os-
cillation is poor circuit board layout or inadequate ground-
ing and shielding, not the device parameters. The wiring,
whether printed or hand wired, forms inductive or capac-
itive coupling loops between the input and output termi-
nals of the amplifying device. This is particularly notice-
able when high gain ICs, such as the NXP SA636, are used.
These integrated circuits have IF gains of over 100 dB and
require very careful board layouts for best results. Unde-
sirable feedback greatly decreases the usable gain of the
circuit.
Software Radio
Digital radios, or radios based on digital signal processing
(DSP), offer some technical advantages over their analog
predecessors. Digital radios are used for digital modula-
tion, and also for AM and FM. One receiver simultaneously
detects both digital and analog modulation, thus they can
be used for cellular telephones in environments where mul-
tiple modulation standards are used. As a class, they belong
to the zero Hz IF frequency group.
The typical receiver consists of a conventional RF front
end and a mixer stage that converts the signal to a lower
frequency, as in the dual conversion radios discussed pre-
viously (Fig. 16). The signal at this stage is broadband, but
not broadband enough to include the image frequencies.
Then the signal is fed to an analog-to-digital (ADC) con-
verter which is sampled at several times fm . This converts
the portion of interest of the signal to the baseband (or 0
Hz) instead of a higher IF frequency. The actual filtering
to remove unwanted interfering signals then takes place
at baseband by baseband by digital filtering. Digital sig-
nal processing and decimation are covered elsewhere in
this encyclopedia. The ADC performs the same functions
as the oscillating detectors shown previously.
Noise figure, amplification, and AGC considerations of
the first IF amplifier are the same as those for a conven-
tional receiver. The ADC and the DSP filters function best
with a constant signal input level.
The term “Software Radio” has been adopted because
the tuning function is done in software by changing the
sampling frequency at the ADC. The sampling frequency is
Intermediate-Frequency Amplifiers 11
obtained from a digitally controlled frequency synthesizer
instead of tuned LC circuits.
Spread-Spectrum Radios
The spread-spectrum receiver also uses a conventional
front end with a wideband first IF stage. The same con-
ditions apply as to software radios and dual conversion re-
ceivers. The first IF stage must have the necessary band-
width to accommodate the spread bandwidth to amplify
it with minimum added noise, and to match the output
to the despreading circuitry. Spread spectrum is covered
elsewhere in this encyclopedia. Although usually associ-
ated with digital reception, spread-spectrum technology is
also used for analog audio.
Computer-Aided Design and Engineering
For IF filter design, the admittances rather than the
impedances are easiest to use, because most components
are in parallel as shown in the equivalent circuit of Fig.
4(b). Unfortunately, most available data is in the form of
S parameters which are very difficult to convert manually
to impedances or admittances. Parameters for the filters
are rarely available, so that calculated values based on
assumed input and output impedances must be used un-
less test equipment capable of measuring return losses or
standing waves is available. Then the S parameters are
measured or calculated.
Smith and Linville charts have been used by some au-
thors to design IF amplifiers, but these methods are not
totally satisfactory for IF amplifier design, because a high
Q circuit has its plot near the outer edge of the circle and
changes are difficult to observe. The network admittance
values shown in Fig. 4 would be used.
Computer programs that handle linear or analog de-
signs, such as the various “Spice” programs, are readily
available. Other programs which concentrate on filter de-
sign can simplify filter design. They have outputs which
interface with the Spice programs if desired. Most semi-
conductor manufacturers provide scattering parameters (S
parameters) or Spice input data on disk for use with these
programs. Some design software sources are listed in the
bibliography.
BIBLIOGRAPHY
1. J. M. Petit M. M. McWhorter Electronic Amplifier Circuits,
New York: McGraw–Hill, 1961.
2. W. T. Hetterscheid Transistor Bandpass Amplifiers, Philips
Technical Library, N. V. Philips, Netherlands/Philips Semicon-
ductors, 1964.
3. R. Hejhall RF Small Signal Design Using Two-Port Parame-
ters, Motorola Applications Note AN 215A.
4. F. Davis Matching Network Designs With Computer Solutions,
Motorola Applications Note AN 267.
5. V. Uzunoglu M. White Synchronous oscillators and coherent
phase locked oscillators, IEEE Trans. Circuits Syst., 36: 1989.
6. H. R. Walker Regenerative IF amplifiers improve noise band-
width, Microwaves and RF Magazine, December 1995 and
January 1996.
12 Intermediate-Frequency Amplifiers

7. R. E. Best Phase Locked Loops, 3rd ed., New York:

McGraw–Hill, 1997.
8. R. W. Goody MicroSim P-Spice for Windows. 2nd ed., Upper
Saddle River, NJ: Prentice–Hall, 1998.
9. M. E. Herniter Schematic Capture with MicroSim P-Spice. 2nd
ed., Upper Saddle River, NJ: Prentice–Hall, 1996.
10. W. Hayt, Jr. J. Kemmerly Engineering Circuit Analysis, 5th
ed., New York: McGraw–Hill, 1993.
11. W. K. Chen The Circuits and Filters Handbook, Piscataway,
NJ: IEEE Press 1995.
12. ARRL Handbook for the Radio Amateur, 65th ed., Newington,
CT: American Radio Relay League (Annual).
13. John Keown, Orcad PSpice and Circuit Analysis Upper Saddle
River, NJ: Prentice-Hall, 2001. (Includes Orcad P-Spice soft-
ware).
14. (Note: Microsim P-Spice is no longer available. See www.web-
ee.com, or Cadence to substitute Orcad P-Spice.)

Integrated Circuits and Semiconductors

AMD, One AMD Place, P.O. Box 3453; Sunnyvale, CA 94088

www.amd.com.
Analog Devices, One Technology Way, P.O. Box 9106, Norwood, MA
02062 www.analog.com
Freescale Semiconductor. www.freescale.com
Linear Technology Corporation. www.linear.com
Maxim Integrated Products, www.maxim-ic.com
Freescale, formerly Motorola, Semiconductors are now under
www.freescale.com
NXP, formerly Philips, www.NXP.com

Software

Ansoft/Compact Software, 201 McLean Blvd., Paterson, NJ 07504.

www.ansoft.com
Agilent.( Hewlett Packard ). Now combines Eagleware, Sysview
and eeSoft. www.eagleware.comEagleware Corp., 1750 Moun-
tain Glen, Stone Mtn, GA 30087Elanix Inc., 5655 Lindero
Canyon Road, Suite 721, Westlake Village, CA 91362 ( SysView
)Hewlett-Packard Company, P.O. Box 58199, Santa Clara, CA
95052 ( eeSoft ).
Cadence. 2655 Seely Ave. San Jose CA.95134. www.cadence.com
Freescale Seminconductor. www.freescale.com
Intusoft, 879 W. 19th St, Suite 100, Gardena CA. 90248-4223
www.intusoft.com.
Linear Technology Corp. www.linear.com
Mathworks. 3 Apple Hill Drive, Nagick MA. 01760
www.mathworks.com
Electronic Design Magazine ( Internet ). www.web-ee.com

HAROLD R. WALKER
Pegasus Data Systems, Inc.,
Edison, NJ

LADDER FILTERS
Ladder filters are an important class of filter structures for
implementing highly selective magnitude frequency re-
sponses. If the ladder filter structure is used to implement or
simulate resistively terminated reactive LC filters, desirable
properties, such as the inherent stability and low sensitivity
with respect to parameter changes, can be retained.
The first LC ladder filters were implemented using induc-
tors (L’s) and capacitors (C’s), operating in the continuous-
time domain and embedded between resistive terminations.
They are referred to as analog or classical LC ladder filters.
These classical LC ladder filters perform remarkably well in
practice and are capable of realizing highly selective magni-
tude frequency responses. However, they are not suitable for
microelectronic integration because inductors are usually
bulky. To overcome this limitation, inductorless microelec-
tronic filters, such as RC-active filters, switched capacitor
(SC) filters, and digital filters, have been developed. In the
early years of their development, these modern microelec-
tronic filters were unfortunately found to be inferior to LC
ladder filters for a number of reasons. In particular, they did
not possess the desired inherent stability and low-parameter
sensitivity properties and, as a result, had poor perform-
ance in terms of stability and parameter sensitivity, espe-
cially for realizing highly selective magnitude frequency re-
sponses.
Fortunately, it has been found that the superior classical
LC ladder filter structure and its corresponding filter design
methodology can be simulated by modern microelectronic fil-
ters. For example, the desired properties of passivity and loss-
lessness, as possessed by LC ladder filters, can be extended
to modern microelectronic filters in order to ensure stability
and to significantly improve the sensitivity performance of
the filter.
In this article, we are concerned with the design, synthe-
sis, and implementation of ladder filters that conform to or
simulate the ladder structure. We shall explain the general
features of the ladder structure and its inherent advantages
as well as its most successful and widely used technological
implementations such as reactive LC, RC-active, SC, and dig-
ital filters. We begin with an overview of this subject and by
placing the subject in its historical context.
OVERVIEW OF LADDER FILTERS
The Historical Development of Classical LC Ladder Filters (1,2)
Filter theory was developed at a remarkable pace in the early
years of the twentieth century. By 1915, Campbell and
Wagner had developed the first LC filter, which not coinciden-
tally was a ladder implementation. The first systematic LC
ladder filter design technique was facilitated by image param-
eter theory as introduced by Zobel in 1923. This theory was
further refined by Bode and Piloty in the 1930s. The resulting
183
J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.
classical ladder filter design technique was employed exten-
sively until the 1960s when the digital computer made alter-
native filter design techniques practical.
The image parameter method helped to develop an intu-
itive approach to the filter design problem without requiring
a computer. However, it was an approximate method which
did not make effective use of the poles and zeros that are
provided by the filter transfer function, resulting in subopti-
mal designs in terms of the order of the filter. Therefore,
much research was devoted to finding an optimal solution for
the LC ladder filter design problem, including both the ap-
proximation of the filter transfer function and the synthesis
of the LC ladder filter network.
In 1924 and 1926, a major advance occurred when Foster
and Cauer invented canonical one-port LC networks, essen-
tially solving the general one-port LC synthesis problem.
Later, in 1931, the general passive one-port synthesis prob-
lem was solved by Brune. His solution led to the fundamen-
tally important concept of the positive real function, which
became the most important mathematical vehicle for the de-
sign of LC filters and which continues to be the basis of many
alternative techniques for designing high-performance RC-ac-
tive, SC, and digital filters. In 1930, Butterworth and Cauer
introduced the maximally flat and Chebyshev approximations
of the filter transfer function, respectively, thereby solving the
approximation problem for an important class of filters. In
1937, Norton proposed a new filter design approach which
started from a prescribed insertion loss function. The general
reactance two-port synthesis problem, which was involved in
this new filter design method, was solved independently by a
number of researchers between 1938 and 1941. In particular,
Darlington and Cauer’s work led to optimal LC ladder filters
that are now widely known as elliptic filters. The insertion
loss theory of filter design was further developed by Belevitch
in 1948 using scattering matrix theory, which evolved to be-
come the most important LC filter design method. However,
because of the extensive numerical computations that this
technique involved, it only found wide applications when pow-
erful digital computers became available in the 1960s.
The Properties and Classical Implementations
of LC Ladder Filters
The classical LC filter is a two-port reactance (thus lossless)
network N that consists of ideal inductors and capacitors and
that is inserted between a voltage source E and two terminat-
ing resistors such as shown in Fig. 1(a), where the uppercase
voltages indicate steady-state voltages. If this two-port N is a
ladder structure, then it consists of alternating series and
shunt branches and is referred to as a double-resistively ter-
minated ladder filter. For LC ladder filters, the series and
shunt branches are made up of simple inductors and capaci-
tors or simple parallel and series resonant circuits. An exam-
ple of a fifth-order LC ladder filter is shown in Fig. 1(a). This
filter structure is widely used to implement the elliptic filter
transfer function, whose typical attenuation response is
shown in Fig. 1(b).
184 LADDER FILTERS
L2 L4
R1
+ such as shown in Fig. 1(a) is characterized by
E Zin V1 C2 C4 R2 V2
C1 C3 C5
N
(a)
α (ω )
α smin
α pmax
ω
(b)
Figure 1. (a) A fifth-order ladder two-port N inserted between re-
sistive terminations. (b) Attenuation response of a fifth-order elliptic
filter. The arrows indicate possible shifts of attenuation caused by
changes of filter parameter values.
The LC ladder filter structure is widely considered to be a
preferred filter structure because of its many inherently use-
ful properties. Apart from the inherent advantages of the lad-
der topology, the properties of passivity and losslessness are
of particular significance. First, the individual inductor and
capacitor components of the embedded LC ladder network are
passive and lossless, implying (according to Kirchhoff ’s volt-
age and current laws) that the complete LC ladder filter is
passive and lossless. It is very important to note that the LC
ladder network actually satisfies a more stringent passivity/
losslessness definition, namely the internal passivity/lossless-
ness. A Kirchhoff ’s network is internally passive/lossless if
and only if all the individual internal components are
passive/lossless. By proper design, the property of internal
passivity/losslessness guarantees stability and freedom from
parasitic oscillations for the filter realizations that are subject
to parasitic effects. Filters, in particular, RC-active, SC, and
digital filters, which do not simulate the internal passivity/
losslessness, are subject to (usually nonlinear) instability
problems that are caused by such parasitic effects as nonideal
phase shift, saturation, and lock-up of op-amps or quantiza-
tion effects in digital filters. It is important to note that the
simulated internal passivity/losslessness must be retained
when internal filter parameters are parasitically perturbed
from their nominal values.
In the early years, the inductors and capacitors within LC
ladder filters were implemented using coils and condensers,
respectively, and could not be manufactured to the level of
precision that is achievalble today. However, the attenuation
responses of those early LC ladder filters did not show high
sensitivity with respect to the LC component values and the
filters performed surprisingly well in practice. The theoretical
explanation for this remarkable property, which may be ex-
plained in terms of the first-order sensitivity property, has
been given by Fettweis (3) and Orchard (4) and is summa-
rized in the following.
The filter transfer function of the reactance two-port N
√
2 R1 /R2V2
S21 = (1)
E
In the terminology of scattering matrix theory, S21 is called
the input–output transmittance or the transmission coeffi-
cient. The filter attenuation response 움, corresponding to S21,
is given by
a = 10 log(1/|S21|2 ) = 10 log(Pmax/P2 ) (2)
where Pmax ⫽ 兩E兩2 /4R1 is the maximum power available from
the voltage source and P2 ⫽ 兩V2兩2 /R2 is the power delivered to
the load resistor. Because a reactance two-port is lossless and
therefore passive, we have P2 ⱕ Pmax and therefore 움 ⱖ 0. Let
x be any internal component value such as an inductance or
capacitance inside the reactance two-port. If for a particular
value of x, say x0, we have 움 ⫽ 0 at a certain frequency 웆0,
the attenuation 움(웆0, x), which is a function of x with a fixed
parameter 웆0, has a minimum at x ⫽ x0. This leads to ⭸움(웆0,
x)/⭸x ⫽ 0 for x ⫽ x0, and in general, ⭸움/⭸x ⫽ 0 for 움 ⫽ 0 and
⭸움/⭸x 앒 0 for 움 앒 0. This shows that, for a well-designed
lossless LC filter network (i.e., having an attenuation re-
sponse with the maximum number of attenuation zeros at
real frequencies in the passband etc.), the first-order sensitiv-
ity of the attenuation response with respect to any LC compo-
nent value is small everywhere in the passband; furthermore,
the closer the attenuation response is to its limiting value of
zero, the smaller the sensitivity of the attenuation to pertur-
bations of x. Furthermore, this low passband-sensitivity prop-
erty can be shown to lead to excellent noise immunity and
superior dynamic range.
In addition to the above-mentioned property of low sensi-
tivity in the passband, LC ladder filters also exhibit superior
low-sensitivity performance in the stopband, compared with
many other lossless filter structures, such as lattice struc-
tures. Although the above lossless argument establishes the
low passband-sensitivity property, it does not apply to the
stopband; in fact, the low stopband sensitivity is a result of
the unique ladder topology, as explained in the following.
Let us consider the filter network in Fig. 1(a). In the pass-
band, the transmitted power P2 closely approximates the max-
imum available power Pmax, and P2 indeed equals Pmax at the
attenuation zeros. This means that the input impedance Zin
equals R1 at those zeros. In the stopband, the attenuation
poles are attributed, in a one-to-one correspondence, to the
reactance poles in the series branches and susceptance poles
in the shunt branches. These poles disconnect the series
branches and short-circuit the shunt branches, respectively.
Therefore, the location of each attenuation pole is indepen-
dently determined by a particular series reactance or shunt
susceptance. Furthermore, because the series reactance and
the shunt susceptance are usually either a single inductor/
capacitor or a simple resonant circuit, the reactance/suscep-
tance and thus the locations of attenuation poles are easily
tuned. Furthermore, the deviation of poles with respect to
their ideal locations, due to perturbations of LC component
values, is small if the change of the component values is

small. In general, the series/shunt reactances/susceptances
are implemented using the Foster canonical forms, which
guarantee that the reactance/susceptance poles are indepen-
dent of each other and are attributed to either a single
inductor/capacitor or to a single second-order resonant cir-
cuits. Therefore, the sensitivity of the locations of attenuation
poles with respect to changes of component values is low for
LC ladder filters. This leads to the low stopband sensitivity
for LC ladder filters, because the attenuation response in the
stopband is mainly determined by the number and the loca-
tions of attenuation poles.
The low stopband sensitivity of LC ladder filters is supe-
rior to that of other types of LC filters, such as LC lattice
filters. In LC lattice filters, the attenuation poles are achieved
by signal cancellation of two or more transmission paths,
causing the above-mentioned superior stopband sensitivity
property to be lost. As a result of this relatively poor stopband
sensitivity performance, classical LC lattice filters are used in
special cases where the problem can be contained. For exam-
ple, modern digital techniques have revitalized LC lattice fil-
ter structures, because the high stopband-sensitivity may be
alleviated by means of appropriate discrete numerical optimi-
zation techniques.
Classical LC ladder filters are implemented by using dis-
crete inductors and capacitors, usually mounted on printed
circuit boards. Continued advances in materials research
have led to small and inexpensive LC components of very
high quality. Filter designers can refer to practical guides,
such as Ref. 5, in order to select the LC values and parts and
to find information on testing and manufacturing.
Modern Implementations of Ladder Filters
The invention of transistors in the 1950s has played an im-
portant role in the integrated circuit revolution and, in partic-
ular, has fueled the pervasive growth of the modern computer
and telecommunications industries. In spite of the high de-
mand for filter systems in microelectronic form and the above-
mentioned attractive properties of classical LC ladder filters,
the integration of the inductor has generally proven to be im-
practical, thereby preventing the application of classical LC
filters in microelectronic forms. This limitation of classical
LC filters led to much research on the topic of inductorless
filters.
In the 1950s, Yanagisawa and Linvill pioneered the field
of RC-active filters and showed that passive RC elements and
active controlled voltage or current sources could be combined
to realize general filter transfer functions. Sallen and Key
proposed a single-amplifier configuration for realizing second-
order transfer functions, which were very useful for imple-
menting low-order low-sensitivity filter transfer functions.
Nevertheless, these early RC-active filters proved to be overly
sensitive with respect to changes of component values for ap-
plications involving high order and highly selective transfer
functions. Moreover, they also required impractically large
spreads of component values and had a tendency to be unsta-
ble due to parasitics.
In the 1960s, the availability of high-performance micro-
electronic operational amplifiers (op-amps) allowed single op-
amp RC-active filters to be used in many applications. In the
1970s and 1980s, the cost of op-amps declined dramatically
whereas the precision RC elements, as required by this type
LADDER FILTERS 185
of RC-active filters, remained expensive, thereby lending sig-
nificant advantage to multiple-amplifier filter implementa-
tions that allowed low-cost RC elements to be used. The RC-
active filters that are based on simulating classical LC ladder
filters possess this very property and thus have been rapidly
developed.
There are two basic LC ladder simulation techniques. One
technique is based on simulating the LC ladder signal flow
graphs (SFG) and is referred to as the operational simulation
technique. The other is based on simulating the inductors in
the LC ladders and is referred to as the component simulation
technique. The inductor simulation technique is best ex-
plained by using the concept of the two-port gyrator, which
was originally proposed by Tellegen in 1948 and led to the
invention of active generalized impedance converters (GIC) by
Riordan (6) and Antoniou. An alternative inductor simulation
technique is to use the so-called frequency-dependent nega-
tive resistance (FDNR) elements, which were invented by
Bruton. These methods are discussed later in this article,
along with other modern ladder filter implementations. In
Ref. 7, a historical review of the development of RC-active
filters and a large number of references are listed.
In the 1970s, the pervasive MOS technology offered new
opportunities for making microelectronic active ladder filters
because low-power amplifiers and highly accurate capacitor
ratios could be made at very low cost and at very high density
by using the same fabrication process. These technical ad-
vances led to the development of SC filters, where capacitors
and switches were initially used to replace the resistors in
RC-active filter configurations.
In general, the voltages in SC filters are ideally constant
except at the instants of time when switches are caused to
open or close. Thus, the voltages waveforms are sampled-data
staircase waveforms that are related to each other by the
same family of linear difference equations that describe the
relationships between the variables of digital filters. A histor-
ical review of the development of SC filters is given in Refs.
8–10.
While SC filters are analog sampled data systems, digital
filters are quantized sampled data systems. The widely
spread industrial applications of digital filters have been en-
abled by the invention of CMOS VLSI technology in the
1980s. Digital filters have the advantage over analog filters
that they do not suffer from manufacturing and temperature
variations and aging effects. This advantage of digital filters
provides an opportunity to exploit the higher-order low-pass-
band-sensitivity property of classical LC filters (11) when de-
signing digital filters to simulate classical lossless LC filters,
such as wave digital filters (WDF) which were invented by
Fettweis and lossless discrete integrator/differentiator (LDI/
LDD) digital filters which were invented by Bruton. A techni-
cal review of digital filters and a large number of references
can be found in Ref. 12.
The benefits of using high-order low passband sensitivity
are considerably greater than might be expected from the
first-order sensitivity property discussed in the previous sec-
tion. To show this, let us consider the attenuation response of
the lossless filter 움(웆, x0) again, where x0 indicates any origi-
nal digital filter coefficient value. If x0 changes to x0 ⫹ ⌬x in
such a way that the losslessness is maintained, 움(웆, x0 ⫹
⌬x) ⱖ 0 still holds for the resulting attenuation response. In
this case, the size of ⌬x does not have to be small and the
186 LADDER FILTERS
attenuation minima can only shift in the same upward direc-
tion [see Fig. 1(b)]. The resulting attenuation distortion ⌬움 is
predominantly determined by the differences of these shifts
and is therefore smaller, possibly substantially smaller, than
the individual changes of the minima. Because, once the filter
coefficients are determined, the attenuation responses of
digital filters do not change due to manufacturing process,
temperature, and aging, this higher-order low passband sen-
sitivity can be used for the discrete optimization of filter co-
efficients to obtain extremely simple-valued coefficients, thus
minimizing the hardware complexity of digital filter imple-
mentations.
High-order direct-form recursive digital filters suffer from
poor sensitivity performance, limit cycle, and parasitic oscilla-
tory problems, due to underflow/overflow and high noise dis-
tortion. However, due to the internal passivity property of
classical LC filters, digital filters that are properly derived
from LC ladder filters, such as WDFs, can be made free from
parasitic oscillations even under extremely difficult looped
conditions. It is noted that in order to obtain superior perfor-
mance, passivity or losslessness must be maintained under
quantized conditions and considerable design effort may be
required to ensure that this is achieved.
The above-mentioned benefits of digital filters were often
offset by the requirement for relatively expensive analog-to-
digital and digital-to-analog converters (ADC and DAC) and
by the relatively high cost of digital filters. However, during
the 1990s, the advent of deep-submicron CMOS VLSI technol-
ogy has virtually reversed the cost equation in favor of digital
filters. Moreover, the transition of the computer and telecom-
munications industries to entirely digital systems has elimi-
nated the need for local ADCs and DACs and, in many cases,
has dictated the use of digital filters. The use of analog con-
tinuous-time filters, such as LC, RC-active, and SC filters,
may soon be restricted to ultrahigh-frequency applications
where sampling and digitization are not economical or feasi-
ble. For example, front-end analog radio-frequency (RF) fil-
ters in wireless systems are typically implemented as analog
circuits because small low-valued RF inductors may be made
at low cost. Furthermore, RF resonator-type ladder filters
such as surface acoustic wave (SAW) ladder filters find wide
applications in wireless systems. In this type of filters, the
ladder branches consist of (SAW) resonators, and the corre-
sponding filter design procedure has many similarities to the
image parameter method.
ON THE DESIGN OF PASSIVE LC LADDER FILTERS
The design of modern microelectronic ladder filters is based
on the same underlying approximation theory and ladder syn-
thesis methods that are used to design classical LC ladder
filters. The values of ladder elements for prototype low-pass
filters are tabulated in design handbooks (13,14). High-pass,
band-pass, and band-stop filters are often derived from proto-
type low-pass filters using frequency transformation tech-
niques. Alternatively, the filter approximation and synthesis
can also be performed by filter design software packages. In
this section we will briefly discuss the underlining principles
of filter approximation theory and the ladder synthesis tech-
niques that lead to optimal LC ladder filter structures. The
interested readers may consult related articles in this ency-
clopedia and Refs. 15–19 for a more comprehensive treatment
of this topic.
The General Design Procedure
There are two steps in designing a filter. The first step is to
find a transfer function having a frequency response that sat-
isfies the specified attenuation and/or phase response require-
ments. The second step is to synthesize a filter network that
realizes this transfer function. In the case of LC ladder filters,
the filter transfer function is realized using an LC ladder net-
work. In the following, we review the method of determining
the filter transfer function and the ladder synthesis technique
for LC filters.
The double-resistively terminated filter network N in Fig.
1(a) possesses transmittance S21 as defined in Eq. (1) and re-
flectance (or the reflection coefficient) S11, which is defined as
S11 = (2V1 − E)/E
For LC ladder filters, the embedded network N is lossless.
Therefore, no power is dissipated in the network N. Thus, the
two transfer functions S11 and S21 are complementary, im-
plying that
|S11 ( jω)|2 + |S21 ( jω)|2 = 1 (3)
By introducing a new variable C ⫽ S11 /S21 and by taking Eq.
(3) into account, the attenuation response given by Eq. (2) can
be rewritten as
a(ω) = 10 log(1/|S21 ( ω)|2 ) = 10 log(1 + |C( jω)|2 ) (4)
The function C( j웆) is the so-called characteristic function
having zeros and poles that correspond with those of the at-
tenuation response 움(웆). This one-to-one correspondence of
zeros and poles between the characteristic function and the
attenuation response makes the characteristic function an
important and sufficient choice for approximating the filter
transfer function. It can be shown (18) that for lossless filters
the transmittance S21 and the reflectance S11 are rational
functions in the complex frequency s (s ⫽ ␴ ⫹ j웆) and that
S21 and S11 have the common denominator polynomial g,
where g is a Hurwitz polynomial. Let
S21 = f /g (5a)
S11 = h/g (5b)
The characteristic function C becomes
C = h/ f (6)
which is also a rational function. It can be shown from Eqs.
(3) and (5) that the following fundamentally important rela-
tion holds between f, h, and g for the entire s domain:
f (s) f (−s) + h(s)h(−s) = g(s)g(−s) (7)
Furthermore, for LC filters, f(s) is either an even or an odd
function of s because of the reciprocity property of embedded
LC two-ports. Now, the transfer function approximation prob-
lem can be formulated so as to find the rational functions
h( j웆), f( j웆) and thereby 兩C( j웆)兩2 ⫽ h( j웆)h(⫺j웆)/f( j웆)f(⫺j웆)
 LADDER FILTERS 187

such that the attenuation response 움(웆), as defined by Eq. also be written as continued fractions
(4), satisfies the specified attenuation requirements. The fact
that g(s) is a Hurwitz polynomial, having its zeros in the left 1
Z(s) = L1 s + (8a)
half of the s plane, allows itself to be obtained by solving the 1
equation f(s)f(⫺s) ⫹ h(s)h(⫺s) ⫽ 0. Subsequently, the func- C2 s +
1
tions S21 and S11 are fully determined. Note that we have L3 s +
1
omitted discussion of phase responses because the phase re- C4 s +
sponse requirements for a ladder filter are usually satisfied by ..
.
cascading an equalizing all-pass filter. Nevertheless, special
ladder filters may be designed to satisfy the phase response or
requirements, such as the Thomson filter that is discussed in
the following. 1 1
Z(s) = 
+ (8b)
The transfer function approximation problem, which is the C1 s 1 1
determination of the characteristic function C, was solved for +
L2 s 1 1
low-pass filters by Butterworth, Cauer, Thomson, and others 
+
C3 s 1 1
in the early years of filter design. In the next section, we dis-

+
cuss design examples for low-pass prototype filters where it is L4 s ..
.
understood that simple frequency transformations are used to
obtain high-pass, band-pass, and band-stop filters from low- leading directly to the first and second Cauer canonical forms
pass prototype filters. shown in Fig. 2(b).
The synthesis of the double-resistively terminated two-port The Cauer canonical forms are reactance one-ports having
N in Fig. 1(a) is facilitated by the LC one-port synthesis tech- a ladder structure. The continued fraction expansion tech-
niques as developed by Foster and Cauer. A reactance func- nique is especially useful for synthesizing resistively termi-
tion, which is obtained as the input immitance of an LC nated two-port ladder network. It can be shown that the re-
one-port, can always be realized in the Foster and Cauer ca- flectance S11 can be written as
nonical forms. The first and second Foster canonical forms
are based on the partial fraction expansion of the reactance S11 = (Zin − R1 )/(Zin + R1 ) (9a)
function, and the first and second Cauer canonical forms are
based on the continued fraction expansion. It can be shown so that Zin can be written as
that a reactance function can be written in the following par-
tial fraction form as the impedance function Zin = R1 (1 + S11 )/(1 − S11 ) (9b)

n
However, Zin is an impedance function and thus a rational
Z(s) = B∞ s + B0 /s + 2Bi s/(s2 + ωi2 )
positive real function which, according to Darlington’s theory,
i=1
can always be synthesized as a lossless two-port network ter-
minated by a resistive load.
or admittance function
In general, the resulting two-port network involves the so-


n called Brune section, which is a second-order two-port net-
Y(s) = D∞ s + D0 /s + 2Di s/(s2 + ωi2 ) work containing coupled inductors or ideal transformers, and
i=1 thus strictly does not have the LC ladder structure according
to our definition. However, in most cases, an LC ladder struc-
leading directly to the first and second Foster canonical forms ture can be found for the input impedance Zin that results
as shown in Fig. 2(a). Similarly, the reactance function can from the reflectance S11 of a practical low-pass filter. This is
especially true if the resulting two-port is allowed to be a non-
canonical network. In fact, the continued fraction expansion
technique, illustrated by Eq. (8), can be applied to Zin in order
to realize an LC ladder two-port that is terminated by a
resistor.
The continued fraction expansion technique is also re-
ferred to as the pole removal technique because it removes
(a)
the attenuation poles of the filter one by one during the
course of the fractional expansion. For low-pass filters, having
multiple attenuation poles at infinity, each step in fractional
expansion removes a full attenuation pole at infinity, re-
sulting in a canonical implementation. For low-pass filters
that have attenuation poles located at finite frequencies, the
(b) removal of a finite frequency pole has to be accompanied by a
Figure 2. (a) The first Foster canonical form. (b) The first Cauer partial removal of an infinity pole, in order to avoid the Brune
canonical form. The second canonical form is the dual network to the section and to obtain a ladder structure. Because of this par-
first canonical form. The Foster canonical forms implement each tial pole removal, the resulting LC ladder two-port is a nonca-
reactance/susceptance pole by a separate second-order resonant cir- nonical network. We will consider examples for LC ladder
cuit. The Cauer canonical forms have a ladder structure. synthesis in the following section.
188 LADDER FILTERS

Low-Pass Prototype Filters the passband, the source terminating resistor, and the load
terminating resistor (where possible) are normalized to unity.
The most widely used low-pass prototype filters are the But-
The LC element formula for the nth-order minimum inductor
terworth, (inverse) Chebyshev, elliptic, and Thomson filters.
Butterworth ladder filter is given by
Each of these filters has particular characteristics that may
be preferred for a given application. We shall briefly discuss 
each type of these filters. Cm (m is odd)
= 2 1/n sin γ2m−1 and m = 1, 2, . . ., n
Lm (m is even)
Butterworth Filters. The nth order Butterworth low-pass
filter has the following characteristic function:
Chebyshev Filters. The characteristic function of the Cheb-
C(s) = (s/ωp )n yshev filter is a Chebyshev polynomial, which can be written
in a compact form as follows:
where 웆p is the passband edge frequency and ⑀ is the pass-

band ripple factor related to the maximum attenuation in the cos(n cos−1 ω/ωp ) for |ω/ωp | ≤ 1
passband by 움pmax ⫽ 10 log(1 ⫹ ⑀2). The first n ⫺ 1 derivatives C(ω/ωp ) = Tn (ω/ωp ) =  −1
cosh(n cosh ω/ωp ) for |ω/ωp | ≥ 1
of the characteristic function are zero at the origin. For this
reason, the attenuation response has the special characteris-
tic that it is maximally flat at the frequency origin. The But- where Tn(웆) is the nth-order Chebyshev polynomial. There-
terworth filter has all of its attenuation zeros and poles at the fore, the Chebyshev filter is an all-pole low-pass filter, having
frequencies zero or infinity. This leads to a less steep transi- all attenuation poles at infinity. In the passband, however,
tion region from the passband to the stopband and results in the Chebyshev filter has attenuation zeros at the finite fre-
a high filter order that is required to satisfy the attenuation quencies and the attenuation function has an equiripple form.
requirements in both the passband and stopband. The polyno- Because of the optimally distributed attenuation zeros in the
mial characteristic function of the Butterworth filter leads to passband, the Chebyshev filter has a steeper transition region
a transfer function having a constant numerator. This type of than the Butterworth filter so that the Chebyshev filter can
filters is called all-pole low-pass filters. For the Butterworth satisfy the same attenuation requirements with a much lower
filter, Eq. (7) can be solved analytically. Thus, S21 and S11 can filter order than the Butterworth filter. For example, an
be written in analytical forms. In particular, eighth-order Chebyshev filter may satisfy the practical atten-
uation requirements that would require a 20th-order Butter-
( 1/n s/ωp )n worth filter. However, it is also noted that because of the max-
S11 = R1


n imum flat property, Butterworth filters have a much
ai ( 1/n s/ωp )i smoother phase/delay response than Chebyshev filters, lead-
i=0
ing to lower time-domain distortion of passband signals.
The LC ladder synthesis of Chebyshev filters can be
where the coefficients a0 ⫽ 1 and ai (i ⫽ 1, 2, . . ., n) are
achieved in the same way as for Butterworth filters and the
given by
synthesized two-ports also have the same ladder structures
 as illustrated in Fig. 3. The explicit formulas for LC ladder
i
cos γk−1
ai = with γk = kπ/2n component values of an nth-order Chebyshev filter are given
κ =1
sin γk with help of two intermediate constants h and ␩ (15) as fol-
lows:
According to Eq. (9b), the input impedance function Zin can be
readily determined and then expanded into a continued frac-   1/2 1/n  
tion at infinity according to the first Cauer canonical form 1 1 1
h= + 1+ 2 and η = h −
(8a). The resulting LC ladder filter is illustrated in Fig. 3,   h
where the minimum inductor structure is selected. It is noted 4 sin γ1
that the minimum capacitor structure is available as the dual C1 = with γm = mπ/2n
ηR1
network to the minimum inductor structure. The LC values
16 sin γ4m−3 sin γ4m−1
of the resulting ladder filter can be determined either ac- C2m−1 L2m = , m = 1, 2, . . ., n/2
cording to the continued fraction expansion of Eq. (8a) or by η2 + 4 sin2 γ4m−2
using explicit formulas, which are available for all-pole filters 16 sin γ4m−1 sin γ4m+1
(15). Such formulas are especially simple for frequency and C2m+1 L2m = , m = 1, 2, . . ., n/2
η2 + 4 sin2 γ4m
impedance normalized filters, for which the edge frequency of
4 sin γ1
Cn = for odd n
ηR2
4R2 sin γ1
R1 L2 Ln–2 Ln Ln = for even n
η
+
E C1 C3 Cn–3 Cn–1 R2
Inverse Chebyshev Filters. The inverse Chebyshev filters
Figure 3. Minimum inductor ladder structure for all-pole filters. The have the reverse passband and stopband behavior with re-
number of inductors is equal to (when Ln ⬆ 0) or less than (when spect to the Chebyshev filters. The passband of the inverse
Ln ⫽ 0 and Cn⫺1 ⬆ 0) the number of capacitors. Chebyshev filter is maximum flat at the origin and the stop-

band has the equiripple form. The characteristic function for
inverse Chebyshev filters can be written as
C(s) = 1/Tn (ωp /ω)
where Tn is the nth Chebyshev polynomial. For the LC ladder
synthesis of the inverse Chebyshev filter, which has finite-
frequency attenuation poles, the continued fraction expansion
technique can be generalized by allowing the removal of sim-
ple resonant circuit branches that have resonant frequencies
in one-to-one correspondence with the finite frequencies of at-
tenuation poles. However, this poses a potential problem such
that, during the generalized continued fraction expansion, the
removal of a finite frequency pole requires shifting a zero of
the remaining input impedance/admittance to the same fre-
quency as the attenuation pole that is to be removed. This so-
called zero-shifting process can introduce a negative LC ele-
ment value that can be absorbed into a Brune section after
the pole removal. Fortunately, there is a way around this
problem of physically unrealizable negative LC elements if
the filter has an attenuation pole at infinity, such as the odd-
order inverse Chebyshev filter. In this case, the zero-shifting
can be achieved by the so-called partial removal of the infinity
attenuation pole. The resulting LC ladder two-port is no
longer a canonical network and no longer contains Brune sec-
tions.
A fifth-order inverse Chebyshev filter can have an imple-
mentation such as that shown in Fig. 1(a), where the two left-
hand shunt capacitors only partially remove the attenuation
pole at infinity and the right-hand shunt capacitor finally re-
moves this pole completely. For the even-order inverse Cheb-
yshev filters, which do not have attenuation poles at infinity,
a frequency transformation, which will be discussed in the
next section, should be performed before the synthesis process
in order to introduce an attenuation pole at infinity.
Because LC ladder implementations of inverse Chebyshev
filters are not canonical networks, they require a larger num-
ber of LC elements than do Chebyshev filters of the same or-
der. Furthermore, because the transition region of both types
of filters are similar with regard to their transition-band
steepness, the Chebyshev filter is usually preferred to its in-
verse version. However, the inverse Chebyshev filter has a
better phase/delay response due to its maximally flat pass-
band. Therefore, it may be preferred if a smooth delay re-
sponse is required.
Elliptic Filters. The elliptic filter has equiripple attenuation
in both the passband and stopband. It provides the lowest
filter order satisfying a given attenuation requirement. For
comparison, a sixth-order elliptic filter can satisfy the same
attenuation requirement that would require an eighth-order
Chebyshev filter. The characteristic function for the nth-order
elliptic filter is a Chebyshev rational function given by
  m s2 + ω 2

 0,2i
s
 2 + ω2
for n = 2m + 1
s
C(s) = d  i=0
m s2 + ω 2
∞,2i




0,2i−1
for n = 2m
i=0
s2 + ω∞,2i−1
2
where d is a scaling constant such that the passband ripple
factor is once again ⑀ and the attenuation zeros 웆0, j and poles
LADDER FILTERS 189
웆앝, j are calculated by means of the elliptic functions, which
are discussed in many filter design books (19). The attenua-
tion zeros and poles of an elliptic characteristic function are
located symmetrically around a frequency 웆t in the transition
band such that 웆0, j웆앝, j ⫽ 웆t2. This frequency 웆t is a measure of
the selectivity of the filter. The synthesis process for elliptic
filters is very similar to that for inverse Chebyshev filters. In
particular, the LC ladder network in Fig. 1(a) can be used to
implement a fifth-order elliptic filter.
Thomson Filters. All of the above filter types are designed
to meet specified attenuation requirements. The Thomson fil-
ter, on the other hand, achieves maximally flat group delay
by maintaining the first n derivatives of the group delay to be
zero at the frequency origin. The transfer function of Thom-
son filters is an all-pole function with the Bessel polynomial
as the denominator:
Bn (0)
S21 (s) =
Bn (s)
where

n
(2n − 1)!si
Bn (s) =
i=0
2n−i i!(n − i)!
The normalized group delay of the Thomson filter approxi-
mates unity in the neighborhood of the frequency origin. The
higher the filter order n, the wider the frequency band over
which a flat delay response is achieved. The time-domain re-
sponses of the Thomson filter are very smooth. For example,
the step response has no overshoot. The synthesis of Thomson
filters is similar to that for other all-pole filters.
It is noted that all the prototype filters discussed so far
allow a closed-form solution for the filter approximation prob-
lem. The filter approximation of more general filter types such
as filters with nonequiripple attenuation/phase behavior may
be solved in a satisfactory manner by using computer-aided
numerical methods.
Frequency Transformations
In the previous sections, we discussed various types of low-
pass prototype filters. The approximation solutions and the
filter structures of these prototype filters can also be used to
obtain other filter types by means of appropriate frequency
transformations.
Frequency Scaling. Low-pass prototype designs are usually
obtained for normalized case so that the passband edge fre-
quency is normalized to unity. This is especially the case
when the explicit design formulas are used. To denormalize
the passband edge to a specified value 웆p, the following fre-
quency transformation can be used:
p = s/ωp
where p is the complex frequency before transformation. The
filter structure does not change after the denormalization, but
the LC element values of a given filter structure are scaled ac-
cordingly.
190 LADDER FILTERS
Low-Pass to High-Pass Transformation. A high-pass filter can
be obtained the following frequency transformation:
p = ωp /s
which results in replacing each inductor with a capacitor and
vice versa.
Low-Pass to Bandpass Transformation. The specification of a
bandpass filter is given by the two passband edges 웆pl and
웆ph (웆pl ⬍ 웆ph) and the two stopband edges 웆sl and 웆sh (웆sl ⬍
웆sh). The bandpass characteristic can be thought of as a com-
bination of a low-pass and a high-pass characteristic such as
s ωpl ωph /(ωph − ωpl )
p= + (10)
(ωph − ωpl ) s
The stopband edges 웆sl and 웆sh can be calculated using Eq.
(10) by setting p equal to the low-pass prototype stopband
edge. Because Eq. (10) is a second-order equation in s, it de-
termines both stopband edges 웆sl and 웆sh. Therefore, these
stopband edges are not independent of each other but related
by 웆pl웆ph ⫽ 웆sl웆sh, resulting in a frequency-domain symmetri-
cal bandpass filter. According to Eq. (10), a bandpass filter
structure is obtained from its low-pass prototype by replacing
each inductor with a series resonant circuit and each capaci-
tor with a parallel resonant circuit.
A minor problem can arise from the direct application of
Eq. (10) to a parallel or series resonant circuit, such as the
parallel resonant circuit in Fig. 1(a), when transforming an
inverse Chebyshev or an Elliptic low-pass filter into the corre-
sponding band-pass filter. The transformed resonant circuit,
which is a combination of a parallel and a series resonant
circuits, does not directly relate to the anticipated attenuation
poles, resulting in a less favorable stopband sensitivity. This
problem can be resolved by using network transformations
such that a parallel resonant circuit transforms into two par-
allel resonant circuits in series while a series resonant circuit
transforms into two series resonant circuits in parallel.
Low-Pass to Band-stop Transformation. The band-stop filter
can be obtained from a bandpass filter by interchanging its
passband with its stopband frequency location. Therefore, the
band-stop characteristic can be obtained by performing a
bandpass transformation on a high-pass filter instead of a
low-pass filter, resulting in the low-pass to band-stop trans-
formation
−1
s ωpl ωph/(ωph − ωpl )
p= + amps) are not discussed. Reference material on these topics
(ωph − ωpl ) s
Because of the similarity between the bandpass and band-
stop transformations, the properties discussed above for the
band-pass transformation can be easily rewritten for the
band-stop transformation.
Other Frequency Transformations. The frequency transfor-
mations discussed so far are reactance transformations; that
is, they transform a reactance into another reactance.
Whereas reactance transformations are very useful, nonre-
actance transformations are often required to transform a
characteristic function that is not realizable as an LC ladder
two-port into a realizable one.
The even-order elliptic filter has the property that its at-
tenuation has a nonzero value at the origin and a finite value
at infinity. However, a practical LC ladder implementation
requires an attenuation pole at infinity. Furthermore, it is
often desirable to have the zero attenuation at the dc level,
which also allows for a balanced load resistance equal to the
source resistance. In order to achieve these requirements, the
following transformation can be applied to the characteristic
function before the synthesis process:
ω∞
2
− ωp2 p2 + ω02
s2 = ωp2 ·
ωp2 − ω02 p2 + ω∞
2
where 웆0, 웆p, and 웆앝 are respective frequencies for the first
passband attenuation zero, the passband edge, and the last
finite-frequency attenuation pole. This transformation trans-
forms the passband attenuation zero at 웆0 to the origin, the
stopband attenuation pole at 웆앝 to infinity, while retaining
the passband edge at 웆p. In general, the transformed filter
has a poorer performance (especially in the transition region)
than the original elliptic filter, because the latter is the opti-
mum solution. However, the transformed filter still has a bet-
ter performance than an original elliptic filter of lower order.
The even-order Chebyshev filters do not have an attenua-
tion zero at the origin while having attenuation poles at in-
finity. The above transformation can be modified to just move
the attenuation zero at 웆0 to the origin:
ωp2
s2 = ( p2 + ω02 )
ωp2 − ω02
Similarly, for even-order inverse Chebyshev filters, the atten-
uation pole at 웆앝 can be moved to infinity by the following
transformation:
p2
s2 = (ω∞
2
− ωp2 )
p2 + ω∞
2
ACTIVE INTEGRATED CIRCUIT IMPLEMENTATIONS
OF LC LADDER FILTERS
In the following sections, we discuss various techniques for
the design of RC-active filters that are derived from LC lad-
der filters. However, the design details and parasitic effects
(primarily due to the finite gain and bandwidth of the op-
can be found in the related articles in this encyclopedia and
in Refs. 20–24.
RC-Active Ladder Filters Based on Simulating Inductors
The RC-active filters in this category can be readily obtained
by replacing inductors with selected active circuits. Three ba-
sic types of active circuits are employed and discussed in the
following.
Gyrators. A classical approach to the replacement of induc-
tors with active circuits is to use a two-port gyrator termi-
 LADDER FILTERS 191

or
R
Z2 Z4
Zin2 = Z (11b)
L L C Z1 Z3 ld1

Gyrator Therefore, choosing

Z 1 = R1 , Z 2 = R2 , Z 3 = R3 , Z4 = 1/sC4 , and Zld1 = R5

(a) (12)

L
R1 R2 leads to a simulated grounded inductance at port 1 with L ⫽
R1R3C4R5 /R2.
According to Eq. (11a), Z2 could be chosen as a capacitor
C instead of Z4. However, for practical reasons the choice in Eq.
(12) has a better performance at high frequencies.
In general, we can define a conversion factor K(s) ⫽
Z1(s)Z3(s)/Z2(s)Z4(s), where Zi(s) can be any impedance func-
(b) tions. Thus, the GIC can perform more general impedance
conversion than the inductance simulation. In particular, if
Figure 4. (a) Grounded-inductor simulation as may be used in high-
port 1 is terminated in a capacitor Cld1, the input impedance
pass filters. (b) Floating-inductor simulation as may be used in low-
at port 2 is given by
pass filters. Both inductor simulations use a gyrator, which is realized
by an active circuit.
R2
Zin2 =
R1 R3C4Cld1 s2

nated at one end with a capacitor C as shown in Fig. 4(a). In which is a so-called frequency-dependent negative resistance
general, the relationship between the input impedance at (FDNR). Applications of FDNRs are discussed in the next
port 1, Zin, and the terminating impedance, Zld, at port 2 of a subsection.
gyrator is given by The GIC is used in a very similar way to that of a gyrator.
In particular, the gyrator simulating a grounded inductor, as
Zin = R2 /Zld shown in Fig. 4(a), can be replaced with a GIC given by Eq.
(12). The GICs can also be used to simulate floating inductors
where R is the gyration resistance inherent to the gyrator as shown in Fig. 5(b), which was first proposed by Gorski-
circuit. Therefore, the inductance seen from port 1 is given by Popiel. It is noted that, unlike the gyrator, the GICs with the
L ⫽ R2C.
There are two types of topological situations involving the
use of inductors, namely grounded inductors and floating in-
ductors, as shown in Figs. 4(a) and 4(b), respectively. To sim- – +
K(s)
ulate a grounded inductor, a one-port grounded gyrator may
be employed; and to simulate a floating inductor, a two-port Z1 Z2
grounded gyrator is needed. Note that because the active gy-
rator circuits involve complicated active circuitry, minimum Z3 Z4
inductor implementations should be chosen in order to mini- K(s) = Z1 Z3 / Z2 Z4 – +
mize the number of required gyrators.
In general, passive implementations of gyrators are not
available for many applications. In the RC-active filter appli-
cation, small-signal active implementations of gyrators have
been specifically designed for converting a capacitor to an in- 1 2
ductor (25–27). When the gyrator is used as an impedance
converter, it may be considered as a special case of the gener- (a)
alized impedance converter (GIC), which is discussed in the
L k⋅s R = L/k k⋅s
following.

Generalized Impedance Converters. The GIC is a two-port

circuit, usually employing two op-amps as shown in Fig. 5(a),
where the impedances Zi are usually either a resistor or a
capacitor. The impedance relations between the input and (b)
terminating impedances of a GIC are given by
Figure 5. (a) Active implementation of GIC and its corresponding
symbol. K(s) is the conversion factor. (b) Floating-inductor simulation
Z1 Z3
Zin1 = Z (11a) using GIC. This simulation uses a resistor connecting two GICs. The
Z2 Z4 ld2 required capacitors are hidden in the GICs.
192 LADDER FILTERS

Ld1 and a capacitor according to

L1 L3 L5
R1/s L2 L4
+
E R2/s Ld2
FDNR FDNR
1/s2C2 1/s2C4
Figure 6. A fifth-order RC-active filter using FDNRs. The dashed
resistors Ld1 and Ld2 are the add-on discharging resistors.
conversion factor k ⭈ s (k is a constant) convert a floating in-
ductor into a floating resistor whereas the required capacitors
are embedded in the GICs.
Frequency-Dependent Negative Resistors. All of the above
RC-active filters use minimum inductor implementations.
The minimum capacitor implementations can also be em-
ployed in an effective way if the concept of the FDNR is used.
The dimensionless filter transfer function of any LCR net-
work is unaltered if each branch is scaled by a uniform func-
tion. Thus, impedance scaling all branches by 1/s converts all
inductors to resistors, all resistors to capacitors, and all ca-
pacitors to FDNR elements. An example of a RC-active filter
using FDNRs is given in Fig. 6, where the dual network to
the fifth-order filter in Fig. 1(a) is 1/s impedance-scaled. The
resulting FDNRs can be implemented using GICs. It is noted
that the filter network in Fig. 6 is no longer resistively termi-
nated, which may cause a practical dc bias problem if the
source and/or load are not resistively coupled to ground. This
termination problem can be resolved by inserting two unity-
gain amplifiers between the source and the load, and the bias
current problem can be compensated for by connecting two
discharging resistors across the capacitors, as shown in Fig.
6. The values of these resistors are suggested to be chosen
such that the filter attenuation at the dc level remains equal
to unity, that is,
1
Vout = I
sC in
so that all the reactive components are represented as inte-
grators within the SFG. The terminating resistors are repre-
sented by constant-valued analog multipliers within the SFG.
The physical interconnections of the LCR elements constrain
the voltage and current signals to obey Kirchhoff ’s laws and
are represented in the SFG by appropriate combinations of
analog inverters and adders. An example of an SFG for the
third-order low-pass filter in Fig. 3 (where n ⫽ 3) is given in
Fig. 7(a), which is often referred to as the leapfrog structure.
It is noted that all inductors are simulated by noninverting
integrators, and all capacitors are by inverting integrators so
that all signals entering an adder have the same positive
sign. Furthermore, because all summations are performed im-
mediately prior to integration, summation can be easily
achieved in the RC-active circuit by current-summing at the
virtual ground input terminals of the integrator’s op-amps.
Thus, no dedicated summing devices are required. In Fig.
7(b), the complete circuit corresponding to the SFG in Fig.
7(a) is given for the selected type of integrator implementa-
tions, where the circuit parameters can be determined by
E R/R1
R/R1 R/sL2 R/R2
–1/sC1R –1/sC3 R
V2
(a)
r1

Ld2 = Ld1 + L1 + L2 e
r2 r5

and that the insertion of Ld1 and Ld2 introduces the least dis-
tortion of the filter frequency response. r
– +

RC-Active Filters Based on Simulating Ladder SFGs r1 c1 + – c3 + – r6

r
The design and implementation of RC-active filters based on
c2
simulating the voltage–current signal flow graphs (SFGs) of
LC ladder prototype structures was proposed by Girling and – +
Good. An SFG can be derived for any given LC ladder filter,
where for the purpose of implementing RC-active filters, the r3 r4 V2
SFG should be arranged in such a way that it consists only
of inverting/noninverting integrators, analog multipliers, and (b)
adders. An inductor is represented in the SFG according to
Figure 7. (a) A third-order leapfrog SFG scaled by a constant R. (b)
The corresponding complete RC-active circuit, where c1r1 ⫽ C1R1,
1 c1r2c2r3 ⫽ C1L2, c2r5c3r4 ⫽ L2C3, c3r6 ⫽ C3R2. No dedicated summing
Iout = V
sL in devices are needed.

comparing the loop gains between the circuit representations
in Figs. 7(a) and 7(b). Note that other types of integrator im-
plementations may be chosen, depending on the frequency
range within which the circuit is intended to operate.
The SFG simulation method is very straightforward and
easy to use, especially when designing band-pass filters. How-
ever, it is noted that, when drawing the SFGs for LC ladder
network that contain a 앟 circuit of capacitors or a T circuit of
inductors, difficulties arise because two adjacent SFG blocks
have ports with the same orientation facing or leaving each
other. This problem can be solved perfectly by using network
transformations involving Brune sections in the same way as
it has been done for LDI/LDD digital filters (28). By now, it
is evident that the Brune section is a very useful building
block in RC-active and digital filter implementations, al-
though it is, strictly speaking, not a ladder component.
DISCRETE-TIME SC AND DIGITAL IMPLEMENTATIONS
OF LC LADDER FILTERS
Both the SC filter and digital filter are sampled data (dis-
crete-time) systems. The frequency response of a discrete-
time system is adequately described in the z domain with
z ⫽ esT, where s is the complex frequency and T is the sam-
pling period. The frequency-domain design methods for SC
filters and for digital filters have many similarities and often
have the same z-domain transfer functions, in spite of the fact
that SC filters are implemented as analog circuits whereas
digital filters employ the digital arithmetic operations of addi-
tion, multiplication, and delay and are implemented as com-
puter programs or by dedicated hardware.
The frequency-domain design of discrete-time SC and digi-
tal filters can be performed directly in the z domain. However,
high-performance discrete-time filters may be designed by
simulating continuous-time LC ladder filters as discrete-time
filters. This is achieved in a way such that all of the above-
mentioned favorable stability and sensitivity properties of
LC filters are preserved. The transfer functions of the contin-
uous-time LC ladder filter and its discrete-time counterparts
are related by the bilinear transformation
s = (z − 1)/(z + 1)
In the following, we briefly discuss methods for converting
continuous-time LC ladder filters into their discrete-time
counterparts. The design details for SC and digital filter cir-
cuit components and the treatment of parasitic and other
nonideal effects are not considered here. Reference material
on these topics can be found in the related articles in this
encyclopedia and in Refs. 11 and 28–32.
Switched Capacitor Filters
SC filters that are based on LC ladder filters can be derived
from RC-active filters that are themselves derived from LC
ladder filters, preferably using the SFG simulation technique.
In fact, the resistors in RC-active ladder filters can be simu-
lated by switched capacitors, leading directly to the SC filter.
There is a variety of different SC circuits for simulating the
resistors in RC-active ladder filters. Different SC resistor cir-
cuits, which are used to replace resistors in RC-active filters,
may result in different frequency-domain relationships be-
LADDER FILTERS 193
tween the transfer functions of the continuous-time LC ladder
filter and its discrete-time SC counterpart. An example of SC
resistor circuits is given in Fig. 8(a), which leads to the de-
sired frequency-domain relationship given by the bilinear
transformation.
In many SC filters, the ideal circuit capacitances are not
significantly larger than the parasitic capacitances. In fact,
the latter is around 20% of the former. Therefore, it is ex-
tremely critical to only use those SC circuits that are not sen-
sitive to parasitic capacitances. An example of a so-called
stray-insensitive SC resistor circuits is given in Fig. 8(b). This
circuit yields a different frequency transformation than the
bilinear transformation. In order to achieve the desired bilin-
ear transformation using simple SC ladder circuits, a so-
called predistortion technique may be used that adds a posi-
tive capacitance to one circuit component and subtracts an
equal-valued negative capacitance from another circuit com-
ponent, along with an impedance-scaling technique (30). It is
noted that a similar technique is also used for LDI/LDD digi-
tal filters.
Another alternative approach for designing SC filters is to
directly simulate each inductor and each terminating resistor
in the LC ladder filter. In this method, the interconnections
of capacitors and simulated inductors/resistors are achieved
by the so-called voltage inverter switchs (VIS), which contain
active op-amps. This component simulation method guaran-
tees the bilinear transformation between transfer functions of
the continuous-time LC ladder filter and its discrete-time SC
counterpart, which can be designed insensitive to parasitic
capacitances. Nevertheless, considerable design effort and/or
complicated switching signals may be required to achieve the
low-sensitivity property.
Digital Ladder Filters
In a way that is similar to the SC simulation of LC ladder
filters, there are two alternative approaches for the digital
simulation of LC ladder filters, namely the simulation of each
LCR component and the simulation of the SFG represen-
tation.
The component simulation method is achieved using wave
digital filters (WDF) (11), where the circuit components of the
LC ladder filter, such as inductors, capacitors and resistors,
are directly simulated by corresponding digital domain com-
ponents, such as delay registers and inverters. The parallel
and serial interconnections of these digital components are
facilitated by so-called parallel and serial adapters that con-
tain adders and multipliers. A distinguishable advantage of
ph0 ph1 ph0 ph1 (ph0)
C C
ph1 ph0 (ph1)
ph0 ph1
(a) (b)
Figure 8. (a) Bilinear SC resistor circuit with two switching phases.
(b) Stray-insensitive SC resistor circuit which can be used to form
inverting or noninverting (switching scheme in parentheses) inte-
grators.
194 LADDER FILTERS
WDFs is that internal passivity is maintained under both in-
finite and finite wordlength conditions. This leads to the sup-
pression of parasitic oscillations that are caused by overflow
and underflow operations.
The SFG simulation of LC ladder filters employs lossless
digital integrators and/or lossless digital differentiators
(LDIs/LDDs) to replace the corresponding integration/differ-
entiation operations in the continuous-time ladder SFG
(28,31,32), where the continuous-time SFG may first be pre-
distorted and impedance scaled in such a way that delay-free
loops are avoided and all inductors and capacitors are individ-
ually and directly realized as discrete-time LDI/LDD ele-
ments. Each LDI/LDD element contains a delay register, a
multiplier, and an adder. This SFG simulation approach does
not require any special interconnection components and re-
tains the one-to-one correspondence between the LC ladder
filter parameters and its LDI/LDD digital counterparts. A
distinguishing advantage of LDI/LDD ladder filters is that
all of the state variables of inductor-simulating or capacitor-
simulating LDI/LDD elements are independent of each other,
thereby allowing concurrent implementation in parallel arith-
metic schemes and flexible scheduling in bit-serial arithmetic
schemes. It is noted that the very useful Brune sections can
be perfectly implemented using the LDI/LDD method.
BIBLIOGRAPHY
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337–382, 1960.
4. H. J. Orchard, Inductorless filters, Electron. Lett., 2, 224–225,
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5. E. Christian, LC Filters: Design, Testing, and Manufacturing, New
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414–417, April 1981.
9. G. C. Temes, MOS switched-capacitor filters—History and the
state of the art, Proc. Eur. Conf. Circuits Theory Design, Den
Haag, pp. 176–185, Aug. 1981.
10. W. K. Jenkins, Observations on the evolution of switched capaci-
tor circuits, IEEE Circuits Syst. Magazine, Centennial Issue, 22–
33, 1983.
11. A. Fettweis, Wave digital filters: Theory and practice, Proc. IEEE,
74: 270–327, 1986.
12. A. Fettweis, Digital circuits and systems, IEEE Trans. Circuits
Syst., CAS-31, pp. 31–48, 1984.
13. R. Saal and W. Entenmann, Handbook of Filter Design, Berlin:
AEG Telefunken, 1979.
14. A. Zverev, Handbook of Filter Synthesis, New York: Wiley, 1967.
15. A. S. Sedra and P. O. Brackett, Filter Theory and Design: Active
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17. G. C. Temes and J. W. LaPatra, Circuit Synthesis and Design,
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18. V. Belevitch, Classical Network Theory, San Francisco: Holden-
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19. R. W. Daniels, Approximation Methods for Electronic Filter De-
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20. G. C. Temes and S. K. Mitra (eds.), Modern Filter Theory and
Design, New York: Wiley, 1973.
21. G. S. Moschytz, Inductorless filters: A survey. I. Electromechani-
cal filters. II. Linear active and digital filters, IEEE Spectrum, 7
(8): 30–36, 1970; 7 (9): 63–75, 1970.
22. S. K. Mitra (ed.), Active Inductorless Filters, New York: IEEE
Press, 1971.
23. L. P. Huelsman (ed.), RC-Active Filters: Theory and Application,
Stroudsburg: Dowden, Hutchinson and Ross, 1976.
24. W. E. Heinlein and W. H. Holmes, Active Filters for Integrated
Circuits, London: Prentice-Hall, 1974.
25. B. A. Shenoi, Practical realization of a gyrator circuit and RC-
gyrator filters, IEEE Trans. Circuit Theory, CT-12: 374–380,
1965.
26. W. H. Holmes, S. Gruetzmann, and W. E. Heinlein, Direct-cou-
pled gyrators with floating ports, Electron. Lett., 3 (2): 46–47,
1967.
27. D. G. Lampard and G. A. Rigby, Application of a positive immi-
tance inverter in the design of integrated selective filters, Proc.
IEEE, 55: 1101–1102, 1967.
28. X. Liu and L. T. Bruton, Improved LDI digital filters derived from
analog LC ladder filters, Signal Processing, 46: 147–158, 1995.
29. G. S. Moschytz, MOS Switched-Capacitor Filters: Analysis and
Design, New York: IEEE Press, 1984.
30. M. S. Lee, G. C. Temes, C. Chang, and M. G. Ghaderi, Bilinear
switched-capacitor ladder filters, IEEE Trans. Circuits Syst.,
CAS-28: 811–822, 1981.
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Circuits Syst., CAS-22: 168–176, 1975.
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XIAOJIAN LIU
Gennum Corp.
LEONARD T. BRUTON
University of Calgary
LADDER NETWORKS. See LATTICE FILTERS.
LADDER STRUCTURES. See LADDER FILTERS.
LAMPS, FILAMENT. See PHOTOMETRIC LIGHT SOURCES.
LAMPS, INCANDESCENT AND HALOGEN. See FIL-
AMENT LAMPS.
LANGUAGE, CONTEXT-SENSITIVE. See CONTEXT-
SENSITIVE LANGUAGES.
LANGUAGE IDENTIFICATION. See AUTOMATIC LAN-
GUAGE IDENTIFICATION.
LANGUAGE ISSUES IN INTERNATIONAL COMMU-
NICATION. See INTERNATIONAL COMMUNICATION.
LANGUAGES. See CONTEXT-SENSITIVE LANGUAGES.
LANGUAGES, AI. See AI LANGUAGES AND PROCESSING.
 LAPLACE TRANSFORMS 195

LANGUAGES, FUNCTIONAL PROGRAMMING.

See FUNCTIONAL PROGRAMMING.
LANS. See ETHERNET; LOCAL AREA NETWORKS.
LAPLACE TRANSFORM. See FOURIER TRANSFORM.
 LATTICE FILTERS 257

1 2

(a)

i1 i2
ya
+ +

v1 v2

yc yb
– –
yd

(b)

u1 1 ta 1 y2

tc tb

y1 td u2
1 1
(c)
LATTICE FILTERS Figure 1. (a) Generic lattice structure. (b) Analog lattice two-port
with v1 and i1 being the input port variables and v2 and i2 the output
This article discusses filters of a special topology called lattice port variables. Here ya, yb, yc, and yd represent the one-port admit-
filters which can be very useful for system phase correction. tances of the four branches of the lattice. (c) Digital lattice signal
Here the focus is on the analog lattice described in terms of flow graph. Here the branches are transmittances and the terminal
admittance, scattering, and transfer scattering matrices. A variables are signal inputs (u1 and u2) and outputs (y1 and y2).
synthesis technique based on the constant-resistance method
that yields a cascade realization in terms of degree-one or de-
gree-two real lattices is included. Also included is an example
to illustrate the technique. as we now show through the use of symmetrical constant R
lattices (4, Chap. 12; 5, p. 223; 6, Chap. 5).
We assume that the lattice branches are described by the
DEFINITION respective admittances, ya, yb, yc, yd in which case the two-port
admittance matrix Y has symmetry around the main and the
A lattice structure is one of the form of Fig. 1(a). In the case skew diagonals
of analog circuits, it is taken to be the two-port of Fig. 1(b)
 
with the port variables being voltages and currents, in which y y12
case the branches are typically represented by their one-port Y = 11 (1)
y12 y11
impedances or admittances. When the lattice is a digital lat-
tice, the structure represents a signal flow graph where the (ya + yb )(yc + yd )
branches are transmittances and the terminal variables are y11 = (2)
ya + yb + yc + yd
signal inputs and outputs, as shown in Fig. 1(c). Here we
treat the analog lattice only; a treatment of the digital lattice yb yc − ya yd
y12 = (3)
can be found in Refs. 1–3. ya + yb + yc + yd

In the case where the lattice is symmetrical as well about an

ANALOG LATTICE
horizontal line drawn through its middle, called a symmetri-
cal lattice,
The analog lattices are most useful for the design of filters
based upon the principle of constant R structures. These are
especially useful for phase correction via all-pass structures yd = ya and yc = yb (4)

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.
258 LATTICE FILTERS

we see by inspection R
...
  + +
1 ya + yb yb − ya +
Y = (5) Vin V1 N(1) N(2) N(n) V R
2 yb − ya ya + yb –
2

– ... –
From Eq. (5) we note that the mutual (off-diagonal) terms can
have zeros in the right half s-plane even when ya and yb may R R R
not. Consequently, the lattice can give nonminimum phase
responses in which case it can be very useful for realizing a Figure 3. Cascade of n constant-R two-port lattices of the type
desired phase shift, possibly for phase correction. shown in Fig. (1b) terminated on an R-ohm resistance at the output
port.

SYNTHESIS BY THE CONSTANT-R LATTICE METHOD

Admittance Matrix From Eq. (6) we can obtain the lattice arm impedances ya and
yb ⫽ G2 /ya since Eq. (9) gives
The constant-R lattice is defined by using dual arms. Specifi-
cally, writing G ⫽ 1/R, we obtain V2
1+
1 V1
Ryb = ⇒ ya yb = G2 (6) ya = G (11)
V2
Rya 1−
V1
which results in
  In order for a passive synthesis to proceed, ya must be positive
1 G2 + y2a G2 − y2a real, the requirement for which is that ya(s) be analytic in the
YR = (7) right half s-plane, Re(s) ⬎ 0, and
2ya G2 − y2a G2 + y2a

Re{ya (s)} ≥ 0 in Re(s) > 0 (12)

The name of this structure results from its beautiful property
that if it is terminated at port 2 on an R-ohm resistor, the
input impedance is an R-ohm resistor, as calculated from the Translated into the voltage transfer function, after some alge-
input admittance bra on Eq. (11), this is seen to be equivalent to

ya yb   
G ya + yb + 2  V2 
det Y + Gy11  ≤1 in Re(s) > 0 (13)
Yin = = G =G (8) V 
G + y22 ya + yb + 2G 1

and as illustrated in Fig. 2. The transfer voltage ratio is given In other words, if the voltage transfer function is rational in
by s and bounded in magnitude by 1 in the right-half plane, it is
guaranteed to be synthesized by a passive symmetrical con-
V2 −y21 yb − ya ya − G stant-R lattice with an R-ohm termination.
= = = (9) However, this synthesis in one whole piece of V2 /V1 may
V1 G + y22 yb + ya + 2G ya + G
require rather complex lattice arms, in which case we can
Also we have take advantage of the constant-R property to obtain a cascade
of lattices. Toward this consider Fig. 3, which shows a cascade
Vin of constant-R two-ports loaded in R. As is clear from Fig. 3
V1 = (10) we obtain a factorization of the voltage transfer function into
2
the product of n voltage transfer functions, one for each sec-
tion:
R      
ya V2 1 V2 V2 V
+ +
= ... 2 (14)
Vin 2 V1 N (1) V1 N (2) V1 N (n)

Vin + V1 V2
In order to synthesize a given realizable voltage transfer func-
R
– tion, we can perform a factorization of V2 /V1 into desirably
simple factors and realize each factor by a corresponding con-
yb yb stant-R lattice. The factorization can be done by factoring the
– – given transfer function into its poles and zeros and associat-
ya
ing appropriate pole–zero pairs with the V2 /V1 terms of Eq.
Zin = R
(14). Usually the most desirable factors are obtained by asso-
Figure 2. Symmetric analog lattice terminated on an R-ohm resis- ciating the poles and zeros into degree-one or degree-two
tance at the output port. real factors.
 LATTICE FILTERS 259

Lossless Synthesis By placing the zeros of N(s) one can usually obtain a desirable
phase shift. In particular, maximally flat delay can be ob-
A particularly interesting case is when the lattice is lossless,
tained by choosing N(s) to be a Bessel polynomial (7, p. 151).
which is expressed by

Example. For R ⫽ 5, design a cascade of two lattices and

ya (−s) = −ya (s) for a lossless lattice (15)
compare with an equivalent single lattice for the all-pass
function
from which we see by Eq. (9) that
Vout (s) 1 s2 − 3s + 2
V2 (s) V2 (−s) =
=1 for a lossless lattice (16) Vin (s) 2 s2 + 3s + 2
V1 (s) V1 (−s) (18)
1 (s − 2)(s − 1)
=
2 (s + 2)(s + 1)
In this lossless case we see that for s ⫽ j웆 the magnitude of
the voltage transfer function, from port 1 to 2, is unity; the
For the first lattice of a cascade of two, using Eqs. (11) and
circuit is all-pass and serves to only introduce phase shift for
(6) with V2 /V1 ⫽ (s ⫺ 2)/(s ⫹ 2), this gives
phase correction and for the design of constant time-delay
networks (7, pp. 144–152). If V2 /V1 is written as the ratio of sG s 2G 1
a numerator polynomial, N(s), over a denominator polyno- ya = = and yb = = (19)
2 10 s 2.5s
mial, D(s), then in the all-pass case we have N(s) ⫽ ⫾D(⫺s),
in which case the phase shift becomes twice that of the nu-
and for the second lattice, with V2 /V1 ⫽ (s ⫺ 1)/(s ⫹ 1), we
merator, which is then
obtain

V ( jω)  
Im(N( jω))

\ 2
V1 ( jω)
= 2 arctan
Re(N( jω))
(17) ya = Gs =
s
and yb =
G
=
1
(20)
5 s 5s

1 1
R = 5Ω 10 F 5 F

+
Vin R = 5Ω
– 2.5H 2.5H 5H 5H

1 1
10 F 5 F

(a)

15
2 H
1
R = 5Ω 5F

+ R = 5Ω
Vin 3 3
– H H
5 5
3 3
10 F 10 F

1
5 F
Figure 4. Lossless lattice synthesis of an all-
15 pass transfer function of degree two. (a) Syn-
H thesis using a cascade of two lattices of degree
2
1 Arms. (b) Equivalent realization using a sin-
(b) gle lattice of degree 2 Arms.
260 LATTICE FILTERS

In the case of a single lattice, for V2 /V1 twice the first expres- The entries s12 and s21 are calculated in terms of ya and G
sion of Eq. (18), we have using Eq. (11):

 
V2

Vout V ya − G
G(s2 + 2) s 1 3Gs G s12 = s21 = 2 =2 = 2 = (25)
ya = =G + 3 and yb = 2 = e1 Vin V1 ya + G
3s 3 s s +2 s 1 e 2 =0
2 + 3
3 2s


(21) The above results give the following scattering matrix:

The final cascade of lattices and equivalent lattice are given

ya − G
0
in Fig. 4(a) and Fig. 4(b), respectively. S= ya + G (26)
ya − G
0
ya + G
Scattering Matrix
It is also of interest to look at the scattering matrix referenced The zeros on the diagonal of S indicate that the constant-R
to R, S, for the constant-R lattice which can be found from lattice is matched to its terminations. Since cascade synthesis
the augmented admittance matrix, Yaug, of the lattice filter as can proceed via factorization of the transfer scattering matrix
illustrated in Fig. 5(a): (3), it is of interest to note that the transfer scattering ma-
trix, T(s), is given by
S = I2 − 2RYaug (22) y 

 a +G
0
1 1 −s22 ya − G
where I2 is the 2 ⫻ 2 identity matrix. By symmetry, we have T (s) = = Ya − G (27)
s12 s11 det S 0
from Fig. 5(b) ya + G

1 When working with the digital lattices of Fig. 1(c), the trans-
yaug11 = yaug22 = yin = (23)
2R fer scattering matrix is particularly convenient since its fac-
torization is readily carried out using Richard’s functions ex-
and thus tractions of degree-one and degree-two sections [see (3) for
details].
1
s11 = s22 = 1 − 2R =0 (24)
2R TRADE-OFFS AND SENSITIVITY

Despite its versatility, the lattice structure presents several

disadvantages of a practical nature. As seen in Fig. 4, there
i1 R R i2
is no possibility of a common ground between the input and
+ + the output terminals of a lattice circuit. Although generally it
is difficult to obtain a transformation of the lattice to a circuit
+ + with common input–output ground, a Darlington synthesis
e1 V1 V2 e2
– – can be undertaken with the desired result (8, Chap. 6). The
lattice also uses at least twice the minimum number of com-
– – ponents required since the upper arms repeat the lower arms.
Furthermore, since the transmission zeros are a function of
Yaug the difference of component values as seen by Eq. (5), small
(a) changes in these may distort the frequency response, the
phase in particular, considerably (6, p. 148). However, if cor-
R responding arm components simultaneously change in a loss-
+ + less lattice, so that the constant-R property is preserved, then
the sensitivity of 兩V2( j웆)/V1( j웆)兩 is zero since it is identically 1.

Vin R Vout
BIBLIOGRAPHY

– –
1 R
yin =
2R
(b)
Figure 5. (a) Network pertinent to the interpretation of the scatter-
ing parameters. (b) The R-terminated two-port used to evaluate the
input admittance yin. This two-port configuration is obtained from Fig.
(5a) by setting e2 ⫽ 0 and applying an input voltage Vin.
1. W. Chen (ed.), The Circuits and Filters Handbook, Boca Raton, FL:
CRC Press, 1995, pp. 2657–2661.
2. C. F. N. Cowan and P. M. Grant, Adaptive Filters, Englewood
Cliffs, NJ: Prentice-Hall, 1985, chap. 5.
3. L. Sellami and R. W. Newcomb, Synthesis of ARMA filters by real
lossless digital lattices, IEEE Trans. Circuits Syst. II, 43: 379–
386, 1996.
4. E. S. Kuh and D. O. Pederson, Principles of Circuit Synthesis, New
York: McGraw-Hill, 1959.
 LAW ADMINISTRATION 261

5. G. C. Temes and J. W. LaPatra, Introduction to Circuit Synthesis

and Design, New York: McGraw-Hill, 1977.
6. D. S. Humphreys, The Analysis, Design, and Synthesis of Electrical
Filters, Englewood Cliffs, NJ: Prentice-Hall, 1970.
7. D. E. Johnson, Introduction to Filter Theory, Englewood Cliffs, NJ:
Prentice-Hall, 1976.
8. H. Baher, Synthesis of Electrical Networks, Chichester: Wiley,
1984.

ROBERT W. NEWCOMB
University of Maryland at College
Park
LOUIZA SELLAMI
University of Maryland at College
Park
US Naval Academy

LAW. See CONTRACTS; LAW ADMINISTRATION; SOFTWARE MAN-

AGEMENT VIA LAW-GOVERNED REGULARITIES.
 LOGIC DESIGN 557

LOGIC DESIGN

The purpose of a design process is to develop a hardware sys-

tem that realizes certain user-defined functionalities. A hard-
ware system is one constructed from electronic components.
Signals enter and leave the system. They are either analog or
digital. Information carried by an analog signal is continuous,
whereas information carried by a digital (binary) signal is dis-
crete, represented as 1 and 0. Input signals are processed by
the hardware system which produces the output signals. Sig-
nals are also generated internally, and can be either digital
or analog. Digital subsystems can be combinational or se-
quential. There are two types of digital sequential systems;
synchronous systems and asynchronous systems. A synchro-
nous system is one whose elements change their values only
at certain specified times determined clock changes. Inputs,
states, and outputs of an asynchronous system can change at
any time.
A design process develops a hardware system capable of
performing some predefined functionality. The functionality
of a digital hardware system can be realized by two processes:
using logic circuits that are implemented with logic gates
and/or using software to drive the system. The former process
is referred to as hardware implementation, and the latter as
software implementation. The use of the software is related
to the use of microprocessors. If microprocessors are used in
a design, the design is referred to as a microprocessor-based
design.
In a microprocessor-based design, the functionalities are
implemented partially by hardware and partially by software.

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.
558 LOGIC DESIGN
The designer needs to divide the tasks between hardware and
software, which is sometimes referred to as software-hard-
ware co-design. The hardware portion includes the micropro-
cessor, memory, peripheral integrated circuits (IC), and glue
logic (glue logic are circuits that ‘‘glue’’ digital components to-
gether). The software is a set of computer programs stored in
the memory.
Logic circuits for digital hardware systems may be combi-
national or sequential. A combinational circuit is one whose
output values depend only on its present input values. A se-
quential circuit is one whose outputs depend not only on its
present inputs but also on its current (internal) state. In other
words, the present outputs are functions of present and previ-
ous input values. The input history is remembered by mem-
ory elements (e.g., registers). A register is a set of flip-flops.
The control unit of a digital system is normally imple-
mented by a sequential circuit. The data path can be imple-
mented by either a sequential circuit or a combinational cir-
cuit (and usually, also some registers). The data path may
consist of logic, arithmetic, and other combinational operators
and registers, as well as counters, memories, small state ma-
chines, interface machines, and other sequential blocks. Logic
design research develops procedures for efficient design of
digital circuits. Various technologies and related design meth-
odologies as well as computer tools are used to transform high
level system characterizations to working devices.
Complex modern systems include subsystems that require
both digital hardware design and microprocessor-based de-
sign. To design such systems, the designers need to be famil-
iar with both the co-design methodologies and co-design tools.
MATHEMATICAL CHARACTERIZATION
The mathematical characterization is concerned with mathe-
matical specification of the problem as some kind of transfor-
mation, equation solving, and so on. In the case of digital
circuit/system applications, the mathematical characteriza-
tions include, for example, the following models: regular ex-
pressions, extended regular expressions, data flow graphs, Pe-
tri nets, finite state machines, Boolean functions, timed
Boolean functions, and physical design models. The physical
design models can only be realized in hardware. All of the
other models mentioned above can be realized either in hard-
ware or in software or in both.
The goal of mathematical characterizations is to provide
the ability to investigate formally the problems of equiva-
lence, optimization, correctness, and formal design correct
from specification, by transformational methods.
Nowadays, most of the design is done automatically by
electronic design automation (EDA) tools. The logic and sys-
tem designers not only use the EDA tools, but also often de-
sign their own tools or adapt and personalize the existing
tools. That is why the problems of logic representation and
mathematical characterization are unseparable from the logic
design, and will be devoted here due attention.
High-Level Behavioral Specifications
Regular expressions are an example of high-level behavioral
specification of a sequential circuit. They describe the input
sequences accepted by a machine, output sequences gener-
ated by a machine, or input-output sequences of a machine.
Regular expressions are used in digital design to simplify de-
scription and improve optimization of such circuits as se-
quence generators or language acceptors. They use some fi-
nite alphabet of symbols (letters) and the set of operations.
The operations are concatenation, union, and iteration. Con-
catenation E1 ⭈ E2 means subsequent occurrence of events E1
and E2. Union E1 傼 E2 means logical-OR of the two events.
Iteration E* of event E means repetition of the event E an
arbitrary finite number of times or no occurrence of this
event. The simplest event is an occurrence of a single symbol.
Extended regular expressions generalize Regular Expressions
by adding the remaining Boolean operations. All the Boolean
operators can be used in an extended regular expression. For
instance, negation or Boolean product.
Petri nets are concurrent descriptions of sequential pro-
cesses. They are usually converted to finite state machines or
directly converted to sequential netlists. Because they are
also used in concurrent system specification, verification, and
software design, Petri nets are increasingly used in software-
hardware codesign and to specify hardware (25).
Finite State Machines
Finite state machines (FSMs) are usually of Mealy or Moore
types. Both Moore and Mealy machines have the following:
the set of input symbols, the set of internal states (symbols),
and the set of output symbols. They also have two functions:
the transition function 웃 and the output function ␭. The tran-
sition function 웃 specifies the next internal state as a function
of the present internal state and the present input state. The
output function ␭ describes the present output state. Moore
machines have output states which are functions of only the
present internal states. Mealy machines have output states
which are functions of both present internal states and pres-
ent input states. Thus state machines can be described and
realized as composition of purely combinational blocks 웃 and
␭ with registers that hold their states.
Parallel state machines are less commonly used compared
to Moore machines and Mealy machines. In a parallel state
machine several states can be successors of the same internal
state and input state. In other words, the parallel state ma-
chine is concurrently in several of its internal states. This is
similar in principle to concurrently having many tokens in
places of the Petri net graph description.
Nondeterministic state machines are another model. In a
nondeterministic state machine, there are several transitions
to next internal states from the same present input state and
the same present internal state. From this aspect, nondeter-
ministic state machines are syntactically similar to parallel
state machines. However, the interpretation between these
two machines is different. In a nondeterministic state ma-
chine, the several transitions to a next internal state is inter-
preted that any of these transitions is possible, but only one
is actually selected for next stages of design. The selection
may occur at the state minimization, the state assignment,
the state machine decomposition, or the circuit realization of
the excitation and output logic. The transition is selected in
order to simplify the circuit at the next design stage, or to
improve certain property of the circuit. The above selection is
done either automatically by the EDA tools, or manually by a
human. Nondeterminism expands the design space, and thus
gives the designer more freedom to improve the design. How-
ever, this can also lead to a more complex or a longer design
process.

There are several other generalizations of FSMs, such as
Buechi or Glushkov machines, which in general assume more
relaxed definitions of machine compatibility. For instance,
machines can be defined as compatible even if their output
sequences are different for the same starting internal states
and the same input sequences given to them, but the global
input–output relations of their behaviors are equivalent in
some sense. All these machines can be described in tabular,
graphical, functional, HDL language, or netlist forms, and re-
alized in many listed below technologies.
Boolean Functions Characterizations
Boolean functions are characterized usually as truth tables,
arrays of cubes, and decision diagrams. Representations can
be canonical or noncanonical. Canonical means that the rep-
resentation of a function is unique. If the order of the input
variables is specified, then both truth tables and binary deci-
sion diagrams are canonical representations. Cube represen-
tations are not canonical, but can be made canonical under
certain assumptions (for instance, all prime implicants of a
completely specified function). In a canonical representation
the comparison of two functions is simple. This is one of the
advantages of canonical representations. This advantage has
found applications in the verification and synthesis algo-
rithms.
Good understanding of cube calculus and decision dia-
grams is necessary to create and program efficient algorithms
for logic design, test generation and formal verification.
Truth Tables and Karnaugh Maps
A truth table for a logic function is a list of input combina-
tions and their corresponding output values. Truth tables are
suitable to present functions with small numbers of inputs
(for instance, single cells of iterative circuits). Truth tables
can be easily specified in hardware description languages
such as VHSIC hardware description language (VHDL).
Table 1 shows the truth table of a full adder. A full adder
is a logic circuit with two data inputs A and B, a carry-in
input Cin, and two outputs Sum and carry-out Cout.
Karnaugh maps are two-dimensional visual representa-
tions of truth tables. In a Karnaugh map, input variables are
partitioned into vertical and horizontal variables, and all
value combinations of input variables are expressed in Gray
codes. The Gray code expressions allow the geometrically ad-
jacent cells to become combinable using the law AB ⫹ AB ⫽
A. For instance, cells abcd and abcd are combined as a prod-
uct acd. For functions with large numbers of inputs, the corre-
sponding truth tables or Karnaugh maps are too large.
Table 1. Truth Table of Full Adder
A B Cin Sum Cout
0 0 0 0 0 generation and functional verifications. Multivalued cube cal-
0 0 1 1 0 culus extends these representations and operations to multi-
0 1 0 1 0 valued variables. In multivalued logic, each variable can have
0 1 1 0 1 several values from a set of values. For a n-valued variable,
1 0 0 1 0 all its literals are represented by n-element binary vectors
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
LOGIC DESIGN 559
Cube Representation. An array of cubes is a list of cubes,
which is usually interpreted as a sum of products of literals,
where a cube corresponds to a product of literals. A (binary) lit-
eral is a variable or a negated variable. In binary logic, symbol
0 corresponds to a negated variable, symbol 1 to a positive (af-
firmative, nonnegated) variable, symbol X to the absence of a
variable in the product, and symbol ⑀ to a contradiction. A cube
is a sequence of symbols 0, 1, X, and ⑀, corresponding to their
respective ordered variables. For instance, assuming the order
of variables: x1, x2, x3, x4, the cube 01X1 corresponds to the prod-
uct of literals x1x2x4, and the cube 0⑀X0 is an intermediate data
generated to show contradiction or a nonexisting result cube of
some cube operation. A minterm (a cell of a Karnaugh map and
a row of a truth table) is thus a sequence of symbols 1 and 0.
Arrays of cubes can also correspond to exclusive sums of prod-
ucts, products of sums, or others. For instance, the array of
cubes {01X1, 11XX} describes the sum-of-products expression
x1x2x4 ⫹ x1x2 called also the cover of the function with product
implicants (usually, with prime implicants). Depending on the
context, the same array of cubes can also describe the exclu-
sive-sum-of-products expression x1x2x4 丣 x1x2, or a product-of-
sums expression (x1 ⫹ x2 ⫹ x4) ⭈ (x1 ⫹ x2). The correct meaning of
the array is taken care of by applying respective cube calculus
operators to it.
An algebra of cube calculus has been created with cubes
and arrays of cubes and operations on them. The most impor-
tant operators (operations) are negation of a single cube or
nondisjoint sharp, disjoint sharp, consensus, crosslink, inter-
section, and supercube of two cubes. The cube operators most
often used in EDA programs are presented briefly below. The
nondisjoint sharp, A#B, creates a set of the largest cubes in
function A ⭈ B. Disjoint sharp, A#dB, creates a set of disjoint
cubes covering function A ⭈ B. Sharp operations perform
graphical subtraction and can be used in algorithms to re-
move part of the function that has been already taken care
of. Consensus of cubes A and B is the largest cube that in-
cludes part of cube A and part of cube B. Supercube of cubes
A and B is the smallest cube that includes entirely both cubes
A and B. Consensus and supercube are used to create new
product groups. Intersection of cubes A and B is the largest
common subcube of cubes A and B. It is perhaps the most
commonly used cube calculus operation, used in all practically
known algorithms. These operations are used mostly in the
inclusive (AND–OR) logic. Crosslink is the chain of cubes be-
tween two cubes. The chain of cubes covers the same min-
terms as the two cubes, and does not cover the minterms not
covered by the two cubes. Since A 丣 A ⫽ 0, an even number
of coverings is treated as no covering, and an odd number of
coverings is treated as a single covering. It is used mostly in
the exclusive (AND–EXOR) logic, for instance, in exclusive-
sum-of-products minimization (21). Positive cofactor f a is
function f with variable a substituted to 1. Negative cofactor
f a is function f with variable a substituted to 0.
Cube calculus is used mostly for optimization of designs
with two or three levels of logic gates. It is also used in test
where value 0 in the position corresponds to the lack of this
value in the literal, and value 1 to the presence of this value.
For instance, in 4-valued logic, the literal X0,1,2 is represented
560 LOGIC DESIGN
as a binary string 1110, which means the following assign-
ment of values: X 0 ⫽ 1, X 1 ⫽ 1, X 2 ⫽ 1, X 3 ⫽ 0. It means, the
literal X 兵0,1,2其 is a 4-valued-input binary-output function de-
fined as follows: X 兵0,1,2其 ⫽ 1 when X ⫽ 1, or X ⫽ 2, or X ⫽ 3,
X 兵0,1,2其 ⫽ 0 when X ⫽ 4. Such literals are realized in binary
circuits by input decoders, literal generators circuits, or small
PLAs. Thus, multivalued logic is used in logic design as an
intermediate notation to design multilevel binary networks.
For instance, in 4-valued model used in programmable logic
array (PLA) minimization, a 4-valued set variable corre-
sponds to a pair of binary variables. PLA with decoders allow
to decrease the total circuit area in comparison with standard
PLAs. This is also the reason of using multivalued logic in
other types of circuits. Well known tools like MIS and SIS
from the University of California at Berkeley (UC Berkeley)
(23) use cube calculus format of input/output data.
A variant of cube calculus representation are the factored
forms (for instance, used in MIS), which are multilevel compo-
sitions of cube arrays (each array specifies a two level logic
block). Factored form is thus represented as a multi-DAG (di-
rected acyclic graph with multiedges). It has blocks as its
nodes and logic signals between them as multiedges. Each
component block specifies its cube array and additionally its
input and output signals. Input signals of the block are pri-
mary inputs of the multilevel circuit, or are the outputs from
other blocks of this circuit. Output signals of the block are
primary outputs of the multi-level circuit, or are the inputs
to other blocks of this circuit. Initial two-level cube calculus
description is factorized to such multi-level circuit described
as a factored form. Also, a multilevel circuit can be flattened
back to a two level cube representation.
Binary Decision Diagrams. Decision diagrams represent a
function by a directed acyclic graph (DAG). In the case of the
most often used binary decision diagrams (BDDs), the nodes
of the graph correspond to Shannon expansions (realized by
multiplexer gates), controlled by the variable a associated
with this node: F ⫽ a ⭈ Fa ⫹ a ⭈ Fa. Shared BDDs are those in
which equivalent nodes of several output functions are
shared. Equivalent nodes g and h are those whose cofactor
functions are mutually equal: ga ⫽ ha and ga ⫽ ha. Ordered
BDDs are those in which the order of nodes in every branch
from the root is the same. A diagram can be obtained from
arbitrary function specifications, such as arrays of cubes, fac-
tored forms, expressions, or netlists. The diagram is obtained
by recursive application of Shannon expansion to the func-
tion, next its two cofactors, four cofactors of its two cofactors,
and so on, and by combination of any isomorphic (logically
equivalent) nodes. The function corresponds to the root of the
diagram. There are two terminal nodes of a binary decision
diagram, 0 and 1, corresponding to Boolean false and true. If
two successor nodes of a node Si point to the same node, then
node Si can be removed from the DAG. There are other simi-
lar reduction transformations in those diagrams which are
more general than BDDs. Decision diagrams with such reduc-
tions are called reduced ordered decision diagrams.
In addition, negated (inverted) edges are introduced in
BDDs. Such edges describe negation of its argument function.
In Kronecker decision diagrams (KDDs) three types of expan-
sion nodes exist: Shannon nodes (realizing function f ⫽
a ⭈ f a ⫹ a ⭈ f a), positive Davio nodes [realizing function f ⫽
a ⭈ ( fa 丣 f a) 丣 f a], and negative Davio nodes [realizing function
f ⫽ a ⭈ ( fa 丣 f a) 丣 f a]. All of the three possible canonical expan-
sions of Boolean functions are thus included in KDD. Other
known decision diagrams include zero-suppressed binary de-
cision diagrams (ZSBDDs) and moment diagrams. They are
used primarily in verification or technology mapping. Multi-
valued decision diagrams have more than two terminal nodes
and multivalued branchings with more than two successors
of a node. These diagrams allow one to describe and verify
some circuits (such as large multipliers) that are too large to
be described by standard BDDs. Some diagrams may also be
better for logic synthesis to certain technologies.
There are two types of decision diagrams: canonical dia-
grams and noncanonical diagrams. Canonical diagrams are
used for function representation and tautology checking.
ZSBDDs and KDDs are examples of canonical representa-
tions. An example of noncanonical decision diagrams is a free
pseudo-Kronecker decision diagram. In this type of diagram,
any types of Shannon and Davio expansions can be mixed in
levels and all orders of variables are allowed in branches.
Free pseudo-Kronecker decision diagrams are used in synthe-
sis and technology mapping (21,22). Decision diagrams can be
also adapted to represent state machines. By describing a
state machine as a relation, the (logic) characteristic function
of the machine can be described by a decision diagram.
Level of Design Abstraction
A design can be described in different levels of abstraction, as
shown in Fig. 1.
• Architecture level (also called behavioral level). At this
level, the designer has the freedom to choose different
algorithms to implement a design (for instance, different
digital filtering or edge detection algorithms). The em-
phasis is on input–output relations. Different implemen-
tations for the same function can be considered. For in-
stance, for a given function, one can chose between two
logic implementations: sequential and parallel combina-
tional (arithmetic adder, comparator or multiplier being
good examples).
• Register transfer level (RTL). At this stage, the design is
specified at the level of transfers among registers. Thus,
the variables correspond to generalized registers, such as
Architectural level
Register transfer
level
Logic gate level
Circuit level
Figure 1. The abstraction levels of a logic design.

shifters, counters, registers, memories, and flip-flops.
The operations correspond to transfers between registers
and logical, arithmetical and other combinational opera-
tions on single or several registers. Examples of opera-
tions on a single register are shift left, shift right, shift
cyclically, add one, subtract one, clear, set, negate. An
example of more general register-transfer operations is
A 씯 B ⫹ C, which adds the contents of registers B and
C and transfers the result to register A. A register-trans-
fer description specifies the structure and timing of oper-
ations in more detail but still allows for transformations
of data path, control unit, or both. The transformations
will allow improved timing, lower design cost, lower
power consumption, or easier circuit test.
• Logic level (gate level). At this level every individual flip-
flop and logic bit is specified. The timing is partially fixed
to the accuracy of clock pulses. The (multioutput) Bool-
ean functions with certain number of inputs, outputs,
and certain fixed functionality are specified by the user
or obtained by automatic transformations from a regis-
ter-transfer level description. These functions are speci-
fied as logic equations, decision diagrams, arrays of
cubes, netlists, or some hardware description language
(HDL) descriptions. They can be optimized for area,
speed, testability, number of components, cost of compo-
nents, or power consumption, but the general mac-
ropulses of the algorithm’s execution cannot be changed.
• Physical level. At this level a generic, technology-inde-
pendent logic function is mapped to a specific technol-
ogy—such as electronically programmable logic devices
(EPLD), complex programmable logic devices (CPLD),
field programmable gate arrays (FPGA), standard cells,
custom designs, application specific integrated circuits
(ASIC), read only memory (ROM), random access mem-
ory (RAM), microprocessor, microcontroller, standard
small scale integration (SSI)/medium scale integration
(MSI)/large scale integration (LSI) components, or any
combinations of these. Specific logic gates, logic blocks,
or larger design entities have been thus defined and are
next placed in a two-dimensional area (on a chip or
board) and routed (interconnected).
Logic Design Representations
A logic function can be represented in different ways. Both
behavioral (also called functional) representations and struc-
tural representations are used in logic designs. The represen-
tations can be used at all different levels of abstraction: archi-
tecture level, register-transfer level, and logic level.
Waveforms. Waveforms are normally used for viewing sim-
ulation results and specifying stimulus (input) to the simula-
tor. Recently they are also being used increasingly as one pos-
sible input data design specification, especially for designing
asynchronous circuits and circuits that cooperate with buses.
Figure 2 shows the waveforms of a full adder.
Logic Gate Networks. Standard design uses basic logic
gates: AND, OR, NOT, NAND, and NOR. Recently EXOR and
XNOR gates were incorporated into tools and designs. Several
algorithms for logic design that take into account EXOR and
XNOR gates have been created. For certain designs, such as
LOGIC DESIGN 561
arithmetic datapath operations, EXOR based logic can de-
crease area, improve speed and power consumption, and im-
prove significantly the testability. Such circuits are thus used
in design for test. Other gate models include designing with
EPLDs, which realize AND–OR and OR–AND architectures,
corresponding to sum-of-products and product-of-sums ex-
pressions, respectively. In standard cell technologies more
powerful libraries of cells are used, such as AND–OR–
INVERT, or OR–AND–INVERT gates. In FPGAs different
combinations of multiplexers, cells that use positive Davio
(AND–EXOR) and negative Davio (NOT–AND–EXOR)
expansion gates, or similar cells with a small number of in-
puts and outputs are used. The lookup-table model assumes
that the arbitrary function of some small number of variables
(3, 4, or 5) and small number of outputs, usually 1 or 2, can be
realized in a programmable cell. Several design optimization
methodologies have been developed for each of these models.
Boolean Expressions. Boolean expressions use logic functors
(operators) such as AND, OR, NOR, NOT, NAND, EXOR, and
MAJORITY, as well as literals, to specify the (multioutput)
function. In order to specify netlists that correspond to DAGs,
intermediate variables need to be introduced to the expres-
sions. Every netlist or decision diagram can be specified by a
set of Boolean expressions with intermediate variables. Bool-
ean expressions can use infix (or standard), prefix (or Polish),
or postfix (or reverse Polish) notations. Most modern specifi-
cation languages use infix notation for operators such as AND
or OR. Operator AND can sometimes be omitted, as in stan-
dard algebraic notations. In conjunction with operators such
as NAND, both infix and prefix notations are used. For in-
stance, (NAND a b c) in prefix and (a NAND b NAND c) in
infix. Care is recommended when reading and writing such
expressions in hardware description languages and input for-
mats to tools. It is always good to use parentheses in case of
doubt about operators’ precedence. In some languages, arbi-
trary operators can be defined by users and then can be used
in expressions on equal terms with well-known operators. Ex-
pressions can be created for SOP (sum-of-products), POS
(product-of-sums), factorized SOPs and POSs, and other rep-
resentations as a result of logic synthesis and optimization
algorithms. Some of these algorithms will be described in the
section on combinational logic design.
Behavioral Descriptions. A logic system can be described by
hardware description languages (HDL). The most popular
ones are Verilog and VHDL. Both Verilog and VHDL can de-
scribe a logic design at different levels of abstraction, from
gate-level to architectural-level representations. Both are now
industrial standards, but VHDL seems to gain its popularity
faster, especially outside the United States. In recent years
A
B
Cin
Sum
Cout
Time
Figure 2. Waveforms for the full adder.
562 LOGIC DESIGN
several languages at higher level than VHDL have been pro-
posed, as well as preprocessors to VHDL language from these
new representations, but so far none of them enjoyed wide
acceptance (e.g., State Charts, SpecCharts, SDL, and VAL).
State Charts and SpecCharts are graphical formalisms that
introduce hierarchy to state machines. SDL stands for the
Specification and Description Language. It is used mainly in
telecommunication. VHDL Annotation Language (VAL) is a
set of extensions to VHDL to increase its capabilities for ab-
stract specification, timing specification, hierarchical design,
and design validation. Other known notations and corre-
sponding data languages include regular expressions, Petri
nets, and path expressions.
Design Implementation
A design can be targeted to different technologies: full custom
circuit design, semicustom circuit design (standard cell and
gate array), FPGAs, EPLDs, CPLDs, and standard compo-
nents.
In the full custom circuit designs, the design effort and cost
are high. This design style is normally used when high-qual-
ity circuits are required. Semicustom designs use a limited
number of circuit primitives, and therefore have lower design
complexity and may be less efficient when compared to the
full custom designs.
Design Verification
A design can be tested by logic simulation, functional testing,
timing simulation, logic emulation, and formal verification.
All these methods are called validation methods.
Logic Simulation. Logic simulation is a fast method of ana-
lyzing a logic design. Logic simulation models a logic design
as interconnected logic gates but can also use any of the
mathematical characterizations specified previously (for in-
stance, binary decision diagrams). The simulator applies test
vectors to the logic model and calculates logic values at the
output of the logic gates. The result of the logic simulation
can be either logic waveforms or truth tables.
Timing Simulation. Timing simulation is similar to logic
simulation, but it also considers delays of electronic compo-
nents. Its goal is to analyze the timing behavior of the circuit.
The results from the timing simulation can be used to achieve
target circuit timing characteristics (e.g., operational fre-
quency).
Formal Verification. While simulation can demonstrate
that a circuit is defective, it is never able to formally prove
that a large circuit is totally correct, because of the excessive
number of input and state combinations. Formal verification
uses mathematical methods to verify exhaustively the func-
tionality of a digital system. Formal verification can reduce
the search space by using symbolic representation methods
and by considering many input combinations at once. Cur-
rently, there are two methods that are widely used: model
checking and equivalence checking. Model checking is used at
the architectural level or register-transfer level to check if the
design holds certain properties. Equivalence checking com-
pares two designs at the gate level or register-transfer level.
It is useful when the design is transformed from one level to
another level, or when the design functionality has changed
at the same level. Equivalence checking can verify if the origi-
nal design and the modified design are functionally equiva-
lent. For instance, two Boolean functions F1 and F2 are equiv-
alent when they constitute a tautology F1 ⇔ F2, ⫽ 1, which
means the function G ⫽ F1 ⇔ F2 is equal to 1 (or function
F1 丣 F2 is equal to zero) for any combination of its input vari-
able values. A more restricted version of tautology may in-
volve equality only on combinations of input values that actu-
ally may happen in actual operation of the circuit (thus ‘‘don’t
care’’ combinations are not verified). Verification of state ma-
chines in the most narrow sense assumes that the two ma-
chines generate exactly the same output signals in every
pulse and for every possible internal state. This is equivalent
to creating, for machines M1 and M2 with outputs z1 and z2,
respectively, a new combined machine with output zcom ⫽
z1 丣 z2 and shared inputs, and proving that output zcom ⫽ 0
for all combinations of state and input symbols (9). A more
restricted equivalence may require the identity of output sig-
nals for only some transitions. Finally, for more advanced
state machine models, only input–output relations may be re-
quired to be equivalent in some sense. Methods based on au-
tomatic theorem proving in predicate calculus and higher or-
der logic have been also developed for verification and formal
design correct from specification, but are not yet much used
in commercial EDA tools. Computer tools for formal verifica-
tion are available from EDA companies and from universities
(e.g., VIS from UC Berkeley (5), and HOL (10) available from
the University of Utah).
Design Transformation
High-level design descriptions make it convenient for design-
ers to specify what they want to achieve. Low-level design
descriptions are necessary for design implementation. Design
transformations are therefore required to convert a design
from a higher level of abstraction to lower levels of abstrac-
tion. Examples of design transformations include removal of
dead code from the microcode, removal of dead register vari-
ables, minimization of the number of generalized registers,
cost minimization of combined operations units (SUM/SUB-
TRACT, MULTIPLY, etc.), Mealy-to-Moore and Moore-to-
Mealy transformations of state machines (which can change
the system’s timing by one pulse), transformation of a nonde-
terministic state machine to an equivalent deterministic ma-
chine, transformation of a parallel state machine to an equiv-
alent sequential machine, and mapping of a BDD to a netlist
of multiplexers.
Logic Design Process
A logic design is a complex process. It starts from the design
specification, where the functionality of the system is speci-
fied. Design is an iterative process involving design descrip-
tion, design transformation, and design verification. Through
each iteration, the design is transformed from a higher level
of abstraction to a lower level. To ensure the correctness of
the design, verification is needed when the design is trans-
formed from one level to another level. Each level may involve
some kind of optimization (for instance, the reduction of the
description size). The logic design process is shown in Fig. 3.

Design specification
Description
Transformation
Verification
Implementation
Figure 3. The logic design process.
COMBINATIONAL LOGIC DESIGN
A combinational logic design involves a design of a combina-
tional circuit. For instance, the design may assume two levels
of logic. A two-level combinational logic circuit consists of two
levels of logic gates. In the sum-of-products two-level form,
the first (from the inputs) level of gates are AND gates and
the second level of gates are OR gates. In the product-of-sums
two-level form, the first level of gates are OR gates and the
second level of gates are AND gates.
The reason of logic minimization is to improve the perfor-
mance and decrease the cost by decreasing the area of the
silicon, decreasing the number of components, increasing the
speed of the circuit, making the circuit more testable, making
it use less power, or achieving any combination of the above
design criteria. The optimization problem can be also speci-
fied to minimize certain weighted cost functions under certain
constraints (for instance, to decrease the delay under the con-
straint of not exceeding certain prespecified silicon area).
There are usually two logic minimization processes; the
first one is generic and technology-independent minimization,
the next one is technology-dependent minimization, called
also technology mapping. This second stage may also take
into account some topological or geometrical constraints of
the device.
Two-Level Combinational Logic
There are two types of programs for two-level logic minimiza-
tion. Exact programs minimize the number of product impli-
cants, the number of literals, or some weighted functions of
the two. Heuristic or approximate programs attempt to mini-
mize these cost functions but do not give assurance of their
minimum values. Usually, the exact programs generate all
prime implicants or a subset of them, which can be proven to
include at least one minimal solution. The prime implicant is
a product of literals from which no literal can be removed.
LOGIC DESIGN 563
These implicants are then the largest products-of-literals
groups of true minterms in a Karnaugh map that imply the
function. Next, an exact program creates a covering table and
find its best covering with prime implicants. Such a table has
true minterms as columns and prime implicants (or their sub-
set) as rows (or vice versa). If an implicant covers (includes)
a minterm, it is denoted by an entry 1 at the intersection of
the row corresponding to the implicant and the column corre-
sponding to the minterm. The exact solution (minimum, prod-
uct-wise) is the subset of rows that cover (have minterms in)
all columns and that has the minimum number of rows. The
minimum solution (literal-wise) is the subset of rows that
cover (have minterms in) all columns and has the minimum
total number of literals in product terms (or that minimizes
another similar cost function). Some algorithms use the con-
cept of essential prime implicants. An essential prime is a
prime that includes a certain minterm that is covered only by
this prime. A redundant prime is an implicant that covers
only minterms covered by essential primes. Redundant
primes can thus be disregarded. A secondary essential prime
is a prime that becomes essential only after previous removal
of some redundant primes.
The essential primes found are taken to be the solution
and the minterms covered by them are removed from the
function (using for instance sharp operator of cube calculus).
This causes some primes to become redundant and results in
origination of the secondary essential primes. This process of
finding essential and secondary essential primes is iterated
until no further minterms remain in the function—thus the
exact solution is found without creating and solving the cov-
ering table. Functions with such a property are called noncy-
clic functions. Most of real-life functions are either noncyclic
or have large noncyclic cores, which is the reason for the rela-
tive efficiency of such algorithms.
Approximate algorithms try to generate primes and find
primes cover at the same time; thus they reshape the current
cover by replacing some groups of primes with other primes,
applying cube operations such as consensus.
Program Espresso from UC Berkeley (4) is a standard for
two-level logic functions. The original program was next ex-
tended to handle multivalued logic to allow for PLAs with
decoders, function generators, and preprocessing PLAs.
Espresso–MV is useful for sequential machine design, espe-
cially state assignment and input/output encodings. Its ideas
help also to develop new programs for these applications. Al-
though heuristic version of Espresso does not guarantee the
exact solution, it is close to minimum on several families of
practical functions. Its variant, Espresso–Exact, finds the
minimum solution, and program Espresso-Signature can find
exact solutions even for functions with extremely large num-
ber of prime implicants. This is due to a smart algorithm that
can find exact solutions without enumerating all the prime
implicants. There are some families of practical functions for
which Espresso does not give good results and which are too
large for Espresso–Exact or Espresso-Signature. Programs
such as McBoole or other internally designed programs are
combined with Espresso as user-called options in some com-
mercial tools. Two-level minimization is used in many pro-
grams for multilevel synthesis, EPLD-based synthesis, and
PLD/CPLD device fitting. These algorithms constitute the
most advanced part of today’s EDA theory and practice.
564 LOGIC DESIGN
Topics close to sum-of-products minimization are product-
of-sums design, three-level design (AND–OR–AND or OR–
AND–OR), four-level design (AND–OR–AND–OR), and other
designs with a few levels of AND–OR logic. Algorithms for
their solution usually generate some kind of more complex
implicants and solve the set-covering or graph-coloring prob-
lems, either exactly or approximately. Such approaches are
used for PLD and CPLD minimization.
Another two-level minimization problem is to find, for a
given function, the exclusive-sum-of-products expression with
the minimum gate or literal cost. Several algorithms have
been created for this task (21,22). Tools for circuits that have
few, usually three, levels and have levels of gates AND,
EXOR and OR, in various orders, have been also recently de-
signed (21,22).
Many concepts and techniques used in two-level minimiza-
tion (for instance, essential implicants or covering tables) are
also used in multilevel synthesis. Similar techniques are used
in sequential synthesis (for example, a binate covering prob-
lem is used in both three-level design and state minimization,
and clique covering is used in creating primes and in several
problems of sequential design).
An important stage of the logic design involves finding the
minimum support of a function, which means the minimum
set of input variables on which the given function depends.
This can be used for logic realization with EPLDs (because of
the limited number of inputs) or in ROM-based function real-
ization.
Many efficient generic combinatorial algorithms have been
created for logic synthesis programs. They include: unate cov-
ering (used in SOP minimization, decomposition and mini-
mum support problems), binate covering (used in state ma-
chine minimization and three-level design), satisfiability (is
F ⫽ 0? if yes, when?), tautology (is F ⫽ G?), and graph color-
ing (used in SOP minimization and functional decomposition).
All these algorithms can be used for new applications by EDA
tool designers.
Multilevel Combinational Logic
Factorization. A multilevel combinational logic circuit con-
sists of more than two levels of logic gates. There are several
design styles that are used to obtain such circuits. The first
method is called factorization. It recursively applies factoring
operations such as ab ⫹ ac ⫽ a(b ⫹ c) and (a ⫹ b) ⭈ (a ⫹ c) ⫽
a ⫹ (bc). Some factoring algorithms also use other transfor-
mations as well, such as ab ⫹ ac ⫽ abc, and abcd ⫽ ababcd
⫽ abacd. Efficient factoring algorithms based on kernels and
rectangle covering have been created (11). They are used in
many commercial tools, and are still being refined and im-
proved to add special functionalities (for instance, improved
testability). They are also being adapted for state assignment
or reduced power consumption of the circuit. Another advan-
tage of factorization is that it allows representation of large
circuits. A high-quality multi-level program, SIS, based
mostly on factorization, can be obtained from UC Berkeley
(23).
Functional Decomposition
The second group of multilevel synthesis methods are those
based on functional decomposition. Such methods have origi-
nated from early research of Ashenhurst (2), Curtis (7), and
Roth/Karp (20). Functional decomposition methods do not as-
sume any particular type of gates: rather they just decompose
a larger function to several smaller functions. Both functions
can be specified as tables, arrays of cubes, BDDs, netlists, or
any other aforementioned logic representations, both binary
and multivalued. Functional decompositions can be separated
into parallel and serial decompositions. Parallel decomposi-
tion decomposes multioutput function [F1(a, b, c, . . ., z),
F2(a, b, c, . . ., z), . . ., Fn⫺1(a, b, c, . . ., z), Fn(a, b, c, . . .,
z)] to several, usually two, multioutput functions, called
blocks. For instance, [F1(a, b, c, . . ., z), F2(a, b, c, . . ., z),
. . ., Fn⫺1(a, b, c, . . ., z), Fn(a, b, c, . . ., z)] is decomposed
into [Fi1(a, . . ., x), . . ., Fir(c, . . ., z)] and [Fir⫹1(a, b, . . ., y),
. . ., Fin(c, . . ., x)], such that each component function de-
pends now on fewer variables (thus the support set of each is
decreased, often dramatically). This problem is similar to the
partitioning of a PLA into smaller PLAs.
Serial decomposition is described by a general formula:
F (A, B, C) = H(A ∪ C, G(B ∪ C)) (1)
where the set of variables A 傼 C is called the set of free vari-
ables (free set), the set of variables B 傼 C is called the set of
bound variables, and the set of variables C is called the
shared set of variables. If C ⫽ 0 兾, the decomposition is called
disjoint, otherwise it is called nondisjoint. Function G is
multioutput (or multivalued) in Curtis decomposition, and
single-output in classical Ashenhurst decomposition. Func-
tion G can be also multivalued. Every function is nondisjoint
decomposable, and many practical functions are also disjoint
decomposable. The more a function is unspecified (the more
‘‘don’t cares’’ it has), the better are the decompositions and
higher the chances of finding disjoint decompositions with
small bound sets.
It was shown that practical benchmark functions are well
decomposable with small or empty shared sets, in contrast to
randomly generated completely specified functions, for which
such decompositions do not exist. Most of the decomposition
methods decompose recursively every block G and H, until
they become non-decomposable. What is defined as non-
decomposable depends on any particular realization tech-
nology (for instance, any function with not more than four
variables is treated as non-decomposable, assuming the
lookup-table model with four input variables in a block). In a
different technology, the decomposition is conducted until ev-
ery block becomes a simple gate realized in this technology
(for instance, a two-input AND gate, a MUX, or a three-input
majority gate). Important problems in decomposition are
finding good bound sets and shared sets and the optimal en-
coding of multivalued functions G to binary vectors, in order
to simplify concurrently both functions G and H.
Designing combinational logic using ROMs or RAMs is an-
other important area. Because of the limited width of indus-
trial chips, one has to create additional combinational address
generator circuits, or other circuits that collaborate with the
memory chip. Some of these techniques are quite similar to
decomposition.
Decomposition methods are not yet used in many indus-
trial tools, but their importance is increasing. A universal
functional decomposer program can be obtained from Port-
land State University (19).
Decision Diagrams. Finally, the last group of multilevel
synthesis methods is based on various kinds of decision dia-

grams. In the first phase the decision diagram such as a BDD,
KFDD, or ZSBDD, is created, and its cost (for instance, the
number of nodes), is minimized. An important design problem
is to find a good order of input variables (i.e., one that mini-
mizes the number of nodes). For synthesis applications these
diagrams are not necessarily ordered and canonical, because
the more general diagrams (with less constraints imposed on
them) can correspond to smaller or faster circuits. A universal
Decision Diagram package PUMA that includes BDDs,
KFDDs, and ZSBDDs, is available from Freiburg University
(8). Free BDDs, with various orders of variables in branches,
or noncanonical Pseudo–Kronecker decision diagrams with
mixed types of expansions in levels, are used in technology
mapping (22). In the next phase, certain rules are used to
simplify the nodes. Among these rules, the propagation of
constants is commonly used. For instance, a Shannon node (a
MUX) realizing a function a ⭈ 0 ⫹ a ⭈ b is simplified to AND
gate a ⭈ b. MUX realizing ab 丣 a is simplified to OR gate a ⫹
b. All rules are based on simple Boolean tautologies. For in-
stance, a positive Davio node realizing a function a ⭈ b 丣 a is
simplified to an AND gate a ⭈ b. The heuristic algorithms that
apply these transformations are iterative, recursive, or rule-
based. They are usually very fast.
For some technologies, the stage of generic multilevel opti-
mization is followed by the technology-related phase (called
technology mapping), in which techniques such as DAG cov-
ering, or tree covering by dynamic programming are applied
(11). At this stage, the particular technological constraints of
a given target technology are taken into account by rede-
signing for particular cell libraries, fitting to certain fan-in or
fan-out constraints, minimizing the number of cells to fit the
IC device, or decreasing the number of connections to fit the
routing channel width.
SEQUENTIAL LOGIC DESIGN
Sequential logic design involves designing sequential circuits.
A sequential circuit contains flip-flops or registers. A good un-
derstanding of flip-flop’s behavior is necessary to design se-
quential circuits. A flip-flop is an elementary register with a
single bit. Flip-flops are synchronous and asynchronous. An
example of an asynchronous flip-flop is a simple latch that
changes its state instantly with the change of one of its in-
puts; it is set to state ON with logic value 1 on input S (set)
and reset to state OFF with logic value 1 on input R (reset).
The disadvantage of such a latch is a nonspecified behavior
when both set and reset inputs are active at the same time.
Therefore, synchronization signals are added to latches and
more powerful edge-triggered or master-slave circuits are
built, called the synchronized flip-flops. The most popular flip-
flop is a D-type flip-flop. It has a clock input C, a data input
D, and two outputs, Q and Q. Output Q is always a negation
of Q. The present state of input D (i.e., the excitation function
D of the flip-flip) becomes the next state of output Q upon
a change of the flip-flop’s clock. Therefore, we can write an
equation, Q⬘ ⫽ D, where Q⬘ is the new state of the flip-flop.
The state changes may occur at the raising slope or the falling
slope of the clock. The moment of change is irrelevant from
the point of view of design methodologies, and modern meth-
ods assume that all change moments are of the same type. It
is not recommended to design a sequential circuit that
changes its states with both leading and falling slopes. A T-
LOGIC DESIGN 565
type flip-flop triggers its state from 0 to 1 and from 1 to 0
whenever its input T is 1 during the change of clock. It re-
mains in its current state if the input T is 0 during the
change. A JK flip-flop has two inputs; J is the setting input,
K is the resetting input. Thus, with J ⫽ 1 and K ⫽ 0 the flip-
flop changes to state 1 (with the clock’s change). If both inputs
are equal to 1, the flip-flop toggles, thus working as a T flip-
flop. If they are both 0, it remains in its present state. Various
procedures have been created to design special machines
(such as counters or registers), general Finite State Machines,
or other sequential mathematical models, with these flip-
flops.
Standard FSM Design Methodology
Sequential logic design typically includes three phases. In the
first phase a high-level description is converted into a state
machine or equivalent abstract description. For instance, a
regular expression is converted into a regular nondeterminis-
tic graph. The graph is converted into an equivalent deter-
ministic graph, and finally into a Moore or Mealy machine
state table. In some systems this table is then minimized.
State minimization always attempts to reduce the number of
internal states, and sometimes, also the number of input sym-
bols. In some algorithms the numbers of output bits are also
minimized. After minimization, the machine has a smaller ta-
ble size but is completely equivalent, with accuracy of the
clock pulses, to the initial table. The next design stage is the
state assignment, in which every present and next state sym-
bol in the table is replaced with its binary codes. In this way
the encoded transition table is created, which functionally
links the encoded present internal states, present input
states, present output states, and next internal states. Now
combinational functions 웃 and ␭ have been uniquely deter-
mined. They are usually incompletely specified. In some sys-
tems, the encoding (state assignment) is also done for input
and/or output symbols. Assignment of states and symbols is
done either automatically or manually. Good assignment
leads to a better logic realization in terms of the number of
product terms, literals, speed, etc. Several good assignment
programs, KISS, MUSTANG, and NOVA, are available in the
SIS system from UC Berkeley. DIET encoding program is
available from University of Massachusetts, Amherst (6).
State minimizer and encoder STAMINA is available from the
University of Colorado. In general, much information about
public domain or inexpensive programs for state machine de-
sign is available on the World Wide Web (WWW).
Because the minimized table is not necessarily the best
candidate for state assignment, in some systems the phases
of state minimization and state assignment are combined into
a single phase and only partial state minimization results as
a byproduct of state assignment of a nonminimized table (15).
This means that some compatible states may be assigned the
same code. This is done to minimize some complex cost func-
tions, which may take into account all kinds of optimizations
of logic realizing this machine: area, speed, power consump-
tion, testability, and so on. State assignment is a very impor-
tant design phase that links the stages of abstract and struc-
tural synthesis of state machines. It can influence greatly the
cost of the solution [for instance, in FPGA or programmable
array logic (PAL) technologies]. It can improve dramatically
the testability of designs, and n out of k codes are used for
566 LOGIC DESIGN
this task. For FPGAs good results are usually achieved by
encoding machines in 1 out of k (or, one-hot) codes.
State Machine Decomposition
Another methodology of designing sequential circuits is de-
composition. There are basically two methods of decomposi-
tion. Formal decomposition of state machines is a generaliza-
tion of functional decomposition of Boolean and multivalued
functions. Most of the decomposition methods are based on
the partition theory (12), a mathematical theory also used in
state assignment. This theory operates on groups of states
that have some similar properties and groups of states to
which these states transit under a given input. Other de-
composition methods operate on state graphs of machines, as
on labeled graphs in the sense of graph theory. They use
graph-theoretical methods to partition graphs into smaller
subgraphs that are relatively disconnected. Yet another de-
composition method decomposes the given state table into two
tables: one describes a state machine, such as a counter or
shift register, and the other describes a remainder machine.
For instance, methods have been developed to decompose a
state machine to an arbitrary counter and the remainder
machine. Another method decomposes a FSM into a special
linear counter (that uses only D flip-flops and EXOR gates)
and a remainder machine. Yet another decomposition type
uses two counters, shift registers, fixed preprocessor or post-
processor machines, and many other variants as one of the
blocks of the decomposition. Each of these methods assumes
that there is some kind of elementary component machine
that can be realized more inexpensively, can be realized in a
regular structure, or has a small delay. Finally, methods have
been developed to decompose a machine into several small
machines, each of them realizable in some technology (for in-
stance, as a logic block of a CPLD or a FPGA, or in a single
PAL integrated circuit).
In addition to formal decomposition methods that operate
on state tables, there are many informal and specialized de-
composition methods that are either done by hand by the de-
signer or are built into VHDL compilers or other high-level
synthesis tools. For instance, many tools can recognize regis-
ters, counters, adders, or shifters in a high-level specification
and synthesize them separately using special methods. Most
of the existing approaches for sequential logic design assume
the use of specific types of flip-flops, typically D flip-flops.
There are, however, methods and algorithms, especially used
in EPLD environments, that take into account other types of
flip-flops, such as JK, RS, and T.
To directly convert and decompose high-level descriptions
such as Petri nets, SpecCharts, or regular expressions to net-
lists of flip-flops and logic gates, or registers/shifters and logic
equations, special methods have been also created, but are
not yet very popular in commercial systems.
If a sequential circuit does not meet the requirements,
there are postprocessing steps such as retiming, re-encoding,
re-synthesis, speed-up, etc. (16,17), which can improve the de-
sign to achieve a higher performance. For instance, retiming
allows shifting of registers through logic without changing its
functionality but affecting the timing. This method is applied
at many description levels of synchronous circuits: behavioral,
register-transfer, architectural, logic, etc. It is most often used
as a structural transformation on the gate-level, where it can
be used for cycle-time minimization or for register minimiza-
tion under cycle-time constraints (18). It has also been used
for low power design and as a general optimization technique
in architectural and logic synthesis.
Finally, approaches have been created that combine these
different synthesis and decomposition methods, with the tech-
nology for which they are applied, such as EPLD, FPGA, PLA,
ROM, or custom design. Design methods have also been cre-
ated to realize finite state machines with RAMs, ROMs, and
content addressable memories (CAM).
MICROPROCESSOR-BASED DESIGN
A microprocessor-based design involves a design of a digital
system which contains one or more microprocessors.
What Is a Microprocessor?
A microprocessor is a general-purpose digital circuit. A typical
microprocessor consists of a data path and a control unit, as
shown in Fig. 4. The data coming from the system’s input is
manipulated in the data path and goes to the system’s output.
The data path contains registers to hold data and functional
units to perform data-processing operations. These operations
include arithmetic operations, logic operations, and data
shifting. The control unit contains a program counter, an in-
struction register, and the control logic. The control unit con-
trols the data path with regard to how to manipulate the data.
The microprocessor is operated under the control of soft-
ware. The software is stored in standard memory devices. The
software enables the same microprocessor to perform differ-
ent functions.
A computer system is a combination of hardware and soft-
ware designed for general-purpose applications. The micro-
processor is the major component of a computer. Besides the
microprocessor, a computer system hardware includes mem-
ory (RAM and ROM) and input/output devices. Memory can
be a main memory and a microcode memory. Additional cir-
cuits, contained in FPGAs or special ASICs, and designed us-
ing the previously outlined techniques, can be also incorpo-
rated.
What Is a Microprocessor-Based System?
The fundamental microprocessor-based system structure con-
tains microprocessor, memory, and input/output devices with
address, data, and control buses (24). A microprocessor-based
system is shown in Fig. 5.
The functionalities performed by a microprocessor are de-
termined by the programs. These programs, commonly called
software, are stored in the memory or off-line storage devices
(e.g., hard drives). There are different technologies used in
memory: static random-access memory (SRAM), dynamic ran-
dom-access memory (DRAM), read-only memory (ROM), elec-
Microprocessor
Control
Datapath unit
Figure 4. A simple microprocessor consisting of a datapath and a
control unit.

Microprocessor Memory
Input/output
Figure 5. A microprocessor-based system.
trically programmable read-only memory (EPROM), electri-
cally erasable programmable read-only memory (EEPROM),
and flash memory. A program stored in a read-only memory
is called a firmware.
The basic operation of all microprocessor-based systems is
the same. The program in the memory is a list of instructions.
The microprocessor reads an instruction from the memory,
executes that instruction, and then reads the next in-
struction.
Logic Design Using a Microcontroller
A microcontroller is a complete computer system on a chip.
Like the microprocessor, a microcontroller is designed to fetch
and manipulate the incoming data, and generate control sig-
nals. A microcontroller contains a microprocessor, input/out-
put (I/O) ports, timer/counter, and interrupt-handling circuit.
A typical microcontroller (e.g., 8051) contains both serial and
parallel I/O ports (3). Microcontrollers are widely used in ap-
plications like motor control, remote access, telephones and
so on. The same microcontroller (e.g., 8051), running different
software, can be used for different applications. Conse-
quently, the overall product cost of a microcontroller-based
design is much lower than an ASIC-based design.
While microcontrollers are commonly used in control appli-
cations, microprocessors are often used for applications re-
quiring large amounts of I/O, memory, or high-speed pro-
cessing. Such applications include data processing and
complex control applications. For instance, personal comput-
ers mainly perform data processing.
Hardware Software Tradeoffs
A logic function can be realized in hardware, as discussed in
the previous sections, or in software. In most cases, however,
the required functionalities are realized partially by specially
designed hardware and partially by software.
If the hardware is used more than the software, or vice
versa, the designs are referred to as a hardware-intensive de-
sign or a software-intensive design, respectively. A designer
can make a tradeoff between the hardware- and software-
intensive realizations. Performance is usually better with
hardware implementations than with software implementa-
tions for a variety of reasons. The microprocessor is a general-
purpose device, and some speed is sacrificed for generality.
Microprocessors perform tasks in sequential fashion. Logic
circuits can be designed to perform operations in parallel.
Most logic functions occur in tens of nanoseconds. A micropro-
cessor instruction execution time ranges from several hun-
dred nanoseconds to tens of microseconds.
A hardware-intensive design requires more hardware in
the system and therefore increases the production cost. The
LOGIC DESIGN 567
performance is usually higher, and the cost for software de-
velopment is reduced. Software-intensive approaches, on the
other hand, require more software development and are
slower. In return, the flexibility may be enhanced and the pro-
duction cost is reduced.
Microprocessor Selection
There are many different microprocessor product families on
the market. The number of bits processed in parallel inside
the microprocessor is a primary criterion with which to evalu-
ate the performance of a microprocessor. The low-end prod-
ucts are 4-bit or 8-bit ones. Typical microprocessors are 16 or
32 bits wide. The 64-bit products are currently entering the
market. There are two factors that should be considered in
microprocessor selection: architecture and development tools.
There are two types of microprocessor architectures: com-
plex instruction set computer (CISC) and reduced instruction
set computer (RISC). A CISC architecture has a larger in-
struction set than a RISC architecture. Besides the instruc-
tion sets, other considerations regarding architecture include
on-chip and off-chip peripherals, operating frequency, and
prices.
Development tools for microprocessor-based systems in-
clude in-circuit emulators, logic analyzers, and on-chip debug-
gers. In-circuit emulators are specially designed hardware
that emulate the microprocessor operations in the target sys-
tem. An in-circuit emulator has its own microprocessor and
its own memory. During debugging, the tasks are run on an
emulator’s microprocessor and memory. The breakpoint can
be set by the user through software to trace the system’s oper-
ations. The emulator is connected to a workstation or a PC.
Thus the user can monitor the system’s performance in real
time. Logic analyzers are devices that can monitor the logic
values of a target system. They can be used to monitor any
bus, control line, or node in the system, and they monitor the
microprocessor passively. On-chip debuggers are software
programs that can monitor a microprocessor’s on-chip debug-
ging registers.
Design Process
A microprocessor-based system can be as simple as a liquid
crystal device (LCD) controller and can be as complex as a
modern network management system. In spite of the diver-
sity in the system complexity, the design of a microprocessor-
based system always starts with a system-level specification.
After the system-level functions are clearly defined in the sys-
tem specification, the overall function is divided into different
functional blocks. The hardware/software implementation
and the selection of the components for each functional block
will be determined at this stage. At this point, the tradeoff
between hardware and software implementation and the
advantage/disadvantage of each component need to be eval-
uated.
The system design activity is typically divided into hard-
ware design and software design. Depending on the complex-
ity of interaction between hardware and software, the two de-
signs may need to be tested together in an integrated
environment. The most commonly used tool for the integrated
debugging is the in-circuit emulator, often referred to as ICE.
An in-circuit emulator can run the software in the target mi-
croprocessor and provide the capability of monitoring the in-
ternal registers. As a result, an in-circuit emulator is an effi-
568 LOGIC DESIGN
Design specification
System design
Hardware design Software design
Hardware Software coding
implemation
Hardware testing Software testing
System integration
System testing
Figure 6. The process of a microprocessor-based design.
cient tool for debugging the software in real time. It can also
interface with the hardware to provide the real application
environment. This hardware-software co-verification is in-
creasingly important in complex system design. A logic ana-
lyzer is also used to trace the signals in a real-time operation.
This signal tracing involves the data storage and manipula-
tion of the signal waveforms. Many in-circuit emulators have
this capability built into the system.
A real-time design involves processing of the events at the
speed at which the events occur. A popular example is the
display of image data coming from the network. The image
processing includes image data decompression and displaying
onto the monitor window with a specified location and dimen-
sion. A real-time design is often performance demanding and
needs to coordinate different event flows. Interrupt handling
can also be complicated. In most cases, the design contains
hardware circuit design and one or more processors. The
hardware-software co-design and/or co-verification become
imperative in a complex real-time design.
In summary, a microprocessor-based system design in-
cludes the following design activities: design specification,
system design, hardware/software tradeoffs, microprocessor
selection, other IC selection, software design and implementa-
tion, hardware design and implementation, hardware testing,
hardware/software integration, hardware and software co-
verification, and system testing. Figure 6 shows the stages of
the microprocessor-based system design process.
Comparing Microprocessor-Based Design and Hardware Design
Microprocessor-based designs have several benefits. Software
control allows easier modification and allows complex control
functions to be implemented far more simply than with other
implementations. A hardware design implementation is for-
warded to the manufacturer and needs to be fully tested. A
software implementation is more flexible than a hardware im-
plementation. It has the ability to revise the design quickly
and easily. Since the standards, specifications, and customer
requirements are evolving constantly, the flexibility is an im-
portant design consideration.
On the other hand, while hardware designs are less flexi-
ble, they usually have better performance. Furthermore, mi-
croprocessor-based designs normally require additional de-
vices, including program memory, data memory, and glue
logic. Consequently, the requirements for board space and
power consumption may be increased.
BIBLIOGRAPHY
1. P. Ashar, S. Devadas, and A. R. Newton, Sequential Logic Synthe-
sis, Boston: Kluwer, 1992.
2. R. L. Ashenhurst, The Decomposition of Switching Functions,
Proc. of the Symposium on the Theory of Switching, April 2–5,
1957, Ann. Computation Lab., Harvard University, 29, pp. 74–
116, 1959.
3. K. J. Ayala, The 8051 Microcontroller, Architecture, Program-
ming, and Applications, West Publishing Company, 1991.
4. R. K. Brayton et al., Logic Minimization Algorithms for VLSI Syn-
thesis, Boston: Kluwer, 1984.
5. R. K. Brayton et al., VIS: A System for Verification and Synthe-
sis, in Computer-Aided Verification, July 1996.
6. M. Ciesielski and J. Shen, A Unified Approach to Input-Output
Encoding for FSM State Assignment, Proc. Design Automation
Conf., 176–181, 1991.
7. H. A. Curtis, A New Approach to the Design of Switching Circuits,
Princeton, 1962.
8. R. Drechsler et al., Efficient Representation and Manipulation
of Switching Functions Based on Ordered Kronecker Functional
Decision Diagrams, Proc. of the Design Automation Conference,
San Diego, CA, June 1994, 415–419.
9. A. Ghosh, S. Devadas, and A. R. Newton, Sequential Logic Testing
and Verification, Boston: Kluwer, 1992.
10. M. J. C. Gordon and T. F. Melham (eds.), Introduction to HOL: A
theorem proving environment for higher order logic, Cambridge,
UK: Cambridge University Press, 1993.
11. G. D. Hachtel and F. Somenzi, Logic Synthesis and Verification
Algorithms, Boston: Kluwer, 1996.
12. J. Hartmanis and R. E. Stearns, Algebraic Structure Theory of Se-
quential Machines, Upper Saddle River, NJ: Prentice-Hall, 1996.
13. R. H. Katz, Contemporary Logic Design, Menlo Park, CA:
Benjamin/Cummings Publishing Company, 1994.
14. Z. Kohavi, Switching and Finite Automata Theory, New York:
McGraw-Hill, 1970.
15. E. B. Lee and M. Perkowski, Concurrent Minimization and State
Assignment of Finite State Machines, Proc. IEEE Conference on
Systems, Man and Cybernetics, Halifax, Canada, Oct. 1984, pp.
248–260.
16. C. Leiserson, F. Rose, and J. Saxe, Optimizing Synchronous Cir-
cuitry by Retiming, Third Caltech Conference on VLSI, 1983, pp.
87–116.
17. G. De Micheli, Synchronous Logic Synthesis: Algorithms for Cycle-
Time Optimization, IEEE Trans. on CAD, 10: (1), Jan. 1991, pp.
63–73.
18. G. De Micheli, Synthesis and Optimization of Digital Circuits, New
York: McGraw-Hill, 1994.
19. M. Perkowski et al., Decomposition of Multiple-Valued Relations,
Proc. ISMVL ’97, Halifax, Nova Scotia, Canada, May 1997, pp.
13–18.
20. J. P. Roth and R. M. Karp, Minimization over Boolean Graphs,
IBM Journal Res. and Develop., No. 4, pp. 227–238, April 1962.
21. T. Sasao (ed.), Logic Synthesis and Optimization, Boston: Kluwer,
1993.
 LOGIC PROGRAMMING 569

22. T. Sasao and M. Fujita, Representations of Discrete Functions, Bos-

ton: Kluwer, 1993.
23. E. M. Sentovich et al., SIS: A System for Sequential Circuit Syn-
thesis, Tech. Rep. UCB/ERL M92/41, Electronics Research Lab.,
Univ. of California, Berkeley, CA 94720, May 1992.
24. M. Slater, Microprocessor-Based Design, A Comprehensive Guide
to Effective Hardware Design, Englewood Cliffs, NJ: Prentice-
Hall, 1989.
25. M. C. Zhou, Petri Nets in Flexible and Agile Automation, Boston:
Kluwer, 1995.

NING SONG
Lattice Semiconductor Corp.
MAREK A. PERKOWSKI
Portland State University
STANLEY CHEN
Lattice Semiconductor Corp.

LOGIC DESIGN. See also NAND CIRCUITS; NOR CIR-

CUITS.
LOGIC DEVICES, PROGRAMMABLE. See PROGRAM-
MABLE LOGIC DEVICES.
LOGIC, DIODE-TRANSISTOR. See DIODE-TRANSISTOR
LOGIC.
LOGIC, EMITTER-COUPLED. See EMITTER-COUPLED
LOGIC.
LOGIC EMULATORS. See EMULATORS.
LOGIC, FORMAL. See FORMAL LOGIC.
LOGIC, FUZZY. See FUZZY LOGIC.
LOGIC GATES. See INTEGRATED INJECTION LOGIC.
LOGIC, HORN CLAUSE. See HORN CLAUSES.
LOGIC, MAGNETIC. See MAGNETIC LOGIC.
LOGIC, MAJORITY. See MAJORITY LOGIC.
LOGIC NETWORKS. See COMBINATIONAL CIRCUITS.
LOGIC OPTIMIZATION. See LOGIC SYNTHESIS.
LOGIC PROBABILISTIC. See PROBABILISTIC LOGIC.
 LOW-PASS FILTERS 619

LOW-PASS FILTERS

A low-pass filter suppresses the high-frequency components

of a signal, leaving intact the low-frequency ones. A low-pass

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.
620 LOW-PASS FILTERS

Attenuation (dB) jω

As

σ
1
–––
RC

Ap

Frequency (Hz)
f1 f2 Figure 3. Pole-zero diagram of the first-order low-pass filter.

Figure 1. Low-pass filter requirements.

Next, compute the quantity

filter specification can be expressed as shown in Fig. 1. In the
100.1 As − 1 

stopband (above f 2 Hz), the attenuation is at least As dB. In log10

kf 
2
the passband (below f 1 Hz), the attenuation is at most Ap dB.
The band from f 1 to f 2 is called the transition band. 2
2 log10
A first-order low-pass filter is shown in Fig. 2. The transfer f1
function is
Choose the order, n, of the filter to be the smallest integer not
1 smaller than the above quantity. Solve for all the left-half-
Vout (s) RC plane roots, Zis, of the equation
=
Vin (s) 1
s+ (−1)n S2n + 1 = 0
RC

The pole-zero diagram is shown in Fig. 3. The Butterworth low-pass transfer function is formed as fol-
An active second-order low-pass filter is shown in Fig. 4. lows:
The circuit is known as the Sallen and Key low-pass circuit. 
1 
The transfer function is TLP (s) = n 

i=1 (S − Zi ) s=k 1/n s/2π f
α 1

Vout (s)
=
1 R1 R2C1C2
1−α
 (1) Example. Find the Butterworth transfer function for a low-
Vin (s) 1 1 pass filter with As ⫽ 15 dB, Ap ⫽ 0.5 dB, f 1 ⫽ 1 kHz, and f 2 ⫽
s2 + + + s+
R1C1 R2C1 R2C2 R1 R2C1C2 5 kHz.

where 움 ⫽ 1 ⫹ r2 /r1. The pole-zero diagram is shown in Fig. 5.

p
k= 100.1(0.5) − 1 = 0.35
An approach to design a circuit (a low-pass filter) whose
100.1(15) − 1 
frequency response satisfies the low-pass requirements shown log10
0.352
in Fig. 1 consists of two steps: approximation of the require-  5k  = 1.72
ments by a transfer function and synthesis of the transfer 2 log10
function. 1k
There are several approximation methods, for instance,
Butterworth, Chebyshev, inverse Chebyshev, and Cauer ap- Choose n ⫽ 2. The left-half-plane roots of the equation
proximations. A transfer function obtained by one method is
different from those obtained by the others, and has different (−1)2 s2(2) + 1 = 0
properties. However, the frequency response of each of the
transfer functions satisfies the low-pass requirements. The
Butterworth approximation method is described below.
Compute the scaling factor k given by the equation below:

R1 R2
C1
k= 10 0.1 A p
−1
Vin –
+ Vout

C2
R r2
r1
+ +
Vin C Vout
– –

Figure 2. First-order low-pass filter. Figure 4. Sallen and Key low-pass circuit.
 LOW-POWER BROADCASTING 621

jω R. W. Daniels, Approximation methods for electronic filter design, New

York: McGraw-Hill, 1974.
G. Morchytz and P. Horn, Active filter design handbook, New York:
Wiley, 1981.
σ
CHIU H. CHOI
University of North Florida

Figure 5. Pole-zero diagram of the Sallen and Key low-pass filter.

are 1/ 兹2(⫺1 ⫾ j). Therefore, the Butterworth transfer func-

tion is
 
 1 

TLP (s) =  √ 

s2 + 2s + 1 s= √0.35s/2π (1000)

which simplifies to

1.128 × 108
TLP (s) =
s2 + 1.502 × 104 s + 1.128 × 108

The above calculations have all been performed before, and

the results are available in tabular and computer program
forms.

The Sallen and Key low-pass circuit can be used to realized

a second-order low-pass transfer function of the form

K
T (s) =
s2 + as + b

Compare T(s) with Eq. (1)

α 1 1 1−α 1
K= a= + + b=
R1 R2C1C2 R1C1 R2C1 R2C2 R1 R2C1C2

Since there are more unknowns than equations, one can as-
sign values to certain unknowns and then solve for the re-
maining unknowns. As an example, choose C1 ⫽ 1, C2 ⫽ 1,
움 ⫽ 2. Then

1 a
K = 2b R1 = R2 =
a b

The impedance-scaling method can be used to scale the values

of R’s and C’s into the practical ranges.
In general, a higher-order low-pass transfer function ob-
tained by Butterworth and Chebyshev approximations can be
factorized into a product of biquadratic functions and possibly
one first-order expression. Each of the biquadratic functions
can be synthesized by using the Sallen and Key or other low-
pass circuits. The first-order transfer function can be realized
by an active or passive circuit. By cascading all the biquad
and first-order circuits together, the low-pass filter is realized.

Reading List
G. Daryanani, Principles of Active Network Synthesis and Design, New
York: Wiley, 1976.
M. E. Van Valkenburg, Analog Filter Design, New York: Holt, Rine-
hart, and Winston, 1982.
MAJORITY LOGIC
Majority Logic is used to implement a majority decision
mechanism. In particular, an Majority Logic Block (MLB)
can be regarded as a black box that receives possibly dif-
ferent data values at its inputs, and gives, at its output,
the data value present on the majority of its inputs. For in-
stance, if a MLB receives the three input data “1”, “1” and
“0”, it gives the output data “1”.
MLBs are generally used as component blocks of dig-
ital electronic systems devoted to critical operations, like
control systems of nuclear plants, flight control systems of
aircrafts, speed control systems of trains, onboard control
systems of satellites, etc. The correct uninterrupted opera-
tion of these systems is mandatory because their malfunc-
tion could cause catastrophic consequences, such as loss of
human life or huge economical loss. To avoid such losses,
the system must be designed to guarantee its correct be-
havior (that is, the behavior expected in the fault-free case)
despite the occurrence of internal faults.
In fact, electronic systems are prone to faults. Faults oc-
cur during the system’s manufacturing process and during
its operation. For instance, in the presence of a high elec-
trical field, high current density within a circuit metal line
might cause the line to break. This might make the faulty
circuit provide an output datum different from the correct
one, for example, a “0” rather than a “1”. If the faulty signal,
for instance, is a signal that activates the alarm device of
a train’s speed control system when equal to “1”, it is obvi-
ous that a faulty “0” may cause the whole system to become
ineffective with possible catastrophic consequences.
Unfortunately, faults of this kind (and faults of a dif-
ferent kind) might occur within a digital electronic sys-
tem. The likelihood of their occurrence is reduced by using
proper electronic components, but ensuring that they never
occur is impractical.
Hence, if the correct operation of a system is crucially
important, some precautions must be taken to avoid the
catastrophic consequences that faults might produce. The
techniques used to reach this goal are generally called
fault-tolerant techniques.
In particular, to guarantee that a system tolerates its
possible internal faults (that is, to ensure that no system
malfunction occurs because of such faults), redundancy is
used. As an example, to guarantee that a train’s speed con-
trol system tolerates faults in the circuit activating the
alarm device, redundant copies of such a circuit are used.
If these redundant copies are properly isolated from one
another, a single fault during the system operation affects
only one copy, hence only this copy provides incorrect (or
faulty) output data, whereas the other copy (or copies) gives
correct output data.
However, it should be obvious that redundancy alone is
not sufficient to ensure that a system tolerates its possi-
ble internal faults. To reach this goal, we need some deci-
sion criterion that allows us to determine which data value,
among those present at the output of the redundant copies,
can be regarded as correct, and which one(s) as incorrect.
This decision criterion normally is the majority criterion,
implemented by an MLB.
J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright © 2007 John Wiley & Sons, Inc.
Of course, three is the minimum number of copies of the
same circuit (or, more generally, module) that we must have
to allow the MLB’s selection of the majority data value.
The use of MLBs and redundant copies of the same mod-
ule characterize the fault-tolerant N-Modular Redundancy
(NMR) systems where, as previously introduced, N must be
≥ 3. The idea to use N-Modular Redundancy and majority
logic blocks (also called majority “voting blocks”, or “vot-
ers”) to achieve fault-tolerance was first introduced in (2)
and has been adopted for several critical applications, such
as space exploration missions and nuclear reactor protec-
tion (3, 4).
In the particular case where N = 3, these systems are
called Triple Modular Redundancy (TMR) systems. Hence
a TMR system consists of: (1) three copies of the original,
non fault-tolerant module, that concurrently process the
same information (where a module is simply a circuit, a
gate, or even a microprocessor, depending on system’s re-
lated choices), (2) n MLBs (where n is the number of out-
puts of the replicated module), each comparing bit-by-bit
the corresponding outputs of the three replicated modules,
and producing at its output the majority data value among
those at its inputs (Figure 1). Moreover, suitable techniques
are generally adopted at the system level to avoid exhaust-
ing all of the system’s redundancy as modules get succes-
sively faulty.
Obviously, MLBs play a critical role in the fault-tolerant
systems described. In fact, the correct operation of the
whole system is compromised if an MLB becomes faulty.
For instance, it is obvious that, if the output of an MLB is
affected by a stuck-at “1” fault (for instance, because of a
short between an output line and the circuit power supply),
the faulty MLB always gives an output “1”, regardless of
the data values at its inputs (that is, also when the data
value on the majority of its inputs is a “0”). Similar prob-
lems may occur because of different kinds of faults possibly
affecting the input (5), internal and output lines/nodes of
a MLB.
In the remainder of this article we consider the problem
of designing MLBs for TMR and NMR systems and the case
of faulty MLBs.
MAJORITY LOGIC FOR TRIPLE MODULAR
REDUNDANCY SYSTEMS
As previously introduced, an MLB can be regarded as a
black box that must produce at its output the datum value
present on the majority of its inputs. To distinguish such
a majority datum value, an MLB must have at least three
inputs. When this is the case, the MLB must satisfy the
truth table shown in Table 1, where Z denotes the output
of the MLB, and X = (X1 , X2 , X3 ) is the MLB input vector.
Hence, the MLB can be implemented (at the logic level)
by a two-level NAND-NAND (Figure 2) or NOR-NOR (Fig-
ure 3) circuit. Equivalently, a two level AND-OR, or OR-
AND implementation can be considered (6).
Of course, the electrical level implementations of these
MLBs depend on the technology adopted. As a significant
example, if the Complementary MOS (CMOS) technology
is used, the NAND-NAND majority logic block can be im-
2 Majority Logic

Figure 1. Representation of a Triple

Modular Redundancy (TMR) system.

Figure 2. NAND-NAND logical implementation of a majority logic

block for a TMR system.

Figure 3. NOR–NOR logical implementation of a majority logic

block for a TMR system.

plemented by means of the circuit shown in Figure 4. Al-
ternatively, the circuit shown in Figure 5, for instance, can
be used (6). Other possible electrical implementations of
MLBs for TMR systems (Figure 6 and Figure 7) were pro-
posed in (7, 8). Different from the conventional MLB re-
alizations considered up to now, these MLBs produce an
output error message in case of internal faults that make
them give an incorrect majority output datum value. The
behavior of these circuits is described later while dealing
with the problems due to faults affecting MLBs.
 Majority Logic 3

Figure 4. Example 1 of a possible CMOS implemen-

tation of the NAND–NAND majority logic block in Fig-
ure 2.

Table 1. Truth Table of a Three-Input Majority Logic Block MAJORITY LOGIC FOR N MODULAR REDUNDANCY
X1 X2 X3 Z SYSTEMS
000 0
001 0 Tto tolerate E errors in the vector X = (X1 , X2 ,. . . , XN ) given
010 0 to the input of an MLB of an NMR system, N and E must
011 1 satisfy the following equation (9):
100 0
101 1 N ≥ 2 · E + 1.
110 1
111 1 In fact, when this is the case, the number of erroneous bits
E is smaller than the number of correct bits (N − E).
Barbour and Wojcik (6) added an upper bound to the
value of N of an NMR system tolerating E errors. In par-
As regards the number of errors in X tolerated by a gen- ticular, they transformed Eq. (1) into:
eral TMR system, it is evident that, if only one of the MLB
input data is incorrect (that is either X1 , X2 , or X3 ), the MLB 2 · E + 1 ≤ N ≤ (E + 1)2 .
produces the correct output datum value. Instead, if two Moreover, they proposed possible two-level implementa-
input data are incorrect, the MLB produces the incorrect tions of MLBs for NMR systems, whose values of N and E
output datum value. Hence, a TMR system tolerates only a satisfy Eq. (2). These are the implementations most widely
single error on the corresponding outputs of the replicated used for MLBs of general NMR systems.
modules. If a higher number of errors must be tolerated (be- In particular, the first level of the proposed MLBs con-
cause of system level requirements) an NMR system with N
n MLBs (where n is the number of outputs of the replicated sists of ( ) AND (or OR, or NAND, or NOR) gates, where
K
module), each with N inputs (N > 3), must be used. K is a parameter [called a “grouping parameter” (6)] that
4 Majority Logic

Figure 5. Example 2 of a possible CMOS implementation of the NAND-NAND majority logic block in Figure 2.

Figure 6. Electrical implementation of the majority logic block

giving an output error message in case of internal faults affecting
its correct operation proposed in (7).

must satisfy the following condition: gates are used at the first level.
As an example, the general NAND-NAND implementa-
E + 1 ≤ K ≤ N − E. tion of such an MLB, with generic “grouping parameter” K,
is shown in Figure 8. We can easily verify that, if N = 3 and
N K = 2, this implementation equals that reported in Figure
The inputs to these first level gates are the ( ) combina-
K 2.
tions of K elements out of the N elements of the MLB input
vector X. The derived electrical level implementations of these
The second level of the proposed MLBs consists of a MLBs are straightforward.
simple OR (or AND, or NAND, or NOR) gate, depending An alternative implementation of MLBs for NMR sys-
on whether AND (or OR, or NAND, or NOR, respectively) tems was proposed in (10). These MLBs (Figure 9) are suit-

able for NMR dynamic systems, that is, in systems where,
differing from the conventional cases considered until now,
the number of processed replicated modules (hence the
number of inputs of the MLBs) can be dynamically changed
during the system’s operation.
PROBLEMS IN CASE OF FAULTY MAJORITY LOGIC
As previously mentioned, if the MLB of a TMR (NMR) sys-
tem becomes faulty, it might produce at its output an in-
correct majority datum value, hence making the adoption
of the TMR (NMR) fault-tolerant technique useless.
To deal with this problem, MLBs can be themselves
replicated (11), as schematically shown in Figure 10 for
Majority Logic 5
Figure 7. Electrical implementation of
the majority logic block giving an output
error message in case of internal faults af-
fecting its correct operation proposed in (8).
Figure 8. NAND-NAND logical implementation of a ma-
jority logic block for an NMR system with “grouping pa-
rameter” = K.
a TMR system. Note that in this and in the following fig-
ures, we use a common symbol to represent n MLBs, and
the n outputs of the replicated modules, respectively. It is
obvious that, if this scheme is adopted, faults affecting one
of the replicated MLBs that make it produce incorrect out-
put data can be tolerated. However, similar to the case of
replicated modules only, in this case the problem of dis-
tinguishing the datum value provided by the majority of
the replicated MLBs also arises. Of course, if other MLBs
(receiving the outputs of the replicated MLBs) are used to
fulfill this purpose, the problem discussed here is simply
translated to these final MLBs.
An alternative strategy for dealing with this problem is
to renounce the fault-tolerance requirement of the MLBs
6 Majority Logic

To reduce these costs in TMR systems, the MLB intro-

duced in (7) or (8) can be adopted.
The electrical structure of the MLB in (7) is shown in
Figure 6, where CKS and CKS denote a periodic signal
whose period is T and an opposite waveform, respectively.
This MLB provides an output error message when in-
ternal faults occur that make it give an output incorrect
majority datum value. This behavior is guaranteed for all
MLB node stuck-at, transistor stuck-on, transistor stuck-
open and resistive bridging faults (whose values of the con-
necting resistance are in the range 0
to 6 k
).
In the fault-free case, this MLB gives as its output: (1)
a signal equal to CKS if the majority of its input signals is
equal to “0”; (2) a signal equal to CKS if the majority of its
input signals is equal to “1” (Table 2). Hence, in the fault-
free case, this MLB gives at its output a signal assuming
both high and low logic values within the same period T. In
particular, the logic value produced when CKS = 1 is equal
to the majority datum value (MV in Table 2) among those
given to its input during such a period T.
Figure 9. Majority logic block suitable to NMR dynamic systems
Table 2. Truth Table of the Majority Logic Block in (6), and Corresponding
introduced in (11).
Majority Datum Value

X1 X2 X3 Z MV
and to require only that the MLBs give an output error 000 CKS 0
message in case of internal faults making them produce 001 CKS 0
incorrect output data. Such an error message can be ex- 010 CKS 0
ploited at the system level to avoid the dangerous conse- 011 CKS 1
quences possibly resulting from incorrect MLB operation. 100 CKS 0
For instance, if an error message is received by one of the 101 CKS 1
MLBs of a train’s speed control system, a system level re- 110 CKS 1
111 CKS 1
covery procedure can be automatically started, eventually
making the train stop.
MLBs of this kind can be found in (1–8).
In particular, in (1), the MLBs are duplicated (Figure Instead, in case of an internal fault of the kind previ-
11), and their outputs are given to the inputs of a compara- ously reported, either the MLB is not affected by the fault
tor that verifies whether or not such outputs are equal to (that is it continues providing the correct majority output
one another. In the case of a disagreement, the compara- data), or it produces an output error message (in partic-
tor gives an output error message. It is obvious that this ular a signal that does not change logic value within T).
strategy guarantees that, in case of faults affecting an MLB If a fault does not affect the MLB and following internal
that make it produce erroneous majority output data, the faults occur, either the MLB is not affected by these in-
comparator gives an output error message. ternal faults or it provides an output error message. This
However, compared with the case where single MLBs condition holds for all possible sequences of internal faults
are used, this solution implies an inevitable increase of the under the general assumptions that internal faults occur
area overhead and power consumption costs of the fault- one at a time during the operation of an integrated circuit
tolerant system. and that the time interval elapsing between two succeed-

Figure 10. Triplicated MLB scheme proposed in

(12). In priciple, triplication of the MLB allows faults
that could possibly affect one of the replicated MLBs
to be tolerated. In practice, problems arise in correctly
discriminating the value given by the majority of the
replicated MLBs.
 Majority Logic 7

Figure 11. Duplicated MLB scheme presented in (1). Faults affecting one of the duplicated MLBs
can not be tolerated, but can be detected by the output comparator.

Figure 12. Detecting scheme possibly adopted to avoid the exhaustion of a TMR system redun-
dancy. The detectors (DTRi , i = 1, 2, 3) reveal the disagreement between the outputs of the replicated
modules and the majority output data given by the MLBs.

ing faults is long enough to allow the fault-free modules to
produce both high and low output data values.
The presence of an error message at the output of this
MLB can be simply revealed. For instance a flip-flop sam-
pling the MLB output on both the CKS rising and falling
edges (12) can be used.
This MLB implementation can also be extended to NMR
systems (13). In this case, compared with the electrical
structure shown in Figure 6: (1) the number of parallel pull-
3 N
up/pull-down branches changes from ( ) to ( ), (2)
2 (N + 1)/2
each branch consists of (N + 1)/2 series transistors, rather
than of 2. Obviously these conditions may limit the maxi-
mal value of N for which this implementation can be con-
veniently used.
The electrical structure of the MLB in (8) is shown in
Figure 11, where CKS and CKS denote a periodic signal
with period T, and an opposite waveform, respectively.
Similarly to the MLB in (7), also this MLB provides
an output error message in case of the occurrence of in-
ternal faults making it give an output incorrect majority
data value. This behavior is guaranteed for all MLB’s node
stuck-at, transistor stuck-on, transistor stuck-open and re-
sistive bridging faults (with values of the connecting re-
sistance in the range 0
to 6 k
), but for the bridging
fault between its two outputs, which should consequently
be avoided, for instance by proper design of the circuit lay-
out.
In the fault-free case, this MLB gives as its output: (1)
(Z1i , Z2i ) = (1, 1), if the majority of its input signals is equal
to “0”; (2) (Z1i , Z2i ) = (0, 0), if the majority of its input signals
is equal to “1”.
In case of internal faults of the kind previously reported,
this MLB behaves as the MLB in (7), with the difference
that the provided error message is an output word with
Z1i = Z2i , rather than a a signal that does not change logic
value within T (as for the MLB in (7)).
Compared to the MLB in (7), the MLB in (8) features
the advantage of being faster (offering a reduction of the
input/output propagation delay of approximately the 80%),
thus being more suitable to high speed, high reliability sys-
tems, while requiring comparable power consumption. This
8 Majority Logic

is achieved at the cost of a small increase in area overhead
(14). Additionally, as proven in (14), the MLB in (8) contin-
ues to work properly (i.e., either it continues to provide the
correct majority vote, or it produces an output error mes-
sage) even when affected by high leakage currents, which
are expected to become a major concern for dynamic CMOS
circuits.
As previously introduced, suitable techniques must be
also adopted to avoid exhausting the TMR (NMR) system’s
redundancy because modules become successively faulty.
To fulfill this purpose, detectors that reveal the disagree-
ment between the outputs of the MLBs and of the repli-
cated modules can be used (15), as shown schematically in
Figure 11. A possible electrical implementation of detec-
tors of this kind, suitable for use together with the MLBs
described, can be found in (13).
Voters operating on a word basis, rather than the tradi-
tional bit-by-bit basis, have also been proposed (16), which
are able to provide an output error message, should the
words produced by the three replicated modules of a TMR
system differ from each other.
Finally, several critical applications require that the
MLBs of the used TMR (NMR) systems provide “fail-safe”
outputs; that is, signals whose value is either correct or
safe (where, as an example, the red color is the “safe” value
for traffic control lights). Possible implementations of this
kind of MLBs can be found in (17).
Arrays, IEEE Trans. Circuits Syst. I, Fundam. Theory Appl.,
vol.43,pp. 143–152,February 1996.
11. P. K. Lala, Fault Tolerant and Fault Testable Hardware Design,
Englewood Cliffs, NJ: Prentice-Hall International, 1985.
12. M. Afghahi and J. Yuan, Double edge triggered D flip-flop for
high speed CMOS circuits, IEEE J. of Solid State Circuit,
vol.SC-26,pp. 1168–1170,August 1991.
13. C. Metra, M. Favalli, and B. Riccò, On-Line Self-Testing Voting
and Detecting Schemes for TMR Systems, J. of Microelectronic
Systems Integration, vol.5, no. 4,pp. 261–273, 1997.
14. J.-M. Cazeaux, D. Rossi, C. Metra, Self-Checking Voter for
High Speed TMR Systems, J. of Electronic Testing: Theory and
Applications, pp. 377–389, 2005.
15. N. Gaitanis, The Design of Totally Self-Checking TMR
Fault-Tolerant Systems, IEEE Trans. Comput., vol.37,pp.
1450–1454,November 1988.
16. S. Mitra, E. J. McCluskey, Word-Voter: A New Voter Design for
Triple Modular Redundant Systems, IEEE Proc. of the 18th
IEEE VLSI Test Symposium,pp. 465–470, 2000.
17. M. Nicolaidis, Fail-Safe Interfaces for VLSI: Theoretical Foun-
dations and Implementation, IEEE Trans. Comput., vol.47,pp.
62–77,January 1988.
CECILIA METRA
D.E.I.S. University of Bologna,
Viale Risorgimento 2,
Bologna, Italy

BIBLIOGRAPHY

1. K. G. Shin and H. Kim, A Time Redundancy Approach to TMR

Failures Using Fault-State Likelihoods, IEEE Trans. Comput.,
vol.43,pp. 1151–1162,October 1994.
2. J. V. Neumann, Probabilistic logics and the synthesis of reli-
able organisms from unreliable components, Automata Stud-
ies, Ann. of Math. Studies, no. 34,pp. 43–98, 1956.
3. C. E. Stroud and A. E. Barbour, Testability and Test Gener-
ation for Majority Voting Fault-Tolerant Circuits, J. of Elec-
tronic Testing: Theory and Applications, Vol.4,pp. 201–214,
1993.
4. D. Audet, N. Gagnon, and Y. Savaria, Quantitative Compar-
isons of TMR Implementations in a Multiprocessor System,
in Proc. of 2nd IEEE Int. On-Line Testing Work.,pp. 196–199,
1996.
5. M. Favalli, and C. Metra, TMR Voting in the Presence of
Crosstalk Faults at the Voter Inputs, IEEE Trans. on Relia-
bility, pp. 342–348,September 2004.
6. A. E. Barbour and A. S. Wojcik, A General, Constructive Ap-
proach to Fault-Tolerant Design Using Redundancy, IEEE
Trans. Comput., pp. 15–29,January 1989.
7. C. Metra, M. Favalli, and B. Riccò, Compact and Low Power
Self-Checking Voting Scheme, in Proc. of IEEE Int. Symp.
on Defect and Fault Tolerance in VLSI Systems,pp. 137–145,
1997.
8. J.-M. Cazeaux, D. Rossi, C. Metra, New High Speed CMOS
Self-Checking Voter, IEEE Proc. of the 10th IEEE Interna-
tional On-Line Testing Symposium,pp. 58–63, 2004.
9. W. H. Pierce, Failure-Tolerant Computer Design, New York:
Academic, 1965.
10. N.-E. Belabbes, A. J. Guterman, and Y. Savaria, Ratioed Voter
Circuit for Testing and Fault-Tolerance in VLSI Processing
410 MATCHED FILTERS

MATCHED FILTERS rameter t. The corresponding output signal and noise

are so(t) and no(t), respectively.
The history of the matched filter can be traced back to more 2. The system is linear and time invariant.
than half a century ago. In 1940s, due to World War II, radar 3. The criterion of optimization is to maximize the output
became a very important detecting device. To enhance the signal-to-noise power ratio. Since noise no(t) is random,
performance of radar, D. O. North proposed an optimum filter its mean squared value E兵no2(t)其 is used as the output
for picking up signal in the case of white-noise interference noise power.
(1). A little bit later, this technique was called matched filter
by Van Vleck and Middleton (2). Dwork (3) and George (4)
Mathematically, this criterion can be written as
also pursued similar work. The filter has a frequency re-
sponse function given by the conjugate of the Fourier trans- s2o (t)
form of a received pulse divided by the spectral density of SNRo = = maximum (1)
E{n2o (t)}
noise. However, the Dwork–George filter is only optimum for
the case of unlimited observation time. It is not optimum if
observations are restricted to a finite time interval. In 1952, at a given time t. The form of the matched filter can be de-
Zadeh and Ragazzini published the work‘‘Optimum filters for rived by finding the linear time-invariant system impulse re-
the detection of signals in noise’’ (5), where they described a sponse function h(t) that achieves the maximization of Eq. (1).
causal filter for maximizing the signal-to-noise ratio (SNR) The mathematical derivation process can be described as
with respect to noise with an arbitrary spectrum for the case follows.
of unlimited observation time, and second for the case of a Since the system is assumed to be linear and time invari-
finite observation interval. Since then, extensive works on ant, the relationship between input signal si(t) and output sig-
matched filters were done in 1950s. A thorough tutorial re- nal so(t) could be written as
view paper called ‘‘An introduction to matched filters’’ (6) was  t
given by Turin. so (t) = si (τ )h(t − τ ) dτ (2)
In the 1960s, due to rapid developments of digital electron- −∞
ics and digital computers, the digital matched filter has ap-
peared (7–9). Turin gave another very useful tutorial paper Similarly, the relationship between input noise ni(t) and out-
in 1976, entitled ‘‘An introduction to digital matched filters’’ put noise no(t) could also be expressed as
(10), in which the class of noncoherent digital matched filters  t
that were matched to AM signals was analyzed. no (t) = ni (τ )h(t − τ ) dτ (3)
At this time, matched filters have become a standard tech- −∞
nique for optimal detection of signals embedded in steady-
state random Gaussian noise. The theory of matched filter Substituting Eqs. (2) and (3) into Eq. (1), the output power
can be found in many textbooks (11–13). SNR can be shown to be
In this article, we will briefly discuss the theory and appli-  2
cation of matched filters. We will start with a continuous in-  t 
 si (τ )h(t − τ ) dτ 
put signal case. Then, we will look at the discrete input signal 
−∞
case. Finally, we will provide some major applications of SNRo =  t  t (4)
matched filters. Rn (τ , σ )h(t − τ )h(t − σ ) dτ dσ
−∞ −∞

THE MATCHED FILTER FOR CONTINUOUS-TIME where Rn(␶, ␴) is the autocorrelation function of the input
INPUT SIGNALS noise ni(t) and is given by

As mentioned previously, the matched filter is a linear filter Rn (τ , σ ) = E{ni (τ )no (σ )} (5)
that minimizes the effect of noise while maximizing the sig-
nal. Thus, a maximal SNR can be achieved in the output. A Now the unknown function h(t) can be found by maximizing
general block diagram of matched-filter system is described Eq. (4). To achieve this goal from Eqs. (4) and (5), one can see
in Fig. 1. To obtain the matched filter, the following condi- that the optimum h(t) (i.e., the matched-filter case) will de-
tions and restrictions are required in the system: pend on the noise covariance Rn(␶, ␴). Since h(t) is required to
be time invariance [i.e., h(t ⫺ ␶) instead of h(t, ␶)], the noise
at least has to be wide-sense stationary [i.e., Rn(t, ␶) ⫽ Rn(t ⫺
1. The input signal consists of a known signal si(t) and an
␶)]. To obtain the optimum filter, based on the linear system
additive random noise process ni(t) with continuous pa-
theory (13), Eq. (4) can be rewritten as
 ∞ 2
 
 H( f )S( f )e df 
iωt 0
Input Output 
si(t) + ni(t) so(t) + no(t) SNRo = −∞∞ (6)
Matched filter
h(t) |H( f )|2 Pn ( f ) df
−∞

Figure 1. The block diagram of the matched filter in continuous where H( f) ⫽ F [h(t)] is the Fourier transform of the impulse
time. response function h(t) (i.e., the transfer function of the sys-

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.
 MATCHED FILTERS 411

tem), S( f) ⫽ F [s(t)] is the Fourier transform of the known where C is an arbitrary real positive constant, t0 is the time
input signal s(t), 웆 ⫽ 2앟f is angular frequency, to is the sam- of the peak signal output. This last result is one of the reasons
pling time when SNRo is evaluated, and Pn( f) is the noise why h(t) is called a matched filter since the impulse response
power spectrum density function. To find the particular H( f) is ‘‘matched’’ to the input signal in the white-noise case.
that maximizes SNRo, we can use the well-known Schwarz Based on the preceding discussion, the matched filter theo-
inequality, which is rem can be summarized as follows: The matched filter is the
 2  linear filter that maximizes the output signal-to-noise power

 ∞  ∞ ∞
ratio and has a transfer function given by Eq. (12).
 A( f )B( f ) d f  ≤ |A( f )|2 df |B( f )|2 df (7)
 In the previous discussion, the problem of the physical re-
−∞ −∞ −∞
alizability is ignored. To make this issue easier, we will start
where A( f) and B( f) may be complex functions of the real vari- with the white-noise case. In this case, the matched filter is
able f. Furthermore, equality is obtained only when physically realizable if its impulse response vanishes for neg-
ative time. In terms of Eq. (15), this condition becomes
A( f ) = kB∗ ( f ) (8) 
0, t<0
h(t) = (16)
where k is any arbitrary constant and B*( f) is the complex si (t0 − t), t ≥ 0
conjugate of B( f). By using the Schwarz inequality to replace
the numerator on the right-hand side of Eq. (6) and letting where t0 indicates the filter delay, or the time between when
A( f) ⫽ H( f)兹Pn( f) and B( f) ⫽ S( f)ei웆t0 / 兹Pn( f), Eq. (6) becomes the filter begins receiving the input signal and when the max-
 ∞  ∞ imum response occurs. Equation 16 also implies that s(t) ⫽ 0,
|S( f )|2
|H( f )|2 Pn ( f ) df df t ⬎ t0, i.e., the filter delay must be greater than the duration
−∞ Pn ( f )
SNRo ≤ −∞  ∞ (9) of the input signal. As an example, let us consider the follow-
|H( f )|2 Pn ( f ) df ing signal corrupted by additive white noise. The known input
−∞ signal has the form

In addition, because Pn( f) is a non-negative real function, Eq. Bebt , t < 0, B, b > 0
(9) can be further simplified into si (t) = (17)
0, t≥0
 ∞
|S( f )|2
SNRo ≤ df (10) Substituting Eq. (17) into Eq. (16), the impulse response of
−∞ Pn ( f )
matched filter h(t) is
The maximum SNRo is achieved when H( f) is chosen such  b(t −t )
that equality is attained. This occurs when A( f) ⫽ kB*( f), that Be 0 , t ≥ t0
h(t) = (18)
is, 0, t < t0

√ ∗
kS ( f )e−iωt 0 The physical realizability requirement can be simply satisfied
H( f ) Pn ( f ) = √ (11)
Pn ( f ) by letting t0 ⱖ 0. The simplest choice is t0 ⫽ 0 so that h(t) has
a very simple form
Based on Eq. (11), the transfer function of the matched filter  −bt
H( f) can be derived as Be , t ≥ 0
h(t) = (19)
0, t<0
S∗ ( f ) −iωt
H( f ) = k e 0 (12)
Pn ( f )
The output signal so(t) of the system can be obtained by sub-
stituting Eqs. (17) and (19) into Eq. (2). The calculated result
The corresponding impulse response function h(t) can be eas-
of so(t) is
ily obtained by taking the inverse Fourier transform of Eq.
(12), that is, 

 B2 bt
 ∞  ∞ 
 2b e , t < 0
S∗ ( f ) iw(t−t ) so (t) = (20)
h(t) = H( f )eiωt df = k e 0 df (13) 
−∞ −∞ Pn ( f ) 
 B2 −bt
 e , t>0
2b
In the matched-filter case, the output SNRo is simply ex-
pressed as To give an intuitive feeling about the results above, Figs.
 2(a)–2(c) illustrate the input signal si(t), matched filter h(t),
∞
|S( f )|2 and output signal so(t). From Fig. 2(c), indeed, one can get the
max{SNRo } = df (14)
−∞ Pn ( f ) maximum signal at time t ⫽ t0 ⫽ 0. Note that, in Fig. 2, we
have assumed the following parameters: B ⫽ b ⫽ 1. The phys-
For the case of white noise, the Pn( f) ⫽ N0 /2 becomes a con- ical implementation of this simple matched filter can be
stant. Substituting this constant into Eq. (13), the impulse achieved by using a simple RC circuit as illustrated in Fig. 3,
response of the matched filter has a very simple form in which the time constant of the RC circuit is RC ⫽ 1.
In many real cases, the input noise may not be white noise
h(t) = Csi (t0 − t), (15) and the designed matched filter may be physically unrealiza-
412 MATCHED FILTERS

ble. Now, let us look at another example with color noise (11). Input R Output
We assume that the input signal si(t) has a form of
 si(t) + ni(t) C so(t) + no(t)
e−t/2 − e−3t/2 , t > 0
si (t) = (21)
0, t<0 Figure 3. Implementation of the discussed example in text using a
RC circuit. This figure shows that the continuous time matched filter
and the input noise is wide-sense stationary with power spec- can be physically implemented by using a simple RC circuit.
tral density

4
Pn ( f ) = (22) input signal can be shown to be
1 + 4(2π f )2
4
To obtain the matched filter, first, we take the Fourier trans- Si (2πf ) = (23)
(1 + i4πf )(3 + i4πf )
form of input signal si(t). Based on Eq. (21), the spectrum of
Substituting Eqs. (22) and (23) into Eq. (12), the transfer
function of matched filter H( f) can be derived as
Input signal
S∗ ( f ) −iωt
H( f ) = k e 0
1 Pn ( f )
(24)
0.8 1 + i4πf −iωt
=k e 0
3 − i4πf
Si (t)

0.6

0.4 To simplify the expression, we let the arbitrary constant

k ⫽ 1 for the later derivations. By taking the inverse Fourier
0.2
transform of Eq. (24), the impulse response of the matched
filter is
–4 –2 0 2 4
t
h(t) = −δ(t − t0 ) + 2e(t−t 0 )3/2 u(t0 − t) (25)
(a)

where u(t) is the unit step function. Note that this filter is not
Matched filter
physically realizable because it has a nonzero value for t ⬍
0. To solve this problem, one method is to take a realizable
1
approximation by letting h(t) ⫽ 0 for t ⬍ 0. In this case, the
0.8 approximated matched filter ha(t) can be expressed as
h (t)

0.6 ha (t) = h(t)u(t)

(26)
0.4 = −δ(t − t0 ) + 2e(t−t 0 )3/2 u(t0 − t)u(t)
0.2
Then, the output spectrum So( f) of the output signal so(t) due
–4 –2 0 2 4 to this approximated matched filter is
t

(b) So ( f ) = Si ( f )Ha ( f ) (27)

Output signal
where Ha( f) is the Fourier transform of ha(t). Again, by taking
the inverse Fourier transform of Eq. (27), the output signal
so(t) can be derived as
1

0.8 so (t) = − e−3t 0 /2 e−t/2 u(t) + 23 e−3(t 0 +t )/2 u(t)

(28)
So (t)

0.6 − 13 e−3(t 0 −t )/2 u(−t) + 13 e−3(t 0 −t )/2

0.4
Again, to have an intuitive feeling about this example, Fig. 4
0.2 illustrates the input signal si(t), the ideal physically unrealiz-
able matched filter h(t), approximated realizable matched fil-
–4 –2 0 2 4 ter ha(t), and the output signal so(t) obtained with the approxi-
t
mated filter.
(c) For the purpose of convenience, we assume that t0 ⫽ 1 for
Figure 2. A simple matched-filter example for white noise and con- these plots. From Fig. 4(d), one can see that, indeed, the out-
tinuous time. (a) Input signal. (b) Matched filter. (c) Output signal. put signal has a maximum value at t ⫽ t0 ⫽ 1. However, there
This figure provides an intuitive feeling about using matched filter is no guarantee that this approximated filter is the optimum
for continuous time signal processing. filter. In fact, it is shown that, a better output SNR can be
 MATCHED FILTERS 413

Input signal achieved for this problem if the prewhitening technique is em-
ployed for the signal detection (11).
1 Before the end of this section, we want to point out that,
0.8 in practical terms, it is impossible to design an optimal
matched filter for any signal which has an infinite time dura-
Si(t)

0.6 tion because it requires infinite delay time. However, the

0.4 above examples are very fast exponential decaying signal, for
0.2 which one can make the delay time long enough so that opti-
mality can be approached to any desired degree. In other
–4 –2 0 2 4 words, the practically ‘‘realizable’’ matched filter only exists
t
for a time limited function. From this point of view, mathe-
(a)
matically speaking, the above two examples both have infinite
time duration. Thus, even for the second example, it becomes
Ideal matched filter unrealizable. However, since there are extremely fast expo-
3
2
nentially decaying signals, optimality can be achieved to any
1 desired degree. In this sense, example 2 can be treated as
0 ‘‘realizable’’ matched filter. Finally, since t0 represents the de-
h(t)

–1 lay time of the filter in the above examples, in practice, it

–2 must be selected longer than the time duration of the target
–3 signal. For the sole purpose of simplicity, in the above exam-
–4 ples, the simple values (that are not strict in the mathemati-
–4 –2 0 2 4 cal sense) of t0 are selected.
t
(b)
THE MATCHED FILTER FOR DISCRETE-TIME INPUT SIGNALS

Approximated matched filter In recent years, with rapid developments of the digital com-
3 puters, digital signal processing becomes more and more pow-
2 erful. Some major advantages of using digital signals as com-
1 pared to their analog forms are the high accuracy, high
0 flexibility, and high robustness. Right now, the matched filter
ha(t)

–1 can be easily implemented with the digital computer in real

–2 time. To implement the filter with digital computer, one has
–3
to deal with the discrete signal instead of continuous signal.
–4
In this case, for the same linear time invariant system as de-
–4 –2 0 2 4 scribed in Fig. 1, the relationship between the output signal
t so(t) and input signal si(t) has changed from the continuous-
(c) time form Eq. (2) to the following discrete time form (11):


j
Output signal by ha(t) filter so j = h j−k sik (29)
1
k=−∞
0.8
where sik represents the input signal at time k (k ⫽ 0, ⫾1, ⫾2,
0.6 . . .), hk is the discrete impulse response function of the lin-
So(t)

0.4 ear, time-invariant matched filter, and soj is the corresponding

discrete output signal at time j. In other words, the integra-
0.2 tion in Eq. (2) has been replaced by the summation in Eq.
(29). Similarly, in the discrete-time case, the Eq. (3) is rewrit-
–4 –2 0 2 4 ten as
t
(d) 
j
no j = h j−k nik (30)
Figure 4. Example of a matched filter with color noise for a continu- k=−∞
ous-time signal. (a) Input signal. (b) Ideal matched filter. (c) Approxi-
mated matched filter. (d) Output signal with approximated matched Again, our objective is to find the optimum form of matched
filter. This figure illustrates how to deal with color noise with filter so that the output signal-to-noise power ratio will be
matched filter.
maximum at some time q. Mathematically, it can be written
as

s2oq
SNRo = = maximum (31)
E{n2oq }
414 MATCHED FILTERS

To find hk, we let maximim SNR, symbolized as SNRomax, equal The input noise is additive white noise with autocorrelation
a constant 1/움. Since SNRomax represents the maximum power function
ratio, it has to be larger than 0, i.e., 움 ⬎ 0. Substituting this 
assumption into Eq. (31), one can obtain  No
= 1, k = 0
Rn (k) = 2 (41)
s2oq 1 0, k=
0
SNRo = ≤ SNRomax = (32)
E{n2oq } α
Substituting Eqs. (40) and (41) into Eq. (39), we have
Equation (32) can be rewritten as

eq−k , k≥q
E{n2oq } − αs2oq =C≥0 (33) hk = si(q−k) = (42)
0, k<q
where C is a positive real constant and the equality holds
only for the optimum matched filter. To find this matched fil- Substituting Eqs. (40) and (42) into Eq. (29), the output sig-
ter, one can substitute Eqs. (29) and (30) into Eq. (33). Then, nal soj can be derived as
one can get
 2 1
   so j = e−| j| , j = 0, ±1, ±2, . . . (43)

q 
q

q
 1 − e2
Rn (k − j)hq−k hq− j −α sik hq−k  = C ≥ 0
k=−∞ j=−∞
k=−∞ 
Again, to have an intuitive feeling about this result, Figs.
(34)
5(a), 5(b), and 5(c) illustrate the discrete input signal sik, the
where Rn(k ⫺ j) is the autocorrelation function of the input discrete matched filter hk, and the discrete output signal soj.
noise ni and C’ is another positive constant. Note that, in the To get the simplest form in Fig. 5, we assumed q ⫽ 0.
process of deriving Eq. (34), we already assume that the input Equation (36) only deals with the physically realizable
noise is at least wide-sense stationary. Under this assump- case. In general, Eq. (36) will be written as (11)
tion, the following condition holds:

∞

Rn (k − j) = Rn ( j − k) = E{nk n j } (35) Rn (k − j)hq− j = sik (44)

j=−∞

Since the equality holds in Eq. (34) when hk is an optimum

In Eq. (44), we have replaced the limit q by 앝. To get the
matched filter regardless of the detail forms of input signal
general form of a discrete matched filter for nonwhite noise,
and noise, it can be shown that the following equation can be
we take the z transform on both size of Eq. (44) and use the
derived under this condition (11):
convolution theorem for z transforms. Then, Eq. (44) can be

q shown to be (14)
Rn (k − j)hq− j = sik (36)
j=−∞
z−q Pn (z)H(1/z) = Si (z) (45)
To make our discussion easy to be understood, we start with
the simple white-noise case. In this case, the autocorrelation where
function can be simply written as

∞
 Pn (z) = Rn (k)z−k
No /2, k = 0
Rn (k) = (37) k=−∞
0, k
= 0 ∞
H(z) = hk z−k (46)
k=−∞
Substituting Eq. (37) into Eq. (36), we obtain
∞
N0 Si (z) = sik z−k
h = sik (38) k=−∞
2 q−k

To get a simpler expression of hk, we let l ⫽ q ⫺ k. Then, Eq. represent the power density spectrum, z transform of a dis-
(38) can be rewritten as crete matched filter, and z transform of discrete input signal.
To obtain the z transform of a discrete matched filter H(z),
2 Eq. (45) is rewritten as
h1 = s (39)
No i(q−l)
Si (1/z) −q
Comparing Eq. (39) with Eq. (15), one can see that Eq. (39) is H(z) = z (47)
Pn (z)
exactly the discrete form of Eq. (19).
As an example, let us consider a discrete input signal sik to
In deriving Eq. (47), we have used a property of power density
be given by
spectrum, that is, Pn(z) ⫽ Pn(1/z). Theoretically speaking, the

ek , k ≤ 0 discrete matched filter in the time domain (that is, the im-
sik = (40) pulse response function of discrete matched filter) can be ob-
0, k > 0 tained by taking the inverse z transform of Eq. (47) (14), that
 MATCHED FILTERS 415

Discrete input filter is

 
1 1 Si (1/z) −q k−1
hk = H(z)zk−1 dz = z z dz (48)
1 2πi  2πi  Pn (z)

0.8 where ⌫ represents a counterclockwise contour in the region

of convergence of H(z) enclosing the origin. Note that, similar
Sik

0.6 to the continuous-time case, the discrete matched filter de-

fined by Eqs. (47) and (48) may not be realizable for arbitrary
0.4
input signal and noise because hk will not vanish for negative
values of the index k.
0.2
To implement the color noise effectively, the prewhitening
technique is used (11). In this approach, the input power den-
–4 –2 0 2 4 sity spectrum Pn(z) is written as the multiplication of two
k facts Pn⫹(z) and Pn⫺(z), that is,
(a)
Pn (z) = Pn+ (z)Pn− (z) (49)

Discrete matched filter

where Pn⫹(z) has all of the poles and zeros of Pn(z) that are
inside the unit circle and Pn⫺(z) has all the poles and zeroes of
1 Pn(z) that are outside the unit circle. By this definition, it is
easy to show that
0.8
Pn+ (z) = Pn− (1/z) (50)
hk

0.6
Note that, in the time domain, Pn⫹(z) corresponds to a discrete-
0.4 time input signal that vanishes for all times t ⬍ 0. Similarly,
Pn⫺(z) corresponds to a discrete-time input signal that van-
0.2 ishes for all time t ⬎ 0. This property can be easily proven in
the following way. Assume that nk is a discrete-time function
that vanishes on the negative half-line; that is,
–4 –2 0 2 4
k nk = 0, k < 0 (51)
(b)
If nk is absolutely summable, that is, if
Discrete output signal

∞ 
∞
| fk | = | fk | < ∞ (52)
k=−∞ k=0
1
then, the z transform of this discrete function nk becomes
Normalized Soj

0.8

∞ 
∞
0.6 N(z) = nk z−k = nk z−k (53)
k=−∞ k=0
0.4
From Eq. (53), one can see that the function N(z) exists every-
0.2 where when 兩z兩 ⱖ 1. Hence, the poles of N(z) will all be inside
the unit circle. Thus, Pn⫹(z) corresponds to a discrete-time in-
put signal that vanishes for all time t ⬍ 0. Similarly, it can
–4 –2 0 2 4 be shown that Pn⫺(z) corresponds to a discrete-time input sig-
j nal that vanishes for all time t ⬎ 0. Assume Hpw(z) is the
(c) prewhitening filter. Based on the definition of prewhitening
filter, Hpw(z) for the noise power spectrum Pn(z) must satisfy
Figure 5. An example of matched filter for the white noise in dis- (11)
crete time. (a) Discrete input signal. (b) Discrete matched filter. (c)
Discrete output signal. This figure gives an intuitive feeling about  +  
Pn (z)Hpw (z) Pn− (z)Hpw (1/z) = 1 (54)
using matched filter for discrete time signal processing.

From Eq. (54), one can conclude that the prewhitening filter
is

1
Hpw (z) = (55)
Pn+ (z)
416 MATCHED FILTERS

iy ing about the time signal detection by a matched filter, let

Unit us consider the following simple example. For the purpose of
circle convenience, the ideal input signal is assumed to be a normal-
1 ized sinc function, that is, sinc(t) ⫽ sin(앟t)/앟t, as shown in
x x x
α α
Fig. 7(a). This ideal signal is embedded into an additive
e– e broadband white noise. The corrupted signal is shown in Fig.
7(b). Figure 7(c) shows the system output when this corrupted
Figure 6. Pole locations of the power spectrum density.

Ideal input sinc signal

Because Pn⫹(z) corresponds to a discrete-time input signal that 3
vanishes for all time t ⬍ 0, the impulse response hpwk of this
prewhitening filter will vanish for k ⬍ 0. Hence, the prewhit- 2.5
ening filter Hpw(z) is physically realizable. For example, let us 2
consider a color noise with power density spectrum
1.5

Si (t)
N e2α 1
Pn (z) = 0 α , α>0 (56)
2 (e − z−1 )(eα − z) 0.5

Equation (56) shows that Pn(z) contains poles both inside and 0
outside the unit circle. As discussed in the early part of this –0.5
section, this Pn(z) can be written as the multiplication of
Pn⫹(z) and Pn⫺(z). For the purpose of convenience and symme- –4 –2 0 2 4
try, we let t

 (a)
No eα
Pn+ (z) =
2 eα − z−1 Input signal with noise
 (57) 3
No eα
Pn− (z) =
2 eα − z 2.5
2
Based on Eq. (57), it is easy to show that Pn⫹(z) has a pole at
Si (t) + ni (t)

z ⫽ e⫺움 (11). Since 움 ⬎ 0, z ⫽ e⫺움 ⬍ 1. In other words, this 1.5

pole is inside the unit circle. Similarly, Pn⫺(z) has a pole at 1
z ⫽ e움 that is a real number greater than unity. Figure 6
0.5
illustrates these pole locations of above power spectral den-
sity Pn(z) in the complex plane. In the figure, we assume that 0
z ⫽ x ⫹ iy. For this particular example, the poles are on the –0.5
real axis.
When applying this prewhitening technique to the discrete –4 –2 0 2 4
matched filter, Eq. (47) will be rewritten as t
  (b)
1 Si (1/z) −q
H(z) = + z (58)
Pn (z) Pn− (z)
Matched filter output
3
Equation (58) is the multiplication of two terms. The first
2.5
term is the prewhitening filter and the second term is the
remainder of the unrealizable matched filter. Note that this 2
So (t) + no (t)

multiplication is equivalent to put two linear systems in tan- 1.5

dem. Similar to the continuous-time case, this remaining un-
realizable filter can be made realizable by throwing away the 1
part that does not vanish for negative time. 0.5
0
APPLICATIONS OF A MATCHED FILTER
–0.5

As mentioned in the first part of this article, the major appli-

–4 –2 0 2 4
cation of the matched filter is to pick up the signal in a noisy t
background. As long as the noise is additive, wide-sense sta-
(c)
tionary, and the system is linear and time invariant, the
matched filter can provide a maximum output signal-to-noise Figure 7. Results of the matched filter acting on an input signal
power ratio. The signal can be a time signal (e.g., radar sig- with sinc function embedded in white noise. (a) Ideal input signal. (b)
nal) or spatial signals (e.g., images). To have an intuitive feel- Signal with noise. (c) Matched-filter output.

signal passes through the matched filter. From Fig. 7(c), one
can see that the much better signal-to-noise power ratio can
be achieved by applying matched filter for the signal detection
as long as the noise is additive at least wide-sense station-
ary noise.
Besides applying matched filters for the time-signal detec-
tion (such as the radar signal previously mentioned), they can
also be used for spatial signal detection (15–17). In other
words, we can use a matched filter to identify specific targets
under the noisy background. Thousands of papers have been
published in this field. To save space, here, we just want to
provide some basic principles and simple examples of it. Since
spatial targets, in general, are two-dimensional signals, the
equations developed for the one-dimensional time signal
needs to be extended into the two-dimensional spatial signal.
Note that when matched filter is applied to the 2-D spatial
(or image) identification, this filtering process can be de-
scribed simply as a cross-correlation of a larger target image
(including the noisy background) with a smaller filter kernel.
To keep the consistency of the mathematical description, a
similar derivation process (used for the 1-D time-signal case)
is employed for the 2-D spatial signal. Assume that the target
image is a two-dimensional function s(x, y) and this target
image is embedded into a noisy background with noise distri-
bution n(x, y). Thus, the total detected signal f(x, y) is
f (x, y) = s(x, y) + n(x, y)
Similar to the one-dimensional time signal case, if f(x, y) is a
Fourier-transformable function of space coordinates (x, y) and
n(x, y) is an additive wide-sense stationary noise, the matched
filter exists. It can be shown that H(p, q) has a form of (15)
S∗ (p, q)
H(p, q) = k
N(p, q)
where S*(p, q) is the complex conjugate of the signal spec-
trum, N(p, q) is the spectral density of the background noise,
k is a complex constant, and (p, q) are corresponding spatial
angular frequencies. Mathematically, S(p, q) and N(p, q) are
expressed as
 +∞  ∞
S(p, q) = s(x, y)e−i( px+qy) dx dy
−∞ −∞
 +∞  ∞
N(p, q) = n(x, y)e−i( px+qy) dx dy
−∞ −∞
 +∞  ∞
 
F (p, q) = s(x, y) + n(x, y) e−i( px+qy) dx dy
−∞ −∞
= S(p, q) + N(p, q)
For the purpose of simplicity, we assume that the input
noise n(x, y) is white noise. In this case, Eq. (60) is reduced to
the simpler form
H(p, q) = k S∗ (p, q)
where k⬘ is another constant. Now, assume that there is an
input unknown target t(x, y). Then, the corresponding spec-
trum is T(p, q). When this input target passes through the
matched filter H(p, q) described by Eq. (62), the system out-
MATCHED FILTERS 417
put in the spectrum domain, that is, (p, q) domain, becomes
T (p, q)H(p, q) = K  T (p, q)S∗ (p, q) (63)
Assume that the final system output is g(x⬘, y⬘), where (x⬘,
y⬘) are the spatial coordinates in the output spatial domain.
Based on the discussion in the section titled ‘‘The Matched
Filter for Continuous-Time Input Signals,’’ g(x⬘, y⬘) can be ob-
tained by taking the inverse Fourier transform of Eq. (63),
that is,
 +∞  ∞
 
g(x , y ) = T (p, q)S∗ (p, q)ei( px +qy ) dp dq (64)
−∞ −∞
In Eq. (64), if the input unknown function t(x, y) is the same
as the prestored function s(x, y), Eq. (64) becomes
 
+∞ ∞
 
g(x , y ) = S(p, q)S∗ (p, q)ei( px +qy ) dp dq
−∞ −∞
 +∞  ∞
(65)
 +qy  )
= |S(p, q)|2 ei( px dp dq
−∞ −∞
In this case, the system output g(x⬘, y⬘) is the Fourier
transform of the power spectrum 兩S(p, q)兩2, which is an en-
tirely positive real number so that it will generate a big out-
(59)
put at the original point (0, 0). Notice that, in recent years,
due to the rapid development of digital computers, most 2-D
filtering can be carried out digitally at relatively fast speed.
However, to have an intuitive feeling about 2-D filtering, an
optical description about this filtering process that was widely
used in the earlier stage of image identification (15) is pro-
vided. Optically speaking, the result described by Eq. (65) can
be explained in the following way. When the input target t(x,
(60)
y) is same as the stored target s(x, y), all the curvatures of
the incident target wave are exactly canceled by the matched
filter. Thus, the transmitted field, that is, T(p, q)S*(p, q), in
the frequency domain, is a plane wave (generally of nonuni-
form intensity). In the final output spatial domain, this plane
wave is brought to a bright focus spot g(0, 0) by the inverse
Fourier transform as described in Eq. (65). However, when
the input signal t(x, y) is not s(x, y), the wavefront curvature
will in general not be canceled by the matched filter H(p, q)
in the frequency domain. Thus, the transmitted light will not
be brought to a bright focus spot in the final output spatial
domain. Thus, the presence of the signal s(x, y) can conceivably
(61)
be detected by measuring the intensity of the light at the focal
point of the output plane. If the input target s(x, y) is not lo-
cated at the center, the output bright spot simply shifts by a
distance equal to the distance shifted by s(x, y). Note that this
is the shift-invariant property of the matched filter. The pre-
ceding description can also mathematically be shown by
Schwarz’s inequality. Based on the cross-correlation theorem
of Fourier transform (17), Eq. (64) can also be written in the
spatial domain as
(62)  
+∞ ∞
g(x , y ) = t(x, y)s∗ (x − x , y − y ) dx dy (66)
−∞ −∞
which is recognized to be the cross-correlation between the
stored target s(x, y) and the unknown input target t(x, y). By
418 MATCHED FILTERS

intensity function is defined as

 +∞  ∞ 2
 
 t(x, y)s ∗
(x − x 
, y − y 
) dx dy
 
−∞ −∞
 +∞  ∞  +∞  ∞ (70)
|t(x, y)|2 dx dy |s(x, y)|2 dx dy
−∞ −∞ −∞ −∞

Based on Eq. (69), we obtain

 +∞  ∞ 2
 
 t(x, y)s (x − x , y − y ) dx dy
∗  

−∞ −∞
 +∞  ∞  +∞  ∞ ≤1 (71)
|t(x, y)|2 dx dy |s(x, y)|2 dx dy
−∞ −∞ −∞ −∞

Figure 8. Autocorrelation results of the matched filter application to
pattern recognition. (a) Stored training image. (b) Absolute value of
the matched filter. (c) Unknown input target. (d) Autocorrelation in-
tensity distribution. (e) Three-dimensional surface profile of autocor-
relation intensity distribution. This figure shows that there is a sharp
correlation peak for autocorrelation.
with the equality if and only if s(x, y) ⫽ t(x, y). Thus, one can
conclude that the normalized correlation intensity function
has a maximum value 1 when the unknown input target t(x,
y) is same as the stored target s(x, y). In other words, if there
is a 1 detected in the normalized correlation intensity func-
tion, we know that the unknown input target is just our
stored target. Therefore, this unknown target is recognized.
Again, to have an intuitive feeling about the pattern recog-
nition with matched filter, let us look at the following exam-
ple. Figure 8(a) shows a triangle image that is used to con-
struct the matched filter. Mathematically speaking, this
image is s(x, y). Then, the matched filter S*(p, q) is synthe-

applying Schwarz’s inequality into Eq. (66), we have

  2
 +∞ ∞ 
 t(x, y)s∗ (x − x , y − y ) dx dy

−∞ −∞
 +∞  ∞  +∞  ∞
≤ |t(x, y)|2 dx dy |s(x − x , y − y )|2 dx dy
−∞ −∞ −∞ −∞
(67)

with the equality if and only if t(x, y) ⫽ s(x, y). Because the
integral limit is ⫾앝 in Eq. (67), by letting x ⫽ x ⫺ x⬘, y ⫽
y ⫺ y⬘, we have
 +∞  ∞  +∞  ∞
|s(x − x , y − y )|2 dx dy = |s(x, y)|2 dx dy
−∞ −∞ −∞ −∞
(68)

Substituting Eq. (68) into Eq. (67), we have

  2
 +∞ ∞ 
 t(x, y)s∗ (x − x , y − y ) dx dy

−∞ −∞
 +∞  ∞  +∞  ∞
≤ |t(x, y)|2 dx dy| |s(x, y)|2 dx dy (69)
−∞ −∞ −∞ −∞
Figure 9. Cross-correlation results of the matched filter applied to
pattern recognition. (a) Stored training image. (b) Absolute value of
with the equality if and only if t(x, y) ⫽ s(x, y). To recognize the matched filter. (c) Unknown input target. (d) Cross-correlation
the input target, we can use the normalized correlation inten- intensity distribution. (e) Three-dimensional surface profile of cross-
sity function as the similarity criterion between the unknown correlation intensity distribution. This figure shows that there is no
input target and the stored target. The normalized correlation sharp correlation peak for cross correlation.
 MATHEMATICAL PROGRAMMING 419

sized based on this image. Figure 8(b) shows the absolute
value of this matched filter. When the unknown input target
t(x, y) is the same triangle image as shown in Fig. 8(c), Fig.
8(d) shows the corresponding autocorrelation intensity distri-
bution on the output plane. Figure 8(e) depicts the corre-
sponding three-dimensional surface profile of the autocorrela-
tion intensity distribution. From this figure, one can see that,
indeed, there is a sharp correlation peak in the correlation
plane. However, if the unknown input target t(x, y) is not the
same image used for the matched-filter construction, the cor-
relation result is totally different. As an example, Figs. 9(a)
and 9(b) show the same stored image and matched filter. Fig-
ure 9(c) shows a circular image used as the unknown input
target. Figures 9(d) and 8(e) illustrate the cross-correlation
intensity distribution and corresponding three-dimensional
surface profile. In this case, there is no sharp correlation
peak. Therefore, from the correlation peak intensity, one can
recognize the input targets. In other words, one can tell
whether the unknown input target is the stored image or not.
Before the end of this section, we would like to point out that,
besides the 2-D matched filter, in recent years, 3-D (spatial-
spectral) matched filters were also developed. Due to space
limitations, we can not provide a detail description about this
work. Interested readers are directed to papers such as the
one written by Yu et al. (19).
11. J. B. Thomas, An Introduction To Communication Theory and
System, New York: Springer-Verlag, 1988, p. 202.
12. J. H. Karl, An Introduction to Digital Signal Processing, New
York: Academic Press, 1989, p. 217.
13. L. W. Couch, Digital and Analog Communication Systems, New
York: Macmillan, 1990, p. 497.
14. L. B. Jackson, Digital Filters and Signal Processing, Boston:
Kluwer Academic Publishers, 1989, p. 34.
15. A. Vander Lugt, Signal detection by complex spatial filtering,
IEEE Trans. Inf. Theory, IT-10, 139–145, 1964.
16. SPIE Milestone Series on Coherent Optical Processing, edited by
F. T. S. Yu and S. Yin (eds.), Bellingham, WA: SPIE Optical Engi-
neering Press, 1992.
17. S. Yin, et al., Design of a bipolar composite filter using simulated
annealing algorithm, Opt. Lett. 20: 1409–1411, 1995.
18. F. T. S. Yu, Optical Information Processing, New York: Wiley-
Interscience, 1983, p. 10.
19. X. Yu, I. Reed, and A. Stocker, Comparative performance analysis
of adaptive multispectral detectors, IEEE Trans. Signal Process.,
41, 2639, 1993.
SHIZHUO YIN
FRANCIS T. S. YU
University Park, PA

MATCHING. See BROADBAND NETWORKS.

CONCLUSION
MATERIALS. See FUNCTIONAL AND SMART MATERIALS.
In this article, we have briefly introduced some basic concepts
MATERIALS, CONDUCTIVE. See CONDUCTING MATE-
RIALS.
of the matched filter. We started our discussion with the con-
tinuous-time matched filter. Then we extended our discussion MATERIALS EVALUATION. See EDDY CURRENT NONDE-
to the discrete-time input signals. After that, some major ap- STRUCTIVE EVALUATION.
plications of the matched filters such as the signal detection MATERIALS, FUNCTIONAL. See FUNCTIONAL AND
and pattern recognition were addressed. SMART MATERIALS.
MATHEMATICAL LINGUISTICS. See COMPUTATIONAL
LINGUISTICS.
BIBLIOGRAPHY
MATHEMATICAL OPTIMIZATION. See MATHEMATI-
1. D. O. North, Analysis of the factors which determines signal/ CAL PROGRAMMING.
noise discrimination in radar, Technical Report No. PtR-6C,
Princeton, NJ: RCA Laboratories, 1943.
2. J. H. Van Vleck and D. Middleton, A theoretical comparison of
visual, aural and meter reception of pulsed signals in the pres-
ence of noise. J. Appl. Phys., 17: 940–971, 1946.
3. B. M. Dwork, Detection of a pulse superimposed on fluctuation
noise, Proc. IRE, 38: 771–774, 1950.
4. T. S. George, Fluctuations of ground clutter return in air-borne
radar equipment, J. IEE, 99: 92–99, 1952.
5. L. Z. Zadeh and J. R. Ragazzini, Optimum filters for the detection
of signals in noise, Proc. IRE, 40: 1123–1131, 1952.
6. G. L. Turin, An introduction to matched filters, IRE Trans. Inf.
Theory, IT-6: 311–329, 1960.
7. C. R. Cahn, Performance of digital matched filter correlation with
unknown interference, IEEE Trans. Commun. Technol. COM-19:
Part II, 1163–1172, 1971.
8. D. J. Gooding, A digital matched filter for signals of large time-
bandwidth product. Technical Report No. 16, Waltham, MA: Syl-
vania Communications System Laboratory, February 1969.
9. K. Y. Chang and A. D. Moore, Modified digital correlator and its
estimation errors, IEEE Trans. Inf. Theory, IT-16: 699–700, 1970.
10. G. L. Turin, An introduction to digital matched filters, Proc.
IEEE, 64: 1092–1112, 1976.
324 MIXER CIRCUITS

MIXER CIRCUITS

A frequency mixer inputs two frequencies—a radio frequency

(RF) and a local oscillator (LO) frequency—mixes them, and
produces their difference frequency and sum frequency. The
output signal is tuned by a filter, and one of the two output
frequencies is selected: the difference or the sum. When the
output difference frequency is an intermediate frequency (IF),
the mixer is usually called a downconversion frequency mixer,
and when the output sum frequency is a high frequency, it is
usually called an upconversion frequency mixer.
A frequency mixer is fundamentally a multiplier, because
the analog multiplier outputs a signal proportional to the
product of the two input signals. Therefore, a frequency mixer
is represented by the symbol for the multiplier, as shown in
Fig. 1.

RF IF

LO
Figure 1. A symbol for a frequency mixer. The symbol for a multi-
plier is used.

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

The transfer function of a nonlinear element is expressed
as
f (u) = a0 + a1 u + a2 u + a3 u + · · · + an u + · · ·
2 3 n
(1)
The product xy of the two input signals x and y can be derived
from only the second-order term: a2u2, where u ⫽ x ⫹ y, and
x and y are the two input signals. The product of the two
input signals is produced by a nonlinear element, such as a
diode or transistor. For example, single-diode mixers, singly
balanced diode mixers, doubly balanced diode mixers, single-
transistor mixers, singly balanced transistor mixers, and dou-
bly balanced transistor mixers are usually used as frequency
mixers.
APPLICATION TO RECEIVERS
Mixers are used to shift the received signal to an intermediate
frequency, where it can be amplified with good selectivity,
high gain, and low noise, and finally demodulated in a re-
ceiver. Mixers have important applications in ordinary low-
frequency and microwave receivers, where they are used to
shift signals to frequencies where they can be amplified and
demodulated most efficiently. Mixers can also be used as
phase detectors and in demodulators, and must perform these
functions while adding minimal noise and distortion.
Figure 2 shows, for example, the block diagram of a VHF
or UHF communication receiver. The receiver has a single-
stage input amplifier; this preamp, which is usually called an
RF amplifier, increases the strength of the received signal so
that it exceeds the noise level of the following stage; therefore,
this preamp is also called a low-noise amplifier (LNA). The
first IF is relatively high (in a VHF or UHF receiver, the
widely accepted standard has been 10.7 MHz); this high IF
moves the image frequency well away from the RF, thus
allowing the image to be rejected effectively by the input fil-
ter. The second conversion occurs after considerable amplifi-
cation, and is used to select some particular signal within the
input band and to shift it to the second IF. Because narrow
bandwidths are generally easier to achieve at this lower fre-
quency, the selectivity of the filter used before the detector is
much better than that of the first IF. The frequency synthe-
sizer generates the variable-frequency LO signal for the first
mixer, and the fixed-frequency LO for the second mixer.
Input First mixer First IF Second mixer
Filter Filter
Second LO
First
LO
Frequency Second IF
synthesizer
Filter Demod
Output
Frequency
set commands
Figure 2. Double superheterodyne VHF or UHF communication re-
ceiver.
MIXER CIRCUITS 325
Multiplier
A(t) cos(ω st) Filter A(t) cos[(ω s – ω p)t]
A(t) cos(ω pt)
A(t) cos(ω st) cos(ω pt) = A(t) cos[(ω s – ω p)t] + cos[(ω s + ω p)t]
2
Figure 3. A mixer is fundamentally a multiplier. The difference fre-
quency in the IF results from the product of sinusoids.
Figure 3 illustrates an ideal analog multiplier with two si-
nusoids applied to it. The signal applied to the RF port has a
carrier frequency 웆s and a modulation waveform A(t). The
other, the LO, is a pure, unmodulated sinusoid at frequency
웆p.
Applying some basic trigonometry to the output is found to
consist of modulated components at the sum and difference
frequencies. The sum frequency is rejected by the IF filter,
leaving only the difference.
Fortunately, an ideal multiplier is not the only device that
can realize a mixer. Any nonlinear device can perform the
multiplying function. The use of a nonideal multiplier results
in the generation of LO harmonics and in mixing products
other than the desired one. The desired output frequency
component must be filtered from the resulting chaos.
Another way to view the operation of a mixer is as a
switch. Indeed, in the past, diodes used in mixers have been
idealized as switches operated at the LO frequency. Figure
4(a) shows a mixer modeled as a switch; the switch interrupts
the RF voltage waveform periodically at the LO frequency.
The IF voltage is the product of the RF voltage and the
switching waveform.
Another switching mixer is shown in Fig. 4(b). Instead of
simply interrupting the current between the RF and IF ports,
S(t)
S(t)
VRF VIF
t
(a)
S(t)
S(t)
t
VRF VIF
(b)
Figure 4. Two switching mixers: (a) a simple switching mixer: (b)
a polarity-switching mixer. The IF is the product of the switching
waveform s(t) and the RF input, making these mixers a type of multi-
plier.
326 MIXER CIRCUITS
the switch changes the polarity of the RF voltage periodically.
The advantage of this mixer over the one in Fig. 4(a) is that
the LO waveform has no dc component, so the product of the
RF voltage and switching waveform does not include any volt-
age at the RF frequency. Thus, even though no filters are
used, the RF and LO ports of this mixer are inherently iso-
lated. Doubly balanced mixers are realizations of the polarity-
switching mixer.
SEMICONDUCTOR DEVICES FOR MIXERS
Only a few devices satisfy the practical requirements of mixer
operation. Any device used as a mixer must have strong
nonlinearity, electrical properties that are uniform between
individual devices, low noise, low distortion, and adequate
frequency response. The primary devices used for mixers are
Schottky-barrier diodes and field-effect transistors (FETs). Bi-
polar junction transistors (BJT) are also used occasionally,
primarily in Gilbert-cell multiplier circuits [see Fig. 6(d)], but
because of their superior large-signal-handling ability, higher
frequency range, and low noise, FET devices such as metal–
oxide–semiconductor FETs (MOSFET), gallium arsenide
(GaAs) metal–semiconductor FETs (MESFET), and high-
electron-mobility transistors (HEMTs) have been usually pre-
ferred.
The Schottky-barrier diode is the dominant device used in
mixers. Because Schottky-barrier diodes are inherently capa-
ble of fast switching, have very small reactive parasitics, and
do not need dc bias, they can be used in very broadband mix-
ers. Schottky-barrier-diode mixers usually do not require
matching circuits, so no tuning or adjustment is needed.
Although mixers using Schottky-barrier diodes always ex-
hibit conversion loss, transistor mixers are capable of conver-
sion gain. This helps simplify the architecture of a system,
often allowing the use of fewer amplifier stages than neces-
sary in diode-mixer receivers.
Since the 1950s, bipolar transistors have dominated mixer
applications as single-transistor mixers in AM radio and com-
munication receivers. In particular, an analog multiplier con-
sisting of a doubly balanced differential amplifier, called the
Gilbert cell, was invented in the 1960s. Since then, the Gil-
bert-cell mixer has been used as a monolithic integrated cir-
cuit (IC) for AM radio receivers and communication equip-
ment. Silicon BJTs are used in mixers because of their low
cost and ease of implementation with monolithic ICs. These
bipolar devices are used as mixers when necessary for process
compatibility, although FETs generally provide better overall
performance. Silicon BJTs are usually used in conventional
single-device or singly and doubly balanced mixers. Progress
in the development of heterojunction bipolar transistors
(HBT), which use a heterojunction for the emitter-to-base
junction, may bring about a resurgence in the use of bipolar
devices as mixers. HBTs are often used as analog multipliers
operating at frequencies approaching the microwave range;
the most common form is a Gilbert cell. Silicon–germanium
(Si–Ge) HBTs are a new technology that offers high perfor-
mance at costs close to that of silicon BJTs.
A variety of types of FETs are used in mixers. Since the
1960s, silicon MOSFETs (often dual-gate devices) have domi-
nated mixer applications in communication receivers up to
approximately 1 GHz. At higher frequency, GaAs MESFETs
are often used. The LO and RF signals can be applied to sepa-
rate gates of dual-gate FETs, allowing good RF-to-LO isola-
tion to be achieved in a single-device mixer. Dual-gate devices
can be used to realize self-oscillating mixers, in which a single
device provides both the LO and mixer functions.
Although silicon devices have distinctly lower transconduc-
tance than GaAs, they are useful up to at least the lower mi-
crowave frequencies. In spite of the inherent inferiority of sili-
con to GaAs, silicon MOSFETs do have some advantages. The
primary one is low cost, and the performance of silicon MOS-
FET mixers is not significantly worse than GaAs in the VHF
and UHF range. The high drain-to-source resistance of silicon
MOSFETs gives them higher voltage gain than GaAs devices;
in many applications this is a distinct advantage. Addition-
ally, the positive threshold voltage (in an n-channel enhance-
ment MOSFET), in comparison with the negative threshold
voltage of a GaAs FET, is very helpful in realizing low-voltage
circuits and circuits requiring only a single dc supply. Mixers
using enhancement-mode silicon MOSFETs often do not re-
quire gate bias, and dual-gate MOSFETs offer convenient LO-
to-RF isolation when the LO and RF are applied to different
gates.
A MESFET is a junction FET having a Schottky-barrier
gate. Although silicon MESFETs have been made, they are
now obsolete, and all modern MESFETs are fabricated on
GaAs. GaAs is decidedly superior to silicon for high-frequency
mixers because of its higher electron mobility and saturation
velocity. The gate length is usually less than 0.5 애m, and may
be as short as 0.1 애m; this short gate length, in conjunction
with the high electron mobility and saturation velocity of
GaAs, results in a high-frequency, low-noise device.
HEMTs are used for mixers in the same way as conven-
tional GaAs FETs. Because the gate IV characteristic of a
HEMT is generally more strongly nonlinear than that of a
MESFET, HEMT mixers usually have greater intermodula-
tion (IM) distortion than FETs. However the noise figure (NF)
of an HEMT mixer usually is not significantly lower than that
of a GaAs FET. An HEMT is a junction FET that uses a het-
erojunction (a junction between two dissimilar semiconduc-
tors), instead of a simple epitaxial layer, for the channel. The
discontinuity of the bandgaps of the materials used for the
heterojunction creates a layer of charge at the surface of the
junction; the charge density can be controlled by the gate volt-
age. Because the charge in this layer has very high mobility,
high-frequency operation and very low noise are possible. It
is not unusual for HEMTs to operate successfully as low-noise
amplifiers above 100 GHz. HEMTs require specialized fabri-
cation techniques, such as molecular beam epitaxy, and thus
are very expensive to manufacture. HEMT heterojunctions
are invariably realized with III–V semiconductors; AlGaAs
and InGaAs are common.
Passive Diode Mixers
Figure 5 shows the most common form of the three diode-
mixer types: a single-device diode mixer, a singly balanced
diode mixer, and a doubly balanced diode mixer. Conversion
loss of 6 to 8 dB is usually accepted in these passive mixers.
Active Transistor Mixers
Active transistor mixers have several advantages, and some
disadvantages, in comparison with diode mixers. Most sig-
 MIXER CIRCUITS 327

Because transistors cannot be reversed, as can diodes, bal-

anced transistor mixers invariably require an extra hybrid at
the IF. This can be avoided only by using a p-channel device
instead of an n-channel device, or vice versa; however, this is
RF ω RF ω IF IF possible only in silicon circuits, and even then the characteris-
tics of p- and n-channel devices are likely to be significantly
different.

Bipolar Junction Transistor Mixers. Figure 6 shows BJT mix-

ω LO
LO
(a)
RF
IF
LO
(b)
LO D2 D3
D1 D4
IF
RF
(c)
Figure 5. The three most common diode-mixer types: (a) single-de-
vice, (b) singly balanced, (c) doubly balanced.
nificantly, an active mixer can achieve conversion gain, while
diode and other passive mixers always exhibit loss. This
allows a system using an active mixer to have one or two
fewer stages of amplification; the resulting simplification is
especially valuable in circuits where small size and low cost
are vital. A precise comparison of distortion in diode and ac-
tive transistor mixers is difficult to make because the compar-
ison depends on the details of the system. Generally, however,
it is fair to say that distortion levels of well-designed active
mixers are usually comparable to those of diode mixers.
It is usually easy to achieve good conversion efficiency in
active mixers. Thus, active transistor mixers have gained a
reputation for low performance. Nevertheless, achieving good
overall performance in active transistor mixers is not difficult.
ers: a single-device BJT mixer, a singly balanced BJT mixer,
a differential BJT mixer, and a doubly balanced BJT mixer.
In a single-device BJT mixer [Fig. 6(a)], the input signals
are introduced into the device through the RF LO diplexer,
which consists of an RF bandpass filter, an LO bandpass fil-
ter, and two strips, ␭ /4 long at the center of the RF and LO
frequency ranges; the square-law term of the device’s charac-
teristic provides the multiplication action. A single-device
BJT mixer achieves a conversion gain of typically 20 to 24 dB,
a noise figure of typically 4 to 5 dB (which is about 3 dB more
than that of the device in the amplifier at the RF), and a third
intercept point near 0 dBm. The IM product from this type of
single-device BJT mixer usually depends on its collector cur-
rent, but when the supplied collector-to-emitter voltage, VCE,
is not enough (typically, below 1.2 V), the IM product in-
creases as VCE decreases.
A singly balanced BJT upconversion mixer [Fig. 6(b)] con-
sists of two BJTs interconnected by a balun or hybrid. The
two collectors are connected through a strip, ␭ /2 long at the
center of the LO frequency range, for reducing the LO leak-
age. This upconversion mixer exhibits 16 dB conversion gain
and 12 dB LO leakage suppression versus the wanted RF out-
put level at 900 MHz.
A singly balanced BJT differential mixer [Fig. 6(c)] con-
sists of an emitter-coupled differential pair. The RF is super-
posed on the tail current by ac coupling through capacitor
C2, and the LO is applied to the upper transistor pair, where
capacitive degeneration and ac coupling substantially reduce
the gain at low frequencies. Note that the circuit following
C2 is differential and hence much less susceptible to even-
order distortion.
A multiplier circuit [Fig. 6(d)] conceived in 1967 by Barrie
Gilbert and widely known as the Gilbert cell (though Gilbert
himelf was not responsible for his eponymy; indeed, he has
noted that a prior art search at the time found that essen-
tially the same idea—used as a ‘‘synchronous detector’’ and
not as true mixer—had already been patented by H. Jones)
is usually used as an RF mixer and sometimes as a micro-
wave mixer.
Ignoring the basewidth modulation, the relationship be-
tween the collector current IC and the base-to-emitter voltage
VBE for a BJT is


VBE
IC = IS exp (2)
VT
where VT ⫽ kT/q is the thermal voltage, k is Boltzmann’s con-
stant, T is absolute temperature in kelvin, and q is the charge
of an electron. IS is the saturation current for a graded-base
transistor.
Assuming matched devices, the differential output voltage
of the Gilbert cell is



VRF VLO
VIF = −RL IEE tanh tanh (3)
2VT 2VT
328 MIXER CIRCUITS

Matching
RF
network
Matching Q1
LO
network
λ
2

LPF IF
RF BPF Matching IF
network
λ
Q1 Q2
4
LO BPF λ
4

(a) (b)

VCC
VCC

RL RL
Vo
VIF
Q3 Q4

VLO
Q1 Q2 Q3 Q4
VLO

C2
VRF Q1
Q5 Q5
VRF
C1
IO

(c) (d)
Figure 6. BJT mixers: (a) a single-device BJT mixer, (b) a singly balanced BJT upconversion
mixer, (c) a singly balanced BJT differential mixer, (d) a doubly balanced BJT mixer consisting
of a Gilbert cell.

For small inputs,
RL IEE
VIF ≈ − V V
4VT2 RF LO
The product VRFVLO is obtained by the Gilbert cell at small
signals.
FET Mixers. Figure 7 shows FET mixers: a single-device
FET mixer, a dual-gate FET mixer, a singly balanced FET
mixer, a differential FET mixer, and a doubly balanced FET
mixer.
In a single-device FET mixer [Fig. 7(a)], the RF–LO
diplexer must combine the RF and LO and also provide
matching between the FET’s gate and both ports. The IF filter
must provide an appropriate impedance to the drain of the
FET at the IF and must short-circuit the drain at the RF and
especially at the LO frequency and its harmonics.
(4)
The configuration of a dual-gate mixer [Fig. 7(b)] provides
the best performance in most receiver applications. In this
circuit, the LO is connected to the gate closest to the drain
(gate 2), while the RF is connected to the gate closest to the
source (gate 1). An IF bypass filter is used at gate 2, and an
LO–RF filter is used at the drain. A dual-gate mixer is usu-
ally realized as two single-gate FETs in a cascade connection.
A singly balanced FET mixer [Fig. 7(c)] uses a transformer
hybrid for the LO and RF; any appropriate type of hybrid can
be used. A matching circuit is needed at the gates of both
FETs. The IF filters provide the requisite short circuits to the
drains at the LO and RF frequencies, and additionally pro-
 MIXER CIRCUITS 329

IF bypass
IF
IF
matching

IF LO G2 D
IF LO
G D filter matching
LO RF LO & RF
RF
diplexer RF bypass
S RF G1
matching S
LO
(a) (b)

IF LPF IF

MC
IF
balun

IF
LO
LO
LO
balun

RF
MC
RF
(c) (d)

IF

IF
balun

LO
LO
balun

RF
RF Figure 7. FET mixers: (a) a single-device FET mixer, (b) a dual-gate
balun
FET mixer, (c) a singly balanced FET mixer, (d) a differential mixer,
(e) (e) a doubly balanced mixer.

vide IF load impedance transformations. The singly balanced
mixer of Fig. 7(c) is effectively two single-device mixers inter-
connected by hybrids.
In a differential FET mixer [Fig. 7(d)], the RF is applied to
the lower FET, and the LO is applied through a balun or hy-
brid to the upper FETs. This mixer operates as an alternating
switch, connecting the drain of the lower FET alternately to
the inputs of the IF balun. An LO matching circuit may be
needed. Because the RF and LO circuits are separate, the
gates of the upper FETs can be matched at the LO frequency,
and there is no tradeoff between effective LO and RF match-
ing. Similarly, the lower FET can be matched effectively at
the RF. An IF filter is necessary to reject LO current.
A doubly balanced FET mixer [Fig. 7(e)] is frequently used
as an RF or microwave mixer. Like many doubly balanced
mixers, this mixer consists of two of the singly balanced mix-
ers shown in Fig. 7(d). Each half of the mixer operates in the
same manner as that of Fig. 7(d). The interconnection of the
outputs, however, causes the drains of the upper four FETs
to be virtual grounds for both LO and RF, as well as for even-
order spurious responses and IM products.
IMAGE-REJECTION MIXERS
The image-rejection mixer (Fig. 8) is realized as the intercon-
nection of a pair of balanced mixers. It is especially useful for
applications where the image and RF bands overlap, or the
image is too close to the RF to be rejected by a filter. The LO
ports of the balanced mixers are driven in phase, but the sig-
330 MIXER CIRCUITS
RF IF
90°
RF 90° LO 90° LO 90°
hybrid
LO
hybrid hybrid
0°
RF IF
Figure 8. Image-rejection mixer.
nals applied to the RF ports have 90⬚ phase difference. A 90⬚
IF hybrid is used to separate the RF and image bands. A full
discussion of the operation of such mixers is a little compli-
cated.
The most difficult part of the design of an image-rejection
mixer is the IF hybrid. If the IF is fairly high, a conventional
RF or microwave hybrid can be used. However, if the mixer
requires a baseband IF, the designer is placed in the problem-
atical position of trying to create a Hilbert-transforming filter,
a theoretical impossibility. Fortunately, it is possible to ap-
proximate the operation of such a filter over a limited band-
width.
MIXING
A mixer is fundamentally a multiplier. An ideal mixer multi-
plies a signal by a sinusoid, shifting it to both a higher and a
lower frequency, and selects one of the resulting sidebands. A
modulated narrowband signal, usually called the RF signal,
represented by
SRF (t) = a(t) sin(ωst) + b(t) cos(ωst)
is multiplied by the LO signal function
f LO (t) = cos(ωpt)
to obtain the IF signal
SIF (t) = 12 a(t) sin[(ωs + ωp )t] + sin[(ωs − ωp )t]}
+ 12 b(t) cos[(ωs + ωp )t] + cos[(ωs − ωp )t]
In the ideal mixer, two sinusoidal IF components, called
mixing products, result from each sinusoid in s(t). In receiv-
ers, the difference-frequency component is usually desired,
and the sum-frequency component is rejected by filters.
Even if the LO voltage applied to the mixer’s LO port is a
clean sinusoid, the nonlinearities of the mixing device distort
it, causing the LO function to have harmonics. Those nonline-
arities can also distort the RF signal, resulting in RF harmon-
ics. The IF is, in general, the combination of all possible mix-
ing products of the RF and LO harmonics. Filters are usually
used to select the appropriate response and eliminate the
other (so-called spurious) responses.
Every mixer, even an ideal one, has a second RF that can
create a response at the IF. This is a type of spurious re-
sponse, and is called the image; it occurs at the frequency
2f LO ⫺ f RF. For example, if a mixer is designed to convert 10
GHz to 1 GHz with a 9 GHz LO, the mixer will also convert
8 GHz to 1 GHz at the same LO frequency. Although none of
the types of mixers we shall examine inherently reject im-
ages, it is possible to create combinations of mixers and hy-
USB brids that do reject the image response.
It is important to note that the process of frequency shift-
LSB
ing, which is the fundamental purpose of a mixer, is a linear
phenomenon. Although nonlinear devices are invariably used
for realizing mixers, there is nothing in the process of fre-
quency shifting that requires nonlinearity. Distortion and
spurious responses other than the sum and difference fre-
quency, though often severe in mixers, are not fundamentally
required by the frequency-shifting operation that a mixer per-
forms.
Conversion Efficiency
Mixers using Schottky-barrier diodes are passive components
and consequently exhibit conversion loss. This loss has a
number of consequences: the greater the loss, the higher the
noise of the system and the more amplification is needed.
High loss contributes indirectly to distortion because of high
signal levels that result from the additional preamplifier gain
required to compensate for this loss. It also contributes to the
cost of the system, since the necessary low-noise amplifier
stages are usually expensive.
Mixers using active devices often (but not always) exhibit
conversion gain. The conversion gain (CG) is defined as
IF power available at mixer output
CG = (8)
RF power available to mixer input
High mixer gain is not necessarily desirable, because it re-
duces stability margins and can increase distortion. Usually,
a mixer gain of unity, or at most a few decibels, is best.
(5)
Noise
In a passive mixer whose image response has been eliminated
(6) by filters, the noise figure is usually equal to, or only a few
tenths of a decibel above, the conversion loss. In this sense,
the mixer behaves as if it were an attenuator having a tem-
perature equal to or slightly above the ambient.
In active mixers, the noise figure cannot be related easily
(7) to the conversion efficiency; in general, it cannot even be re-
lated qualitatively to the device’s noise figure when used as
an amplifier. The noise figure (NF) is defined by the equation
input signal-to-noise power ratio
NF = (9)
output signal-to-noise power ratio
The sensitivity of a receiver is usually limited by its inter-
nally generated noise. However, other phenomena sometimes
affect the performance of a mixer front end more severely
than noise. One of these is the AM noise, or amplitude noise,
from the LO source, which is injected into the mixer along
with the LO signal. This noise may be especially severe in a
single-ended mixer (balanced mixers reject AM LO noise to
some degree) or when the LO signal is generated at a low
level and amplified.
Phase noise is also a concern in systems using mixers. LO
sources always have a certain amount of phase jitter, or phase
noise, which is transferred degree for degree via the mixer to
the received signal. This noise may be very serious in commu-
nications systems using either digital or analog phase modu-
 MIXER CIRCUITS 331

Mixer S(f )
Image
RF IF IF
RF in LNA rejection
filter filter stage
filter

LO
f2 – f1 f1 f2 2f1 2f2 3f1 3f2 f
Figure 9. RF front end.
2f1 – f2 2f1 – f1 f2 + f1 2f1 + f2 2f2 + f1

Figure 10. IF spectrum of intermodulation products up to third or-

lation. Spurious signals may also be present, along with the der. The frequencies f 1 and f 2 are the excitation.
desired LO signal, especially if a phase-locked-loop frequency
synthesizer is used in the LO source. Spurious signals are
usually phase-modulation sidebands of the LO signal, and,
like phase noise, are transferred to the received signal. Fi- nents, however, mixers often employ strongly nonlinear de-
nally, the mixer may generate a wide variety of intermodula- vices to provide mixing. Because of these strong nonlineari-
tion products, which allow input signals—even if they are not ties, mixers generate high levels of distortion. A mixer is
within the input passband—to generate spurious output at usually the dominant distortion-generating component in a
the IF. These problems must be circumvented if a successful receiver.
receiver design is to be achieved. Distortion in mixers, as with other components, is mani-
An ideal amplifier would amplify the incoming signal and fested as IM distortion (IMD), which involves mixing between
incoming noise equally and would introduce no additional multiple RF tones and harmonics of those tones. If two RF
noise. From Eq. (9) such an amplifier would have a noise fig- excitations f 1 and f 2 are applied to a mixer, the nonlinearities
ure equal to unity (0 dB). in the mixer will generate a number of new frequencies, re-
The noise figure of several cascaded amplifier stages is sulting in the IF spectrum shown in Fig. 10. Figure 10 shows
all intermodulation products up to third order; by nth order,
NG2 − 1 NF3 − 1 NFn − 1 we mean all n-fold combinations of the excitation tones (not
NF = NF1 + + + · · · + n (10)
G1 G1 G2 1 Gn including the LO frequency). In general, an nth-order nonlin-
earity gives rise to distortion products of nth (and lower)
where NF is the total noise figure, NFn is the noise figure of order.
the nth stage, and Gn is the available gain of the nth stage. An important property of IMD is that the level of the nth-
From Eq. (10), the gain and noise figure of the first stage order IM product changes by n decibels for every decibel of
of a cascaded chain will largely determine the total noise fig- change in the levels of the RF excitations. The extrapolated
ure. For example, the system noise figure (on a linear scale) point at which the excitation and IMD levels are equal is
for the downconverter shown in Fig. 9 is called the nth-order IM intercept point, abbreviated IPn. This

 dependence is illustrated in Fig. 11. In most components, the
1 NFLNA − 1 1 1 intercept point is defined as an output power: in mixers it is
NF = + + −1
LRF LRF LRF GLNA LIM traditionally an input power.


NFM − 1 1 NFM − LI
+ +··· = NFLNA + +···
LRF GLNA LI LRF GLNA LI
(11)
10
where LRF and LI are the insertion losses of the RF filter and
the image-rejection filter, respectively, NFLNA and NFM are the
Intercept
noise figures of the LNA and the mixer, respectively, and point
0
GLNA is the power gain of the LNA. This equation assumes
that the noise figures of the filters are the same as their inser-
POUT dBm

tion losses.
–10 Linear output
Bandwidth level

The bandwidth of a diode mixer is limited by the external IM output

level
circuit, especially by the hybrids or baluns used to couple the –20
RF and LO signals to the diodes. In active mixers, bandwidth
can be limited either by the device or by hybrids or matching
circuits that constitute the external circuit; much the same
factors are involved in establishing active mixers’ bandwidths –30
as amplifiers’ bandwidths. –20 Pl –10 PI 0 IPn 10 20
Pin, dbm
Distortion
Figure 11. The output level of each nth-order IM product varies n
It is a truism that everything is nonlinear to some degree and decibels for every decibel change in input level. The intercept point is
generates distortion. Unlike amplifiers or passive compo- the extrapolated point at which the curves intersect.
332 MIXER CIRCUITS
Given the intercept point IPn and input power level in deci-
bels, the IM input level PI in decibels can be found from


1 1
PI = P1 + 1 − IPn (12)
n n
where Pl is the input level of each of the linear RF tones
(which are assumed to be equal) in decibels. By convention,
Pl and PI are the input powers of a single frequency compo-
nent where the linear output level and the level of the nth-
order IM product are equal; They are not the total power of
all components. For example, Pl is the threshold level for a
receiver. The fluctuation of the IMD level is rather small in
spite of the fluctuations of Pl and IPn.
Spurious Responses
A mixer converts an RF signal to an IF signal. The most com-
mon transformation is
f IF = f RF − f LO (13)
although others are frequently used. The discussion of fre-
quency mixing indicated that harmonics of both the RF and
LO could mix. The resulting set of frequencies is
f IF = m f RF − nf LO (14)
where m and n are integers. If an RF signal creates an in-
band IF response other than the desired one, it is called a
spurious response. Usually the RF, IF, and LO frequency
ranges are selected carefully to avoid spurious responses, and
filters are used to reject out-of-band RF signals that may
cause in-band IF responses. IF filters are used to select only
the desired response.
Many types of balanced mixers reject certain spurious re-
sponses where m or n is even. Most singly balanced mixers
reject some, but not all, products where m or n (or both) are
even.
Harmonic Mixer
A mixer is sensitive to many frequencies besides those at
which it is designed to operate. The best known of these is
the image frequency, which is found at the LO sideband oppo-
site the input, of the RF frequency. The mixer is also sensitive
to similar sidebands on either side of each LO harmonic.
These responses are usually undesired; the exception is the
harmonic mixer, which is designed to operate at one or more
of these sidebands.
When a small-signal voltage is applied to the pumped di-
ode at any one of these frequencies, currents and voltages are
generated in the junction at all other sideband frequencies.
These frequencies are called the small-signal mixing frequen-
cies 웆n and are given by the relation
ωn = ω0 + nωp (15)
where 웆p is the LO frequency and
n = · · · , −3, −2, −1, 0, 1, 2, 3, . . . (16)
V(ω ), I(ω )
ω0 ω –1 ω p ω 1 ω –2 ω –2 2ωp ω 2 ω
Figure 12. Small-signal mixing frequencies 웆n and LO harmonics
n웆p. Voltage and current components exist in the diode at these fre-
quencies.
These frequencies are shown in Fig. 12. The frequencies are
separated from each LO harmonic by 웆0, the difference be-
tween the LO frequency and the RF.
MODULATION AND FREQUENCY TRANSLATION
Modulation
Modulation is the process by which the information content
of an audio, video, or data signal is transferred to an RF car-
rier before transmission. Commonly, the signal being modu-
lated is a sine wave of constant amplitude and is referred to
as the carrier. The signal that varies some parameter of the
carrier is known as the modulation signal. The parameters of
a sine wave that may be varied are the amplitude, the fre-
quency, and the phase. Other types of modulation may be ap-
plied to special signals, e.g., pulse-width and pulse-position
modulation of recurrent pulses. The inverse process—
recovering the information from an RF signal—is called de-
modulation or detection. In its simpler forms a modulator
may cause some characteristic of an RF signal to vary in di-
rect proportion to the modulating waveform: this is termed
analog modulation. More complex modulators digitize and en-
code the modulating signal before modulation. For many ap-
plications digital modulation is preferred to analog modu-
lation.
A complete communication system (Fig. 13) consists of an
information source, an RF source, a modulator, an RF chan-
nel (including both transmitter and receiver RF stages, the
antennas, the transmission path, etc.), a demodulator, and an
information user. The system works if the information user
receives the source information with acceptable reliability.
The designer’s goal is to create a low-cost working system
that complies with the legal restrictions on such things as
transmitter power, antenna height, and signal bandwidth.
Since modulation demodulation schemes differ in cost, band-
width, interference rejection, power consumption, and so
forth, the choice of the modulation type is an important part
of communication system design.
Modulation, demodulation (detection), and heterodyne ac-
tion are very closely related processes. Each process involves
generating the sum and/or difference frequencies of two or
more sinsuoids by causing one signal to vary as a direct func-
tion (product) of the other signal or signals. The multiplica-
tion of one signal by another can only be accomplished in a
nonlinear device. This is readily seen by considering any net-
work where the output signal is some function of the input
signal e1, for example,
e0 = f (e1 ) (17)

RF source Modulator RF channel Demodulator
Information
source
In any perfectly linear network, this requires that
e0 = ke1 (18)
and, assuming two different input signals,
e0 = k(Ea cos ωat + Eb cos ωbt) (19)
where k is a constant. In this case the output signal contains
only the two input-signal frequencies. However, if the output
is a nonlinear function of the input, it can, in general, be rep-
resented by a series expansion of the input signal. For exam-
ple, let
e0 = k1 e1 + k2 e22 + k3 e33 + · · · + kn enn (20)
When e1 contains two frequencies, e0 will contain the input
frequencies and their harmonics plus the products of these
frequencies. These frequency products can be expressed as
sum and difference frequencies. Thus, all modulators, detec-
tors, and mixers are of necessity nonlinear devices. The prin-
cipal distinction between these devices is the frequency differ-
ences between the input signals and the desired output signal
or signals. For example, amplitude modulation in general in-
volves the multiplication of a high-frequency carrier by low-
frequency modulation signals to produce sideband signals
near the carrier frequency. In a mixer, two high-frequency
signals are multiplied to produce an output signal at a fre-
quency that is the difference between the input-signal fre-
quencies. In a detector for amplitude modulation, the carrier
is multiplied by the sideband signals to produce their differ-
ent frequencies at the output.
To understand the modulation process, it is helpful to visu-
alize a modulator as a black box (Fig. 14) with two inputs
and one output connected to a carrier oscillator producing a
sinusoidal voltage with constant amplitude and frequency
f RF. The output is a modulated waveform
F (t) = A(t) cos[ωst + (t)] = A(t) cos (t) (21)
Modulated
Oscillator
Modulator F(t)
( fRF) signal
vm(t)
Modulating voltage
Figure 14. Black-box view of a modulator.
MIXER CIRCUITS 333
Information
user
Figure 13. Conceptual diagram of a com-
munication system.
whose amplitude A(t) or angle ⌽(t), or both, are controlled by
vm(t). In amplitude modulation (AM) the carrier envelope
A(t) is varied while ⌰(t) remains constant; in angle modula-
tion A(t) is fixed and the modulating signal controls ⌽(t).
Angle modulation may be either frequency modulation (FM)
or phase modulation (PM), depending upon the relationship
between the angle ⌽(t) and the modulation signal.
Although the waveform (21) might be called a modulated
cosine wave, it is not a single-frequency sinusoid when modu-
lation is present. If either A(t) or ⌰(t) varies with time, the
spectrum of F(t) will occupy a bandwidth determined by both
the modulating signal and the type of modulation used.
Amplitude Modulation. Amplitude modulation in the form
of on–off keying of radio-telegraph transmitters is the oldest
type of modulation. Today, amplitude modulation is widely
used for those analog voice applications that require simple
receivers (e.g., commercial broadcasting) and require narrow
bandwidths.
In amplitude modulation the instantaneous amplitude of
the carrier is varied in proportion to the modulating signal.
The modulating signal may be a single frequency, or, more
often, it may consist of many frequencies of various ampli-
tudes and phases, e.g., the signals constituting speech. For a
carrier modulated by a single-frequency sine wave of constant
amplitude, the instantaneous signal e(t) is given by
e(t) = E(1 + m cos ωm t) cos(ωct + φ) (22)
where E is the peak amplitude of unmodulated carrier, m is
the modulation factor as defined below, 웆m is the frequency of
the modulating voltage (radians per second), 웆c is the carrier
frequency (radians per second), and ␾ is the phase angle of
the carrier (radians).
The instantaneous carrier amplitude is plotted as a func-
tion of time in Fig. 15. The modulation factor m is defined for
asymmetrical modulation in the following manner:
Emax − E
m= (upward or positive modulation) (23)
E
E − Emin
m= (downward or negative modulation)
E
(24)
The maximum downward modulation factor, 1.0, is reached
when the modulation peak reduces the instantaneous carrier
envelope to zero. The upward modulation factor is un-
limited.
334 MIXER CIRCUITS

e(t) Angle Modulation. Information can be transmitted on a

carrier by varying any of the parameters of the sinusoid in
Emax accordance with the modulating voltage. Thus, a carrier is
described by
E
Emin e(t) = Ec cos θ (26)

where ␪ ⫽ 웆ct ⫹ ␾.
This carrier can be made to convey information by modu-
lating the peak amplitude Ec or by varying the instantaneous
Modulation envelope phase angle ␪ of the carrier. This type of modulation is known
Figure 15. Amplitude-modulated carrier.
as angle modulation. The two types of angle modulation that
have practical application are phase modulation (PM) and fre-
quency modulation (FM).
In phase modulation, the instantaneous phase angle ␪ of
The modulation carrier described by Eq. (22) can be rewrit- the carrier is varied by the amplitude of the modulating sig-
ten as follows: nal. The principal application of phase modulation is in the
utilization of modified phase modulators in systems that
e(t) = E(1 + m cos ωm t) cos(ωct + φ) transmit frequency modulation. The expression for a carrier
mE phase-modulated by a single sinusoid is given by
= E cos(ωct + φ) + cos[(ωc + ωm )t + φ] (25)
2
mE e(t) = Ec cos(ωct + φ + φ cos ωm t) (27)
+ cos[(ωc − ωm )t + φ]
2
where ⌬␾ is the peak value of phase variation introduced by
Thus, the amplitude modulation of a carrier by a cosine wave modulation and is called the phase deviation, and 웆m is the
has the effect of adding two new sinusoidal signals displaced modulation frequency (radians per second).
in frequency from the carrier by the modulating frequency. In frequency modulation, the instantaneous frequency of
The spectrum of the modulated carrier is shown in Fig. 16. the carrier, that is, the time derivative of the phase angle
␪, is made to vary in accordance with the amplitude of the
modulating signal. Thus,

E 1 dθ
f = (28)
2π dt
Em Em When the carrier is frequency-modulated by a single sinusoid,
2 2
f = f RF +  f cos ωmt (29)
ωm ωm
where ⌬f is the peak frequency deviation introduced by modu-
lation. The instantaneous total phase angle ␪ is given by
ωm – ωm ωc ωm + ω m 
Frequency θ = 2π f dt + θ0 (30)
(a) f
θ = 2π f RFt + sin 2π f m t + θ0 (31)
E fm

The complete expression for a carrier that is frequency-modu-

lated by a single sinusoid is


f
e(t) = Ec cos ωtc + sin 2π f mt + θ0 (32)
fm

The maximum frequency difference between the modu-

lated carrier and the unmodulated carrier is the frequency
deviation ⌬f. The ratio of ⌬f to the modulation frequency f m
0 ωc Frequency
is known as the modulation index or the deviation ratio. The
degree of modulation in an FM system is usually defined as
Spectrum of Spectrum of modulated carrier the ratio of ⌬f to the maximum frequency deviation of which
modulating signal
the system is capable. Degree of modulation in an FM system
(b) is therefore not a property of the signal itself.
Figure 16. Frequency spectrum of an amplitude-modulated carrier: In digital wireless communication systems, Gaussian-
(a) carrier modulated by a sinusoid of frequency 웆m, (b) carrier modu- filtered minimum-shift keying (GMSK) is the most popular,
lated by a complex signal composed of several sinusoids. and four-level frequency-shift keying (4-FSK) and 앟/4-shifted

differential encoded quadriphase (or quadrature) phase-
shift keying (앟/4-DQPSK) are also used. GMSK and 4-FSK
are both frequency modulation, but 앟/4-DQPSK is phase mod-
ulation.
Pulse Modulation. In pulse-modulated systems, one or more
parameters of the pulse are varied in accordance with a mod-
ulating signal to transmit the desired information. The modu-
lated pulse train may in turn be used to modulate a carrier
in either angle or amplitude. Pulse modulation provides a
method of time duplexing, since the entire modulation infor-
mation of a signal channel can be contained in a single pulse
train having a low duty cycle, i.e., ratio of pulse width to in-
terpulse period, and therefore the time interval between suc-
cessive pulses of a particular channel can be used to transmit
pulse information from other channels.
Pulse-modulation systems can be divided into two basic
types: pulse modulation proper, where the pulse parameter
which is varied in accordance with the modulating signal is a
continuous function of the modulating signal, and quantized
pulse modulation, where the continuous information to be
transmitted is approximated by a finite number of discrete
values, one of which is transmitted by each single pulse or
group of pulses. The two methods are illustrated in Fig. 17.
Modulation of
pulse parameter
Instantaneous
modulating signal
(a)
Modulation of
pulse parameter
Instantaneous
modulating signal
(b)
Figure 17. Input versus output relationships of quantized and un-
quantized pulse-modulation systems: (a) unquantized modulation
system, (b) quantized modulation system.
MIXER CIRCUITS 335
Modulating signal
Quantized pulse code groups
Figure 18. Example of a quantized pulse-modulation system.
In quantized pulse modulation systems, the input function
can be approximated with arbitrary accuracy by increase of
the number of discrete values available to describe the input
function. An example of a quantized pulse modulation system
is shown in Fig. 18: the information is transmitted in pulse
code groups, the sequence of pulses sent each period indicat-
ing a discrete value of the modulating signal at that instant.
Typically, the pulse group might employ a binary number
code, the presence of each pulse in the group indicating a 1
or 0 in the binary representation of the modulating signal.
The principal methods for transmitting information by
means of unquantized pulse modulation are pulse-amplitude
modulation (PAM; see Fig. 19), pulse-width modulation
(PWM), and pulse-position modulation (PPM).
Frequency Translation
The most common form of radio receiver is the superhetero-
dyne configuration shown in Fig. 20(a). The signal input, with
a frequency 웆s, is usually first amplified in a tunable band-
pass amplifier, called the RF amplifier, and is then fed into a
circuit called the mixer along with an oscillator signal, which
is local to the receiver, having a frequency 웆p. The LO is also
Modulating signal
Pulse train
(a)
0 1 2 3 4 5 6 7 8 9 10 11
T T T T T T T T T T T
fm
Frequency
(b)
Figure 19. Pulse-amplitude modulation: (a) amplitude-modulated
pulse train, (b) frequency spectrum of the modulated pulse train.
336 MIXER CIRCUITS

ωs RF ωs ω s – ωp IF Audio
Mixer Demod.
amp. amp. amp.

ωs
Coupled
tuning
Local
oscill.

(a)

fm fm fm fm

Figure 20. (a) The superheterodyne con- fRF – fm fRF fRF + fm fRF – fLO fRF + fLO
figuration; frequency spectra of (b) the in-
put and (c) the multiplier output. (b) (c)

tunable and is ganged with the input bandpass amplifier so The input can be represented as in Fig. 20(b), with the carrier
that the difference between the input signal frequency and frequency term and an upper and a lower sideband, each side-
that of the LO is constant. band containing the modulation information.
In operation, the mixer must achieve analog multiplica- For a linear multiplier, each of the input components is
tion. With multiplication, sum and difference frequency com- multiplied by the LO input, and the output of the multiplier
ponents at 웆s ⫾ 웆p are produced at the output of the mixer. contains six terms, as shown in Fig. 20(c): the difference-fre-
Usually, the sum frequency is rejected by sharply tuned cir- quency carrier with two sidebands and the sum-frequency
cuits and the difference frequency component is subsequently carrier with two sidebands. The latter combination is usually
amplified in a fixed-tuned bandpass amplifier. The difference rejected by the bandpass of the IF amplifier.
frequency is called the intermediate frequency (IF), and the
fixed-tuned amplifier is called the IF amplifier. The advan-
tage of this superheterodyne configuration is that most ampli- ANALOG MULTIPLICATION
fication and outband rejection occurs with fixed-tuned cir-
cuits, which can be optimized for gain level and rejection. An analog multiplier can be used as a mixer. A multiplier
Another advantage is that the fixed-tuned amplifier can pro- inputs two electrical quantities, usually voltages but some-
vide a voltage-controlled gain to achieve automatic gain con- times currents, and outputs the product of the two inputs,
trol (AGC) with input signal level. In high-performance and/ usually currents but sometimes voltages. The product of two
or small-size receivers, the filtering in the IF amplifier is ob- quantities is derived from only the second-order term of the
tained with electromechanical crystal filters. transfer characteristic of the element, because the product
To formalize the mixer operation, assume that both the xy can be derived from only the second term of (x ⫹ y)2. The
input signal and the local oscillator output are unmodulated, second-order term is, for example, obtained from the inherent
single-tone sinusoids: exponential law for a bipolar transistor or the inherent
square law for a MOS transistor.
There are three methods of realizing analog multipliers:
Vs = Es cos(ωst) (33)
the first is by cross-coupling two variable-gain cells, the sec-
Vp = Ep cos(ωpt) (34) ond is by cross-coupling two squaring circuits, and the third
is by using a multiplier core. Block diagrams of these three
If the multiplier (mixer) has a gain constant K, the output is multiplication methods are shown in Fig. 21(a–c). For exam-
ple, the bipolar doubly balanced differential amplifier, the so-
K called Gilbert cell, is the first case, and utilizes two-quadrant
Vo = Es Ep [cos(ωs − ωp )t + cos (ωs + ωp )t] (35) analog multipliers as variable-gain cells. The second method
2
has been known for a long time and is called the quarter-
square technique. The third method is also based on the quar-
The difference frequency, 웆s ⫺ 웆p, is denoted by 웆if .
ter-square technique, because a multiplier core is a cell con-
If the input is a modulated signal, the modulation also is
sisting of the four properly combined squaring circuits.
translated to a band about the new carrier frequency, 웆if . For
example, if the input is amplitude-modulated,
Multipliers Consisting of Two Cross-Coupled Variable-Gain Cells
Vs = Es (1 + m cos ωmt) cos ωst The Gilbert Cell. The Gilbert cell, shown in Fig. 22, is the
m most popular analog multiplier, and consists of two cross-cou-
= Es cos(ωst) + Es cos(ωs − ωm )t (36)
2 pled, emitter-coupled pairs together with a third emitter-cou-
m pled pair. The two cross-coupled, emitter-coupled pairs form
+ Ep cos (ωs + ωm )t
2 a multiplier cell. The Gilbert cell consists of two cross-coupled
 MIXER CIRCUITS 337

∆I ogies. The operating frequency of the Gilbert cell was 500

MHz at most in the 1960s.
I+ I– The series connection of the two cross-coupled, emitter-
coupled pairs with a third emitter-coupled pair requires a
high supply voltage, more than 2.0 V. Therefore, many circuit
+ + + + +
Variable – + Variable design techniques for linearizing the low-voltage Gilbert cell
Vx Vy
gain cell gain cell have also been discussed.
– – – –

Modified Gilbert Cell with a Linear Transconductance Am-

plifier. The modified Gilbert cell with a linear transconduc-
tance amplifier in Fig. 23 possesses a linear transconductance
characteristic only with regard to the second input voltage
(a) Vy, because it utilizes a linear transconductance amplifier for
the lower stage. Low-voltage operation is also achieved using
the differential current source output system of two emitter-
+ + + I+
follower-augmented current mirrors. The general structure of
Vx X2 ∆I
– –
the mixer is a Gilbert cell with a linear transconductance am-
– I–
+ plifier, since the cross-coupled emitter-coupled pairs that in-
Vy put the LO signal possess a limiting characteristic. To achieve
– the desired low distortion, the differential pair normally used
as the lower stage of the cell is replaced with a superlinear
transconductance amplifier. In practice, the linear input volt-
+ +
age range of the superlinear transconductance amplifier at a
1.9 V supply voltage is 0.9 V peak to peak for less than 1%
X2
– – total harmonic distortion (THD) or 0.8 V for less than 0.1%
THD.
The differential output current of the modified Gilbert cell
(b) with a linear transconductance amplifier is
+
+ I+ I = I + − I − = (IC1 + IC3 ) − (IC2 + IC4 )
Vx

– Vx (38)
–
+ Input stage Four-transistor ∆I = 2GyVy tanh
+ multiplier core 2VT
Vy
– I–
–
(c)
VCC
Figure 21. Multiplier block diagrams: (a) built from two cross-cou-
pled variable-gain cells, (b) built from two cross-coupled squaring cir-
cuits, (c) built from a multiplier core and an input system.
RL RL

variable-gain cells, because the lower emitter-coupled pair

varies the transconductance of the upper cross-coupled, emit-
ter-coupled pairs.
Assuming matched devices, the differential output current
of the Gilbert cell is expressed as Q1 Q2 Q3 Q4

Vx
I = I + − I − = (IC13 + IC15 ) − (IC14 + IC16 )



Vx Vy (37)
= αF2 I0 tanh tanh
2VT 2VT
Q5 Q6
where 움F is the dc common-base current gain factor.
The differential output current of the Gilbert cell is ex- Vy
pressed as a product of two hyperbolic tangent functions.
Therefore, the operating input voltage ranges of the Gilbert
cell are both very narrow. Many circuit design techniques for
linearizing the input voltage range of the Gilbert cell have
Io
been discussed to achieve wider input voltage ranges.
In addition, the Gilbert cell has been applied to ultra-high-
frequency (UHF) bands of some tens of gigahertz using GaAs
heterojunction bipolar transistor (HBT) and InP HBT technol- Figure 22. Gilbert cell.
338 MIXER CIRCUITS

VCC

Io Io RL RL

Q8 Q11

Q5 Q6 Q1 Q2 Q4
Vy
Vx
Ry

Q7 Q10 Q12 Q9

RE RE RE RE

Figure 23. Modified Gilbert cell with a

linear transconductance amplifier.

where Gy ⫽ 1/Ry and the dc common-base current gain factor If each squaring circuit is a square-law element with an-
움F is taken as equal to one for simplification, since its value other parameter z, the identity becomes
is 0.98 or 0.99 in current popular bipolar technology.

 2
The product of the hyperbolic tangent function of the first 1
input voltage and the second input voltage of the linear trans- (ax + by + z)2 + (a − c)x + b − y+z
c
conductance amplifier is obtained.
− [(a − c)x + by + z]2 (41)

 2
Quarter-Square Multipliers Consisting 1
− ax + b − y + z = 4xy
of Two Cross-Coupled Squaring Circuits c
To realize a multiplier using squaring circuits the basic
idea is based on the identity (x ⫹ y)2 ⫺ (x ⫺ y)2 ⫽ 4xy or In Eqs. (40) and (41), the parameters a, b, c, and z can be
(x ⫹ y)2 ⫺ x2 ⫺ y2 ⫽ 2xy. The former identity is usually ex- canceled out.
pressed as MOS transistors operating in the saturation region can be
used as square-law elements. Four properly arranged MOS
1
[(x + y)2 − (x − y)2 ] = xy (39) transistors with two properly combined inputs produce the
4
product of two inputs in accordance with Eq. (22). Also, four
The quarter-square technique based on the above identity has properly arranged bipolar transistors with two properly com-
been well known for a long time. bined inputs produce the product of the hyperbolic functions
The two input voltage ranges and the linearity of the of the inputs. A cell consisting of four emitter- or source-com-
transconductances of the quarter-square multiplier usually mon transistors biased by a single cell tail current can be
depend on the square-law characteristics of the squaring cir- used as a multiplier core.
cuits and sometimes depend on the linearities of the adder
and subtractor in the input stage. A quarter-square multi- Bipolar Multiplier Core. Figure 24(a) shows a bipolar multi-
plier does not usually possess limiting characteristics with re- plier core. The individual input voltages applied to the bases
gard to both inputs. of the four transistors in the core can be expressed as V1 ⫽
aVx ⫹ bVy ⫹ VR, V2 ⫽ (a ⫺ 1)Vx ⫹ (b ⫺ 1)Vy ⫹ VR, V3 ⫽ (a ⫺
Four-Quadrant Analog Multipliers with a Multiplier Core 1)Vx ⫹ bVy ⫹ VR, V4 ⫽ aVx ⫹ (b ⫺ 1)Vy ⫹ VR. The differential
output current is expressed as
The multiplier core can be considered as four properly com-
bined square circuits. The multiplication is based on the iden- I = I + − I − = (IC1 + IC2 ) − (IC3 + IC4 )
tity


Vx Vy (42)
= αF I0 tanh tanh

 2 2VT 2VT
1
(ax + by)2 + (a − c)x + b − y
c

 2 (40) The parameters a and b are canceled out. The transfer func-
1 tion of the bipolar multiplier core is expressed as the product
− [(a − c)x + by] − ax + b −
2
y = 2xy
c of the two transfer functions of the emitter-coupled pairs. The
difference between Eq. (42) and Eq. (38) is only in whether
where a, b, and c are constants. the tail current value is multiplied by the parameter 움F or by
 MIXER CIRCUITS 339

∆I

I+ I–

Q1 Q2 Q3 Q4

aVx – bVy aVx + (b – 1)Vy

(a – 1)Vx + (b – 1)Vy (a – 1)Vx + bVy

VR Io

(a)

VCC

RL RL

VM1 VM2

Q1 Q2 Q3 Q4

Vx + Vx Vx

VR Io Vy

(b)

∆I

I+ I–

Vx R R
Q1 Q2 Q3 Q4
Vy R R R R

VR Io

(c)

Figure 24. Bipolar multiplier: (a) general circuit diagram of core, (b) the core with the simplest
combination of the two input voltages, (c) the bipolar multiplier consisting of a multiplier core
and resistive dividers.
 ∆I

I+ I–
M1 M3
aVx + bVy V1
M1 M2 M3 M4
1
Vx (a – c)Vx + (b – c )Vy V2
V3 V4
(a – c)Vx + bVy

1
Vy aVx + (b – c )V y

Io

Input system Multiplier core

(a)

∆I

I+ I–
M1 M4

M2 M4

Vx + Vx Vx

Vy

VR Io

(b)

VDD

M9 M10

M11 M12

∆I

M4 M3

M5 M6 M1 M2 M8 M7
Vx Vx

VR Ioo Io Ioo

(c)

Figure 25. MOS multiplier: (a) general circuit diagram of core (b) the core with the simplest
combination of the two input voltages, (c) MOS multiplier consisting of the multiplier core and
an active voltage adder.

340

Transmit
Baseband
data
Info. signal Data
source modulator
Frequency
synthesizer
Figure 26. Block diagram of communications system, showing modulation and demodulation.
its square. Therefore, a bipolar multiplier core consisting of a
quadritail cell is a low-voltage version of the Gilbert cell.
Simple combinations of two inputs are obtained when a ⫽
b ⫽ 
, a ⫽ 
and b ⫽ 1, and a ⫽ b ⫽ 1 as shown in Fig. 24(b).
In particular, when a ⫽ b ⫽ 1, resistive voltage adders are
applicable because no inversion of the signals Vx and Vy is
needed [Fig. 24(c)].
MOS Multiplier Core. Figure 25(a) shows the MOS four-
quadrant analog multiplier consisting of a multiplier core. In-
dividual input voltages applied to the gates of the four MOS
transistors in the core are expressed as V1 ⫽ aVx ⫹ bVy ⫹
VR, V2 ⫽ (a ⫺ c)Vx ⫹ (b ⫺ 1/c)Vy ⫹ VR, V3 ⫽ (a ⫺ c)Vx ⫹
bVy ⫹ VR, V4 ⫽ aVx ⫹ (b ⫺ 1/c)Vy ⫹ VR. The multiplication is
based on the identity of Eq. (41).
Ignoring the body effect and channel-length modulation,
the equations for drain current versus drain-to-source voltage
can be expressed in terms of three regions of operation as
ID = 0 (43a)
for VGS ⱕ VT, the off region,


V rity of the modulation–demodulation process.
ID = 2β VGS − VT − DS VDS (43b)
2 Frequency synthesizers are ubiquitous building blocks in
for VDS ⱕ VGS ⫺ VT, the triode region, and
ID = β(VGS − VT )2 (43c)
for VGS ⱖ VT and VDS ⱖ VGS ⫺ VT, the saturation region, where
웁 ⫽ 애(CO /2)(W/L) is the transconductance parameter, 애 is the
effective surface carrier mobility, CO is the gate oxide capaci-
tance per unit area, W and L are the channel width and
length, and VT is the threshold voltage.
The differential output current is expressed as
I = I + − I − = (ID1 + ID2 ) − (ID3 + ID4 )
(44)
= 2βVxVy (Vx2 + Vy2 + |VxVy | 5 I0 /2β )
The parameters a, b, and c are canceled out. Four properly
arranged MOS transistors with two properly combined inputs
MIXER CIRCUITS 341
Receive
Data Info.
modulator source
Frequency
synthesizer
produce the product of two input voltages. Simple combina-
tions of two inputs are obtained when a ⫽ b ⫽ 
and c ⫽ 1,
a ⫽ 
and b ⫽ c ⫽ 1, and a ⫽ b ⫽ c ⫽ 1 as shown in Fig. 25(b).
Figure 25(c) shows a CMOS four-quadrant analog multi-
plier consisting of only a multiplier core and an active volt-
age adder.
In addition, a multiplier consisting of the multiplier core
in Fig. 25(a) and a voltage adder and subtractor has been
implemented with a GaAs MESFET IC, and a useful fre-
quency range from dc to UHF bands of 3 GHz was obtained
for a frequency mixer operating on a supply voltage of 2 or
3 V.
RADIO-FREQUENCY SIGNAL AND LOCAL OSCILLATOR
Figure 26 shows a block diagram of a communication system,
showing modulation and demodulation. A wireless communi-
cation system will usually consists of an information source,
which is modulated up to RF or microwave frequencies and
then transmitted. A receiver will take the modulated signal
from the antenna, demodulate it, and send it to an informa-
tion ‘‘sink,’’ as illustrated in Fig. 26. The rate at which infor-
mation can be sent over the channel is determined by the
available bandwidth, the modulation scheme, and the integ-
wireless communication systems, since they produce the pre-
cise reference frequencies for modulation and demodulation
of baseband signals up to the transmit and/or receive fre-
quencies.
A simple frequency synthesizer might consist of a transis-
tor oscillator operating at a single frequency determined by a
precise crystal circuit. Tunable transistor frequency sources
Va
Vamp
Frequency
Time
synthesizer
T
Figure 27. Block diagram of frequency synthesizer producing single-
tone sinusoidal output.
342 MIXER CIRCUITS
Reference
÷Q
oscillator
Figure 28. Indirect frequency synthe-
sizer using a phase-locked loop.
rely on variations in the characteristics of a resonant circuit
to set the frequency. These circuits can then be embedded in
phase-locked loops (PLLs) to broaden their range of operation
and further enhance their performance.
A representative view of a frequency synthesizer is given
in Fig. 27 which shows a generic synthesizer producing a sin-
gle tone of a given amplitude that has a delta-function-like
characteristic in the frequency domain.
Indirect frequency synthesizers rely in feedback, usually in
the form of the PLL, to synthesize the frequency. A block dia-
gram of a representative PLL frequency synthesizer is shown
in Fig. 28. Most PLLs contain three basic building blocks: a
phase detector, an amplifier loop filter, and a voltage-con-
trolled oscillator (VCO). During operation, the loop will ac-
quire (or lock onto) an input signal, track it, and exhibit a
fixed phase relationship with respect to the input. The output
frequency of the loop can be varied by altering the division
ratio (N) within the loop, or by tuning the input frequency
with an input frequency divider (Q). Thus, the PLL can act
as a broadband frequency synthesizer.
FREQUENCY SYNTHESIZER FIGURES OF MERIT
An ideal frequency synthesizer would produce a perfectly
pure sinusoidal signal, which would be tunable over some
specified bandwidth. The amplitude, phase, and frequency of
the source would not change under varying loading, bias, or
temperature conditions. Of course, such an ideal circuit is im-
possible to realize in practice, and a variety of performance
measures have been defined over the years to characterize the
deviation from the ideal.
Noise
The output power of the synthesizer is not concentrated exclu-
sively at the carrier frequency. Instead, it is distributed
;yy;
around it, and the spectral distribution on either side of the
carrier is known as the spectral sideband. This is illustrated
schematically in Fig. 29. This noise can be represented as
Ps
Signal
Pssb
Sideband Ps
noise
Power
Pssb
fm
f0 Frequency
1 Hz
Figure 29. Phase noise specification of frequency source. The noise
is contained in the sidebands around the signal frequency at f 0.
Phase Loop
VCO Output
detector filter
÷N
modulation of the carrier signal, and resolved into AM and
FM components. The AM portion of the signal is typically
smaller than the FM portion.
FM noise power is represented as a ratio of the power in
some specified bandwidth (usually 1 Hz) in one sideband to
the power in the carrier signal itself. These ratios are usually
specified in ‘‘dBc/Hz’’ at some frequency offset from the car-
rier. The entire noise power can be integrated over a specified
bandwidth to realize a total angular error in the output of the
oscillator, and oscillators are often specified this way.
Tuning Range
The tuning range of an oscillator specifies the variation in
output frequency with input voltage or current (usually volt-
age). The slope of this variation is usually expressed in mega-
hertz per volt. In particular, the key requirements of oscilla-
tor or synthesizer tuning are that the slope of the frequency
variation remain relatively consistent over the entire range of
tuning and that the total frequency variation achieve some
minimum specified value.
Frequency Stability
Frequency stability of an oscillator is typically specified in
parts per million per degree centigrade (ppm/⬚C). This param-
eter is related to the Q of the resonator and the frequency
variation of the resonator with temperature. In a free-run-
ning system this parameter is particularly important,
whereas in a PLL it is less so, since an oscillator that drifts
may be locked to a more stable oscillator source.
Harmonics
Harmonics are output from the oscillator synthesizer that oc-
cur at integral multiples of the fundamental frequencies.
They are typically caused by nonlinearities on the transistor
or other active device used to produce the signal. They can be
minimized by proper biasing of the active device and design
of the output matching network to filter out the harmonics.
Harmonics are typically specified in ‘‘dBc’’ below the carrier.
Spurious Outputs
Spurious outputs are outputs of the oscillator synthesizer
that are not necessarily harmonically related to the funda-
mental output signal. As with harmonics, they are typically
specified in ‘‘dBc’’ below the carrier.
BIBLIOGRAPHY
1. A. A. Abidi, Low-power radio-frequency IC’s for portable commu-
nications, Proc. IEEE, 83: 544–569, 1995.
2. L. E. Larson, RF and Microwave Circuit Design for Wireless Com-
munications, Norwood, MA: Artech House, 1996.
 MOBILE COMMUNICATION 343

3. N. Camilleri et al., Silicon MOSFETs, the microwave device tech- 27. B. Razavi, Challenges in the design of frequency synthesizers for
nology for the 90s. In 1993 IEEE MTT-S Int. Microw. Symp. Dig., wireless applications. Proc. IEEE 1997 Custom Integrated Circuits
June 1993, pp. 545–548. Conf., May 1997, pp. 395–402.
4. C. Tsironis, R. Meierer, and R. Stahlman, Dual-gate MESFET
mixers, IEEE Trans. Microw. Theory Tech., MTT-32: 248–255, KATSUJI KIMURA
March 1984. NEC Corporation
5. S. A. Maas, Microwave Mixers, 2nd ed., Norwood, MA: Artech
House, 1993.
6. J. M. Golio, Microwave MESFETs & HEMTs, Norwood, MA: Ar-
tech House, 1991.
MIXERS. See MULTIPLIERS, ANALOG; MULTIPLIERS, ANALOG
CMOS.
7. F. Ali and A. Gupta (eds.), HEMTs & HBTs: Devices, Fabrication,
and Circuits, Norwood, MA: Artech House, 1991. MMIC AMPLIFIERS. See MICROWAVE LIMITERS.
8. D. Haigh and J. Everard, GaAs Technology and its Impact on MOBILE AGENTS. See MOBILE NETWORK OBJECTS.
Circuits and Systems, London: Peter Peregrinus, 1989.
9. D. O. Pederson and K. Mayaram, Analog Integrated Circuits for
Communication—Principles, Simulation and Design, Norwell,
MA: Kluwer Academic, 1991.
10. W. Gosling, R ⭈ A ⭈ D ⭈ I ⭈ O Receivers, London: Peter Peregrinus,
1986.
11. K. Murota and K. Hirade, GMSK modulation for digital mobile
telephony, IEEE Trans. Commun., COM-29: 1044–1050, 1981.
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nications with a linear modulation method, IEEE J. Selected
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13. J. Eimbinder, Application Considerations for Linear Integrated
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14. H. E. Jones, Dual output synchronous detector utilizing transistor-
ized differential amplifiers, U.S. Patent No. 3,241,078, March
15, 1966.
15. B. Gilbert, A precise four-quadrant analog multiplier with sub-
nanosecond response, IEEE J. Solid-State Circuits, SC-3 (4): 365–
373, 1968.
16. P. R. Gray and R. G. Meyer, Analysis and Design of Analog Inte-
grated Circuits, New York: Wiley, 1977, pp. 667–681.
17. K. W. Kobayashi et al., InAlAs/InGaAs HBT X-band double-bal-
anced upconverter, IEEE J. Solid-State Circuits, 29 (10): 1238–
1243, 1994.
18. F. Behbahani et al., A low distortion bipolar mixer for low voltage
direct up-conversion and high IF frequency systems. Proc. IEEE
1996 Bipolar Circuits Technol. Meet., Sept. 1996, pp. 50–52.
19. H. Song and C. Kim, An MOS four-quadrant analog multiplier
using simple two-input squaring circuits with source-followers,
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20. K. Kimura, A unified analysis of four-quadrant analog multipli-
ers consisting of emitter and source-coupled transistors operable
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737, 1993.
21. K. Bult and H. Wallinga, A CMOS four-quadrant analog multi-
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22. K. Kimura, An MOS four-quadrant analog multiplier based on
the multitail technique using a quadritail cell as a multiplier
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448–454, 1995.
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ended voltage output and improved temperature performance,
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674 MULTIPLIERS, ANALOG
MULTIPLIERS, ANALOG
The multiplication of continuous-time continuous-amplitude
analog signals has been of fundamental importance since the
earliest days of electronic systems, notably in computing and
nonlinear control systems, modulation, correlation, the deter-
mination of signal power, variable-gain amplifiers, and other
signal management functions. Many ingenious multiplier
methods have been devised during the past fifty years, most
of which have fallen into obsolescence (1,2).
In contemporary electronics, two-variable analog multipli-
cation, and the closely related function of division, are invari-
ably implemented by inexpensive monolithic integrated cir-
cuits whenever cost, low power consumption, small size,
accuracy, and high speed are essential requirements. By far
the largest proportion of current commercial products utilize
bipolar junction transistor (BJT) technologies and invoke
translinear principles (3), providing dependable, accurate,
complete solutions that are easy to use. When optimized for
accuracy, using special circuit techniques and laser trimming,
static errors may be ⫾0.05% full scale (FS) or better, with
nonlinearity errors (deviation from the ideal function) as low
as ⫾0.01%. Translinear multipliers may also be optimized for
very high speed, which can extend up to the limits of the tech-
nology; a 3 dB bandwidth of over 30 GHz is nowadays possible
in special applications such as wideband variable-gain cells.
J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.
In principle, monolithic multipliers can provide both very
high static accuracy and very high bandwidth in a single de-
vice, but such a need is rare, and products providing this ca-
pability are not generally available. A typical integrated cir-
cuit (IC) four-quadrant multiplier (one that generates the
true algebraic product for inputs of either polarity) usually
provides a compromise solution, with accuracy–bandwidth
combinations of the order of 0.1% and 10 MHz (found, for ex-
ample, in the Analog Devices AD734), or 3% and 1 GHz
(AD834).
Analog multiplier techniques are widely used in gain-con-
trol applications. Two-quadrant multipliers often serve this
function, with careful optimization to meet difficult and con-
flicting performance objectives. Occasionally, dual-channel
operation is provided, as in the 60 MHz AD539. The voltage-
controlled amplifier (VCA) function is often better addressed
by a different class of circuits, particularly those that provide
an exponential relationship between the control variable and
the resulting gain, thus providing a linear-in-dB control law.
Other multiplier applications require a response only to
inputs of one polarity. These are called one-quadrant multipli-
ers. Many of the cells proposed in contemporary research pa-
pers are in this class and need considerable elaboration with
auxiliary circuitry to permit operation in two or four quad-
rants. The careful choice and optimization of the root struc-
ture is therefore of critical importance, and a few solutions
have gained preeminence.
A mixer is sometimes regarded as an analog multiplier,
optimized by close attention to noise and intermodulation for
use in frequency-translation applications. While this view is
useful in thinking about the basic function, mixer designs dif-
fer markedly. For example, the response to one of its two in-
puts (the signal at the local oscillator port) desirably approxi-
mates a binary (switching) function, and the mixer ideally
performs only the sign-reversal (or phase-alternation) func-
tion on the other input (the carrier). This can also be viewed
as the multiplication of the analog input signal by all the
terms in the Fourier expansion of a square wave.
While the time-domain and amplitude-domain behavior of
analog multipliers are usually of greatest interest, mixers are
more often assessed by their performance in the frequency
and power domain, with a strong emphasis on two dominant
imperatives: the minimization of spurious intermodulation
terms, and the minimization of noise. Thus, from a practical
perspective, it is unwise to view mixers in the same terms as
analog multipliers. The term modulator is often used, though
modulators (and demodulators) may be fully linear multi-
pliers.
Multiplication of two binary variables is implemented by
the exclusive-OR logic function, and this operation is at the
heart of a modern digital multiplier–accumulator cell. With
the advent of inexpensive analog-to-digital and digital-to-ana-
log converters and the microprocessor, many applications for-
merly solved in the analog domain have migrated to digital
implementations. The benefits include greater stability, re-
configurability and increased flexibility, and easy integration
into a software-governed hierarchy. Modern digital signal pro-
cessing (DSP), using specialized very large scale integration
(VLSI) multiplication algorithms, has taken this trend a step
further. However, the time quantization of DSP approaches
precludes operation at high speeds.

MULTIPLIER BASICS
An ideal multiplier generates the product of two time-varying
input variables (rarely more), historically identified as X and
Y. In most practical multipliers, the inputs and output (here
labeled W) are voltages. Occasionally the exterior variables
are in the form of currents; however, the interior variables
are very often in this form. The function is described by the
equation
VX
VW = V (1)
VU Y
where VW is the output, VX and VY are the two inputs, and
VU will here be called the scaling voltage. VU is of critical im-
portance in establishing the accuracy of the function. Equa-
tion (1) is written in a way which emphasizes that VX is the
variable whose voltage range is determined by VU. A more
useful multiplier structure allows the addition of a further
variable, VZ, to the output:
VX
VW = V + VZ (2)
VU Y
VU may also be varied from an input interface in some IC
multipliers. Thus, in its most general implementation, Eq. (2)
describes a versatile multiplier–divider–adder element. Its
practical value depends on the speed and accuracy with which
it implements this function, the noise levels at input and out-
put, the harmonic distortion under various drive conditions,
and detailed practical issues such as the impedance at its in-
terfaces (often differential), its ability to drive a load, the sup-
ply voltage and current-consumption requirements, its size,
its cost, and the like.
A basic consideration relates to the number of quadrants
in which a multiplier can operate (Fig. 1). Some multipliers
provide operation in only one quadrant, that is, all variables
are unipolar. These are useful in specialized embedded analog
computing applications; for example, in certain temperature-
compensation applications (4), a unipolar output V⬘C(T) must
be proportional to absolute temperature (PTAT) as well as to
the primary controlling variable VC, which is independent of
temperature:
(+)VC T (differencing) amplifiers, by implementing the even more gen-
MULTIPLIERS, ANALOG 675
where VR is a reference voltage that scales the controlling (in-
put) function while V0 is a second reference voltage that scales
the output, T is the system temperature, and T0 is a reference
temperature, often taken as 300 K (앒27⬚C). The robust design
of all nonlinear analog circuits is characterized by the need
for careful consideration of such detailed scaling attributes.
In a two-quadrant multiplier, commonly used in gain-con-
trol applications, one of the two inputs is unipolar, that is,
constrained to a single polarity, while the other input and the
output are bipolar, as is the case for a VCA. This functional
restriction does not represent a concession to structural com-
plexity, but rather has as its objective the improvement of
performance in gain-control applications.
In a four-quadrant multiplier, the sign of VW is algebrai-
cally correct for all sign combinations of VX and VY, that is,
for the quadrants (⫹ ⫻ ⫹), (⫹ ⫻ ⫺), (⫺ ⫻ ⫹), and (⫺ ⫻ ⫺).
This may appear to be the most versatile case and could be
used in any application, but in practice it will not perform
optimally in all of them. For example, a two-quadrant multi-
plier, used as a VCA, can provide output-referred noise and
distortion that is proportional to the magnitude of the unipo-
lar input, while in a four-quadrant type these remain almost
constant for a given magnitude of input on the bipolar (sig-
nal) channel.
Equation (1) indicated that the input VX is associated with
a divisor VU, and the full-scale value of VX will be determined
by this denominator. When VU is arranged to be controllable
from an interface, analog division is implemented. In some
practical IC products, the range of allowable values for VU
may be quite large. For example, the AD734 provides a
1000 : 1 range (⫹10 mV to ⫹10 V) at its high-impedance VU
interface. As a fixed-scale multiplier a high-precision refer-
ence voltage, generated by a buried zener, laser-trimmed to
0.01%, provides VU. As well as its utility in contemporary ana-
log computing applications, where the value lies in the mea-
surement of a ratio of voltages over a wide range of absolute
values, the division function may also be used in gain-control
applications, where VX represents the signal and VU is the
(one-quadrant) gain-control voltage, providing a gain range of
over 60 dB.
Many monolithic multipliers use a differential cell topology,
and can process differential signals at their X and Y inter-
faces, with high common-mode rejection. These versatile de-
vices add features normally only found in instrumentation
(+)VC (T ) = V (3) eral function
(+)VR 0 T0
VX 1 − VX 2
VW = (VY 1 − VY 2 ) + VZ (4)
VU
+Y
In the most versatile IC dividers, the VU input interface would
also be differential, and allow this voltage to change sign
(that is, support four-quadrant division). Because of its lim-
ited utility and the basic problem of the singularity at VU ⫽
1Q
0, this capability is generally not provided in commercial
–X +X products. However, the function is practicable, and a method
4Q 2Q will later be shown for its implementation and use in fil-
terless demodulation.
During the 1970s and 1980s, the supply voltages for analog
multipliers invariably were ⫾15 V, the voltage ranges for VX,
–Y
VY and VW were ⫾10 V FS, and VU was 10 V. During recent
Figure 1. Multiplier operating quadrants. years, supply voltages have dropped, first to ⫾5 V, heralding
676 MULTIPLIERS, ANALOG
FS input and output voltages of typically ⫾2 V (with a VU of
1 V to 2 V) and more recently to single supplies of either ⫹5
V or ⫹3 V, necessitating some modification in the approach
to full four-quadrant operation, for example, by providing a
differential output as well as differential inputs. Current-
mode interfaces for the signals are sometimes used to cope
with these limitations.
Contemporary analog multiplier developments are moving
away from generic, textbook objectives toward system-specific
embodiments, with increasing emphasis on extending the
high-frequency accuracy, lowering spurious nonlinearities,
and reducing noise levels. The development of high-perfor-
mance analog multipliers remains a specialized art; only a
few IC companies have the skills to cope with the numerous
arcane design details. Cell developments being reported in
the professional journals, particularly those promoting the
use of complementary metal–oxide–semiconductor (CMOS)
technologies, are often not fully in touch with the imperatives
of modern systems and their challenging requirements.
MULTIPLIER ERRORS
The absolute accuracy of analog multipliers has traditionally
been defined in terms of the error between the actual and
ideal output relative to the FS value of the output. This is
invariably a more optimistic metric than the error specified
in terms of the actual output. Further, it is common practice
to emphasize the static accuracy, obtained under dc or low-
frequency conditions. The dynamic errors at realistic op-
erating frequencies are then layered over the static specifica-
tions, using similar metrics to those for linear amplifiers,
such as 3 dB bandwidth, rise and fall times, slew rate, etc.
These practices came about largely because of the context
within which high-accuracy multipliers were historically de-
veloped: in analog simulators, in military applications, and in
industrial plant control and various types of instrumentation,
prior to the advent of the microprocessor. The FS static accu-
racy remains a key parameter in defining the performance of
a multiplier.
The most accurate monolithic multipliers—using translin-
ear techniques and high-performance complementary bipolar
(CB) processes with silicon-on-insulator (SOI) fabrication,
temperature-stable thin-film resistors, and laser trimming for
precise calibration against NBS-traceable standards—
achieve a guaranteed absolute accuracy of ⫾0.1% FS, with
⫺80 dBc harmonic distortion. Selected components can main-
tain a short-term accuracy of ⫾0.02% FS, which is practically
the state of the art in analog multiplication, using any
known technique.
Errors arise from many mechanisms, and are of several
types. Some, such as the linear errors, can usually be attrib-
uted to component mismatches; nonlinear errors can be
caused by mismatches in device size and in current density;
dynamic errors are due to the finite response time of these
devices and to parasitic signal coupling across them. While
these may be captured in mathematical expressions, little in-
sight is gained from such, and they become particularly enig-
matic when the modeling of all of the nonlinear and dynamic
effects is attempted. A more useful approach is to consider
the linear, nonlinear, and dynamic errors separately.
Analog
VXO multiplier
VX ′
VX
′
VW VW
VY ′
VY VWO
VYO V ′U = VU + VUO
Embedded reference
Figure 2. Linear error sources in a multiplier.
LINEAR ERROR SOURCES
There are four linear error sources in an analog multiplier,
identified in Fig. 2. First is the uncertainty, VUO, in the scaling
voltage VU, equivalent to a gain error. Contemporary mono-
lithic multipliers often use a bandgap reference to provide
VU. Without trimming, these can achieve an absolute accuracy
of ⫾2% and a temperature coefficient of ⫾50 ⫻ 10⫺6 /⬚C. Using
trimming, the initial and long-term accuracy may be as high
as ⫾0.1% or better, with a temperature coefficient of under
⫾5 ⫻ 10⫺6 /⬚C. For higher accuracies, some type of breakdown
device is used; their use is limited to applications in which at
least one supply voltage is available that exceeds the break-
down voltage of the reference element (about 8 V). Monolithic
circuits may use a buried-zener reference, whose voltage can
be adjusted to within ⫾0.01% using laser-wafer trimming in
high-volume production, with commensurate temperature
stability and long-term stability.
The second linear error is the dc offset at the output of the
multiplier, VWO. Consider a multiplier having VU ⫽ 10 V and
full-scale X and Y inputs of 10 V. When both inputs are 1 V
(that is, 10% of FS), the output should be 100 mV. While an
output offset of VUO ⫽ 10 mV is only 0.1% of the FS output, it
is 10% of the actual output. Some applications of multipliers
are severely affected by this output-referred dc error. How-
ever, in a VCA, where the output will invariably be ac-cou-
pled, this offset is inconsequential. In considering the specifi-
cations of a multiplier, one must pay careful attention to all of
the many detailed requirements of each specific application.
The two remaining linear errors are those due to the input
offsets, VXO and VYO. An input applied to one of the two inputs
will generate a spurious output when the second input is
nominally zero. Thus, if a 10 V sinusoid is applied to the X
input, and the Y input is set to zero but exhibits an internal
offset of VYO ⫽ 10 mV, there will be a residual sine output of
amplitude 10 mV when VU ⫽ 10 V. This is called static feed-
through and is commonly specified either in fractional or deci-
bel terms. In the above case, the feedthrough of 10 mV is
0.1%, or 60 dB below the potential full-scale output of 10 V.
It is important, however, to make a distinction between the
feedthrough due to dc offsets and that due to parasitic signal
coupling at actual operating frequencies. Residual nonlineari-
ties in the multiplier may also cause signal feedthrough.
NONLINEAR ERRORS
When all linear errors have been eliminated by exact calibra-
tion of the scaling voltage VU and by nulling the offsets associ-
 MULTIPLIERS, ANALOG 677

ated with VX, VY, and VW, some errors will remain. These may +0.025%
be called irreducible errors, to the extent that they are diffi-
cult for the user to eliminate in most practical applications.
However, there are many ways by which these may be low-
ered in a production context, using careful design and IC lay- VX = 3.5 V
out techniques, laser trimming, and special packaging. They
are sometimes addressed using a multiplexed analog-to-digi-
tal converter (ADC) for VX and VY, followed by digital multipli-
cation in a microprocessor and digital-to-analog conversion

Absolute error
back to the voltage domain, in which case the residual nonlin-
earities will usually be less than a least-significant bit (LSB).
This approach is appealing for low-frequency instrumenta- VX = 3.0 V
tion-grade multiplication, but not in applications where band-
width, power consumption, size, and cost are dominant con-
siderations.
The IC multiplication method most widely used today is VX = 2.5 V
based on the translinear principle, and the following com-
ments regarding residual nonlinear errors are with this im-
plementation in mind. It is found that, for the commonly used
two- and four-quadrant types, one error is essentially quad-
ratic in form, while another is essentially cubic. Quadratic –0.025%
errors can be largely traced to VBE matching errors in the core +2.0 V +3.0 V
of the four-quadrant multiplier. Cubic errors arise due to mis- VY
matches in current density and are minimized by the optimal
Figure 4. Typical multiplier crossplot.
choice of topology, device sizes, and bias conditions. High-vol-
ume production experience over a period of more than two
decades shows that residual nonlinearities of under 0.1% of
of the reference multiplier—is displayed on an oscilloscope,
FS can be routinely achieved without trimming.
generating an insight-rich real-time display. Using a high
Since an analog multiplier has two independent inputs,
vertical sensitivity, errors as small as 0.01% of FS are readily
the output and the error generate surfaces, formally requiring
visible. One of the two inputs is swept linearly over its full
three-dimensional representation. Here again, no special in-
range; this input also provides the horizontal sweep voltage
sights are gained by using such in examining the behavior of
for the oscilloscope. The other input is stepped through sev-
a multiplier. Instead, an excellent practical assessment of
eral spot values (typically ⫺100%, ⫺50%, zero, ⫹50% and
static accuracy is provided by a crossplot (5). The term arose
⫹100% of FS) by automatically incrementing one step for
in a testing context, in which a multiplier of unknown quality
each sweep of the first input. The sweep times are chosen to
was compared with one of impeccable credentials.
ensure a flicker-free display, but not much faster, since dy-
In the classical crossplot technique (Fig. 3), both multipli-
namic errors quickly become dominant, even in a 1 MHz
ers are excited by the same inputs (whose precise calibration
bandwidth multiplier. The X and Y inputs can then be
is unimportant), and the difference in the outputs of the two
swapped for a different view of the errors. Insight into inter-
units—that is, the error relative to the internal calibration
preting the multiplier errors displayed in a crossplot can be
acquired rapidly after a little practice.
In contemporary production practice, when multipliers of
Slow time scale the highest accuracy are to be characterized, the input volt-
+10 V ages are generated by computer-programmable sources trace-
+5 V
able to NBS standards, and the output is measured by a high-
–5 V
–10 V grade digital voltmeter. The error is then calculated in the
X Analog
VW1 host computer, which may generate a crossplot as a graphical
VX multiplier W entity. Figure 4 shows a typical result for a state-of-the-art
being Oscilloscope
Y tested
laser-trimmed multiplier; the peak error is seen to be within
in X–Y mode ⫾0.02% over the range of X and Y input values (6).
+
Σ Vert.
– DYNAMIC ERRORS
X
Accurate Horiz.
reference W The errors discussed so far relate to slowly varying inputs.
VY VW2
multiplier Dynamic errors arise when the inputs are varying rapidly and
Y
+10 V may be generated in the input interfaces of the multiplier, in
the core, or in the output stage. Since multipliers may exhibit
different response times on the X and Y input channels (that
–10 V
is, different phase angles), their dynamic errors need to be
Fast time scale
measured separately. When a high degree of phase matching
Figure 3. Typical crossplot measurement technique. is required in the response from the X and Y inputs, two mul-
678 MULTIPLIERS, ANALOG
tipliers can be used (either in cell form or as complete ICs)
with their two pairs of input interfaces cross-connected and
their outputs summed. The key dynamic property of a multi-
plier is its small-signal bandwidth, the frequency at which
the output amplitude is 3 dB below its midband value. The
measurement should be made with one of the input channels
receiving the ac test signal, while the other receives a fixed
dc level. For modern commercial IC multipliers, values range
from 1 MHz to 1 GHz, but operation of bipolar multiplier cells
at 13 GHz (7) and 32.7 GHz (8) is currently feasible in auto-
matic gain control (AGC) applications.
The individual bandwidths of the input circuits, the multi-
plying core, and the output stage are often different, and de-
sign optimization depends on the requirements. Consider a
signal-squaring application being implemented by a four-
quadrant multiplier, with the two input channels connected
in parallel and sinusoidally excited. This generates an output
from the multiplier core at twice the input frequency, plus a
dc component. To extract the ac component, as in a frequency
doubler, the output bandwidth must be at least twice that of
the input frequency; however, if we wish to determine the
mean squared value, as in a power measurement application,
the output bandwidth must be much lower, requiring a post-
multiplication low-pass filter to perform averaging.
It is often found that the ac response from one of the two
multiplier inputs depends in some complex way on the dc
value of the other input, due to another type of dynamic error,
namely, high-frequency (HF) feedthrough. This occurs when
the effective gain of a multiplier is low, and results in the ac
output being (usually) larger than the dc gain value would
predict. Two-quadrant multipliers may show this problem
more noticeably, because they are sometimes designed to pro-
vide a very high gain-control range (as much as 80 dB) and
will therefore be operating in an attenuation mode for much
of this range. Even minute parasitic capacitances can lead to
large feedthrough errors at, say, 100 MHz and above. The
solution lies in the use of special cell topologies for HF multi-
plication.
The notion of vector error arose in computing applications.
This is only another way of describing errors due to the finite
bandwidth of the device, but taking phase lag into account.
In a system characterized by a single-pole response, a dy-
namic error of 1% will occur at a frequency of 1% of the ⫺3
dB bandwidth, and is closely proportional below this fre-
quency. Thus, a multiplier having a 10 MHz bandwidth ex-
hibits a 0.1% vector error at 10 kHz, while the output magni-
tude is in error by only ⫺0.005%. Practical wideband
multipliers rarely conform to a simple one-pole response,
however, and this metric is not often invoked in contemporary
applications of multipliers.
In multipliers based on pulse-averaging methods, there is
a residual periodic ripple on the output, and vector errors are
large, due to the use of multipole filters. Further types of dy-
namic error will be found in multipliers implemented using
hybrid analog–digital techniques, due to time quantization.
Slew-rate (dV/dt) limitations generate dynamic errors under
large-signal conditions, and increase settling time. Overload-
recovery effects may also arise: a well-designed multiplier will
not ‘‘fold over’’ when the inputs greatly exceed the nominal
FS value, and will recover quickly when the overdrive condi-
tion is removed.
Finally, multiplier noise needs consideration. This is usu-
ally specified in terms of the output noise spectral density (so
many nV/Hz1/2). In translinear multipliers, the dominant
wideband noise source is the core: because of the high effec-
tive gain to the output, multiplier noise will invariably be
much higher than in typical IC amplifiers. In multipliers us-
ing MOS technologies, there is a significant increase at low
frequencies, due to 1/f mechanisms. In a multiplier used for
gain-control purposes, this may cause modulation noise.
HISTORICAL TECHNIQUES
The earliest analog multipliers were electromechanical (1). In
a servomultiplier (Fig. 5) one of the two inputs, VX, deter-
mined the relative angular position X of a shaft. A first poten-
tiometer, P1, on this shaft, biased by a dc voltage, which can
be equated to the denominator voltage VU in Eq. (1), gener-
ated the voltage VX ⫽ XVU. Thus, the shaft angle X was pro-
portional to VX /VU. A second potentiometer, P2, whose excita-
tion was provided by VY, generated the output (VX /VU)VY. The
static accuracy was determined by VU and the matching of the
X and Y potentiometers. The response time to the X input,
typically 100 ms to 1 s, was determined by the inertia of the
mechanical system. The response bandwidth of the Y input
was limited by the ac behavior of the potentiometers (which
were often wire-wound resistance elements, and thus very in-
ductive) and associated circuitry; it extended to at most a
few megahertz.
Mechanical servomultipliers are essentially obsolete, but
in 1975 Gilbert (9) described a novel solid-state realization, in
which the position of a rotating shaft was mimicked by the
angular position of a carrier domain, a narrow region of
highly localized minority carrier injection from a semicircular
emitter of a bipolar semiconductor structure. The track of the
mechanical potentiometer was replaced by the resistive col-
lector region. Smith described a second-generation rotational
design (10). In more recent BiCMOS embodiments of this
principle the domain moves linearly, in a long, narrow n-type
emitter, in response to the X input. Its position 0 ⬍ X ⬍ LE is
precisely determined by a parabolic voltage profile induced in
the p-type base-region, which also serves as a resistor and as
the drain of the superintegrated PMOS devices, as shown in
Shaft
Motor
Error VU VY
amp
Output
P1 P2
buffer
VX X VXVY/VU
Ground
Figure 5. Electromechanical servomultiplier.
 MULTIPLIERS, ANALOG 679

L/R base p-type region acts n-type n-type ers). The effective value of VU is determined by these gm’s, the
contacts as PMOS source emitter buried load resistors RL, and A, the voltage gain of the buffer ampli-
PMOS gate (poly-Si) layer
fier. Note that the squaring function implies an embedded
voltage reference VR, a fundamental requirement, since the
basic scaling demands of Eq. (1) must be met. The source of
this voltage, which dominates the accuracy, is not always
made clear in some descriptions of circuit operation.
MOS transistors are said to exhibit a square-law relation-
ship between the channel current and the gate–source volt-
age, when operating in the saturation region. Many of the an-
p-type region simultaneously serves as the alog multiplier cells devised for CMOS implementation
L/R collector npn base, the PMOS drain, and a resistor
contacts during the 1980s depended on this notion. Here, the denomi-
nator VU is traceable to device parameters that are not accu-
(a)
rately known or well controlled. Furthermore, the basic rela-
tionship is far from square-law for modern short-channel
Carrier transistors, which have other error sources (for example,
domain Domain can be moved back-gate channel modulation). Other problems arise in MOS
= “slider” by voltage control
from left to right cells based on operation in the triode region.
Analog multipliers have also been based on the use of
squaring cells made with bipolar transistors, whose practical
Current flow value is questionable, since they perform only indirectly what
into extended can be more efficiently achieved using direct translinear mul-
collector region
tiplier implementations. Indeed, the appeals to the quarter-
CL CR square approach in a contemporary context seem to overlook
Buried layer forms resistive track the historical reasons for invoking this principle in the first
place, at a time when bipolar transistors and their highly ad-
vantageous translinear properties were not yet available.
(b)
In an attempt to push the static accuracy to fundamental
Figure 6. Solid-state servomultiplier: (a) upper regions; (b) detail of limits, the use of nonlinear device behavior has often been set
subcollector. aside to explore what might be done using little more than
analog switches (11). Invariably, the accuracy of these multi-
pliers is limited more by the auxiliary circuitry required to
Fig. 6(a). An n-type buried-collector layer beneath the emitter support the core function, as is true of most practical multipli-
corresponds to the track of the output potentiometer. The do- ers, and any theoretical benefits that might be possible using
main, whose current magnitude is controlled by the Y input, switching techniques are often lost in this way. A more seri-
is analogous to the slider; Fig. 6(b) shows just the collector ous limitation, for all but a few specialized low-frequency ap-
region. plications (for example, power measurement at line frequen-
Two domains may readily be integrated into a single device cies), is that the output must be derived from averaging a
to realize a four-quadrant multiplier. The response time to pulse train whose duty cycle and amplitude vary with the two
the position-controlling X input is typically nanoseconds; the multiplicands. A considerable time is required to determine
Y input is even faster, since the extended npn transistor be- the average value, even using an optimal filter.
haves essentially as a grounded-base stage. While the perfor-
mance of these carrier-domain multipliers is excellent, the
use of superintegrated structures is deprecated in a commer-
cial context, since they are not amenable to standard model-
ing and simulation techniques. RL
With the increased need for speed in analog computers
+ +
during the mid-1940s, electromechanical multipliers were re- VX + VY
placed by vacuum tube circuits. A popular technique of this x2
2
time was based on cells that generated a square-law function, – –
used in conjunction with summing and differencing circuits
to implement a quarter-square multiplier (5), so named be- R A
VR
cause of the algebraic identity VW
R
+ +
XY = 14 [(X + Y )2 − (X − Y )2 ] (5) VX Output
VX – VY 2R x2 buffer
2
A generic implementation is shown in Fig. 7. The squaring – –
VY
circuits are here presumed to be transconductance (gm) ele- R
ments and able to handle X and Y inputs of either polarity VR
(although in practice it is often necessary to include an abso-
lute-value circuit to allow the use of single-quadrant squar- Figure 7. Quarter-square multiplier.
680 MULTIPLIERS, ANALOG
S2
+VY
Low-pass VW
–VY B filter
±VX
R +VU
A and base–emitter voltage, VBE:
S1
–VU
Figure 8. Pulse-averaging multiplier.
An illustrative embodiment of this principle is shown in
Fig. 8. The hysteretic comparator, which operates the change-
over switch S1, and the low-pass filter RC constitute an asyn-
chronous delta modulator. This loop generates a pulse se-
quence whose duty cycle is forced to a value such that the
average voltage appearing at node A is equal to the input
VX, which is assumed to be varying only slowly compared to
the oscillation period of the loop, which is determined by the
hysteresis band of the comparator, VH, the reference voltages
⫾VU, and the time constant ␶ ⫽ RC. It is easily shown that
the duty cycle is
thi V + VU
P = = X (6)
tlo + thi 2VU
varying from 0 when VX ⫽ ⫺VU to 100% when VX ⫽ ⫹VU,
independent of VH, which must be considerably less than VU.
The comparator is arranged to operate a second switch, S2, to
which the Y input voltage is applied, and whose output at
node B is a voltage of ⫹VY and ⫺VY, also having the duty cycle
P . This is averaged in a multipole low-pass filter to generate
the output
VW = ave{P VY − (1 − P )VY }
VX (7)
= V
VU Y
A clocked comparator may be used to provide synchronous
operation. This multiplier offers very high accuracy, arising
from a fundamentally sound architecture, which does not de-
pend on any device nonlinearity, such as vacuum tube or
MOS square-law behavior, or the exponential junction law. It
is well suited to CMOS implementation, where the chief
sources of error will be the offset voltage in the comparator
(which can be eliminated using doubly correlated sampling)
and in the output filter. The fundamental need for averaging,
however, severely limits the response bandwidth to the high
kilohertz region; if higher oscillation periods are used in the
delta modulator, second-order effects due to inaccurate
switching eventually become troublesome.
VARIABLE-TRANSCONDUCTANCE MULTIPLIERS
Analog multipliers may be implemented in a true transcon-
ductance mode, that is, using cells accepting voltage-mode
signals at their input interfaces, and generating a differential
output current that ideally, is proportional to the product,
and is converted back to a voltage using a simple resistive
load. While space precludes a discussion of true gm-mode mul-
tipliers, the underlying device-modeling issues are crucial to
the operation of modern multipliers using translinear-loop
techniques.
A bipolar junction transistor exhibits an accurate and reli-
able exponential relationship between its collector current IC

V 
V 
IC = AE JS (T ) exp BE
−1 ≈ AE JS (T ) exp BE
(8)
VT VT
AE is the effective emitter area (never exactly equal to the
physical junction area, because of edge effects, though exactly
proportional when using replicated unit devices). The factor
JS(T) is the saturation current density, a characteristic of the
doping in the transistor’s base region; it is highly tempera-
ture-dependent. The product AEJS is usually called IS, the sat-
uration current, and is a key scaling parameter. VT is the ther-
mal voltage kT/q, where k is Boltzmann’s constant, 1.38 ⫻
10⫺23 C ⭈ V/K, T is the absolute temperature, and q is the elec-
tron charge, 1.60 ⫻ 10⫺19 C. VT evaluates to 25.85 mV at T ⫽
300 K, which temperature is assumed unless otherwise
stated.
Equation (8) is essentially Shockley’s junction law, stated
in transistor terms, with some concessions to simplicity, in-
consequential for most practical purposes. First, the approxi-
mation of the quantity exp(VBE /VT) ⫺ 1 by the simpler
exp(VBE /VT) is readily justified: even at VBE ⫽ 360 mV, the
exponential term is over a million. Second, VT should be
multiplied by a factor, called the emission coefficient, which is
very close to, but not exactly, unity. Finally, the forward
Early voltage VAF and the reverse Early voltage VAR, which do
not appear in Eq. (8), have an effect on the IC –VBE relation-
ship. These and other device effects are of importance in the
detailed analysis of high-performance analog multipliers.
However, they are truly second-order effects, and the design
of practical, robust, and manufacturable multipliers can ig-
nore many of them, or utilize simple compensation techniques
to lessen or eliminate their effect on accuracy.
The dual equation is
VBE = VT log(IC /IS ) (9)
Using IS ⫽ 3.5 ⫻ 10⫺18 A, typical for a modern small transis-
tor, VBE evaluates to 800 mV at 100 애A, and varies by a factor
VT log 10, or 59.5 mV, per decade. These equations describe
the most important characteristics of a bipolar junction tran-
sistor (BJT), which operates as a voltage-controlled current
source (VCCS), having an exponential form in its collector-
current response to an applied base-emitter voltage, or as a
current-controlled voltage source (CCVS), having a logarithmic
form in its base-emitter-voltage response to its collector cur-
rent. The accurate log–antilog properties of bipolar transis-
tors are the basis of innumerable nonlinear circuits, not avail-
able from CMOS devices.
An important outcome of Eq. (8) is that the small-signal
transconductance gm is accurately related to the collector cur-
rent:
∂IC I (T ) exp(VBE /VT ) I
gm = = S = C (10)
∂VBE VT VT
 MULTIPLIERS, ANALOG 681

that is, the transconductance is an exactly linear function of

the collector current—the origin of the term translinear. Even
more remarkably, this equation holds true for all bipolar IX IY IU
IW
transistors, on any technology (including heterojunction bipo-
lar transistors (HBT) in SiGe, GaAs, etc.) and is independent + + +
of IS, thus being unaffected by doping levels or device size.
Q5 Q6 Q7
These transconductance multipliers are best viewed as a
subset of the larger class of translinear circuits, and are
widely used in contemporary practice where linearity and ac-
Q3
curacy are less important than extreme simplicity. It is in- Q2
structive to review the history from this broader perspective.
Regrettably, some confusion has arisen in the nomenclature,
Q1 Q4
and what should be called ‘‘translinear multipliers,’’ whose
internal operation can be analyzed entirely in the current
mode, are often mistakenly classified as ‘‘transconductance Q8 Q9
types,’’ which properly have at least one input in voltage form
and generate a current output.

Figure 10. Elaborated current-mode multiplier cell.

TRANSLINEAR MULTIPLIERS

During the period 1960 to 1970, the planar fabrication pro- sistor loop and assigning a value IW to the current in Q4, we
cess for bipolar junction transistors was being perfected, and obtain the equation
it became possible to produce a large number of integrated VT log(IX /IS ) + VT log(IY /IS ) = VT log(IU /IS ) + VT log(IW /IS )
circuits on a 1 in. (2.5 cm) wafer, each having many transis- (11)
tors with excellent analog characteristics and closely match-
ing parameters. In particular, the base-emitter voltages, for It is immediately apparent that the thermal voltages VT may
a given device geometry and collector current, were closely be eliminated from this equation, leaving sums of logarithms.
matched, partly due to operating at near-identical tempera- These may be converted to products:
tures. These and other aspects of monolithic fabrication IX IY I I
= U W (12)
opened the floodgates to stunning new design techniques, IS IS IS IS
hitherto quite impracticable using discrete-transistor imple-
mentations. In fact, many related cell concepts were gener- The saturation currents IS may also be eliminated, leaving
ated within a short period of time. The translinear technique IX IY
for analog multiplication was one such development. IW = (13)
IU
We will begin with a discussion of cells using loops of junc-
tions, called strictly translinear, and identified here as TL The most important observations about this result are: (1)
(translinear loop) cells. TL multipliers can be readily under- temperature sensitivity has been completely eliminated; (2)
stood by considering first a simple one-quadrant cell (Fig. 9) the product IW is exactly proportional to IX and IY; (3) the cell
using four identical, isothermal transistors (12, p. 51). The also provides analog division; (4) the actual VBE’s are of no
collector currents of Q1, Q2 and Q3, which are here assumed interest; that is, we have realized a pure current-mode cell.
to have the same size, are forced to values IX, IY, and IU re- This is a simple demonstration of the power of the
spectively. This cell does not, in principle, place any restric- translinear-loop principle (TLP), which describes the relation-
tions on the values of these currents, but they are restricted ship between all the currents in a loop of transistors, as in
to a single polarity. Summing the VBE’s around the four-tran- this example, and allows complex nonlinear functions to be
synthesized with ease. The TLP states:



IC = λ IC (14)
cw ccw

+ which reads: ‘‘The product of the collector currents in the

IX
IC2 IC3 IC4 clockwise direction around a translinear loop is equal to the
= IW product of the counterclockwise collector currents, times a fac-
IC1 Q3 tor ␭ that allows for the possibility that the transistors emit-
Q2
ter areas AE may differ.’’ For present purposes, we will gener-
ally assume ␭ ⫽ 1, except when discussing certain distortion
Q1 Q4 mechanisms. Note that this condition may be achieved using
devices of different emitter area, arranged in balanced pairs
IY IU of equal area, or in many other ways. Any number of loops
may overlap, and thus interact, but each loop will indepen-
dently satisfy this equation.
Figure 10 shows a practical development of the basic cell
Figure 9. Translinear one-quadrant multiplier–divider cell. that retains the pure current-mode operation and can provide
682 MULTIPLIERS, ANALOG
+ logarithmic relationship to IC ⫽ IX over a very wide dynamic
– may also be used as a logarithmic element (see LOGARITHMIC
CC
S loop remains stable.
RC
RX
VX Q1
IX IC
Figure 11. Method for forcing IC ⫽ IX ⫽ VX /RX using an OPA.
very accurate operation. Transistors Q5 to Q9 ensure that the
collector currents are forced to the desired value, even when
the dc current gain 웁0 is low; all of the above equations re-
main accurate in this eventuality. The main sources of static
error in this multiplier are (1) emitter-area uncertainties in
Q1 to Q4, which cause a simple scaling error, but do not gen-
erate nonlinearity; (2) the base and emitter resistances, rbb⬘
and ree⬘, which will cause nonlinearity, but only at high cur-
rents, when the voltage drops across them are a significant
fraction of VT; (3) the modulation of IW by the collector–base
voltage VCB of Q4, due to finite Early voltage.
Many further improvements in current-mode multipliers
are possible, and have been developed, but it is generally nec-
essary for a multiplier to receive and generate voltage-mode
variables. Special-purpose high-bandwidth interface cells can
be designed for high-bandwidth voltage-to-current (V–I) and
current-to-voltage (I–V) conversion. However, in moderate-
speed applications operational amplifier (OPA) interfaces can
provide these functions. Figure 11 shows a rudimentary
structure for forcing a collector current (5).
The low input offset voltage of the OPA serves two func-
tions. First, it places the current-summing node S close to
ground potential (under static conditions), which allows the
input current IX to be generated from a voltage VX with high
accuracy, scaled by RX, thus: IX ⫽ VX /RX. Assuming the OPA
has very low input current, all of IX flows in the collector of
the transistor. Second, it forces the VCB of Q1 to be zero, elimi-
nating modulation effects due to VAF. The VBE of Q1 bears a
+ –
OPA1
Figure 12. One-quadrant log–antilog multiplier having volt-
age interfaces.
range, specifically, VBE ⫽ VT log(VX /RXIS); accordingly, this cell
AMPLIFIERS). RC and CC are necessary to ensure that the OPA
Figure 12 shows a complete one-quadrant multiplier based
on this approach. It is traditionally called a log-antilog multi-
plier, because of the reliance on the dual log-exp relationships
of Eqs. (8) and (9). Its function is not, however, predicated on
the small-signal transconductance given by Eq. (10), which
is also temperature-dependent, but is accurately linear with
respect to the X or Y input under large-signal conditions, and
temperature-stable. A simpler view is therefore that it is a
translinear multiplier, following the principle stated in Eq.
(14), aided by operational amplifiers to accurately force the
collector currents.
OPA1 to OPA3 provide the input interfaces (the HF com-
pensation has been omitted for clarity). OPA4 converts the
current IC3 ⫽ IW to a voltage VW ⫽ IWRW. The op-amps hold the
collector voltages of all transistors at ground potential, elimi-
nating Early-voltage errors. From inspection,
RU RW VX VY
VW = (15)
RX RY VU
The linear errors are determined by the offset voltages of the
amplifiers (a 1 mV offset represents a 0.01% error for a FS
input or output of 10 V), by element matching, and by the
voltage reference. Nonlinear errors are mainly determined by
the junction resistances in Q1 to Q4. The dynamic errors are
dominated by the op-amps. This remains a one-quadrant mul-
tiplier–divider, useful in specialized contemporary applica-
tions. Incidentally, this drawing hints at the care which must
be taken in a practical realization with regard to the place-
ment of the current-forcing connections.
More often, multipliers are used as gain-control elements,
which require two-quadrant (bipolar) operation of the signal
path, with single-polarity operation of the other multiplicand
and the divisor. However, a one-quadrant cell can be adapted
for two- or four-quadrant operation. The rearrangement
shown in Fig. 13 shows the extension to two quadrants; fur-
ther rearrangements of this same core allow operation in all
four quadrants.
VX VY VU VW
RX IX RY IY RU IU RW IW
OPA4
– +
+ – – +
Q2 Q3
OPA2 OPA3
Q1 Q4
 MULTIPLIERS, ANALOG 683

VP
RW
Voltage inverter RL

R +
±VW
–
R OPA4 ±VX
±VX – = V
+VU Y
+ RW
RX
OPA1

RX Q1 Q4

+VU – –
RU Q2 Q3 RU
+ +
OPA2 OPA3

IY
Figure 13. Two-quadrant multiplier/di-
vider.

HIGH-FREQUENCY TRANSLINEAR MULTIPLIERS multiplier technique provides such broad coverage of the ap-
plications domain.
The bandwidth of the preceding circuits is severely limited To illustrate the principles, Fig. 14 shows a practical two-
by the operational amplifiers. Some improvement in a fully quadrant translinear multiplier. The bandwidth of the TL
monolithic design is possible using specialized amplifiers, but core extends from dc to a substantial fraction of the fT of the
in order to realize the full potential of the translinear core, transistors, which for a modern BJT process is commonly 25
other types of interface—often, though not necessarily, using GHz, and as high as 100 GHz using advanced SiGe hetero-
open-loop rather than feedback techniques, are used. Note junction technologies. The chief practical limitation to overall
that moderately accurate conversion back to voltage mode in bandwidth is usually the support circuitry, notably the V–I
a wideband current-mode multiplier may be achieved by the conversion cell at the X input and in the conversion of the
use of simple load impedances. differential current-mode outputs to a voltage output.
The first translinear multipliers, described by Gilbert in The input voltage VX is first converted to a pair of differen-
1968 (13), achieved a response from dc to 500 MHz, and ex- tial currents (1 ⫹ X)IX and (1 ⫺ X)IX by the V–I cell; these
hibited a large-signal rise time of 0.7 ns. Two-quadrant types currents are applied to the diode-connected outer pair of tran-
were originally developed for use in oscilloscope vertical de- sistors, Q1, Q2. Assume that the V–I interface is perfectly
flection amplifiers, to provide interpolation between the linear, that is, X ⫽ VX /IXRX. For the case of the pnp-style in-
1 : 2 : 5 step attenuator settings that determine the sensitivity, terface shown here, X runs from ⫹1 when the value of VX is
replacing the use of potentiometers, which were formerly used
in the signal path. Four-quadrant types were also developed
during that period, for use in modulation and demodulation;
optimized low-noise mixer cells, including the widely used to-
IX IX
pology known as the ‘‘Gilbert mixer,’’ were developed for use VX/RX
in frequency translation applications, though prior art using
discrete devices (14) was discovered in patent searches.
The immediate combination of monolithic simplicity, accu-
racy, speed, and low cost was unprecedented at that time, and VX (1 – Y) IY (1 + Y) IY
remains unimproved on even to this day. These classic circuit VBB
cells have undergone little change in design, and have become (1 – X) IX (1 + X) IX
– +
the dominant technique for analog multiplication across a
broad front.
Numerous commercial products are nowadays available Q1 Q2 Q3 Q4
providing one-quadrant, two-quadrant and four-quadrant op-
ccw cw ccw cw
eration, sometimes supporting the division function. Absolute
accuracies may be as high as 0.05%, nonlinear errors as low
as 0.01% (roughly corresponding to harmonic distortion levels 2IY
of ⫺80 dBc) and bandwidths extend from dc, through audio,
ultrasonic, IF, RF, and microwave ranges, and as high as 40
GHz in advanced optical receiver AGC applications. No other Figure 14. Two-quadrant wideband multiplier cell (type A).
684 MULTIPLIERS, ANALOG
at, or more than, its FS negative limit of ⫺IXRX, to ⫺1 at the
other extreme, when VX ⱖ IXRX.
The variable X, called a modulation factor, is frequently
useful in describing the operation of these cells. A feature of
this multiplier cell (and unique to TL cells) is that operation
remains linear up to the extremities of the FS range, in other
words, for all values ⫺1 ⱕ X ⱕ ⫹1. In practice, a moderate
peak value of XFS of about ⫾0.75 is generally used, first, to
ensure that at FS drive, the current densities remain above
the point where the instantaneous bandwidth, that is, f T(IC,
VCB), is jeopardized during portions of the signal cycle, and
second, to reduce the incidental nonlinearity in the V–I cell.
Since the peak input voltage is VXFS ⫽ XFSIXRX, it follows that
the bias current must be raised to IX ⫽ VXFS /XFSRX to provide
this overrange capacity. For XFS ⫽ 0.75 and a FS input of 1
V, the product IXRX must be 1.333 V.
To analyze the operation of this Type A multiplier cell—so
named because the junction polarities alternate around the
loop, cw–ccw–cw–ccw—we can assign a similar modulation
index Y to describe the currents in the driven pair Q3, Q4
and then apply the TLP. To gain rapid insight, we will ignore
for the moment the effects of junction resistance, finite base
currents, and device mismatches. While these may appear to
be naive simplifications, the performance capabilities of TL
multipliers are well proven, and the practical errors can in
fact be held to very low levels. Applying the TLP, from Eq.
(14), we have
IC2 IC4 = IC1 IC3 (16)
cw ccw
Inserting the actual currents, we have
(1 − Y )IX (1 + X )IY = (1 − X )IX (1 + Y )IY (17)
Thus
Y ≡X (18)
independent of IX and IY. That is, the modulation factor in the
outer pair has been exactly replicated in the inner pair, and
the current-gain is simply IY /IX.
This is a very important result. Note the simplicity of the
analysis that results from direct application of the TLP,
which completely bypasses considerations involving VBE, its
exponential nature, and the temperature-dependent satura-
tion current IS and thermal voltage kT/q. Equation (18) holds
over all temperatures, for all bias currents (from nanoamp-
eres to milliamperes), any device size, either device polarity
(pnp or npn), for any material (Si, Ge, SiGe, GaAs), and for
any bipolar technology (homojunction or heterojunction).
For this striking reason, the TLP was originally named
‘‘the pervasive principle.’’ It is as fundamental a result for
translinear circuits as that for gm stated in Eq. (10) is for a
single transistor. Of course, when implementing the principle
in robust, high-performance products, many detailed issues
need consideration. The differential output current is just
IW = IC3 − IC2 = (1 + X )IY − (1 − X )IY
(19)
= 2X IY
The differential voltage VBB has the magnitude
1+X
VBB = VT log (20)
1−X
and while this voltage, having a peak value of ⫾50 mV for
Xmax ⫽ ⫾0.75, is of only incidental interest, it provides a use-
ful way to assess the wideband noise of a translinear multi-
plier. For example, when IX ⫽ IY ⫽ 1 mA, the total voltage
noise spectral density (NSD) of this four-transistor cell evalu-
ates to about 1.3 nV/Hz1/2. Thus, if the FS output is raised to
⫾1 V—a factor of 20 times VBB —the lowest possible NSD at
this node will be 26 nV/Hz1/2. Assuming a 1 MHz signal band-
width, this amounts to 26 애V rms, providing a dynamic range
of 88.7 dB for a 707 mV rms sine-wave output.
More detailed analysis shows that this particular cell is
beta-immune, that is, finite base currents do not affect the
basic operation, provided that the current gain 웁 ⫽ IC /IB is
substantially independent of current over the X range. This
can be understood by noting that the fractional loss of current
in the outer transistors due to the base currents IB3 and IB4 of
the inner pair bears a constant-ratio relationship to IC3 and
IC4; thus, the modulation factor X is unaffected by the base
currents, and Y continues to have the same modulation factor
as generated by the input V–I converter. Even when the base
currents are almost equal to the available drive currents, and
Q1, Q2 are operating under starved conditions, the multiplier
remains linear—a unique property of this particular circuit.
The scaling error due to 움 ⫽ IC /IE can be considered as a sepa-
rate mechanism, even though arising from the same device
limitations. Highly refined design techniques address such
matters of scaling stability and robustness in mass pro-
duction.
The most serious nonlinear error sources in this cell are (1)
small mismatches in the emitter areas and (2) finite junction
resistances. These and other causes of errors in translinear
multipliers were fully quantified in the seminal papers pub-
lished in 1968 (15,16). Mismatches between the ratios
AE1 /AE2 and AE3 /AE4 cause even-order nonlinearities (essen-
tially quadratic), and also linear offsets. The factor ␭ used in
Eq. (14) is here given by
AE1AE4
λ= (21)
AE2 AE3
Q1 Q4
ccw (1 – Y) IY (1 + Y) IY cw
(1 + X) IX Q2 Q3 (1 – X) IX
cw ccw
VX
VX/RX
IX 2IY IX
Figure 15. Alternative two-quadrant multiplier cell (type B).
 MULTIPLIERS, ANALOG 685

Q1 Q4
Q2 Q3 Q5
(1 + X) IX (1 – X) IX (1 – Y) IY
VX
RX RY
IX IX IY
Figure 16. Wideband four-quadrant multiplier cell.
The VBE mismatch around the loop Q1–Q2–Q3–Q4 is VT log
␭. While this voltage is a function of temperature, the effects
of emitter-area mismatches in translinear circuits are tem-
perature-independent, and the voltage view is irrelevant.
For Xmax ⫽ ⫾0.75, it is found that the peak quadratic error
is 0.1% of FS output when ␭ ⫽ 1.002 (VBE mismatch of 52 애V).
To minimize this error the transistors should be arranged in
a common-centroid manner in the IC layout. This level of
quadratic error is routinely achieved in untrimmed multipli-
ers, and may be reduced by a factor of at least ten by using
laser trimming to null the second harmonic distortion. This
error is independent of device size and bias currents.
Errors due to junction resistance, on the other hand, are
dependent on device size (mostly because of the effect on the
base resistance rbb⬘) and operating currents. These cause odd-
order nonlinearity errors (essentially cubic), but no offsets.
This source of nonlinearity is particularly troublesome in two-
quadrant VCA cells, where current densities vary widely.
However, when certain simple criteria are met (16), this dis-
tortion can be eliminated in four-quadrant cells, and for this
reason they are often used even where only two-quadrant op-
IW eration is required.
A four-transistor multiplier has only one other topological
form, shown in Fig. 15, called a Type B (balanced) cell. The
Q6 junctions occur in pairs, cw–cw–ccw–ccw. It can be shown
that this circuit does not enjoy the beta immunity of the Type
A multiplier, since the currents in the driven transistors Q2,
Q3 are now out of phase with those in the input transistors
(1 + Y) IY
Q1, Q4; the base currents subtract from the drive currents in
antiphase. It is nonetheless widely used, because it can be
VY
easily driven from all-npn interfaces (V–I converters), which
until recently were the only available high-speed transistors
in a bipolar IC process.
A four-quadrant multiplier is formed by adding a further
IY
pair of transistors Q5, Q6, also having their bases driven from
Q1, Q2, as shown in Fig. 16, and their outputs connected in
parallel antiphase. The common-emitter nodes are driven
from a second V–I, handling the Y input and generating a
complementary pair of currents (1 ⫹ Y)IY and (1 ⫺ Y)IY, where
Y ⫽ VY /IYRY.
The operation is an extension of that analyzed for the two-
quadrant cell. Elaborating Eq. (19), we have
IW = IC3 − IC2 + IC6 − IC5
= (1 − X )(1 − Y )IY /2 − (1 + X )(1 − Y )IY /2
(22)
+ (1 + X )(1 + Y )IY /2 − (1 − X )(1 + Y )IY /2
= 2XY IY
The conversion of the differential currents back to the voltage
domain can be accomplished in several ways, depending
largely on accuracy and bandwidth considerations. In high-
frequency applications, a balanced-to-unbalanced transformer
(balun) can be employed, with the working load impedance
RW determining the overall scaling factor.
Substituting the full expressions for X and Y into Eq. (22),
we can write
VX VY IY RW V V R
VW = 2XY IY = = X Y W (23)
IX RX IY RY VU RY

RL ∆V → 0

+
IW
Q1 Q4 –
AO
σ
Q2 Q3 Q5 Q6

VX VY VZ

RX RY RZ

IX IX IY IY IZ IZ
Figure 17. Versatile four-quadrant struc-
ture using active feedback.
686 MULTIPLIERS, ANALOG

+ V XV Y
VX X W G
– VU
R1
× V Z1

+ – R2
VY Y Z
– + V Z2

Figure 18. Four-quadrant multiplier

with gain.

where VU ⫽ IXRX in this implementation. It follows that the
biasing arrangements for IX should be traceable to an accu-
rate, temperature-stable voltage reference. In a complete mul-
tiplier, this current will also include compensation for finite
beta. The AD834 is a dc to 1 GHz four-quadrant multiplier
having essentially this structure, having open-collector out-
puts; special techniques are employed to linearize the X and
Y interfaces.
In low-frequency (⬍300 MHz) applications, it is possible to
provide a more versatile output interface based on feedback
around a closed loop. Of particular interest here is the use of
active-feedback techniques (17) to improve linearity. Figure
17 shows the general structure: a third V–I cell has been
added to handle the feedback path; its differential output is
VZ /RZ. Note that while the currents IY and IZ do not enter into
the scaling of this multiplier, they nevertheless affect the FS
capacity of the Y and Z interfaces. Resistive loads RL are used
at the collectors of the core, but the high open-loop gain of the
output amplifier ensures that the differential voltage swing is
very small. The output currents of the Z cell are attenuated
by a scaling factor ␴; the purpose of this will become clear in
a moment.
The output can be expressed as

V σVZ RL
 IX RX RY
X VY IY RL
VW = AO − (24)
IX RX IY RY RZ
As before, the IY factors cancel, and when the effective resis-
tance AORL is very high, the two terms inside the brackets
must be equal. This condition will always be forced by VW act-
ing on one of the inputs, by a feedback connection, but it does
not have to be the Z input. We will show that in addition to
four-quadrant multiplication, this versatile IC structure can
be used for two-quadrant squaring, simple one-quadrant
square-rooting, absolute-value extraction, two-quadrant
square-rooting (with very few external components), two-
quadrant division, four-quadrant division (using two ICs),
and N-dimensional vector summation (using N multiplier
ICs).
The active-feedback structure can also easily generate an
accurate bipolar current output having a very high imped-
ance, and thus also provide exact time integration using a
capacitor. This structure was first used in the highly success-
ful AD534, a fully calibrated laser-trimmed monolithic multi-
plier introduced by Analog Devices in 1975, and since then in
the AD633, AD734, and AD835, and IC multipliers from other
manufacturers. It has become a classic form, having been de-
signed into thousands of systems.
To complete the theory of this multiplier form, we will re-
write the general solution found by nulling the bracketed
terms in Eq. (24):
VX VY σVZ
=
RZ
(25)
which can be simply cast as
VX VY = VZVU (26)
where the scaling voltage is

VX VU = σ IX RX RY /RZ (27)
+
X W
– This current is
R It was previously noted that the product IXRX needed to be
proportional
× to the product 1.333 times the FS input to result in a FS modulation factor
VW across RI XFS of 0.75. For a FS X input of 10 V, this requires IXRX to
A + – evaluate to 13.33 V (though no such explicit voltage may arise
Y Z RI
– + Vout in the IC). Further, it is desirable that RZ ⫽ RY, so that the
+1
R nonlinearity arising in the feedback (Z) cell exactly cancels
that of the Y-input cell; this is an important advantage of the
active feedback scheme. Finally, we wish the scaling voltage
to be exactly 10 V. Solving Eq. (27), this requires that the
CI
factor ␴ must be set to 0.75.
These multipliers also provide fully differential, high-im-
Figure 19. Rms–dc converter using difference-of-squares technique. pedance X, Y, and Z interfaces, implementing a more compre-
 MULTIPLIERS, ANALOG 687

V1
10 kΩ 100 pF
X1 O/P
–
+ +
– + OPA1
KW
X2 Z1 VW
×
Y1
+ –
– +
–KW
Y2 Z2
KVW
V2
X1 O/P R
+
+
–
– + OPA2
KW R
X2 Z1
×
Y1
+ –
– +
–KW –KVW
Y2 Z2

N stages
VN
X1 O/P
+
– +
KW VW = V12 + V22 + ... + VN2
X2 Z1
× when r = ( N – 1)R
Y1
+ –
– +
–KW
Y2 Z2
Figure 20. N-dimensional vector sum-
mation.

hensive function, which can be expressed in terms of the bal-
ance equation
(VX 1 − VX 2 )(VY 1 − VY 2 ) = VU (VZ1 − VZ2 )
While many general purpose multipliers support 10 V FS in-
puts and utilize a denominator voltage VU of 10 V (such as
the AD534, AD633, and AD734), the 250 MHz AD835 has ⫾2
V FS inputs, with a VU that is readily trimmed to 1 V, thus
providing a ⫾4 V FS output; the node VZ1 is internally con-
nected to VW, but access to VZ2 allows many useful extra func-
tions based on summing at the output. The 1 GHz AD834
provides differential current outputs.
add feature), and many more nonlinear/linear operations,
such as trigonometric-function synthesis, rms–dc conversion,
and programmable filters. The availability of this Z interface
(28) is of great practical value, and is used in many of the applica-
tion examples which follow (18), in most of which either the
low-cost AD633 or the AD534 can be used.
Figure 18 shows the basic symbol for versatile multipliers
of this class, and demonstrates how one may be connected for
basic four-quadrant multiplication. With VW simply connected
to VZ1, the balance equation (28) becomes
(VX 1 − VX 2 )(VY 1 − VY 2 ) = VU (VW − VZ2 ) (29)
thus

MULTIPLIER APPLICATIONS VX VY
VW = + VZ2 (30)
VU
The balance equation can be used to implement numerous
functions: modulation, demodulation, mean-square and root- In this case, however, only a fraction of VW is returned to the
mean-square extraction, power measurement, gain control; Z interface, invoking familiar feedback techniques, which
filterless demodulation, correlation (using the multiply-and- raises the output gain by the factor G ⫽ (R1 ⫹ R2)/R2, and
688 MULTIPLIERS, ANALOG

X1 O/P
u′ =
+ u cos θ + v sin θ
– +
10 kΩ
X2 Z1
Vθ ×
0±10 V Y1
+ –
– +
10 kΩ
Y2 Z2
θ = 2 tan–1(Vθ /20)
(rads)
u

X1 O/P
v′ =
+ v cos θ+ u sin θ
– +
10 kΩ
X2 Z1
×
Y1
+ –
– +
10 kΩ
Y2 Z2

Figure 21. Vector rotation circuit. v

thus the effective value of the denominator voltage is VU /G. A nique (19), shown in Fig. 19. This scheme generates the prod-
voltage at the lower end of R2 adds directly to the output, with uct
a scaling factor of unity.
The output may be taken in current-mode form from the Vin + Vout V 2 − Vout
2
VZ2 node by a resistor placed from VW to VZ2 since the product (Vin − Vout ) = in (31)
2 2
voltage VXVY /VU is forced across this resistor, whatever its
value and for any load voltage (for both within a wide range);
the long-term average of which is forced to zero by the action
the output impedance is very high (megohms), being deter-
of the loop including the integrator, which also serves to aver-
mined by the common-mode rejection ratio of the Z interface.
age the signal at the multiplier output, VW. It follows that
When this current is applied to a grounded capacitor, the
time-integration function can be implemented. This is used in
the rms–dc converter based on a difference-of-squares tech- Vout = ave(Vin2 ) (32)

VM
+
X W
– VM
(1 + ) E sin ω t
VU
×

+ –
E sin ω t Y Z
– +

Figure 22. AM modulator. Carrier feedforward

 MULTIPLIERS, ANALOG 689

Negative feedback It is sometimes required to rotate a pair of signals repre-

senting a two-dimensional vector, for example, in image pre-
sentation systems. Figure 21 shows how just two multipliers
may be used. The vector (u, v) is turned through an angle ␪
+ V XV U controlled by the V␪ input, to generate
X W
– VZ u  = u cos θ + v sin θ (34a)

× v = v cos θ + u sin θ (34b)
+
+
+ – VZ where
VY Y Z
– + –
– θ ≈ 2 arctan(Vθ /20) (35)

Using AD534 or AD633 multipliers, the rotation scaling is

Figure 23. Two-quadrant division.
in other words, the rms value of Vin has been generated. Using
an integration time constant CIRI of 16 애s, the loop settles to
within 1% of the final value after 123 애s for a 10 V sine-wave
input, and within 305 애s for a 4 V input. With the capacitor
omitted, the circuit provides the absolute-value function.
A further example of the utility of the summation feature
is provided by the N-dimensional vector-summing circuit (Fig.
20), where this function is provided by daisy-chaining the
multiplier outputs. The inputs V1 through VN may have either
polarity, and the loop seeks to null the sum of the N indepen-
dent difference-of-the-squares components. When the factor K
is set to 1/ 兹N, the overall scaling from the inputs is unity,
that is
5.725 deg/V and is ⫾60⬚ at V␪ ⫽ ⫾11.55 V; the relative error
is ⫺2% at V␪ ⫽ ⫾5 V (␪ ⫽ ⫾28⬚). The length of the vectors is
unchanged. A related scheme for cathode-ray tube (CRT) ge-
ometry and focus correction was described in Ref. 18.
In a more commonplace application, the Z interface is also
used in the AM modulator shown in Fig. 22, where the carrier
E sin 웆t is fed forward to the output (which responds as a
voltage follower to the Z2 input) and thus added to the product
of the modulation voltage VM and this carrier.
The Z interface is especially useful in analog division (Fig.
23), since it presents a high-impedance, fully differential in-
put port. From Eq. (28), with VX1 now being the output VW, we
have
(VW − VX 2 )(VY 1 − VY 2 ) = VU (VZ1 − VZ2 ) (36)
thus

VW =

V 2 + V22 + · · · + VN2
VZ1 − VZ2
1
(33) VW = VU + VX 2 (37)
VY 1 − VY 2

The integration time, provided by the 10 k⍀ resistor and the
100 pF capacitor, will normally be chosen to ensure stable
loop operation, but when large enough to implement averag-
ing, the circuit performs the root-mean-sum-of-squares oper-
ation.
The use of normalized variables is often valuable in ana-
lyzing and synthesizing multiplier applications. Thus:
x = VX /VU ; y = VY /VU ; w = VW /VU ; z = VZ /VU ;
A high-impedance summing input is again available. To
maintain negative feedback around the output amplifier, the
denominator must be positive, but the numerator may have
either polarity. The circuit therefore provides two-quadrant
division, with the added advantage of differential signal pro-
cessing available at both the numerator and denominator
inputs.
The determination of the ratio of two voltages, both of
etc. which have indeterminate polarity, calls for a divider capable

x2 x1

x1 – x2
w=
y1 – y2
X1 O/P X1 O/P
+ +
– + – +
X2 Z1 X2 Z1
× ×
Y1 Y1
+ – + –
– + – +
Y2 Z2 Y2 Z2

y1

y2 Figure 24. Four-quadrant division.

690 MULTIPLIERS, ANALOG

X1 O/P

+ uπ
R3 = w = sin
– + 2
4.70 kΩ 0<u<1
X2 Z1
R1 = R2 = ×
10.0 kΩ 18.0 kΩ Y1 R4 =
4.30 kΩ
+ R5 =
– 3.00 kΩ

Y2 Z2

Figure 25. Sine-function synthesis. u

of accepting a bipolar denominator input. This is the four-
quadrant division function. Commercial products that per-
form this function are not in demand, but it is easily imple-
mented using two of these general-purpose multipliers, as
shown in Fig. 24. The behavior is benign through the singu-
larity where the denominator is zero, though of course sig-
nificant errors arise for small values. This circuit is unusual
in being able to divide one sine wave by another. In a test in
which a 400 Hz, 10 V amplitude sine wave was applied to
both numerator and denominator inputs, the output was es-
sentially constant at ⫹10.03 V, with a ripple of only ⫾50 mV
at the zero crossings.
These versatile multipliers allow the implementation of ar-
cane and often complicated nonlinear functions. For example,
the sine function can be approximated by
1.0468θ − 0.4278θ 2
sin θ ≈
1 − 0.2618θ
over the range 0 ⱕ ␪ ⱕ 앟/2. The theoretical error is ⫾0.4% of
FS. While the synthesis requires considerable elaboration,
Fig. 25 shows how simple the implementation becomes, using
a single, low-cost multiplier. A better approximation, provid-
ing a theoretical error of only ⫾0.01%, and ⬍0.2% in practice,
can be implemented with just two such multipliers and five
resistors (18). Cosine synthesis needs only one multiplier and
two resistors (18), with a peak error of ⫾2% at 22⬚ and 73⬚,
and the useful arctangent function may be approximated with
a peak error of ⫾0.46⬚ as shown in Fig. 26.
Many further examples could be provided. These general-
purpose voltage-in, voltage-out translinear multipliers cover
a very broad range of applications, and their structure is prac-
ticable for operation from dc to at least 1 GHz. Contemporary
wideband translinear multipliers, implemented using very
fast complementary bipolar silicon-on-insulator (CB-SOI) pro-
cesses and aided by advances in noise and distortion reduc-
tion, calibrated to high accuracy using laser-wafer trimming
and presented in tiny surface-mount packages, represent the
epitome of the analog nonlinear art, while squarely meeting
the pragmatic ongoing requirements for a wide variety of non-
linear continuous-time signal-processing tasks, which go far
beyond the basic task of multiplication.
All manner of special-purpose multiplier cells, of either
transconductance or translinear types, have found their way
(38)
into numerous IC systems: as gain-control elements, often im-
plementing the AGC function; as power detectors and power
controllers; in correlation applications; in analog-programma-
ble filters; as modulators and demodulators, for example, syn-
chronous detectors; and much else. Their simplicity, com-
pleteness (no external components are usually required), very
high speed combined with excellent accuracy, low supply volt-
age requirements, and low power, coupled with low cost and
very small size, ensure the continued use of these ubiquitous
elements.

BIBLIOGRAPHY

1. S. Fifer, Analogue Computations, New York: McGraw-Hill, 1961.

X1 O/P 2. G. A. Korn and T. M. Korn, Electronic Analog Computers, New
+ R3 = tan–1u York: McGraw-Hill, 1956.
– + 4.70 kΩ w=
45° 3. B. Gilbert, Translinear circuits: An historical overview, Analog
X2 Z1 (+10 V output Integrated Circuits Signal Proc., 9 (2): 95–118, 1996.
×
Y1 R2 = for +10 V input) 4. B. Gilbert, Adavnces in BJT techniques for high-performance
+ – 5.10 kΩ R1 = transceiver, Eur. Solid-State Circuits Conf. Rec., Sept. 1997, pp.
– + 3.60 kΩ 31–38.
u
Y2 Z2 5. D. Sheingold (ed.), Nonlinear Circuits Handbook, 2nd ed., Analog
Devices, Norwood, MA: 1976.
6. B. Gilbert and B. Sam, 4-quadrant analog multiplication to
⫹/⫺0.025% accuracy needs few parts, Electron. Design, June 23,
Figure 26. Arctangent synthesis. 1997, pp. 70–72.
 MULTIPLIERS, ANALOG CMOS 691

7. M. Moller et al., 13 Gb/s Si-Bipolar AGC amplifier IC with high

grain and wide dynamic range for optical-fiber receivers, IEEE J.
Solid-State Circuits, 29: 815–822, 1994.
8. T. Masuda et al., 40 Gb/s analog IC chipset for optical receiver
using SiGe HBTs, 1998 IEEE ISSCC Techn. Dig., 1998, pp.
314–315.
9. B. Gilbert, A new technique for analog multiplication, IEEE J.
Solid-State Circuits, SC-10: 437–447, 1975.
10. J. Smith, A second-generation carrier domain four-quadrant mul-
tiplier, IEEE J. Solid-State Circuits, SC-10: 448–457, 1975.
11. J. G. Holt, A two-quadrant multiplier integrated circuit, IEEE J.
Solid-State Circuits, SC-8: 434–439, 1973.
12. B. Gilbert, Current-mode circuits from a translinear viewpoint: A
tutorial, in C. Toumazou, F. J. Lidgey, and D. G. Haigh (eds.),
Analogue IC Design: The Current-Mode Approach, IEE Circuits
and Systems Series, Vol. 2, Stevenage, UK: Perigrinus, 1990.
13. B. Gilbert, A dc-500 MHz amplifier/multiplier principle, ISSCC
Tech. Dig., IEEE, Feb., 1968, pp. 114–115.
14. H. E. Jones, Dual output synchronous detector utilizing transistor-
ized amplifier, March 15, 1996, US Patent 3,241,078.
15. B. Gilbert, A new wideband amplifier technique, IEEE J. Solid-
State Circuits, SC-3: 353–365, 1968.
16. B. Gilbert, A precise four-quadrant multiplier with subnanosec-
ond response, IEEE J. Solid-State Circuits, SC-3: 365–373, 1968.
17. B. Gilbert, A high-performance monolithic multiplier using active
feedback, IEEE J. Solid State Circuits, SC-9: 364–373, 1974.
18. B. Gilbert, New analogue multiplier opens way to powerful func-
tion-synthesis, Microelectronics, 8 (1): 26–36, 1976.
19. B. Gilbert, Novel technique for rms-dc conversion based the dif-
ference of squares, Electron. Lett., 11 (8): 181–182, 1975.

BARRIE GILBERT
Analog Devices Inc.
62 MULTIVIBRATORS

ri
MULTIVIBRATORS
A multivibrator is a device which transitions (vibrates) be- ri
tween several (multi) fixed output levels. Besides their use for
+ +
timing, they are commonly used either for storage or for clock-
ing of data in digital computers using binary numbers where +
the number of levels is generally two. There are several types U – C x y
of multivibrators and several classification schemes. One clas-
sification is (1) triggered or (2) free-running. Another more – –
frequent classification method uses their stability properties Trigger
for which, in the two-level case, there are (1) monostable, (2)
bistable, or (3) astable multivibrators. The bistable multivi- (a)
brator has an output that remains in either of its two stable
states until a trigger occurs, which forces a transition to the y
other stable state; consequently, the name flip-flop is fre-
quently ascribed to it. The monostable multivibrator remains Yhi Xwid
in its one stable state until triggered into its unstable state,
from which it eventually returns, usually after a fixed transi-
tion time, to the stable state; an alternate name of one-shot
is frequently used for it. The astable multivibrator acts as a Xlo Xmid Xhi
nonlinear oscillator as it oscillates periodically between its x
two unstable states, often in an asymmetrical manner and
giving different resting times for each state. Most standard Ylo
electronic circuits texts contain some material on multivibra-
tors, as, for example, Refs. 1 and 2 as well as Refs. 3 to 6.
(b)
GENERIC—BINARY HYSTERESIS MULTIVIBRATOR Figure 1. (a) Generic multivibrator using hysteresis. (b) Binary hys-
teresis. Gives philosophy for all multivibrator types. Hysteresis gen-
A generic form of binary multivibrator is obtained by combin- erated as per Fig. 7(a).
ing a nonlinearity that is binary hysteresis with a linear load
line, a single capacitor for dynamics, and a possible trigger
input; the type of multivibrator depends upon the position of and is seen to represent an offset of the hysteresis curve along
the load line on the hysteresis curve. Such a circuit is illus- the x axis. Of similar importance is the hysteresis width given
trated in Fig. 1(a), where all signals are taken as voltages by
referenced to ground; the hysteresis is illustrated in Fig. 1(b).
A circuit for the hysteresis is given in Fig. 5, but here we Xwid = Xhi − Xlo (5)
assume infinite input impedance and zero output impedance.
If at time t we take u(t) to be the multivibrator (trigger) in- By considering Eq. (1) at DC we obtain the (untriggered, that
put, y(t) its output, and x(t) its internal state signal, which is is, with u ⫽ 0) load line for the hysteresis as given by
input to the hysteresis h(x), we can write
gi

y= 1+ x = Lx (6)
dx gf
C = gi (u − x) + gf (y − x) (1)
dt
y = h(x) (2) which defines the slope L ⫽ [1 ⫹ (gi /gf )], with L ⬎ 1. De-
pending upon this slope L the hysteresis mid-point and the
hysteresis width, we have three basic types of intersections of
in which the constants are the capacitance C, input conduc-
the load line with the hysteresis as discussed in the next sec-
tance gi ⫽ 1/ri, and feedback conductance gf ⫽ 1/rf . The binary
tions and shown in Fig. 2(a–c).
hysteresis is characterized by
 Monostable Multivibrator
Ylo if Xlo ≤ x
y = h(x) = (3) The monostable multivibrator results from the situation
Yhi if x ≤ Xhi
shown in Fig. 2(a), where in the absence of an input trigger
(that is, u ⫽ 0), there is one intersection, at the Q point,
where the constants Xlo and Xhi are the low and high transi-
tion points of the hysteresis, satisfying Xlo ⬍ Xhi; Ylo and Yhi Yhi
are the two output values of the binary hysteresis. The x-axis XQ = (7)
L
mid-point of the hysteresis is given by
which is stable. In this case the system remains at the inter-
X − Xlo X + Xhi section point Yhi until there is an input trigger: thus the mo-
Xmid = Xlo + hi = lo (4)
2 2 nostable output Yhi. If a positive input trigger impulse is ap-

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.
 MULTIVIBRATORS 63

y y
y = Lx y = L(x – Utrig)
Yhi Q Yhi

xlo xhi Utrig

x x
xa

Ylo Ylo

(a) (b)

Utrig

x
Utrig
Xlo
XQ
t
ri ttrans

+ +
Y
Yhi

ri x C Ylo

t
– –

Ylo
(c) (d)

Figure 2. (a) Monostable Q point. (b) Triggered effective load line. (c) Equivalent circuit for
transient, Xinitial ⫽ Utrig ⱖ Xhi. (d) Triggered response. Shows operation of the monostable multivi-
brator.

plied of peak value Utrig [u(t) ⫽ Utrig웃(t) with 웃( ⭈ ) the unit heads toward the low asymptotic value
impulse], which is larger than needed to move the capacitor
voltage x past the value Xhi (Utrig ⱖ Xhi) then, as shown in Fig. gf
Xasym−lo = Ylo (9)
2(b), this effectively moves the load line to intersect the x axis gi + gf
of the hysteresis at the capacitor initial value (which is the
peak trigger voltage value Utrig). On removal of the trigger as determined from the voltage division of Ylo between rf and
peak, a transient transition is made from the output Ylo back ri. Consequently, assuming that the trigger impulse is applied
to Yhi. The (minimum) value of this input trigger is seen to be at t ⫽ 0, the state for this transition is given as a first order
just Xhi. The transient return is governed by a time constant response by
determined by C and the Thevenin’s equivalent resistor seen
t

by C, that is, with time constant
x(t) = Xasym−lo + [Utrig − Xasym−lo] exp − (10)
tcnst
C
tcnst = (8)
gi + gf
From Eq. (10) the transition time is found, by setting
x(ttrans) ⫽ Xlo, to be
The transition time will be the time to go from the maximum
value of x, as determined by the trigger, to Xlo with this time
Xlo − Xasym−lo

constant. An equivalent circuit for determination of this tran- ttrans = −tcnst × ln (11)
sition time is shown in Fig. 2(c), in which it is seen that x Utrig − Xasym−lo
64 MULTIVIBRATORS

where we naturally assume that the asymptotic value is y

smaller than the jump point value, Xasym–lo ⬍ Xlo, so that the
h(x)
transition point Xlo can actually be reached. The output y at
this transition time jumps back to Yhi. A typical response of y = Lx
this monostable multivibrator to an impulse trigger is shown
in Fig. 2(d).
In this case, as illustrated by Fig. 2(a), the output remains x
at the high level Yhi until a positive input trigger occurs, at
which time the output immediately falls to the low level Ylo,
where it remains until the signal of the state x falls below
Xlo as determined by the time constant. A similar situation
clearly holds if the load line intersects just the lower branch
of the hysteresis curve; but here the transition occurs with a Figure 4. Load line on hysteresis for astable multivibrator oper-
negative impulse input trigger rather than a positive one, and ation.
the asymptotic value heads toward the positive value of

gf
Xasym−hi = Yhi (12)
gi + gf
Equation (11) remains valid when this asymptotic value is
used. In either case, since only one output pulse occurs per
input trigger, the monostable multivibrator is often called a
one-shot.
Bistable Multivibrator
In the case where the load line intersects both the upper and
lower branches of the hysteresis, as shown in Fig. 3, then a
bistable multivibrator results, since both intersection points
serve as stable rest points. As in the monostable case, an im-
pulse trigger input of sufficiently large amplitude to shift the
load line off of one of the hysteresis branches will transition
the system to the other stable point. The time constant will
again be C/(gi ⫹ gf ), and the system will remain in the state
to which it transitioned until another appropriate input trig-
ger makes it transition again. The equations governing the
transitions are essentially those developed for the monostable
multivibrator with substitutions of the appropriate levels.
Astable Multivibrator
Figure 4 illustrates the astable situation in which the load
line intersects the jump lines of the hysteresis. As these inter-
sections are unstable, the system will not rest at either ‘‘inter-
section’’ but will transition between them with no input re-
quired to cause the transition. Again the transitions are
governed by the time constant C/(gi ⫹ gf ), which generally
leads to symmetrical output pulses.
To obtain equations for the transition times and the pe-
riod, we begin by assuming that the multivibrator has just
switched from one to the other of its two output levels, taken
here for convenience to be from Yhi to Ylo. At that time, nor-
malized to t ⫽ 0, we again have the equivalent circuit of Fig.
2(c), except that now the initial condition on C is given by x
at the switching point, this being Xhi. Consequently, the ca-
pacitor value heads toward a low value with the mentioned
time constant, stopping when x reaches Xlo, at which time an-
other transition (from low to high) is initiated. Substitution
of the correct initial condition and asymptotic value in Eq.
(11) gives the time for transition from the high to the low
output, thi–lo, as

X − Xasym−lo

lo
thi−lo = −tcnst × ln (13)
Xhi − Xasym−lo
By changing hi to lo and vice versa, this formula serves to
give the transition time from lo to hi as

X − Xasym−hi

hi
tlo−hi = −tcost × ln (14)
Xlo − Xasym−hi
Consequently the period of oscillation of this astable multivi-
brator is given by

tper = tlo=hi + thi−lo (15)

y
h(x) y = Lx Note that in the symmetric case where Xlo ⫽ ⫺Xhi and Ylo ⫽
⫺Yhi we have tlo–hi ⫽ thi–lo, in which case the period is given by

−Xhi + Yhi
gf 
C gi + gf
x tper−sym = −2 × ln gf (16)
gi + gf Xhi + Yhi
gi + gf

Should asymmetrical output pulses be desired, then a differ-

ent time constant can be obtained for the rise as compared to
Figure 3. Load line on hysteresis for bistable multivibrator oper- the fall by replacing ri or rf by a parallel combination of two
ation. resistors in series with inverted diodes, as shown in Fig. 5(a–
 MULTIVIBRATORS 65

ra rhf

r
Rhi
rb
+ +
+
(a) Vbias +
v+
–
y + y
x
y = Lx – – – –

(a)

y
x
y = (1 + a) v+ – aVbias

Vdd

(b)
v+
Figure 5. (a) Replacement of ri or rf for asymmetrical output. (b) x
Piecewise linear load line using ri or rf replacement. Resistor diode
circuit for generation of nonsymmetrical outputs.
Vss

b). In fact one of the diodes can be omitted, depending upon (b)
which of the two slopes is the biggest. An alternate means of
obtaining asymmetry is via hysteresis asymmetry, which will y
show up inside the logarithmic terms of Eqs. (13) and (14).
Vdd

Trigger Generation
Since an impulse trigger is desired for triggering the mono-
stable and bistable multivibrators, the standard way to obtain xlo xhi
x
it is by differentiation of a step pulse. Figure 6 shows a typical
means of generating a trigger impulse from a step pulse of
amplitude Vp. Here the terminals a and b are those of the
trigger input u in Fig. 1(a). However, one could alternatively
apply the terminals a and b through a diode directly to the Vss
multivibrator capacitor (and replace u by a short) to better
(c)
insure the direct application of desired initial values. This
method is most useful in the monostable case, while in the Figure 7. (a) Hysteresis generation circuit using an op-amp. (b)
bistable case one would need to switch between two differ- Loading for the generic multivibrator. The op-amp characteristic
ently directed diodes. moves with x to intersect the fixed load line. (c) Resulting hysteresis.

Hysteresis Generation
Figure 7(a) shows an op-amp circuit that generates the binary
hysteresis—in essence this is a Schmitt trigger. In Fig. 7(b)
we illustrate the means of calculating the hysteresis with the
hysteresis curve shown in Fig. 7(c). For Fig. 7(b) we describe
the op-amp as a function of v⫹, the positive op-amp input ter-
minal voltage with respect to ground, with x as a parameter
by

y(v+ ) = Vdd × 1(v+ − x) + Vss × 1(x − v+ ) (17)

Ct
a a
where 1( ⭈ ) is the unit step function and Vdd and Vss are the
upper and lower power supply voltages. The resistor portion
+ rt +
V – – of Fig. 7 acts as a load line on the op-amp characteristic and
is described by
b b
V = Vp1(t) y(v+ ) = (1 + a)v+ − aVbias (18)
Step input Impulse output ghi
a= (19)
ghf
Figure 6. Differentiation circuit for impulse trigger.
66 MULTIVIBRATORS

As seen in Fig. 7(b), when we increase x the op-amp jump Vdd

moves to the right and eventually the intersection of the two
curves remains at Vss, while as we decrease x the op-amp
jump moves to the left and eventually the intersection is at R
C
Vdd. For intermediate values of x there are two intersections. u 1 2 y
The second one starts, as seen by moving the op-amp curve
left, at v⫹ ⫽ x, where y ⫽ Vdd for both curves. This gives the
geometry of Fig. 7(b) (a)
Vdd + aVbias
Xhi = (20)
1+a
R
C
and the value for moving right starts at
1 2 y
Vss + aVbias
Xlo = (21)
1+a
(b)
These two values give the hysteresis jump values as indicated
on the hysteresis curve of Fig. 7(c) to jump between the hys- S Q
u y
teresis values of Vdd and Vss.
In summary, the Schmitt trigger circuit of Fig. 7(a) gives
the hysteresis needed for the generic multivibrator of Fig.
1(a), with the hysteresis parameters given in terms of the cir- R Q
cuit parameters of Fig. 7 by (c)

Vss + aVbias Vdd + aVbias Figure 8. NAND realization of (a) monostable multivibrator, (b)
Yhi = Vdd , Ylo = Vss , Xlo = , Xhi = astable multivibrator, and (c) bistable multivibrator.
1+a 1+a
(22)

Because we have four values (a, Vbias, Vdd, Vss) to set the hys- ers again can be made with NOR or NAND gates. The in-
teresis and four circuit parameters available, we can obtain verter on the right of Fig. 9 is used to square up the signal
reasonable multivibrators using the circuits developed to generated by the crystal, which acts as a second-order system
this point. to produce sinusoidal oscillations. Setting s ⫽ jw in the char-
It should be noted that transistorized versions of the acteristic equation found from Kirchhoff ’s laws, we see that
Schmitt trigger exist and can be used in place of the op-amp the inverter gains need to be set to ⫺2 to force the real part
circuit as shown in Fig. 7(a). See Ref. 2, p. 317 for a BJT- of the characteristic equation to zero; this is done by the
Resistor type Schmitt trigger and Ref. 2, p. 321 for a CMOS choice of equal resistors. From the imaginary part, the square
type. However, it is to be pointed out that these lack the of the radian frequency of oscillations of such an oscillator is
sharpness and flexibility for design of the op-amp Schmitt 1/LC, where L and C are the equivalent inductance and ca-
trigger. An operational transconductance amplifier (OTA) ver- pacitance of the crystal; consequently the period of the output
sion of the Schmitt trigger can be found in Ref. 7. pulses is 2앟兹LC. A commonly used inverter comes in a pack-
age of six and is known as the 74LS04 (9, p. 779).
LOGIC GATE CIRCUITS
THE 555 TIMER
It is also possible to construct multivibrators using digital
gates; in fact this is probably the most frequently used A standard commercial package that can be used to make any
method. Most books on digital circuits cover these multivibra- of the multivibrators is the 555 timer, for which a full circuit
tors (see, for example, Ref. 8 as well as Ref. 4). Using only
two-input NOR gates, Fig. 8(a) shows a monostable, Fig. 8(b), Crystal
an astable, and Fig. 8(c) a bistable multivibrator. Throughout
Fig. 8 the NOR gates, with their inputs tied together, act as
inverters, so that they can be replaced to advantage by invert-
ers. Figure 8(c) is an SR (set-reset) flip-flop with its S and R
inputs made complementary to force the bistable state deter-
y
minations. Also, throughout Fig. 8, the NOR gates can be re-
placed by NAND gates and similar behavior obtained by us-
ing triggers inverse to those used for the NOR gates.
Although the use of standard gates makes these gate-con-
structed multivibrators attractive, and they work at relatively
high pulse rates, their characteristics are not as sharp as
R R
those obtained from the op-amp Schmitt trigger circuits.
An astable circuit often used for precision clocks and using Figure 9. Astable multivibrator using crystal pulse repetition rate
crystal control is shown in Fig. 9 (6, p. 930), where the invert- control and inverters.
 MULTIVIBRATORS 67

diagram can be found in Ref. 10, pp. 9-33 through 9-38, along Using these formulas with the three parameters available it
with settings and applications. This is useful for printed cir- is quite easy to design the 555 to give any reasonable duty
cuit board designs using standard components. Because of its cycle and oscillation frequency for a square wave going be-
common use, the 555 timer is treated in most standard elec- tween ground (low) and Vcc (high). Data sheets show how to
tronic circuits textbooks, such as Ref. 4, pp. 975–979 and Ref. use it for such applications as frequency division, ramp gener-
11, pp. 683–688, 767. It comes in an eight-pin package (or as ation, pulse width modulation, and pulse position modulation.
the 556 14-pin dual set), these pins being 1 ⫽ ground, 2 ⫽
trigger, 3 ⫽ output, 4 ⫽ reset, 5 ⫽ control voltage, 6 ⫽ thresh-
old, 7 ⫽ discharge and 8 ⫽ Vcc bias. It can set the timing from
THE VAN DER POL OSCILLATOR
microseconds to hours, and can source or sink up to 200 mA
at the output. Depending upon the external circuitry used,
A robust astable multivibrator is obtained by using small
the 555 can serve many functions, including that of a bistable,
damping in the van der Pol oscillator. The robustness results
monostable, or astable multivibrator with an adjustable duty
from the van der Pol oscillator being structurally stable,
cycle. Basically, the 555 is a set-reset flip-flop (a bistable
which makes it both practically and mathematically impor-
multivibrator) surrounded by circuitry in the package that
tant. The van der Pol oscillator is described by the second-
allows it to take on various uses depending upon external cir-
order differential equation
cuitry. Its voltage at the output pin, Q of the SR flip-flop, is
set (to Vcc) when the threshold pin voltage falls below Vcc /3
and is reset (to ground) when the threshold pin voltage rises d2y dy
+ (y2 − 1) +y=0 (27)
above 2Vcc /3. Thus, by simple control on the threshold pin, a dt 2 dt
bistable multivibrator results. By controlling the threshold
voltage with the external circuitry one readily obtains other where ⑀ is a parameter that determines the nature of the re-
behavior. For example, Fig. 10 shows the connections for the laxation oscillation (⑀ small gives close to a sine wave, while
555 as an astable multivibrator. Here the capacitor C charges ⑀ large gives close to a square wave). Observing Eq. (27) we
from Vcc /3 to 2Vcc /3 through R7–8 ⫹ R6–7, and discharges from see that if y2 ⬎ 1 then we have positive damping and the
2Vcc /3 to Vcc /3 through R6–7 at times independent of Vcc, given signal decays, while if y2 ⬍ 1 there is negative damping and
respectively by the signal grows; consequently the signal heads toward y2 ⫽
1. To set up a means to realize this multivibrator we first
tcharge = 0.693(R7−8 + R6−7 )C (output ending high) (23) obtain the equivalent state variable description by rewriting
Eq. (27) as
tdischarge = 0.693R6−7C (output ending low) (24)

dy 
2 d + f (y)
d y df(y) dt
for a period and frequency of + +y= +y=0 (28)
dt 2 dy dt
1 1.44

1 
Tperiod = 0.693(R7−8 +2R6−7 )C, f = = f (y) =  y3 − y (29)
Tperiod (R7−8 +2R6−7 )C 3
(25)
Then by setting
and a duty cycle of
x1 = y (30)
R6−7
Duty cycle = dy dx1
R7−8 + 2R6−7 (26) x2 = + f (y) = + f (x1 ) (31)
dt dt

and rewriting (30) and (31), upon using (28), we get

dx1
= − f (x1 ) + x2 (32)
dt
dx2
1 8
R7-8 = −x1 (33)
GND Vcc dt
555
2 7
Trigger Discharge R6-7 Figure 11(a) shows a circuit realization of these equations us-
3 6 ing capacitors to form the derivatives, voltage-controlled cur-
Output Threshold +
rent sources—made via transistors as differential pairs (12,
C Vcc p. 431) to realize the cross coupling, and a nonlinear (voltage-
RL 4 5
Reset Control – controlled) resistor to realize f( ⭈ ). By changing the time scale
Cbias and by multiplying the equations by constants, circuit compo-
nents and waveform frequencies of interest can be obtained.
However, this design is predicated on obtaining the cubic law
nonlinear resistor, which is inconvenient. Fortunately, the
Figure 10. 555 Timer connected as an astable multivibrator. equations are structurally stable and allow for similar results
68 MULTIVIBRATORS

R1
i
+
+
+ Vdd
C1 x1 i = f(x1) +
–
– v
–
i = x1 –Vdd

+
+
C2 x2 R2
– R
–
+
i = –x2
(a) (b)

van der Pol PWL nonlinearity and limit cycle

6

2
x2 and f(x1)

y
0

LPQ P –2
Q
x1 –4

f(x1)
–6
–0.6 –0.4 –0.2 0 0.2 0.4 0.6
x1

(c) (d)

Limit cycle vs time

6

2
x1
x 0

–2
x2
–4

–6
0 5 10 15 20 25 30 35 40
t
(e)

Figure 11. (a) A van der Pol oscillator constructed with voltage-controlled current. (b) Op-amp
piecewise linear circuit to approximate cubic law of Eq. (29). (c) Limit cycle construction in state
space. (d) Limit cycle obtained from Matlab runs of Eqs. (32) and (33) with piecewise linear
f(x1). (e) Waveforms obtained from Matlab runs. x1(t) is a square wave and x2(t) is a triangular
wave.
 MULTIVIBRATORS 69

for a piecewise linear function approximation to the cubic. For Vcc

this the cubic can be replaced by R1 R2 R3 R4
 1.0k 100k 100k 1.0k

ax − b for x ≤ −d +
C1 C2
f (x) = −cx for − d ≤ x ≤ d (34) 5V


1 2 4
ax + b for d ≤ x 50p 10p –
   
(a + c)  b  (a + c)  b 
= ax − x + a + c  + x − a + c  (35)
2 2 Q1 Q2

We can design this piecewise linear current vs voltage law,

3
i ⫽ f(v), via the op-amp circuit of Fig. 11(b), which results in
the parameters

1 Vdd R2 Vdd (a)

a= , b= , c= , d= (36)
R1 R1 R1 R R
1+ 2 5.0 V
R

V(1)
The van der Pol oscillator finally results by inserting the cir-
cuit of Fig. 11b into Fig. 11a.
To see the multivibrator nature of the van der Pol oscilla-
tor, we look at the limit cycle in state space. Figure 11(c) 0V
shows a plot of f(x1) inserted into the state space plane x1 –x2.
5.0 V
Trajectories in this state space are determined by Eqs. (32)
and (33), for which we find, by simple division
V(2)

dx2 −x1
= (37)
dx1 x2 − f (x1 )
0V
Consequently, the slope of the trajectory at any point is well 5.0 V
determined, and we can construct the trajectory by determin-
V(3)

ing this slope graphically as follows: Choose a point P of inter-

est and drop a perpendicular to the x1 and x2 axes; that gives
x1 and x2 at P, x1P, and x2P. Next drop a perpendicular from
f(x1P) to the x2 axis, intersecting at Q, and draw a line LPQ 0V
from P to Q. The slope of LPQ is ⫺1/(dx1 /dx2) by (37), and by
5.0 V
trigonometry the slope of the line perpendicular to LPQ is the
negative inverse of this, which is dx1 /dx2. Connecting nearby
V(4)

points on this line gives the trajectory. From this construction

we can see that there is one limit cycle toward which all tra-
jectories converge (except the [unstable] one at the origin).
We also easily see that if the slope of the negative conduc-
tance portion is small in magnitude, then the limit cycle is
close to a circle giving sinusoidal-like oscillations. But if the
slope of the negative conductance portion of f( ⭈ ) is large, then
the oscillations are close to a square wave, as desired for a
multivibrator. Figures 11(d)–(e) show a typical phase-plane
plot of a limit cycle and waveforms obtained from Matlab
runs.
By using an f(v) which is odd, f(v) ⫽ ⫺f(⫺v), with multiple
negative resistance regions, one can obtain many different
limit cycles and consequently make a multivibrator that has
more than two vibration levels.
TRANSISTORIZED CIRCUITS
Figures 12(a)–(b) show an astable BJT (Bipolar Junction
Transistor) circuit (13, pp. 285–289) along with typical wave-
forms. Noting these waveforms, we see that transitions result
at the end of the first-order exponential rises in the base-
emitter voltages v2 and v3. If we take T1 to be the time when
v1 is high, then T1 ⫽ R3C2 ln 2, which is found by equating
0V
2 4 6 8 10
Time ( µs)
(b)
Figure 12. (a) BJT astable multivibrator. (b) Waveforms for the
astable multivibrator obtained from PSpice runs.
the current in R3 at T1, of value 2Vcc /R3, to its exponentially
decaying value from the previous transition, (2Vcc /R3)
exp(⫺T1 /(R3C2)). For the value T2 for which v4 remains high,
we similarly find T2 ⫽ R2C1 ln 2. Consequently, the period is
independent of Vcc and is given by
Tperiod = T1 + T2 = 0.7(R2C1 + R3C2 ) (38)
with various duty cycles possible.
Figures 13(a)–(b) show a bistable BJT multivibrator cir-
cuit (2, p. 300) with its node voltages. One of the two stable
states is triggered by a positive pulse Vin1, of amplitude Vcc, at
the left input, and the other by a similar pulse Vin2 applied at
70 MULTIVIBRATORS

R1 R2 R3 R4 R5 R6
20k 5k 20k 20k 5k 20k

+
4
Vcc 5V
1
–

Q1 Q4 Q5 Q8
+ +
– Vin1 Q2 Q3 Q6 Q7 Vin2 –

(a)

5.0 V

V(in1)
V(in2)

0V
5.0 V

V(1)

0V

2.0 V

V(2)

0V

2.0 V

V(3)

0V

10 V

V(4)

0V
0s 0.5 1.0 1.5 2.0
Time (ms)
Figure 13. (a) BJT bistable multivibrator. (b) Voltage waveforms for the
(b) bistable multivibrator obtained from PSpice runs.

the right. As can be seen from the waveforms, a pulse at the
right, on the emitter of Q8, is transmitted through Q8 to raise
the base voltage of Q7, which by its increased collector current
causes v4 to drop. In turn this drop is fed through Q4, lowering
the base-emitter voltage of Q3 and decreasing the current in
R2 to raise v1, which is fed back to the base of Q6 via Q5 to
reinforce the lowering of v4. The result of the positive feed-
back is a very sharp rise. Thus the risetime is limited only by
the transition delays of the transistors.
Figures 14(a–b) show a BJT monostable multivibrator (13,
pp. 290–292) along with typical waveforms. Essentially this
is the multivibrator of Fig. 12(a), with C2 replaced by a resis-
tor and a voltage divider, including R5 and Vss, to insure that
the base of Q1 will be biased to bring the transition consis-
tently to the same stable state. As can be verified from the
waveforms, the pulse width is determined by the time con-
stant that determines the rise of v3. Since during the pulse
transition, the transistor Q1 (being saturated) acts as a short
between collector and emitter, the time constant is just R2C1.
Roughly, during the pulse, v3 rises from ⫺Vcc to Vcc and stops
when it reaches 0 (actually at Vbe(on) of about 0.7 V). Because
v3(t) ⫽ Vcc ⫺ 2Vcc exp(⫺t/(R2C1) we calculate
Tpulse−width = R2C1 ln 2 (39)
The most frequent means of making multivibrators using
MOS transistors are through the logic circuits shown in the
logic gate circuits section above, where the gates are con-
structed in CMOS form, but others are described in the litera-
ture (14–16).
 MUSICAL INSTRUMENTS 71

3. T. F. Schubert, Jr. and E. M. Kim, Active and Non-Linear Elec-

R1 R2 R4 tronics, New York: Wiley, 1996, Chap. 13.
3k 50k 1k 4. M. N. Horenstein, Microelectronic Circuits and Devices, 2nd ed.,
R3 50k Upper Saddle River, NJ: Prentice-Hall, 1996, Sect. 15.2.
1 3 4 5. R. Boylestad and L. Nashelsky, Electronics: A Survey, 3rd ed.,
5n Englewood Cliffs, NJ: Prentice-Hall, 1989, Sect. 12.5.
C1
6. S. D. Ferris, Elements of Electronic Design, Minneapolis, MN:
+
Vcc West Publishing Company, 1995, Chap. 12.
Q1 2 – 5V 7. B. Linaras-Barranco, E. Sanchez-Sinencio, and A. Rodriguez-Vaz-
Q2 quez, CMDS circuit implementation for neuron models, Proc.
R5
+ IEEE Int. Symp. Circuits Syst., New Orleans, LA, pp. 2421–
Iin – 100k
2424, 1990.
8. J. M. Rabaey, Digital Integrated Circuits, Upper Saddle River,
NJ: Prentice-Hall, 1996, Chap. 6.
– 9. A. J. Tocci, Digital Systems, Principles and Applications, 6th ed.,
Vss Upper Saddle River, NJ: Prentice-Hall, 1995.
–5 V 10. National Semiconductor, Linear Databook, Santa Clara, CA:
+
1982.
(a) 11. C. J. Savant, Jr., M. S. Roden, and G. L. Carpenter, Electronic
Circuit Design, An Engineering Approach, Menlo Park, CA:
0A Benjamin/Cummings, 1987.
12. R. L. Geiger, P. E. Allen, and N. R. Strader, VLSI Design Tech-
I(in1) niques for Analog and Digital Circuits, New York: McGraw-Hill,
1990.
–100 A 13. P. H. Beards, Analog and Digital Electronics, 2nd ed., New York:
Prentice-Hall, 1991.
10 V 14. I. M. Filanovsky and I. G. Finvers, A simple nonsaturated CMOS
multivibrator, IEEE J. Solid-State Circuits, 23(1): 289–292, 1988.
V(1) 15. D. J. Comer, Electronic Design with Integrated Circuits, Reading,
MA: Addison-Wesley, 1981, Chap. 3.
0V 16. G. M. Blair, Comments on new single-clock CMOS latches and
flip-flops with improved speed and power savings, IEEE J. Solid
1.0 V
State Circuits, 32(10): 1610–1611, 1997.

V(2) ROBERT W. NEWCOMB

University of Maryland, College
–1.0 V Park
4.0 V LOUIZA SELLAMI
U.S. Naval Academy

V(3)

–4.0 V MULTIVIBRATORS. See VARIABLE-FREQUENCY OSCIL-

LATORS.
5.0 V
MUSCLE SIGNALS. See ELECTROMYOGRAPHY.
V(4)

0V
0s 0.5 1.0 1.5 2.0
Time (ms)
(b)

Figure 14. (a) BJT monostable multivibrator. (b) Voltage waveforms

for the monostable multivibrator obtained from PSpice runs.

BIBLIOGRAPHY

1. A. S. Sedra and K. C. Smith, Microelectronic Circuits, New York:

Oxford Univ. Press, 4th ed., 1997, Chap. 12.
2. D. A. Hodges and H. G. Jackson, Analysis and Design of Digital
Integrated Circuits, 2nd ed., New York: McGraw-Hill, 1988,
Chap. 8.
NETWORK PARAMETERS
The Laplace transform is commonly used to solve network
equations. However, the mere computation of the solution
of network equations is one of the many important appli-
cations for this elegant tool of network analysis. Our pur-
pose here is to use this transform to define network func-
tion and to study the different ways of its representation,
the superposition theorem, the characterizations and rep-
resentations of one-port and two-port networks (1–3).
NETWORK PARAMETERS
We begin by considering a system of differential equations
associated with an electrical network, most conveniently
written in matrix notation as
where W(p), x(t), and f(t) are used to represent the coef-
ficient matrix of the differential operator p, the unknown
vector x(t) and the known forcing or excitation vector f(t).
On taking the Laplace transform on both sides, we obtain
a system of linear algebraic equations
where X(s) and F(s) denote the Laplace transforms of x(t)
and f(t), respectively, and h(s) is a vector that includes the
contributions due to initial conditions. The coefficient ma-
trix W(s) in the complex frequency variable s is obtained
from W(p), with s replacing p. An analysis of Eq. (2) is often
referred to as analysis in the frequency domain, in contrast
to the analysis of Eq. (1), which is called analysis in the time
domain.
Network Functions
The unknown transform vector X(s) can be obtained imme-
diately by inverting the matrix W(s):
provided that det W(s) is not identically zero.
Consider a linear time-invariant network that contains
a single independent voltage or current source as the input
with arbitrary waveform. Assume that all initial conditions
in the network have been set to zero. Let the response be
either a voltage across any two nodes of the network or a
current in any branch of the network. Such a response is
known as the zero-state response. Then, the network func-
tion H(s) is defined by
Network functions generally fall into two classes depend-
ing on whether the terminals to which the response relates
are the same or different from the input terminals. For the
J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright © 2007 John Wiley & Sons, Inc.
same pair of terminals, it is referred to as the driving-point
or input function; and for different pairs of terminals, the
transfer function. Since the input and the response may ei-
ther be a current or a voltage, the network function may be
a driving-point impedance, a driving-point admittance, a
transfer impedance, a transfer admittance, a transfer volt-
age ratio, or a transfer current ratio. Our objective here
is to obtain some general and broad properties of network
functions, recognizing that each of the network functions
mentioned has its own distinct characteristics.
Example. We write the nodal equations for the network
of Fig. 1 for t ≥ 0 after the switch S is closed and compute
the input impedance Zin facing the current source I and the
transfer current ratio relating the transform current I6 to
the transform current source I.
The nodal equations are found to be
By using Cramer’s rule, the nodal voltage V1 can be ex-
pressed in terms of the source current I as
Principle of Superposition
The principle of superposition is intimately tied up with the
concept of linearity, and is applicable to any linear network,
whether it is time invariant or time varying. It is funda-
mental in characterizing network behavior and is very use-
ful in solving linear network problems. For our purposes,
we shall restrict ourselves to the class of linear time in-
variant networks.
Consider an arbitrary linear time-invariant network
with many input excitations describable by a system of lin-
ear algebraic equations:
where
and the prime denotes matrix transpose. Suppose that the
kth row variable Xk of X(s) is the desired response. By ap-
pealing to Cramer’s rule, we obtain from Eq. (8)
Observe that Fi (s) (i = 1, 2, . . . , n) are due to the contri-
butions of independent sources. Therefore, to compute the
complete response transform Xk , we may consider each of
the transform sources Fi one at a time and then add the par-
tial responses so determined to obtain Xk . If Fi represents a
2 Network Parameters
Figure 1. A network used to illustrate network functions.
linear combination of many sources, each source can again
be considered separately, one at a time, and then add these
partial responses to obtain the complete response. This is
in essence the superposition principle.
Superposition Theorem. For a linear system, the zero-
state response due to all the independent sources acting
simultaneously is equal to the sum of the zero-state re-
sponses due to each independent source acting one at a
time. If, in addition, the system is time invariant, the same
holds in the frequency domain.
Two aspects of superposition are important to empha-
size. The first is the additivity property. The other is the
homogeneity property, which states that if all sources are
multiplied by a constant, the response is also multiplied by
the same constant.
Different versions of the superposition principle can be
advanced. It states that in a linear time-invariant system
the zero-input response is a linear function of the initial
state, the zero-state response is a linear function of the in-
put, and the complete response is the sum of the zero-input
response and the zero-state response. Thus, the complete
response of a linear network to a number of excitations
applied simultaneously is the sum of the responses of the
network when each of the excitations is applied individu-
ally. This statement remains valid even if we consider the
initial capacitor voltages and inductor currents themselves
to be separate excitations. Of course, the controlled sources
cannot be considered as separate excitations. In the case
of linear time-invariant networks, the same holds in the
frequency domain or in the transform network.
We apply the principle of superposition to compute the
inductor current i2 in the network of Fig. 2. When the volt-
age source is short-circuited, the inductor current i2 (t) is
found to be
When the current source is removed, the inductor current
i2 (t) is obtained as
Figure 2. A network used to illustrate the principle of superpo-
sition.
The inductor current i2 (t) is the algebraic sum of these two
currents:
Two-Port Networks
A network is a structure comprised of a finite number of
interconnected elements with a set of accessible terminal
pairs called ports at which voltages and currents can be
measured and the transfer of electromagnetic energy into
or out of the structure can be made. The situation is similar
to ships leaving or entering the ports. Fundamental to the
concept of a port is the assumption that the instantaneous
current entering one terminal of the port is always equal
to the instantaneous current leaving the other terminal of
the port. This assumption is crucial in subsequent deriva-
tions and resulting conclusions. If it is violated, the ter-
minal pair does not constitute a port. A network with one
such accessible port is called a one-port network or simply
a one-port, as represented in Fig. 3(a). If a network is ac-
cessible through two such ports as shown in Fig. 3(b), the
network is called a two-port network or simply a two-port.
The nomenclature can be extended to networks having n
accessible ports called the n-port networks or n-ports.
Figure 4 is a general representation of a one-port that
is electrically and magnetically isolated except at the port
with sign convention for the references of port voltage and
current as indicated. Likewise, Fig. 5 is a general represen-
tation of a two-port that is electrically and magnetically
isolated except at the two ports with sign convention for
the references of port voltages and currents as indicated.
By focusing attention on the ports, we are interested in the
behavior of the network only at the ports. Our discussion
will be entirely in terms of the transform network, under
the assumption that the one-port or two-port is devoid of
 Network Parameters 3

Figure 6. Representation of a two-port in terms of its short-

circuit admittance parameters yij .

Figure 7. Networks used to compute the short-circuit admittance

Figure 3. Symbolic representations of a one-port network (a), a parameters yij of a two-port.
two-port network (b), and an n-port network (c).

Figure 4. A general representation of a one-port with port voltage

and current shown explicitly.

Figure 8. A small-signal network model of a transistor.

culate these parameters, we set either V1 or V2 to zero and

Figure 5. A general representation of a two-port with port volt- obtain
ages and currents shown explicitly.

independent sources inside and has zero initial conditions.

Short-Circuit Admittance Parameters. Refer to Fig. 5.
There are four variables associated with the two ports: V1 ,
V2 , I1 , and I2 . Suppose that we choose port voltages V1 and
V2 as the independent variables. Then, the port currents
I1 and I2 are related to the port voltages V1 and V2 by the
equation
The choice of the name short circuit becomes obvious.
In computing y11 and y21 , the port V2 is short-circuited,
whereas for y12 and y22 , the port V1 is short-circuited, as
depicted in Fig. 7.
Example. Consider the equivalent network of a transis-
tor amplifier shown in Fig. 8. Applying Eq. (16) yields

or, in matrix form,

giving the short-circuit admittance matrix as

where I(s) = [I1 I2 ] is the port-current vector and V(s)
= [V1 V2 ] is the port-voltage vector. Equation (13) can be
represented equivalently by the network of Fig. 6. The four
admittance parameters yij (i, j = 1, 2) are called the short-
circuit admittance parameters or simply the y-parameters.
The coefficient matrix Y(s) is referred to as the short-circuit Open-Circuit Impedance Matrix. Instead of choosing the
admittance matrix or simply the admittance matrix. To cal- port voltages V1 and V2 as the independent variables, sup-
4 Network Parameters
Figure 9. Representation of a two-port in terms of its open-circuit
impedance parameters zij .
Figure 10. Networks used to compute the open-circuit
impedance parameters zij of a two-port.
pose that we choose port currents I1 and I2 as the indepen-
dent variables. Then, V1 and V2 are related to I1 and I2 by
the equation
or, in matrix form,
Equation (18) can be represented equivalently by the net-
work of Fig. 9. The four impedance parameters zij (i,j =
1,2) are called the open-circuit impedance parameters or
simply the z parameters. The coefficient matrix Z(s) is re-
ferred to as the open-circuit impedance matrix or simply
the impedance matrix. Obviously, if Z(s) is not identically
singular, its inverse is the short-circuit admittance matrix
or
and vice versa. To calculate these parameters, we set either
I1 or I2 to zero and obtain
The choice of the name open circuit becomes obvious. In
computing z11 and z21 , the port I2 is open-circuited, whereas
for z12 and z22 , the port I1 is open-circuited, as depicted in
Fig. 10.
Example. Consider the equivalent network of a transis-
tor amplifier shown in Fig. 8. Applying Eq. (21) yields
Figure 11. Representation of a two-port in terms of its hybrid
parameters hij .
Figure 12. Networks used to compute the hybrid parameters hij
of a two-port.
giving the open-circuit impedance matrix as
The Hybrid Parameters. Suppose that we choose port
variables I1 and V2 as the independent variables. Then,
the remaining port variables V1 and I2 are related to I1
and V2 by the equation
or, in matrix form,
where y(s) = [V1 I2 ] and u(s) = [I1 V2 ] . Equation (24)
can be represented equivalently by the network of Fig. 11.
The four immittance parameters hij (i,j = 1,2) are called
the hybrid parameters or simply the h parameters. The
coefficient matrix H(s) is referred to as the hybrid matrix.
To calculate these parameters, we set either I1 or V2 to zero
and obtain
In computing h11 and h21 , the port V2 is short-circuited,
whereas for h12 and h22 , the port I1 is open-circuited, as
depicted in Fig. 12. Thus, h11 is the short-circuit input
impedance, h21 is the short-circuit forward current ratio,
h12 is the open-circuit reverse voltage ratio, and h22 is the
open-circuit output admittance. These parameters are not
only dimensionally mixed but also under a mixed set of
terminal conditions. For this reason they are called hybrid
parameters.

Figure 13. Representation of a two-port in terms of its inverse
hybrid parameters gij .
Example. Consider the equivalent network of a transis-
tor amplifier shown in Fig. 8. Applying Eq. (27) yields
giving the hybrid matrix as
Inverse Hybrid Parameters. Suppose now that we choose
V1 and I2 as the independent variables. Then I1 and V2 are
related to V1 and I2 by the equation
or, in matrix form,
Equation (30) can be represented equivalently by the net-
work of Fig. 13. The four immittance parameters gij (i,j =
1,2) are called the inverse hybrid parameters or simply the
g parameters. The coefficient matrix G(s) is referred to as
the inverse hybrid matrix. To calculate these parameters,
we set either V1 or I2 to zero and obtain
If G(s) is not identically singular, its inverse is the hybrid
matrix or
Transmission Parameters. Another useful set of parame-
ters is formed by choosing V2 and −I2 as the independent
variables. Then V1 and I1 are related to V2 and −I2 by the
equation
The four immittance parameters A, B, C, and D are called
the transmission parameters, which are also known as the
chain parameters or the ABCD parameters. The coefficient
matrix is referred to as the transmission matrix. The first
two names come from the fact that they are the natural
Network Parameters 5
ones to use in a cascade, tandem, or chain connection of two-
ports. We remark that there is a negative sign associated
with I2 , being a consequence of our choice of reference for
I2 in Fig. 5. To calculate these parameters, we set either V2
or I2 to zero and obtain
Example. Consider again the equivalent network of a
transistor amplifier shown in Fig. 8. Applying Eq. (34)
yields
giving the transmission matrix as
By interchanging the roles of the excitation and the re-
sponse in Eq. (33), we obtain yet another set of parameters
called the inverse transmission or inverse chain param-
eters, and their corresponding matrix the inverse trans-
mission or inverse chain matrix, the details of which are
omitted.
Interrelations Among the Parameters Sets
The various ways of representing the external behaviors of
a two-port are presented in the foregoing. Each finds use-
ful applications, depending on the problem on hand. Table
1 gives the interrelationships among the different sets of
parameters.
Interconnection of Two-Ports
Simple two-ports are interconnected to yield more compli-
cated and practical two-ports. Two two-ports are said to be
connected in cascade or tandem if the output terminals of
one two-port are connected to the input terminals of the
other, as depicted in Fig. 14. This type of connection is
most conveniently described by the transmission param-
eters. From Fig. 14 we have for the two-port Nb
and for two-port Na
where the subscripts a and b are used to distinguish the
transmission parameters of Na and Nb . Combining Eqs.
6 Network Parameters

(37) and (38) gives

showing that the coefficient matrix, being the product of

two matrices, is the transmission matrix of the composite
two-port N. Thus, the transmission matrix of two two-ports Figure 14. Symbolic representation of two two-ports connected
connected in cascade is equal to the product of the trans- in cascade.
mission matrices of the individual two-ports:

Another useful connection is depicted in Fig. 15 where the

input terminals and output terminals of the individual
two-ports are connected in parallel, and is called a parallel
connection. This connection forces the equality of the termi-
nal voltages of the two-ports, and is most conveniently de-
scribed by the short-circuit admittance parameters. From
Fig. 15 we have

Figure 15. Symbolic representation of two two-ports connected

in parallel.

employ the Brune’s test as shown in Fig. 16: the voltage

showing that the short-circuit admittance matrix of the
composite two-port N is the sum of those of the component
two-ports Na and Nb .
We remark that the validity of Eq. (41) is based on the
assumption that the instantaneous current entering one
terminal of a two-port is equal to the instantaneous current
leaving the other terminal of the two-port after the inter-
connection. If this condition is violated, the statement that
when two two-ports are connected in parallel, their admit-
tance matrices add is no longer valid. To ensure that the
nature of the ports are not altered after the connection, we
marked V is zero. If Brune’s test is not satisfied, an ideal
transformer with turns ratio 1:1 is required, and this trans-
former needs to be inserted either at the output or input
port of one of the two-ports.
Example. Figure 17 is a simple RC twin-Tee used in the
design of equalizers. This two-port N can be considered as
a parallel connection of two two-ports Na and Nb of Fig.
18. It is easy to verify that the Brune’s test is satisfied and
the short-circuit admittance matrix Y(s) of the twin-Tee is
simply the sum of those Ya (s) and Yb (s) of the component

Figure 16. Brune’s test for parallel connection of two two-ports.
Figure 17. A twin-Tee used in the design of equalizers.
Figure 18. The parallel connection of two two-ports to form the
twin-Tee of Fig. 17.
two-ports Na and Nb :
Two two-ports Na and Nb are said to be connected in se-
ries if they are connected as shown in Fig. 19. This con-
nection forces the equality of the terminal currents of the
two-ports, and is most conveniently described by the open-
circuit impedance parameters. From Fig. 19 we have
showing that the open-circuit impedance matrix of the
composite two-port N is the sum of those of the component
two-ports Na and Nb .
Note again that the validity of Eq. (43) is based on the
assumption that the instantaneous current entering one
terminal of a two-port is equal to the instantaneous cur-
rent leaving the other terminal of the two-port after the
Network Parameters 7
Figure 19. Symbolic representation of two two-ports connected
in series.
Figure 20. Brune’s test for series connection of two two-ports.
Figure 21. Symbolic representation of two two-ports connected
in series-parallel.
Figure 22. Symbolic representation of two two-ports connected
in parallel-series.
interconnection. If this condition is violated, the previous
statement is no longer valid. To test to see if this condition
is satisfied, we employ the Brune’s test as shown in Fig. 20:
the voltage marked V is zero. If Brune’s test is not satisfied,
an ideal transformer with turns ratio 1:1 is required, and
this transformer needs to be inserted either at the output
or input port of one of the two-ports.
Combinations of the parallel and series connections are
possible such as the series-parallel and parallel-series con-
nections shown in Figs. 21 and 22.
8 Network Parameters

available average power P1a at the source:

Figure 23. A feedback network N.
Figure 24. A decomposition of the feedback network N into three
two-ports Na , Nb , and Nf .
Example. Consider the feedback network N of Fig. 23.
To compute its short-circuit admittance matrix Y(s), it is
advantageous to consider N as being composed of two two-
ports Na and Nb connected in cascade and then in parallel
with another Nf as depicted in Fig. 24. The transmission
matrix of the two two-ports Na and Nb connected in cas-
cade, being the product of their transmission matrices, is
given by
P2a
Gp = (48)
P1a
Therefore, it is a function of the two-port parameters and
the source impedance Z1 , being independent of the load
impedance Z2 .
Finally, the third and most useful measure of power flow
is known as the transducer power gain G defined as the
ratio of average power P2 delivered to the load to the max-
imum available average power P1a at the source:
P2
G= (49)
P1a
Clearly, it is a function of the two-port parameters and the
source and load impedances Z1 and Z2 . It is important be-
cause it compares the average power delivered to the load
with the average power that the source is capable of sup-
plying under the optimum terminations, thereby making
this the most meaningful description of the power transfer
capabilities of a two-port network. Notice that the three
power gains can only be meaningfully defined on the real-
frequency axis s = jω. In other words, we have substituted
s = jω in all the equations, even though they are not ex-
plicitly shown.
To show how these power gains can be expressed in
terms of the two-port parameters of Fig. 5 and Z1 and Z2 ,
we substitute V2 = −I2 Z2 in Eq. (18) and solve for I1 and
I2 , yielding
I2 z21
=− (50)
I1 z22 + Z2

where yija are the y-parameters of Na and
y = y11a y22a − The average power P1 entering the input port and the av-
y12a y21a . The corresponding admittance matrix of Eq. (44) erage power P2 delivered to the load Z2 are given by
is found from Table 1 as P1 = |I1 |2 Re Z11 (51)
P2 = |I2 |2 Re Z2 (52)
where Z11 is the impedance looking into the input port with
the output port terminating in Z2 .
The short-circuit admittance matrix Y(s) of the overall two-
The maximum available average power P1a at the input
port N of Fig. 23 is obtained as
port is attained, when the source impedance Z1 and the
°
input impedance Z11 are conjugately matched, or Z11 = Z1 ,
the complex conjugate of Z1 , giving
|Vs |2
P1a = (53)
4 Re Z1
Power Gains
where Vs is the voltage source at the input port.
Refer to the two-port network of Fig. 5. The simplest mea-
To express Z11 in terms of the two-port parameters zij
sure of power flow in N is the power gain Gp defined as the
and Z2 , we substitute V2 = −I2 Z2 in Eq. (18) and solve for
ratio of the average power delivered to the load P2 to the
I1 , yielding
average power entering the input port P1 :
V1 z12 z21
P2 Z11 = = z11 − (54)
Gp = (47) I1 z22 + Z2
P1
Combining Eqs. (51)–(55) obtains
which is a function of the two-port parameters and the load
impedance Z2 , being independent of the source impedance P2 |z21 |2 Re Z2 |z21 |2 Re Z2
Z1 . For a passive and lossless two-port network, G p = 1. Gp = = = z12 z21 (55)
P1 |z22 + Z2 |2 Re Z11 |z22 + Z2 |2 Re(z11 − z22 +Z2
)
The second measure of power flow is called the avail-
able power gain Ga defined as the ratio of the maximum P2 4|z21 |2 Re Z1 Re Z2
available average power P2a at the load to the maximum G= = (56)
P1a |(z11 + Z1 )(z22 + Z2 ) − z12 z21 |2
 Network Parameters 9

For the available power gain, we first compute Thévenin

equivalent voltage Veq and impedance Zeq looking into the
output port of Fig. 5, when the input port is terminated
in a series combination of a voltage source Vs and source
impedance Z1 :
z12 z21
Zeq = z22 − (57)
z11 + Z1
z21 Vs
Veq = (58)
z11 + Z1
Using this Thévenin equivalent network, the maximum
available average power at the output port is attained
°
when Z2 = Zeq , the complex conjugate of Zeq , obtaining
|z21 |2 |Vs |2
P2a = (59)
4|z11 + Z1 |2 Re Zeq
The available power gain is found to be
P2a |z21 |2 Re Z1
Ga = = (60)
P1a |z11 + Z1 |2 Re Zeq
which in conjunction with Eq. (57) gives
P2a |z21 |2 Re Z1
Pa = = z12 z21 (61)
P1a |z11 + Z1 |2 Re(z22 − z11 +Z1
)

Likewise, we can evaluate the three power gains in terms

of other two-port parameters as follows:
P2 |z21 |2 Re Z2 |y21 |2 Re Y2
Gp = = z12 z21 = y12 y21
P1 |z22 + Z2 |2 Re(z11 − ) |y22 + Y2 |2 Re(y11 − )
z22 + Z2 y22 + Y2
(62)
|h21 |2 Re Y2
=
h12 h21
|h22 + Y2 |2 Re(h11 − )
h22 + Y2
P2 4|z21 | Re Z1 Re Z2
2
4|y21 |2 Re Y1 Re Y2
G= = =
P1a |(z11 + Z1 )(z22 + Z2 ) − z12 z21 |2 |(y11 + Y1 )(y22 + Y2 ) − y12 y21 |2
(63)
4|h21 |2 Re Z1 Re Y2
=
|(h11 + Z1 )(h22 + Y2 ) − h12 h21 |2
P2a |z21 |2 Re Z1 |y21 |2 Re Y1
Pa = = z z = y12 y21
P1a |z11 + Z1 |2 Re(z22 −
12 21
) |y11 + Y1 |2 Re(y22 − )
z11 + Z1 y11 + Y1
(64)
|h21 | Re Z1
2
=
h12 h21
|h11 + Z1 |2 Re(h22 − )
h11 + Z1

BIBLIOGRAPHY

1. W. K. Chen Linear Networks and Systems: Algorithms and

Computer-Aided Implementations, Vol. 1 Fundamentals, 2nd
ed., Singapore: World Scientific, 1990.
2. M. E. Van Valkenburg, Network Analysis, 3rd ed., Englewood
Cliffs, NJ: Prentice-Hall, 1974.
3. W. K. Chen Active Network Analysis, Singapore: World Scien-
tific, 1991.
WAI-KAI CHEN
University of Illinois at Chicago,
Chicago, IL
NOISE GENERATORS
GENERATION OF NOISE
APPLICATIONS OF NOISE
Noise is a broadbanded signal generated by environmen-
tal effects, such as lightning, or by man-made electrical
devices. Two common categories of noise are thermal noise
and shot noise. Looney (1) describes thermal noise as an
electromotive force generated at the open terminals of a
conductor due to the charges bound to thermally vibrating
molecules. This type of noise is often referred to as John-
son noise in recognition of the first observations of the phe-
nomenon (2). On the other hand, shot noise is associated
with the passage of current across a barrier. For instance,
a circuit or an appliance that produces electric arcing pro-
duces noise. Shot noise was first described by Schottky us-
ing the analogy of a small shot patterning into a container
(3). Noise can be felt in audio systems as a crackle. Noise
appears as white or black spots on a television screen.
Noise is generally characterized as a source of corrup-
tion of information and therefore is treated as an undesired
signal. Noise contaminates informational signals to a cer-
tain extent by superimposing extrasignal fluctuations that
assume unpredictable values at each instant. Noise has
been studied extensively in the literature because noise
reduction is one of the major goals. A more compelling rea-
son for the study of noise is its potential application in real
life. These applications encompass biomedical engineering,
electronic circuits, communication systems, cryptography,
computers, electroacoustics, geosciences, instrumentation,
and reliability engineering. This article addresses the var-
ious noise generation techniques and implementing them
in analog and digital circuit technology and concludes with
a discussion of typical applications.
MODELING OF NOISE
A mathematical model of a phenomenon, such as noise, al-
lows us to understand its generation, characteristics and
application well. We start with the observation that the
structures of thermal and shot noise are similar, although
their sources are different. Both types of noise can be rep-
resented as a random wave form consisting of a sequence
of peaks randomly distributed in time. A noise signal can
be modeled by a random process X(t) with a probability
distribution for the values of x it assumes. Any particular
set of outcomes {(t, xt )} of the random variable Xt is called
a realization of the noise process. An adequate character-
ization of such a random process can be often made with
first- and second-order statistics. The first-order statistic
of X(t) is the expected value E[X(t)] and the second-order
statistic is the autocorrelation function RX (τ) = E[X(t)X(t +
τ)], where E is the expectation operator. When the first- and
J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright © 2007 John Wiley & Sons, Inc.
second-order statistics do not change over time, the process
is called wide-sense stationary (4).
Power spectral density, a standard measure used to de-
scribe a wide-sense stationary process, is defined as the
Fourier transform of the autocorrelation function RX (τ) (4):
With this modeling, we can analyze the spectra of noise.
White noise is a wide-sense stationary process with zero
mean. It has constant power spectral density over all fre-
quencies. Stated another way, white noise is a process
that is uncorrelated over time. The most mathematically
tractable noise is the Gaussian wide-sense stationary pro-
cess, where at each time t the probability distribution for
the random variable Xt = X(t) is Gaussian.
Colored noise is a variation of white noise which arises
from the fact that actual circuits attenuate signals above
certain frequencies. Therefore it makes sense to truncate
the white noise spectral density at both extremes. Noise
with this spectral characteristic is termed pink noise.
Apart from thermal noise and shot noise, a third cate-
gory of noise observed in electronic systems is the 1/f noise.
It is so called because the power spectral density of this
noise varies with frequency as |f|−α , where α takes val-
ues between 0.8 and 1.2. This type of noise is exhibited by
biological and musical systems in addition to electronics
(3). 1/f noise is variously called current noise, excess noise,
flicker noise, semiconductor noise, and contact noise. It is
applied in medical treatment and also in engineering, jus-
tifying the need for inclusion in our study.
NOISE GENERATION TECHNIQUES
Noise can be generated in many different ways. A diode
tube operating at its saturation point produces broadband
noise. A semiconductor diode is an inexpensive source of
noise generation. When operated in the fully conducting
region, the diode produces broadband noise. A current-
carrying resistor produces thermal noise. It is necessary
to condition noise signals by proper amplification, modu-
lation, and filtering to suit one’s application at a desired
bandwidth. In our discussion of noise generation, we con-
centrate only on semiconductor techniques because ap-
proaches based on vacuum tubes are antiquated now.
The noise generation schemes range from simple me-
chanical techniques to electronic methods employing both
analog and digital circuits. Inexpensive noise generators
can be realized with discrete components and basic build-
ing blocks available in the IC market. We classify the noise
generators into two categories, namely, analog and digital,
based on their implementation.
Analog Techniques
Under this category, we discuss three different approaches:
(1) a mechanical scheme, (2) amplifying inherent noise in
op-amps, (3) oscillator method, and (4) using the chaotic
behavior of deterministic systems.
2 Applications of Noise
Figure 1. A simple analog noise generator based on amplification
of op-amp input noise.
Mechanical Approach. For audio-frequency noise, a very
simple scheme can be devised at home or in the laboratory
without any sophisticated circuits or components. Dunn (5)
uses just a linen-covered phonograph and a foam-covered
microphone. A piece of linen cloth is tied to the turntable
and a foam-covered microphone is used to pick up the sig-
nal. As the turntable rotates, the microphone’s foam cover
rubs along the surface of the linen, producing sound with
a nearly flat spectral density in the audio-frequency range
of 20 Hz to 20 kHz. Dunn shows that by using a good hi-fi
microphone and a broadband amplifier, the output signal
closely approximates white noise over the audio-frequency
range. Other mechanical approaches include the use of
gears and radioactive decay (6).
Amplification of Inherent Noise. The schematic of a rel-
atively simple op-amp noise generator is shown in Fig.
1, which uses a single bipolar input amplifier and some
discrete components. The principle used here to generate
wideband noise is to amplify its own input noise in a de-
compensated op-amp (7). Many op-amps have large 1/f in-
put noise components. A bipolar input op-amp is chosen
because bipolar devices exhibit much less 1/f noise than
MOSFET devices.
In the figure, the op-amp is used as a fixed-gain stage
amplifier with a closed-loop gain factor:
If the input resistors R2 and R3 are chosen small, the ther-
mal noise of the amplifier is forced to a small value. This
choice of low values for the resistors also helps keep the
amplifier’s current noise component negligibly small when
it is converted to voltage noise. Thus, the dominant noise
of the circuit is the input voltage noise of the amplifier.
The choice of a single gain stage amplifier of the type
shown in Fig. 1 results in a frequency-independent noise.
This contrasts with multistage amplifiers which may have
peaks in the output noise response caused by frequency
compensation effects. The values for resistors R1 and R2
can be designed by knowing the typical noise of the op-amp
from data sheets and the required level of noise across the
load RL . The output is coupled through a blocking capacitor
C1 which removes any amplified dc value at the output of
the amplifier. However, the value of this capacitor should
be large enough to pass the lowest noise frequencies of in-
terest. Interested readers may refer to Ref. 7 for a detailed
circuit diagram and typical component values used to gen-
erate a noise of 50 nV/ . Op-amp AD829 is used in the
circuit which features flat voltage noise in the range of 100
Hz to 10 MHz.
Oscillator Method. A popular analog class of noise gen-
erators is the oscillator method (8), which samples the fre-
quency noise or instability of free-running oscillators. In
this scheme, the output of a fast oscillator is sampled on
the rising edge of a slower clock using a D flip-flop. Oscil-
lator jitter causes uncertainty in the exact sample values,
ideally producing a random bit for each sample. For further
details, readers may refer to 9.
Using Chaos in Deterministic Systems. Another elegant
way of generating white noise is based on the observation
that certain simple deterministic systems exhibit chaotic
behavior (10). The chaos or noise is generated by iterat-
ing a map either electronically or in a software program.
A simple and most widely studied system for generating
chaos is the logistic map (10) given by:
The asymptotic behavior of the system described by the
parabolic transfer function of Eq. (3) depends on the value
of λ. McGonigal and Elmasry (11) show that values of λ
between 0.89 and 1.0 result in oscillations without any de-
tectable period. In fact, this is the region of chaotic behavior
leading to power spectral density corresponding to white
noise.
A noise generator can be implemented in hardware to
test actual instruments or in software for simulation. Mc-
Gonigal and Elmasry (11) use a multiplier and a differ-
ence amplifier to realize the term xi − x2i of the parabolic
transfer function of Eq. (3). A variable-gain amplifier con-
nected to the output of the differential amplifier, as shown
in Fig. 2, allows variation of λ. The iteration of the trans-
fer function is realized by the feedback of the xi+1 signal
as the next xi input. The clock-driven multiplexer and the
storage capacitors shown in the figure separate the im-
pulses at the output of the circuit. During clock signal ck,
the voltage on capacitor C1 provides the input xi whereas
the resulting output xi+1 is stored on C2 . During <over-
line>ck</overline>, the roles of the capacitors are reversed
leading to two iterations of the parabolic function in ev-
ery clock cycle. The IC numbers and typical values of the
discrete components are shown in the figure to generate a
power spectrum from dc to 1 kHz. Experimental study in
11 confirms that the signal is uncorrelated in the chaotic
region and that the power spectral density remains flat in
this region. Interested readers may refer to 11 for further
details of the circuit and a trace of the power spectrum.
The software implementation of the deterministic-
chaotic, variably colored, noise generator is shown in Fig. 3.
Colored noise is generated by organizing chaotic elements
into a hierarchy and coupling them (12). Each element of
the hierarchy is modeled as a recursive loop whose output
is a sequence of impulses. The unit delay element shown in
the figure separates the instances of impulses of varying
amplitude at the output. The gain unit and the nonlinear
amplifier implement the map xi+1 = gn f(xi ). The output at

Figure 3. Block schematic of a software-based, deterministic-
chaotic, variably colored noise generator.
any instant becomes the input at the next instant. The ini-
tiator block is used only to set the amplitude of the first im-
pulse and is then disconnected. This software setup yields
sequences of impulses which are essentially aperiodic and
hence noiselike from a practical point of view (12).
Researchers have used discrete, nonlinear, one-
dimensional maps (13) that yield a transition between
regions of chaotic motion to produce 1/f noise. The cir-
cuits used to implement such discrete maps are usually
switched-capacitor type because discrete maps are de-
scribed by nonlinear, finite-difference equations and they
can be easily and accurately implemented by switched-
capacitor circuits. Delgado–Restituto et al. (14) build a
programmable prototype to generate colored noise to test
systems with spectral density proportional to 1/f. They
use op-amps and switched capacitors to realize a chaotic,
one-dimensional, piecewise-linear discrete map that yields
a hopping transition between regions of chaotic motion.
Murao et al. (15) propose a simple switched-capacitor
circuit that realizes a one-dimensional, nonlinear, discrete
map as opposed to a piecewise-linear approximation. With
an IC and a couple of logarithmic and antilogarithmic
amplifiers, they can synthesize a simple 1/f noise gener-
ator over a wide range of frequencies compared with the
previous method of Delgado–Restituto et al. (14).
Applications of Noise 3
Figure 2. A low-frequency noise generator
based on logistic map (from 11, courtesy of IEEE,
© 1987 IEEE).
Figure 4. Structure of a programmable noise generator.
Of the four techniques of noise generation based on
chaotic behavior of deterministic systems discussed here,
the first is used for white noise generation, whereas the
next three implementations generate colored noise. Al-
though colored noise is derived by properly filtering the
output of white noise sources (16), the direct methods de-
scribed here are simpler and lend themselves to easy VLSI
implementation. Some other simple IC-compatible chaos
generators are found in 17 and 18.
Programmable Noise Generators. It is often desirable to
have a programmable noise generator. The variability is
achieved by multiplying the noise signal by a factor K and
then passing the signal through a noise filter, as shown in
Fig. 4. A linear phase filter passes frequencies between F1
and F2 , thus band-limiting the filter output noise. In the
simulated noise generator of (19), the output is sampled at
a particular rate and stored in a data array. The statistics of
the output data, such as mean, variance, min, and max are
stored in another data array. This kind of programmable
noise generator produces uniform Gaussian noise whose
output noise power is set by adjusting the K factor shown
in the figure.
Digital Techniques
The first generation digital noise generators utilized ran-
dom waveforms based on telegraph signals to obtain ran-
dom noise (20). For application in modern digital circuits,
however, pseudorandom number sequence generators pro-
vide a better basis. Pseudorandom numbers are generated
with linear congruent algorithms (21). If noise is needed
4 Applications of Noise
in analog form, the numbers generated in binary form are
converted to analog quantity. The analog output at the con-
verter is essentially Gaussian white noise. This signal can
be filtered appropriately to obtain colored noise. Figure 5
shows the block schematic of a digital noise generator.
Linear Feedback Shift Register as Random Number
Generator. The digital circuitry implementing the pseudo-
random number generator can be realized using a linear
feedback shift register (LFSR). An LFSR consists of two ba-
sic digital building blocks, D-type flip-flops and exclusive-or
gates. The LFSR draws theory from cyclic error-detecting
codes (22) where all algebraic manipulations on polyno-
mials are done in GF(2), that is, Galois field-modulo-2 ad-
dition, subtraction, multiplication, and division of binary
vectors. A k-stage LFSR generates at most (2k − 1) distinct
binary patterns which then repeat on itself. In general, the
length of the sequences generated depends on the size of
the LFSR and the polynomial representing it. If the poly-
nomial representing the LFSR is primitive (22), the LFSR
generates a maximal length sequence [(2k − 1) vectors]. If
the polynomial is irreducible but nonprimitive, then the
length of the sequence is not maximal and depends on the
initial contents of the LFSR, called the seed. The presence
of internal memory in the LFSR makes the choice of the
seed critical for nonprimitive case. In the primitive case,
the seed does not affect the statistical properties of the
output. However, if all of the flip-flops are set to zero, the
LFSR remains dormant and is useless.
The upper block of Fig. 6 shows an LFSR implementa-
tion of a primitive polynomial of degree six:
where ⊕ is the exclusive-or operator. In this implementa-
tion of LFSRs, the output and selected internal stages of
the LFSR corresponding to the nonzero terms of the poly-
nomial are exclusive-ored and fed back to the input. The
pseudorandom digital output sequence is plotted in Fig.
7. A clock frequency of 1 MHz is used to run the LFSR.
Because a six-stage LFSR is used, the period of the pseu-
dorandom output waveform is 63 µs. For clarity the figure
shows a couple of periods of the waveform.
In the following, we describe several implementations of
digital noise generators. They all have LFSRs as the basis
for random number generation and use low-pass filtering
to obtain the analog noise signal.
Analog Conversion by Time Integration. Alspector et al.
(23) use a low-pass filter to convert the digital waveform at
the outputs of the LFSR to a voltage signal. The cutoff fre-
quency of the filter is kept at just a few percent of the clock
frequency used to drive the LFSR. This arrangement has
the effect of performing a time integration over many bits.
If each bit is equally likely (i.e., a 0 or 1 with equal proba-
bility) as is the case in LFSRs, the value of this integration
Figure 5. Block schematic of a basic digital noise generator.
follows a binomial distribution that approaches Gaussian
for a large number of bits. This creates a Gaussian pseudo-
random noise source whose statistical properties are anal-
ogous to thermal or shot noise. A variable amplifier with
gains low enough to avoid any coupling is used at the out-
put.
Analog Conversion by a Resistive Network. D’Alvano and
Badra (24) use a resistive network to convert the digital sig-
nal to an analog signal, as shown in the lower block of Fig.
6. The shift register outputs are linearly combined through
the resistive network which also plays the role of the coeffi-
cient set of a discrete-time FIR filter. These weights provide
a low-pass transfer function with a raised-cosine impulse
response. The output level at the filter is adjusted through
a 1 k trimmer.
The probability density function of the noise signal at
the output can be predicted because of the random na-
ture of the binary sequence generated at each of the shift-
register outputs. The random binary variables added to
form the noise signal are statistically independent from
one another. From the central limit theorem (4), it follows
that the probability density function of the signal at the
output is asymptotically Gaussian.
To illustrate noise generation, we have performed a sim-
ulation using commercial software produced by MicroSim
Corporation, USA. Figure 8 shows a trace of analog noise
observed at the output of the op-amp (see Fig. 6). What
is shown in Fig. 8 is repetitive noise. The periodicity in
the noise is an undesirable feature, yet inevitable when
small-size LFSRs are used for pseudorandom number se-
quence generation. The periodicity can be broken by ran-
domly changing the seed of the LFSR. The periodicity can
also be improved by lengthening the shift register. Inter-
ested readers may refer to (24) for details of the circuit
which produces truly random noise.
High-Frequency Noise Generation. A shift-register-based
noise generator can be realized for RF noise power metrol-
ogy (25). Superconducting rapid, single-flux, quantum
(RSFQ) logic (26) is used to meet the requirements of low
noise and fast switching necessary to generate noise in the
gigaHertz range. In the RSFQ logic, the binary informa-
tion is coded by flux quanta with the value φ0 = h/2e in su-
perconducting interferometers and is transmitted and pro-
cessed as very short voltage pulses V(t) of quantized area.
The active circuit components are overdamped Josephson
junctions (JJ) which need only dc bias currents set to val-
ues slightly below their critical currents. With these el-
ements, SFQ pulses can be created, transmitted, repro-
duced, amplified, processed, and detected (25). The basic
RSFQ logic elements for constructing complex digital cir-
cuits are available in current technology. Superconducting
microstrip lines together with JJ technology allow trans-
mitting picosecond waveforms with very low attenuation
and dispersion. In a pseudorandom noise generator of this

Figure 6. A six-stage linear feedback shift register with a resistive network for digital-to-analog
conversion.
type, the logic enables the generation of pseudostatisti-
cal SFQ pulse sequences, operating as quasi-shot noise
sources.
Arrays of Noise Generators. It is often necessary to have
an array of noise generators, especially in neural networks
(25). Although such noise generators can be designed with
LFSRs, one should be careful to avoid any correlation
among the outputs of these noise generators. Alspector et
al. (23) accomplish this by tapping the outputs from various
stages of the LFSR and processing them using exclusive-
or gates and low-pass filters. A cellular automaton is used
by Dupret et al. (27) to generate arrays of Gaussian white
noise sources. Cellular automata feature regular structure
leading to compact VLSI layouts.
APPLICATION OF NOISE GENERATORS
Noise generators are used in a variety of testing, calibra-
tion, and alignment applications especially with radio re-
ceivers. Some of the other applications are in digital com-
munication, analog integrated circuit diagnosis, and learn-
Applications of Noise 5
ing processes of stochastic neural networks. In digital com-
munication, noise is added as an “uncertainty” to a crypto-
graphic exchange to confuse the information and to prevent
unauthorized use or forgery. This is increasingly important
in today’s electronic-commerce society. Random signals are
also used for dithering in analog electronic circuits, forcing
a signal to use the entire dynamic range of an analog sys-
tem, one which reduces distortion. These applications can
be classified into four categories: noise used as a broad-
band random signal, measurements in which noise is used
as a test signal, measurements in which noise is used as a
probe into microscopic phenomena, and noise as a concep-
tual tool. This categorization of applications was first made
by Gupta (28) and is used here. We include some examples
and illustrations.
Noise as a Broadband Random Signal
This kind of signal is widely used in electronic countermea-
sures, microwave heating, simulation of random quanti-
ties, stochastic computing, and generation of random num-
bers. Noise generators are used to simulate random vibra-
tions in mechanical systems. The combination of a random
6 Applications of Noise

Figure 7. The waveform of the digital sequence at the output of LFSR.

noise generator and a shake table is widely used to test the Noise as a Test Signal in Measurements
response of mechanical structures to random vibrations.
There are several cases of measurements where one needs
A well-known application of a high-power broadband
a broadband signal with known properties like amplitude
noise generator is active jamming of radar and communi-
probability density and an autocorrelation function. Ran-
cation equipment. Radar jamming is called active if the
dom noise is one such source and is ideal for measuring im-
jammer radiates a signal at the operating frequency of
pulse response, insertion loss, linearity and intermodula-
the radar system, as distinguished from passive jamming
tion of communication equipment, and in noise-modulated
which employs nonradiating devices like chaff. The broad-
distance-measuring radar.
band jamming signal can be generated either by a noise
It is well known (4) that if a random signal X(t) with
generator centered at the carrier frequency or by noise
autocorrelation function RX (τ) is applied at the input of
modulating a continuous wave signal.
a linear system with an impulse response H(t), the cross-
An interesting medical application is inducing sleep or
correlation between the input and the resulting output Y(t)
anesthesia and suppressing dental pain in a technique
is given by the convolution integral
called audio-analgesia. A dental patient listens to relaxing
music via earphones, and switches to filtered random noise
on feeling pain, increasing the intensity of noise as neces-
sary to suppress pain. It is reported that audio-analgesia
has about the same level of effectiveness as morphine (29). This relationship can be used to calculate the impulse re-
In modern musical instruments, white or color noise sponse H(t) if RX and RXY are known. For causal, lumped,
generators are successfully used to generate the sound ef- linear, time-invariant systems, this calculation can be car-
fect of desert wind, ocean surf, thunderstorm, lightning, ried out algebraically. However, solving the integral equa-
and even the virtual cosmic background sound. tion for H(t) is greatly simplified by using white noise as
the input signal. If the bandwidth of the input signal is

much larger than that of the system under test, RX (τ) is
effectively the impulse function δ(τ), and the equation sim-
plifies to
Thus the impulse response is directly measured without
involved calculation.
Spina and Upadhyaya (30) use the previous observation
on impulse response measurement in testing and diagnos-
ing analog VLSI. Here, a white noise generator is used as
input stimuli to the analog chip. At the output of the circuit
under test, a pattern classifier which is usually an artifi-
cial neural network does the signature analysis and hence
fault diagnosis. Alspector et al. (23) study application of
noise as input to facilitate learning in parallel stochastic
neural networks.
Noise is used in measuring linearity and intermodula-
tion in a communication channel as follows. When a large
number of telephone channels are to be carried by a coax-
ial cable or a broadband radio link, any existing nonlinear
distortions in the system introduce unwanted intermod-
ulation products of the various components of the multi-
plexed signal. Calculation of the intermodulation noise so
introduced is very difficult because of the large number of
channels. Because statistical properties of white noise are
similar to those of a complex multichannel signal with a
large number of intermittently active channels, white noise
is used to simulate such a signal. A band-limited Gaussian
white noise is introduced at the input into the system un-
der test. The noise power in a test channel is measured
first with all channels loaded with white noise and then
with all but the test channel loaded with white noise. The
ratio of the first to the second measurement is called the
Applications of Noise 7
Figure 8. A simulation trace of an
analog noise signal.
noise power ratio from which the channel noise due to in-
termodulation can be calculated. The spectral density of
input noise can be shaped to match the signal under ac-
tual operating conditions.
The use of noise generators for checking system per-
formance in manufacturing or in the laboratory is com-
monly known. The procedure can be extended to in-service
monitoring of radar and communication equipment in the
field because of the development of solid-state noise gener-
ators which have smaller power consumption, weight, vol-
ume, radio-frequency interference, turn-on time, and turn-
off time, but higher noise power output and reliability than
gas-discharge noise generators. As a result, the need for re-
tuning or servicing the equipment is recognized before its
performance becomes unacceptable. As the noise signal is
very small and unrelated to all other signals, the monitor-
ing can be carried out while the equipment is in operation,
thus reducing the downtime due to checkups.
Noise is specifically used in the noise immunity test
of several digital systems and TV pictures (31). High fre-
quency noise generators are needed in RF noise-power
calibration. The shift-register-based noise generator using
RSFQ logic can function at frequencies up to 45 GHz (25)
and can be used for this purpose. Digital, pseudorandom
numbers are also used to test a random collection of input
possibilities with test circuits built on-chip.
Noise as a Probe into Microscopic Phenomena
Noise measurements can be used for estimating physi-
cal parameters related to microscopic phenomena, such as
emission, recombination, or ionizing collision. Noise can
also be used in testing semiconductors for uniformity and
for estimating the reliability of semiconductor devices. Us-
 8 Applications of Noise

Table 1. Commercial noise generators and their characteristics

Designation Function Name of Manufacturer Noise Type and Range Technique Used
TSC-300 White Noise Marpac Sound Generator Electronic
Generator White noise
DNG 7500 Digital Noise Noise/Com White Digital
Generator Gaussian noise
K4301 Pink Noise QualityKits Pink Noise Pseudorandom
Generator (Digital noise)
ANG Automated Noise Micronetics Truly Gaussian Analog
Generator
CNG-70/140 Carrier to Noise dBm White Noise Not available
Generator (50-180 MHz)
AM700 Mixed Signal Audio Tektronix Shaped Noise Analog
Measurement Set White & Pink
3024 Very Random noise ACO Pacific, Inc. White & Pink Digital
Generator (1.6 Hz to 39 kHz) (pseudorandom)
SMT02 Signal Generator Rohde & Schwarz 500 kHz bandwidth Not Available
SMT03, 06
IE-20B Pink and White Ivie Technologies, Pink & White Digital
Inc.
PNG-2000 Portable Noise Research Audio frequency Not Available
Generator Electronics, Intl. (300 Hz to 3 kHz)
DS345 Waveform Generator Stanford Research White Noise Digital
Systems Wideband (10 MHz)
DS360 Low Distortion Stanford Research White and Pink Digital
Function Generator Systems
NG-1 Audible Noise Audio Technologies, White & Pink Not Available
Generator Inc.
PNG-7000 Precision Noise Noise/Com Gaussian White Noise Not Available
Generator
UFX7000 Programmable Noise Noise/Com Broadband Noise Microprogram controlled
Generator (10 Hz to 40 GHz)

ing noise in device reliability prediction has several ad-
vantages over conventional lifetime tests. Noise testing is
nondestructive and does not take up a considerable frac-
tion of the life of the device being tested. It also allows
testing a specific individual device rather than measuring
an average lifetime for a lot.
There are many ways in which measuring the noise in
a device can be used to make reliability predictions. For
instance, transistors with low 1/f noise exhibit longer life
spans, and reverse-biased p–n junction diodes having a
noise power spectral density with multiple peaks undergo
rapid degradation. It has been found experimentally that
the low-frequency 1/f noise output of a transistor increases
by two or three orders of magnitude shortly before failure
(28).
Noise as a Conceptual Tool
Noise is the motivating cause for developing new disci-
plines like information theory, the statistical theory of com-
munication, and circuit theory. It is also useful as a vehicle
for theoretical investigations and for modeling other phys-
ical systems. For example, the concepts and principles de-
veloped with electrical noise have been used as guides in
working with thermodynamics. Noise has been used as a
tool for interpreting impedance in circuit theory. It has also
led to the development of some analogies between quantum
mechanics and the analyses of noisy circuits and systems
and has helped simplify the concept of the quantum me-
chanical uncertainty principle. For further details, readers
may refer to (28).
COMMERCIAL NOISE GENERATORS
A number of companies sell noise generators either as sep-
arate instruments or as part of an apparatus, such as a
function generator. Table 1 lists the model numbers and the
names of the manufacturers along with various features
of the instruments including noise range, the technique
used in the design, and application areas where known.
Some of the instruments are portable and battery-powered,
whereas others are somewhat bulky. This list is not exhaus-
tive and is provided only as a quick reference. The address
of each company is provided in Table 2 as a ready reference.
Although the internal circuitry of these noise generators is
not available, the reader may refer to other guidebooks on
electronics circuits, such as (32) which contains the circuit
diagram of digital white noise generators, thermal noise
generators using incandescent lamp, and a simple diode
noise generator.
ACKNOWLEDGMENTS
The author acknowledges Yi-Hao Wang, Shu Xia, and Ar-
shad Nissar for their help in the simulation effort.

1.
 Applications of Noise 9

Table 2. Companies that make noise generators

Marpac Corporation
P.O. Box 560
Rocky Point, NC 28457 USA

QKits Limited
49 McMichael St.
Kingston, ON K7M 1M8, Canada

Micronetics
26 Hampshire Drive
Hudson, NH 03051 USA

dBm
6 Highpoint Drive
Wayne, New Jersey 07470 USA

Tektronix, Inc.
1500 North Greenville Avenue
Richardson, TX 75081 USA

ACO Pacific, Inc.

2604 Read Avenue
Belmont, CA 94002, USA

Rohde & Schwarz

Muhldorfstrasse 15
81671 Munchen (Munich), Germany

Ivie Technologies, Inc.

1605 N West State St.
Lehi, UT 84043-1084 U.S.A.

Research Electronics International

455 Security Place
Algood, TN 38506, USA

Stanford Research Systems

1290-D Reamwood Avenue
Sunnyvale, California 94089, USA

ATI - Audio Technologies, Incorporated

154 Cooper Rd. # 902
West Berlin, NJ 08091 USA

Noise Com
25 Eastmans Road
Parsippany, New Jersey 07054-3702 USA

Tundra Semiconductor Corporation

603 March Road
Kanata, Ontario, K2K 2M5, Canada

BIBLIOGRAPHY 5. J. Dunn White-noise generator, Electron. Design, 44: 90, 1996.

C. Looney Noise, in R. Dorf (ed.), The Electrical Engineering
Handbook, 2nd ed., Boca Raton, FL: CRC Press, 1997, pp.
1642–1653.
2. J. Johnson Thermal agitation of electricity in conductors, Na-
ture, 119: 50–51, 1927.
3. M. Buckingham Noise in Electronic Devices and Systems, New
York: Wiley, 1983.
4. A. Papoulis Probability, Random Variables, and Stochastic
Processes, 3rd ed., New York: McGraw-Hill, 1991.
6. B. Schneier Applied Cryptography, New York: Wiley, 1994.
7. W. Jung Simple wideband noise generator, Electron. Design,
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8. L. Letham et al. A 128K EPROM using encryption of pseudo-
random numbers to enable read access, IEEE J. Solid State
Circuits, 21: 881–889, 1986.
9. C. S. Petrie J. A. Connelly A noise-based random bit generator
IC for applications in cryptography, Proc. Int. Symp. Circuits
Systems, 197–201, June 1998.
10 Applications of Noise

10. R. May Simple mathematical models with very complicated Department of Computer
dynamics, Nature, 261: 459–467, 1976. Science & Engineering, State
11. G. McGonigal M. Elmasry Generation of noise by electronic University of New York at
iteration of the logistic map, IEEE Trans. Circuits Syst., CAS- Buffalo, Buffalo, NY, 14260
34: 981–983, 1987.
12. R. Bates A. Murch Deterministic-chaotic variably-colored
noise, Electron. Lett., 23 (19): 995–996, 1987.
13. R. Devaney An Introduction to Chaotic Dynamical Systems,
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14. M. Delgado–Restituto et al. A chaotic switched-capacitor cir-
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325–328, 1992.
15. K. Murao et al. 1/f noise generator using logarithmic and
antilogarithmic amplifiers, IEEE Trans. Circuits Syst. I, 39:
851–853, 1992.
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17. M. Delgado-Restituto et al. Nonlinear switched-current
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18. J. T. Bean P. J. Langlois A current-mode analog circuit for tent
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19. F. Vitaljic Programmable noise generator, Electron. Design, 44:
122, 1996.
20. H. Sutcliffe K. Knott Standard LF noise sources using digital
techniques and their application to the measurement of noise
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stochastic neural networks, IEEE Trans. Circuits Syst., 38:
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shift register for applications in RF noise power metrology,
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white noise sources for analogue VLSI implementation, Elec-
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996–1010, 1975.
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30. R. Spina S. Upadhyaya Linear circuit fault diagnosis using
neuromorphic analyzers, IEEE Trans. Circuits Syst. II, Analog
Digit. Signal Process., 44: pp. 188–196, 1997.
31. T. Takagi Composite noise generator as a noise simulator and
its application to noise immunity test of digital systems and
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McGraw-Hill, 1974.
SHAMBHU J. UPADHYAYA
570 NONLINEAR FILTERS

NONLINEAR FILTERS

Numerous linear and nonlinear digital filters have been de-

veloped for a wide range of applications. Linear filters enjoy
the benefits of having a well-established and rich theoretical
framework. Furthermore, real-time implementation of linear
filters is relatively easy since they employ only standard oper-
ations (multiply and add) and can also be implemented using
fast Fourier transforms. In many cases, however, the restric-
tion of linearity can lead to highly suboptimal results. In such

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

cases, it may be desirable to employ a nonlinear filter (1,2).
Furthermore, as digital signal processing hardware becomes
ever more sophisticated and capable, complex nonlinear oper-
ations can be realized in real time. For these reasons, the field
of nonlinear filters has grown and continues to grow rapidly.
While many applications benefit from the use of nonlinear
methods, there exist broad classes of problems that are funda-
mentally suited to nonlinear methods and which have moti-
vated the development of many nonlinear algorithms. In-
cluded in these classes of problems are the following:
1. Suppression of Heavy-Tailed Noise Processes. Sim-
plifying approximations and the Central Limit Theorem
often lead to the assumption that corrupting noise pro-
cesses are Gaussian. However, many noise processes
are decidedly heavy-tailed, or impulsive, in nature (i.e.,
have probability density functions with relatively high
valued tails). Linear filters often do a poor job sup-
pressing such noise, necessitating the use of robust non-
linear methods.
2. Processing of Nonstationary Signals. Linear filters tend
to be sensitive to nonstationarities (changes in local sig-
nal statistics), which are common in images and bio-
medical signals, for example. In images and video se-
quences, nonstationarities in the form of edges and
scene changes are abundant. Linear processing of such
data for restoration or enhancement may produce
blurred edges and/or ringing artifacts, which can seri-
ously degrade visually important features.
3. Super-resolution Frequency Extension. Frequency anal-
ysis shows that linear methods can be designed to ei-
ther amplify or attenuate signal power at selected fre-
quencies. However, linear filters are incapable of
restoring frequency content to a signal from which it
has been completely eliminated. Such frequency content
extension requires nonlinear methods and is important
in applications such as the restoration of high-resolu-
tion broad-band images from low-resolution narrow-
band realizations.
4. Modeling and Inversion of Nonlinear Physical Systems.
Signals are generally acquired through physical sys-
tems (such as transducers or optics) that are inherently
nonlinear. Both the accurate modeling of such systems
and the inversion of their effects on acquired signals
necessitate the use of nonlinear methods.
Here we describe a variety of nonlinear filters and identify
some current areas of research on nonlinear methods. An ex-
tensive treatment of nonlinear filters can be found in the
books by Astola and Kuosmanen (1) and by Pitas and Venet-
sanopoulos (2). The fact that nonlinear methods lack a unify-
ing framework makes presenting a general overview difficult.
However, we organize the presented filters into two general
methodologies:
1. Weighted Sum Filters. The output of a linear filter is
formed as a linear combination, or weighted sum, of ob-
served samples. Nonlinearities can be introduced into
this general filtering methodology by transforming the
observation samples, through reordering or nonlinear
warping for instance, prior to the weighting and sum-
NONLINEAR FILTERS 571
ming operations. We refer to all filters that form an esti-
mate through linear combinations in this way as
weighted sum filters.
2. Selection Filters. Combining samples to form an esti-
mate, especially in a weighted sum fashion, can lead to
cases where corrupted samples have a disproportionate
influence on the estimate. Moreover, the output of a
weighted sum estimate is generally an intermediary
sample that is not equal to any of the observed samples,
which is undesirable in some applications. These issues
are addressed by a broad class of nonlinear filters (re-
ferred to as selection filters) that restrict their output
to be one of input samples.
Weighted sum filters combine the benefits of linear filters
with some strategically designed nonlinearity to provide the
desired result. Selection filters tend to offer robustness from
outliers, provided that a proper selection rule is implemented.
That is, as long as an outlier is not selected to be the output,
the outlier is effectively removed and generally has little im-
pact on the filter output. Furthermore, selection filters gener-
ally do not blur edges in signals since the output is forced to
be one of the input samples and no intermediate transition
samples are created by the filter. In the following analysis,
we show that many useful nonlinear filters can be placed into
these two broad categories. Signal and image processing ex-
amples are included at the end of this article to illustrate the
performance of selected filtering methods. Also, numerous ref-
erences are provided to allow the reader to pursue the study
of the filters described in greater detail.
The organization of the remainder of this article is as fol-
lows. In the section entitled ‘‘The Filtering Problem,’’ the fil-
tering problem is described and much of the notation is de-
fined. The general class of nonlinear weighted sum filters is
described in the section entitled ‘‘Nonlinear Weighted Sum
Filters.’’ The family of selection filters is described in the sec-
tion entitled ‘‘Selection Filters.’’ Illustrative filtering exam-
ples are provided in the section entitled ‘‘Filtering Examples,’’
where selected filters are applied to the restoration of an im-
age embedded in Gaussian noise, to the restoration of an im-
age contaminated by impulsive noise, and, finally, to edge en-
hancement. Some conclusions are provided in the section
entitled ‘‘Conclusions.’’
THE FILTERING PROBLEM
The goal in many filtering applications is to transform an ob-
served signal into an approximation of a desired signal, where
the transformation is designed to optimize some fidelity crite-
rion. This scenario is illustrated in Fig. 1, where 兵x(n)其 and
兵y(n)其 represent the observation (input) and approximation
(output) sequences, respectively. In this representation,
{ d(n)}
–
{ x(n)} { y(n)} { e(n)}
Filter Σ
+
Figure 1. The filtering problem where an observed signal is trans-
formed by the filtering operation to approximate a desired signal.
474 OVERVOLTAGE PROTECTION

OVERVOLTAGE PROTECTION

Most semiconductor devices are intolerant of overvoltage

transients in excess of their voltage ratings. Even a microsec-
ond overvoltage transient can cause a semiconductor to fail
catastrophically or may result in severe stress, reducing the
useful life of the equipment. Overvoltage transients in electri-
cal circuits result from the sudden release of previously stored
energy. Some transients may be created in the circuits by in-
ductive switching, commutation voltage spikes, and so on.
Other transients may be created outside the circuit and then
coupled into it. These can be caused by lightning, capacitor-
bank switching at the substation, or similar phenomena. This
article discusses overvoltage protection in terms of the follow-
ing three categories:

1. Overvoltage transients
2. Overvoltage protection devices
3. Overvoltage protection for switch-mode power supplies

OVERVOLTAGE TRANSIENTS

Overvoltage transients in a low-voltage (600 V or less) ac

power circuit originate from two major sources: system
switching transients and direct or indirect lightning strikes
on the power system. A sudden change in the electrical condi-
tion of any circuit will cause a transient voltage due to the
stored energy in the circuit inductance or capacitance.
Switching-induced transients are a good example of this; the
rate of change of current (di/dt) in an inductor (L) will gener-
ate a voltage

V = −Ldi/dt (1)

The transient energy is equal to

E = 1/2Li2 (2)

This energy exists as a high-power impulse for a relatively

short time (J ⫽ Pt). Consider an example as shown in Fig. 1.
If load 2 is shorted, load 1 and/or the diode rectifier will be
subjected to a voltage transient. As load 2 is shorted, the fuse
will open and interrupt the fault current. The power supply
will produce a voltage spike equal to Eq. (1) with an energy

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.
 OVERVOLTAGE PROTECTION 475

Fuse
+ +
Power A
supply 0
Short
Load Load across VAB
B 1 2 Load 2
– Figure 1. Overvoltage transient due to
– change of current in an inductor.

content of Eq. (2). This transient may be beyond the voltage
limitations of the diode rectifiers and/or load 1. Switching out
a high-current load will have a similar effect.
Energizing a Transformer Primary. When a transformer pri-
mary is energized at the peak of the supply voltage, the cou-
pling of this voltage step function to the stray capacitance and
inductance of the secondary winding can generate a transient
voltage with a peak amplitude up to twice the normal second-
ary voltage. Figure 2 shows a circuit in which the secondary
side is a part of the capacitive divider network in series with
the transformer interwinding capacitance (CS). This stray ca-
pacitance has no relation to the turns ratio of the trans-
former, and it is possible that the secondary circuit may see
a substantial fraction of the applied primary peak voltage.
sulting collapse of the magnetic flux in the core, couples a
high-voltage transient into the transformer’s secondary wind-
ing, as shown in Fig. 3. Unless a voltage-limiting device is
provided, this high-voltage transient appears across the load.
Switch Arching. When the current in an inductive circuit,
such as a relay coil or a filter reactor, is interrupted by a
contactor, the inductance tries to maintain the current by
charging the stray capacitance. Similar behavior can occur
during closing if the contacts bounce open after the initial
closing, as shown in Fig. 4. During the opening and closing of
the electromechanical switches, the bouncing action of con-
tacts can result in high-frequency overvoltage transients.

Deenergizing a Transformer Primary. The opening of the pri-

mary circuits of a transformer generates extreme voltage
Closing
transients in excess of ten times the normal voltage. Inter-
switch
rupting the transformer magnetizing current, and the re-
+ –

Closing CS
switch VP VS

IM

L
VP VS
C

CS C Load

;; ;;
;;;;
Line
voltage
Load
Line Vp
voltage
Vp Magnetizing
current iM

; ;
and flux
Switch

;
Switch
closed opened
Secondary
voltage Vs Voltage
Vs-PK transient
Secondary
voltage
Vs

Figure 2. Voltage transient caused by energizing transformer Figure 3. Voltage transient caused by interruption of transformer
primary. magnetizing current.
476 OVERVOLTAGE PROTECTION

stress current is relatively low, of the order of 200 A

VCAP VLINE
Solid-state
VSUPPLY
equipment
Figure 4. Voltage transients caused by switch arcing.
Random Transients
Overvoltage transients create the most confusion because it
is difficult to define their amplitude, duration, and energy
content. In general terms, the anticipated surge voltage level
depends on the location of the equipment to be protected.
When it is inside a building, the stress depends on the dis-
tance from the electrical service entrance to the equipment,
the size and length of the connection wires, and the complex-
ity of the branch circuits. IEEE Std. 587-1980 proposes three
location categories for low-voltage ac power circuits that are
representative of a majority of locations from the electrical
service entrance to the most remote wall outlet. These catego-
ries are shown in Fig. 5 and described as follows:
1. Category A: Outlets and Long Branch Circuits. This is
the lowest-stress category in which outlets and branch
circuits are ‘‘long distance’’ from electrical service en-
trance. This category includes all outlets more than 10
m (30 ft) from category B with #14 to #10 AWG wires.
It also includes all outlets more than 20 m (60 ft) from
service entrance with #14 to #10 wires. In category A,
the stress voltage may be of the order of 6 kV, but the
(a) (b) (c)
maximum.
2. Category B: Major Feeders and Short Branch Circuits.
This category covers the highest-stress conditions likely
to be subjected to an equipment power supply. It applies
to distribution panel boards, bus and feeder systems in
industrial plants, heavy appliance outlets with ‘‘short’’
connections to the service entrance, and lightning sys-
tems in commercial office buildings. Note that category
B locations are closer to the service entrance, so stress
voltage of the order of 6 kV and stress current level of
up to 3000 A may be expected.
3. Category C: Electrical Service Entrance and Outdoor Lo-
cations. This location is defined as the power line be-
tween pole and electrical service entrance of a building.
Very high stress conditions can occur. Since most of the
sensitive electronic equipment will be in category A and
B, within a partially protected environment inside the
building, only protection to categories A and B is nor-
mally required.
Rate of Occurrences
The rate of occurrence of voltage transients varies over a wide
range, depending on a particular power system, although low-
level surges are more prevalent than high-level transients.
Prediction of the rate of occurrence for a particular system is
always difficult and frequently impossible. Data collected
from various sources are the basis of the curves shown in
Fig. 6.
1. Low Exposure. These are systems with little load-
switching activity, which are located in geographical
areas of light lightning activity.
2. Medium Exposure. Medium-exposure systems are in
areas of frequent lightning activity and severe switch-
ing transients problems.
3. High Exposure. These are rare but real systems sup-
plied by overhead lines and subject to reflections at line

103

High
2
exposure
10
Surge per year in excess

Medium
of crest kV of abscissa

exposure
101

1
Sparkover of
clearances
Figure 5. Location categories. (a) Outlets and Long Branch Circuits: (note)
10–1
All outlets at more than 10 m (30 ft) from Category B with wires #14 Low
to #10; All outlets at more than 20 m (60 ft) from Category C with exposure
wires #14 to #10. (b) Major Feeders and Short Branch Circuits: Distri-
10–2
bution panel devices; Bus and feeder systems in industrial plants; 0.3 0.35 1 2 5 10 20
Heavy appliance outlets with ‘‘short’’ connections to the service en- Surge crest (kV)
trance; Lighting systems in commercial. (c) Outside and Service En-
trance: Service drop from pole to building entrance; Run between me- Figure 6. Rate of surge occurrence versus voltage level at unpro-
ter and distribution panel; Overhead line to detached buildings; tected locations. Note: In some locations, sparkover of clearances may
Underground lines to well pumps. limit the overvoltages.
 OVERVOLTAGE PROTECTION 477

Table 1. Surge Voltages and Current Deemed to Represent the Indoor Environment and Suggested for Consideration in
Designing Protective Systems
Energy (Joules) Deposited
Impulse in a Suppressor c
with Clamping Voltage of
Comparable Medium-
to IEC 664 Exposure Type of Specimen 500 V 1000 V
Location Category Category Waveform Amplitude on Load Circuit (120 V System) (240 V System)
A. Long branch circuits and II 0.5 ms–100 kHz 6 kV High impedance a — —
outlets 200 A Low impedance b 0.8 1.6
B. Major feeders short branch III 1.2/50 애s 6 kV High impedance a — —
circuits, and load center 8/20 애s 3 kA Low impedance b 40 80
0.5 ms–100 kHz 6 kV Low impedance a — —
500 A High impedance b 2 4
a
For high-impedance test specimens or load circuits, the voltage shown represents the surge voltage. In making simulation tests, use that value for the open-
circuit voltage of the test generator.
b
For low-impedance test specimens or load circuits, the current shown represents the discharge current of the surge (not the short-circuit current of the power
system). In making simulation tests, use that current for the short-circuit current of the test generator.
c
Other suppressors which have different damping voltages would receive different energy levels.

ends, where the characteristics of the installation pro-
duce high sparkover levels of the clearances.
These data were taken from unprotected (no limiting volt-
age devices) circuits, meaning that the transient voltage is
limited only by the sparkover distance of the wires in the dis-
tribution system.
Overvoltage Transient Waveforms
The definition of a transient waveform is critical for the de-
sign of overvoltage protection circuitry. An unrealistic voltage
waveform with long duration of the voltage or very low source
impedance requires a high-energy protection device, resulting
a cost penalty to the end-user. IEEE Std. 587 defines two ov-
ervoltage current waveforms to represent the indoor environ-
ment recommended for use in designing protection devices.
Table 1 describes the waveforms, open circuit voltage, source
impedance, and energy stored in the protection circuitry.
sentative of category I indoor low-voltage (ac lines less
than 600 V) system transients. This 100 kHz ring wave
has a rise time of 0.5 애s (from 10% to 90% of its final
amplitude), with oscillatory decay at 100 kHz, each
peak being 60% of the previous one. The rapid rate of
rise of the waveform can cause dv/dt problems in the
semiconductors. The oscillating portion of the waveform
produces voltage polarity reversal effects. Some semi-
conductors are sensitive to polarity changes or can be
damaged when unintentionally turned on or off.
V
0.9 VPEAK VPEAK
0.5 VPEAK
0.3 VPEAK

1. Category I. The waveform shown in Fig. 7 is defined as T1 50 µ s

‘‘0.5 애s–100 kHz ring wave.’’ This waveform is repre-
T1 × 1.67 = 1.2 µ s

0.9 VPEAK VPEAK

IPEAK
0.9 IPEAK
T = 10 µ s (F = 100 kHz)

0.5 IPEAK
0.1 VPEAK
0.5 µ s
0.1 IPEAK

T2
20 µ s
60% of VPEAK T2 × 1.25 = 8 µ s

Figure 7. 0.5 애s to 100 kHz ring wave (open-circuit voltage). Figure 8. Unidirectional waveshapes.
478 OVERVOLTAGE PROTECTION

ZS 2. Category II. In this category, close to the service en-

trance, much larger energy levels are encountered. Both
oscillatory and unidirectional transients have been re-
corded in this outdoor environment. IEEE Std. 587 rec-
ZV
VOC ZV VZV = ( ( VOC ommends two unidirectional waveforms and an oscilla-
ZV + ZS tory waveform for category II. These two waveforms are
shown in Fig. 8. The various stress conditions are com-
puted in Table 1.
Figure 9. Voltage-clamping device.
OVERVOLTAGE PROTECTION DEVICES

There are two major categories of transient suppressors: (1)

those that attenuate transients, thus preventing their propa-

Table 2. Characteristics and Features of Transient Voltage Suppressor Technology

Follow Clamping Energy Response
V–I Characteristics Device Type Leakage on I Voltage Capability Capacitance Time Cost

V Ideal device Zero to No Low High Low or high Fast Low

Clamping voltage low

Working voltage
I
Transient current

V Zinc oxide varistor Low No Moderate to High Moderate to Fast Low

low high
Working
voltage
I

V Zener Low No Low Low Low Fast High

Max I limit
Working
voltage
I

Peak voltage Crowbar (Zener– Low Yes Low Medium Low Fast Moderate
V (ignition) SCR combination) (latching
Working holding I )
voltage
I

Peak voltage Spark gap Zero Yes High ignition High Low Slow Low to
V
(ignition) voltage high
Working Low clamp
voltage
I

V Peak voltage Triggered spark gap Zero Yes Lower ignition High Low Moderate High
(ignition) voltage
Working Low clamp
voltage
I

V Selenium Very No Moderate to Moderate High Fast High

high high to high

Working
voltage

V Silicon carbide High No High High High Fast Relative

varistor low
Working
voltage

I

Line Fuse
+ of the voltage results from the increased voltage drop in the
Ac
Rectifier Switch mode IC
input power supply
– (Fig. 9). The voltage-clamping device cannot be effective with
Figure 10. SCR crowbar overvoltage protection circuit for switching
power supplier.
gation into the sensitive circuit; and (2) those that divert
transients away from sensitive loads and so limit residual
voltages. Attenuating a transient, that is, keeping it from
propagating away from the source or keeping it from imping-
ing on a sensitive load, is accomplished with series filters
within a circuit. The filter, generally of low-pass type, attenu-
ates the transients (high-frequency) and allows the signal or
power flow (low-frequency) to continue undisturbed. Diverting
a transient can be accomplished with a voltage-clamping de-
vice or with a ‘‘crowbar’’ type device.
Filters. The frequency of a transient is several orders of
magnitude above the power frequency (50/60 Hz) of an ac cir-
cuit. Therefore, an obvious solution is to install a low-pass
filter between the source of transients and the sensitive load.
The simplest form of filter is a capacitor placed across the
line. The impedance of the capacitor forms a voltage divider
with the source impedance, resulting in attenuation of the
transients at high frequencies. This simple approach may
have undesirable effects, such as (1) unwanted resonance
with inductive components located in the circuit resulting in
high-peak voltages; (2) high capacitor in-rush current during
switching, and (3) excessive reactive load on the power system
voltage. These undesirable effects can be minimized by add-
ing a series resistor (RC snubber circuit).
Voltage-Clamping Devices. A voltage-clamping device is a
component having variable impedance depending on the cur-
rent flowing through the device or on the voltage across its
terminal. These devices exhibit nonlinear impedance charac-
teristics. Under steady-state, the circuit is unaffected by the
presence of the voltage-clamping device. The voltage-clamp-
ing action results from increased current drawn through the
Voltage (VH )
Q1
FS1
Q2
(fuse)
R1
Ac
input – C0
A1
+ SCR
R2
RIF, V
Transformer
rectifier Series regulator
and shooting circuit
circuit
OVERVOLTAGE PROTECTION 479
device as the voltage tends to rise. The apparent ‘‘clamping’’
source impedance due to the increased current. It must be
R clearly understood that the device depends on the source im-
Load
pedance to produce clamping. One is seeing a voltage divider
SCR action at work, where the ratio of the division is nonlinear
zero source impedance. Table 2 lists various types of voltage-
clamping devices and their features and characteristics.
Crowbar Devices. Crowbar-type devices involve a switch-
ing action, either the breakdown of a gas between electrodes
or turn-on of a thyristor. After switching on, the crow-bar de-
vice offer a very low impedance path which diverts the tran-
sient away from the parallel-connected load. These crowbar
devices have two limitations. The first is their delay time, typ-
ically microseconds, which leaves the load unprotected during
initial voltage rise. The second limitation is that a power cur-
rent from the steady-state voltage source will follow the tran-
sient discharge current (called ‘‘follow current’’ or ‘‘power-
follow’’).
OVERVOLTAGE PROTECTION FOR SWITCH-MODE
POWER SUPPLIES
During fault conditions, most power supplies have the poten-
tial to deliver higher output voltages than those normally
specified or required. If unprotected, the higher output volt-
age can cause internal and external equipment damage. To
protect the equipment under these abnormal conditions, it is
common practice to provide some means of overvoltage pro-
tection within the power supply. Overvoltage protection tech-
niques for switch-mode power supplies fall broadly into
three categories:
1. Simple SCR ‘‘crowbar’’ overvoltage protection
2. Overvoltage protection by voltage-clamping techniques
3. Overvoltage protection by voltage-limiting techniques
SCR ‘‘Crowbar’’ Overvoltage Protection
Figure 10 shows the principle of a SCR (silicon-controlled rec-
tifier) ‘‘crowbar’’ overvoltage protection circuit connected to
the output of a switch-mode power supply. If the output volt-
age increases under a fault condition, the SCR is turned on
and a short-circuit is imposed at the output terminals via the
ZD1
R5
Load
R4
R3 C1
Simple crowbar
circuit Figure 11. A simple SCR crowbar circuit
for linear regulators.
480 OVERVOLTAGE PROTECTION
Dc
supply
Figure 12. Shunt regulator type voltage
clamp circuits. (a)
resistor R, and the overvoltage condition is prevented. With
linear regulator-type dc power supplies, SCR crowbar overvol-
tage protection is the normal protection method, and the sim-
ple circuit shown in Fig. 11 is often used. The linear regulator
and crowbar operate as follows:
The dc output voltage, VH, is regulated by a series transis-
tor, Q1, to provide a lower but regulated output voltage, Vout.
Amplifier A1 and resistors R1 and R2 provide the regulator
voltage control, and transistor Q2 and current-limiting resis-
tor R1 provide the current-limiting protection. The worst case
overvoltage condition would be a short-circuit of the series-
regulating device Q1 so that the higher unregulated voltage,
VH, is now presented to the output terminals. Under such
fault conditions, both voltage control and current limiting ac-
tions are lost, and the crowbar SCR must be activated to
short-circuit the output terminals.
In response to such a fault condition, the overvoltage pro-
tection circuitry in Fig. 11 responds as follows: As the voltage
across the output terminals rises above the voltage-limiting
threshold of the circuit, or zener diode ZD1 conducts the driv-
ing current via R4 into SCR gate C1. After a short delay de-
fined by the values of C1, R4, and the applied voltage, C1
charges will reach gate firing voltage (0.6 V), and SCR will
conduct to short-circuit the output terminals via low-value
limiting resistor R5. However, a large current now flows from
Dc
Converter
input
–
Ramp
comparator
Figure 13. Typical overvoltage shutdown
protection circuit for switch mode power
supplier.
+Output +Output
Zener diode Dc Shunt regulator
voltage clamp supply voltage clamp
– –
(b)
the unregulated dc input voltage through the shunt-connected
SCR. To prevent overdissipation in the SCR, it is necessary
to use a fuse, FS1, or circuit-breaker in the unregulated dc
supply. If the series regulator device Q1 has failed, the fuse
or circuit breaker now clears to disconnect the source from
the output before the SCR is destroyed. This approach is pop-
ular for many noncritical applications. Although this circuit
has the advantage of low cost and circuit simplicity, it has
ill-defined operating voltage, which can cause large operating
spreads. Design modifications can be incorporated to over-
come these limitations.
Overvoltage Clamping Technique
In low-power applications, overvoltage protection may be pro-
vided by a simple clamp action. In many cases, a shunt-con-
nected zener diode is sufficient to provide the required over-
voltage protection [see Fig. 12(a)]. If higher current capability
is required, a more powerful transistor shunt regulator may
be used [Fig. 12(b)]. It should be noted that when a voltage
clamp device is employed, it is highly dissipative, and the
source resistance must limit the current to acceptable levels.
Hence, shunt clamping action can be used only where the
source resistance (under failure conditions) is large. In many
cases, shunt protection of this type relies on the action of a
Opto
coupler
ZD1
SCR2
Overvoltage
protection cct
Voltage
control cct

separate current or power-limiting circuit for its protective
performance. An advantage of the clamp technique is that
there is no delay in the voltage clamp action, and the circuit
does not require resetting upon removal of the voltage con-
dition.
Overvoltage Clamping with SCR Crowbar Backup
For low-power application, an SCR crowbar circuit can be
used in parallel with a zener clamp diode. In that case, the
advantage of the fast-acting voltage clamp can be combined
with the more powerful SCR crowbar. With this design, the
delay required to prevent spurious operation of the SCR will
not compromise the protection of the load, as the zener clamp
diode will provide protection during the SCR delay period.
Overvoltage Protection by Voltage-Limiting Technique
Figure 13 shows a typical example of a voltage-limiting circuit
used in switch-mode power supplies. In this circuit, a sepa-
rate optocoupler is energized in the event of an overvoltage
condition. This triggers a small-signal SCR on the primary
circuit to switch off the primary converter. The main criterion
for such protection is that the protection loop is entirely inde-
pendent of the main voltage control loop. This may be impos-
sible to achieve if a single IC is employed for voltage control
and shut-off. Additional design modifications may become
necessary.
Voltage-limiting circuitry may either latch, requiring cy-
cling of the supply input to reset, or be self-recovering, de-
pending on application requirements. In multiple output ap-
OVERVOLTAGE PROTECTION 481
plications, where independent secondary limits or regulators
are provided, the voltage limit circuit may act upon the cur-
rent limit circuit to provide the overvoltage protection. Once
again, the criterion is that a single component failure should
not result in an overvoltage condition. Many techniques are
used solid are beyond the scope of this article.
Reading List
K. H. Billings, Switch Mode Power Supply Handbook, New York:
McGraw-Hill.
M. Brown, Practical Switching Power Supply Design, Motorola Semi-
conductor, Inc. Series in Solid State Electronics.
S. Cherniak, A Review of Transients and Their Means of Suppression,
Motorola Application Note AN843, Motorola Semiconductor, Inc.
A. Greenwood, Electrical Transients in Power Systems, 2nd ed., New
York: Wiley, 1991.
IEEE Recommended Practice on Surge Voltages in Low-Voltage AC
Power Circuits, IEEE C62.41-1991.
Transient Voltage Surge Suppression Devices, DB 450.4, Harris
Semiconductor, 1995.
ASIF JAKWANI
Current Technology, Inc.
P. ENJETI
Texas A & M University
OXIDE RAMP DIODES. See SCHOTTKY OXIDE RAMP
DIODES.
J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering
Copyright
c 1999 John Wiley & Sons, Inc.

PHASE-LOCKED LOOPS, APPLICATIONS

Phase-locked loops (PLLs) are used for a variety of functions, all of which may be incorporated in a generic
PLL form. The fundamentals of PLL systems are actually rather straightforward, but are typically enshrouded
in mystery. This mystery stems in part from the difficulty of identifying the basic signal components in the
loop and of understanding the unit as a feedback system with the peculiarities related to its phase-detector
properties. This article provides a foundation of principles, including those of tracking and acquisition. From
this foundation, several applications will be explored with the intent of providing an approach toward extending
the concepts and not simply being able to replicate the analysis and design discussed.
The PLL has wide application. The majority of its applications fall into the four main categories frequency
synthesis, frequency (FM) and phase (PM) modulation and demodulation, data and carrier recovery, and
tracking filters. Applications for each category will be considered.

The Generic Phase-Locked Loop

Definition. The basic PLL is rather simple in concept. However, we extend it a bit to include most
of the features of interest in a loop. The generic loop is shown in Fig. 15. Features that have been included
are frequency synthesis, frequency offset, and modulation and detection. The phase detector is shown as
a multiplier, since many classic phase detectors actually use the process of multiplication to extract phase
information about a nominal phase shift of 90◦ . Many of the loop effects may be absorbed into the simpler
model of Fig. 1 without any loss of generality. This basic PLL includes all the behavioral blocks needed for
analysis of loops. The components of the basic loop are a phase detector (PD), a low-pass filter (LPF), and a
voltage-controlled oscillator (VCO). In reality, the oscillator may be current-controlled and may be preceeded
by an amplifier to adjust the range of performance of the oscillator or make a filter active. It is not uncommon
to have to allow for additional delays and for low-pass filter effects at the input of the oscillator. Such delays
and filtering increase the need for adequate phase and amplitude margins of the open-loop gain compared to
unity at −180◦ , in order to prevent oscillation of the feedback system. The latter would cause either a highly
undesired frequency modulation of the VCO or a total loss of frequency lock in the loop.
An aspect that causes much grief for newcomers to PLL systems is the varied notation. We will use typical
notation and explain the meaning of each item as we proceed through the concepts. Many of the terms lend
themselves to approximations that offer excellent predictions of system results.
A PLL is generally analyzed as a linear, feedback-control system with a transfer function H(s) representing
the relationship between the input phase θs and the VCO phase θo . This transfer function is one of the most
confusing features of PLL analysis to the newcomer. In the signal sense, we have phase as a signal, not voltage
or current amplitude. Thus, the frequency response is that of a time-varying phase, not of the amplitude
variations in a typical input signal. Once this dual-frequency concept is understood, the analysis of a PLL is
1
2 PHASE-LOCKED LOOPS, APPLICATIONS

Fig. 1. Basic PPL, offering the most basic structure of a PLL needed for analysis, and consisting of a VCO, phase detector,
loop filter, and possible amplifier.

rather straightforward. The transfer function just mentioned is written as

This transfer behavior is typically written in terms of the linear transfer characteristics of the control-
system open-loop transfer function G(s). From Fig. 1 we have

where the VCO is modeled as an integrator (the VCO converts the control voltage V c into an instantaneous
frequency, which is then integrated to obtain the phase). The gain terms provide the appropriate conversion,
such as voltage to frequency for the VCO. The overall gain K is found with a variety of subscripts in the
literature, which we have chosen not to use. In the control-theory context, the phase detector acts as a difference
block—comparing the phase of the incoming signal with that of the VCO. The units used throughout the loop
are the radian and the volt. In some cases, the ampere is appropriate for a particular device, simply requiring
a change of the appropriate terms.
The filter used in a PLL is basically a low-pass filter designed to reject harmonics and spurious frequencies
generated in the phase-detection process, a design requirement not typically found in control systems. This
cutoff of the filter should be greater than the bandwidth of the PLL. However, additional filter shaping may also
used to enhance the bandwidth and performance of the PLL. A simple lag–lead filter may be used to narrow
the loop bandwidth, followed by a lag (or low pass) to provide the out-of-band low-pass filtering. In discussing
filters, we will generally neglect this latter out-of-band lag filter, which should always be added to a PLL.
The use of integrators in the filter facilitates tracking of velocity and acceleration signals (velocity signals
have a constant offset frequency, while acceleration signals have a changing offset frequency over time, typical
of the Doppler shift in a low-earth-orbit satellite system). These integrators allow the steady-state phase error
to be zero for specific applications, an important feature for many phase-demodulation processes.
 PHASE-LOCKED LOOPS, APPLICATIONS 3

Since the filters and the loop VCO response are generally monotonically decreasing in amplitude with
increasing frequency, it is obvious that H(s) may be simply approximated in two separate ranges as

where ω is the bandwidth of the loop. A major problem in PLL design is ensuring that G(s) does not approach
−1 near the bandwidth of the loop. If the latter occurs, then substantial ringing or possible instability of the loop
should be expected. To avoid this stability difficulty, the loop is specified with a sufficient damping factor, phase
margin, or gain margin at ω = ω. The analytical treatment of the stability must take account of possible stray
delays in the system caused by low-pass coupling of oscillator control lines and related connections needed
for circuit isolation. It is common to simply add some extra margin to allow for common stray effects, but
such actions should be taken carefully, since they may add substantial switching delays and performance
degradation in an operational system. It should be noted that the PLL bandwidth ω is not the bandwidth
of a filter inserted in the loop, but rather comes from an interaction of the loop filter with the entire loop,
particularly the feedback filter effects of the VCO.
A secondary transfer function that is important for evaluating the limitations of the system is the error
transfer function relating the phase error to the input phase. This function may be written as

This error function is critical in the determination of the limits beyond which the signal may cause the
loop to lose lock, or simply to exceed the linear range of the components of the loop—most commonly the
phase detector or active filters. Additional transfer functions may be defined to describe the modulation and
demodulation processes of both FM and PM systems, as will be considered with specific applications. For
FM, the product of the modulation signal and the error transfer function tends to peak at ω. This peak
substantially increases the probability of the phase range of the detector being exceeded, causing a loss of lock
in the vicinity of ω. This peaking suggests that ω would be a good frequency to be check during loop testing.
Simple Phase-Locked-Loop Analysis. The simple linear analysis of a PLL starts with Eq. (2) written
as

Thus the basic analysis and design stem from the choice of the open-loop gain K and the filter function F.
It is common to assume that F is monotonically decreasing in frequency, though this need not be the case. If
F = 1, then the transfer function is simply a low-pass filter defined by a radian bandwidth of K. In practice, an
additional filter pole is added above the loop bandwidth for rejection of spurious signals created by the phase-
detector process (generally a form of multiplication) and will only increase the rejection of higher frequencies
in the loop, not having a substantial effect on the in-lock performance. If this additional filtering is not used
with multivibrator VCOs, the resultant output of the VCO will have a duty cycle related to the phase error.
4 PHASE-LOCKED LOOPS, APPLICATIONS

Let us consider the poor choice of a lag filter to control the bandwidth by adjusting the filter bandwidth
relative to K. In this case we would have

The new transfer function is commonly written as

where ωn is called the natural frequency and ζ is the damping factor. In controls, ζ takes on an important role
in the stability of the system. Generally speaking, ζ should not be chosen any smaller than about 1/ . That
exact value leads to optimal coupling for the system, in the sense that smaller coupling values lead to transient
ringing, while larger values lead to longer transient times or slower responses. Actual choices of ζ must also
allow for spurious delays in the system. The corresponding response of such a transfer function to a step change
in phase is easily obtained using Laplace transforms and is given by Blanchard (1) as

where θo represents the transient phase equivalent of the output phase, o . For ζ< 0.707, substantial oscillatory
behavior near ωn is created that dies out at the rate 1/τ (τ being the filter time constant), slower than K. For
larger ζ, the trigonometric functions become hyperbolic and the solution becomes a double exponential in 1/τ
and K. This connection with the actual parameters being selected is sometimes scaled out of the problem,
leaving the designer in a bit of a quandary about how to make some of the choices. In this case, it is clear that
the decay at the rate of K is the limiting feature of the loop. If K is not adjustable, the only consideration with
a lag filter is setting τ for good rejection of the spurious output frequencies created by the detector outside of
the bandwidth of K.
A lag–lead filter offers a reasonable alternative to adjustment of the loop gain constant. The lag–lead
filter and response are given by

The step response for this loop is similar to the last case and is given by Blanchard as (1)
 PHASE-LOCKED LOOPS, APPLICATIONS 5

Fig. 2. Bode plot of a second-order filter and the associated G and H magnitudes. The lag–lead properties of the filter
are seen in the two breakpoints of the filter response |F|. The filter behavior produces |G| as |F/s|, resulting in a transfer
function H with response of unity within the passband and G outside the passband.

where ωn = and ζ= (1 + Kτ2 ) / (2 ). This response has a key τ1 that was missing with the
simple lag filter. As τ1 is increased to narrow the filter response, the zero of the filter may also be changed. In
essence, the effective gain of the loop is changed to Kτ2 /τ1 , with a fundamental pole at − Kτ2 /τ1 and a second
pole at about − 1/τ2 as long as the response of F changes almost entirely within the bandwidth of the loop. This
is easily seen in a Bode plot of H along with the plots of |F| and |G|, as in Fig. 2 with τ1 = 0.1 s, τ2 = 1 s, and
K = 500 rad/s. In this instance, the bandwidth of the loop has been reduced to 50 rad/s, from 500 rad/s with no
filter. The inclusion of an additional pole in the filter at 200 rad/s (τ3 = 0.005 s) helps to filter out the spurious
output frequencies of the detector without much change to the in-band response of the PLL, as shown in Fig. 3.
There is a slight increase in the bandwidth due to the proximity of the pole to the 50-rad/s bandwidth, but with
improved rejection. The values of the other filter parameters may be adjusted slightly to bring the bandwidth
back to the desired value.
This Bode-plot viewpoint has been provided to emphasize the design information that is directly available
from the Bode plot for many PLL situations. The Bode plot often provides a faster approach to the design needs
while still maintaining reasonable accuracy. Evaluating the phase margin (phase of G relative to −180◦ when
|G| = 1) is an alternate method for estimating the stability of the loop. With the extra pole, the margin in this
example becomes 65.8◦ rather than 80◦ . The advantage to this approach is a quick look at a design based on
the physical system rather than the scaled control system variables. In addition, once the Bode-plot approach
is adopted, the extension to higher-order systems is straightforward, not requiring information for Nyquist or
root-locus plots. The latter are useful tools, but do not substantially speed the design of a well-designed PLL.
The criteria for the Bode design is that the slope of G about the bandwidth should be approximately
20 dB/decade, similar to a simple integrator. A phase margin of 90◦ is desirable to minimize peaking in the
passband response. A 65.6◦ phase margin corresponds to a damping factor of 1/ , often
found to give the fastest settling of transient responses with no ringing. A damping factor of 1/2 creates a phase
margin of 52◦ with a peaking at the band edge of about 1.2 dB above the nominal passband response. This
slight peaking in the response is often a reasonable compromise for faster transient response times, though
with some damped ringing. Additional filtering may be added above the bandwidth to reject spurious detector
6 PHASE-LOCKED LOOPS, APPLICATIONS

Fig. 3. Bode plot of the second-order filter with an additional rejection pole. The performance within the passband is
equivalent to the filter of Fig. 2, but with additional rejection for higher frequencies.

output. Such filtering may even include notch filters. With the additional filtering design guidelines placed
above the loop bandwidth, the transient response of the system approaches that of a simple low-pass filter with
a bandwidth set from the Bode analysis. If a designer hedges on the phase margin by bringing these higher-
frequency filter poles closer to the passband, the PLL response peaks at the bandwidth limit as suggested.
Such a slight peak was seen in the response of Fig. 3 and is considered acceptable for many applications if kept
below 1 dB. A large collection of typical transient response plots is provided by Blanchard (1).

Components

Phase Detector. The critical component of a PLL is the phase detector. In control theory, it becomes
simply a difference block as previously suggested. However, the difference in phase between the two incoming
signals or frequencies is typically obtained by multiplying the two signals together and filtering the resulting
frequency-difference product. A multiplier is an ideal mixer that produces a phase detector whose output
voltage is proportional to the sine of the phase difference θe . The multiplier-type phase detector is one of four
basic forms. The basic detector forms give error output voltages as

which are depicted graphically in Fig. 4. The arrows in Fig. 4(d) emphasize that the transitions at the voltage
extremes are directed back to the zero value as a one-way transition, not to the opposite extreme as with
 PHASE-LOCKED LOOPS, APPLICATIONS 7

Fig. 4. Phase detector characteristics: (a) sinusoidal, (b) triangular, (c) ramp, and (d) extended ramp. The arrows of (d)
are to emphasize the one-way transition to the zero output state rather than the opposite extreme of the output.

the two-way transition of the ramp detector. The one-way transition of the extended ramp is critical to the
development of a dc offset level to aid in acquisition when the loop is out of lock.
How are these results obtained? They are obtained through basic mixing processes creating a product of
the two signals in question. Consider the input frequencies to be given by

where φ has been used to represent the phase difference from a reference oscillator at frequency ωf . This
frequency ωf is often called the free-running frequency and is indeed just that for several of the detectors. For
the other detectors, which use integrating filters, it is typically chosen as the center of the frequency range.
8 PHASE-LOCKED LOOPS, APPLICATIONS

The corresponding input signals are

If we use an ideal multiplier followed by a low-pass filter, we obtain

Using a low-pass rejection filter for the second harmonic, we take the output as

To obtain the sinusoidal form we have to include a π/2 phase shift, θoffset . Thus if we define θs = φs and
θo = φo − π/2, we have the sinusoidal error form. An important aspect of the sinusoidal detector is the need for
amplitude control of the input signals to avoid gain variations due to the signal amplitude changes. The needed
product may be obtained using a variety of mixer configurations. See Egan (2) for an analysis of the various
types of mixers used as phase detectors.
The simplest way of considering the triangular detector is to replace the cosine inputs of the sinusoidal
detector with pure square waves. Then the phase-detector response is simply the convolution of two square
waves, providing the triangular response after filtering. Due to the multiplication process, the same π/2 phase
shift is required as used for the sinusoidal detector. A simple square-wave phase detector is a logic AND, OR, or
exclusive-OR gate. If we filter the output of the gate, we obtain the logical product with a dc voltage offset, the
latter describing the linear variation of the two waves from in phase to totally out of phase. For the AND gate,
the dc offset is 14 the maximum output voltage, the variation between between 0 and one-half the maximum
output voltage. The OR gate simply raises the average voltage of the AND gate to three-fourths the maximum
output voltage of the gate. Relative to the center of this voltage variation, we have triangular-wave performance
of the offset voltage with respect to the phase difference of the two signals.
A ramp detector has a phase offset of 180◦ (π rad). This form of detector is obtained by using the two input
signals to set and reset an edge-triggered RS flip-flop, followed by appropriate low-pass filtering.
The extended ramp requires no phase offset and obtains its output from a tristate logic circuit that has a
cycle memory to extend the range beyond a single cycle. This detector is one of the most commonly used phase
detectors in integrated systems. The extended ramp is simply a transient-logic combination of ramp-type
detectors and is commonly called a phase–frequency detector. A fundamental problem that has been overcome
in recent years is its zero-phase residual error. The transition through the zero-phase crossing involves several
state changes, which may cause random behavior. The frequency-detection properties of the detector occur
when the PLL is not in lock, creating a high or low triangular waveform with one-way transitions shown by
the arrows of Fig. 4(d). This high–low feature causes an additional dc offset that aids in frequency acquisition.
The detector is generally followed by an integrating low-pass filter in order to reach a zero steady-state error
with no frequency or phase error. Further information on these detectors are given by Egan (2), Best (3), and
Rohde (4).
 PHASE-LOCKED LOOPS, APPLICATIONS 9

Fig. 5. Filter for spurious-output rejection. This simple low-pass filter is the minimum filtering that should be used with
a PLL to rejected unwanted frequency products produced in the phase-detection process.

A final phase detector that should be noted is the sample-and-hold. The classic sample-and-hold extracts a
sample of an oscillator signal and holds it until the next sample, at which time the hold is simply updated. This
technique operates much like a sinusoidal detector for a sinusoidal input signal, having the digital equivalent
of a D flip-flop phase detector. The sample-and-hold can offer a major advantage in feedthrough reduction for
the pulsed phase–frequency detector. To take advantage of such a use in a synthesizer, the sample is held
off one or more clock cycles of the VCO frequency. Thus, the sample is taken after the integrated output of
the phase–frequency detector has settled. In so doing, the feedthrough signal is reduced to a correction step
rather than a short pulse, substantially reducing the sideband generation in the system. The sample-and-hold
detector is not restricted to following another detector, but may be used directly as the phase detector. It is
sometimes advantageous in a synthesizer application to cascade two sample-and-hold phase detectors to obtain
even further sideband reduction. Further filtering should still be used, but with reduced rejection requirements
on the filter.
A second significant use of the sample-and-hold detector is in microwave frequency synthesis and stabi-
lization. For this application, the sample is taken on every N th cycle of an input sinusoidal waveform from the
VCO. The result is to effectively treat the input signal as though it were N times smaller, acting as a synthesizer
with a frequency that is N times the reference frequency. For many applications, the primary purpose of this
multiplying loop is to stabilize a microwave oscillator that may otherwise drift in frequency with temperature
and power.
Filters. The filters of the phase-locked loop provide two vital functions. First, the PLL filter provides the
necessary feedback frequency response to control the gain and bandwidth of the system. An additional low-pass
characteristic that should always be included provides the needed spurious rejection of mixing products that
result from the phase-detector operation. In frequency synthesis applications, the feedthrough of the spurious
frequencies of the phase detector is the major cause of sideband modulation components in the oscillator output.
These sidebands are usually severely restricted by governmental regulation to prevent interference with other
spectrum users. Thus the regulatory issue is a major concern that must be added to the problem, where the
spurious products usually have little effect on the PLL performance other than the sideband generation. On
reception, interference rejection of adjacent-channel signals, produced by the conversion with the spurious
sidebands generated in the VCO, is also a potential problem.
It is a good rule to make the filter only as sophisticated as needed for the particular application. If no
bandwidth control is needed, then a simple low-pass filter for eliminating the spurious frequencies may be all
that is used. In such a case, the filter bandwidth will be above the PLL bandwidth and may be obtained with
a simple RC low-pass filter. In such a case, the PLL operates in a first-order mode within the bandwidth of
operation.
The filters used in the PLL define the system type and order. The order refers to the degree of the system
polynomial in the denominator of the transfer function, while the type refers to the number of integrators in
the loop. By default, a PLL is at least a type-I loop. An ideal first-order loop would have no filter. In reality,
we use a filter (Fig. 5) to eliminate the spurious outputs of the phase detectors. However, as long as the filter
bandwidth is much greater that the loop bandwidth (which is K for this case), the linear system analysis of the
loop is closely approximated by a first-order loop with no filter.
10 PHASE-LOCKED LOOPS, APPLICATIONS

Fig. 6. Lag–lead passive filter with spurious-frequency rejection. The lead produced by R2 returns the filter response to
a constant for transition through the bandwidth limit, reducing the potential instability due to a small phase margin. The
capacitor C3 is added to provide high-frequency rejection of the undesired phase-detection products.

The lag–lead filter is easily implemented in discrete form with the addition of a single resistor as shown
in Fig. 6. The extra capacitor, C3 , provides the spurious-sideband rejection and is not directly a part of the
lag–lead circuit. This filter is described by

where the approximation occurs when the extra capacitor is ignored. A second lag–lead filter may be cascaded
with this filter to obtain an approximation to a double-pole, double-zero filter for use in a third-order system.
Third-order systems find use in tracking of low-earth-orbit satellites, which have an acceleration profile that
causes a continuously changing frequency. The third-order system is necessary to minimize the steady-state
phase error in the received signal and is typically implemented as a type-II loop.
Active filter systems are useful for implementing many filter functions. A major advantage of active filters
is their ability to make the denominator of the filter function a simple s and thus yield an integrator. Such a
configuration is shown in Fig. 7, giving

The new difficulty added by active filters is a phase inversion in the path that must be correctly taken
into account in the feedback analysis. An additional filter is simply cascaded if needed.
One must take care that the high-frequency response of the operational amplifier used does not allow
undesired pulse streams through the device. It is often wise to add passive rejection filters within the active-
filter design to guard against such problems. In practice, the frequency response of the operational amplifier
limits the ability to reject the transmission of the higher-frequency spurious signals, for which C3 is added. To
aid in the rejection and reduce the potential for overdrive of the operational amplifier, C3 may be relocated as
part of an input T network as shown in Fig. 8, giving

Additional factors that must often be adjusted in practical systems are offset voltages within the filters
and other components.
 PHASE-LOCKED LOOPS, APPLICATIONS 11

Fig. 7. Integrating operational-amplifier filter with spurious-signal rejection, providing the desired zero to control the
phase margin while still providing high-frequency rejection with C3 .

Fig. 8. Modified filter for improved spurious-signal rejection. This filter is a modified version of Fig. 7, designed to reduce
possible high-frequency feedthrough in the filter due to inadequate operational-amplifier performance and to also avoid
overdrive of the amplifier.

Oscillators. The type of oscillator depends strongly on the application at hand. For low-frequency
applications, the oscillator that forms the VCO in the loop is often a simple multivibrator, typically constructed
with a balanced pair of devices and current-controlled in frequency. As frequencies are increased into the radio
and microwave realms, the oscillators are generally tuned circuits (resonant LC combination, cavity, or YIG
structure) with varactor frequency adjustment. The circuits are often balanced to reduce harmonic content, and
varactors are often used in pairs to reduce noise effects. Care must be used in providing the bias to varactors.
These units are part of a tuned circuit that effectively forms a low-pass filter with the bias resistor to the
control signal, producing an unwanted lag filter in the loop. In addition, the resistor must be sufficiently large
not to reduce the Q (or bandwidth) of the tuned circuit and yet not so large as to become a substantial noise
source in the loop. Noise is a critical item of concern in the design of synthesizer systems.
The tuning of the VCO is often nonlinear, even with some multivibrators. It is sometimes desirable
to linearize the voltage-to-frequency response, improving the linear system performance of the loop. Such
linearization is generally done with a diode switching network for selective loading that creates a piecewise
compensation of the VCO transfer function to obtain an effective linearization of the transfer. One drawback
to such piecewise loading systems is the inherent noise that may be created in the process.
In power and related applications, the oscillator may not always be obvious. The effective oscillator may
be a variable-speed motor that must be controlled or be a fully mechanical system such as the combustion
engine of an automobile with a speed sensor on the shaft. The specific design of oscillators is not the goal of
12 PHASE-LOCKED LOOPS, APPLICATIONS

this section, but rather a brief consideration of the types of units that might compose an oscillator in a PLL
system. For the purposes of analysis, the oscillator, frequency divider, and offset oscillator to be considered in
the applications may be considered as a single oscillator. Keep your mind open, and you may be surprised at
the systems that might be considered as oscillators in a PLL.

Acquisition

Analytic Approach. The first step in the operation of a PLL is the acquisition phase. In the previous
sections we considered the PLL as a linear system, always in lock. We begin the consideration of achieving
this locked state by assuming the VCO is running at a free-running frequency and the input is offset from the
free-running frequency by an amount 0 . The analysis that follows provides a basic viewpoint of acquisition
for the generic loop with a sinusoidal phase detector. If the detector is a triangular or ramp type, the same
basic mechanism occurs with a slight increase in the effective detector gain for the beat-frequency component
of the system. The analysis for the phase-frequency detector is a bit simpler due to the built-in offset voltage
when the frequencies are different. Other considerations must also be taken if the filter is an integrator that
is likely sitting on a power-supply rail when out of lock.
This analytical derivation is approximate, but gives surprisingly useful guidelines to the acquisition
process of phase-locked loops with lag–lead filters. We assume that only a sinusoidal term plus a slowly
varying offset need be considered at the control terminal of the VCO. With this in mind, we will look at the
operation of the loop for frequency differences in the various frequency ranges of the loop filter in order to
obtain limits on acquisition as well as an estimate of the time for acquisition.
For the nonintegrating lag–lead filter used with nearly all but the phase–frequency detector, the output of
the detector will be dominated by a beat frequency between the two detector inputs and a small low-frequency
(approximately dc) part that provides the locking mechanism. For such an output, we may write the control
voltage of the loop as approximately

From this voltage we may write the output of a sinusoidal detector as

 PHASE-LOCKED LOOPS, APPLICATIONS 13

The quantity θ is an unknown phase offset of the VCO. We have chosen to use simple Taylor expansions
of the trigonometric functions rather than taking the additional step of using Bessel functions before taking a
Taylor series.
For the analysis we will assume the first term of Eq. (20) is above the filter breakpoints and is simply
reduced in amplitude by the high-frequency response of τ2 /τ1 of the filter. The second term is considered slowly
varying and is the term we shall consider for the filter interaction. Thus we have

where the ⊗ denotes convolution in time. Assuming the second term is a low-frequency term as previously
mentioned, we can determine coefficients by comparison with the original vc to give

Thus we may write a summary equation as

Rather than work with the full f (t), we may consider each frequency range of the filter separately. The
purpose of checking each region to search for a possible solution and or limit on the operation. First, consider
f (t) ≈ τ2 / τ1 (the high-frequency response). Equation (23) becomes

with solution

There are two cases of interest. First, if o ≥ K τ2 /τ1 , the solution provides
for a constant difference frequency as well as a low-frequency term at zero frequency, not above 1/τ2 , which

is an invalid solution. If o ≤ K τ2 /τ1 , the solution is nonphysical and we have

14 PHASE-LOCKED LOOPS, APPLICATIONS

chosen the wrong region of the filter for the analysis. Thus this frequency range of operation is not possible
within the constraints of the model.
For the second low-frequency, unity-transmission region, we have

or

Again there are two cases of interest. First, if o ≥ , the solution is

a constant difference frequency along with a low-frequency term at zero frequency, an out-of-lock condition.
This limit becomes our basic limit of frequency pull-in, ωp , the range within which the PLL is able to lock
eventually. If o ≤ , the solution is nonphysical and we have again chosen
the wrong region of the filter for the analysis.
The third midrange frequency region gives an integration of the detector output that is needed for
acquisition as

with a solution given by

In this analysis we have used the smallness restriction that

At the limit of this restriction, the PLL has reached the system bandwidth and ceases the pull-in process
of acquiring lock we have just identified, locking in without further cycle slippage. This latter process is the
basic transient response of the system and is referred to as lock-in; it occurs over a range ωL . The time it
takes for this process to move the VCO from the starting offset frequency to the loop bandwidth comes from
Eq. (29) as
 PHASE-LOCKED LOOPS, APPLICATIONS 15

The pull-in transient occurs in about τ2 seconds, giving a total acquisition time of

Thus τ2 has a major role in setting the acquisition time of a loop. For the largest frequency of pull-in,
called the pull-in range, we have

If the frequency difference of the loop is within this range, the loop will eventually pull in to the locked
condition. After the pull-in process error reaches the loop bandwidth, the transient effects of a well-designed
loop will take over and complete the locking process with no further cycle slippage. The smaller range over
which this occurs is the lock-in range; it is approximately equal to the loop bandwidth and given by

The integrating filter does not have a low-frequency, unity-gain region. Thus the pull-in range for the
integrating filter is not limited by the detector, but rather by the filter, amplifier, or VCO. Unfortunately, an
integrator also tends to send an unlocked PLL to a supply limit of one of the components rather than to the
free-running frequency for an initial value, so that it requires an acquisition-process initialization. With active
filters, the initialization may simply be a Schmidt trigger arrangement that reverses the bias voltage on the
reference terminal to begin integration back across the active region of the device. As long as the desired
frequency is within the tuning range, this integration process should pick up the locking process. In the case
of the phase–frequency detector, the detector has a built-in bias that is added to the loop-filter input if the
frequencies of the inputs differ. This bias results from the phase–frequency detector being reset to the center
of the phase range rather than the opposite phase limit when the range is exceeded [refer to Fig. 4(d)].
Phase-Plane Approach. In the phase-plane approach, it is desired to relate the time derivative of
the phase error to the instantaneous phase error. In relating these two properties, a plot may be made of the
phase error versus time. In a numerical sense, you would simply start with the current phase error, determine
the time derivative, and estimate the new phase error at the next time step. In stepping through the process,
acquisition will occur if the process converges to smaller phase errors as time progresses and the phase error
cycles through multiple cycles. These plots are interesting, and the reader is referred to Blanchard (1) for
further information.

Noise Fundamentals

Noise can be a problem in PLL systems, though it can be alleviated by the proper use of PLLs. Slightly
different problems are encountered for low and for high signal-to-noise ratios. For the small-signal case, many
of the small-signal approximations relating amplitude and phase may be used. For the large-signal case, the
nonlinearities of the system must often be considered, particularly with respect to the the potential for loss
16 PHASE-LOCKED LOOPS, APPLICATIONS

Fig. 9. Simple noise model of a PLL, with a generic noise being added at a single point just after the detector. This location
is most suited to the analysis of the noise in a PLL used as a receiving system, yet represents the fundamental concepts of
general noise analysis.

of lock and cycle slipping. This overview of noise will provide a basic knowledge of the noise effects in PLL
systems, and further comments will be made in other sections.
A Simple Noise Model. The basic model typically adds a noise source in summation with the output
of the phase detector as shown in Fig. 9. Both Gardner (5) and Blanchard (1) discuss the case of additive
Gaussian noise at the model input. Rohde (4) adds substantial information on noise sources within the PLL
itself. Manassewitsch (6) concentrates on the determination of noise bandwidth. Approaches to high-level noise
are built around nonlinear system descriptions, often incorporating Monto Carlo techniques for analysis of the
noise statistics and determination of the potential for loss of lock. We refer the reader to the classic papers by
La Frieda and Lindsey (7) and by Viterbi (8) for details on high-level noise problems.
The level of noise in the model is determined by the translation of the input statistics due to the additive
noise conversion in the detector process and by the noise figures of the remaining components in the loop,
referenced to the detector output. We may typically treat the noise as a broadband noise voltage and simply
evaluate the transfer of this noise to the appropriate point of the loop. This explanation is slightly oversimplified,
but contains all of the basic analysis needs of the problem. If we consider the output point of interest to be the
θo at the output of the VCO, the appropriate transfer function is simply H(s)/K d . Thus the noise properties are
determined by the amplitude of the noise-source power density times the noise bandwidth. The latter is not
necessarily the 3 dB bandwidth; is often found to be 1.5 times larger than the 3 dB bandwidth, and is obtained
through integration of the transfer function.
A major source of noise is semiconductor junctions, which create partition and shot noise. Any resistive
component in the loop is a source of wideband thermal noise proportional to kTB (k being Boltzmann’s constant,
1.38 × 10 − 23 J/K; T being the absolute temperature, often taken as 290 K; and B being the bandwidth in hertz).
Such thermal noise was mentioned in connection with the choice of the isolation resistor used with varactors.
The spurious output of the detector may also be treated as noise, though by no means Gaussian. Other
low-frequency noise results from active device flicker (a low-frequency noise particularly important in the
phase detector, filter, and amplifier) and poorly chosen feedback levels in the VCO. Stability and microphonics
(frequency variations due to mechanical vibrations of the VCO components) are also critical aspects of the
VCO. People often forget that a VCO is mounted in a hostile environment where it may be subject to severe
vibration, particularly in the 1000 Hz range for automobiles and aircraft. Such periodic noise can cause havoc
through unwanted modulation on the VCO and is not corrected by the PLL for higher frequencies.
 PHASE-LOCKED LOOPS, APPLICATIONS 17

Fig. 10. PLL with a frequency divider in the feedback loop, forming a basic, divider-type frequency synthesizer.

All of these sources, as suggested, may typically be lumped together as a single source at the output of
the detector and the noise analysis done by simply considering each of them as independent and feeding the
system transfer function. Improvement in noise performance involves improving the noise filtering properties
of the transfer function or reducing the noise contribution of individual components to the system. Though
simple in concept, this noise reduction process is often tedious and is considered by many to be an art.
Though this noise discussion has been brief, it should point to the potential sources of noise and the
fundamental analysis process for determining their contributions to the system noise. It is also wise to remind
the reader that the uncorrelated noise power adds, not the noise voltage. Pure random noise has zero correlation
with other noise sources. A few comments are offered on noise throughout the applications, but to only suggest
the correct path to consider in design.

Applications of Phase-Locked Loops

The PLL has wide application. The majority of its applications fall into four main categories:

• Frequency synthesis
• Frequency (FM) and phase (PM) modulation and demodulation
• Data and carrier recovery
• Tracking filters

Frequency Synthesis. Frequency synthesis is one of the most widely used applications for PLLs. The
local oscillators in most cell phones, land mobile radios, television sets, and broadcast radios are built around
PLLs. Frequency-synthesizer integrated circuits are available from a number of manufacturers (3). The basic
topology of the PLL frequency synthesizer is shown in Fig. 10.
The phase difference between a reference signal, ωref , and a divided sample of the output frequency, ω o ,
is measured at the phase detector. In a synthesizer, the signal frequency previously used is replaced by a
frequency standard referred to as the reference signal. When phase lock is achieved, the output frequency from
the divider must be equal to

where N is the divider ratio and ωref is the reference frequency. The basic frequency synthesizer acts as a
frequency multiplier. Since the phase comparison is done at the reference frequency, the effective VCO gain is
18 PHASE-LOCKED LOOPS, APPLICATIONS

given by

A synthesizer loop can be analyzed as a conventional loop where the VCO gain above is substituted into
the calculations.
The value of N is often made programmable. N is an integer; so changing it has the effect of increasing or
decreasing the output frequency, ω o , in steps that are a multiple of ωref . It is also important to recognize that
changing the value of N has the effect of changing the loop dynamics. Since the VCO gain K o is a function of N
in a synthesizer, changing N will change the critical parameters ωn and ζ in second-order loops and the phase
margin in third and higher-order loops.
The value of N influences the loop transfer function H(s). Consider the situation where s = jωm and ωm is
a modulating frequency:

or

Any phase or frequency deviation on the reference is multiplied N times for the output by the synthesizer.
Figure 10 shows a simple synthesizer with a divider in the loop. It is also possible to put a mixer in the
loop. This configuration is called an offset loop, and it is shown in Fig. 11. In order for the loop to be locked, the
following must be true:

or

The offset oscillator can operate either above or below the output oscillator frequency, and the filter can
select either the sum or the difference of the two oscillator frequencies. In the case of the offset loop, the loop
gain is unaffected by the frequency translation, expect for a possible phase inversion. The divider in Fig. 11
can be bypassed. In such a case N is set to one.
In most synthesizers, the reference frequency ωref must be significantly higher than the loop bandwidth.
The reason for this requirement is that the output of most phase detectors is not a pure dc signal. The signal
is pulses whose duty cycle and/or polarity are proportional to the phase difference. The loop filter not only sets
loop dynamics, but it must reject the ac component of the phase-detector output, passing only the dc value to the
VCO. The attenuation of the loop filter is finite, so some of the ac component does make its way to the VCO. The
 PHASE-LOCKED LOOPS, APPLICATIONS 19

Fig. 11. Offset-loop frequency synthesizer. The offset oscillator is often used to lower the frequency requirements on the
divider.

result is undesired phase modulation sidebands at the reference frequency on the output signal. Narrow-band
loop filters provide better suppression of this reference feedthrough, but narrow-band filters exact a cost. Notch
filters are also used to filter out the reference frequency components.
Consider this example: The channel spacing in the FM broadcast band is 200 kHz. A synthesizer with a
reference frequency of 200 kHz will produce steps at the channel spacing. A second-order type-II synthesizer
loop, ζ= 1, ωn = 2π (200 Hz), will settle in approximately 10 ms to within 100 Hz of its target frequency after a
200 kHz step. A similar loop with a reference frequency of 200 Hz will produce 200 Hz steps but, everything
else being the same, will require that ωn = 2π (0.2 Hz) to produce the same level of reference suppression. This
loop will take almost 8 s to settle to the same accuracy after being commanded to change frequency by 200
kHz.
Most cell-phone, television, and broadcast radio receivers employ simple offset or divider-type synthesiz-
ers. For these applications, the required step size is usually much greater then the loop bandwidth required
for the desired dynamics. In order to produce small steps and at the same time obtain acceptable reference
suppression and settling time, it is often necessary to resort to multiloop synthesizers.
An example of a multiloop synthesizer is shown in Fig. 12. It was designed for an upconverting HF (0 to
30 MHz) in a communications receiver with a 75 MHz IF (4). This synthesizer will produce 10 Hz steps, but it is
much more complex than a simple offset or divider-type synthesizer. Loop 1 in Fig. 12 is a simple divider-type
synthesizer. It tunes from 50 MHz to 60 MHz in 1 kHz steps. The output of this loop is divided by 100, and
the resulting 0.5 MHz to 0.6 MHz output changes by 10 Hz each time the divider in loop 1 is incremented or
decremented by 1. Loop 2 is also a divider synthesizer, but it tunes from 75.5 MHz to 106.5 MHz in 100 kHz
steps. Loop 3 is an offset loop without a divider. This loop forces the difference between the loop-3 VCO and
the loop-2 VCO to be equal to the divided output of loop 1. Loop 1 can tune loop 3 over a 100 kHz range in
10 Hz steps, while loop 2 tunes loop 3 from 75 MHz to 105 MHz in 100 kHz steps. By proper choice of divider
programming, it is possible to continuously tune the loop-3 VCO from 75 MHz to 105.1 MHz in 10 Hz steps.
The multiloop synthesizer in Fig. 12 employs a combination of divider and offset loops. Another technique,
called fractional N, permits a synthesizer to produce steps smaller than the reference frequency. Details on
fractional-N synthesizers can be found in Refs. 9 and 10. A particularly simple implementation of a fractional-N
synthesizer can be found in Ref. 11.
The design of frequency synthesizers is often a careful balancing act that requires minimizing the lock
time, the reference feedthrough, and the spurious outputs generated by mixing and dividing, while at the same
20 PHASE-LOCKED LOOPS, APPLICATIONS

Fig. 12. This triple-loop frequency synthesizer of Rohde can tune from 75 MHz to 105.1 MHz in 10 Hz steps (4). Loop 1
is used to obtain a stable 10 Hz step interval for use in locking loop 3 to 10 Hz steps.

Fig. 13. PLL configured as a frequency or phase demodulator. The outputs at u1 and u2 offer tracking alternatives for
demodulation, allowing output for frequencies both above and below the loop bandwidth.

time meeting power, size, frequency, and step-size requirements. The literature contains additional information
on these design tradeoffs (4,9,10,12).
Modulation/Demodulation. A PLL can be used for phase or frequency modulation and demodulation.
Before presenting the analysis, it maybe valuable to obtain an intuitive understanding of the modulation–
demodulation process.
Figure 13 contains the block diagram of a PLL configured as a demodulator. If the modulating frequency
ωm is inside the loop bandwidth, the loop follows the phase and frequency of the incoming signal with little
error. The phase (and thus the instantaneous frequency) of the VCO follows that of the input signal. The VCO
control voltage u2 must be an exact replica of the modulating voltage for this to be true. It is generally assumed
that there is a linear relation between the control voltage and the VCO frequency. If the relation is nonlinear,
the VCO will still track the input frequency, but the control voltage will be a distorted replica of the modulation
voltage.
 PHASE-LOCKED LOOPS, APPLICATIONS 21

Fig. 14. PLL configured as a frequency/phase modulator. As in Fig. 13, this configurations offers alternative modulation
inputs for modulation frequencies both above and below the loop bandwidth.

When the modulation frequency is outside the loop bandwidth, the VCO phase will no longer track the
instantaneous input signal phase. The loop can only track the average frequency of the incoming signal. This
causes the average VCO phase to remain constant. The instantaneous output voltage of the phase detector will
be a function of the difference between the applied phase modulation and the average VCO phase. Thus, the
phase-detector output voltage will be a replica of the source modulating voltage.
The output voltage for a FM demodulator is given by

Here ωs (ωm ) is the frequency deviation of the input signal and ωm is the modulating frequency. Recall
that H(jωm ) ≈ 1 for ωm less than the loop bandwidth. For the phase demodulator, the output voltage can be
obtained at u1 as

where φs (ωm ) is the phase deviation of the input signal. Note that

The situation is reversed for the PLL modulator shown in Fig. 14. Here a modulating voltage is added to
the loop. In the case of frequency modulation, the VCO control voltage is the sum of the voltage from the loop
filter, F(s), and the modulating voltage, u2 . If the modulating frequency is less than the loop bandwidth, the
loop will interpret any change of frequency due to u2 as an error and produce an equal and opposite correction
voltage at the loop filter output. The result is no change in the output frequency. If, however, the modulating
frequency is greater then the loop bandwidth, the loop can only follow the average frequency. The instantaneous
frequency will be controlled by u2 , and frequency modulation will result.
Phase modulation can be generated by introducing the modulation voltage at u1 . When the modulating
frequency is less than the loop bandwidth, the modulating voltage will cause a phase change at the VCO, which
the loop will track. The VCO phase must be adjusted to produce a phase difference at the phase detector that
cancels u1 . The VCO phase is now forced to track u1 ; thus the VCO output is phase-modulated. Beyond the
loop bandwidth, the loop can no longer track the error introduced by u1 and no modulation will occur.
22 PHASE-LOCKED LOOPS, APPLICATIONS

Fig. 15. Generic phase-locked loop with options. The options include frequency offset, frequency division, and modulation
and demodulation terminals.

The output deviation of the FM modulator is given by

Here ωo (ωm ) is the frequency deviation of the input signal and f m is the modulating frequency. We have

For the phase modulator, the output phase deviation can be obtained by

where φo (ωm ) is the phase deviation of the output signal and H(jωm ) ≈ 1 for ωm less than the loop bandwidth.
For FM the loop acts as a high-pass filter, and for PM the loop acts as a low-pass filter. Loop-bandwidth
considerations driven by loop dynamics and reference suppression may prevent FM at low modulating frequen-
cies or PM at high modulating frequencies. It is possible to overcome some of this limitation by applying the
modulating voltage at both u1 and u2 . Low-frequency FM can be generated by applying the modulating signal
to u2 in the conventional manner and applying an integrated version of the modulating voltage to u1 . Details
of this process can be found in Ref. 2.
It is also possible to obtain low-frequency FM by modulating the reference. For frequencies less than the
loop bandwidth the instantaneous phase and frequency are transferred to the output. This technique is used
 PHASE-LOCKED LOOPS, APPLICATIONS 23

Fig. 16. The Costas loop for BPSK demodulation specifically locks to the carrier so that the modulation data may be
recovered. In this role, it is a carrier recovery loop.

in land mobile and cellular phone transmitters in conjunction with divider-type synthesizers. The synthesizer
acts as a multiplier, and a small amount of modulation applied to the reference is multiplied at the output.
All real oscillators are phase-modulated with noise. This noise modulation results from the finite-Q
resonators in the oscillators and the inherent noise of the active devices used in oscillators. While a full noise
analysis is beyond the scope of this article, combining the multiplier effect with the loop modulation response
gives insight into the noise performance of synthesizers. A more complete analysis can be found in the literature
(6,10,13).
Phase noise in oscillators is often described by a single-sided power spectral density Lφ . Below the loop
bandwidth, the loop follows a multiplied replica of the noise on the reference signal. The phase noise on the
VCO is suppressed, as the VCO phase is forced to follow the reference phase. Beyond the loop bandwidth, the
VCO phase no longer follows the reference phase, the error between the VCO and the reference increases, and
the noise output becomes the noise of the VCO. This effect can be expressed by

A careful choice of loop bandwidth can minimize the total noise output. An example of this can be seen
in many microwave synthesizers. Well-designed microwave oscillators such as YIG oscillators have very low
phase noise at large offsets ωm from the center frequency, but close to the center frequency their phase noise
24 PHASE-LOCKED LOOPS, APPLICATIONS

Fig. 17. Early–late data synchronizer that offers the ability to synchronize with a data stream in order to have reliable
recovery of the data stream in a sampled detection system.

is relatively high. Crystal oscillators multiplied into the microwave region, on the other hand, have very low
noise close to the center frequency, but the multiplication process tends to bring up the noise far removed from
the center frequency. The loop bandwidth can be chosen so the crystal-oscillator noise dominates close to the
center and the microwave oscillator noise dominates at large offsets from the center frequency. Such a loop is
referred to as a cleanup loop.
Data and Carrier Phase Recovery. Synchronization is probably one of the oldest applications for the
PLL. The timing and phase synchronization of 60 Hz power generating plants can be analyzed as a kind of
PLL. Television, and particularly color TV, would not be possible without PLLs to extract timing and phase
information from the TV signal. The growth of digital systems that employ various types of phase and phase-
difference modulation has brought renewed interest in PLLs to extract phase and timing information from a
data stream.
An example of a carrier phase recovery loop is the Costas loop. A Costas loop is shown in Fig. 16. The
Costas loop can coherently demodulate binary phase-shift keying (BPSK) signals. With a BPSK signal, a phase
shift of − π/2 or π/2 rad represents a data 0 or 1.
The input to the loop is 2 cos(ωc + φi ± π/2) = ± 2 sin(ωc + φi ), where ωc is the carrier frequency and
φi is the carrier phase. The ± π/2 represents the data modulation. The input is equally split and multiplied
by the quadrature of a locally generated carrier, cos (ωc t + φo ), in multipliers A and B. The low-pass filters
extract the difference signals from the product. The result is a quadrature of the phase difference between the
locally generated carrier and the incoming signal, ± cos(φi − φo ) and ± sin (φi − φo ). These quadrature outputs
are multiplied together in multiplier C. The result is a doubling of the quadrature component arguments as
0.5 sin [2 (φi − φo )]. The modulation disappears, and the resulting phase difference between the input and the
output is used to steer the VCO. While this example is for simple BPSK, it is possible to design similar loops
for N-phase modulation (5).
Another data synchronizer is the early–late gate (5). The circuit works well for rectangular pulses. Figure
17 contains a block diagram of an early–late gate synchronizer. Figure 18 shows the timing.
Integration from + T bit /4 to the data transition is controlled by the late timing. This integration will
produce an equal and opposite value for the integration controlled by the early timing from − T bit /4 to the data
transition only if the data transition occurs halfway between + T bit /4 and − T bit /4. The VCO is steered to this
point by the difference of the absolute values of the integration products.
 PHASE-LOCKED LOOPS, APPLICATIONS 25

Fig. 18. Early–late data synchronizer timing, showing the balance of the early and late pulses used to center the data
stream.

Fig. 19. Bandpass and low-pass representation of a PLL, emphasizing the relationship between the transmitted signal
and the baseband representation of the signal used for detection.

Tracking Filters. Tracking filters are another early application for the PLL. The early space program
used PLL receivers to track weak satellite signals that were accompanied by changing Doppler shift.
The loop transfer function, H(jωm ), is almost always represented by its baseband representation, but
phase measurement is actually accomplished at some carrier frequency. The loop appears as a bandpass filter
centered at ωc with bandwidth twice that of H(jωm ). See Fig. 19. The unique property of this filter is that it can
track ωc as it changes. A signal with large frequency excursions can be passed through a filter that would be
otherwise too narrow to accommodate the frequency changes by using PLL tracking-filter technology.
Since it is desired to follow Doppler-shifted signals or signals that change frequency, loop dynamics
are an important consideration. The loop dynamics are related to the loop order and loop type. Loop type is
determined by the number of poles at zero in the open-loop transfer function. Table 1 shows the dynamic
behavior of various loops. The table shows the loop phase error after the loop reaches steady state following
a phase step, a frequency step, or a frequency ramp. The frequency ramp can be used to describe the loop’s
performance in tracking a satellite signal as the satellite passed from horizon to horizon.
26 PHASE-LOCKED LOOPS, APPLICATIONS

Conclusions

This article has provided the fundamentals of PLL analysis and several examples to illustrate typical appli-
cations. There are many extensions that may be made to a PLL for a particular application. The emphasis of
this article has been to highlight the process of the analysis and operation so that such extensions are easily
handled. The examples of frequency synthesis, frequency and phase modulation and demodulation, data and
carrier recovery, and tracking filters have provided extensions to suggest the variety of configurations that may
be considered. In all cases, the extensions may be brought back to the form of the basic PLL for analysis, giving
the reader the fundamental tools needed to design effective phase-locked systems.

BIBLIOGRAPHY

1. A. Blanchard Phase-Locked Loops: Application to Coherent Receiver Design, New York: Wiley, 1976.
2. W. F. Egan Phase-Lock Basics, New York: Wiley, 1998.
3. R. E. Best Phase-Locked Loops: Theory, Design, and Applications, 3rd ed., New York: McGraw-Hill, 1997.
4. U. L. Rohde Digital PLL Frequency Synthesizers: Theory and Design, Englewood Cliffs, N J: Prentice-Hall, 1983.
5. F. M. Gardner Phaselock Techniques, 2nd ed., New York: Wiley, 1979.
6. V. Manassewitsch Frequency Synthesizers: Theory and Design, 3rd ed, New York: Wiley, 1987.
7. J. R. La Frieda W. C. Lindsey Transient analysis of phase-locked tracking systems in the presence of noise, IEEE
Trans. Inf. Theory, IT-19: 155–165, 1973; in Lindsey and Simon (eds.), Phase-Locked Loops & Their Application, New
York: IEEE Press, 1978.
8. A. J. Viterbi Phase-locked loop dynamics in the presence of noise by Fokker–Planck techniques, Proc. IEEE, 51,
1737–1753, 1963; in Lindsey and Simon, (eds.), Phase-Locked Loops & Their Application, New York: IEEE Press, 1978.
9. W. F. Egan Frequency Synthesis by Phase Lock, 2nd ed., New York: Wiley, 2000.
10. U. L. Rohde Wireless and Microwave Frequency Synthesizers, Englewood Cliffs, N J: Prentice-Hall, 1997.
11. S. D. Marshall Extending the flexibility of a RFIC transceiver through modifications to the external circuit, MS Thesis,
Virginia Tech, Blacksburg, VA, 1999; http://scholar.lib.vt.edu/theses/available/etd-052599-165152/
12. J. A. Crawford Frequency Synthesizer Design Handbook, Boston: Artech House, 1994.
13. W. P. Robins Phase Noise in Signal Sources, IEE Telecommunications Series 9, London: Peregrinus, 1982.

WILLIAM A. DAVIS
DENNIS G. SWEENEY
Virginia Tech
200 PHASE SHIFTERS

The attenuation of the microwave signal due to the presence

of the phase shifter can be calculated from its S parameters,
and it is expressed in decibels as

(Insertion loss)1 = 20 log |S21 | (3)

(Insertion loss)2 = 20 log |S12 | (4)

The subscripts 1 and 2, respectively, refer to the phase shifter

when the input signal is at port 1 or port 2. The mismatch is
expressed as standing wave ratio (VSWR) at each port and is
given by

1 + |S11 |
(VSWR)1 = (5)
1 − |S11 |
1 + |S22 |
(VSWR)2 = (6)
1 − |S22 |

In order to evaluate the performance of a phase shifter, it is

PHASE SHIFTERS
A microwave phase shifter is a two-port device capable of pro-
ducing a true delay of a microwave signal flowing through it.
The produced time delay can be fixed or adjustable, and the
phase shifter is accordingly called fixed phase shifter or tun-
able phase shifter. The geometry of the phase shifter is inti-
mately related to the guiding structure which is used to de-
sign it and is also related to the operational frequency. Most
phase shifters are realized in waveguides or in planar struc-
tures. Electrically, a phase shifter can be characterized by its
scattering parameters matrix. The scattering matrix for an
ideal phase shifter (see Fig. 1) takes the form
 PHASE SHIFTER CLASSIFICATION
0 e− jφ 1
S = − jφ (1)
e 2 0
The signal arriving at port 1 will appear at port 2 with a
phase shift ␾1 without being reflected at port 1 and with no
attenuation, while the signal arriving at port 2 will appear at
port 1 with phase shift ␾2 and without reflection or attenu-
ation.
In general, ␾1 ⬆ ␾2 and the phase shifter is called nonrecip-
rocal, and if ␾1 ⫽ ␾2 the phase shifter is called reciprocal. In
practice it is impossible to achieve perfect matching at the
two ports (no reflection) and to avoid some attenuation while
the signal flows through the phase shifter. For these reasons
the scattering matrix of a real phase shifter can be written in
general as

S11 |S21 |e− jφ 1
S= (2)
|S12 |e− jφ 2 S22
necessary to introduce a quality factor. For a phase shifter
operating at a specific frequency we can define a figure of
merit as the ratio between the maximum phase shift (in de-
grees) and the corresponding attenuation in dB at that fre-
quency. This parameter can be expressed as
(phase S21 )
figure of merit = (7)
|S21 |
The performance of a phase shifter can be measured using a
standard S parameter setup, including a network analyzer
and a test-set of calibration standards suitable for the specific
guiding structure (1).
A first classification of a phase shifter can be based on its
phase shifting capability, according to which it can be identi-
fied as fixed or adjustable. A fixed phase shifter will provide
a constant phase change between the two ports, while an ad-
justable phase shifter will provide a phase change between
the ports which can be controlled mechanically or electrically.
Further classification for the adjustable type is based on elec-
trical performance and operational principle. Within the ad-
justable phase shifters we can distinguish between those
where the phase change is achieved through a mechanical
tuning and those where the change is obtained with an elec-
trical signal. Furthermore, for the electrically tunable type we
can distinguish between those where the phase can be
changed continuously (analog) and those where the phase can
only be changed by discrete steps (digital). Figure 2 shows a
graphical classification of different types of phase shifters.
PHASE SHIFTER PERFORMANCE

In the evaluation of a phase shifter performance, besides the

b1 = S11a1 + S12a2 a2 quantities derived from its S parameters such as insertion
S11 S12 loss, quality factor, and VSWR, other quantities are impor-
S21 S22 tant for practical design. Below we discuss such parameters
a1 b2 = S21a1 + S22a2 and their corresponding meaning.
Port 1 Port 2
• Operational Bandwidth. This is defined as the 3 dB
Figure 1. Phase shifter viewed as a two-port device. bandwidth (2), which is expressed as the frequency range

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

Phase shifters
Tunable
Mechanical Electrical
Waveguide Coaxial Planar Digital
Ferrite Semiconductor Ferrite
Waveguide Planar Planar Waveguide
Figure 2. Phase shifter classification chart.
in which the insertion loss is contained within 3 dB
change.
• Power Handling Capabilities. This is expressed as the
maximum power which can flow in the phase shifter
without overheating its components or without introduc-
ing nonlinear phenomena due to the amplitude of the mi-
crowave field. This second limitation is particularly im-
portant for phase shifters which employ discrete devices
such as field-effect transistors (FETs) or diodes.
• Switching Speed. This is the time needed by the phase
shifter to switch between two different states, usually at
the two ends of the achievable phase shift (larger allow-
able jump).
• Temperature Sensitivity. This expresses the sensitivity
in terms of degree of phase shift degradation per ⬚C
change. This parameter should be small to avoid the ne-
cessity to adopt thermal compensation.
• Physical Size. This parameter can be very important, es-
pecially when the phase shifter is employed in a radar
system where thousands of units are required. Physical
dimensions and weight must be minimized even at the
cost of other parameters. As an example, think of a radar
system which needs to be mounted on the front side of a
jet fighter.
FIXED PHASE SHIFTERS
A fixed phase shifter must provide a constant phase change
between its two ports. Theoretically any transmission line
would be suitable for producing such a function as illustrated
in Fig. 3. For instance, in the X band (1) a coaxial cable could
x
V1 β V2 = V1e–jβ x
Port 1 Port 2
Figure 3. Transmission line acting as a phase shifter.
PHASE SHIFTERS 201
Fixed
Waveguide Coaxial Planar
Analog
Semiconductor Ferroelectric
Planar Planar Monolithic Waveguide Planar
be used as a fixed phase shifter, while in the Ku band a wave-
guide can be employed for the same purpose. In many applica-
tions, it is desirable to achieve a differential phase shift be-
tween two lines having the same length. For this purpose,
lines with different time delay must be used. A possible ap-
proach to this problem is to change the propagation constant
of the line, loading it with lumped or distributed elements. So
if 웁1 is the propagation constant of the unloaded line and 웁2
is the propagation constant of the loaded one, the achieved
differential phase shift will be given by (3)

φ = (β1 − β2 )x (8)
where x is the length of the line. So the basic idea in the
realization of this type of phase shifter is to change the propa-
gation constant of the transmission line by properly loading
it. As an example, consider the realization of a fixed phase
shifter in circular waveguide geometry. The waveguide is
loaded with metal inserts as shown in Fig. 4. The equivalent
circuits for the loaded and unloaded cases, assuming that the
;;;;
guide is operating with the fundamental mode TE11 (4), are
reported in Fig. 5. Both lines have the same length, and the
differential phase shift between the two TE11 modes is related
;;;;
E E
45°
Unloaded line Loaded line
Figure 4. Loaded circular waveguide.
202 PHASE SHIFTERS

x x

Y0 Y0 jBA jBB jBA Y0

Figure 5. Equivalent circuits for loaded Port 1 Port 2 Port 1 Port 2

and unloaded circular waveguides op- β1 β2
erating with the fundamental mode. Unloaded Loaded

to the normalized susceptance of the loads (5) by the following parts. The specific geometry depends on the operational fre-
equations: quency and on the guiding structure. As an example, three
classical implementations—a coaxial cable, a waveguide, and
BB sin 2βx − sin(2βx +
φ) a microstrip line, respectively—are outlined below.
BB = = (9)
Y0 sin2 βx
Coaxial Cable Phase Shifter
BA sin
φ cos βx − (1 − cos
φ) sin βx
BA = = (10)
Y0 sin βx sin(2βx +
φ) In a coaxial cable the dominant mode is TEM (see ELECTRO-
MAGNETIC FIELD MEASUREMENT) (6) so the phase of the signal
The use of Eqs. (9) and (10) allows one to design the loads propagating over a length between two cable ends points is
necessary to achieve a desired phase shift. Using a similar given by
concept, depending on the transmission line geometry, differ- √
ent type of loads can be devised as shown in Fig. 6. A quarter- ω r
φ= x (11)
wave transformer is used to avoid reflection at the load in- c
terface. Figures 6(a) and 6(b) show realization in circular
waveguide geometry using dielectric or metallic loads, while where x is the cable length, 웆 is the operating frequency, ⑀r is
Figs. 6(c) and Fig. 6(d) are rectangular waveguide geometry the dielectric constant of the inner core of the cable, and c is
using dielectric loads. the speed of light in free space. A ⌬x change in its length will
produce a change in phase (⌬␾) between the two cable points
end expressed by
MECHANICALLY TUNED PHASE SHIFTERS

;;;;;;
;;;;;;
√
ω r
Mechanically tunable phase shifters are capable of varying
φ =
x (12)
c
the signal delay in a transmission line using some moving
Figure 7 illustrates a section view of this type of phase
shifter. To allow for the stretch, the coaxial cable has concen-
tric air lines which can slide one into another, maintaining
the characteristic impedance of the cable constant while
changing length.

Waveguide Phase Shifter

In waveguide geometry, one way of obtaining a tunable phase
shift without changing its length is to change the effective

;;
yy ;;
yy ;;;
dielectric constant in some region of the guide, inserting a
Metal
Dielectric plates movable dielectric slab. Figure 8 illustrates one version of this
slab mechanical tunable phase shifter. The insertion of the flap in
Impedance Impedance
transformer transformer
(a) (b) Z0 Z0 Z0 Movable part

;;yy
yy ;; Dielectric
Impedance slab
transformer
(c)
Dielectric load

(d)

Figure 6. Different types of loaded transmission line.

Coaxial section
Sided in

Side view
Coaxial section

Figure 7. Mechanically tuned coaxial phase shifter.

Section view
 yy
;;
Dielectric slab
Narrow slot
t necessary to delay the electric signal independently from the
TE10
b mission line ⌬x which produces a delay of the signal at the
a
Figure 8. Mechanically tuned waveguide phase shifter.
the center of the waveguide, where the electric field is maxi-
mum assuming that the fundamental mode is propagating,
will delay the signal, producing a phase shift. This type of
device is only usable with some restrictions, since the thick-
ness of the flap and its dielectric constant must be calculated
to avoid the propagation of higher-order modes (i.e., TE30). A
simple equation for the design of this type of phase shifter,
which avoids higher modes, was proposed by Gardiol (7) and
leads to the following relation:
√ √
r tan[π (a − d)/λc ] = cot(π r d/λc ) (13)
Based on the same concept, it is possible to have a movable
dielectric inside a rectangular waveguide operating with the
fundamental mode TE10 as shown in Fig. 9, where the interac-
tion of the field with the dielectric will be maximum when the
plate is in the center of the guide (maximum delay corre-
sponding to maximum phase shift) and minimum when it is
on the side walls. Proper design of the ␭ /4 transformer (8) is
necessary to avoid reflections at the phase shifter interface.
Microstrip Phase Shifter
For the microstrip geometry a mechanically tuned phase
shifter was proposed by Joines (9). In this geometry it is pos-
sible to achieve a phase shift by changing the dielectric con-
stant of the substrate above and below the strip as depicted
in Fig. 10.
The change in the dielectric constant will induce a change
in the propagation constant, and consequently different phase
shifts will be achieved. This structure is attractive because it
yields a continuous phase shift while maintaining the charac-
yy
;;
teristic impedance constant. If we observe its section view de-
picted in Fig. 10, we notice that by a proper design of the
thicknesses t1 and t2, accordingly with the dielectric constant
(9), it is possible to keep the characteristic impedance of the
strip constant while changing its propagation constant.
;;
yy
Moving screw
Movable slab
Figure 9. Dielectric loaded rectangular waveguide phase shifter.
PHASE SHIFTERS 203
These are just a few examples of mechanically tunable
phase shifters; of course, many others are possible, but the
basic concept on which they operate is the same and can be
summarized as follows. In order to obtain a phase shift, it is
type of guiding structure used. This can be achieved in two
ways: One way is to change the physical length of the trans-
output port, inducing a phase shift change given by ⌬␾ ⫽
웁⌬x. In the second case, a change of the wave propagation
velocity obtained by changing the propagation constant of the
line ⌬웁 will produce a phase shift at the output port given by
⌬␾ ⫽ ⌬웁x.
ELECTRICALLY TUNED PHASE SHIFTERS
In electrically tuned phase shifters the phase change is con-
trolled by an electric signal (driving signal) such as a voltage
or a current. Since no moving parts are involved in the phase
control process, electrically controlled phase shifters can
achieve faster phase shift compared to mechanical ones. They
can be subdivided into two major categories—digital and ana-
log—depending on the type of control on the phase shift they
provide. One of the most important application of electrically
tuned phase shifters is the so-called phased array system. A
phased array system is an array of antennas of which by elec-
tronically controlling the phase of the electromagnetic signal
at each antenna element one can change its pointing direc-
tion. As an example, let us consider a linear array of antenna
as illustrated in Fig. 11. If all the elements are excited with
the same phase signal, the radiated signal adds coherently
and forms a wave front parallel to the array direction (line
joining all the elements). The beam pointing direction is per-
pendicular to the wave front, so the radiated beam will point
in a broadside direction. In a phased array, this direction is
adjustable by acting on the phase of the electromagnetic sig-
nal at the aperture of each radiating element. In a linear
array with equispaced elements the beam can be steered by
introducing a progressive phase shift between successive ele-
ments. If ␪0 is the scan angle with respect to the broadside
direction, then the phase delay to be introduced between adja-
cent antenna apertures can be calculated from
ω

φ = d sin θ0 (14)
c
where d is the element spacing, and c is the free space light
speed. For scanning the beam continuously, ⌬␾ is varied by
analog phase shifters; and for switching the beam from one
scan angle to another, ⌬␾ is varied in discrete steps by digital
phase shifters. The same principle applies to planar array for
achieving three-dimensional scanning and switching.
Digital Phase Shifters
Digital phase shifters use electronic devices such as pin di-
odes or FETs as switching elements; this allows the digital
phase shifter to direct the microwave signal through paths of
different length, obtaining in this way the phase shift. The
use of a pin diode as a switching circuit allows biasing of the
diode forward (to obtain a trough) or reverse (to obtain a open
circuit) by means of a dedicated bias circuitry. In a similar
 ;;
204 PHASE SHIFTERS

;;
t

C r C'
GND
r

B' Section CC'

;
;;
t2 Rotation axis

r2
A
r(2)
r2
Rotation disk

;;;
r(1)
r1

r1
A' Section AA'

t2 Rotation axis

;;
Rotating
dielectric
r2
B disk

Rotation disk

r1
Microstrip line Section BB'
Dielectric slab
Figure 10. Microstrip mechanical tuned
phase shifter. Top view Side view

way, an FET channel can be switched on or off by proper bias
(10). The use of FETs and diodes allows four basic designs.
The simplest one is shown in Fig. 12, where the shift is ob-
tained by switching the signal between two different length
transmission lines; Fig. 12 also shows a microstrip implemen-
tation of this type. The phase shift is proportional to the dif-
ference between the length of the two lines and is given by
⌬␾ ⫽ ⌬x웁. In a similar way, as shown in Fig. 13, the use of
different loads on the transmission lines, which are switched
on and off by the diodes, allows a phase change between the
biased and unbiased condition (⌬␾) related to the impedance
of the line (Z0) and to the susceptance of the loads (B) ac-
cording to the relation (5)

Bn
 from the rest of the circuit. The two ␭ /2 high-impedance mi-

φ = 2 arctan
1 − B2n /2
where Bn ⫽ Z0B. A microstrip implementation of this circuit
is also shown in Fig. 13; the reactive and inductive loads are
obtained using open stubs of different length, and their values
can be calculated for a given susceptance using (11)

2π f √  of the pin diode: The source and drain are grounded (only for
B = ZS cot
r
lS
c drain capacitances are equal. Because of this, the drain is not
where Zs is the stub impedance, f is the operation frequency,
⑀r is the relative dielectric constant, ls is the stub length, and
c is the speed of light in free space. Another design using a
pin diode in combination with a 90⬚ hybrid circuit is illus-
trated in Fig. 14. In this case the differential phase shift ob-
tained between the biased and unbiased condition is given by
x

φ = β (17)
2
The bias circuit must be designed carefully here, in order to
avoid degradation of performance and direct-current (dc)
leaks. The bias circuit must allow biasing of all the active
devices independently, while insulating the dc biasing signal
from the radio-frequency (RF) signal. A simple design for a
microstrip topology is illustrated in Fig. 15. The two dc blocks
are acting as series capacitors for the RF signal, allowing the
RF to go through the diode while stopping the dc component
(15) crostrip lines are operating as an open stub (11). At the mi-
crostrip junction they will result in an open circuit transpar-
ent to the microwave signal while allowing the dc signal to
provide the necessary bias for the diode. The high impedance
of the open stub makes it look like an open circuit for a larger
bandwidth (11).
The use of FETs as a switching element is similar to that
(16) the dc signal). In the off state, the gate-source and the gate-
isolated from the gate terminal. In real circuits, the bias net-
work is configured so as to provide high impedance for the RF
at the gate terminal. This is achieved by using a low-pass
filter such that it presents an effective RF open at the gate.
This arrangement is shown in Fig. 16.
 PHASE SHIFTERS 205

Beam direction

θ00

Equiphase front

7∆φ 6∆φ 5∆φ 4∆φ 3∆φ 2∆φ ∆φ 0° Antenna

Phase
shifter
Power
splitter RF signal Figure 11. Beam-steering concept using
input a phase shifter at each radiating element.

x1

Bias line

;;;
RF input RF output

;;;;;;
;;;;
x2

x1

x2 RF output

Pin diode Figure 12. Pin diode type of electrically

Bias line controlled digital phase shifter.
206 PHASE SHIFTERS

λ /4
Common bias

;;;; ;;
Bias line

RF input RF output
—jB jB —jB jB

;;;;;
Bias line

;;;;;
RF input Pin diode RF output

λ /4
Figure 13. Loaded pin diode electrically Dc blocking
capacitor
tuned digital phase shifter. Common bias

3 dB, 90°
Hybrid coupler
RF input x/2
0°

0° Bias line RF GND

90°
x/2
90°

;; ;;
;;;
RF output
Figure 14. Pin diode and 90⬚ hybrid cir- Bias line RF GND
cuit type of electrically controlled digital
phase shifter.

;;;;
Pin diode

RF input RF output

Dc block λ /2

2 kΩ
Ω 2 kΩ
Ω

Figure 15. Bias circuit for pin diode type

of phase shifter. Bias
;;;;
PHASE SHIFTERS 207

Analog Phase Shifters

RF input
S D
G
Low-pass
filter
Bias
Figure 16. Bias circuit for an FET type of phase shifter.
Because digital phase shifters only allow discrete phase
jumps, a cascade of them must be used when high resolution
in the phase change is desired. Figure 17 shows a typical ar-
rangement and the corresponding phase shift states for a
4-bit phase shifter, capable of giving phase jumps with an
increment of 22.5⬚ and a maximum phase shift of 360⬚. By
increasing the number of phase shifters, higher resolution is
achievable. The maximum achievable resolution will obvi-
ously depend on the number of phase shifters and is ex-
pressed by the relation
2π

φmin = n
2
where n is the number of discrete phase shifters.
Analog phase shifters allow time delay control of a microwave
signal by using an electric driving signal. They differ from
digital phase shifters due to their capability to provide contin-
RF output
uous phase delay control. This characteristic is very attractive
when a fixed phase resolution is impractical to use. Consider
as an example the received signal coming from a broadcast
TV, as illustrated in Fig. 18. Because a multiple reflection
path exist, a double image is received. One possible solution
to overcome the problem is to use two receiving antennas and
by proper adjustment of the phase difference between them
eliminate the reflected signal. Because of the random nature
of the delay, only a continuous adjustable phase shifter can
be employed.
Electrically analog tunable phase shifters can be subdi-
vided in three major subcategories as illustrated in Fig. 2. A
description of the operational principle for each of them is
provided below.
Ferrite Phase Shifters
Ferrite phase shifters are employed in a waveguide or a pla-
nar structure. They operate using the ferrite property of non-
linear dependence between magnetization (B) and magnetic
field (H). Ferrites are nonlinear and nonreciprocal magnetic
materials composed of a mixture of divalent metal and iron
oxide having the general chemical structure
MO + Fe2 O3 (19)
where M is a divalent metal such as manganese, magnesium,
nickel, or iron. They exhibit a hysteresis B–H dependence as
(18) reported in Fig. 19. To explain how ferrites are used in phase
shifters, it is not necessary to describe in detail the material
properties which are well documented in Refs. 12 and 13. The

22.5° 45° 90° 180°

Input Output
signal 1 1 1 1 signal

0 0 0 0
0° 0° 0° 0°
S1 S2 S3 S4 S2

Switch state Phase shift

S1 S2 S3 S4
0 0 0 0 0°
1 0 0 0 22.5°
0 1 0 0 45°
1 1 0 0 67.5°
0 0 1 0 90°
1 0 1 0 112.5°
0 1 1 0 135°
1 1 1 0 157.5°
0 0 0 1 180°
1 0 0 1 202.5°
0 1 0 1 225°
1 1 0 1 247.5°
0 0 1 1 270°
1 0 1 1 292.5°
0 1 1 1 315°
1 1 1 1 337.5°

Figure 17. Diagram of 4-bit phase shifter and corresponding switching scheme.
208 PHASE SHIFTERS

Broadcast TV
;;
;
H

Direct ray
Magnetic Ferrite Biasing
Multiple path field lines slabs wire
reflection
Figure 20. Nonreciprocal waveguide ferrite phase shifter.

achieved using a current loop around the ferrite slab (with

the aid of a biasing wire). The ferrite is placed in the wave-
guide in such a way to maximize the interaction with the ex-
Φ isting magnetic field in the guide. For waveguide operating
with the fundamental mode (TE10), the magnetic field will be
Σ maximum at 
and  of the longitudinal section of the guide
(6) as illustrated in Fig. 20. Because the magnetic field has
opposite direction at those sections, an asymmetrical bias (see
Fig. 20) will be necessary in order to obtain a phase shift.
This is done using a current flowing in the two wires in oppo-
Multiple image Single image
site direction. Another concept is to use different geometries
Figure 18. Phase shift recovering for a multiple path reflected as illustrated in Fig. 21. The cross section depicted in Fig.
signal. 21(a) is an extension of the one shown in Fig. 20, with the
difference being that the ferrite is placed where the maximum
magnetic field exists at the bottom and top of the guide. This
allows a reduction of the mismatch with the empty wave-
nonlinear H–애 dependence will be exhibited as shown in Fig.
guide, making easier the design of the matching circuit. Also
19. The permeability at specific magnetization value (H*) can

;;
yy
in this case as illustrated in the figure, a differential bias of
therefore be calculated as
the ferrite must be used. Figure 21(b) is also based on a simi-
∂B
B
µ = µ0 + (20)
∂H
H H=H ∗
Ferrite
In general the ferrite permeability takes the form of a tensor

yy
;;
because of the nonreciprocal behavior. The elements of this H H
tensor are a function of the applied magnetic field. When the External
magnitude or direction of the magnetic field is changed, the magnetization
permeability of the ferrite changes, thereby changing the
propagation constant of the electromagnetic wave. Phase shift
(a)
is a consequence of the change in the propagation constant
brought about by electronically controlling the applied mag- Ferrite

;;
yy
netic field. For a more extensive and complete treatment of
ferrite properties at microwave frequencies, see Refs. 14 and
15. As direct application of this concept, a waveguide ferrite
H
loaded phase shifter is described. The geometry of the device
is shown in Fig. 20, the magnetization of the ferrite is

(b)

;;
yy
B µ δB Ferrite
µ* = µ 0 +
δH H = H*

H H
H* 0 H*

(c)

Figure 19. Nonlinear B–H dependence and correspondent 애–H de- Figure 21. Different types of nonreciprocal waveguide ferrite phase
pendence. shifter.
 yy
;;
Biasing wires
;;
yy
Ferrite
rod
Dielectric
;y;y
yyy
;;;
support
Impedance
transformer
Ferrite rod Biasing wires
Dielectric support
Figure 22. Reggia–Spencer reciprocal ferrite phase shifter.
lar concept; but the asymmetrical bias is replaced by an
asymmetric geometry, so the ferrite is only placed on one side
of the guide. Further improvement toward the matching for
this structure is obtained in the case of Fig. 21(c). Several
versions of a planar structure which employ ferrites as tun-
able elements have been proposed (16–18). Even though in
principle those structures work, most ferrite phase shifters
currently constructed use waveguide geometry.
Another operational principle for the ferrite reciprocal
phase shifters is to use Faraday rotation to produce time de-
lay of microwave signal. This type of phase shifter was at first
proposed by Reggia and Spencer (19) and is illustrated in Fig.
22. Several modifications of the original form were proposed
later, but the basic operative principle remains the same. In
this phase shifter a longitudinal ferrite toroid is placed in the
longitudinal section of a rectangular waveguide (see Fig. 22).
The magnetic biasing field is produced by an external magne-
tization circuit. It is well known that when a linearly polar-
ized wave propagates in a ferromagnetic rod, the plane of po-
larization of the wave in the rod rotates. Now if the rod is
placed inside a rectangular waveguide with one of its dimen-
sion at cut-off, then the rotational effect is suppressed (for
small size rod). Reggia and Spencer have demonstrated large
changes in insertion phase with external magnetic field bias
for the transmitted power. They also demonstrated that the
= (21)
phase variations are independent of the propagation direc-
tion. Many other authors investigated the theory beyond this
effect (20,21). Practical design of the Reggia–Spencer phase
shifter is mostly based on approximate equations (22) which
consider the phase shift as a consequence of a small perturba-
tion in the effective permeability.
Ferroelectric Phase Shifters
In ferroelectric phase shifters the phase-shift capability of fer-
roelectric materials results from the fact that if we are below
their Curie temperature (23,24) (see FERROELECTRICS), the di-
electric constant of such a material can be modulated under
the effect of an electric bias field. Particularly, if the electric
PHASE SHIFTERS 209
field is applied perpendicularly to the direction of propagation
of the electromagnetic signal, the propagation constant (웁 ⫽
2앟/ ␭) of the signal will depend upon the bias field since 웁 ⫽
2앟兹⑀r / ␭0 and ⑀r ⫽ ⑀r(Vbias). The total wave delay will become a
function of the bias field, and therefore this will produce a
phase shift ⌬␾ ⫽ ⌬웁l, where l is the length of the line. Two
major implementations of a ferroelectric phase shifter have
been used: waveguide geometry and planar structures. In
waveguide geometry the ferroelectric material is placed inside
a waveguide as illustrated in Fig. 23. A voltage is applied to
the center conductor, creating a vertical electric field to the
grounded flange. The matching layer must be placed on either
side of the sample to couple the RF energy in and out of the
material. These rectangular layers of dielectric are needed in
the design of the phase shifter because of the impedance mis-
match between air and the high permittivity ferroelectric.
One problem in the use of this type of setup is the high bias
required (typically 1 kV to 2 kV) due to the thickness of the
material. Ferroelectrics require a bias voltage of the order 2
V/애m to 4 V/애m in order to change significantly their dielec-
tric constant (25,26).
Use of the planar type of ferroelectric material in micro-
strip geometry avoids this problem as demonstrated in Ref.
27. The geometry is illustrated in Fig. 24. The active part of
the device consists of a microstrip line printed on a ferroelec-
tric substrate whose dielectric constant is changed by bias.
The length of the strip determines the maximum phase shift
achievable for a fixed change of the propagation constant
(⌬웁), associated with the maximum bias voltage. The com-
plete design of this type of phase shifter is reported in Ref.
28. To reduce the required bias the ferroelectric material has
a thickness of the order of 0.1 mm to 0.2 mm, allowing bias
voltage of a few hundred volts. As in the case of the pin diode
phase shifter, attention must be dedicated to the design of
the biasing circuit, to avoid leakage of the dc voltage in the
RF circuit.
Varactor Diode Phase Shifter
In varactor diode phase shifters a varactor diode is used as
a variable-capacitance element. This variable capacitance is
obtained through a voltage-tuned capacitance of the diode un-
der a reverse-bias condition (24). The varactor diode is used
in combination with a hybrid coupled circuit as illustrated in
Fig. 25(a). The 3 dB 90⬚ hybrid circuit is symmetrically termi-
nated with the diodes. If X is the reactance of the diode, the
reflection coefficient can be calculated as (11)
jX /Z0 − 1
jX /Z0 + 1
and the corresponding phase of the reflection coefficient is
given by
φ = π − 2 arctan(X /Z) (22)
where Z0 is the characteristic impedance of the transmission
line (50 ⍀ typically). We notice that in order to obtain a phase
variation in the range going from 0 to 2앟, the reactance of the
diode must go from ⫺앝 to 0 to ⫹앝 and the maximum change
of phase is obtained when X ⫽ 0. Hence, in order to obtain a
maximum phase shift, the diode must be connected in series
with an inductive load to allow resonance (X ⫽ 0); this can be
210 PHASE SHIFTERS

yyy
;;; ;;;
yyy
;;;yyy
yyy ;;;
Figure 23. Waveguide ferroelectric type
of analog phase shifter.
Ferroelectric
material

achieved with a stub as illustrated in Fig. 25(b) for a micro-

strip realization. The impedance of the reflecting termination
(diode and stub) is given by
Section view
Biasing
electrode
Matching
layer
Side view

Also at X ⫽ 0 (resonance condition) a maximum insertion loss

due to Rd will occur. The corresponding attenuation in this
circumstance is

1

1 + R 
Z = Rd + j ZS tan βlS − (23) d /Z0
ωCd αdB = 20 log10 (27)
1 − Rd /Z0

where Rd and Cd are the equivalent parameters of the diode,

and Zs and ls are the stub characteristic impedance and The figure of merit (F) for the analyzed structure is calculated
length, respectively. The associated reflection coefficient is as
calculated from
|
φ|deg
R − Z0 + jX F= (28)

= d (24) αdB
Rd + Z0 + jX
A possible improvement of the presented structure can be ob-
As the bias voltage changes from 0 to a negative value, Cd
tained using two series varactor diodes as presented in Ref.
goes from Cdmax to Cdmin, giving a change of X expressed by
29. The operational principle remains the same, but a larger
1 1 change in the capacitance is obtained.

X = − (25)
ωCdmin ωCdmax

For such change of X the correspondent phase change can be

Γ
obtained as RF output


X 
|
φ| = 4 arctan (26) jX
2Z0

;;
yy
3 dB, 90°
Hybrid coupler
Ferroelectric
Microstrip line substrate

RF input jX

;y;yy
y;;
(a)
Side view

Γ jX
Ferroelectric Connection RF output lS
material pads Ground plane
ZS

3 dB, 90°
Hybrid coupler

RF input
Top view Bottom view (b)

Figure 24. Microstrip ferroelectric type of analog phase shifter. Figure 25. Varactor-based tunable phase shifter.

RF input RF output
Z
Figure 26. Active FET type of phase shifter.
Active Phase Shifter
Use of FET in an analog phase shifter (30) allows one to take
advantage of the gain of the FET at microwave frequencies,
while producing the time delay at the same time. Figure 26
shows the topology of this kind of phase shifter. The phase
variation in the transmission coefficient (S21) is achieved by
controlling the bias voltage at the gate of the FET. The bias
voltage is applied on the second gate of the FET, while a fixed
inductive load is connected to it. The bias voltage will change
the capacitance between the first gate (G1) and the source,
and this will change the amplitude and phase of the S21. One
limitation of this topology is the narrow bandwidth which is
achieved. Use of more complicated topologies as reported in
Ref. 31 will allow larger bandwidth and larger phase shift-
ing capabilities.
ACKNOWLEDGMENTS
The author wishes to thank Professor N. G. Alexopoulos of
the Electrical and Computer Engineering Department at the
University of California, Irvine, for useful suggestions.
BIBLIOGRAPHY
1. M. Sucher and J. Fox, Handbook of Microwave Measurements,
New York: Polytechnic, 1963.
2. G. D. Vendelin, A. M. Pavio, and U. L. Rohde, Microwave Circuit
Design Using Linear and Nonlinear Techniques, New York:
Wiley, 1990.
3. R. E. Collin, Foundations for Microwave Engineering, New York:
McGraw-Hill, 1966.
4. R. E. Collin, Field Theory of Guided Waves, 2nd ed., New York:
IEEE Press, 1991.
5. R. Winnery and V. Durez, Campi e Onde nell’ Elettronica per le
Comunicazioni, Milan: 1984.
6. C. A. Balaniis, Advanced Engineering Electromagnetics, New
York: Wiley, 1989.
7. F. E. Gardiol, Higher order modes in dielectrically loaded rectan-
gular waveguides, IEEE Trans. Microwave Theory Tech., MTT-
16: 919–924, 1969.
8. N. Marcuvitz, Waveguide Handbook, London: Peregrinus, 1986.
9. W. T. Joines, A continuously variable dielectric phase shifter,
IEEE Trans. Microw. Theory Tech., MTT-19: 729–732, 1971.
PHASE SHIFTERS 211
10. P. R. Gray and R. G. Meyer, Analysis and Design of Analog Inte-
grated Circuits, New York: Wiley, 1993.
11. G. Gonzalez, Microwave Transistor Amplifiers, Englewood Cliffs,
NJ: Prentice-Hall, 1984.
12. G. P. Rodrigue, Magnetic materials for millimeter wave applica-
tions, IEEE Trans. Microw. Theory Tech., MTT-11: 351–356,
1963.
13. J. Smith and H. P. J. Wijn, Ferrites, New York: Phillips’ Techni-
cal Library, 1959.
14. G. L. Matthaei, L. Young, and E. M. T. Jones, Microwave Filters,
Impedance Matching Networks, and Coupling Structures, Ded-
ham, MA: Artech House, 1980.
15. J. J. Green and F. Sandy, Microwave characterization of partially
magnetized ferrites, IEEE Trans. Microw. Theory Tech., MTT-22:
641–645, 1974.
16. R. R. Jones, A slow-wave digital ferrite strip transmission line
phase shifter, IEEE Trans. Microw. Theory Tech., MTT-14: 684–
687, 1966.
17. L. R. Whicker and R. R. Jones, A digital latching ferrite strip
transmission line phase shifter, IEEE Trans. Microw. Theory
Tech., MTT-13: 781–784, 1965.
18. W. M. Libbey, Characteristic of a microstrip two meander ferrite
phase shifter, IEEE Trans. Microw. Theory Tech., MTT-21: 483–
487, 1973.
19. F. Reggia and E. G. Spencer, A new technique in ferrite phase
shifting for beam scanning of microwave antennas, Proc. IRE, 45:
1510–1517, 1957.
20. P. A. Rizzi and B. Gatlin, Rectangular guide ferrite phase shifter
employing longitudinal magnetic fields, Proc. IRE, 47: 1130–
1137, 1959.
21. W. E. Hord, F. J. Rosenbaum, and C. R. Boyd, Theory of the
suppressed-rotation reciprocal ferrite phase shifter, IEEE Trans.
Microw. Theory Tech., MTT-16: 902–910, 1968.
22. K. J. Button and B. Lax, Perturbation theory of the reciprocal
ferrite phase shifter, Proc. IRE, 109B: 1962.
23. M. E. Lines and A. M. Glass, Principles and Applications of Ferro-
electrics and Related Materials, Oxford, UK: Clarendon Press,
1977.
24. C. Kittel, Introduction to Solid State Physics, New York: Wiley,
1986.
25. T. Mitsui and S. Nomura, Landolt–Bornstein: Numerical data
and functional relationship in science and technology, Ferroelectr.
Related Substances, 16: 1981.
26. R. Pepinsky, Physics of Electronic Ceramics, New York: Dekker,
1972.
27. F. De Flaviis et al., Ferroelectric materials for microwave and
millimeter wave applications, Proc. SPIE, Smart Structures and
Materials, 2448: 9–21, 1995.
28. F. De Flaviis, O. M. Stafsudd, and N. G. Alexopoulos, Planar mi-
crowave integrated phase shifter design with high purity ferro-
electric materials, IEEE Trans. Microw. Theory Tech., 45: 963–
969, 1997.
29. B. T. Henoch and P. Tamm, A 360⬚ reflection type diode phase
modulator, IEEE Trans. Microwave Theory Tech., MTT-29: 103–
105, 1971.
30. C. Tsironis and P. Harrop, Dual gate GaAs MESFET phase
shifter with gain at 12 GHz, Electron. Lett., 16: 553–554, 1980.
31. M. Kumar, R. J. Menna, and H. Huang, Broadband active phase
shifter using dual-gate MESFET, IEEE Trans. Microw. Theory
Tech., MTT-29: 1098–1102, 1981.
FRANCO DE FLAVIIS
University of California at Los
Angeles
212 PHASE SHIFT KEYING

See also FERRITE PHASE SHIFTERS; MICROWAVE PHASE

SHIFTERS.
J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering
Copyright
c 1999 John Wiley & Sons, Inc.

PREAMPLIFIERS
The essential task of sensors, detectors, and transducers is to convert the characteristics of the physical
world (e.g., light, sound, pressure, displacement, temperature) into electrical signals, which are then suitably
processed for the required application. Before being processed, these electrical signals must be conditioned by
appropriate electronic circuitry.
Despite the improvements carried out in recent years, all sensors have a common characteristic: a weak
signal delivered and a limiting noise level. Therefore, the front end of the sensor-associated electronic system
must be an amplifier, usually called a preamplifier. Two main requirements must be satisfied for preamplifiers.
First, they must raise the signal level adequately over a certain frequency range (linear amplification is very
often requested). Second, they must contribute only a minimum amount of additional noise. Depending on
the specific application, other features such as high linearity, large output swing, wide-band operation, and
large output drive capability may be needed, but these requirements do not differ substantially from those of
normal amplifiers. What is specifically important for preamplifiers is to optimize their noise performance. This
is because, although the noise performance of a generic electronic system [which is made up of a preamplifier,
signal conditioning and processing circuitry, and output interface (Fig. 1)] depends on the noise behavior of all
these subsystems, in practice, in a well-designed system the noise performance is entirely dominated by the
noise characteristics of the front-end circuit (preamplifier). This is true if the preamplifier gain is sufficiently
high to allow the subsequent processing to be performed with negligible degradation in the signal-to-noise
ratio. Hence, low-noise system design is mainly focused on low-noise preamplifier design.

Basic Concepts Related with Preamplifiers

Some basic concepts useful in analyzing preamplifiers from the noise standpoint, namely, equivalent input
noise, noise factor and noise figure, and noise matching, are introduced in this section.
Equivalent Input Noise. In the characterization of many nonideal electrical quantities, which are
generated by a plurality of sources or mechanisms within a circuit, it is a common practice to replace all by one
equivalent input source. This equivalent source has the same effect at the circuit output as the global effect of
all the individual internal sources and, therefore, the circuit can be considered free of such mechanisms (1),
which greatly simplifies circuit analysis and design. Offset voltage and noise are representative examples of
what has been discussed.
A network, such as an amplifier, is made up of many components. Any electrical component has its own
internal mechanisms of noise generation. As a result, the output of any real amplifier exhibits noise, which
depends on factors such as internal noise sources, circuit topology, gain, and measurement bandwidth. The
amplifier’s output noise power spectral density can be found by multiplying the noise power spectral density of
each source by the squared module of its particular transfer function and then superposing all the individual
noise contributions. This procedure must be followed for any frequency of interest.
1
2 PREAMPLIFIERS

Fig. 1. The electronic chain associated with a sensor includes a preamplifier, signal conditioning and processing circuitry,
and output interface. The stages cascaded to the preamplifier may provide additional gain.

Rather than by the noise measured at its output, an amplifier is best characterized by the minimum
signal applied to its input, which is still detectable at the output of the signal processor. This signal may be
conveniently regarded as equivalent to a virtual noise source located at the input. This is known as equivalent
input noise or input-referred noise of the amplifier, and allows one to easily compare the total noise generated
by the amplifier with the input signal. From the above considerations, the equivalent input noise power of an
amplifier coincides with the output noise power divided by the squared module of the amplifier gain (2).
A similar idea is applied to the noise model of a generic sensor. Starting from its small-signal equivalent
circuit, including all impedances and current/voltage signal generators, a noise equivalent circuit is derived
by including the noise sources associated with resistances (or, better, with the real parts of impedances) and
signal generators. From this equivalent noise circuit, an expression for small-signal gain and equivalent input
noise is derived.
Figure 2(a) represents the equivalent noise circuit of a generic system consisting of a sensor and a
preamplifier. The sensor is described by its signal voltage generator V s , its internal series impedance Zs , and
a noise voltage generator, V n,s , which includes the contributions by all sensor noise sources. The preamplifier,
having voltage gain Av and input impedance Zi , is represented from the noise point of view, by a noise voltage
generator V n,a and a noise current generator In,a placed in series and in parallel, respectively, with the input
port. These noise generators, whose magnitude is specified in units of V/(Hz)1/2 and A/(Hz)1/2 , respectively,
are in general, frequency dependent, and are very often represented in terms of their mean square voltage,
V 2 n,a (V 2 /Hz), and mean square current, I2 n,a (A2 /Hz). The two generators can be statistically correlated or
not, depending on the specific case. For example, they are practically 100% correlated and totally uncorrelated,
respectively, when modeling a metal-oxide-semiconductor (MOS) field-effect transistor or a bipolar junction
transistor (BJT) in the mid-frequency range (3). When combining the effects of different noise sources, one
must remember that noise is a random signal. Therefore, when summing two noise variables An and Bn , the
result is C2 n = A2 n + B2 n + 2 Re{A∗ n Bn }, where Re{A∗ n Bn } represents the real part of the cross-correlation
spectrum of An and Bn . For ease of use, the correlation effect between two variables is very often expressed
by using the so-called correlation coefficient γ, which is a normalized factor having a value between 0 (no
correlation) and 1 (100% correlation). Using this approach, one has C2 n = A2 n + B2 n + 2γAn Bn .
Although the number of noise sources in Fig. 2(a) has been reduced to three, further simplifications are
usually carried out to represent them just by one equivalent input noise voltage generator, V n,eq , at the signal
source location (2). To derive an expression for the equivalent input noise, the total noise at the amplifier
 PREAMPLIFIERS 3

Fig. 2. A generic system noise model (a) can be reduced to an equivalent circuit with an equivalent input noise voltage
generator (b), or to an equivalent circuit with an equivalent input noise current generator (c).

output, V n,o , must be first derived. Assuming V n,a and In,a to be statistically uncorrelated, one obtains:

The system gain from the signal source location is

4 PREAMPLIFIERS

Therefore, the equivalent input noise voltage, V n,eq , which is equal to the total output noise divided by the
squared module of the system gain, is given by;

After combining and reflecting all noise sources to the signal source location, the resulting equivalent circuit
is shown in Fig. 2(b). The noise source V n,eq will generate exactly the output noise given by Eq. (1).
V 2 n,eq can also be obtained from Fig. 2(a) by disconnecting the noiseless amplifier and evaluating the
voltage across the noise generator In,a , which results in Eq. (3). This operation corresponds to finding the
equivalent dipole connected at the input of the noiseless amplifier (Thévenin theorem). In practice, the dipole
in Fig. 2(a) constituted by V s , V n,s , Zs , V n,a , and In,a , is exactly equivalent to the dipole in Fig. 2(b) constituted
by V s , V n,eq , and Zs .
Observe that, as indicated in Eq. (3), the equivalent input voltage noise does not depend on the amplifier
gain and input impedance, although the effect of any noise generated at Zi is implicit in In,a . However, V n,eq
depends on the impedance of the signal source, as well as on the noise generated by the sensor (hence, the
design approach for noise optimization will also depend on the kind of sensor impedance, that is resistive,
capacitive, inductive, as will be shown below). Output noise will obviously depend on both the gain and the
input impedance of the amplifier.
Following similar steps, an equivalent noise circuit of the system can also be derived in terms of an
equivalent input noise current generator In,eq [Fig. 2(c)]:

where I2 n,s = V 2 n,s /|Zs |2 .

Either equivalent noise circuit can be used, however, it is generally more appropriate to characterize the
system noise in the same terms as the source signal (voltage or current).
If the amplifier noise voltage and current generators V n,a and In,a are not statistically independent, as
occurs when they contain some components arising from a common phenomenon, the scheme of Fig. 2(b) must
include another noise voltage generator in series with V n,eq . The power spectral density of this generator is
a function of their correlation coefficient: V 2 n = 2γ|V n,a In,a Zs |. In the same way, an additional noise current
generator I2 n = 2γ|V n,a In,a /Zs | has to be placed in parallel with In,eq in the scheme of Fig. 2(c).
Equivalent Input Noise in Cascaded Stages. Consider the network in Fig. 3, which consists of n
cascaded stages having respective voltage gains Av1 , Av2 , . . ., Avn and equivalent input noise voltage sources
V n,eq1 , V n,eq2 , . . ., V n,eqn . It should be pointed out that a “stage” in this figure can be a complex circuit or even a
single active device. Moreover, for each stage i (i = 1, 2, . . ., n), Avi and V n,eqi are evaluated taking the value of
input and output impedances into account. Assuming that noise sources of different stages are uncorrelated,
as is the usual case, the total output noise power is
 PREAMPLIFIERS 5

Fig. 3. Schematics for evaluating the noise performance of an n-stage voltage amplifier.

which corresponds to an equivalent input noise for the whole network equal to

From this equation, one concludes that the noise behavior of the whole network can be dominated by the first
stage, provided that its voltage gain is large enough. In this case, in fact, noise contributions by the following
stages can be neglected. The same conclusion also holds when considering current noise, obviously referring to
the current gain rather than to the voltage gain of the stages.
Noise Factor and Noise Figure. Noise factor F is one of the most traditional parameters used to
characterize the noise performance of an amplifier. It is defined as the ratio of the total available output noise
power per unit bandwidth to the portion of that output noise power caused by the noise associated with the
sensor, measured at the standard temperature of 290 K (4). To emphasize that this parameter is a point
function of frequency, the term “spot noise factor” may be used. Since the noise factor is a power ratio, it can
be expressed in decibels. In this case, the ratio is referred to as noise figure (NF). That is, taking Fig. 2 and Eq.
(3) into account,

An alternative expression for the noise figure can be derived from Eq. (7), obtaining

where (SNR)i is the signal-to-noise ratio (SNR) available at the sensor output, and (SNR)o is the SNR at the
output of the real (i.e., noisy) amplifier. The above result indicates that NF accounts for the signal-to-noise
power degradation caused by the preamplifier. Thus, for an ideal amplifier, which does not add any noise, the
6 PREAMPLIFIERS

output signal-to-noise ratio is kept equal to its input counterpart, and NF = 0 dB. Alternatively, an NF of 3 dB
means that half the output noise power is due to the amplifier.
As will be shown later, NF by itself is not always an appropriate figure of merit to characterize the
noise performance of an amplifier. As stated above, NF is only valid to indicate how much noise is added by a
preamplifier to a given input source resistance, and is therefore useful to compare noise behavior of different
preamplifiers with a determined signal source. However, it is not a useful tool for predicting noise performance
with an arbitrary source.
Noise Matching. Let us consider now the particular case where the internal impedance of the signal
source is a resistor Rs . This corresponds to one of the most frequently used types of sensors, which can be
represented by a signal source generator V s in series with its internal resistance and a thermal noise generator
V n,s , whose power spectral density is:

where K is Boltzmann’s constant (1.38 × 10 − 23 Ws/K) and T is the absolute temperature (K). According to Eq.
(7), the noise figure for this resistive signal source is given by

By differentiating this expression with respect to Rs , one obtains the so-called optimum source resistance, for
which NF is minimum:

From Eqs. (10) and (11), NF can be written as

in which M = Rs /Ropt is the matching factor. For a given V n,a ·In,a product, NF is minimum for M = 1.
The effect of the source resistance variation on NF for amplifiers having different values of the noise
sources product V n,a · In,a , is illustrated in Fig. 4 [p. 46 in Ref. 2.]. The minimum value of the noise figure,
NFopt , occurs at Rs = Ropt . As the product V n,a · In,a increases, the noise figure also increases and is more
sensitive to source resistance variations.
In the more general case where the correlation factor, γ, is different from zero, the optimum value, F opt ,
of the noise factor corresponding to the optimum source resistance is easily calculated as

F opt defines the best performance obtainable when the source resistance can be selected to match Ropt . Eq. (13)
also clearly shows that, for any given source resistance and temperature, the best noise performance, obtained
when perfect matching is achieved, depends on the product V n,a ·In,a of the amplifier (5,6).
 PREAMPLIFIERS 7

Fig. 4. NF reaches its minimum value for Rs = Ropt . NF increases with increasing value of the product V n,a ·In,a .

Noise matching is based on the idea of modifying the amplifier equivalent input noise sources as seen at
the signal source location, to meet the condition Rs = Ropt , so as to minimize the total equivalent input noise
(5). This condition, which indicates that the preamplifier input stage is matched to the sensor, is considered as
the essence of low-noise design. Of course, to keep the noise low, the rest of the amplifier must also be designed
so that its noise contributions are low compared with those of the input stage.
A very simple and illustrative way to modify the amplifier equivalent input noise consists of coupling the
sensor to the amplifier by means of a transformer with a primary-to-secondary turns ratio of 1:N (Fig. 5 shows

this for the case of a resistive sensor). The amplifier noise sources are reflected to the primary as V n,a = V n,a /N

and I n,a = NIn,a . The ratio of these reflected parameters is:


Matching R s to Rs , one can derive the turns ratio required in the coupling transformer:

When this condition is met, the amplifier sees the optimum source resistance and, hence, the equivalent input
noise is minimized. It has to be pointed out that a real transformer has its own internal noise sources and
stray impedances, which have to be taken into account in an accurate low-noise design. Moreover, the use of a
transformer requires a suitable shield to external electromagnetic fields, which can induce spurious currents
in the transformer itself.
According to the above results, it appears that the noise figure NF can be alternatively improved by
adding a series or shunt resistance to a given source resistance Rs (or, by correspondingly changing the sensor
resistance), to make its final value equal to Ropt . However, due to the addition of an extra resistor, the signal-to-
noise ratio gets worse. On the other hand, for Rs = 0, NF goes to infinity, although the actual output noise is less
than that corresponding to any other value of source resistance, including Ropt . This contradictory situation
arises from the fact that reducing NF improves the output SNR only if the SNR at the source remains constant.
8 PREAMPLIFIERS

Fig. 5. Noise matching by coupling transformer minimizes the total equivalent input noise.

This condition is not met when matching is achieved by modifying the source resistance, but it is satisfied
when using a coupling transformer. For the same reason, only when increasing sensor resistance increases
the signal proportionally, it should be modified so as to match the amplifier optimum noise source resistance.
When choosing or designing a preamplifier, the best noise performance is obtained by achieving the minimum
equivalent input noise rather than the lowest noise figure.
Noise matching can also be achieved in the case of narrow-band signal sources. By exploiting the resonance
of a suitable LC group, the amplifier equivalent input noise as seen at the signal source location, can be
optimized at the required center frequency. It is possible to follow this approach for both resistive and reactive
narrow-band sources (6).
Since transformers, as well as other coupling techniques using discrete components, are not compatible
with solid-state circuits, noise matching for monolithic preamplifiers has to be obtained by appropriate choice of
transistor sizes and bias conditions (7). In particular, when V n,a is the dominant noise source of the preamplifier,
noise matching can be obtained by using n input transistors connected in parallel rather than a single input
transistor. Indeed, this technique reduces input noise voltage by a factor of and increases input noise
current by the same factor, which from the noise standpoint, is equivalent to using a coupling transformer with
a turns ratio of 1: (5). Similar techniques can also be adopted for discrete preamplifiers, even though much
less flexibility is obviously available.

Design Considerations for Preamplifiers

Designing or selecting a preamplifier for a specific application involves many specifications and choices. The
procedure starts by considering sensor characteristics, such as signal source type, noise, impedance, and
frequency response. As a function of that, the preamplifier must be designed so as to achieve the lowest value
of equivalent input noise.
According to the above discussion, the ultimate limit of equivalent input noise is determined by the sensor
impedance Zs and the amplifier noise generators, V n,a and In,a , where all these parameters may generally be
frequency dependent. Therefore, the signal source impedance and frequency range are decisive when choosing
the type of preamplifier input device, as in a well-designed amplifier, noise performance is heavily affected by
this element. To assist in this task, Fig. 6 [p. 210 in Ref. 2] can serve as a general guide. In this figure, the
different ranges of source impedance values are covered by the different types of active or coupling devices.
Low values of source resistance usually require the use of a coupling transformer for noise matching, while, for
 PREAMPLIFIERS 9

Fig. 6. Guide for selection of input devices.

matching the highest source resistance range, the extremely low noise current In,a of field-effect transistors is
exploited.
With respect to the frequency range, in the simplest case of a resistive source, matching the amplifier
optimum source resistance Ropt to the source resistance, minimizes the equivalent input noise at a given
frequency. However, if the preamplifier must operate over a large frequency band, the designer’s task is to
minimize the noise integrated over this interval. Then, if the source impedance is reactive and/or the equivalent
amplifier noise sources are functions of frequency, the use of a circuit simulator is often necessary to perform
this integration over the whole bandwidth and optimize noise performance. With respect to this, it is important
to note that the preamplifier bandwidth has to match, as much as possible, the signal spectrum needed in
the specified application, since increasing the bandwidth increases the integrated output noise. Once the low
and high amplifier cutoff frequencies of the preamplifier have been adjusted, the computer analysis may show
that noise requirements are not fullfilled and, then, another operating point or different device sizes must be
chosen. In extreme cases, different amplifiers or circuit topologies must be used.
Finally, needless to say, any noise injection from external sources must be minimized. For example, in
case electrical and/or magnetic shielding has to be provided against electromagnetic interference, power supply
filtering can be required to ensure a quiet supply voltage, ground connections have to be carefully studied, noise
injection from digital sections has to be minimized. However, these considerations regard general system design,
and are not specific to preamplifier design.
Next, the above design considerations are particularized for three types of source impedances (i.e., resis-
tive, capacitive, and inductive), with emphasis in amplifiers for monolithic implementations. For this reason,
mainly bipolar and MOS transistors will be considered as amplifier devices.
Preamplifiers with Resistive Sources. The simplest type of source impedance is a resistance. Among
sensors with this type of source impedance, some (i.e., voltaic sensors, such as thermocouples, thermopiles,
infrared detectors, etc.) generate a voltage signal, while others (e.g., photoconductive detectors used in opto-
electronic applications) produce a current signal. Figure 7 shows two generic preamplifiers with a resistive
source (the noise sources, i.e., the resistor thermal noise generators and the equivalent amplifier input noise
generators, are also included in both schemes). In Fig. 7(a), a sensor voltage source is coupled to a voltage am-
plifier by means of a coupling capacitor Cc , while a resistor Rb is added for biasing the amplifier input device,
which corresponds to a very usual situation. Instead, a resistive sensor, which provides a current signal, has
been assumed in Fig. 7(b). In this case, a transimpedance amplifier is used to amplify the signal from the high
impedance source. The transimpedance gain of the amplifier, V o /Is , is determined by the feedback resistor Rf ,
provided that the loop gain is high enough.
Referring to the voltage amplifier in Fig. 7(a), a high-pass response is caused by the coupling capacitor
Cc along with the equivalent series resistance of the input network. Cc must be chosen in such way that its
reactance can be neglected in the frequency range of interest. Thus, the voltage gain in the input network is
substantially independent of frequency. Moreover, the contribution of In,a to the equivalent input noise voltage
V 2 n,eq [see Eq. (3)] results equal to (In,a Rs )2 .
10 PREAMPLIFIERS

Fig. 7. Preamplifiers with resistive sources: (a) voltage amplifier with coupling capacitor; (b) wide-band transimpedance
preamplifier.

Assuming a much higher amplifier input impedance than Rs and Rb , the equivalent input noise voltage
of the system turns out to be:
 PREAMPLIFIERS 11

In the remainder of this article, the generally accepted assumption that the amplifier noise is dominated by its
input device will be adopted. In addition, single-ended input stages, which as a general rule allow the designer
to minimize the noise contribution of the amplifier, will also be assumed.
First consider the case when the input transistor is a bipolar device. Neglecting 1/f noise and frequency-
dependent terms in the frequency band of interest, the equivalent input noise sources can be approximated as
(6):

where rb is the base resistance, q is the electron charge, IE , IB , and IC are the dc emitter, base and collector
currents, respectively, and β = IC /IB is the dc current gain. This operating region of the BJT is known as
shot noise region (2), since the shot noise mechanisms are the dominant ones. In this operating region, the
correlation effects between the input voltage and current noise sources can be usually neglected (γ ∼ = 0). Here
and in the following, it shall also be assumed that the noise contribution by the base resistance is negligible,
as can be achieved with adequate layout, that is by making rb sufficiently small. The optimum noise resistance
can be expressed as a function of the design parameters of the input transistor:

The equivalent input noise of the system is minimum when the noise matching condition is fulfilled, that is
when Ropt as from Eq. (18) is made equal to the equivalent resistance of the input network, Rs Rb . This is
achieved for the following biasing collector current:

Obviously, the same result is achieved by differentiating V n,eq with respect to IC for V n,eq , as given by Eq. (16).
Replacing Eq. (19) into Eq. (16), the total equivalent input noise for the optimum biasing collector current
can be derived:

The first term, 4KTRs (1 + Rs /Rb ), is due to the thermal noise contribution of the source and biasing resistances,
while the second term, 4KTRs (1 + Rs /Rb )β − 1/2 , arises from the amplifier noise. It is apparent that the noise
contributed by the amplifier is lower than the thermal noise by a factor of β1/2 . Also, the noise contribution
of the biasing resistor can always be kept lower than that of Rs , by choosing Rb > Rs . Therefore, the noise
performance of voltage amplifiers with bipolar input devices and resistive sources can be made to be dominated
by the resistive source itself, if IC can be chosen equal to IC,opt . An alternative interpretation of Eq. (19) consists
in considering the term (1 + β − 1/2 ) as the factor by which the preamplifier increases the thermal noise of the
source and biasing resistances. In other words, this term is the lowest value of the optimum noise factor, F opt ,
12 PREAMPLIFIERS

of a BJT working in the shot noise region used as the input device of an amplifier, which is obtained when the
value of IC,opt corresponds to a sufficiently small collector current density (2).
Very similar conclusions are obtained when considering transimpedance amplifiers with resistive sources
(3)—see Fig. 7(b). Following the above procedure, one finds that the bias collector current of the input bipolar
transistor for minimum noise is IC,opt = (KT/q)β1/2 /(Rs Rf ), and that the corresponding total equivalent input
noise current is I2 n,eq = [4KT/(Rs Rf )] · (1 + β − 1/2 ). Again, in a well-designed bipolar preamplifier, noise perfor-
mance can be made to be dominated by the resistive source, if Rf can be chosen sufficiently large. The choice of
the feedback resistor Rf will result as the best trade-off between noise, transimpedance gain, and bandwidth
requirements.
Now refer to the case when an MOS transistor is used as the input device of the preamplifier in Fig. 7(a).
The equivalent input noise generators of an MOS device in the mid-frequency range can be approximated as
(3):

where Af is a suitable technology-dependent constant, W and L are the width and length, respectively, of the
transistor, gm is its transconductance, and Ci its input capacitance. As the noise voltage source is placed in series
with the signal source, the only way to minimize its contribution to the total equivalent input noise voltage
V 2 n,eq is to minimize the noise source itself. To reduce thermal noise, a large transistor transconductance must
be used, which means a large aspect ratio and a large bias current. To reduce the 1/f term, a large gate area is
required. The contribution of the noise current source to V 2 n,eq is equal to V 2 n,a [ω(Rs Rb )Ci ]2 , and is, therefore,
negligible with respect to V 2 n,a in the frequency band of interest {ω < [(Rs Rb )Ci ] − 1 }.
When transimpedance amplifiers in MOS technology are considered, the contribution of the term V 2 n,a
to the total equivalent input noise current is given by V 2 n,a /(Rs Rf )2 . This should be compared with the
noise current 4KT/(Rs Rf ) contributed by the source and feedback resistances. Therefore, in the presence of
a very large source resistance, the noise contribution of the amplifier can be made negligible provided that a
sufficiently large feedback resistor is used. In this case, MOS amplifiers should be preferred to bipolar ones (3).
By contrast, in the case of a small source resistance, the source V 2 n,a must be minimized to ensure low-noise
performance of the preamplifier. This can be obtained with the same techniques as seen above for the case of
the voltage amplifier. Again, the contribution due to the amplifier input current noise can be neglected in the
frequency band of interest.
Preamplifiers for Optical Receivers. A very popular preamplifier application is for optical receivers.
An optical receiver is a circuit able to detect and process a signal coming from an optical source. Basically,
it is made up of an optical sensor followed by a preamplifier and a processing section. The optical sensor
(photodetector), which in its simplest form, is a reversed-biased diode, converts the optical signal into an
electrical current. The photodetector is modeled as a current source with an ideally infinite output resistance
and a capacitance in parallel. As the input electrical signal can be very small (e.g., down to the nA range), it
must be amplified with a preamplifier to a level suitable for the following processing. Therefore, low noise, high
gain and, in many cases, high bandwidth and adequate dynamic range, are key amplifier requirements in this
kind of application.
The basic principle of a preamplifier for optical receivers is to convert the current signal provided by the
photodetector, Is , into a voltage signal having a suitable amplitude. The most popular configuration consists of
a transresistance amplifier, as illustrated schematically in Fig. 8(a) (8), where noise generators are not shown.
The current Is generated by the photodetector flows through the feedback resistor Rf which, in turn, produces
an amplifier output voltage V o = −Is Rf , provided that the loop gain is large enough. The required current-to-
 PREAMPLIFIERS 13

Fig. 8. Preamplifiers for optical receivers: a transresistance preamplifier (a) is generally preferred to the use of a grounded
resistor followed by an active stage (b).

voltage conversion can also be achieved by feeding the signal current directly to a grounded resistor Rg [Fig.
8(b)] (9). A suitable active stage is cascaded to provide decoupling between the input section and the following
stages and, in this case, additional voltage gain. The choice of Rg results as a tradeoff between gain (V o /Is ) and
low thermal noise added to the signal current (4KT/Rg ) on the one hand, and bandwidth, which is limited to
1/(2πRg Cp ), on the other, where Cp includes the photodetector capacitance in parallel with the amplifier input
capacitance. For this reason, an equalizer stage (substantially, a parallel group RC) is very often cascaded to
the active stage when Rg has a large value (9). The use of a large Rg also causes a limited input dynamic range,
as the whole voltage signal Rg Is , is applied to the input of the active stage.
The transresistance configuration of Fig. 8(a) provides the best trade-off in terms of noise and gain on
the one hand and bandwidth on the other, and also gives no problems regarding input dynamic range. The
achievable signal bandwidth (assuming that the amplifier has an ideal frequency behavior) is now equal to
1/[2πRf (Cf + Cp /A)], where Cf is the parasitic capacitance around the amplifier (Cf  Cp ). The actual bandwidth
of the system is limited either by parasitic capacitances in the feedback network or by the bandwidth of the
amplifier. The former is a common case in high-gain applications, when a large value of Rf is used, while the
latter is more typical in lower-gain applications. In any case, attention must be paid to achieving frequency
stability, as a closed-loop configuration is adopted. Neglecting the feedback parasitic capacitance, the equivalent
input current noise of the system in the frequency band of interest is

where In,s and In,d account for shot noise of signal and dark currents of the photodetector, respectively. From
the above equation, one can observe that the contribution of V n,a to the total equivalent input noise increases
at high frequencies, even though at low frequencies, it can be negligible if V n,a is sufficiently small [“noise gain
peaking” effect (8)]. However, at very high frequencies, the contribution of V n,a is limited by the ratio Cp /Cf and
then rolls off due to the amplifier open-loop response.
Preamplifiers with Capacitive Sources. A capacitive sensor source can be modeled, in its useful
frequency range, as a voltage source in series with a capacitor or as a current source in parallel with a
14 PREAMPLIFIERS

capacitor (the case where the sensor signal is delivered in the form of a charge packet will be briefly addressed
at the end of this section). The output signal of the sensor is taken either as the open-circuit voltage or the
short-circuit current, respectively. Sensor capacitance and signal frequency depend on the application, and can
vary by several orders of magnitude (from picofarad up to nanofarad and from hertz to megahertz ranges,
respectively). Typical examples are capacitive antennas (e.g., for radio receivers), electret microphones, some
piezoelectric sensors such as hydrophones, optical detectors, and so forth. In this section, wide-band monolithic
preamplifiers, specifically, will be considered. In the case of narrow-band applications, noise optimization can
be achieved by adding a suitable series or parallel inductance in the input network, using a technique very
similar to that used for narrow-band preamplifiers with inductive sources (6) (see the next section). The basic
principle is to determine a proper resonance which ideally makes the effects of the amplifier input current or
voltage noise source disappear at the frequency of interest, thereby minimizing the system equivalent input
noise.
Two basic topologies of wide-band preamplifiers for capacitive signal sources are depicted in Fig. 9,
where the voltage source representation is used for the sensor, and equivalent input noise generators are also
shown. Notice that, ideally, no noise is generated in the signal source, due to its reactive nature. In Fig. 9(a),
a biasing resistor Rb has been included. This resistor must be large enough so that, in the frequency band
of interest, the pole generated by the group Rb Cc roughly cancels out the effects of the zero located in the
origin, which arises due to Cc . Thus, the preamplifier gain is independent of frequency, as required in most
wide-band applications. This is a typical situation in preamplifiers for electret microphones, where, in the
case of monolithic implementations, an active biasing resistor is generally used to avoid excessive silicon area
occupation due to the large resistance value required (10,11). Noise considerations for this topology are very
similar to those for voltage amplifiers with resistive sources, although in the present case the source resistance
is assumed to be negligible, and obviously the dominant noise source is the amplifier.
In the capacitive-feedback structure of Fig. 9(b), no dc feedback or biasing element has been drawn,
although generally dc stabilization is required (this can be obtained, e.g., with a very large feedback resistor,
and will be neglected in the following noise considerations). In this scheme, the feedback capacitor Cf sets the
mid-frequency voltage gain equal to −Cs /Cf . Also in this case, therefore, the gain is substantially independent
of frequency. Moreover, it shows no dependence upon the parasitic capacitance Cp associated to the input line,
which is very useful in applications requiring long cable connections between the sensor and the amplifier (12).
Choosing the best value of Cf derives from two contrasting requirements. On the one hand, a small capacitor Cf
should be chosen, so that the minimum input signal must be amplified to a level adequate to drive the cascaded
stages, while on the other hand, capacitor Cf should not be so small that the amplifier output saturates in the
presence of the maximum allowed input signal.
Again, regardless of the application, the noise performance of the preamplifier is of paramount importance,
as it generally determines the sensitivity of the overall system. From Fig. 9(b), the equivalent input noise voltage
is

For the best noise performance, the most straightforward choice is again the use of single-ended input stages,
although fully differential amplifier solutions are also used for this kind of sensors (12,13). As pointed out
above, in this section we consider mainly bipolar and MOS input devices, as currently JFET circuits are used
only in specific applications (e.g., in charge-sensitive amplifiers for nuclear physics experiments; see below). In
the case of a bipolar input transistor, taking into account its equivalent input sources given in Eqs. (17) and
 PREAMPLIFIERS 15

Fig. 9. Preamplifier with capacitive sources: (a) voltage amplifier with biasing resistor; (b) voltage amplifier with capacitive
feedback.

neglecting the correlation factor γ, the total equivalent input noise turns out to be:

It is apparent that a small base resistance rb and a high large current gain β are needed for low noise. Moreover,
one can see that, for any given value of IC , the base current shot-noise contribution [second term in Eq. (24)]
is dominant at low frequencies, while voltage noise [first term in Eq. (24)] dominates at high frequencies. To
achieve noise minimization, noise matching must be achieved by a suitable choice of the collector bias current
16 PREAMPLIFIERS

IC . Indeed, increasing IC has opposite effects on the two noise contributions. The optimal value of IC can be
easily calculated by taking the derivative of Eq. (24) with respect to IC , obtaining (3,7):

Notice that Eq. (25) is formally identical to Eq. (19): ω(Cs + Cp + Cf ) represents the module of the admittance to
the input network. As observed, IC,opt depends on the frequency. As a consequence, when required, wide-band
noise optimization with bipolar input stages is not possible. Obviously, when choosing the value of IC , other
features such as gain and operation speed must also be taken into account.
In the case of an MOS input transistor, using the noise sources in Eqs. (21), the equivalent input voltage
noise source turns out to be:

where the term Ci results from the presence of the input noise current, taking also in account the 100%
correlation existing between V n,a and In,a .
It should be emphasized that noise transfer gain does not depend on frequency. The term V 2 n,a includes
a flicker as well as a thermal component. Both these contributions should be reduced to a minimum to achieve
low-noise performance. To reduce input-referred noise, capacitances Cp and Cf must be minimized, even though
they are noiseless elements. As far as Ci is concerned, it is worth pointing out that its value is strictly related to
the input transistor size. Changing its value has two opposite effects on noise performance. On the one hand,
increasing the aspect ratio W/L of the input device leads to a decrease in both flicker and thermal noise, as a
result of the corresponding increase in its gate capacitance and transconductance, respectively. On the other,
from Eq. (26), increasing Ci will also degrade noise performance. An optimized value of the input transistor
capacitance and, hence, of its size, is therefore necessary, which is determined by taking the derivative of Eq.
(26) with respect to Ci . The gate length should be set to the minimum to maximize amplifier performance
in terms of thermal noise and gain-bandwidth product. Noise optimization results are different when flicker
and thermal components are considered, as a consequence of the different dependence of their noise spectral
density upon Ci . In the case of flicker noise, the best capacitance matching is obtained by setting Ci = Cs + Cp
+ Cf , while for thermal noise, the best value is Ci = (Cs + Cp + Cf )/3. When both flicker and thermal noise
contributions are important, a trade-off value of Ci is chosen, for example, the average of the two optimal values
(3). An analytical derivation of the optimum Ci value in the presence of both thermal and flicker series noise
can be found in (14). A suitably large bias current is also required to maximize the transconductance of the
input transistor and, hence, reduce its thermal noise. An n-channel input device also helps to this end. On the
contrary, flicker noise is generally smaller for p-channel devices (15,16,17).
It has been shown (3) that, for a capacitive source, an MOS input device offers better noise performance
than a bipolar one. Obviously, a suitable design is needed to minimize noise contributions by the other compo-
nents and following stages in the circuit (for the latter purpose, e.g., some gain should be introduced in the first
stage of the amplifier). Depending on the application, high linearity, large load drive capability, and wide output
dynamic range can also be required of the preamplifier, these features being related mainly to an optimized de-
sign of its output stage. Moreover, due to the presence of the feedback loop, adequate frequency stability must be
provided. Bipolar technology offers inherent advantages for such requirements, however, CMOS preamplifiers
meeting all the specifications needed can be developed using adequate circuit design approaches. These include
using a three-stage topology, a noninverting class A-B output stage, and suitable compensation techniques (3),
 PREAMPLIFIERS 17

Fig. 10. Basic scheme of a charge-sensitive preamplifier.

and employing parasitic bipolar transistors (12). When possible, CMOS technology is the preferred choice as it
allows the designer to integrate the preamplifier together with the cascaded processing section at low cost.
BiCMOS technology has also been proposed to implement the preamplifier (3). BiCMOS technology
provides both CMOS and bipolar devices on the same chip. This allows the designer to take advantage of
the superior noise performance of a CMOS transistor used as the input device and, at the same time, to exploit
the excellent features of bipolar transistors to achieve the other requirements with simpler circuits with respect
to fully CMOS solutions. The main disadvantage of BiCMOS technology is its increased process complexity
and, hence, its higher cost.
Charge-Sensitive Preamplifiers. In some very important applications using a capacitive source, the
input signal is delivered as a charge packet Qi . The signal source can be generally represented as a delta-
like current source Qi δ(t). Popular examples are detector systems for elementary-particle physics experiments
(18,19) and spectrophotometers and vision systems based on photodiodes operating in the storage mode (20).
The basic scheme (Fig. 10) is substantially the same as the previous one. The readout amplifier, generally
referred to as a charge-sensitive amplifier, produces an output voltage step with an amplitude equal to −Qi Cf in
response to an input charge packet Qi ; dc stabilization is generally obtained either with a very large feedback
resistor or with a feedback switch SR , which is turned on during suitable reset time intervals.
The above noise-matching considerations still apply (in particular, the relationships obtained for the
optimal input capacitance of the amplifier). In these applications, noise performance is usually expressed in
terms of equivalent noise charge (ENC). This is defined as the charge which the detector must deliver to
the amplifier input in order to achieve unity signal-to-noise ratio at the output, and is usually expressed in
electrons.
Detectors for nuclear physics experiments represent a very critical application of charge-sensitive am-
plifiers. Here, the amplifier is generally followed by a noise-shaping filter (or “pulse shaper”), which has the
purpose of optimizing the overall signal-to-noise ratio of the detector system. This is required as, in general,
electronic noise sets the limit to the accuracy of these systems. The best achievable value of ENC increases,
with a substantially linear relationship, with increasing detector capacitance Cs (in fact, a larger Cs leads to a
larger equivalent noise charge for the same equivalent input noise). The obtained values of ENC ranges from
18 PREAMPLIFIERS

few electrons for Cs < 1 pF (pixel detectors), to hundreds of electrons for microstrip detectors, up to thousands
of electrons for calorimeter detectors (Cs in the order of several hundred or even more than 1000 pF).
In some applications, junction field-effect transistors (JFET) are preferred in front-end electronics for
ionization detectors of capacitive nature, mainly because they show better radiation tolerance with respect to
MOS devices and much smaller input current as compared to BJTs (21,22). Nevertheless, under particular
operating conditions, such as very short shaping time (<50 ns) and low-power constraints, BJTs can offer
superior performance (23,24). CMOS solutions have also been developed for readout electronics to exploit the
capability of CMOS technology for very high integration density and low power consumption (3,25). In fact, as a
huge number of read-out channels are needed in modern detector systems, small size and low power dissipation
are also important requirements, which make the monolithic approach the most appealing solution. CMOS
technology is very attractive, especially for detectors that are placed not very close to the radiation environment
and use a pulse shaper with a very fast response (i.e., short peaking time), so that flicker noise is negligible with
respect to thermal noise. A BiCMOS solution implementing a low-power high-gain transresistance amplifier
has also been presented (26).
Preamplifiers for Inductive Sources. An inductive sensor source can be generally modeled as a
current source in parallel with an inductance. An internal resistance can also be present, to account for
the real part of the sensor impedance. Examples of inductive sensors include magnetic heads (e.g., for tape
and video cassette recorders), inductive pick-ups, dynamic microphones, ferrite antennas, and so forth. The
operation principle of such sensors is to convert the information, received in the form of an electromagnetic
field, into an electrical signal by means of an inductive coil. In most cases, very weak signals are generated and,
therefore, very severe noise specifications have to be met by the preamplifier. Obviously, the reactive elements
in the circuit do not contribute any noise directly, however, their presence affects the noise behavior of the
circuit.
Very different situations occur when narrow-band and wide-band applications are considered. A typical
preamplifier topology for narrow-band inductive signal sources is illustrated in Fig. 11, where equivalent input
noise generators are also shown. Lp is the source inductance, Rs is the sensor resistance, Rb can be a biasing or
a load resistor, and Cp is a shunt capacitance (including both parasitic and, in this case, added capacitances).
Cc is a dc decoupling capacitor (Cc  Cp ), and will be regarded as a short circuit in the frequency band of
interest. The voltage signal at the amplifier input turns out to be equal to:

where RT = Rb Rs . The presence of the resonance due to the group Lp Cp is apparent.
For this configuration, one can choose a suitable size of the shunt capacitance Cp to obtain the best noise
matching (6). In fact, the expression of the equivalent input noise current for the circuit in Fig. 11 is easily
calculated as:

Each noise current source reflects unchanged to the input at any frequency. By contrast, the coefficient of the
noise voltage contribution is frequency dependent, and turns out to be minimum at the resonant frequency
ωo = 1/(Lp Cp )1/2 . This behavior obviously derives from the large impedance shown by the parallel group Lp Cp
 PREAMPLIFIERS 19

Fig. 11. Basic topology of a preamplifier for a narrow-band inductive source (shunt capacitance Cp includes both parasitic
and, in this case, added capacitances).

at the resonance frequency. Neglecting the correlation effect between V n,a and In,a , the resulting equivalent
input noise current is given by I2 n,eq = I2 n,s + I2 n,b + I2 n,a + V 2 n,a /R2 T . It should be pointed out that no reactive
element appears in the expression for minimum noise.
Let us now turn our attention to wide-band applications, where a flat response is required for the signal.
The amplifier configuration in Fig. 11 can no longer be used, as the resonant group inherently provides narrow-
band signal response. To overcome this limitation, a constant transimpedance topology can be used, as shown
in Fig. 12. The voltage across the group Lp Cp is ideally maintained constant, regardless of signal amplitude
and frequency, thereby preventing any resonance effect. The current Is delivered by the sensor is injected into
Rf , thus achieving the desired frequency-independent transfer gain: V o /Is = −Rf . The equivalent input noise
current in this topology turns out to be:

The noise contributed by the amplifier is represented by the terms including In,a and V n,a . The use of a large
inductance Lp reduces the contribution of V 2 n,a . This is especially true at low frequencies, where ω2 Lp Cp  1.
By contrast, at high frequencies, a small value of Cp helps to achieve low noise.
For practical cases, when very low noise is required, the term I2 n,f = 4KT/Rf due to the feedback resistor
can result too high, thus setting too large a noise floor to the structure. To reduce this contribution, a combined
capacitive and resistive feedback configuration has been proposed, as shown in Fig. 13 (27). The transimpedance
gain of this structure is equal to −[1 + jω(C1 + C2 )Rf ]/jωC1 , which for the frequency range ω  1/[(C1 + C2 )Rf ]
can be approximated by −Rf (C1 + C2 )/C1 and, hence, achieves the required frequency independence. Obviously,
a careful stability analysis is required when designing the amplifier for this feedback configuration. The input-
referred noise current due to the feedback network turns out to be I2 n,f [C1 /(C1 + C2 )]2 , and is, therefore, reduced
by a factor of (1 + C2 /C1 )2 , with respect to the noise generated by the feedback resistor. To obtain a substantial
noise reduction, C2 is set much larger than C1 and, hence, the reduction factor becomes ∼(C2 /C1 )2 . In practice,
to achieve any given transimpedance gain, we now use a resistor which is C2 /C1 times smaller than in the
case of a conventional transimpedance topology using a purely resistive feedback. Its current noise I2 n,f is,
therefore, larger by the same factor, however, its input-referred contribution is divided by a factor of (C2 /C1 )2
20 PREAMPLIFIERS

Fig. 12. A transimpedance configuration for an inductive source ensures frequency-independent gain.

Fig. 13. The use of a combined resistive and capacitive feedback in a transimpedance amplifier minimizes the noise
contribution of the feedback network.

and, therefore, a substantial improvement (by a factor of C2 /C1 ) is achieved. It should be noted that with this
assumption (C2  C1 ), the resonance frequency in the input network is approximately equal to ωLC = 1/[Lp (Cp
+ C1 )]1/2 .
When a bipolar input transistor is used in the amplifier, the correlation term in Eq. (29) can be neglected,
and noise minimization requires a small base resistance rb and a large current gain β. Moreover, as in the
case of a capacitive signal source, the collector current IC must be set to an optimal value, as a consequence
of its opposite effects on input voltage and current noise components. Again, this optimal current is frequency
 PREAMPLIFIERS 21

dependent, and therefore noise optimization cannot be obtained in a wide frequency range (3,27), leading to
the choice of a trade-off current for any given application.
When using CMOS technology, no noise contribution due to the gate current is present, thus removing
the basic limiting factor to the noise performance in bipolar preamplifiers (i.e., the base shot noise component).
As for the case of capacitive signal sources, it can be shown that noise optimization is achieved by suitably
sizing the input transistor of the preamplifier. Again, the optimal size is different when considering flicker and
thermal noise. Furthermore, as a consequence of the frequency dependence of the coefficient of V 2 n,a in the
expression of the total equivalent input noise current [see Eq. (29)], the optimal transistor size also depends
on frequency, in contrast with the case of preamplifiers for capacitive sources. For frequencies much lower
than the resonance frequency ωLC , optimization is achieved by choosing an amplifier input capacitance Ci ∼ =
1/(ω2 Lp ) for both flicker and thermal noise (3). For ω > ωLC , wide-band noise optimization can be obtained by
setting Ci = ∼(CP + C1 )/3 and Ci = ∼(CP + C1 ) in the thermal and flicker noise domain, respectively. Both noise
components must be taken into account when determining the input transistor size for any given application,
which can be done by using numerical simulation.
Also in the case of wide-band preamplifiers for inductive sources, a detailed noise analysis (3) shows that,
in spite of the presence of a large flicker noise component, CMOS technology leads to better noise performance
than the bipolar one. Again, BiCMOS technology has been proposed to exploit the advantages coming from
integrating both CMOS and bipolar devices in the same chip, even though at an increased cost of the fabrication
process.

BIBLIOGRAPHY

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3. Z. Y. Chang W. M. C. Sansen Low-Noise Wide-Band Amplifiers in Bipolar and CMOS Technologies, Norwell, MA:
Kluwer, 1991.
4. IRE Subcommittee on Noise, IRE standards on methods of measuring noise in linear two ports, 1959 (IRE Standard
59 IRE 20. S1), Proc. IRE, 48: 60–68, 1960.
5. Y. Netzer A new interpretation of noise reduction by matching, Proc. IEEE, 62: 404–406, 1974.
6. Y. Netzer The design of low-noise amplifiers, Proc. IEEE, 69: 728–741, 1981.
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Signal Process., 1: 9–19, 1991.
8. J. G. Graeme Photodiode Amplifiers: Opamp Solutions, New York: McGraw-Hill, 1996.
9. D. J. T. Heatley Optical Receivers, in J. E. Franca and Y. Tsividis (eds.), Design of Analog-Digital VLSI Circuits for
Telecommunications and Signal Processing, 2nd ed., Englewood Cliffs, NJ: Prentice-Hall, 1994.
10. J. Silva-Martı́nez J. Salcedo-Suñer A CMOS preamplifier for electret microphones, Proc. 1995 IEEE Int. Symp. Circuits
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11. J. F. Duque-Carrillo et al. VERDI: An acoustically programmable and adjustable CMOS mixed-mode signal processor
for hearing aid applications, IEEE J. Solid-State Circuits, SC-31: 634–645, 1996.
12. B. Stefanelli et al. A very low-noise CMOS preamplifier for capacitive sensors, IEEE J. Solid-State Circuits, SC-28:
971–978, 1993.
13. A. C. Pluygers A novel microphone preamplifier for use in hearing aids, Analog Integr. Circuits Signal Process., 3:
113–118, 1993.
14. L. Fasoli M. Sampietro Criteria for setting the width of CCD front end transistor to reach minimum pixel noise, IEEE
Trans. Elec. Dev., ED-43: 1073–1076, 1996.
15. J.-C. Bertails Low-frequency noise considerations for MOS amplifier design, IEEE J. Solid-State Circuits, SC-14:
773–776, 1979.
16. E. A. Vittoz The design of high-performance analog circuits on digital CMOS chips, IEEE J. Solid-State Circuits, SC-20:
657–665, 1985.
22 PREAMPLIFIERS

17. K. R. Laker W. Sansen Design of Analog Integrated Circuits and Systems, New York: McGraw-Hill, 1994.
18. E. Gatti P. F. Manfredi Processing the signals from solid-state detectors in elementary particle physics, La Rivista del
Nuovo Cimento, 1, serie 3, 1986.
19. V. Radeka Low-noise techniques in detectors, Ann. Rev. Nucl. Part. Sci., 38: 217–277, 1988.
20. A. Sartori et al. A 2-D photosensor array with integrated charge amplifier, Sensors and Actuators A. Physical, 46–47:
247–250, 1995.
21. G. Bertuccio A. Pullia A low noise silicon detector preamplifier system for room temperature X-ray spectroscopy, Proc.
Symp. Semicon. Room-Temperature Radiation Detector Appl. Mater. Res. Soc. Symp. Proc., 302: 1993, pp. 597–603.
22. G. Bertuccio A. Pullia G. De Geronimo Criteria of choice of the front-end transistor for low-noise preamplification of
detector signals at sub-microsecond shaping times for X- and γ-ray spectroscopy, Nucl. Instr. Meth. Phys. Res., A 380:
301–307, 1996.
23. E. Gatti A. Hrisoho P. F. Manfredi Choice between FETs or bipolar transistors and optimization of their working points
in low-noise preamplifiers for fast pulse processing: Theory and experimental results, IEEE Trans. Nucl. Sci., 30:
319–323, 1983.
24. G. Bertuccio L. Fasoli M. Sampietro Design criteria of low-power low-noise charge amplifiers in VLSI bipolar technology,
IEEE Trans. Nucl. Sci., 44: 1708–1718, 1997.
25. I. Kipnis et al. A time-over-threshold machine: The readout integrated circuit for the BABAR silicon vertex tracker,
IEEE Trans. Nucl. Sci., 44: 289–297, 1997.
26. J. Wulleman A low-power high-gain transresistance BiCMOS pulse amplifier for capacitive detector readout, IEEE J.
Solid-State Circuits, SC-32: 1181–1191, 1997.
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J. F. DUQUE-CARRILLO
University of Extremadura
GUIDO TORELLI
University of Pavia
POWER SYSTEM ON-LINE TRANSIENT STABILITY
ASSESSMENT
INTRODUCTION
Recent major blackouts in North America and Europe
vividly demonstrated that power interruptions or black-
outs can significantly impact the economy and are not ac-
ceptable to society. And yet, the ever increasing loading
of transmission networks coupled with a steady increase
in load demands have pushed the operating conditions of
many power systems worldwide ever closer to their stabil-
ity limits. The combination of limited investment in new
transmission and generation facilities, new regulatory re-
quirements for transmission open access, and environmen-
tal concerns are forcing transmission networks to carry
more power than they were designed to withstand. This
problem of reduced operating security margins is being fur-
ther compounded by factors such as (1) the increasing num-
ber of bulk power interchange transactions and non-utility
generators, and (2) the trend toward installing higher out-
put generators with lower inertia constants and higher
short-circuit ratios. Under these conditions, it is now well
recognized that any violation of power system dynamic se-
curity limits leads to far-reaching consequences for the en-
tire power system.
By nature, a power system continually experiences two
types of disturbances: event disturbances and load vari-
ations. Event disturbances (contingencies) include loss of
generating units or transmission components (lines, trans-
formers, substations) from short-circuits caused by light-
ning, high winds, failures such as incorrect relay opera-
tions or insulation breakdown, sudden large load changes,
or a combination of such events. Event disturbances usu-
ally lead to a change in the network configuration of the
power system caused by actions from protective relays and
circuit breakers. They can occur in the form of a single
equipment (or component) outage or in the form of multi-
ple simultaneous outages when taking relay actions into
account. Load variations, on the other hand, are variations
in load demands at buses and/or power transfers among
buses. The network configuration may remain unchanged
after load variations.
Power systems are planned and operated to with-
stand the occurrence of certain disturbances. The North
American Electric Reliability Council defines security as
the ability to prevent cascading outages when the bulk
power supply is subjected to severe disturbances. The
specific criteria that must be met are set by individual
reliability councils. Each council establishes the types
of disturbances that its system must withstand without
cascading outages.
A major activity in power system planning and opera-
tions is to examine the impact of a set of credible distur-
bances on power system dynamic behaviors such as sta-
bility. Power system stability analysis is concerned with a
power system’s ability to reach an acceptable steady state
(operating condition) after a disturbance. Stability analy-
sis is one of the most important tasks in power system op-
J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright © 2007 John Wiley & Sons, Inc.
erations and planning. Today, stability analysis programs
are being used by power system planning and operating
engineers to simulate the response of the system to var-
ious credible disturbances. In these simulations, the dy-
namic behavior of a current or proposed power system is
examined to determine whether stability has been main-
tained or lost after the contingency. For operational pur-
poses, power system stability analysis plays an important
role in determining the system operating limits and oper-
ating guidelines. During the planning stage, power system
stability analysis is performed to check relay settings, to
set the parameters of control devices, or to assess the need
for additional facilities and the locations at which to place
additional control devices in order to enhance the system’s
static and dynamic security. Important conclusions and de-
cisions about power system operations and planning are
made based on the results of stability studies.
Transient stability problems, a class of power system
stability problems, have been a major operating constraint
in regions that rely on long-distance transfers of bulk
power (e.g., in most parts of the Western Interconnection
of the United States., Hydro Quebec, the interfaces be-
tween Ontario and the New York area and the Manitoba/
Minnesota area, and in certain parts of China and Brazil).
The trend now, with increased instances and total volume
of bulk power transfer, is that many parts of the vari-
ous interconnected systems are becoming constrained by
transient stability limitations. The wave of recent changes
has greatly increased the adverse effect of both event dis-
turbances and load variations on power system stability.
Hence, it is imperative to develop powerful tools to exam-
ine power system stability in a timely and accurate manner
and to derive necessary control actions for both preventive
control and enhancement control.
On-line transient stability assessment (TSA) is an
essential tool needed to avoid any violation of dynamic se-
curity limits. Indeed, with current power system operating
environments, it is increasingly difficult for power system
operators to generate all operating limits for all possible
operating conditions under a list of credible contingencies.
Hence, it is imperative to develop a reliable and effective
on-line TSA to obtain the operating security limits at or
near real time. In addition to this important function,
power system transmission open access and restructuring
further reinforce the need for an on-line TSA as it is
the base upon which determination of available transfer
capability and dynamic congestion management problems
and coordination of special protection systems can be
effectively resolved.
Significant engineering and financial benefits are ex-
pected from an on-line TSA. First, one may be able to op-
erate a power system with operating margins reduced by
a factor of 10 or more if the transient stability assessment
is based on the actual system configuration and operating
conditions, instead of assumed worst-case conditions, as is
done in off-line studies. A second benefit of on-line analysis
is that the analysis can be reduced to those cases relevant
to actual operating conditions, thereby obtaining more ac-
curate operating margins, allowing more power transfer,
and freeing engineering resources for other critical activi-
ties.
2 Power System On-Line Transient Stability Assessment
Modern energy management systems periodically per-
form the tasks of on-line power system static security as-
sessment and control for ensuring the ability of the power
system to withstand a set of credible contingencies (dis-
turbances). The assessment involves the selection of the
set of credible contingencies and then the evaluation of the
system’s response to contingencies. Various software pack-
ages for security assessment and control have been im-
plemented in modern energy control centers. These pack-
ages provide comprehensive on-line security analysis and
control based almost exclusively on steady-state analysis,
making them applicable only to static security assessment
and control [1].
From a computational viewpoint, on-line TSA requires
the handling of a large set of mathematical models, which is
described by a large set of nonlinear differential equations
in addition to the nonlinear algebraic equations involved
in the static security assessment. The computational ef-
fort required by on-line TSA is roughly three magnitudes
higher than that for the static security assessment (SSA).
This result explains why TSA has long remained an off-line
activity instead of on-line activity in the energy manage-
ment system. Extending the functions of energy manage-
ment systems to take account of on-line TSA and control
is a rather challenging task and requires several break-
throughs in measurement systems, analysis tools, compu-
tation methods, and control schemes.
Currently, stability analysis programs routinely used in
utilities around the world are based mostly on step-by-step
numerical integrations of power system stability models
to simulate system dynamical behaviors. This practice of
power system stability analysis based on the time-domain
approach has a long history [1–12]. However, because of the
nature of the time-domain approach, it has several disad-
vantages: (1) It requires intensive, time-consuming compu-
tation efforts; therefore, it has not been suitable for on-line
application; (2) it does not provide information as to how
to derive preventive control when the system is deemed
unstable and how to derive enhancement control when the
system is deemed critically stable; and (3) it does not pro-
vide information regarding the degree of stability (when
the system is stable) and the degree of instability (when
the system is unstable). This piece of information is valu-
able for both planning and operations.
An alternative approach to transient stability analy-
sis employing energy functions, called direct methods, was
originally proposed by Magnusson [13] in the late 1940s
and was pursued in the 1950s by Aylett [14]. Direct meth-
ods have a long development history spanning six decades.
Significant progress, however, has been made recently in
the practical application of direct methods to transient sta-
bility analysis. Direct methods can determine transient
stability without the time-consuming numerical integra-
tion of the (post-fault) power system [15–18]. In addition to
its speed, direct methods also provide a quantitative mea-
sure of the degree of system stability. This additional in-
formation makes direct methods very attractive when the
relative stability of different network configuration plans
must be compared or when system operating limits con-
strained by transient stability must be calculated quickly.
Another advantage of direct methods is the ability to pro-
vide useful information regarding how to derive preven-
tive control actions when the underlying power system is
deemed unstable and how to derive enhancement control
actions when the underlying power system is deemed crit-
ically stable.
After decades of research and developments in the
energy-function-based direct methods and the time-
domain simulation approach, it has become clear that the
capabilities of direct methods and that of the time-domain
approach complement each other. The current direction of
development is to include appropriate direct methods and
time-domain simulation programs within the body of over-
all power system stability simulation programs [19–22].
For example, the direct method provides the advantages of
fast computational speed and energy margins, which make
it a good complement to the traditional time-domain ap-
proach. The energy margin and its functional relations to
certain power system parameters are an effective comple-
ment to develop tools such as preventive control schemes
for credible contingencies that are unstable and to develop
fast calculators for available transfer capability limited by
transient stability. The direct method can also play an im-
portant role in the dynamic contingency screening for on-
line transient stability assessment.
PROBLEM FORMULATION AND SYSTEM MODEL
Electric power systems are nonlinear in nature. Their non-
linear behaviors are difficult to predict because of (1) the
extraordinary size of the systems, (2) the nonlinearity in
the systems, (3) the dynamical interactions within the sys-
tems, and (4) the complexity of its component modeling.
These complicating factors have forced power system en-
gineers to analyze the complicated behaviors of power sys-
tems through the process of modeling, simulation and val-
idation.
The complete power system model for calculating sys-
tem dynamic response relative to a disturbance comprises
a set of first-order differential equations
ẋ = f (x, y, u) (1)
describing the internal dynamics of devices such as
generators, their associated control systems, certain loads
and other dynamically modeled components, and a set of
algebraic equations
0 = g(x, y, u) (2)
describing the electrical transmission system (the inter-
connections between the dynamic devices) and internal
static behaviors of passive devices (such as static loads,
shunt capacitors, fixed transformers, and phase shifters).
The differential equations (1) typically describe the dy-
namics of the speed and angle of generator rotors; the flux
behaviors in generators; the response of generator control
systems such as excitation systems, voltage regulators,
turbines, governors, and boilers; the dynamics of equip-
ment such as synchronous VAR compensators (SVCs),
DC lines, and their control systems; and the dynamics
of dynamically modeled loads such as induction motors.
The stated variables x typically include generator rotor

angles, generator velocity deviations (speeds), mechanical
powers, field voltages, power system stabilizer signals,
various control system internal variables, and voltages
and angles at load buses (if dynamic load models are
employed at these buses). The algebraic equations (2)
comprise the stator equations of each generator, the
network equations of transmission networks and loads,
and the equations defining the feed-back stator quantities.
An aggregated representation of each local distribution
network is usually used in simulating power system
dynamical behaviors. The forcing functions u acting on the
differential equations are terminal voltage magnitudes,
generator electrical powers, and signals from boilers and
automatic generation control systems.
Some control system internal variables have upper
bounds on their values because of their physical satura-
tion effects. Let z be the vector of these constrained state
variables; then the saturation effects can be expressed as
0 < z(t) ≤ z̄
A detailed description of equations (1)–(3) for each com-
ponent can be found, for example, in Refs. 3 and 4. For
a 900-generator, 14,000-bus power system, the number of
differential equations can easily reach as many as 20,000,
whereas the number of nonlinear algebraic equations can
easily reach as many as 32,000. The sets of differential
equations (1) are usually loosely coupled.
To protect power systems from damage caused by distur-
bances, protective relays are placed strategically through-
out a power system to detect faults (disturbances) and to
trigger the opening of circuit breakers necessary to iso-
late faults. These relays are designed to detect defective
lines and apparatus or other power system conditions of
an abnormal or dangerous nature and to initiate appropri-
ate control circuit actions. Because of the action of these
protective relays, a power system subject to an event dis-
turbance can be viewed as going through changes in its
network configuration in three stages: from the pre-fault,
to the fault-on, and finally to the post-fault system. The
pre-fault system is in a stable steady state; when an event
disturbance occurs, the system then moves into the fault-
on system before it is cleared by protective system oper-
ations. Stated more formally, in the pre-fault regime, the
system is at a known stable equilibrium point (SEP), say
(xspre , yspre ). At some time t0 the system undergoes a fault (an
event disturbance), which results in a structural change in
the system caused by actions from relay and circuit break-
ers. Suppose the fault duration is confined to the time in-
terval [t0 , tcl ]. During this interval, the fault-on system is
described by (for ease of exposition, the saturation effects
expressed as 0 < z(t) ≤ z̄ are neglected in the following):
ẋ = f F (x, y) t0 ≤ t < tcl
0 = gF (x, y)
where x(t) is the vector of state variables of the system at
time t. Sometimes, the fault-on system may involve more
than one action from system relays and circuit breakers. In
these cases, the fault-on systems are described by several
Power System On-Line Transient Stability Assessment 3
Figure 1. The simulated dynamical behavior, pre-fault, fault-on,
and post-fault of a generator’s angle of a large power system model.
sets of nonlinear equations:
ẋ = f 1F (x, y), t0 ≤ t ≤ tF,1
(3)
0 = gF1 (x, y)
ẋ = f kF (x, y), tF,1 ≤ t ≤ tF,2
0 = gF2 (x, y) (5)
···
ẋ = f kF (x, y), tF,k ≤ t ≤ tcl
0 = gFk (x, y)
The number of sets of equations equals the number of sepa-
rate actions from system relays and circuit breakers. Each
set depicts the system dynamics caused by one action from
relays and circuit breakers. Suppose the fault is cleared
at time tcl and no additional protective actions occur after
tcl . The system, termed the post-fault system, is henceforth
governed by post-fault dynamics described by
ẋ = f PF (x, y), tcl ≤ t < ∞
(6)
0 = gPF (x, y)
The network configuration may or may not be the same as
the pre-fault configuration in the post-fault system. We will
use the notation z(tcl ) = (x(tcl ), y(tcl )) to denote the fault-on
state at switching time tcl The post-fault trajectory after an
event disturbance corresponds to the solution of equation
(5) over the fault-on time period t0 ≤ t < tcl and the solution
of equation (6) over the post-fault time period tcl ≤ t < t∞ .
The fundamental problem of power system stability
caused by a fault (i.e., a contingency) can be roughly stated
as follows: Given a pre-fault SEP and a fault-on system,
will the post-fault trajectory settle down to an acceptable
steady state [18]? A simulated system trajectory starting
from a pre-fault SEP, fault-on trajectory and post-fault tra-
jectory, is shown in Figs. 1 and 2.
The two sets of equations (1) and (2) describing power
system dynamic response relative to a contingency are
fairly complex, because electric power systems comprise
a large number of components (equipment and control
devices) interacting with each other, exhibiting nonlinear
(4)
dynamic behaviors with a wide range of time scales. The
dynamic behavior after a disturbance involves all system
components, to varying degrees. The degree of involvement
from each component determines the appropriate system
model necessary for simulating the dynamic behaviors.
Traditional practice in power system analysis has been to
4 Power System On-Line Transient Stability Assessment

Figure 2. The simulated dynamical behavior, pre-fault, fault-on,

and post-fault of a voltage magnitude of a large power system
model. During the fault, the voltage magnitude drops to about
0.888 p.u.

use the simplest acceptable system model that captures

the essence of the phenomenon under study. A logic com-
monly used in power system dynamic simulations is that
the effect of a system component or control device can be
neglected when the time scale of its response is very small
or very large compared with the time period of interest
and, hence, can be considered in quasi-steady state. This
philosophy has been deemed acceptable because of the
severe complexity involved with a full large-scale power
system model.
Based on the different time-scale involvement of each
component and control device on the overall system dy-
namic behaviors, power system models have been divided
into three models with different time scales: (1) short-
term stability model (predominately describing electro-
mechanical transients) on which transient stability is
based, (2) extended transient and mid-term stability
model, and (3) long-term stability model on which long-
term stability is based. These three models are described
by a set of differential-algebraic equations of the same na-
ture as equations (1) and (2) but with different sets of state
variables with different time constants. However, a “fuzzy”
boundary distinguishes between the mid-term and long-
term model. Compared with transient stability analysis,
mid-term and long-term dynamic behaviors have only come
under study relatively recently [3,4,23]. For transient sta-
bility analysis, the assumption of one unique frequency is
kept for the transmission network model, but generators
have different speeds. Generators are modeled in greater
detail, with shorter time constants compared with the mod-
els used in long-term stability analysis. Roughly speaking,
transient stability models reflect the fast-varying system
electrical components and machine angles and frequencies,
whereas the long-term models are concerned with the rep-
resentation of the slow oscillatory power balance, assuming
that the rapid electrical transients have damped out.
ON-LINE TSA
On-line TSA is designed to provide system operators with
critical information, including, (1) the transient stability
of the system subject to a list of contingencies and (2)
Figure 3. An architecture for on-line transient stability assess-
ment and control.
available (power) transfer limits at key interfaces subject
to transient stability constraints. An integrated architec-
ture for on-line TSA and control is presented in Fig. 3. In
this architecture, there are two major components in the
on-line TSA module: dynamic contingency screening and a
fast time-domain stability program for performing detailed
stability analysis. Several systems have been developed in-
tended for on-line TSA [24–29].
When a new cycle of TSA is warranted, a list of credible
contingencies, along with information from the state esti-
mator and topological analysis, are applied to the dynamic
contingency screening program whose basic function is to
screen out contingencies that are definitely stable or po-
tentially unstable. Contingencies that are classified to be
definitely stable are eliminated from additional analysis.
Contingencies that are classified to be potentially unsta-
ble are sent to fast time-domain simulation for detailed
analysis. It is the ability to perform dynamic contingency
screening on a large number of contingencies and to filter
out a much smaller number of contingencies requiring ad-
ditional analysis that makes on-line TSA feasible. Contin-
gencies that are either undecided or identified as unstable
are then sent to the time-domain transient stability simu-
lation program for detailed stability analysis.
The block function of control actions decisions deter-
mines whether timely post-fault contingency corrective

actions such as automated remedial actions are feasible
to steer the system from unacceptable conditions to an
acceptable state. If appropriate corrective actions are not
available, the block function of preventive actions deter-
mines the required pre-contingency preventive controls
such as real power redispatches or line switching to main-
tain the system stability should the contingency occur. If
the system will be marginally stable; i.e., critically stable,
the block function of enhancement actions determines the
required pre-contingency enhancement controls such as
real power redispatches or line switching to increase the
degree of system stability should the contingency occur.
In this architecture, a fast and yet reliable method for
performing dynamic contingency screening plays a vital
role in the overall process of on-line TSA.
Two types of basic information are needed to perform
power system on-line TSA: static data (which is the power
flow data) and dynamic data. The power flow data de-
scribe the network and its steady-state operating condi-
tions, which corresponds to a real-time system condition
captured by the EMS and solved by state estimators. The
dynamic data supply the information needed to compute
the response of the modeled devices to a given distur-
bance, which refers to dynamic models and data matching
the real-time power flow. The dynamic data include mod-
els of detailed synchronous machines, dynamic load mod-
els, induction motor, static VAR compensator, high-voltage
DC link, FACTS, and user-defined models. Another set of
data, sequence network data, is required only if unbalanced
faults are to be simulated. This set of data contains the
negative and zero sequence network data compatible with
power flow data.
In addition to the above basic information, the following
additional information is needed:

Description of disturbances: this information de-
scribes the disturbance to be simulated, e.g., fault
location and duration, circuit switching, or genera-
tion/load rejection.

Relay data: These data describe the characteristics of
the protection devices.
A complete on-line TSA assessment cycle will be com-
pleted within, say, 15 minutes. This cycle starts when all
necessary data are available to the system and ends when
the system is ready for the next cycle. Depending on the
size of the underlying power system, it is estimated that,
for a large-size power system such as 15,000-bus power
system, the number of contingencies in a contingency list
is between 1000 and 3000. The contingency types will in-
clude both three-phase faults with primary clearance and
single-line-to-ground faults with backup clearance.
The outputs of on-line TSA in a given cycle include the
following:

Overall status of the system (secure or insecure and
the operating margin).

Unstable contingencies (contingency details such as
fault type, fault location, and circuits lost).
Power System On-Line Transient Stability Assessment 5

Stability margin in terms of energy margin, or op-
erating margin in MW and/or MVar for each unsta-
ble contingency and may include preventive control
actions.

Detailed time-domain responses (swing curves) of
user-specified quantities for potentially unstable con-
tingencies.

Critical contingencies (contingency details such as
fault type, fault location, and circuits lost).

Stability margin in terms of energy margin, or operat-
ing margin in MW and/or MVar for each critical con-
tingency and may include enhancement control ac-
tions.

Detailed time-domain responses (swing curves) of
user-specified quantities for critical contingencies.

If transfer limits are computed, limits (or security
boundary) at key interfaces, and the limiting contin-
gencies.
In addition to the above main functions, the on-line TSA
system should have the following functions:

A study mode with which the users, such as relia-
bility engineers, can analyze various scenarios using
cases archived from real-time system models or cre-
ated from operational planning studies.

Software and hardware failover protection.

Interfaces with EMS functions.

Definition of contingency list and creation of neces-
sary data for stability analysis, data validation and
correction (option), and output visualization.
DYNAMIC CONTINGENCY SCREENING
The strategy of using an effective scheme to screen out a
large number of stable contingencies and capture critical
contingencies and to apply detailed simulation programs
only to potentially unstable contingencies is well recog-
nized. This strategy has been successfully implemented in
on-line SSA. The ability to screen several hundred contin-
gencies to capture tens of the critical contingencies has
made the on-line SSA feasible. This strategy can be ap-
plied to on-line TSA. Given a set of credible contingencies,
the strategy would break the task of on-line TSA into two
assessment stages [21, 31]:
Stage 1. Perform the task of dynamic contingency
screening to quickly screen out contingencies that
are definitely stable from a set of credible contingen-
cies.
Stage 2. Perform a detailed assessment of dynamic per-
formance for each contingency remaining in Stage 1.
Dynamic contingency screening is a fundamental func-
tion of an on-line TSA system. The overall computational
speed of an on-line TSA system depends greatly on the ef-
fectiveness of the dynamic contingency screening, the ob-
jective of which is to identify contingencies that are defi-
nitely stable and thereby avoid further stability analysis
6 Power System On-Line Transient Stability Assessment
for these contingencies. It is from the definite classification
of stable contingencies that considerable speed-up can be
achieved for transient stability assessment. Contingencies
that are either undecided, identified as critical, or unstable
are then sent to the time-domain transient stability simu-
lation program for additional stability analysis.
It is, hence, imperative that a dynamic contingency
screening program satisfies the following five require-
ments [31]:
1. Reliability measure: Absolute capture of unstable con-
tingencies as fast as possible; i.e., no unstable (single-
swing or multi-swing) contingencies are missed. In
other words, the ratio of the number of captured un-
stable contingencies to the number of actual unstable
contingencies is 1.
2. Efficiency measure: High yield of screening out stable
contingencies as fast as possible; i.e., the ratio of the
number of stable contingencies detected to the number
of actual stable contingencies is as close to 1 as possible.
3. On-line computation: Little need of off-line computa-
tions and/or adjustments in order to meet with the con-
stantly changing and uncertain operating conditions.
4. Speed measure: High speed, i.e., fast classification for
each contingency case.
5. Performance measure: Robust performance with respect
to changes in power system operating conditions.
The requirement of absolute capture of unstable con-
tingencies is a reliability measure for dynamic contingency
screening. This requirement is extremely important for on-
line TSA. However, it is from the nonlinear nature of the
dynamic contingency screening problem that this require-
ment can best be met by a reliable method such as one
with a strong analytical basis. The third requirement as-
serts that a desired dynamic contingency classifier is one
that relies or little or no off-line information, computations,
and/or adjustments. This requirement arises because, un-
der current and near future power system operating envi-
ronments, the correlation between on-line operational data
and presumed off-line analysis data can be minimal, or in
extreme cases, the two can be irrelevant to one another. In
other words, in a not-too-extreme case, off-line presumed
analysis data may become unrelated to on-line operational
data. This uncorrelated relationship is partly attributed
to the imminent bulk power transactions resulting from
deregulation. The first four requirements should not be de-
graded by different operating conditions as dictated by the
requirement for robust performance.
Several methods developed for on-line dynamic contin-
gency screening have been reported in the literature; see,
for example, [21, 31–33]. These methods can be categorized
as follows: the energy function approach, the time-domain
approach, and the artificial intelligence (AI) approach. The
time-domain approach involves the step-by-step simula-
tion of each contingency for a few seconds, say 2 or 3 sec-
onds, to filter out the very stable or very unstable contin-
gencies. This approach may suffer from an accuracy prob-
lem in identifying multi-swing stable or unstable contin-
gencies. The AI approaches, such as the pattern recognition
technique, the expert system technique, the decision tree
technique, and the artificial neural network approach, all
first perform extensive off-line numerical simulations aim-
ing to capture the essential stability features of the sys-
tem’s dynamic behavior. They then construct a classifier
attempting to correctly classify new, unseen on-line con-
tingencies. As such, the AI approach is likely to become
ineffective for on-line application to current or near-future
power systems if little correlation exists between on-line
operational data and presumed off-line analysis data. In
addition, the existing AI-based methods unfortunately fail
to meet the on-line computation requirement and cannot
guarantee the reliability requirement. In this regard, the
BCU classifiers can meet the requirements [21, 31].
DIRECT METHODS FOR TRANSIENT STABILITY
The direct method evolved in the last several decades.
The current direct method, the controlling unstable equi-
librium point (UEP) method, uses an algorithmic proce-
dure to determine, based on the energy function theory
and controlling UEP, whether the system will remain sta-
ble, without integrating the post-fault system [16, 17, 18].
The direct method assesses the stability property of the
post-fault trajectory, whose initial state is the system state
when the fault is cleared, by comparing the system energy
at the initial state of post-fault trajectory with a critical
energy value. The direct method not only avoids the time-
consuming numerical integration of the post-fault system
but also provides a quantitative measure of the degree of
system stability. The direct method has a solid theoretical
foundation [16, 17].
Given a power system transient stability model with
specified fault-on systems and a specified post-fault sys-
tem, direct methods for transient stability analysis consist
of four key steps:
Step 1. Construct an energy function for the post-fault
power system.
Step 2. Compute the energy immediately after the fault
clearing point is reached.
Step 3. Compute the critical energy for the fault-on tra-
jectory.
Step 4. Perform transient stability assessments by com-
paring the energy computed at Step 2 with the crit-
ical energy computed at Step 3. If the former is
smaller than the latter, then the post-fault trajectory
will be stable. Otherwise, it may be unstable.
In Step 4, direct methods determine whether a post-
fault power system will remain stable when the fault
is cleared solely by comparing the system energy (con-
structed in Step 1) immediately after the fault clearing
point is reached (computed in Step 2) with to a critical en-
ergy (computed in Step 3). It is hence very important to
correctly calculate critical energy values.
The theoretical basis of direct methods for the direct
stability assessment of a post-fault power system is the
knowledge of a stability region; if the initial condition of
the post-fault system lies inside the stability region of a

desired post-fault stable equilibrium point, then one can
ensure without performing numerical integrations that the
ensuing post-fault trajectory will converge to the desired
point. Therefore, the knowledge of the stability region plays
an important role in the theoretical foundation for direct
methods. A comprehensive theory of stability region can
be found in [30]. An overview of the energy function theory
for general nonlinear autonomous dynamical systems will
be presented. The energy function theory has been applied
to power system transient stability models to develop a
theoretical foundation for direct methods. We will also give
an overview of this development.
Several methods are proposed in the literature for deter-
mining the critical energy values. The classic method, the
closest UEP method proposed in the early 1970s, has been
found to yield unduly conservative results when applied
to power system transient stability analysis. The potential
energy boundary surface (PEBS) method [34] gives fairly
fast but inaccurate results (mostly overestimates). A de-
sirable method for determining the critical energy value
would be the one that can provide the most accurate ap-
proximation of the part of the stability boundary toward
which the fault-on trajectory is heading, even though it
might provide a very poor estimate of the other part of
the stability boundary. To this end, the controlling UEP
method, which uses the (connected) constant energy sur-
face passing through the controlling UEP to approximate
the relevant part of stability boundary, is the most promis-
ing method. The concept of controlling UEP and its theo-
retical basis will be presented in next section.
Energy Function Theory
We consider a general nonlinear autonomous dynamical
system described by the following equation:
ẋ(t) = f (x(t)) (7)
to be the power system model under study, where the state
vector x(t) belongs to the Euclidean space Rn , and the func-
tion f : Rn → Rn satisfies the sufficient condition for the
existence and uniqueness of solutions. A state vector x̂ is
called an equilibrium point of system (7) if ( f (x̂) = 0). We
say that an equilibrium point of (7) is hyperbolic if the
Jacobian of f (·) at x̂, denoted J f (x̂), has no eigenvalues
with a zero real part. For a hyperbolic equilibrium point, it
is an (asymptotically) stable equilibrium point if all eigen-
values of its corresponding Jacobian have negative real
parts; otherwise it is an unstable equilibrium point. If the
Jacobian of the equilibrium point x̂ has exactly one eigen-
value with a positive real part, we call it a type-one equi-
librium point. Likewise, x̂ is called a type-k equilibrium
point if its corresponding Jacobian has exactly k eigenval-
ues with positive real parts.
Let x̂ be a hyperbolic equilibrium point. Its stable and
unstable manifolds, W s (x̂) and W u (x̂), are defined as follows:
W s (x̂) := {x ∈ Rn :
t (x) → x̂ as t → ∞}
(8)
W u (x̂) := {x ∈ Rn :
t (x) → x̂ as t → − ∞}
Every trajectory in the stable manifold W S (x̂) converges to
x̂ as time goes to positive infinity, whereas every trajectory
in the stable manifold W u (x̂) converges to x̂ as time goes to
Power System On-Line Transient Stability Assessment 7
negative infinity. For a stable equilibrium point, it can be
shown that a number δ > 0 exists such that x0 − x̂ < δ im-
plies
t (x0 ) → x̂ as. If (t → ∞) is arbitrarily large, then x̂ is
called a global stable equilibrium point. Many physical sys-
tems contain multiple stable equilibrium points. A useful
concept for these kinds of systems is that of the stability
region (also called the region of attraction). The stability
region of a stable equilibrium point xs is defined as
A(xs ) := {x ∈ Rn : limt → ∞
t (x) = xs } (9)
From a topological point of view, the stability region A(xs )
is an open, invariant, and connected set. The boundary of
stability region A(xs ) is called the stability boundary of xs
and will be denoted by ∂A(xs ).
We say a function V : Rn → R is an energy function for
the system (7) if the following three conditions are satisfied:
1. The derivative of the energy function V (x) along any sys-
tem trajectory x(t) is nonpositive, i.e.,
V̇ (x(t)) ≤ 0 (10)
2. If x(t) is a nontrivial trajectory, i.e., x(t), is not an equi-
librium point, then, along the nontrivial trajectory x(t),
the set
{t ∈ R : V̇ (x(t)) = 0} (11)
has measure zero in R.
3. That a trajectory x(t) has a bounded value of V (x(t)) for
t ∈ R+ implies that the trajectory x(t) is also bounded.
Stating this in brief:
That V (x(t)) is bounded implies x(t) is also
bounded.
Property (1) states that the energy function is nonin-
creasing along its trajectory, but it does not imply that
the energy function is strictly decreasing along its trajec-
tory. A time interval [t1 , t2 ] may exist such that V̇ (x(t)) = 0
for t ∈ [t1 , t2 ]. Properties (1) and (2) imply that the energy
function is strictly decreasing along any system trajectory.
Property (3) states that the energy function is a proper map
along any system trajectory but need not be a proper map
for the entire state space. Recall that a proper map is a
function f : X → Y such that for each compact set (D ∈ Y ),
the set f −1 (D) is compact in X. Property (3), which can be
viewed as a “dynamic” proper map, is useful in the charac-
terization of stability boundary. From the above definition
of energy function, it is obvious that an energy function
may not be a Lyapunov function.
In general, the dynamic behaviors of trajectories of
general nonlinear systems could be very complicated; the
asymptotic behaviors of trajectories can be quasi-periodic
trajectories or even chaotic trajectories [35, 41]. If the un-
derlying dynamical system has some special properties,
then the system may admit only simple trajectories. For
instance, every trajectory of system (7) having an energy
function has only two modes of behaviors: Its trajectory ei-
ther converges to an equilibrium point or goes to infinity
(becomes unbounded) as time increases or decreases and
8 Power System On-Line Transient Stability Assessment
the stability region of the system can be completely charac-
terized. These results are shown in the following theorems:
Theorem 1: [16, 17] (Global behavior of trajectories). If a
function exists satisfying condition (1) and condition (2) of
the energy function for general nonlinear system (7), then
every bounded trajectory of system (7) converges to one of
the equilibrium points.
Theorem 2: [16, 17] (Energy function and stability
boundary). If an energy function exists for the system (7),
which has an asymptotically stable equilibrium point xs
(but not globally asymptotically stable), then the stability
boundary ∂A(xs ) is contained in the set, which is the union
of the stable manifolds of the UEPs on the stability bound-
ary ∂A(xs ); i.e.,
∂A(xs ) Ⲵ ∪ W s (xi )
xi ∈ {E ∩ ∂A(xs )}
Theorem 2 offers a means for completely characterizing
the stability boundary of the class of nonlinear dynami-
cal systems having energy functions: The stability bound-
ary ∂A(xs ) is contained in the union of the stable mani-
folds of the UEPs on the stability boundary. These stable
manifolds govern the dynamical behaviors on the stabil-
ity boundary. This theorem leads to the development of a
theoretical foundation for direct methods.
The energy function theory presented above is appli-
cable to transient stability models described by ordinary
differential equations (ODEs). Extensions of these results
to network-preserving transient stability models that are
mathematically described by a set of differential and alge-
braic equations (DAE) can be found in Ref. 36.
CONSTRUCTING ENERGY FUNCTIONS
It can be shown that an analytical expression of en-
ergy functions does not exist for general lossy network-
preserving transient stability models [35]. Consequently,
numerical energy functions must be used. We present
procedures to derive numerical energy functions for
structure-preserving transient stability models. Most ex-
isting network-preserving models can be rewritten as a set
of general differential-algebraic equations of the following
compact form [15]:
∂U
0=− (u, w, x, y) + g1 (u, w, x, y)
∂u
∂U
0=− (u, w, x, y) + g2 (u, w, x, y)
∂w
∂U (12)
T ẋ = − (u, w, x, y) + g3 (u, w, x, y)
∂x
ẏ = z
∂U
M ż = −Dz − (u, w, x, y) + g4 (u, w, x, y)
∂y
where u ∈ IRl and w ∈ IRl are instantaneous variables while
x ∈ IRn , y ∈ IRn , and z ∈ IRn are state variables. T is a pos-
itive definite matrix, and M and D are diagonal pos-
itive definite matrices. Here differential equations de-
scribe generator and/or load dynamics, whereas algebraic
equations express the power flow equations at each bus.
g1 (u, w, x, y), g2 (u, w, x, y), g3 (u, w, x, y), and g4 (u, w, x, y) are
vectors representing the effects of the transfer conductance
in the network Y-bus matrix. With the aid of the singu-
larly perturbed systems, the compact representation of the
network-preserving model becomes
∂U
ε1 u̇ = − (u, w, x, y) + g1 (u, w, x, y)
∂u
∂U
ε2 u̇ = − (u, w, x, y) + g2 (u, w, x, y)
∂w (13)
∂U
T ẋ = − (u, w, x, y) + g3 (u, w, x, y)
∂x
∂U
M ż = −Dz − (u, w, x, y) + g4 (u, w, x, y)
∂y
where ε1 and ε2 are sufficiently small positive numbers.
For the compact representation of the singularly perturbed
network-preserving power system model (14) without the
transfer conductance, we consider the following function
W : Rk+l+2n+m → R:
W(u, w, x, y, z) = K(z) + U(u, w, x, y)
1 T
= z Mz + U(u, w, x, y) (14)
2
Suppose that along every nontrivial trajectory of sys-
tem (13) with a bounded value of W(u, w, x, y, z), the
vector (u(t), w(t), x(t)) is also bounded for t ∈ R+ . Then
W(u, w, x, y, z) is an energy function for system (13).
A numerical network-preserving energy function
Wnum (u, w, x, y) can be constructed by combining an ana-
lytic energy function Wana (u, w, x, y, z) = K(z) + U(u, w, x, y)
and a path dependent potential energy Upath (u, w, x, y);
i.e.,
Wnum (u, w, x, y, z) = Wana (u, w, x, y, z) + Upath (u, w, x, y)
= K(z) + U(u, w, x, y) + Upath (u, w, x, y)
= K(z) + Unum (u, w, x, y)
A general methodology for the derivation of an energy func-
tion for general power system stability models can be found
in Refs. 37–39 and references therein.
ENERGY FUNCTIONS AND STABILITY REGION
We next present how to estimate the stability region of
a high-dimension nonlinear system, such as a power sys-
tem, via an energy function. These analytical results will be
used to provide a theoretical foundation for direct methods
in general and for the controlling UEP method.
We consider the following set:
Sv (k) = {x ∈ Rn : V (x) < k} (15)
n
where V (·) : R → R is an energy function. We shall call the
boundary of set (15), ∂S(k) := {x ∈ Rn : V (x) = k}, the level set
(or constant energy surface) and k the level value. If k is a
regular value (i.e., ∇V (x) = 0, for all x ∈ V −1 (k)), then by the
Inverse Function Theorem, ∂S(k) is a Cr (n-1)-dimensional
submanifold of Rn . Generally speaking, this set S(k) can
be very complicated with several disjoint connected com-
ponents even for the two-dimensional case. Let
S(k) = S 1 (k) ∪ S 2 (k) ∪ . . . ∪ S m (k) (16)
i j
where S (k) ∩ S (k) = ␾ when i = j. That is, each of these
components is connected and disjoint from each other.

Since V (·) is continuous, S(k) is an open set. Because S(k)
is an open set, the level set ∂S(k) is of (n-1) dimensions.
Furthermore, each component of S(k) is an invariant set.
Despite the possibility that a constant energy surface
may contain several disjoint connected components, there
is an interesting relationship between the constant energy
surface and the stability boundary. This relationship is that
at most one connected component of the constant energy
surface ∂S(r) has a nonempty intersection with the stability
region A(xs ). This relationship is established in Theorem 5
below.
Theorem 5: [16, 17] (Constant energy surface and stabil-
ity region). Let xs be a stable equilibrium point of system
(7) and A(xs ) be its stability region. Then, the set S(r) con-
tains only one connected component, which has a nonempty
intersection with the stability region A(xs ) if and only if
r > V (xs )
Motivated by Theorem 5, we shall use the notation Sxs (r)
to denote the connected set of S(r) (whose level value is r)
containing the stable equilibrium point xs . We drop the sub-
script xs of Sxs (r) when it is clear from the context. There
is a close relation between the constant energy surfaces at
different level values and the stability region A(xs ). It can
be shown that the connected set Sxs (r) with a level value r
smaller than the critical value is very conservative in the
approximation of the stability boundary ∂A(xs ). As the set
Sxs (r) is expanded by increasing the level value r, the ap-
proximation gets improved until this constant energy sur-
face hits the stability boundary ∂A(xs ) at some point. This
point will be shown to be an unstable equilibrium point. We
call this point the closest UEP of the SEP xs with respect to
the energy function V (·). Furthermore, as we increase the
level value r, the connected set Sxs (r) would contain points
that lie outside the stability region A(xs ).
It is inappropriate to approximate the stability region
A(xs ) by the connected set Sxs (r) with a level value higher
than that of the lowest point on the stability boundary
∂A(xs ). Among the several disjoint connected sets of the con-
stant energy surface, the connected set Sxs (r) is the best can-
didate to approximate the stability region A(xs ) as shown
in the following theorem.
Theorem 6: [16, 17] (Topological characterization). Con-
sider the nonlinear system (7) that has an energy function.
Let xs be an asymptotically stable equilibrium point whose
stability region A(xs ) is not dense in Rn . Then, the point
with the minimum value of the energy function over the
stability boundary ∂A(xs ) exists, and it must be an unsta-
ble equilibrium point.
We recall that the fundamental problem of power sys-
tem transient stability analysis is concerned with whether,
given a pre-fault SEP and a fault-on trajectory, the post-
fault initial state is located inside the stability region of an
asymptotically stable equilibrium point at which all the
engineering and operational constraints are satisfied. In
the context of power system transient stability analysis,
we remark that, given a point in the state space (say, the
initial point of the post-fault system), it is generally diffi-
Power System On-Line Transient Stability Assessment 9
cult to determine which connected component of a level set
contains the point by simply comparing the energy at the
given point and the energy of the level set, because a level
set usually contains several disjoint connected components
and these components are not easy to differentiate based
on an energy function value.
Fortunately, in the context of direct methods, this diffi-
culty can be circumvented because direct methods compute
the relevant pieces of information regarding (1) a pre-fault
stable equilibrium point, (2) a fault-on trajectory, and (3)
a post-fault stable equilibrium point. These pieces of infor-
mation are sufficient to identify the connected component
of a level set that contains the initial point of a post-fault
system. We next discuss the most viable direct method: the
controlling UEP method.
CONTROLLING UEP METHOD
Several methods are proposed in the literature attempt-
ing to determine accurate critical energy values; see for
example, Refs. 34, 40–44. The classic method, the closest
UEP method proposed in the early 1970s, when applied to
power system transient stability analysis has been found
to yield unduly conservative results. The origin of this con-
servativeness can be explained from a nonlinear system
viewpoint. The closest UEP method attempts to provide
an approximation for the entire stability boundary of the
post-fault system, rather than for the relevant part of the
stability boundary toward which the fault-on trajectory is
heading. This approximation by the closest UEP method
is independent of the fault-on trajectory. Thus, the closest
UEP method usually gives very conservative results for
transient stability analysis. The potential energy bound-
ary surface (PEBS) method proposed by Kakimoto et al.
gives fairly fast and accurate stability assessments but
may give inaccurate results (both overestimates and un-
derestimates).
A desirable method (for determining the critical energy
value) would be the one that can provide the most accurate
approximation of the part of a the stability boundary to-
ward which the fault-on trajectory is heading, even though
it might provide a very poor estimate of the other part of
stability boundary. This is the spirit of the controlling UEP
method, which uses the (connected) constant energy sur-
face passing through the controlling UEP to approximate
the part of stability boundary toward which the fault-on
trajectory is heading. If, when the fault is cleared, the sys-
tem state lies inside the (connected) energy surface pass-
ing through the controlling UEP, then the post-fault sys-
tem must be stable (i.e., the post-fault trajectory will settle
down to a stable operating point); otherwise, the post-fault
system may be unstable. This is the essence of the con-
trolling UEP method. A consensus seems to have emerged
that, among several methods (for determining the critical
energy value), the controlling UEP method is the most vi-
able for direct stability analysis of practical power systems
[20,45,16]. The success of the controlling UEP method,
however, hinges on its ability to find the correct control-
ling UEP.
Given a power system model with a prefault SEP Xspre ,
a fault-on trajectory Xf (t), and a post-fault (transient) sta-
10 Power System On-Line Transient Stability Assessment
bility system S post with a post-fault SEP Xspost , suppose an
energy function exists for the post-fault system S post and
Xspre lies inside the stability region of Xspost . We next discuss
a rigorous definition of the controlling UEP
Definition [16]. The controlling UEP with respect to the
fault-on trajectory Xf (t) is the UEP of the post-fault sys-
tem S post whose stable manifold contains the exit point of
Xf (t); i.e., the controlling UEP is the first UEP whose sta-
ble manifold is hit by the fault-on trajectory X f (t) at the
exit point.
This definition is motivated by the fact that a sustained
fault-on trajectory must exit the stability boundary of a
post-fault system and that the exit point, i.e., the point
from which a given fault-on trajectory exits the stability
boundary of a post-fault system, of the fault-on trajectory
must lie on the stable manifold of a UEP on the stability
boundary of the post-fault system. This UEP is the control-
ling UEP of the fault-on trajectory. Note that the existence
and uniqueness of the controlling UEP with respect to a
fault-on trajectory are assured by Theorem 2 and that the
controlling UEP is independent of the energy function used
in the direct stability assessment. With the formal defini-
tion of the controlling UEP, we are in a position to formalize
the controlling UEP method.
The Controlling UEP Method
The controlling UEP method for direct stability analysis of
large-scale power systems proceeds as follows:
1. Determination of the critical energy
Step 1.1: Find the controlling UEP, Xco , for a given
fault-on trajectory Xf (t).
Step 1.2: The critical energy, vcr , is the value of energy
function V (·) at the controlling UEP; i.e., v cr =
V (Xco ).
2. Approximation of the relevant part of stability boundary
Step 2.1: Use the connected constant energy surface of
V (·) passing through the controlling UEP Xco
and containing the SEP Xs to approximate
the relevant part of stability boundary for the
fault-on trajectory Xf (t).
3. Determination of stability: Check whether the fault-on
trajectory at the fault clearing time (tcl ) is located inside
the stability boundary characterized in Step 2.1. This is
done as follows:
Step 3.1: Calculate the value of the energy function V (·)
at the time of fault clearance (tcl ) using the
fault-on trajectory; i.e., vf = V (Xf (tcl )).
Step 3.2: If vf < vcr , then the point Xf (cl) is located in-
side the stability boundary and the post-fault
system is stable. Otherwise, it is unstable.
The controlling UEP method yields an approximation of
the relevant part of the stability boundary of the post-fault
system to which the fault-on trajectory is heading. It uses
the (connected) constant energy surface passing through
the controlling UEP to approximate the relevant part of
stability boundary.
Analysis of the Controlling UEP Method
The controlling UEP method asserts that the energy value
at the controlling UEP be used as the critical energy for
the fault-on trajectory Xf (t) to assess stability. Using the
energy value at another UEP as the critical energy can give
erroneous stability assessment. Theorem 7 gives a rigorous
theoretical justification of the controlling UEP method for
direct stability analysis of post-fault systems by just com-
paring the energy value of the state vector at which the
fault is cleared with the energy value at the controlling
UEP.
Theorem 7: (Fundamental theorem for the controlling UEP
method). Consider a general nonlinear autonomous sys-
tem that has an energy function V (·) : Rn → R. Let Xco be an
equilibrium point on the stability boundary ∂A(Xs ) of this
system. Let r > V (Xs ) and S(r)  the connected component
of the set {X ∈ Rn : V (X) < r} containing Xs , and ∂S(r):  the
(topological) boundary of S(r).
Then,
1. The connected constant energy surface ∂S(V (Xco )) in-
tersects with the stable manifold W s (Xco ) only at point
Xco ; moreover, the set ∂S(V (Xco )) has an empty intersec-
tion with the stable manifold W s (Xco ). In other words,
∂S(V (Xco )) ∩ W s (Xco ) = Xco and S(V (Xco )) ∩ W s (Xco ) = φ.
2. S(V (Xu )) ∩ W s (Xco ) = φ if Xu is a u.e.p. and
V (Xu ) > V (Xco ).
3. S(V (Xu )) ∩ W s (Xco ) = φ if Xu is a u.e.p. and
V (Xu ) > V (Xco ).
c
4. If X̂X̂ is not the closest UEP, then ∂S(V (X̂)) ∩ (Ā(Xs )) =
␾.
5. Any connected path starting from a point
P ∈ {S(V (Xco )) ∩ A(Xs )} and passing through W s (Xco )
must hit ∂S(V (Xco )) before the path hits W s (Xco ).
We next elaborate on the above fundamental theorem.
Results [1] and [5] of Theorem 7 assert that, for any fault-
on trajectory Xf (t) starting from a point Xspre ∈ A(Xs ) and
V (Xspre ) < V (X̂), if the exit point of this fault-on trajectory
Xf (t) lies on the stable manifold of Xco , then this fault-on
trajectory Xf (t) must pass through the connected constant
energy surface ∂S(V (Xco )) before it passes through the sta-
ble manifold of Xco [thus exiting the stability boundary
∂A(Xs )]. Therefore, the connected constant energy surface
∂S(V (X̂co )) can be used to approximate the relevant part of
the stability boundary.
Theorem 7 also shows the slightly conservative nature
of the controlling UEP method in direct stability assess-
ment. More importantly, this method can directly detect
both first-swing and multiswing stability or instability, al-
though historically direct methods have been said to be
only applicable to first-swing stability analysis. Note that
once the initial point of the post-fault system lies inside
the stability region A(xs ), the post-fault trajectory will con-
verge to Xs after one or multiple swings.
On the other hand, results [2] and [4] of Theorem 7 as-
sert that the following two situations may occur:

Case (1): The set S(V (Xu )) contains only part of the
stable manifold. W s (Xco )
Case (2): The set S(V (Xu )) contains the whole stable
manifold. W s (Xco )
In case (1), the fault-on trajectory Xf (t) may pass
through the connected constant energy surface ∂S(V (Xu ))
before it passes through the stable manifold W s (Xco ). In this
situation, incorrect use of Xu as the controlling UEP still
gives an accurate stability assessment. Alternatively, the
fault-on trajectory Xf (t) may pass through the connected
constant energy surface ∂S(V (Xu )) after it passes through
the stable manifold W s (Xco ). In this situation, the control-
ling UEP method using Xu as the controlling UEP, which
in fact not the controlling UEP gives an inaccurate sta-
bility assessment. This classification is incorrect. In case
(2), the fault-on trajectory Xf (t) always passes through the
connected constant energy surface ∂S(V (Xu )) after it passes
through the stable manifold W s (Xco ). Under this situation,
incorrect use of Xu as the controlling UEP can give inaccu-
rate stability assessments. In particular, it can classify the
post-fault trajectory to be stable when in fact it is unstable.
Results [3] and [4] of Theorem 7 assert that the set
S(V (Xu )) has an empty intersection with the stable man-
ifold W s (Xco ). Under this situation, the fault-on trajectory
Xf (t) always passes through the connected constant en-
ergy surface ∂S(V (Xu )) first before it passes through the
connected constant energy surface ∂S(V (Xco )). Thus, using
V (Xu ) as the critical energy value always gives more conser-
vative stability assessments than using that of the (exact)
controlling UEP, Xco . From these cases, it is clear that for a
given fault-on trajectory Xf (t), if the exit point of this fault-
on trajectory Xf (t) lies on the stable manifold of Xco , then
using the energy value at a UEP other than Xco can give
stability assessments in both directions: too conservative
stability assessments (classify many stable trajectories to
be unstable) or too optimistic stability assessments (clas-
sify unstable trajectories to be stable).
Challenges in Computing Controlling UEP. The task of
finding the (exact) controlling UEP of a given fault for gen-
eral power system models is very difficult. This difficulty
comes in part from the following complexities:
1. The controlling UEP is a particular UEP embedded in
a large-degree state-space.
2. The controlling UEP is the first UEP whose stable
manifold is hit by the fault-on trajectory (at the exit
point).
3. The task of computing the exit point is very involved;
it usually requires a time-domain approach. I
4. The task of computing the controlling UEP is compli-
cated further by the size and the shape of its conver-
gence region.
It is known that, with respect to a selected numerical
method, each equilibrium point has its own convergence
region, i.e., the region from which the sequence generated
by the numerical method starting from a point in the region
will converge to the equilibrium point. It has been observed
Power System On-Line Transient Stability Assessment 11
Figure 4. Because of “small” size and the irregular shape
(fractal-like) of the convergence region of UEP with respect to
Newton method, the task of computing the controlling UEP is
very challenging (see the shaded area). If an initial guess is
not sufficiently close to the controlling UEP, then the resulting
sequence generated by, the Newton method, will diverge or
converge to another exit point. This figure depicts that the
sequence generated by the Newton method from the exit Xe point
will not converge to the controlling UEP
and theoretically investigated by several researchers that,
under the Newton method, the size of the convergence re-
gion of UEP can be much smaller than that of the SEP. In
addition, the convergence region of either a SEP or a UEP
is a fractal, which refers to structures that cannot be de-
scribed by the typical geometrical objects such as lines, sur-
faces, and solids. Irregular shape (no smooth boundaries)
and self-similarity (each tiny piece we observe is similar to
the form of the entire shape) are characteristics of fractals
(Fig. 4.) Unfortunately, finding an initial guess sufficiently
close to the controlling UEP is a difficult task.
The complexity (3) also calls into doubt the correctness
of any attempt to directly compute the controlling UEP of
a power system stability model. The only one method that
can directly compute the controlling UEP of a power system
stability model is the time-domain approach. This complex-
ity can serve to explain why many methods proposed in the
literature fail to compute the controlling UEP. It is because
these methods attempt to directly compute the controlling
UEP of the power system stability model that is, as pointed
out in complexity (3), difficult if not impossible to compute
without using the time-domain approach.
The ability to compute the controlling UEP is vital in
direct stability analysis. It may prove fruitful to develop
a tailored solution algorithm for finding controlling UEPs
by exploiting special properties as well as some physical
and mathematical insights of the underlying power system
model. We will discuss in great detail such a systematic
method, called the BCU method, along this line for finding
controlling UEPs for power system models.
BCU METHOD
We next discuss a method that does not attempt to directly
compute the controlling UEP of a power system stability
model (original model); instead it computes the controlling
UEP of a reduced-state model, and then it relates the con-
trolling UEP of the reduced-state model to the controlling
UEP of the original model.
12 Power System On-Line Transient Stability Assessment
A systematic method, called the boundary of stability re-
gion based controlling unstable equilibrium point method
(BCU method), to find the controlling UEP was developed
[46, 47]. The method was also given other names such as
the exit point method [6,48,49] and the hybrid method [50].
The BCU method has been evaluated in a large-scale power
system, and it has been compared favorably with other
methods in terms of its reliability and the required compu-
tational efforts [48, 49]. The BCU method has been stud-
ied by several researchers; see for example [51–56]. De-
scriptions of the BCU method can be found in books such
as Refs. 3,4,6 and 50. The theoretical foundation of BCU
method has been established in. The Refs. 15, 46, and 57
BCU method and BCU classifiers have several practical ap-
plications. For example, a demonstration of the capability
of the BCU method for on-line transient stability assess-
ments using real-time data was held at two utilities, the
Ontario Hydro Company and the Northern States Power
Company [58, 59]. The BCU method was implemented as
an EPRI TSA software package that was integrated into
an EMS installed at the control center for the Northern
States Power Company [19]. A TSA system, composed of
the BCU classifiers, the BCU method, and a time-domain
simulation engine, was developed and integrated into the
Ranger EMS system [60]. The TSA system has been in-
stalled and commissioned, as part of an EMS system at
several energy control centers. The BCU method has been
applied to fast derivation of power transfer limits [61] and
applied to real power rescheduling to increase dynamic se-
curity [62]. The BCU method has been improved, expanded,
and extended into the integrated package of TEPCO-BCU
[33,46,47,63–65].
We next present an overview of the BCU method from
two viewpoints: numerical aspects and theoretical aspects.
In developing a BCU method for a given power system sta-
bility model, the associated artificial, reduced-state model
must be defined. To explain the reduced-state model, we
consider the following generic network-preserving tran-
sient stability model:
∂U
0=− (u, w, x, y) + g1 (u, w, x, y)
∂u
∂U
0=− (u, w, x, y) + g2 (u, w, x, y)
∂w
∂U
T ẋ = − (u, w, x, y) + g3 (u, w, x, y)
∂x
ẏ = z
∂U
M ż = −Dz − (u, w, x, y) + g4 (u, w, x, y)
∂y
where U(u, w, x, y) is a scalar function. It has been shown
that the above canonical representations can represent ex-
isting transient stability models. In the context of the BCU
method, the above model is termed as the original model.
Regarding the original model (17), we choose the following
differential-algebraic system as the reduced-state model
associated with the original model (17).
∂U
0=− (u, w, x, y) + g1 (u, w, x, y)
∂u
∂U
0=− (u, w, x, y) + g2 (u, w, x, y)
∂w (18)
∂U
T ẋ = − (u, w, x, y) + g3 (u, w, x, y)
∂x
∂U
ẏ = − (u, w, x, y) + g4 (u, w, x, y)
∂y
There are several close relationships between the
reduced-state model (18) and the original model (17). The
fundamental ideas behind the BCU method can be ex-
plained as follows. Given a power system stability model
(which admits an energy function), say the original model
(17), the BCU method first explores the special properties
of the underlying model with the aim of defining a reduced-
state model, say the model described in (18), such that the
following static as well as dynamic relationships are met
Static Properties
(S1) The locations of equilibrium points of the reduced-
state model (18) correspond to the locations of equi-
librium points of the original model (17). For ex-
ample, (û, ŵ, x̂, ŷ) is an equilibrium point of the
reduced-state model if and only if (û, ŵ, x̂, ŷ, 0) is an
equilibrium point of the original model (17), where
0 ∈ Rm and m is an appropriate positive integer.
(S2) The types of equilibrium points of the reduced-
state model are the same as that of the original
model. For example, (us , ws , xs , ys ) is a stable equi-
librium point of the reduced-state model if and only
if (us , ws , xs , ys , 0) is a stable equilibrium point of
the original model. (û, ŵ, x̂, ŷ) is a type-k equilib-
rium point of the reduced-state model if and only
if (û, ŵ, x̂, ŷ, 0) is a type-k equilibrium point of the
original model.
Dynamical Properties
(D1) An energy function for the artificial, reduced-state
model (18) exists.
(D2) An equilibrium point, say, (û, ŵ, x̂, ŷ) is on the stabil-
ity boundary of the reduced-state model (18) if and
only if the equilibrium point (û, ŵ, x̂, ŷ, 0) is on the
stability boundary of the original model (17).
(D3) It is computationally feasible to efficiently de-
(17)
tect the point at which the projected fault-on tra-
jectory (u(t), w(t), x(t), y(t)) hit the stability boundary
∂A(us , ws , xs , ys ) of the post-fault reduced-state model
(18) without resorting to an iterative time-domain
procedure to compute the exit point of the post-fault
reduced-state model (18).
The dynamic relationship (D3) plays an important role
in the development of the BCU method to circumvent the
difficulty of applying an iterative time-domain procedure
to compute the exit point on the original model. The BCU
method then finds the controlling UEP of the artificial,
reduced-state model (18) by exploring the special struc-
ture of the stability boundary and the energy function of
 Power System On-Line Transient Stability Assessment 13

the reduced-state model (18). Next, it relates the control-

ling UEP of the reduced-state model (18) to the controlling
UEP of the original model (17).
The fundamental ideas behind the BCU method can be
explained in the following. Given a power system stability
model (which admits an energy function), the BCU method
first explores special properties of the underlying model
with the aim to define an artificial, state-reduced model
such that certain static as well as dynamic relationships
are met. The BCU method then finds the controlling UEP
of the state-reduced model by exploring the special struc-
ture of the stability boundary and the energy function of
the state-reduced model. Third, it relates the controlling
UEP of the state-reduced model to the controlling UEP of
the original model. In summary, given a power system sta-
bility model, a corresponding version of the BCU method
exists. The BCU method does not compute the controlling
UEP directly on the original model because, as pointed out,
the task of computing the exit point of the original model,
a key step to compute the controlling UEP, is very difficult
and usually requires the time-domain approach. Instead,
the BCU method (1) explores the special structure of the
underlying model so as to define an artificial, state-reduced
model that captures all the equilibrium points on the sta-
bility boundary of the original model; and then (2) com-
putes the controlling UEP of the original model via com-
puting the controlling UEP of the artificial model, which
can be computed without resorting to the time-domain ap-
proach.

Figure 5. Steps 1 and 2 of the conceptual BCU method.

A Conceptual BCU Method
Step 1. From the fault-on trajectory [u(t), ω(t), x(t), y(t),
z(t)] of the network-preserving model (17), de-
tect the exit point (u∗ , w∗ , x∗ , y∗ ) at which the
projected trajectory [u(t), ω(t), x(t), y(t)] exits the
stability boundary of the post-fault reduced-
state model (18).
Step 2. Use the exit point (u∗ , w∗ , x∗ , y∗ ), detected in
Step 1, as the initial condition and integrate
the post-fault reduced-state model to an equilib-
rium point. Let the solution be (uco , wco , xco , yco ).
Step 3. The controlling UEP with respect to the
fault-on trajectory of the original network-
preserving model (17) is (uco , wco , xco , yco , 0).
The energy function at (uco , wco , xco , yco , 0) is
the critical energy for the fault-on trajectory
[u(t), ω(t), x(t), y(t), z(t)].
Steps 1 and 2 of the conceptual BCU method compute
the controlling UEP of the reduced-state system. Note that
starting from the exit point (u∗ , w∗ , x∗ , y∗ ), Step 2 of the con-
ceptual BCU method, will converge to an equilibrium point.
The controlling UEP always exists and is unique, and the
stable manifold of controlling UEP of the reduced-state sys-
tem (uco , wco , xco , yco ) contains the exit point (u∗ , w∗ , x∗ , y∗ )
(Fig. 5.) Step 3 relates the controlling UEP of the reduced-
state system (with respect to the projected fault-on trajec-
tory) to the controlling UEP of the original system with
respect to the original fault-on trajectory.
Theoretical Basis
Some analytical results showing that, under certain con-
ditions, the original model (17) and the artificial, reduced-
state model (18) satisfy static relationships (S1) and (S2) as
well as dynamic relationships (D1) and (D2) can be found
in [46, 57]. A computational scheme has been developed
and incorporated into the BCU method to satisfy dynamic
relationship (D3). We next verify the static relationship.
Theorem 8: (Static relationship). Let (us , ws , xs , ys ) be a
stable equilibrium point of the reduced-state model (18).
If the following conditions are satisfied:
∂4 U(ui , wi , xi , yi )
1. Zero is a regular value of for all the
∂u∂w∂x∂y
UEP (ui , wi , xi , yi ), i = 1, 2, . . . , k on the stability bound-
ary ∂A(us , ws , xs , ys ).
2. The transfer conductance of reduced-state model (18)
is sufficiently small. Then, (û, ŵ, x̂, ŷ) is a type-k equi-
librium point of reduced-state model (18) if and only if
(û, ŵ, x̂, ŷ, 0) is a type-k equilibrium point of the original
model (17).
Theorem 8 asserts that, under the stated conditions, the
static properties (S1) and (S2) between original model (17)
and the reduced-state model (18) hold. It can be shown
that a numerical energy function exists for the reduced-
state model (18). More specifically, it can be shown that for
14 Power System On-Line Transient Stability Assessment
any compact set S of the state-space of model (18), there is
a positive number ␣ such that, if the transfer conductance
of the model satisfies |G| <␣, then there is an energy func-
tion defined on this compact set S. The examination of the
dynamic property (D2) can be found in Refs. 46 and 57.
NUMERICAL BCU METHOD
There are several possible ways to numerically imple-
ment the conceptual BCU method for network-preserving
power system models. A numerical implementation of this
method along with several numerical procedures necessary
are presented in this section.
A Numerical BCU Method
Step 1. Integrate the fault-on system of the original
model (19) to obtain the (sustained) fault-on tra-
jectory [u(t), w(t), x(t), y(t), z(t)] until the point
(u∗ , w∗ , x∗ , y∗ ) at which the projected trajectory
[u(t), w(t), x(t), y(t)] reaches its first local maxi-
mum of the numerical potential energy function
Unum (., ., ., .) along the projected trajectory.
Step 2. Apply the stability-boundary-following proce-
dure starting from the point (u∗ , w∗ , x∗ , y∗ ) un-
til the point at which the (one-dimensional) lo-
cal minimum of the following norm of the post-
fault, reduced-state system is reached; i.e.,

∂U
5. n Step 3, the MGP is used as an initial guess for the




(u, w, x, y) + g1 (u, w, x, y)

∂u

∂U




+
(u, w, x, y) + g2 (u, w, x, y)

∂w

∂U




+
(u, w, x, y) + g3 (u, w, x, y)

∂x

∂U
A robust nonlinear algebraic solver (with a large con-



+
(u, w, x, y) + g4 (u, w, x, y)

∂y
Let the local minimum of the above norm be
occurred at the point (u∗0 , w∗0 , x0∗ , y0∗ ).
Step 3. Use the point (u∗0 , w∗0 , x0∗ , y0∗ ) as the initial guess
and solve the following set of nonlinear alge-
braic equations:

∂U
7. From a computational viewpoint, the exit point is char-




(u, w, x, y) + g1 (u, w, x, y)

∂u

∂U




+
(u, w, x, y) + g2 (u, w, x, y)

∂w

∂U
the each integration step. When the sign of dot-product



+
(u, w, x, y) + g3 (u, w, x, y)

∂x

∂U
tected.



+
(u, w, x, y) + g4 (u, w, x, y)
= 0
∂y
Let the solution be (uco , wco , xco , yco ).
Step 4. The controlling UEP with respect to the fault-
on trajectory [u(t), w(t), x(t), y(t)] of the original
system is (uco , wco , xco , yco , 0).
Remarks
1. In Step 1, the projected trajectory [u(t), w(t), x(t), y(t)] can
be viewed as the projection of the original fault-on tra-
jectory on the state-space of the reduced-state system
(18). The first local maximum of the numerical potential
energy function Unum (., ., ., .) along the projected trajec-
tory is an approximated exit point at which the projected
trajectory intersects with the stability boundary of the
reduced-state system (18).
2. In Step 2, a stability-boundary-following procedure, pre-
sented below, is developed to guide the search process
for CUEP of the reduced-state system starting from the
point (u∗ , w∗ , x∗ , y∗ ) by moving along the stability bound-
ary of the reduced-state system (18) toward the CUEP.
During the search process, the point (u∗0 , w∗0 , x0∗ , y0∗ ) has
the local minimum of the norm among all computed
points in the search process. The norm is a measure
of distance between the current point and an equilib-
rium point. This point is also termed as the minimum
gradient point (MGP).
3. The reduced-state system can be numerically stiff, and a
stiff differential equation solver should be used to imple-
ment Step 2 of the numerical network-preserving BCU
method.
4. Without the stability-boundary-following procedure im-
plemented in Step 2, the search process can move away
from CUEP, making the corresponding MGP distant
from the CUEP and causing the divergence of the New-
ton method.
Newton method to compute the controlling UEP. It is
well known that if the MGP is sufficiently close to the
controlling UEP, then the sequence generated by the
Newton method starting from the MGP will converge to
the controlling UEP; otherwise, the sequence may con-
verge to another equilibrium point or diverge (Fig. 6.).
vergence region) is desirable in Step 3 of the numerical
BCU method.
6. Note that Steps 1 to 3 of the above numerical network-
preserving BCU method compute the controlling UEP
of the reduced-state system (18) and Step 4 relates the
controlling UEP of the reduced-state system to the con-
trolling UEP of the original system (17).
acterized by the first local maximum of the potential en-
ergy along the (sustained) fault-on trajectory. To find the
exit point, one can compute the dot-product of the fault-
on speed vector and post-fault power mismatch vector at
changes from positive to negative, the exit point is de-
Numerical Detection of Exit Point. A numerical proce-
dure for accurate detection of exit point in Step 1 of nu-
merical BCU method by employing the linear interpolation
method is described in the following:
Step 1. Integrate the fault-on trajectory until the dot
product changes sign, say between the interval
[t1 , t2 ].

Figure 6. If the MGP does not lie inside the convergent region of the Newton method, then the sequence generated by the Newton method
starting from the MGP will not converge to the controlling UEP. The sequence may diverge as illustrated in (a), or it may converge to the
stable equilibrium point as illustrated in (b).
Step 2. Apply the linear interpolation to the interval
[t1 , t2 ], which results in an intermediate time t0
where the interpolated dot product is expected
to be zero. Compute the exact dot product at
t0 for the post-fault reduced-state system. If the
value is smaller than a threshold value, the exit
point is obtained. Exit loop.
Step 3. If the dot product is positive, then replace t1 with
t0 ; otherwise replace t2 with t0 and go to Step 2.
To find an adequate MGP for reliably computing the
controlling UEP, a stability-boundary-following procedure
to guide the search process for the MGP starting from the
exit point and move along the stability boundary of the
state-reduced system is described below:
Stability-Boundary-Following Procedure.
Step 1. Integrate the post-fault reduced-state system
starting from the exit point for a few time-steps,
say, 4 to 5 steps of integration; let the new point
be termed the current point on the trajectory.
Step 2. Construct a ray connecting the current point
on the trajectory and the SEP of the post-fault
reduced-state system.
Power System On-Line Transient Stability Assessment 15
Step 3. Move along the ray starting from the current
point and detect the point with the first local
maximal potential energy, which is an energy
function for the reduced-state system, along the
ray. In practical implementation, this task is
to check the zero crossing of the dot product
between the power mismatch and the speed.
The sign of the dot product at the current point
determines the direction of the local maximal
search. Replace the current point with the point
with the first local maximal potential energy.
Step 4. Repeat Steps 1–3 until a point where the norm
of the post-fault reduced-state is lower than a
threshold value is reached. This point is a de-
sired MGP.
The analytical basis for the above procedure is the struc-
ture of the stability boundary of the reduced-state system.
It can be shown that the stability boundary of the origi-
nal system (respectively, the reduced-state system) is com-
posed of the stable manifold of the u.e.p on the stability
boundary. The controlling UEP is the u.e.p whose stable
manifold contains the exit point of the fault-on trajectory
on the stability boundary of the original system. Moreover,
controlling UEP is usually of type-1 (the UEP whose cor-
responding Jacobian matrix contains only one eigenvalue
16 Power System On-Line Transient Stability Assessment
with a positive real part). The type-1 u.e.p has the nice
feature of being a “SEP” inside the stability boundary. Fur-
thermore, the stability boundary is an “attracting” set in
the state space. Hence, if one can confine the entire search
process to a neighborhood close to the stability boundary of
the post-fault reduced-state system, then the search pro-
cess will likely obtain an MGP close to the controlling
u.e.p, facilitating the convergence of Newton method. The
stability-boundary-following procedure described above of-
fers such a capability. We note that in Step 3 of the stability-
boundary-following procedure, the task of updating the
point along the post-fault reduced-state trajectory with the
point having a local maximal energy function along the ray
amounts to confine the MGP search process close to the sta-
bility boundary.
GROUP-BASED BCU METHOD
The one-parameter transversality conditions play an im-
portant role in the theoretical foundation of the conceptual
BCU method [46, 57]. Under this condition, the reduced-
state system shares the same UEPs as the original system
on the stability boundaries of both systems. Note that as
this condition is a sufficient condition, the reduced-state
system and the original system may still share the same
UEPs on their stability boundaries, even though the one-
parameter transversality condition is not satisfied. How-
ever, because of the complexity of practical power system
models, the one-parameter transversality conditions may
not be always satisfied [51–54].
We can take a different approach for verifying the
one-parameter transversality condition. Instead of check-
ing the one-parameter transversality condition and the
small-transfer-conductance condition, we propose to di-
rectly check whether the UEP (u∗co , w∗co , xco
∗ ∗
, yco , 0) lies on the
stability boundary of the original model, i.e., check the dy-
namic property (D2) directly. We will also term the dynamic
property (D2) the boundary property. It can be shown that
the boundary property holds for sufficient damping sys-
tems, whereas it may not hold for low damping systems.
The issue of how to determine the critical damping value
above which the boundary property holds remains open.
The critical damping value seems to depend on a variety of
factors, including network topology, loading condition, and
system models used. To overcome this issue, we propose
the development of a group-based BCU method.
We have observed, through our intensive numerical sim-
ulations, that the controlling UEPs computed by the BCU
method with respect to a set of contingencies tend to be
close to each other. These controlling UEPs are close to each
other in the state space, whereas the locations where the
faults of the set of contingencies occur are close in the ge-
ographical sense. These controlling UEPs are said to form
a group. These contingencies are referred to as a group of
coherent contingencies.
The idea behind the development of the group-based
BCU method is based on observations that the contin-
gency list for transient stability assessment is composed
of groups of coherent contingencies. Some groups may con-
tain a large number of contingencies, whereas others may
contain a small number. This idea is similar, but not re-
lated, to the ideas behind the development of dynamic net-
work reduction methods, which are based on the observa-
tion of the formation of coherent generators after a con-
tingency. Coherency is an observed phenomenon in power
systems where certain generators tend to swing together
after a disturbance.
The concept of a group of coherent contingencies will
prove to be useful in several applications such as correc-
tive control and preventive control. The coordinates of the
controlling UEP in each group of coherent contingencies
provide useful information on how to design controls to sta-
bilize a power system or to enhance stability with respect
to a set of contingencies.
Extensive computation experience reveals that if the
controlling UEP (CUEP) of the reduced-state system lies
on the stability boundary of the original system, then it is
indeed the CUEP of the original system. This observation,
which is very important, brings up an important numeri-
cal question, i.e., how to check whether or the CUEP of the
reduced-state system lies on the stability boundary of the
original system. This property is referred to as the bound-
ary property of the UEP. By checking the boundary prop-
erty, one can ascertain whether the UEP of the reduced-
state system computed by the BCU method is the control-
ling UEP of the original system, without the need of check-
ing the one-parameter transversality condition. It seems
that the only numerical method capable of checking the
boundary property is the one based on an iterative time-
domain process.
An effective time-domain process to check the bound-
ary property for the entire group of coherent contingen-
cies, rather than just for on contingency, has been devel-
oped. By checking the boundary property, one can ascertain
whether the UEP of the reduced-state system computed
by the BCU method is the controlling UEP of the origi-
nal system, without needing to check the one-parameter
transversality condition. To assure the correct grouping of
coherent contingencies, we have introduced the concept of
SEP separation. This concept seens effective for identify-
ing whether contingencies in the same group are correctly
grouped. In addition, by virtue of SEP separation, contin-
gencies within each group can be quickly regrouped. Once
a group of coherent contingencies has been formed, one
only needs to concentrate on the contingencies with the
largest and smallest SEP separation in the same group. In
this manner, a complete check of the boundary property for
each contingency in each group can be avoided and a great
deal of computational work can be saved.
The group-based BCU method has several advantages
over any existing direct stability methods. For instance,
the group-based BCU method ensures the reliability of the
BCU method. In addition, the group-based BCU method
can reduce the conservativeness of the BCU method. The
method captures the inherent characteristics of coherent
contingencies. It reduces the large number of contingen-
cies, whose corresponding CUEP boundary property needs
to be checked, to a small number. The group-based BCU
method is a strict, systematic, yet reliable method to per-
form stability assessment for a complete list of contingen-
cies. Compared with the conventional TSA procedure, the

increase of computational time of the group-based BCU
method is mild because of the development of contingency
reranking by the SEP separation in each coherent group.
BCU CLASSIFIERS
We present a sequence of seven (improved) BCU classifiers
for on-line dynamic contingency screening, developed in
Refs. 31, 33, and 46. Improved BCU classifiers are designed
to meet the five requirements for dynamic contingency
screening. In particular, the BCU classifiers can achieve
absolute capture of unstable contingencies, i.e., no unsta-
ble (single-swing or multiswing) contingencies are missed.
In other words, the ratio of the captured unstable contin-
gencies to the actual critical contingencies is 1 for both test
systems. Furthermore, the yield of dropout, i.e., the ratio
of dropped-out stable contingencies to actual stable contin-
gencies), of BCU classifiers is very high. These simulation
results reveal that the proposed improved BCU classifiers
can be highly reliable and effective for on-line dynamic se-
curity assessments.
The analytical basis of BCU classifiers is based mainly
on the three steps of the BCU method and the dynamic
information derived during the computational procedure
of the BCU method. A large majority of the computational
efforts required in the improved BCU method are involved
in computing the three important state points: the exit
point (step 1), the minimum gradient point (step 2), and
the controlling UEP (step 3). Useful stability information
can be derived from these three points for developing effec-
tive schemes for dynamic contingency screening. We next
present the design of each BCU classifier along with its
analytical basis.
Classifier I: (Classifier for SEP Problem)
This classifier is designed to screen out potentially unsta-
ble contingencies. The basis for this classifier is insuffi-
ciency in the size of the post-fault stability region or in the
extreme case, the nonexistence of a post-fault stable equi-
librium point. This is explained as follows. This classifier
also checks whether a network island is formed after the
contingency.
For direct methods to be applicable, the following three
conditions need to be satisfied: (1) The post-fault equilib-
rium point is asymptotically stable, (2) the pre-fault stable
equilibrium point ␦so and the post-fault equilibrium point ␦s
are close to each other (so that using a nonlinear algebraic
solver, such as the Newton method, with ␦so as the initial
guess, will lead to δs ), and (3) the pre-fault stable equilib-
rium point δso lies inside the stability region of the post-
fault equilibrium point δs . If the pre-fault SEP lies outside
the stability region of the post-fault SEP, δs , it is very likely
that the post-fault trajectory will not approach δs , and is,
hence, potentially unstable. In this classifier, two indices
are designed to identify the contingencies that have the
convergence problem of computing post-fault stable equi-
librium points.

Ismax : the maximum number of iterations in comput-
ing the (post-fault) stable equilibrium point.
Power System On-Line Transient Stability Assessment 17

δsmax : the maximum angle difference between the pre-
fault stable equilibrium point and the computed (post-
fault) stable equilibrium point.
Classifier II (Highly Stable Classifier)
This classifier is intended to screen out highly stable con-
tingency cases. Additional stability analysis is unnecessary
for highly stable contingencies. Screening out highly stable
contingencies can greatly improve the goal of high yield for
dynamic contingency screening. If the PEBS crossing can-
not be found in the time interval [0, Texit ], and if the poten-
tial energy difference Vp (δ(Texit )) is greater than zero but
less than the threshold value Vpel , and if the maximum an-
gle difference δsmax is less than a threshold value, then the
contingency case is highly stable and no further analysis
is needed.
Classifier III (Classifier for Exit Point Problem)
A key step in the BCU method is to integrate the (post-
fault) state-reduced system starting from the exit point to
find the minimum gradient point that will be used as an
initial guess for computing the controlling UEP. A problem,
called the minimum gradient point problem, may arise dur-
ing the integration of the state-reduced system. The prob-
lem is described by the following: (1) there is no minimum
gradient point in the simulated trajectory of the (post-fault)
state-reduced system, or (2) the minimum gradient point
lies in such a region that another UEP, instead of the con-
trolling UEP, is obtained when a nonlinear algebraic solver

n
is used to solve fi (δ) = 0. The causes of the minimum
i=1
gradient point problem can be explained from a compu-
tational viewpoint. However, the minimum gradient point
problem usually damages the effectiveness and accuracy
of the BCU method.
Classifier IV (Classifier for Stability-Boundary-Following
Problem)
This classifier is intended to screen out potentially un-
stable contingencies based on some dynamic informa-
tion during the minimum gradient point search. If the
stability-boundary-following fails during the minimal gra-
dient point search, then it indicates the CUEP cannot be
found by the BCU method for the study contingency and
the contingency is sent to the time-domain simulation pro-
gram for additional analysis.
Classifier V (Classifier for Convergence Problem)
This classifier is designed to detect the convergence prob-
lem of computing the controlling UEP. In this classifier, the
maximum number of iterations, say Iumax , in computing the
controlling UEP starting from the minimum gradient point
is used to detect such a problem. If the required number
of iterations is more than a prespecified number, then the
corresponding contingency is viewed as having a numerical
divergence problem and is classified as unstable.
The convergence region of the Newton method is known
to have a fractal boundary. Using the Newton method, it
18 Power System On-Line Transient Stability Assessment
has been observed that the region of the starting point that
converges to a stable equilibrium point is more significant
than that of a unstable equilibrium point such as the con-
trolling UEP. Thus, in regular power flow calculation, the
initial guess can be chosen near the stable equilibrium
point to safely lie within the convergence region so that,
after a few iterations, it converges to the desired stable
equilibrium point. This explains why the fractal nature of
the convergence region of Newton method has been unno-
ticed in power flow study for so long. As power flow study
has been expanded to compute unstable equilibrium points
for applications such as direct transient stability analysis
and low-voltage power flow solutions for voltage collapse
analysis, the fractal nature and the different size of the
convergence region have become more pronounced. Unfor-
tunately, this nature must be taken into account when a
unstable equilibrium point is to be sought.
Classifier VI (Classifier for Incorrect CUEP Problem)
The problem is described as follows: It converges to a wrong
controlling UEP; i.e., the minimum gradient point lies in
such a region that another UEP, instead of the controlling
UEP, is obtained when a nonlinear algebraic solver is used

n
to solve  f i (δ) = 0. In this classifier, both the coordi-
i=1
nate of the obtained UEP and the angle difference between
the MGP and the obtained UEP are used as indices to de-
tect the problem.
Classifier VII (Controlling UEP Classifier)
The remaining unclassified contingencies are then sent to
BCU classifier VII for final classification. This classifier
uses the energy value at the controlling UEP as the criti-
cal energy to classify each remaining contingency as (defi-
nitely) stable or (potentially) unstable. If the energy value
at the fault clearing time is less than the energy value at
the controlling UEP, then the corresponding contingency
is (definitely) stable; otherwise it is (potentially) unstable.
The theoretical basis of this classifier is the CUEP method.
The index used in this classifier is the energy value at the
fault clearing time, whereas the threshold value for this
index is the energy value at the controlling UEP.
In summary, given a list of credible contingencies to
the seven BCU classifiers, the first classifier is designed
to screen out those contingencies with convergence prob-
lems in computing post-fault stable equilibrium points. The
second and third classifiers, based on Step 1 of the BCU
method, are the fastest ones. They use the energy value at
the exit point on the stability boundary of the reduced-state
model as an approximation for the critical energy. The sec-
ond classifier is designed to drop those contingencies that
are highly stable, whereas the third is designed to screen
out those contingencies that may cause computational dif-
ficulties for the BCU method and, hence, may damage the
reliability of the following BCU classifiers. The fourth clas-
sifier screens out those contingencies that cause failure in
finding the MGP. The fifth classifier screens out the contin-
gencies with the problem of converging to the controlling
UEP. The sixth classifier drops those contingencies with
the problem of incorrect CUEP. The seventh classifier uses
the energy at the controlling u.e.p as the critical energy to
classify every contingency left over from the previous clas-
sifiers into two classes: stable contingencies and unstable
contingencies. This classifier is based on Step 3 of the BCU
method.
Contingencies that are classified as definitely stable at
each classifier are eliminated from additional analysis. It
is because of the definite classification of stable contingen-
cies that considerably increased speed for dynamic secu-
rity assessment can be achieved. Contingencies that are
either undecided or identified as unstable are then sent
to the time-domain transient stability simulation program
for further stability analysis. Note that the conservative
nature of the BCU method guarantees that the results
obtained from the seven dynamic contingency classifiers
are also conservative; i.e., no unstable cases are misclassi-
fied as stable. Classifying a stable contingency, either first-
swing or multiswing, as unstable is the only scenario in
which the BCU classifiers give conservative classifications.
From a practical viewpoint, it is worth noting that a
time-domain simulation program is needed to further an-
alyze those contingencies that are only dropped out from
Classifiers I, III, IV, V, and VI. Therefore, the efficiency of
the proposed BCU classifiers depends on the ratio of those
contingencies screened out from Classifiers II and VII with
respect to the total stable contingencies, i.e., the yield of
drop-out of stable contingencies. Note that the number of
stable contingencies is not a criterion for evaluating perfor-
mance because it depends on several factors, among which
the loading condition, network topology, and contingency
selection all play an important role. The seven BCU classi-
fiers perform the process of dynamic contingency screening
in a sequential order.
Numerical Studies
The improved BCU classifiers has been extensively evalu-
ated on a practical power system transient stability model.
A total of 507 contingencies on the test system with heavy
loading conditions and ZIP load model and a total of 466
contingencies on the test system with medium loading con-
ditions and non-smooth load model were applied. The type
of faults considered in the evaluation were three-phase
faults with fault locations at both generator and load buses.
Some contingencies are faults that were cleared by open-
ing double circuits, whereas others are faults that were
cleared by opening the single circuit. Two load models were
employed in the simulation: the non-smooth load model
and the ZIP load model with the composition of the 20%
constant current, 20% constant power, and 60% constant
impedance. Both severe and mild faults were considered.
All faults were assumed to have been cleared after 0.07 s.
A time-domain stability program was used to numerically
verify all classification results. Simulation results on both
systems are presented next.
A summary of dynamic contingency screening by the im-
proved BCU classifiers and the time-domain stability pro-
gram on the test system with heavy-loading condition and
ZIP load model for the undamped factor and damped factor
is displayed in Table 1 and Table 2, respectively. A summary
 Power System On-Line Transient Stability Assessment 19

Table 1. BCU classifiers on a test system (undamped, heavy-loading): ZIP model

Tools Results I (U) II (S) III (U) IV (U) V (U) VI (U) VII (S) VII (U) Total
BCU Classifiers Drop-Out cases 83 6 0 2 12 1 378 25 507
Time-Domain Stable 6 6 0 2 12 1 378 17 422
Unstable 77 1 0 0 0 0 0 8 85

Table 2. BCU classifiers on a test system (damped, heavy-loading): ZIP model

Tools Results I (U) II (S) III (U) IV (U) V (U) VI (U) VII (S) VII (U) Total
BCU Classifiers Drop-Out cases 83 16 0 1 11 1 369 26 507
Time-Domain Stable 9 16 0 1 11 1 369 18 425
Unstable 74 0 0 0 0 0 0 8 82

Table 3. BCU classifiers on a test system (undamped, medium-loading): non-smooth model

Tools Results I (U) II (S) III (U) IV (U) V (U) VI (U) VII (S) VII (U) Total
BCU Classifiers Drop-Out cases 26 8 0 4 4 0 419 5 466
Time-Domain Stable 4 8 0 4 4 0 419 5 444
Unstable 22 0 0 0 0 0 0 0 22

Table 4. BCU classifiers on a test system (damped, medium-loading): non-smooth model

Tools Results I (U) II (S) III (U) IV (U) V (U) VI (U) VII (S) VII (U) Total
BCU Classifiers Drop-Out cases 26 11 0 4 3 0 418 4 466
Time-Domain Stable 4 11 0 4 3 0 418 4 444
Unstable 22 0 0 0 0 0 0 0 22

of dynamic contingency screening on the test system with
medium-loading and non-smooth load model for undamped
factor and damped factor is displayed in Table 3 and Table
4, respectively. A detailed explanation is presented below.
1. Test system with heavy-loading. For the test system
with heavy-loading conditions, ZIP load model, and un-
damped effect, we summarized the evaluation of BCU
classifiers on a total of 507 contingencies in Table 1.
Given a total of 507 contingencies sent to the BCU clas-
sifiers, the first BCU classifier dropped out 83 cases
and classified them to be unstable. These 83 cases were
numerically verified by the time-domain stability pro-
gram. Among these cases 77 were indeed unstable ac-
cording to the time-domain stability program and 6
were stable. The remaining 424 contingencies were sent
to the second BCU classifier for another classification.
This classifier dropped 6 cases that were classified to
be stable, and they were indeed stable according to the
time-domain stability program. The remaining 418 con-
tingencies were sent to the BCU classifier III, which
screened out 0 unstable cases. The remaining 418 con-
tingencies were sent to the BCU classifier IV, which
screened out 2 unstable cases. Among these contingen-
cies, according to the time-domain stability program,
2 cases were stable. The fifth BCU classifier screened
out 12 contingencies as unstable. The BCU VI classifier
screened out 1 contingency, which was classified as un-
stable. This contingency, however, is stable, according to
the time-domain stability program. The remaining con-
tingencies entered the last BCU classifier for final clas-
sification. Among them, 378 cases were classified to be
stable and all of these were verified by the time-domain
stability program to be indeed stable; 25 cases were clas-
sified to be unstable. Among these cases 8 were indeed
unstable and 17 were stable, as verified by the time-
domain stability program. Similar explanations apply
to Table 2, which summarizes the evaluation of BCU
classifiers on a total of 507 contingencies on the same
test system with damping effect.
2. Test system with medium loading. For the test sys-
tem with medium-loading conditions, non-smooth load
model, and undamped effect, we summarized the eval-
uation of BCU classifiers on a total of 466 contingencies
in Table 3. Given a total of 466 contingencies sent to the
BCU classifiers, the first BCU classifier dropped out 26
cases and classified them to be unstable. These 26 cases
were numerically verified by the time-domain stability
program. Among these cases 22 were indeed unstable
according to the time-domain stability program and 4
were stable. The remaining 440 contingencies were sent
to the second BCU classifier for another classification.
This classifier dropped 8 cases, which were classified
to be stable, and they were indeed stable according to
the time-domain stability program. The remaining 432
contingencies were sent to the BCU classifier III, which
screened out 0 unstable cases. The remaining 432 con-
tingencies were sent to the BCU classifier IV, which
screened out 4 unstable case. These 4 cases according
to the time-domain stability program were stable. The
fifth BCU classifier screened out 4 contingencies. Those
contingencies were classified unstable. Of which, 4 con-
tingencies were, however, all stable. The BCU VI classi-
fier screened out 4 contingencies, which were classified
as unstable. The remaining 424 contingencies were sent
to the BCU classifier VI, which screened out 0 unstable
cases. The remaining 424 contingencies were sent to the
last BCU classifier for final classification. Among them,
419 cases were classified to be stable and all of these
were verified by the time-domain stability program to
be indeed stable; 5 cases were classified to be unstable.
Of which, they were however all stable. Similar explana-
tions apply to Table 4, which summarizes the evaluation
20 Power System On-Line Transient Stability Assessment

of BCU classifiers on a total of 466 contingencies on the
test system with damping effect.
Performance Evaluation
Absolute Capture and Drop-Out. The BCU classifiers
met the requirements of absolute capture of unstable con-
tingencies on a total of 1946 contingencies. The capture ra-
tio (the ratio of the captured unstable contingencies to the
actual contingencies) is 1.0. In other words, the BCU clas-
sifiers capture all unstable contingencies as summarized
in Table 5.
High Drop-out Stable Contingencies. The yield of drop-
out (the ratio of the dropped-out stable contingencies to
the actual stable contingencies by the BCU classifiers) is
90.99% (heavy, ZIP-model, undamped), 90.58% (heavy, ZIP
model, and damped), 96.17% (medium, non-smooth load
model, and undamped), and 96.62% (medium, non-smooth
load model, and damped), respectively, as summarized in
Table 5.
Off-Line Calculations and Robust Performance. It should
be pointed out that the same threshold values for the six
BCU classifiers were applied to these 1946 cases. The com-
putational effort required in each BCU classifier is differ-
ent from each other. In addition, as the proposed BCU clas-
sifiers are connected in a sequential order, the total compu-
tational effort required to screen out a contingency (stable
or unstable) by a BCU classifier is the summation of the
computational effort required in each BCU classifier pre-
ceding and including the BCU classifier. For instance, the
total computational effort required to screen out a contin-
gency by the BCU classifier III is the summation of the
computational effort required in BCU classifier I, II and
III.
TEPCO-BCU FOR ON-LINE TSA
TEPCO-BCU is an integrated package developed for fast
and yet exact transient stability assessment (including ac-
curate energy margin calculation and controlling UEP cal-
culations) of large-scale power systems for on-line mode,
on-line study mode, or off-line planning mode [33,63,66].
The architecture of TEPCO-BCU for on-line TSA is pre-
sented in Figure 8. Two major components exist in this
architecture: a set of BCU classifiers for dynamic contin-
gency screening and a fast and reliable time-domain tran-
sient stability simulation program and a BCU-guided time-
domain method. When a new cycle of on-line TSA is war-
ranted, a list of credible contingencies, along with infor-
mation from the state estimator and topological analysis,
are applied to the dynamic contingency screening program
whose basic function is to screen out contingencies that are
definitely stable and to screen out contingencies that are
potentially unstable.
BCU classifiers screen out stable contingencies, which
are then eliminated from additional analysis. BCU clas-
sifiers also screen out potentially unstable contingencies,
which are sent to the fast time-domain stability analysis
program, stage II of TEPCO-BCU, for final verification and,
if necessary, further analysis. Thus, the slightly conserva-
tive nature of BCU method and BCU classifiers are reme-
died. The remaining contingencies that are undecided by
BCU classifiers are then sent to the fast time-domain sta-
bility program for detailed stability analysis.
It is the ability to perform dynamic contingency screen-
ing on a large number of contingencies and to filter out
a much smaller number of contingencies requiring fur-
ther analysis that make on-line TSA feasible. The block
function of control actions decisions determines whether
timely post-fault contingency corrective actions such as au-
tomated remedial actions are feasible to steer the system
away from unacceptable conditions to an acceptable oper-
ating state. If appropriate corrective actions are not avail-
able, the block function of preventive actions determines
the required pre-contingency preventive controls such as
real power redispatches or line switching to maintain the
system stability should the contingency occur.
The algorithmic methods behind TEPCO-BCU include
the BCU method [46, 47], BCU classifiers [31, 67], improved
energy function construction [35], and the BCU-guide

Table 5. Performance evaluation of BCU classifiers on a test system with four different operating and modeling conditions: heavy, medium, ZIP load, and
non-smooth load
Heavy/undamped/ Heavy/damped/ Medium/undamped/ Medium/damped/
# Conditions/requirements ZIP load model ZIP load model non-smooth load model non-smooth load model
1 Absolute capture of unstable contingencies 100% 100% 100% 100%
2 High yield of stable contingencies 90.99% 90.58% 96.17% 96.62%
3 Litile off-line computations Yes Yes Yes Yes
4 High speed Yes Yes Yes Yes
5 Robust performance Yes Yes Yes Yes

Table 6. The average time per contingency per processor and the average time per contingency per node calculated from the total CPU time
Number of nodes Clock time duration Average time per node Number of CPUs Average time per processor
1 node 118 seconds 0.59 seconds 2 CPUs 1.18 seconds
2 node 61 second 0.31 seconds 4 CPUs 1.22 seconds

Table 7. The average time per contingency per processor/per node

Number of CPUs Total processing time Average time per processor Number of compute nodes Average time per node
2 CPUs 211.7 seconds 1.059 seconds 1 node 0.529 seconds
4 CPUs 209.3 seconds 1.046 seconds 2 node 0.523 seconds

Table 8. The wall clock time calculated to process 3000 contingencies, (the timings for the 1-node and the 2-node configurations are calculated for the 3000
contingencies directly from the test results)
Number of computer nodes Reference
1 node Test results
2 node Test results
10 nodes Conservative estimate
Figure 7. The architecture of BCU classifiers.
time domain method [33]. Several advanced numerical
implementations for BCU method have been developed
in TEPCO-BCU. The improved energy function construc-
tion has been developed to overcome the long-standing
problem associated with the traditional numerical energy
function, which has suffered from severe inaccuracy.
Another distinguishing feature of TEPCO-BCU is that
it provides useful information regarding derivation of
preventive control against insecure contingencies and of
enhancement control for critical contingencies.
The main functions of TEPCO-BCU include the follow-
ing:

Fast screening of highly stable contingencies

Given a contingency on a power system, the energy mar-
Fast identification of insecure contingencies

Fast identification of critical contingencies

Computation of energy margin for transient stability
assessment of each contingency

BCU-based fast computation of critical clearing time
of each contingency

Contingency screening and ranking for transient sta-
bility in terms of energy margin or critical clearing
time
Power System On-Line Transient Stability Assessment 21
Wall clock time
29.5 minutes
15.5 minutes
3.1 minutes

Detailed time-domain simulation of selected contin-
gencies
It is true that most contingencies in a contingency list
associated with a well-planned power system should be
stable. Furthermore, some of these stable contingencies
are highly stable in the sense of large CCTs (critical clear
times). For each highly stable contingencies, one may not
be very interested in its degree of stability or in its accu-
rate energy margin other than interested in the assurance
of its being indeed highly stable. On the other hand, all un-
stable contingencies must be all correctly identified. From
an analysis viewpoint, the exact energy margin of each un-
stable contingency may not be important. From a control
viewpoint, the exact energy margin of each unstable con-
tingency and its sensitivity with respect to control vari-
ables can be useful for developing an effective control for
preventing the system from instability should the contin-
gency occur. As to a marginally stable or critically stable
contingency, its exact energy margin provides the informa-
tion regarding how far the system is away from transient
instability once the contingency occurs and the sensitivity
of energy margin with respect to control actions provide
useful information for deriving (enhancement) control to
increase the system “distance” to transient instability.
BCU Guided Time-Domain-based Methods
The existing direct methods may not be able to compute an
accurate energy function value for every contingency. The
alternative is the time-domain based method for comput-
ing the energy margin. The task of how to derive an energy
function value from a time-domain simulated trajectory is
a practical one. Theoretically speaking, the exact energy
margin is the difference between the energy value at the
exit point of the original (post-fault) system and the en-
ergy value at the fault clearance point. The exit point of the
original system is the intersection point between the (sus-
tained) fault-on trajectory and the stability boundary of the
(post-fault) power system. It is well known that the task of
computing the exit point of the original system is very time
consuming and requires several time-domain simulations.
Hence, the task of computing the exact energy margin is
challenging.
gin, an indicator for transient stability and a measure for
the degree of stability/instability, for the given contingency
is defined by the following formula:
V = Vcr − Vcl (19)
where V is the energy margin, Vcr is the (exact) critical
energy with respect to the given fault, and Vcl is the energy
at the fault clearing time. Physically speaking, the critical
energy of a contingency corresponds to the total energy in-
22 Power System On-Line Transient Stability Assessment
Figure 8. The architecture of TEPCO-BCU for on-line TSA.
jected into the fault-on system at the critical clearing time.
Any attempt to develop a method for computing energy
margin (19) will encounter the following difficulties

The (exact) critical energy with respect to the given
fault is very difficult to compute.

The (functional) relationship between energy margin
and fault clearing time is nonlinear and difficult to
derive.
Another approach, trajectory sensitivity-based time-
domain methods, has been suggested in the literature
[68, 69]. It may appear from the surface that the trajec-
tory sensitivity-based time-domain method might be faster
than regular time-domain based methods. However, for a
practical power system, the task of calculating trajectory
sensitivity with respect to initial conditions always encoun-
ters the difficulty of formidable dimensionality explosion.
This difficulty arises especially for large power system,
and the trajectory sensitivity-based method is not practi-
cally applicable to energy margin computations of practical
power systems. We envision that the trajectory sensitivity-
based method would be useful in some applications where
only moderate dimensionality explosion is involved.
A BCU-guided time-domain method for accurate energy
margin calculation has been developed and tested on sev-
eral practical power system models [63]. The method is
reliable and yet fast for calculating energy margins whose
value is compatible with that computed by the controlling
UEP method. The BCU-guided time-domain method uses
a BCU-guided scheme to specify, within a given time in-
terval, a reduced-duration time interval and employs an
one-dimensional search method, such as the golden bisec-
tion interpolation algorithm to the specified time interval,
to reduce the total number of time-domain simulations re-
quired for finding the CCT, which is then used to compute
critical energy.
The BCU-guided method is highly effective compared
with existing time-domain-based methods: it is reliable
and yet fast for exact stability assessment and energy
margin computations. Another important property is that
the energy margins computed by the BCU-guided time-
domain method is comparable with, and yet less than,

exact energy margins, which are computed by an exact
time-domain stability method. The effectiveness can be
attributed to the fact that some information provided by
the BCU method such as the exit point and the minimum
gradient point are fully integrated into the BCU-guided
method to significantly reduce the duration of time in-
terval within which time-domain stability simulations are
performed.
A comparison study among the BCU-guided method, the
second-kick method, and the exact time-domain method
in terms of accuracy and computational speed was con-
ducted on a practical 200-bus power system model [63].
The following observations were derived from this compar-
ison. For every contingency, the BCU-guided time-domain
method always computes an energy margin that is less
than, and yet close to, that computed by the exact time-
domain method. This property indicates the conservative-
ness of the BCU-guided method in computing the energy
margin. This property, which lies in the spirit of direct
methods, is desirable in practical applications. A com-
parison between the computational speed of the BCU-
guided time-domain method and that of the exact time-
domain method is roughly the ratio of 1 to 2. The en-
ergy margins computed by the BCU-guided time-domain
method are compatible with those computed by the ex-
act time-domain method. Overall, the BCU-guided method
has the fastest computational speed among the three
methods.
Applications to Large-Scale Test System
TEPCO-BCU program has been evaluated on a large-scale
power system consisting of more than 12,000 buses and
1300 generators. In this test data, the system was mod-
eled by a network-preserving network representation. Of
the 1300 generators, 25% are classic modeled generators,
whereas 75% are detail-modeled generators with an ex-
citation system. A contingency list composed of 200 con-
tingencies are considered. Of the 200 contingencies, 2 are
unstable, about 20 are critically stable, and the remaining
are stable.
The performance of TEPCO-BCU on this test system is
summarized as follows. The capture of unstable contingen-
cies by TEPCO-BCU is 100%; i.e., no unstable (single-swing
or multiswing) contingencies are missed. Thus, the ratio of
the number of captured unstable contingencies to the num-
ber of actual unstable contingencies is 1. The ratio of the
number of stable contingencies screened out by TEPCO-
BCU to the number of actual stable contingencies is about
95%. The average computation time per contingency run-
ning TEPCO-BCU on a single processor is 1.18 second for
a 3.6-GHz PC.
Parallel TEPCO-BCU
To meet the on-line dynamic contingency screening re-
quirements for large power systems with a large number of
contingencies, TEPCO-BCU needs to be implemented on a
parallel processing architecture. Parallel processing is the
simultaneous execution of the same task (split up and spe-
cially adapted) on multiple processors in order to obtain
faster speed. The parallel nature can come from a single
Power System On-Line Transient Stability Assessment 23
machine with multiple processors or multiple machines
connected together to form a cluster. It is well recognized
that every application function benefits from a parallel pro-
cessing across a wide-range of efficiency. Some application
functions are just unsuitable for parallel processing.
The test bed system is made up of two IBM 236 IBM
eServer xSeries Servers interconnected by a Gigabit Eth-
ernet Switch. The configuration for each IBM 236 eServer
is as follows: CPU: Xeon 3.6 GHz – (Dual processors) with
2-MB L2 cache per Processor, Hyper-Threading Technol-
ogy and Intel Extended Memory 64 Technology, 1 GB DDR
II SDRAM - ECC - 400 MHz - PC2-3200, Storage Control:
SCSI (Ultra320 SCSI) - PCI-X / 100 MHz (Adaptec AIC-
7902), and RAM: 1 GB (installed) / 16 GB (max) - DDR II
SDRAM - ECC - 400 MHz - PC2-3200.
The parallel TEPCO-BCU program has been evaluated
on a large-scale power system consisting of more than
12,000 buses and 1300 generators. Of the 1300 genera-
tors, 25% are classical modeled generators whereas 75%
are detail-modeled generators with an excitation system.
A contingency list composed of 3000 contingencies are con-
sidered. The parallel TEPCO-BCU was run on the test
data to determine the average time needed to process a
contingency for each configuration tested. Two tests were
ran, first using a single compute-node and then using two
compute-nodes. Time was marked at the beginning of the
test and again when TEPCO-BCU completed the screening
to give the duration of the test, or the wall clock time. The
computation performance regarding the average time per
contingency per node and the average time per contingency
per processor was recorded. The test showed that the par-
allel implementation of TEPCO-BCU cut the average pro-
cessing time per node by 50% when a second compute-node
was added.
Test data that were collected during the tests to record
the total CPU time spent during the TEPCO-BCU run on
processing of the contingencies is summarized in Tables
6–8. The average time per contingency per processor and
the average time per contingency per node calculated from
the total CPU time are also presented in the tables. It is ob-
served that the average time per contingency per processor
remains essentially unchanged irrespective of the number
of processors given uniform testing conditions. The 2-node
and 4-node test comparison is provided to observe the small
degree of variation.
The timings for the 1-node and the 2-node configura-
tions were calculated for the 3000 contingencies directly
from the test results. A 5% overhead was used in the es-
timation of the 10-node timing, despite the fact that the
testing showed overhead to be in the vicinity of 3%, in or-
der to be on the conservative side. In addition, as the test
dataset resulted in a high number of unstable and critical
stable cases, it is likely that datasets that produce a more
typical percentage of stable cases will result in even faster
performance results for the TEPCO-BCU fast screening.
CONCLUDING REMARKS
On-line transient stability assessment (TSA) is an essen-
tial tool needed to obtain the operating security limits at
24 Power System On-Line Transient Stability Assessment
or near real time. In addition to this important function,
power system transmission open access and restructuring
further reinforce the need for on-line TSA, as it is the base
upon which available transfer capability, dynamic conges-
tion management problems, and special protection systems
issues can be effectively resolved. There are significant en-
gineering and financial benefits to be expected from on-line
TSA.
After decades of research and development in the
energy-function-based direct methods and the time-
domain simulation approach, it has become clear that the
capabilities of direct methods and that of the time-domain
approach complement each other. The current direction of
development is to include appropriate direct methods and
time-domain simulation programs within the body of over-
all power system stability simulation programs. For exam-
ple, the direct method provides the advantages of fast com-
putational speed and energy margins, which make it a good
complement to the traditional time-domain approach. The
energy margin and its functional relation to certain power
system parameters form an effective complement to de-
velop tools, such as preventive control schemes for credible
contingencies that are unstable and to develop fast calcu-
lators for available transfer capability limited by transient
stability. The direct method can also play an important role
in the dynamic contingency screening for on-line transient
stability assessment.
This chapter has presented an overview of state-
of-the-art methodology and effective computational
methods useful for on-line TSA. The current direction of
development for on-line TSA is to combine a reliable and
fast direct method and a fast time-domain method into an
integrated methodology to take advantage of the merit of
both methods. TEPCO-BCU has been developed under this
direction by integrating the BCU method, BCU classifiers,
and the BCU-guide time domain method. Several ad-
vanced numerical implementations for BCU method have
been developed in TEPCO-BCU. The current version of
TEPCO-BCU can perform exact stability assessment and
accurate energy margin computation of each contingency
of large-scale power systems. Exact stability assessment
is meant to classify stable contingencies as stable and
unstable contingencies as unstable, whereas accurate
energy margin computation is meant to give accurate
critical clearing time of each contingency of large-scale
power systems. The evaluation results indicate that a
parallel version of TEPCO-BCU works well with reliable
transient stability assessment results and accurate energy
margin calculations on a 12,000-bus test system with a
contingency list of 3000 contingencies.
The group-based BCU method raises and addresses the
issue of how to rigorously verify the correctness of the TSA
results. In the past, this issue has been neglected because
of the great computational efforts and difficulty involved.
Given a credible list of contingencies, the TEPCO-BCU sys-
tem can fast screen out critical contingencies. This capabil-
ity in conjunction with some relevant functions can lead to
several practical applications. These relevant functions in-
clude the energy function method and the controlling UEP
coordinates and their sensitivities with respect to param-
eters or control actions. One such application is the devel-
opment of a dynamic security constrained optimal power
flow method. A preliminary dynamic security constrained
OPF algorithm is realized based on the TEPCO-BCU en-
gine [66]. Several applications based on TEPCO-BCU en-
gine will be developed in the future.
As the size of power system analysis data increases
due to, say, deregulation, it becomes clear that effective
data-handling schemes, data verification and correction,
and graphical user interface (GUI) are important for
power system analysis tools. It is also clear that the
approach of detailed representation for the study system
and adequate and yet simplified representation for the
external system is well accepted and several methods
for reducing external systems have been proposed. In
this regard, the data handling of the separated power
system data, i.e., the data for the study system and the
data for the external system, can be very complicated and
error-prone with the conventional text-based format. In
Ref. 70, effective data-handling schemes and GUI have
been developed for an integrated power system analysis
package. Two reduction techniques are also presented: one
is a static reduction technique for power flow analysis, and
the other is a dynamic reduction technique for transient
stability analysis and small-signal analysis.
Although current power system networks cannot com-
pletely prevent disastrous cascading, their ability to man-
age power system disturbances can be considerably en-
hanced. Power systems have been relying mostly on protec-
tion systems and discrete supplementary control schemes
to manage disturbance and prevent disastrous cascading.
This practice needs further enhancement in both scope and
depth. On-line TSA should join this practice. The design
of protection systems and discrete supplementary control
schemes have been often based on passive and static
considerations. The parameter settings of protection sys-
tems and discrete supplementary control schemes are not
adaptive to system operating conditions and network con-
figurations. Moreover, the design and parameter settings
of protection systems and discrete supplementary control
schemes do not take into account system dynamic behav-
iors. Consequently, several adverse behaviors of protection
systems and discrete supplementary control systems occur
that cause service interruption of electricity and system
blackouts. These behaviors include (1) unnecessary relay
trippings (relays overact to stable swings) and (2) unneces-
sary distance relay trippings caused by system low voltage
and heavy loading conditions. Increased coordination be-
tween on-line TSA and the parameter settings of protection
systems and between that and discrete supplementary
control schemes should help eliminate these adverse
behaviors and make protection systems really adaptive.
Traditionally, an energy management system (EMS)
performs generation scheduling and control of the electri-
cal power output of generators so as to supply the continu-
ously changing customer power demand in an economical
manner. All system analysis and decision making in EMS
are all based on static considerations. A linkage between
EMS and protection systems, discrete supplementary con-
trol systems, and special protection systems has been miss-
ing. This linkage can be established using on-line measure-
ments, static analysis results available at the EMS, and

additional required measurements, such as wide-area mea-
surements, to design and develop new needed functions,
both static and dynamic security, for EMS. These new func-
tions can be utilized to develop hierachical and adaptive re-
lays and adaptive discrete supplementary controllers and
adaptive special protection systems by periodically broad-
casting updated information of both static and dynamic
security assessment results derived at the EMS to selected
protection systems and generator sites for adaptive pro-
tection systems. This updated static and dynamic security
assessment information can be used to improve the rules
residing in the relays and control schemes of discrete sup-
plementary controller and/or special protection systems so
that the overall system will greatly improve the ability to
manage disturbance and to prevent disastrous cascading.
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54. F. Paganini and B. C. Lesieutre, “Generic properties, one-
parameter deformations, and the BCU method,” IEEE Trans.
Circuits and Systems, Part-1, Vol. 46, No. 6, June 1999, pp.
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55. L. F. C. Alberto, “Transient stability analysis: Studies of the
BCU method; Damping Estimation Approach for Absolute Sta-
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60. H.-D. Chiang and A. K. Subramanian, “BCU dynamic security
assessor for practical power system models,” IEEE PES Sum-
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18–22, 1999.
61. J. Tong, H. D. Chiang, and T. P. Conneen, “A sensitivity-based
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power systems,” IEEE Trans. Power Systems, Vol. PWRS-8,
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62. D. H. Kuo and A. Bose, “A generation rescheduling method
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security assessment at northern States Power Company,” Conference and Exhibition, New York, Oct. 13–16, 2004.
IEEE PES Summer Meeting, Edmonton, Alberta, Canada, pp. F. A. Rahimi, M. G. Lauby, J. N. Wrubel, and K. L. Lee, “Evaluation
270–272, July 18–22, 1999. of the transient energy function method for on-line dynamic
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204–220. rect methods,” IEEE Trans. Power Systems, Vol. 7, Feb., 1992,
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proaches for direct computation of critical parameters in a M. A. El-kady, C. K. Tang, V. F. Carvalho, A. A. Fouad, and V. Vittal,
power system,” International Journal of Electrical Power and “Dynamic security assessment utilizing the transient energy
Energy Systems, Vol. 24, June 2002, 337–343. function method,” IEEE Trans. Power Systems, Vol. PWRS-1,
70. Y. Tada, A. Ono, A. Kurita, Y. Takahara, T. Shishido, and K. 1986, pp. 284–291.
Koyanagi, “Development of analysis function for separated
power system data based on linear reduction techniques on
integrated power system analysis package,” 15th Conference
Dr. HSIAO-DONG CHIANG
of the Electric Power Supply, Shanghai, China, Oct. 2004.
Dr. YASUYUKI TADA
Dr. HUA LI
Further Reading Cornell University, Ithaca, NY
Tokyo Electric Power Company,
T. Takazawa, Y. Tada, H.-D. Chiang, and H. Li, “Development of Tokyo, Japan
parallel TEPCO-BCU and BCU screening classifiers for on-line Bigwood Systems, Inc., Ithaca,
dynamic security assessment,” The 16th Conference of the Elec- NY
tric Power Supply Industry, Mumbai India, Nov. 2006, 6–10.
Y. Tada, A. Kurita, M. Masuko, Y. Takahara, and K. Koyanagi,
“Development of an integrated power system analysis pack-
age,” Power System Technology, 2000. Proceedings, Power-
Con2000. International Conference, Perth Australia, Dec. 2000,
4–7.
Y. Tada, T. Yamada, T. Takazawa, Y. Takahara, and T. Shishido,
“Enhancement of data handling in integrated power system
analysis package, named IMPACT, using information technolo-
gies,” International Power Engineering Conference, IPEC 2003,
Singapore, Nov. 2003, 26–30.
Y. Tada, A. Kurita, T. Ryuya, and H. Okamoto, “Development of
voltage stability constrained OPF as one of the functions of the
integrated power system analysis package, Named IMPACT,”
IFAC Symposium on Power Plants & Power Systems Control,
Seoul, Korea, Sep. 2003, 15–19.
J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering
Copyright
c 1999 John Wiley & Sons, Inc.

PROGRAMMABLE FILTERS
This article is about programmable electric filter circuits. It is a practical review and involves no difficult
mathematics, although it does assume some familiarity with filter terminology. It does not cover digital filters,
which tend to be programmable by definition, since they are usually the direct result of running a computer
program or at least some kind of number-crunching algorithm.
Programmable filters have characteristics which can be intentionally adjusted to provide useful and
desired results, by means of external control inputs which can be of many different forms, both analog and
digital.
The circuits described in detail here are programmable in the sense that the resulting response of the
filter is a known function of the adjustment process employed. A wider class of filters, which might be termed
“variable” rather than “programmable,” have response parameters which can be changed by altering something,
but perhaps in a way which is an imprecise function of variables under the user’s control, or which varies in
an unknown way between different units from a production batch; these techniques are not covered in depth
here.

The Need for Programmability in a Filter Circuit

In many applications, the response shape, passbands, and stopbands of filter circuits needed in the design can
be specified in advance; these frequencies are fixed numbers, the same for every unit which is manufactured
and unchanging no matter what the circumstances of use. For such applications, fixed frequency filters are
utilized, and design procedures for such circuits are well established.
Applications involving some form of filtering are familiar to everybody; for instance, a radio receiver can
be viewed as a form of filter because its job is to pick out a carrier signal on which some wanted information
has been impressed by the sender, in the presence of huge amounts of competing unwanted information. A
radio receiver which could only receive one station out of the thousands transmitted would be of little use, and
so any usable “radio” can in this sense be thought of as a programmable filter.
There are many other applications where filtering is required, in order to discriminate between some
wanted signals and some unwanted ones on the basis of their frequencies, but where the characteristics of this
filtering need to be changed in response to some changing mode of application or in response to an external
circumstance.
The primary form of parameter adjustment covered here will be that of the “cutoff frequency” of the
filter; in other words, it is assumed that when the filter is adjusted, its intrinsic response “shape” is not to be
altered. For example, if the desired response shape is described by a Chebychev lowpass function, then the
flatness and ripple in the passband should not be affected simply by changing the actual value of the passband
cutoff frequency. In some cases, programmability of the response shape itself is also required, such as in the
programmable audio equalizer described subsequently.
1
2 PROGRAMMABLE FILTERS

The choice between a fully “programmable” filter , or simply a circuit in which some parameter can be
varied somewhat, generally depends on whether it is possible to determine, by examining the result of filtering
the signal, whether the filtering was effective. Another way of saying this is that if a form of “closed-loop control”
is possible, then it may be possible to get away with an unpredictable adjustment method. If only open-loop
operation is possible, then the adjusting technique needs to be correct because an iterative approach to getting
the response correct is not possible.
Another frequent feature of the need for programmability, as distinct in this case from “selectability,” is
that the actual operational parameter required—for instance the cutoff frequency—may not be known until
the actual point in time at which it has to be set.
To return again to the radio analogy, a closed-loop technique—listening to the radio and judging whether
the desired station is correctly tuned—enables a rough-and-ready adjustment method to be used, one for
which the manufacturer may not have made any promises about what the position of the tuning dial actually
“means.” In contrast, a more modern radio might enable you to “punch in” the frequency of the station with
such precision, and to set it with such accuracy, that the tuning is achieved with no correction necessary. This
is open-loop operation and requires different (and more accurate) techniques whether the system is a radio or,
say, an industrial data acquisition process.

Programmable Elements Available for Filter Parameter Adjustment

We now assume that we are to attempt to control the behavior of a single filter circuit in some way. Naturally,
the “brute force” method of achieving a range of filter responses is to design a fixed filter circuit for each of the
desired outcome responses and build them all into the equipment, with a big selector switch. This is generally
likely to work (assuming no unexpected interactions between the circuits) but is rarely likely to be efficient for
component cost, power consumption, or board area consumed and thus it is not usually a serious approach.
The adjustability might be offered to the user in the form of a big front-panel dial, or some form of interface
port to attach to a processor or network. Whatever way the interface is achieved, at some point in the circuit
programmable components of some sort will be required in order to turn the needs of the user into intentionally
adjusted parameters of a filter circuit.
Adjustable or Variable Components. These components generally have no role to play in pro-
grammable rather than adjustable filters, but they are useful in certain noncritical circuits. This is because the
control relationship may be known only empirically and may offer poor consistency over batches and perhaps
unknown stability over time and temperature.
Examples are (1) light-sensitive resistors using cadmium sulfide or a semiconductor junction, programmed
using a controllable light source, and (2) rotary resistive potentiometers adjusted with a motor (some form of
positional feedback might be used to improve the accuracy and consistency of this approach).
Note that discrete junction field-effect transistors (FETs) make excellent switches for the techniques of the
next sections, but their analog characteristics—the region between fully on and fully off—are not well-defined
and so it is difficult to make repeatable circuits when used as variable resistances with a programmable gate-
source voltage. However, careful matching of individual FETs may produce usable results over a range of up
to a decade (1,2).
Switched Two-terminal Component Arrays. These comprise arrays of fixed two-terminal compo-
nents (i.e., resistors, capacitors, or inductors) connected together by controllable switches to provide composite
components whose value can be selected from a range of values (but which is constant any time that the
selection is not being changed).
This approach is perhaps the most obvious one; it is similar to the “build several complete filters and
select between them” method except that it changes less than the entire network of filter components each
time you select a new cutoff frequency. How many components you actually need to change when you change
 PROGRAMMABLE FILTERS 3

Fig. 1. A 4-bit binary-weighted resistor array.

Fig. 2. An 8-bit binary-weighted capacitor array.

the cutoff frequency depends on the filter circuit used; clearly, the fewer the better; this is covered in more
detail in the section entitled “Fundamental Restrictions on Programmability.”
Binary-Weighted Arrays. A particularly useful technique for constructing programmable components—
and it can be capacitors (3) or resistors—is to use a switched array of components with a binary weighting
between the values. A couple of examples will illustrate the point.
Firstly, consider four resistors in series, of value 100
, 200
, 400
, and 800
. Place a controllable
switch in parallel with each resistor, and construct a truth table showing the realized resistance from node 1 to
node 5 for each of the 16 possible 4-bit input control “words” which are used to control the switches. This shows
that the circuit generates a resistance whose value is 100
multiplied by the value of this digital word—from
0
to 1500
in increments of 100
, assuming the switches’ resistance is negligible (Fig. 1).
Another example is eight capacitors, of value 1 pF, 2 pF, 4 pF, and so on up to 128 pF, each in series with
a switch, such that all capacitors share one common terminal (node 1) and all switches share another (node
10) as shown in Fig. 2. A 256-entry truth table could be constructed, though this is unnecessary because it
should be fairly clear that this circuit will realize a programmable capacitance which can be varied from 0
pF (all switches open) to 255 pF (all switches closed) in steps of 1 pF. Here we are ignoring any capacitance
contribution from the switch elements, which at this level of capacitance can be quite significant.
“Programmable” two-terminal components can be substituted quite freely in most active (and passive)
filter circuits for conventional components, as long as the limitations of the switch technology do not affect the
circuit performance.
4 PROGRAMMABLE FILTERS

Fig. 3. An inverting integrator.

The Integrator. Before moving on to the other techniques in this section, let us introduce a versatile
circuit block with great relevance to active filter design, the integrator. The simplest form, the operational
amplifier-based integrator (Fig. 3), uses the “virtual earth” at the inverting input of an op-amp operating with
feedback, to produce an output voltage which is the time integral of the current flowing through the capacitor:
The input current Ii is determined by the input voltage V i as Ii = V i /R; this same current flows in the capacitor,
resulting in an output voltage of

or

Other mechanisms are possible which turn the applied input voltage into a proportional current which is
applied to the virtual earth, and they can be thought of as having a “transresistance” equivalent to R in
the equation above. The “time constant” of the integrator, t, which can also be thought of as determining its
gain, directly determines the frequency behavior of any filter circuit in which the integrator is embedded, and
this time constant can be programmed in various ways other than using a resistor; the following subsections
describe some approaches.
Continuously Variable Transconductances. These consist of circuits integrated on a single sub-
strate are based on the highly predictable and repeatable physics of the bipolar junction transistor [and also
the metal-oxide semiconductor (MOS) transistor operating in its weak inversion region] and produce a control-
lable attenuation, gain, or conductance.
The bipolar junction transistor has a highly predictable relationship between its output current and its
input voltage. By relying additionally on the very close matching of devices available on a single substrate, it
is possible to produce a range of circuits whose performance can be adjusted accurately enough with externally
applied control voltages or currents that they are useful in the construction of programmable filters. The control
of such circuits is easily arranged because the production of programmable voltages or currents is quite simple.
These circuits tend to be used in the construction of integrators within active filter designs (4).
The OTA. The operational transconductance amplifier (OTA) is a voltage input, current output device
with a “programming” terminal into which a current is injected which controls the transconductance of the
device (5). Filters based on such programmable transconductances are termed gm –C filters and have become
an important technology for the integration of continuous-time filters onto monolithic processes (6,7). OTA
integrated circuits are also available, with the classical example being the CA3080 (8). A programmable
 PROGRAMMABLE FILTERS 5

Fig. 4. Two integrators with gain-tuned time constants. Dynamic range considerations determine the choice between
them. Any form of gain control element can be used.

integrator is particularly easy to implement with an OTA, requiring simply a grounded capacitor attached to
the output.
The VCA or Analog Multiplier. Another device which has found use in programmable filter circuits is
the voltage-controlled amplifier (VCA). The amplifier can actually be either a voltage amplifier or a current
amplifier. A voltage-controlled voltage amplifier with a linear relationship between gain and control voltage is
also known as a four-quadrant voltage multiplier; cascading one of these with a fixed time constant integrator
is one method of producing an integrator with a voltage-controlled time constant; a careful analysis of dynamic
range is required to determine whether the VCA should be located before or after the integrator (Fig. 4). In
either case, the effective time constant te = RC/Gv .
Particularly effective filters can be constructed with the voltage-controlled current amplifier (VCCA) (9)
which once again finds its place in the integrator, this time shown in Fig. 5. The VCCA is interposed between the
resistor R and the “virtual earth” of the operational amplifier around which the capacitor C provides feedback.
Impressing an input voltage V i on the resistor causes a current V i /R to flow into the VCCA, and the output
current Ia (shown in Fig. 5 as directed toward the VCCA) will therefore be −Gc V i /R, where Gc is the current
gain of the VCCA. The current flowing in the integrating capacitor is therefore changed by the same amount,
and hence the time constant of the integrator is changed:

so
6 PROGRAMMABLE FILTERS

Fig. 5. Noninverting integrator using a voltage-controlled current amplifier.

Fig. 6. A digital potentiometer; the resistance of the selector switches does not affect the accuracy of potential division
between A and B.

This technique can provide very high linearity performance since there is no signal voltage on either the input
or output terminals of the VCCA due to the virtual earth at the input of the operational amplifier—only the
current changes with differing input signals.
Switched Voltage or Current Dividers. These are voltage or current dividers and variable transcon-
ductances constructed from switched arrays of resistors, whose division ratio can be altered by applying some
form of control. This might be thought to be simply an extension of the switched two-terminal component array,
but elements which offer attenuation (or gain) are used in quite separate roles in filter circuits from simple
two-terminal impedances and are worth considering separately.
Digital Potentiometers. An electronically switched version of the conventional resistive potentiometer
has become popular; this version consists of a “string” of resistors connected in series such that each of the
points at which adjacent resistors join can be selected for connection to the “wiper” terminal (Fig. 6). This type
of circuit is easier to implement in low-cost silicon processes because it is much easier to make a large number
of resistors whose absolute value is not too important but whose matching and tracking is quite critical than
it is to make even a small number of resistors whose value is accurate and stable. As a result, these “digital
pots” find favor in circuits where their rather unpredictable impedance does not affect the circuit response at
all, this being done by the very stable division ratio afforded by the chain of well-matched resistors; in other
words, these “pots” are being used purely for their division properties and not as variable resistances.
Digital potentiometers are also available with built-in nonvolatile memory, enabling them to store their
setting when power is removed. This makes them useful for programming filters where the setting needs to be
changed only occasionally (e.g., for calibration purposes).
The R-2R Ladder and the MDAC. Another circuit arrangement of resistors and switching, which can
be used to form a programmable divider for either voltage or current, is the “R–2R ladder,” which is a key
element of a component called a multiplying digital-to-analog converter (MDAC) (10).
 PROGRAMMABLE FILTERS 7

Fig. 7. A 3-bit R–2R network controlling an integrator.

The R–2R ladder has the useful property that, when fed by an input voltage, the voltage on each successive
node on the ladder is reduced by a factor of exactly 2 from that on the previous node. To see why this is, we first
prove by induction that the input resistance of an R–2R ladder which is terminated at its last node by a resistor
of value 2R has itself an input resistance of 2R. Figure 7 shows a single section of the ladder terminated into
2R; by inspection, the resistance from node 2 to ground is the parallel combination of two 2R resistors—in
other words, R. The input resistance measured at node 1 is therefore R + R = 2R, and the voltage at node two
is just V i R/(R + R) or V i /2.
We can cascade as many of these ladder sections as we require; and note that since the voltage at each
successive node is reduced by a factor of 2, then so is the current in each of the 2R resistors. In other words, the
currents in the grounded arms of the ladder form a binary weighted set. A selection of these binary weighted
currents can be routed to the virtual earth of an op-amp instead of to ground, and it can be deployed to program
an integrator with a programmable time constant (Fig. 8 shows a circuit with three branches but MDACs are
available with up to 16 branches, offering very high resolution):

with

where any Dx can equal 0 or 1 depending on whether the branch current is switched to ground or to the op-amp
input.
Since Ii = V i /2R and I2 = Ii /2, I3 = I2 /2, I4 = I3 /2, we have

where here a ranges between 0 and 78 .

The fundamental value of the MDAC resistors is sometimes not known to within a certain tolerance error,
due to the limitations of integrated circuit (IC) processing. The time constant of an integrator made with the
MDAC will similarly suffer from this same error because it is proportional to the reference resistance R (11).
8 PROGRAMMABLE FILTERS

Fig. 8. A mark:space ratio controlled integrator; any suitable electronic switch can be used for SW1.

One solution to this is to use the MDAC instead in a programmable attenuator which can be used to provide
an adjustable integrator in the manner of Fig. 4(a) or Fig. 4(b).
Time-Domain Switching. This refers to circuits using some form of signal division in the time domain
to manipulate an existing fixed component in order to synthesize a component which appears to have a value
which is dependent on the nature of the controlling signal or “clock.”
Mark:Space Ratio Control. A technique for varying the apparent value of a resistor is to place it in
series with a switch which is periodically opened and closed at a rate which is much higher than the frequency
of any interesting signals in the circuit (12). In Fig. 8, if the mark:space ratio of the switching waveform is
1:1, it should be clear that the average value of the current which can flow when a voltage is impressed on the
resistor–switch combination is only half that which could flow if the switch were always on. In fact the effective
conductance is simply proportional to the fraction m of time that the switch is “on,” so Ii = V i m/R. Since this
adjustable mark:space ratio can be generated by a very precise digital divider, it is clear that this can be used
to turn an accurate resistor into an accurate digitally programmed resistor over quite a wide range:

Switched Capacitor Filters. The other, highly significant technique is that of the “switched capacitor”;
this is an important configuration in modern electronics and is covered elsewhere (see Switched capacitor
networks). However, a brief review of the basic principle should illustrate how this technique relates to the
other methods described here.
Consider Fig. 9, in which the capacitor C1 is switched between positions 1 and 2 by an input clock, which
we shall assume has a 1:1 mark:space ratio. In position 1, the voltage on capacitor C1 rapidly assumes the
value of the input voltage V i (we assume that the switch resistance is low enough for this to happen). When
the switch moves over to position 2, the charge in capacitor C1 is transferred to C2 ; in other words,

Therefore
 PROGRAMMABLE FILTERS 9

Fig. 9. A switched-capacitor integrator.

Since this transfer happens once every period t where t = 1/F s , we can integrate the successive small changes
in V 0 to get

Once again, this circuit is a controllable integrator, and thus it can be used in any active filter circuit which
consists of combinations of integrators—several of which are ideal candidates for programmable filters as we
shall now see.

Active Filter Architectures and Programming

This section provides a quick and practically biassed summary. Coverage of particular active filter circuits can
be found in Van Valkenburg (13) and particularly in Moschytz and Horn (14). The two most common forms of
active filter synthesis are the cascade method and the ladder-derived method; this article will focus on cascade
synthesis since it is the most common and practical method for programmable filters.
Filter circuit blocks which have a frequency response which can be described by a pair of poles (and possibly
one or two zeroes) are used as basic building blocks to construct a filter circuit of high order; these blocks are
called second-order filter sections, or sometimes just “biquads.” Higher-order filter circuits are needed when
greater discrimination is needed between different frequencies in the input signal—in common parlance, when
a “sharper” filter is required. If the filter circuit blocks can be made programmable by using the techniques of
the last section, then several of these blocks can be combined to make a programmable filter with the required
response to do the job.
Some Representative Filter Sections and their Applications. A second-order active filter section
will consist of at least one amplifier [which is usually an op-amp (voltage in, voltage out)], at least two capacitors,
and several resistors. The analysis of the popular sections has been carried out many times, and the results are
widely published. Figures 10, 12, and 13 show three second-order all-pole low-pass filter sections in a format
representative of published filter textbooks (14), and they show equations which relate their component values
and the parameters which the sections are intended to produce. These are expressed here as the pole frequency
wp and the pole quality factor qp , which is the most common way of describing such a section. Sections which
also create a transmission zero are not covered here, but the same principles will apply.
Examples of practical applications are also shown for these filter circuits, but practical considerations
such as component choice and the effect of device imperfections are covered in detail in the section entitled
“Design for Manufacturability.” Note that there are many more active filter topologies than can be covered by
this article, and the reader is encouraged to seek them out and apply these principles to determine how they
can be programmed.
10 PROGRAMMABLE FILTERS

Fundamental Restrictions on Programmability. Before examining the individual circuit topologies,

it is worth asking the question, “How may components need to be altered in a programmable filter?” These all-
pole filters can be completely described by two parameters wp and qp , which are functions of the components
in the filter. It will usually (but not always) be possible to rearrange the expressions so that two selected
component values are a function of all the other component values plus wp and qp , which means that in general
any filter circuit can be set to the required wp and qp by programming just two components. However, the
functional relationship between filter parameter and control code may be highly nonlinear, and there may also
be forbidden regions where parameter values cannot be set.
Circuits which are useful bases for programmable filters therefore need to conform to more stringent
criteria so that the programming approaches described in the previous section can be used effectively. The
majority of applications considered require that the pole frequency of the filter section be adjusted while the
pole quality factor remains constant. This is needed to ensure that the shape factor of the filter does not change
when the frequency is programmed.
This leads to an important rule: If two components are such that pole frequency is a function of only the
product of their values and the pole quality factor is a function of only the ratio of their values, then the cutoff
frequency of the filter section can be adjusted without change of filter shape by making an equal fractional
change to each component. As long as the component ratio stays constant, the pole quality factor does not
change. Equally, but of slightly less importance, the quality factor can be altered by changing the ratio of the
components, and the pole frequency will not change as long as the product of the component values is invariant.
If, for a given filter section, a pair of components can be found for which the rule above is valid, then the
section can be called “canonically programmable.” A particular circuit might offer several pairs of components
for which it is canonically programmable, in which case the choice depends on the suitability or attractiveness
of the programming techniques available for the project.
The VCVS or Sallen & Key Circuit. The first filter section is commonly called the Sallen & Key circuit;
requiring only one operational amplifier, set in this case to have unity gain, it has a low component count. Note
by examining the equations in Fig. 10 that the pole frequency is a simple function of the four basic passive
components, and that changing any one of these will change the frequency. If we look at the expression for the
pole quality factor qp , we can see that this constrains the changes we can make to the components if we also
don’t want the qp to change. We can see that qp is actually a function only of the ratios R3 /R1 and C2 /C4 , so
if we can keep these ratios constant we will keep the qp constant and thus preserve the shape of the filter; in
other words, this section is canonically programmable for (R1 , R3 ) and for (C2 , C4 ). In this simple Sallen & Key
circuit, value-programmable components are ideal control elements, whereas programmable dividers cannot
be so easily employed.
In the unity gain lowpass version of the Sallen & Key circuit shown, the resistors can be set to be of equal
value whereas the capacitors will be unequal, unless the pole quality factor is equal to 0.5, which is unlikely.
Therefore for this lowpass version, it is common to see the tuning carried out by two identical banks of switched
resistors—with the capacitors being fixed, or possibly switched in decade steps to give a really large overall
range of cutoffs.
The Sallen & Key circuit is also frequently used in a highpass role (Fig. 11), and in this application it is
usual to have the capacitors of equal value and use the ratio between the resistors to set the pole quality factor.

The GIC-Derived or Fliege Circuit. The second filter type is usually known as the Generalised
Impedance Converter (GIC)-derived filter section (Fig. 12 shows the lowpass circuit). Requiring two opera-
tional amplifiers and a few more passive components than the Sallen & Key circuit, it has been shown to be
much more suited to high values of pole quality factor (15).
Comparing the expressions for wp and qp , it can be seen that the circuit is only canonically programmable
for (C1 , C4 ). This means that the GIC-derived section can be programmed for cutoff frequency with adjustable
capacitors. Interestingly, the component R1 is absent from the expression for the cutoff frequency, and therefore
 PROGRAMMABLE FILTERS 11

Fig. 10. The voltage controlled voltage source (VCVS) or Sallen & Key unity-gain low-pass filter. (Adapted from Ref. 14,
with permission.)

Fig. 11. The Sallen & Key unity gain high-pass filter. (Adapted from Ref. 14, with permission.)

it is possible to adjust the pole quality factor freely by adjusting this resistor, which could be implemented as
a single programmable resistor array.
Variations of this circuit cover high-pass, bandpass, and notch responses and share the same characteristic
as the lowpass circuit, namely that the pole frequency can only be canonically tuned by adjusting the capacitor
values.
State-Variable Circuits. The third filter type, shown in Fig. 13, is variously known as the state-variable
or Kerwin–Huelsman–Newcombe (KHN) biquad. It employs three operational amplifiers, which might be
considered to be wasteful in comparison to other circuits, but the cost and area penalties using modern amplifier
technologies are small. The only significant disadvantage is the increased power consumption entailed.
Inspection once more of the expressions for wp and qp shows that both the resistor pair (R5 , R6 ) and
the capacitor pair (C6 , C8 ) meet the criterion for canonical programmability. The ratio of resistors R3 and R4
12 PROGRAMMABLE FILTERS

Fig. 12. The generalized impedance converter (GIC)-derived or Fliege low-pass filter. (Adapted from Ref. 14, with permis-
sion.)

appears in both expressions, meaning that this ratio should best be left alone. The ratio of resistors R1 and R2
appears only in the expression for qp , providing an independent method for adjusting the pole quality factor,
which will be found useful.
Examining the topology more closely, it can be seen that the component pairs (R5 , C6 ) and (R7 , C8 ) are
each employed with an amplifier to form an integrator; in fact, only the products R5 C6 and R7 C8 appear in
the expressions for wp and qp . In other words, the structure is canonically programmable for integrator time
constants (t1 , t2 ). This is extremely useful because it means that the integrators can be replaced with any of
the programmable integrator structures discussed in the previous section. This versatility has resulted in the
KHN biquad being the filter topology of choice for the majority of programmable filter applications requiring
high performance and closely predictable responses.
Most of the programmable integrator techniques discussed earlier can be employed in a KHN biquad
circuit. Figure 14 shows such a biquad programmed by binary-weighted switched resistors and decade-selected
capacitors; all the switching is done by an integrated switch array. Note that the switches are referred to
the inverting inputs of the integrator amplifiers, which means that there is no signal swing on a conducting
switch (see section entitled “Component Nonlinearities and Imperfections”). It is important to ensure that
enough control voltage is available to turn the switches on and off fully over the entire signal voltage swing;
commercially available integrated complementary metal-oxide semiconductor (CMOS) switch packages will
achieve this, but more care must be taken with individual JFET or DMOS switches.
 PROGRAMMABLE FILTERS 13

Fig. 13. The KHN state-variable low-pass filter, shown in its noninverting configuration. (Adapted from Ref. 14, with
permission.)

Figure 15 shows the classical circuit for using an OTA in a KHN biquad circuit (8). This circuit is limited in
its dynamic range not by fundamental constraints but because the integrated circuit OTAs currently available
have a very limited input voltage range, only a few tens of millivolts for linear operation, which is the reason
that input attenuation must be used at the front of each OTA.
An alternative topology (Fig. 16) using OTAs relies on their very high output impedance to allow a
grounded capacitor connected at the output to directly integrate the output current. The capacitor is then
buffered to prevent the next stage from loading it. Integrated circuits combining OTAs and buffers are readily
available. In this circuit the integrators are noninverting, which allows a passive summation network to be
used to combine the state feedback, eliminating one op-amp.
A common audio frequency application of the programmable state-variable circuit is in the design of
equalizers for audio systems. Reference 9 describes a representative circuit employing VCCA tuning for the
integrators in a KHN biquad; the current actually injected into the virtual earth of the amplifier is equal to
the current flowing through the VCCA’s input resistor multiplied by a scaling factor which is the logarithm of
the input control voltage divided by a reference voltage. This results in a linear decibels per millivolt function
which is appropriate for audio applications. Note also that the VCCA used here produces an output current
which is in the same direction with respect to the VCCA as the input current is. From the point of view of the
filter circuit, this turns the integrator in which the VCCA is embedded into a noninverting one, and so the
polarity of the feedback from the output of the first integrator must be reversed to allow for this. The reference
14 PROGRAMMABLE FILTERS

Fig. 14. The KHN low-pass filter programmed with arrays of resistors and capacitors.

Fig. 15. A KHN low-pass filter with op-amp integrators tuned by operational transconductance amplifiers (OTAs).

also illustrates the ease in which a VCCA-based circuit can be configured to provide independent control over
wp and qp in this topology.
MDAC-Programmed State-Variable Filters. The MDAC has found wide application in programmable
KHN biquads; many manufacturers produce highly accurate MDAC devices and provide application notes on
their use in filter design. Figure 17 shows a circuit in which not only the integrator time-constants but also the
feedback paths which were represented by (R3 , R4 ) and (R1 , R2 ) (see Fig. 13) are replaced with MDACs (11),
 PROGRAMMABLE FILTERS 15

Fig. 16. An alternative OTA-tuned low-pass filter with two integrators, not requiring a summing amplifier.

Fig. 17. An MDAC-programmed KHN state-variable low-pass filter, with additional MDACs to give finer control of pole
frequency and quality factor.

with an extra inverter employed to ensure that all feedback can be returned to the virtual earth of the input
op-amp. The extra MDACs a and b provide higher resolution for setting the wp and qp values of the section; the
MDACs controlling the integrators (in multiple biquads which may be cascaded to make a higher order filter)
can be controlled with a common code. The tolerances of the programming MDACs’ fundamental resistance
can be compensated for with the extra MDACs.
The MDAC-programmed integrator has several subtleties which can affect the performance of filters into
which it is embedded. Firstly the output capacitance is a nonlinear function of the code applied, which can
cause the behavior of filters using this technique to depart from ideal at high frequencies (16).
A further difficulty is not immediately obvious but restricts the performance of MDAC-based filters
primarily at the lower extremes of their programming range and also affects any other tuning method in
which some form of resistive voltage or current division is used to alter the integrator time constant. The
operational amplifiers used to construct the integrators contribute to the overall noise and direct-current (dc)
16 PROGRAMMABLE FILTERS

Fig. 18. A test circuit to explore the effect of the dc offset of a standard integrator in a feedback configuration.

Fig. 19. A test circuit to explore the effect of the dc offset of an attenuator-tuned integrator in a feedback configuration.

offset performance of the filters; and the greater the voltage division set by the programming circuits for the
integrators, the greater is the consequent magnification of these effects, due to the overall dc feedback which
exists around the KHN circuit (17).
Consider the two integrators of identical time constant as shown embedded in the circuits of Figs. 18 and
19. In Fig. 18 the time constant is set to be RC by means of components of those values; in Fig. 19 the same
time constant is achieved by feeding a resistor of value R/100 through an attenuator with a gain of 0.01; this
produces the same current into the integrator and hence the same time constant. These integrators are each
embedded in the feedback loop of an ideal test op-amp with grounded input to force the integrator output V 0 to
zero (note that feedback is returned to the noninverting input of this test amplifier since the integrators invert;
also note that the op-amps in the integrators are assumed ideal for the moment). The noninverting input of
the integrator op-amps would normally be grounded, but let us inject a small voltage V e into each inverting
input and work out what the change in the output voltage of the test op-amp will be. In the case of Fig. 18 we
can see that to balance the voltage V e the output of the test opamp V a will equal V e ; at dc the capacitor has no
effect and can be ignored. This is because there is no voltage dropped across the resistor R.
In Fig. 19 we can see by the same argument that the output of the attenuator has to be equal to V e to
balance the dc conditions, but this means that the output of the test amplifier is now 100V e to achieve this.
 PROGRAMMABLE FILTERS 17

These test circuits are not real filter circuits, but the split feedback loops in a state-variable filter mean
that the effective attenuation caused by either an MDAC or for instance a “digital pot” causes a buildup of
dc offset, and also low frequency noise, related to the input behavior of the integrator op-amps; it worsens as
the effective attenuation factor increases—that is, toward low cutoff frequencies. This effect is not seen when
programmable resistances are used, and it allows the latter type of filter to offer superior stability and dynamic
range compared to MDAC-tuned filters using the same filter op-amps.

Design for Manufacturability

Programmable filters of the types referred to here tend to be manufactured from separate general-purpose
electronic components, although some manufacturers have produced integrated circuits combining several of
the required functions (18). The integration of entire circuits of this type onto a monolithic substrate presents
many problems, which is why alternative techniques such as switched capacitor filtering have become popular.
This section highlights issues relating to the use of real components in programmable filters.
Device Tolerances. Clearly, since the frequency response of a filter circuit is a function of the values
of the components in it, changes in these values will change the filter response. For some special applications,
it is possible to have resistors and capacitors manufactured to the exact values determined by theory; but
this is impractical for most filter designs, whether fixed shape or programmable. Normally, the designer
must recognize the availability of “preferred value ranges” in the design process. The finite tolerances and
the availability of only discrete values of components impacts the design of programmable filters employing
directly switched components; the small deviations of the values of these components from ideal will cause the
frequency response of the realized filter, after it has been normalized to the intended cutoff frequency, to vary.
Controlling this variation usually leads to the requirement for closely matched and toleranced components.
In this respect, control techniques using MDACs, which are trimmed very accurately during the production
phase, can be very helpful.
Op-Amp Bandwidth and Predistortion. Predistortion is the term applied to the alteration of the
values used in a filter circuit so that the finite bandwidth effects of the amplifiers used are exactly compensated
for. If a programmable filter needs to cover a wide frequency range, it is quite possible that it will have to work in
regions where predistortion would not otherwise be an issue, as well as in regions where the “undistorted” values
would produce an incorrect response due to amplifier limitations. The presence of this problem presupposes that
it has not been possible within the design to find an amplifier whose performance is in all respects adequate,
and that some form of compensation will be required.
There are two approaches to a resolution of this problem. Firstly, it may be possible to set the adjustable
components or circuit elements (e.g., integrators) to values which are different from what would be expected
if the amplifiers were perfect, but in such a way that both the pole frequency and the pole quality factor are
achieved. This will require higher resolution from the controlled circuit elements than would be needed simply
to achieve the individual frequency steps required. For instance, a pair of simple 4-bit binary-switched resistor
arrays would normally be sufficient to provide a 15:1 frequency adjustment for say a Sallen & Key circuit or a
KHN Biquad at lower frequencies, but at high frequencies the 15 different values needed by each resistor (and
they will probably not be equal) might require at least 8-bit resolution, immediately doubling the complexity
of the control elements (19).
In fact, as mentioned in the section entitled “Parasitic Capacitance,” this increase in the complexity of
the control elements may itself inject another form of variability into the parameter setting process due to the
variation of parasitic capacitances which cannot be disregarded at higher frequencies, and which can combine
to make the pole frequency and pole quality factor an almost unpredictable function of the digital control
word, making automated functional calibration on a computer-controlled test fixture the only realistic way of
manufacturing these circuits (16).
18 PROGRAMMABLE FILTERS

However, the use of voltage-controlled circuit elements blends in well with this approach, since it is
usually quite easy to provide large numbers of static or slowly varying dc control signals from the central
control processor, often using a Pulse Width Modulation (PWM) technique which requires little in the way of
expensive, high-accuracy DAC components.
The other way of resolving the problem is to find a compensation technique for the circuit topology which
is orthogonal to the process for generating the theoretical component values. This involves additional (usually
passive) circuit elements which are added to the circuit so that, to at least a good approximation, the circuit
produces the intended response parameters when a particular set of component values, intended for use with
ideal amplifiers, are selected by the control circuitry.
By far the most important example of this technique is the use of phase-lead compensation in the two
popular biquads based on a pair of integrators: (a) the KHN biquad already discussed in detail, and (b) its close
cousin the Tow–Thomas biquad (20). In this technique a fixed capacitor is placed across one of the resistors
in the filter which is not adjusted when the filter is used in a programmable context (nearly always R3 in Fig.
13); the RC time constant is set to provide phase lead which cancels out the phase lag introduced by the three
amplifiers. This compensation is effective whatever the components used in the two integrators, and it is a
sound practical way to compensate programmable KHN filters. To a first approximation, the value of the time
constant for such a compensation capacitor used in a loop with three amplifiers, two of which are realizing a
standard integrator, is

where wa , the unity gain frequency of the amplifiers, is measured in rads/second. If we know the value of the
resistor, the capacitor value follows directly.
Parasitic Capacitance. Layout parasitics are generally constant and unrelated to the activities of the
control circuits in a programmable filter circuit. Such parasitics often affect the performance of an active filter
and should be taken into account in the design. Layout parasitics can be expanded to include the effects of
input capacitance of the amplifiers used; this is a significant source of error in many circuits and must also be
considered. Naturally, filter circuits containing only grounded capacitors are the easiest to make allowances
for (since the parasitic input capacitance of the amplifier is effectively connected to ground because ground and
the power supplies are, or should be, common at high frequencies).
However, a separate class of parasitics plague programmable filters and can be the limiting factor in their
successful operation at higher frequencies. All programming techniques which deploy an array of switches to
link components into the circuit—and this includes the MDAC structures discussed earlier—are affected by
the variation of the parasitic capacitance of the switch elements between the “off” and “on” states. In addition,
since various circuit branches are switched in and out by this process, static parasitics associated with these
branches are switched too, making the total amount of parasitic capacitance a complex function of the digital
code used to control the filter parameter.
The reason why this causes an unwelcome effect rather than just a smoothly varying degradation which
can be coped with in a similar way to the problem caused by op-amp bandwidth limiting relates to the way in
which a wide range of component value is implemented efficiently using some form of binary coding. As seen
earlier, this applies to both binary-weighted component networks and to MDACs.
Consider the integrator circuit of Fig. 20, in which a 4-bit binary controlled resistor network is being used
to control the time constant. The relevant parasitic capacitances are also included; C1 through C4 are the stray
capacitances across the resistor elements (note that these will in general not be related to the resistance value
in any simple way) while the switch terminal capacitances are shown as Ci and C0 (again, note that these
capacitances depend on the state of the switch). As shown previously, this circuit is capable of adjusting the
cutoff frequency of a filter in which this integrator, and others like it, are embedded, between F and 15F, where
 PROGRAMMABLE FILTERS 19

Fig. 20. A resistively programmed inverting integrator showing the parasitic capacitances associated with typical 4-bit
control.

F will be set by all the other components in the filter but will be proportional to 1/RC. With switches in the solid
position, the cutoff is being set to 7F; the most significant bit is off and all the rest are on. With switches in
the dotted position, the cutoff is being set to 8F and the most significant bit is now on, with the rest off. In one
case, we have three “on” switches, together with their own parasitics and those of the connected sub-branches
(the resistors themselves), while in the other case, only one switch is on. In particular the effect of the stray
capacitance on the resistors causes a variable degradation of the performance of the integrator.
Since there is a very nonlinear relationship between a number and the number of “on” binary bits needed
for its representation, then if the parasitic elements in a circuit are significant, their effect will vary in a very
complex way as the filter cutoff frequency is programmed using a switched resistor technique. Solutions to this
problem generally involve ensuring that the ratio between the fixed capacitor used in the integrator and the
parasitic capacitances introduced by the switched components is as high as possible.
Component Nonlinearities and Imperfections. The effect of amplifier nonlinearity on filter perfor-
mance is common to both programmable and fixed response filters; however, the particular techniques used
to achieve programmability have their own influence on nonlinearity and also to a certain extent on the noise
developed by the circuit.
Circuits using electronic switches will be sensitive to the nonlinear behavior of the on resistance of the
switch used, as a function of signal voltage swing. Improving process technologies bring steady reductions in
this source of distortion, but clearly the best solution is to eliminate the signal voltage swing by some means.
The KHN biquad employing switched resistors (Fig. 14) achieves this by operating the “on” switches at a
virtual earth point, so that whatever the signal swings at the outputs of the amplifiers in the filter, there is no
modulation of the on resistance.
20 PROGRAMMABLE FILTERS

When analog switches are used to switch banks of capacitors into a filter circuit, the on resistance of the
switch will cause an error in the filter response which is difficult to compensate for. This resistance should be
kept as low as possible; if space and power consumption are not critical, small relays can be used instead of
silicon-based switches.
Even when used in series with an intentional resistor, the on resistance behavior of a silicon switch can
cause problems due to the high positive temperature coefficient of resistance which it displays. The effect of
this resistance temperature coefficient should be taken into account; it makes little sense to spend money on
ultrastable resistors only to throw it away with this source of error (17).
Testing. Filters of this complexity present a greater alignment and testing challenge than those with
a fixed shape and cutoff frequency, because the programmability must be confirmed for the whole range over
which it is offered. It may be that a single specification for the realized performance of the filter is applied
whatever the programmed parameter, or the deterioration of performance occurring toward the extremes of
the range of programmability may be recognized by a loosening of tolerances at these extremes.
Automated testing in which both the programmable filter under test and the test equipment employed
are sent through a sequence of settings is essential for testing to be both efficient and effective. The nature of
the tests employed can be thought of as providing a “test vector” which is quite analogous to that employed in
the testing of digital circuits. The test vector, or set of tests to be performed, must be constructed to ensure that
(1) the end user of the circuit can see clearly that specification-related tests have been performed and have
been passed and (2) any potential areas known to the designer where failure may occur have been carefully
explored.

BIBLIOGRAPHY

1. U. Kumar A decade range linearly tuneable versatile filter, IEEE Trans. Instrum. Meas., IM-30: 165–167, 1981.
2. E. Damm Spannungsgesteuerte Analogfilter, Elektronik, 10: 90–92, 1976.
3. A. M. Durham W. Redman-White J. B. Hughes Digitally-tuneable continuous time filters with high signal linearity,
IEE Colloquium Digital Analogue Filter Filtering Syst., 1991, pp. 9/1–9/4.
4. R. Schaumann Design of continuous-time fully integrated filters: A review, IEE Proc., 136 (4, Pt. G): 184–190, 1989.
5. S. Franco Use transconductance amplifiers, Electron. Des., 24 (19): 98–101, 1976.
6. Y. P. Tsividis J. O. Voorman (eds.) Integrated Continuous-Time Filters: Principles, Designs & Applications, New York:
IEEE Press, 1993.
7. K. Fukahori A bipolar voltage-controlled tuneable filter, IEEE J. Solid-State Circuits, SC-16: 729–737, 1981.
8. H. A. Wittlinger Applications of the CA3080 high performance operational transconductance amplifier, application note
ICAN6668, NJ: RCA, 1973.
9. G. K. Hebert F. Floru Digitally-controllable audio filters and equalizers, 13th Int. Conf. AES, Dallas, TX, 1994.
10. D. J. Sheingold Application Guide to CMOS Multiplying D/A Converters, Norwood, MA: Analog Devices, 1978, pp.
12–14.
11. J. M. Zurada Digitally tuneable active filter biquads, Proc. Southeastcon ’81, 1981, Huntsville, AL, pp. 364–368.
12. R. W. Harris H. T. Lee Digitally controlled, conductance tuneable active filters, IEEE J. Solid-State Circuits, SC-10:
182–185, 1975.
13. M. E. Van Valkenburg Analog Filter Design, Philadephia: Holt-Saunders, 1982.
14. G. S. Moschytz P. Horn Active Filter Design Handbook, New York: Wiley, 1981.
15. N. Fliege A new class of second-order RC-active filters with two operational amplifiers, Nachrichtentech. Z., 26 (6):
279–282,1973.
16. K. Goodman J. M. Zurada Frequency limitations of programmable active biquadratic filters, Proc. Southeastcon ’81,
1981, Huntsville, AL, pp. 369–373.
17. K. Castor-Perry Using resistor-set filters, application note 7, Kemo, Ltd.
18. UAF42 Universal active filter data sheet, Tucson, AZ: Burr-Brown.
 PROGRAMMABLE FILTERS 21

19. K. Goodman J. M. Zurada A predistortion technique for RC-active biquadratic filters, Int. J. Circuit Theory Appl., 11:
289–302, 1983.
20. L. C. Thomas The biquad: part I—some practical design considerations, IEEE Trans. Circuit Theory, CT-18: 350–357,
1971.

READING LIST
D. Lancaster Active Filter Cookbook, Indianapolis, IN: Sams.
P. Horowitz W. Hill The Art of Electronics, 2nd ed., Cambridge, UK: Cambridge Univ. Press, 1989.
R. Schaumann M. A. Soderstrand K. R. Laker Modern Active Filter Design, New York: IEEE Press, 1981.
W. Heinlein H. Holmes Active Filters for Integrated Circuits, New York: Springer-Verlag, 1974.

KENDALL CASTOR-PERRY
Burr-Brown Corp.
J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering
Copyright
c 1999 John Wiley & Sons, Inc.

PULSE-SHAPING CIRCUITS
Digital communications systems such as wireless, optical, and wireline telecommunication networks have
numerous well-known advantages over analog systems. These systems format binary data into discrete time
symbols, modulate the carrier using some form of digital modulation scheme (modulation in this simplified
context includes symbol modulation and up-conversion to a carrier frequency) to convert them to transmittable
continuous-time signals, and transmit them over a channel. At the receiver the received signal is demodulated
(demodulation includes both down-conversion and symbol demodulation), symbol timing is recovered, and the
received symbols are reformatted into a usable form. This process is shown in simplified form in Fig. 1.
The discrete time symbols of a digital communication system are of duration T and are sequential, that
is, they are orthogonal in time. To preserve the fixed time duration of symbols generated in the transmitter
would require infinite bandwidth in the signal processing of the communication system and the communication
channel. Finite bandwidth processing causes the symbols to spread in time. This causes the symbols to overlap
in time and induces intersymbol interference (ISI).
As will be described in the next section, even when finite bandwidth signal processing is used in the
communication system, the effects of ISI could be eliminated if ideal signal processing components (brick
wall filters as an example) could be implemented. This is of course not possible. Pulse shaping is used in the
implementation of digital communication systems to minimize ISI caused by nonideal channel characteristics
and nonideal component implementations.
Pulse shaping is performed in the transmit and receive filters of a communication system. The most
common class of filters used for pulse shaping are Nyquist filters (1,2,3). This article gives an overview of the
theoretical foundations of pulse-shaping and describes some practical implementations of pulse shaping filters.
The material in this article assumes that the communication channel can be modeled as a linear time-invariant
filter with additive white Gaussian noise (AWGN). For more detailed and in-depth coverage of pulse shaping
the reader is referred to Refs. 1 to 3.

Theoretical Background

Ideal data symbols are of fixed duration T. The spectrum for such a symbol is of the form

1
2 PULSE-SHAPING CIRCUITS

Fig. 1. Simplified block diagram of a digital communication system.

Fig. 2. General form of a pulse shape for an ideally band-limited symbol.

Thus such a symbol would require infinite bandwidth, which is of course impractical. Real communication
channels are of fixed bandwidth W. The ideal band-limited channel response (1) is

The transmit filter, which is designed to shape the transmit symbols to meet the power spectrum con-
straints of the channel, has an ideal frequency-domain response (1) of

The time-domain transmit filter response is therefore

This response is referred to as the pulse shape. hT (t) is the familiar sinc function, which has zero crossings
at integer multiples of Wt except at Wt = 0 where it has a value of 1. If we assume a symbol sequence Sn and
set T = π/W, then the pulse for each symbol is of the form shown in Fig. 2 for a single pulse and in Fig. 3 for
multiple pulses.
From Fig. 3 it is obvious that if symbols are sampled at times t = nT, where n is an integer, the effects of
ISI are mitigated. This is because the contribution to the composite waveform is zero for all pulses except for
the pulse corresponding to S 0 because they are all at a zero crossing point.
The problem is that to produce hT (t) = sin(Wt)/Wt requires an ideal brick wall filter, which is impossible
to implement. One could attempt to approximate the ideal filter but this would not be cost effective and would
 PULSE-SHAPING CIRCUITS 3

Fig. 3. Multiple pulse shapes for an ideally band-limited symbol.

have other undesirable effects on the system such as making timing recovery difficult (1). To address these
problems, more practical pulse shapes have been developed.
The pulse shape at the input to the demodulator, hp (t), is the convolution of the transmit filter, the channel
response, and the receive filter, that is,

From our preceding discussions it is clear that to eliminate ISI, hp (t) should be forced to cross zero at
nonzero integer multiples of T. This can be written as

The composite input to the demodulator is

where N R (t) is the noise input at the demodulator, that is,

From Eq. (1) it can be seen that forcing the composite pulse to cross zero does not necessarily produce an
optimal solution because it ignores the noise contribution. Joint optimizations are possible but they are beyond
the scope of this discussion. The reader is referred to 1 for in-depth coverage of this subject matter.
Taking the Fourier transform of Eq. (6) and applying the Nyquist sampling theorem, we get

Equation (9) is referred to as the Nyquist criterion, and filter responses (pulses) that meet this criterion
are referred to as Nyquist filters (pulses).
These filters require more than the ideal bandwidth defined in Eq. (3). While simplifying the system
implementation, this additional bandwidth requirement costs additional spectrum and noise bandwidth at the
4 PULSE-SHAPING CIRCUITS

receiver. The additional bandwidth is referred to as excess bandwidth and is usually expressed as a percentage
of the ideal bandwidth, that is,

The actual pulse shape used in a particular application is highly dependent on the targeted channel
characteristics. The most commonly used filters satisfying the Nyquist criterion for pulse shaping are raised
cosine filters. For this reason raised cosine pulse shaping will be used in this article to describe implementations.
Raised cosine filters are of the form

where α controls the rate at which the energy rolls off. The smaller α is, the faster the roll off. Note that for
α = 0,

which is the ideal pulse shape for a band-limited channel.

In most actual implementations the raised cosine filter is partitioned with part of the response imple-
mented in the transmit filter and part implemented in the receive filter. The most common partitioning is to
implement each as the square root of the raised-cosine filter. This is commonly referred to as a root-raised-cosine
filter (1) and is given as
 PULSE-SHAPING CIRCUITS 5

Fig. 4. Pulse-shaping process in a digital transmitter.

and

Implementation

In contemporary digital communication systems it is often not possible to achieve economically the required
performance from analog pulse-shaping filters. Shaping filters are therefore implemented using a hybrid
approach. The bulk of the shaping is done at baseband using finite impulse response (FIR) digital filters, which
implement a truncated version of the pulse shape.
On the transmit side of a communication system data symbols are passed to an interpolating digital filter
(4). The impulse response of the digital filter typically spans multiple symbol times and is the convolution of
the desired pulse-shaping response and precompensation for the roll-off frequency response of the subsequent
digital-to-analog converter (DAC) if the roll-off is great enough to affect system performance. The output of the
digital filter is passed to a DAC and a subsequent image reject filter for conversion to continuous-time analog
format. The output of the DAC in the spectral domain is the baseband spectrum and images of the baseband
spectrum occurring within bands, which are bounded by integer multiples of one-half of the sampling rate f s ,
all multiplied by a sinc function with nulls occurring at integer multiples of the sampling rate. In the case of
low-pass signals the images are present near integer multiples of the sampling rate. In the time-domain the
output waveform is “stair stepped.” The image reject filter removes all of the spectral images and passes the
baseband spectrum, thus “smoothing” or interpolating the time-domain waveform.
At the output of the image reject filter, the shaped symbol pulses are in continuous-time analog format.
They can then be up-converted to the desired radio frequency (RF) for transmission. This process is shown in
Fig. 4.
The operation at the receiver is the transpose of the transmit operation. The analog front end (AFE) of
the receiver translates the RF signal into a convertible pulse train. The pulse train is then converted to a
digital form via an analog-to-digital converter (ADC). The pulse train is filtered by a decimating FIR filter (4)
with a root-raised-cosine response to complete the raised-cosine pulse-shaping operation. The receive process
is shown in Fig. 5.
6 PULSE-SHAPING CIRCUITS

Fig. 5. Pulse-shaping process in a digital receiver.

Digital Pulse-Shaping Network. The actual design procedure for a pulse-shaping network is now
presented. A transmit-side root-raised-cosine pulse-shaping network is described. The receive-side network
will not be addressed since it is the network transpose of the transmit network.
Assume a digital data transmission system has a symbol period of T seconds, that is, every T seconds a
new b Q bit symbol is transmitted. In this description we assume bQ = 1 for simplicity of illustration, although
this is not necessary. Before transmission, it is necessary to shape each transmitted pulse. In this case a positive
pulse shape is transmitted for a bit value of one, and a negative pulse is transmitted for a bit value of zero. In
addition to considering the desired pulse type, it is necessary to determine the length of the pulse relative to
the symbol length and the resolution of the pulse or the number of bits used to compute the pulse values.
The interpolating FIR filter shown in Fig. 4 must be economically implementable and can therefore only
approximate a desired pulse shape, the root-raised cosine given by Eq. (14) in this case. The response is
approximated by first determining the desired filter length. The filter length N is the product of the symbol
interpolation factor L and the desired span M. The span is the number of symbol periods over which the shaping
filter will operate.
The interpolation factor is selected to minimize the sinc(x) distortion at the upper edge of the band
of interest caused by the DAC and to simplify the implementation of the image reject filter: the greatest
consideration is the latter. As was mentioned previously, sinc(x) distortion in the band of interest can be
compensated for by putting a precompensation function [1/sinc(x)] in the interpolating filter’s response. The
higher the interpolation rate, the more distance there is between the band of interest and the first image in
the spectral domain. The more distance there is, the simpler the image reject filter. Thus the interpolation
factor becomes a trade-off between the complexity of the digital interpolating filter and DAC speed, and the
complexity of the image reject filter. Typically, an interpolation factor of between 8 and 16 is a reasonable trade.
The span over which the impulse response is approximated depends on the amount of out-of-band energy
that can be tolerated. An ideal impulse response begins to approach zero after a number of time-domain side
lobes. However, the synthesized impulse is of finite duration. How closely the tails of the response approach
zero is dependent on the length of time the impulse is approximated. Out-of-band energy is reduced as the
span increases so the trade-off becomes filter order versus out-of-band energy due to time-domain side-lobe
truncation. Typical values of the span factor are 4 to 16. A typical root-raised-cosine pulse shaper would have
an interpolation factor of 8 coupled with a span of 8 to yield a total filter length of 64.
Filter Coefficient Calculation. There are a number of possible methods for calculating the coefficients
of the pulse-shaping filter. Two will be discussed here: the direct and optimal methods.
The Direct Method.. An FIR digital filter is of the form
 PULSE-SHAPING CIRCUITS 7

The direct method samples the continuous-time impulse response at appropriate points in time to generate
the filter coefficients a. Under the assumption of proper sampling

where H D (z) is the desired frequency-domain pulse shape and N − 1 is the filter order.
As stated previously, the total number of coefficients, N, is related to the span and interpolation factors
by N = LM. Thus, continuing with the root-raised-cosine example one would simply calculate N evenly spaced
values using Eq. (14) to calculate the coefficients a n . Since hT (t) is an even function about t = 0, it is necessary
to shift hr (t) in time such that the sampled version of hT (t) [ denoted by h(n) ] is evenly symmetric around
samples (N − 2)/2 and N/2 to ensure a fully linear phase response (5). Since there are L samples per symbol
period T, h r (t) should be evaluated at integer multiples of T/L. This, along with the time-shift requirement,
dictates that the discrete-time values necessary to define h T (t) are given by

Substituting this into Eq. (14) gives the sampled version of h T (t),

This process is illustrated in Fig. 6 for a filter of length N equal to 64 and including 4 12 side lobes on either
side of the main lobe of the root-raised-cosine function. Figure 7 shows the corresponding frequency-domain
response of the pulse-shaping filter.
As is the case with any digital filter coefficient design method, once the floating-point coefficients are
calculated, they must be converted to fixed-point format if the target digital filter is to be implemented in fixed-
point arithmetic. Conversion of coefficients to fixed-point format can be as simple as truncation or rounding or
can require sophisticated optimization processes. Let

be the quantized coefficients. The next step in the coefficient design process is to calculate the frequency
response of the quantized filter coefficients and compare it with the desired frequency response to see if the
filter is within acceptable error bounds. The frequency response of an FIR filter is found by evaluating the
filter’sz transform on the unit circle. That is, the magnitude frequency response of the quantized coefficients is
8 PULSE-SHAPING CIRCUITS

Fig. 6. A discrete time sampled root raised cosine.

Fig. 7. Frequency-domain response of the sampled root-raised cosine shown in Fig. 6.

given as

H
(z) can be evaluated directly or by using a form of the DFT. If the filter’s frequency response does not meet
the required error bounds, then either the filter order N or the number of bits in the coefficient quantization
must be increased and the appropriate steps in the coefficient design process must be repeated.
Coefficient quantization is not as straightforward as data quantization. The quantization of data words
yields 6.02 dB of signal-to-noise ratio per bit. The number of bits required for coefficient quantization is a
function of filter order and the frequency-response shape. A good rule of thumb for a worst-case metric (6) for
 PULSE-SHAPING CIRCUITS 9

the number of coefficient bits required is

so that

assuming no limiting roundoff error in the actual filter implementation. In most practical pulse-shaping filter
implementations, the coefficient word length should be closer to the lower bound.
The floating-point coefficients (a) for the case M = L = 8 are shown in matrix form. Each column represents
samples in adjacent symbol periods. Since the impulse response spans eight symbol periods, there are eight
corresponding columns.

In converting the floating-point coefficients to fixed-point coefficients, maximum arithmetic efficiency can
be obtained by scaling the fixed-point coefficients so that the maximum possible filter output is at the overflow
threshold. Worst-case peak signals would occur for data patterns in which the maxima and minima of the
impulse response overlap, or add (in the case of a negative pulse, the absolute value of the minima adds to the
composite pulse). It turns out for the example here that an efficient peak value for the impulse response to
take is 194 for a 9-bit integer two’s complement representation (maximum possible positive value of 255).
10 PULSE-SHAPING CIRCUITS

Fig. 8. Illustration of the conceptual interpolation process.

Scaling the matrix of the floating-point values to a peak value of 194 and rounding each coefficient to the
nearest integer results in the coefficient set shown here, which completes the synthesis of the pulse coefficients.

The Optimal Method.. The optimal method requires an optimizing filter design program such as the
Parks–McClellan program (5,7) but guarantees an optimum solution. To design the pulse-shaping filter coeffi-
cients using the optimal method the EFF subroutine (EFF is the actual name of the subroutine in the published
program) in the Parks–McClellan computer design program must be modified by inserting a floating-point,
discrete-frequency version of the desired frequency- domain pulse shape. The program is then executed with
a desired filter order and the same iterative process of evaluating the frequency response of the quantized
coefficient set as described previously for the direct method is followed until a set of coefficients is generated
that is within the desired error bound. This method yields much more reliable results than the direct method.
Even more sophisticated filter programs exist that optimize quantized coefficients. These programs allow
designers to optimize the efficiency of a filter implementation.
Filter Hardware Implementation. The actual hardware realization of a pulse-shaping filter is highly
dependent on symbol rates, filter order, process, etc. Assuming symbol rates that allow implementations in
state-of-the-art semiconductor processes, the filter would be implemented as some variation of a polyphase
architecture (4).
Interpolation is the process of increasing the sampling rate while preserving the signal’s spectral content.
The conceptual first step in interpolation is to insert L − 1 zero-valued samples between each valid input
sample, expanding the sampling rate by L. This causes the original signal spectrum to be repeated L − 1 times.
This process is referred to as sample rate expansion. To complete the interpolation, the zero-valued input
samples are converted to spectrally accurate approximations of the signal. This is equivalent to preserving the
original signal spectrum. Thus, and again conceptually, the zero-stuffed input stream is filtered by a low-pass
filter with a passband at the original spectral location and a passband gain of L. This filters out all of the
repeated spectra. This conceptual process is shown in Fig. 8.
In real implementations it would be a waste of storage and computational resources to store and multiply
zero-valued data samples. For this reason, polyphase structures are used. A polyphase interpolator configures
 PULSE-SHAPING CIRCUITS 11

Fig. 9. Polyphase implementation of an FIR interpolation filter.

the standard N-tap filter structure into k phases of an (N − 1)-element delay line. For example, an eighth-order
(N = 9) FIR filter with k = 3 phases has three sets of three coefficients. The coefficients for the eighth-order
filter are a0 , a1 , . . ., a8 . The first polyphase taps the eight element delay line at the input to the filter (a0 ), after
the third delay (a3 ), and after the sixth delay (a6 ). The second phase taps a1 , a4 , and a7 . The third phase taps
a2 , a 5 , and a8 . However, since all but every third element in the delay line would contain a zero-valued data
sample, the delay line can be collapsed to a two-element delay line (N/k − 1 elements) with all phases using the
same samples. The output of the interpolator is the commutated output of the three phases. Figure 9 illustrates
the polyphase implementation of the nine-tap interpolator. Reference 4 details the efficient implementation of
interpolation and decimation filters.
An interpolation filter can be implemented using standard multiply and accumulate elements, or in some
cases it is most efficient to use table look up based bit-slice filter methods (8). The trade-off is dependent on
12 PULSE-SHAPING CIRCUITS

the number of bits required for the representation of a symbol. For low-bit count, the bit-slice implementation
is usually more efficient. As bit count increases, table sizes become unmanageable.

DAC

The DAC has the task of generating an analog output based on the digital input supplied by the FIR filter.
The DAC must be linear to ensure no unwanted spurious energy is generated. Several implementations are
possible depending on the DAC resolution required. For relatively modest resolutions of 4 to 8 bits, simple
binary weighted current or charge-based approaches are possible. For higher resolutions, it may be desirable
to use segmented approaches where each least significant bit (LSB) step has a separate current- or charge-
based generator. For example, a 5-bit segmented current-steered DAC would have 32 separate current sources
feeding a common resistor to generate the desired output voltage. Sources are turned on or off depending on
the value of the control word. This is opposed to a binary approach in which only five current sources are used
scaled in binary fashion. For higher-bit resolutions, the binary approach can suffer from linearity errors due to
mismatches at major carries. The advantage of a binary approach is smaller implementation area. For DACs
of 9-bit resolution or higher, a combination of binary [for the most significant bits (MSBs)] and segmented (for
the LSBs) is frequently used.
Standard DACs offer no image suppression, even if the DAC runs at a rate greater than the digital
word update rate. Image suppression could be improved if the DAC could interpolate between successive word
updates. Such a converter can be demonstrated, following up on the example begun for the pulse-shaping
network. Suppose specifications require that all spurious energy be at least 40 dB down with respect to the
baseband level. This requires that all spectral images of the FIR filter be attenuated sufficiently to achieve this.
Further suppose that the symbol rate is 128 kbaud. The update rate f s of the digital filter is 1.024 MHz (due
to the 1:8 interpolation factor from the preceding example), and hence the first image replica will appear there.
If the DAC were updated at the 1.024 MHz rate, then the amount of attenuation of the image due to roll off
is only 17 dB. Consider an interpolating DAC operating at five times the digital update rate (f s1 = 5.12 MHz).
The block diagram of an architecture suitable for monolithic integration accompanied by illustrative spectral
plots is shown in Fig. 10. In this architecture, it is shown that interpolation can provide 20 dB of additional
attenuation.
A simplified single-ended schematic of an interpolating DAC is shown in Fig. 11 (9). φ and φ2 are nonover-
lapping clocks operating at the interpolation frequency (5.12 MHz in the preceding example). The operational
amplifiers are conventional fully differential folded cascade topologies. The input voltage reference is selected
based on specific channel requirements and typically ranges from 250 mV to 1 V. It is usually supplied by an
on-chip band-gap generator. The configuration is a cascaded charge redistribution DAC with the first stage
an offset insensitive programmable amplifier to realize the four least significant bits (10). Gain is determined
by the sum of the binary weighted capacitors at the input, dependent on the LSB word. The second stage
is a modified second-order switched-capacitor biquad (11). This stage has programmable gain to realize the
four most significant bits of the DAC and acts as the summing point for the LSB portion. A straightforward
charge-transfer analysis yields the low- frequency output level as a function of the reference voltage V ref and
critical circuit capacitor values
 PULSE-SHAPING CIRCUITS 13

Fig. 10. Digital-to-analog converter top-level block diagram.

Here, b0 , b 1 , . . ., b 7 represent the digital data (possible values of 0 or 1) with b 7 as the least significant
bit. Since the DAC is fully differential, the sign bit is easily incorporated by cross-coupling the input connection
to V ref . Interpolation is accomplished by the fact that the final stage is really a switched-capacitor filter. dc
and ac analysis is simplified by replacing the DAC capacitor array structure with an equivalent single-ended
switched-capacitor network as shown in Fig. 12. Including the input offset voltages Voff2 , Voff3 for the operational
amplifiers, the defining charge equations for this network are given by

where V o2 and V o3 are outputs of amplifiers 2 and 3, respectively.

14 PULSE-SHAPING CIRCUITS

Fig. 11. Simplified single-ended DAC schematic.

Fig. 12. Interpolating filter.

Under steady-state conditions n→ ∞. With V in (n) = V in (n−1) = 0, then

where V o2 and V o3 are the dc offset voltage at the outputs of amplifiers 2 and 3, respectively. Under these
conditions, solving Eqs. (27) and (28) yield the output offset voltages for the DAC,
 PULSE-SHAPING CIRCUITS 15

where Eq. (31) is valid during high φ1 . It is interesting to note that although the DAC output is a fully held
signal over the 5.12 MHz clock period, it has no operational-amplifier-induced dc offset. This is simply due to
the fact that output offset at this point is due solely to amplifier 2, which has been nulled out.
Ignoring offset, Eqs. (27) and (28) may be transformed to the z domain, where the following transfer
function may be derived:

This is the form of a second-order low-pass filter. Interpolation is accomplished by designing the filter such that
little passband loss occurs at the digital filter’s 3 dB point of 64 kHz. Setting specifications for the interpolating
filter at no more than 0.3 dB loss at 100 kHz; then with a sampling frequency of 5.12 MHz, this leads to a
desired transfer function of

Coefficient matching with Eq. (32) yields the necessary capacitor values. With 17 dB of loss due to the S/H effect
and the loss at 1.024 MHz due to Eq. (33), the image at the DAC output is 37 dB lower. Hence, an additional
20 dB of image rejection is achieved with the use of interpolation techniques.
Image Filter. There are several techniques that are used to realize continuous-time monolithic filters.
Standard active filter techniques utilizing resistors and capacitors are the simplest approach but pole frequen-
cies cannot be accurately placed due to typical process variations. If the image response is located very far away
from the baseband spectrum, then accurate pole placement may not be necessary. In that case, the filter is
simply designed such that the worst-case RC product leading to a high cutoff frequency is still sufficient to meet
stopband energy requirements. Frequently, only first-order filters are required, but if the passive variation is
significant enough, higher-order filters may be necessary to provide sufficient attenuation. If a process has
very linear components, such as thin-film resistors and double polysilicon or metal capacitors, it is possible to
realize wide dynamic range filters with excellent linearity. Dynamic ranges over 93 dB are possible if linearity
is a concern. If only diffused resistors or depletion capacitors are available, then the corresponding voltage
dependence of the passive devices reduces linearity considerably. In that case, interpolating DAC techniques
may be desirable such that only a simple external RC filter is necessary for image filtering. Of course linearity
requirements must be considered to make a final decision.
Another technique that may be used includes MOSFET-C (metal oxide semiconductor field-effect tran-
sistor capacitance) filters (12), where MOSFET transistors operated in the linear region are used to replace
resistors in active filters. Using special linearization techniques, MOSFET-C filters can achieve reasonable
linearity (50 dB to 60 dB) and no special resistor material is required. However, MOSFET-C filters are limited
in the frequency range that they can operate due to operational amplifier limitations and distributed parasitics
(13). They also require the use of tuning networks to ensure that the MOSFET devices stay in the linear region
and close to the resistor values necessary to achieve the necessary time constants.
Finally, transconductance-C (g m –C) networks can be used as image filters (14). g m –C filters have the
advantage of being able to achieve very high cutoff frequencies, typically in the 10 MHz to 100 MHz area.
These may be useful in cases where data rate is very high and image frequencies may be close to baseband.
16 PULSE-SHAPING CIRCUITS

Linearization techniques can achieve dynamic ranges in the area of 50 dB to 65 dB. g m –C filters have pole
frequencies proportional to g m /C, so stable transconductance networks are required to achieve stable pole
locations. Usually, this implies some sort of tuning network to accurately set gm for the desired cutoff.

Summary

In this article an overview of the motivation, theory, and implementation of pulse shaping in digital commu-
nication systems has been presented. Digital communication systems transmit digital data as discrete-time
symbols modulating a continuous-time waveform. Because actual communication channels are band limited,
symbol times can overlap, inducing intersymbol interference. Pulse shaping can reduce or eliminate intersym-
bol interference if it is closely matched to the characteristics of the channel.
A theoretical background for pulse shaping was established based on a channel that can be modeled as
a linear time-invariant filter with additive white Gaussian noise. It was shown that for this type of channel a
class of filters known as Nyquist filters are the most commonly used for pulse shaping and the most popular
filter in this class is the raised cosine filter. Since the implementation of pulse shapers are commonly distributed
between the transmit and receive sides of a communication system, an example of the implementation of a
transmit-side square-root-raised-cosine filter was presented.
The square-root-raised-cosine filter implementation presented was a hybrid analog and digital implemen-
tation, taking advantage of the strengths of both technologies.

BIBLIOGRAPHY

1. E. A. Lee D. G. Messerschmitt, Digital Communication, 2nd ed., Norwell, MA: Kluwer Academic, 1994.
2. B. Sklar, Digital Communications, Fundamentals and Applications, Englewood Cliffs, NJ: Prentice-Hall, 1988.
3. R. E. Ziemer R. L. Peterson Digital Communications and Spread Spectrum Systems, New York: Macmillan, 1985.
4. R. E. Crochiere L. R. Rabiner, Multirate Digital Signal Processing, Englewood Cliffs, NJ: Prentice-Hall, 1983.
5. L. R. Rabiner B. Gold, Theory and Application of Digital Signal Processing, Englewood Cliffs, NJ: Prentice-Hall, 1975.
6. G. A. Mian A. P. Nainer, On the performance of optimum linear phase low-pass FIR digital filters under impulse
response coefficient quantization, IEEE Trans. Acoust. Speech Signal Process. ASSP-29: 925–932, 1981.
7. T. W. Parks McClellan, A program for the design of linear phase finite impulse response digital filters, IEEE Trans.
Audio Electroacoust., AU-20: 195–199, 1972.
8. F. J. Taylor, Digital Filter Design Handbook, New York: Dekker, 1983.
9. B. A. Myers et al., A frequency agile monolithic QPSK modulator with spectral filtering and 75  differential line
driver, IEEE J. Solid State Circuits, 33: 1394–1405, 1998.
10. R. Gregorian G. Temes, Analog MOS Integrated Circuits for Signal Processing, New York: Wiley, 1986, pp. 414–416.
11. R. Gregorian, Switched capacitor filter design using cascaded sections, IEEE Trans. Circuits Syst., CAS-27: 515–521,
1980.
12. Y. Tsividis, M. Banu, J. Khoury, Continuous-time MOSFET-C filters in VLSI, IEEE J. Solid State Circuits, SC21:
15–30, 1986.
13. J. Khoury Y. Tsividis, Analysis and compensation of high frequency effects in integrated MOSFET-C continuous-time
filters, IEEE Trans. Circuits Syst., CAS-34: 862–875, 1987.
14. K. Laker W. Sansen, Design of Analog Integrated Circuits and Systems, New York: McGraw-Hill, 1994, pp. 652–657.

BRENT A. MYERS
DAVID B. CHESTER
Intersil Corporation
220 RAMP GENERATOR

RAMP GENERATOR C

Vref
Ramp generators are found in many circuit applications – R
where a linear change of some voltage is required. For exam- –
ple, ramp voltages are used to generate the x and y scan volt- +
R1 +
ages in a CRT or in electronic motor controllers. A voltage
VS Vo
that rises or falls linearly in time can be generated very sim-
ply, by charging a capacitor at a constant rate over a period
of time. When a capacitor is charged from a simple voltage R2
source Vo, via a series resistor R, the voltage on the capacitor
rises according to the well-known exponential relationship
VC ⫽ Vo(1 ⫺ e⫺t/RC). This voltage is not a linear ramp, because Vo
the charging current is not constant. To render the ramp volt-
age linear, a constant current source must be substituted for
the resistor-voltage source combination, to provide the de-
VM
sired linearity. Now all that is required is a system of control-
ling the pattern and rate of capacitor charge and discharge,
to determine whether the circuit is a triangle-wave or saw- t
tooth-wave generator. T1 T2

Figure 2. Triangle-wave generator using an integrator and showing

GENERATING A RAMP VOLTAGE
the relationship between T1 and T2.

The next sections contain some examples of how practical cir-

cuits might be constructed using comparators, discrete com-
ponents and a 555 timer. The ramp period in all of these cir- circuit works by feeding back the output voltage Vo via the
cuits is effectively calculated from the magnitude of the resistor R to provide a current that charges and discharges
voltage swing, the magnitude of charging current, and the the capacitor C in an oscillatory manner. Whenever the out-
value of timing the capacitor, although, in those circuits, em- put changes state, the positive input to the comparator snaps
ploying integrators it is convenient to use the expression for to a new value, above or below earth potential, providing the
the integrator output in the derivation of output period. regenerative action. The changing VC causes the differential
input to become less and eventually to change sign, at which
Non-linear Ramp point the output changes state again. If one looks at the ca-
pacitor voltage, VC, also shown in Fig. 1, one can see that this
Consider the square wave generator circuit based on a regen-
is an approximation to a triangle wave, but is not linear as
erative comparator (Schmitt Trigger) shown in Fig. 1. This
explained above.
An operational amplifier integrator circuit can be used to
R ensure that the capacitor charging current is constant and
Vc Vo the linear ramp output of the circuit then only need be fed
+VA back to the comparator input to produce a circuit that is si-
–
multaneously a square wave and triangle-wave generator.
+ This approach requires just one further change to the circuit.
–VA R1 Since an integrator is an inverting circuit, such feedback will
C produce a ramp voltage on the comparator that is in anti-
phase with that required to make the two inputs converge,
R2 and can be corrected by connecting an inverting buffer be-
tween the integrator and the capacitor.

Triangle-Wave Generator
Vc
A slightly different approach has been taken in the circuit
βVA
shown in Fig. 2. The square-wave output of the comparator is
t applied to an integrator as described, but the integrator out-
–βVA put is then fed back to the noninverting input of the compara-
tor rather than the inverting input, thus eliminating the need
for an additional inverting buffer (1,2). The frequency of the
Vo
output, f o, for this circuit is (2):
VA

t R1 VS2
fo = 1− 2 (1)
—VA 4R2 RC VA

Figure 1. Square-wave generator showing the presence of a nonlin- The median point of the output waveform is set according to
ear ramp voltage on the timing capacitor. Eq. (2) and the ratio of ramp-up and ramp-down periods,

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

T1 : T2, is set by Eq. (3), where the comparator output switches
between ⫾VA (2).

R + R2
 RC1
1
VM = Vref (2)
R1
T1 V + VS
= A (3)
T2 VA − VS
Even though the T1 : T2 ratio can be varied widely, this circuit
is not such a good choice if a sawtooth waveform is required,
since either T1 or T2 is then required to be zero. If a single
ramp is required rather than the repetitive output provided
by this circuit, it can be easily converted to monostable opera-
tion (1).
This circuit has a useful operating frequency range up to
about 40 kHz, with the limit set by the comparator output
slew rate. A general purpose operational amplifier can easily
be used here, but for higher frequency operation a high slew
rate device, such as an LM6365, can be used to extend the
maximum frequency (depending on the voltage swing re-
quired). However, it should be noted that bipolar operational
amplifiers do not generally provide full rail to rail output volt-
age swing, which can lead to drift in the Schmitt Trigger
thresholds, so for general use, an FET output operational
amplifier which does give full rail to rail voltage swing is a
better choice.
Current Source-Controlled Circuit
The direct approach, shown in the circuit of Fig. 3, uses one
current source to charge the timing capacitor and a second to
discharge it, so that the rising and falling slopes are set by
the ratio of the current sources. The charge and discharge of
the capacitor is once again controlled by a regenerative com-
parator, this time connected to a complementary pair of
switches. When the comparator output is high, S1 is closed,
allowing C to be charged by I1, while S2 is open. When the
differential input to the comparator changes sign, its output
changes state and S2 is closed, while S1 is open, and C can be
discharged via I2, until the comparator differential input
changes sign again. This circuit can be easily used for saw-
tooth generation, since one or the other of the current sources
S2 S1
+VS
Vo I1
– turning Q2 off and Q3 on again.
+ This configuration has one disadvantage, in that Q4 must
I2 R1
C current from Q1. Q4 must accommodate both of these currents,
R2
–VS
Figure 3. Ramp voltage generator using current source switching for
triangle or sawtooth output, showing the action of S1 and S2 to charge
and discharge C.
RAMP GENERATOR 221
VCC
RC2 RC3
R1
Q1
R2 Q2 Q3
RBB
Q5 REE
Vo
C
–VEE VBB
RE5 Q4
Figure 4. Sawtooth generator constructed from discrete components
which also makes use of a (single transistor) current source.
can be omitted and replaced by a short circuit, so that C can
be charged or discharged using a very short time constant
circuit. The current sources themselves could be either simple
current regulator connected BJTs or FETs, or a more complex
current regulator device, depending on the accuracy and sta-
bility required. Once again, the maximum useful operating
frequency is set by the comparator output slew rate, but may
be pushed beyond the normal operating range of the compara-
tor if great accuracy is not required (and also no use is being
made of the square-wave output). Note that if the output is
driving a low impedance load, a buffer circuit will be required
to prevent load current from affecting the charge and dis-
charge rates of C.
Sawtooth Circuit Using Discrete Devices
It is usually simpler to use operational amplifier-based cir-
cuits, where the specifications allow, but their slew rate limit
can be overcome by using discrete components, and one im-
plementation of a sawtooth generator is shown in Fig. 4. The
p-n-p Q1 is configured as a current source, but a more accu-
rate current regulator circuit could be substituted, if required.
The collector current from Q1 charges the timing capacitor,
C, with the capacitor voltage used as the input to the differen-
tial pair Q2 and Q3 connected as a Schmitt Trigger. Initially,
let Q2 be off and Q3 be on. When the voltage on the base of
Q2 rises above that on the base of Q3, the circuit switches
regeneratively, so that its output at the collector of Q3 goes
high. This output, in turn, switches on Q4 and discharges C
conduct both the discharge current from C and the charging
and the discharge of C is thus slowed. A useful modification
is to use the Schmitt Trigger output from the collector of Q3,
to set the base voltage on Q1, so that it switches on and off in
antiphase with Q4, but output levels of the Schmitt Trigger
must be compatible with the bias requirements of Q1.
The input switching levels for the Schmitt Trigger can be
varied by changing VBB, allowing the circuit to be used as a
voltage to frequency converter if desired, since the time taken
222 RAMP GENERATOR

– C
+ Q1 Q2
R1 R
V3
+Vi –
–Vi Vo
+
R2
R3

+
Figure 5. Voltage-controlled circuit for triangle-wave R3
generation illustrating the use of a CMOS inverter to Vi
integrate the correct polarity of the input voltage Vi.

for the capacitor voltage to ramp to the switching point will tooth circuit, which makes use of the THRESHOLD (TH) and
vary. Q5 is simply an emitter follower to buffer the load. TRIGGER (TR) inputs and the DISCHARGE (DIS) terminal
(3). The capacitor C is charged via the p-n-p transistor work-
VOLTAGE-CONTROLLED ARCHITECTURES ing as a current source. When the voltage on the capacitor is
high enough to activate the TH input, C is discharged quickly
Some of the circuits can be modified to operate in voltage- through the DIS pin (achieved by turning on an internal dis-
charge transistor). When the voltage on C has fallen to the
controlled mode, an example of which is shown in Fig. 5, and
value that activates the TR input, the discharge transistor is
is based on the triangle-wave generator from Fig. 2. Here the
turned off and the cycle begins again. The voltage on the
comparator output controls two MOS transistors, Q1 and Q2,
capacitor is therefore a sawtooth wave, which varies between
acting as a CMOS inverter, effectively selecting either the
1/3 VCC and 2/3 VCC (in a 555 the TH input is activated for a
voltage on the n-channel source or the voltage on the p-chan-
voltage greater than 2/3 VCC and the TR input is activated for
nel source. The input control voltage, Vi, is applied to the p-
a voltage less than 1/3 VCC). A buffer is required as before to
channel source and its inverse is applied to the n-channel avoid loading the capacitor. The frequency of operation can
source, via the unity gain inverting amplifier. Thus the inte- be calculated from the values of VCC, C, and the current
grator is integrating ⫾Vi rather than the comparator output, source.
so that the slope rate of the integrator output now depends
upon Vi. Since the voltage required at the input of the com-
parator to cause it to switch is constant, the effect is that
output frequency, f o, depends on Vi and, where the compara- Vref
tor output switches between ⫾VA, is given by (2):
Voltage controlled
=
V 1 + R1 /R2 Rt current source (LM)
fo = i · (4)
VA 4RC
LM1
Note that the presence of the CMOS inverter circuit, in effect,
provides the additional inverter missing from the original tri-
angle-wave generator (as discussed above) and the feedback A
connection is brought to the inverting input of the comparator B
this time. The operation is once again limited by amplifier S1
slew rate and the frequency varies linearly over a reasonably
large range. Care must be taken, however, to ensure that Vi C
–
does not become too large; otherwise, the amplifier inverting
D
Vi will saturate and the circuit will not function correctly. +
Figure 6 shows a further approach, where the circuit is E Ct
S2
an extension of the current source-controlled circuit. Voltage-
controlled switches are switched between their open and F R1
closed states by the operational amplifier output. The capaci-
tor charge and discharge current is set by the voltage-con- R2
trolled current sources whose control voltage is determined LM2
by the input voltage Vi.
–Vref
USING THE 555 Input Vi Output Vo
Figure 6. Voltage-controlled circuit providing variable frequency tri-
555 integrated circuit components are used in many timing angle or sawtooth output using voltage-controlled current sources
circuits, as well as in ramp generators. Figure 7 shows a saw- switched to charge and discharge C.
 RANGE IMAGES 223

+15 V (VCC) drops below VCC. This would then leave insufficient voltage
across the current sources, to allow for conduction (about 1 V
R3 for the current regulator and a further 0.7 V for the gate-
4 8 drain diode). The CMOS 555, however, produces a full-range
R1
R VCC output swing.

6 3
R2 TH 555 BIBLIOGRAPHY
2
TR
7
DIS 1. J. Millman and C. C. Halkias, Integrated Electronics: Analog and
1 Digital Circuits and Systems, New York: McGraw-Hill, 1972.
= 50 µA
2. P. M. Chirlian, Analysis and Design of Integrated Electronic Cir-
+10 cuits, 2nd ed., New York: Wiley, 1987.
Vc
+ 3. P. Horowitz and W. Hill, The Art of Electronics, 2nd ed., Cam-
+5
bridge: Cambridge University Press, 1989.
C – Sawtooth
L. I. HAWORTH
A. F. MURRAY
Figure 7. 555 timer circuit for sawtooth-wave generation using a University of Edinburgh
transistor current source to charge C and the DIS terminal to dis-
charge C.

RANDOM ACCESS MEMORIES. See SRAM CHIPS.

If a triangle wave is required, the circuit of Fig. 8 can be RANDOMNESS. See PROBABILITY.
used (3), which operates in a similar way to the sawtooth cir-
cuit. It does not make use of the DIS pin, but does require a
bidirectional current source, which can be implemented as
two current-regulator-connected JFETs in series (e.g.,
1N5287, providing about 33 mA). Current flow is bidirec-
tional, because one JFET will regulate the current, while the
other behaves like a forward-biased diode, due to gate-drain
conduction, and the square wave output of the 555 is used to
drive the current sources. When the 555 output is at VCC the
capacitor charges up to 2/3 VCC, whereupon the output
switches to 0 V and the capacitor discharges to 1/3 VCC, caus-
ing the output to switch back to VCC again. Once again, the
output varies between 1/3 VCC and 2/3 VCC, and an output
buffer is required. Finally, if this circuit is used with a 5 V
power supply it is essential to use a CMOS 555 variant, be-
cause bipolar 555s typically have a high output, two-diode

+15 V (VCC)

4 8
R VCC

6 3
TH 555
2
TR

+10
Vc
+
+5
C – Triangle out

Figure 8. 555 timer circuit for triangle-wave generation which uses

two current-regulator-connected JFETs to provide charge and dis-
charge current for C.
302 RECTIFYING CIRCUITS

RECTIFYING CIRCUITS

Almost all electronic circuits need to utilize direct current (dc)

sources of power for operation. Hand-held and portable elec-
tronic equipment use replenishable or rechargeable batteries
as their main source of power. Normally, a power supply pro-
vides energy for all other electronic equipment. A power sup-
ply is composed of electronic circuitry that essentially con-
verts alternating current to direct current. Electronic circuits
designed to accomplish this conversion are known as rectify-
ing circuits (see Table 1). They are classified into three ma-
jor categories:

Half-wave rectifier (HWR)

Full-wave rectifier (FWR)
Bridge rectifier

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.
 RECTIFYING CIRCUITS 303

Table 1. Comparison of the Three Rectifier Circuits the valleys of the pulsating dc signal output of the rectifier
Half-Wave Full-Wave Bridge and strives to accomplish a ‘‘smooth’’ dc output. The voltage
regulator tries to maintain a constant output voltage regard-
Number of diodes One Two Four less of the fluctuations in the input ac signal and the output
Peak line voltage Vm Vma Vm
dc load current consumption. Main equations pertaining to
rms line voltage V m / 兹2 Vm / 兹 2 Vm / 兹 2
Peak inverse voltage Vm 2Vm Vm
the three rectifier circuits can be found in the Appendix 1, 2,
dc output voltage 0.318Vm 0.636Vm 0.636Vm and 3.
Ratio of rectification 0.406 0.812 0.812
Transformer utilization factor 0.287 0.693b 0.812
HALF-WAVE RECTIFIER CIRCUIT
Ripple frequency f 2f 2f
Ripple factor 1.21 0.482 0.482
The basic action of a simple half-wave rectifier circuit with a
a
One-half the secondary coil voltage. resistive load can be examined using a circuit shown in Fig.
b
Average of primary and secondary coils.
3(a). A semiconductor diode, a load resistor, and the second-
ary coil of a transformer are connected in series. The primary
coil of the transformer receives the ac input supply. Let the
At the present time, the silicon diode is the most commonly output voltage of the transformer secondary coil be repre-
used electronic device for rectification purposes. Semiconduc- sented as vi ⫽ Vm sin 웆t where vi is the instantaneous value
tor diodes have replaced previously used devices such as vac- of the voltage and Vm is the peak value. Furthermore, let us
uum tube diodes and dry-disk or metallic rectifiers. Figures assume that the forward voltage drop of the diode is very
1(a) and 1(b) show the constructional features of four types of small (0.7 V for silicon and 0.3 V for germanium) compared
rectifiers that can be used to accomplish the task of con- to the input signal. We find the relation i ⫽ id ⫽ iR, where i is
verting alternating current (ac) to dc. The principle of rectifi- the current in the transformer secondary coil closed circuit,
cation is to permit current flow in one direction only. The di- id is the diode current, and iR is the current in the resistance
ode is capable of accomplishing this task because it conducts R. The diode offers a resistance Rf while conducting in the
only when it is forward biased. This means that the anode or ‘‘on’’ state and offers infinite resistance while not conducting
the positive electrode of the diode receives positive voltage. in the ‘‘off ’’ state. Therefore, mathematically speaking, the
When the cathode or the negative electrode is connected to the half-wave rectifier obeys the following equations:
positive supply terminal, the diode is reverse biased. Thereby 
id = iR = Im sin ωt if 0 ≤ ωt ≤ π
the diode can be used in an appropriate circuit, called a recti- i=
fier circuit, to convert an alternating waveform to a unidirec- 0 if π ≤ ωt ≤ 2π
tional waveform. While discussing rectifier circuits through-
out this article a sinusoidal waveform is considered as input, where Im ⫽ Vm /(Rf ⫹ R).
for convenience of mathematical treatment. Figures 3(b) and 3(c) represent the input and output wave-
A rectifying circuit is normally used in conjunction with a forms. It is observed that the output load resistance experi-
transformer, filter, and a voltage regulator. Figure 2 shows a ences only one half cycle for every one full cycle of input wave-
block diagram representation of a power supply. The trans- form. The average value of one full cycle of the input
former reduces or increases the amplitude of the ac voltage so waveform can easily be computed to be equal to zero. Simi-
that appropriate dc magnitude is obtained after rectification larly, the average value of the output dc current can be calcu-
filteration and regulation. In addition, the transformer pro- lated by considering one full cycle of the output waveform. It
vides electrical isolation that may be necessary. The rectifier needs to be recognized that the output waveform is only one
circuit converts the sinusoidal output of the transformer to a half cycle of the sine wave input. This is because the negative
unidirectional pulsating dc signal. The filter circuit ‘‘fills in’’ half of the input waveform is not admitted to pass through

Cathode end

Metal

Cathode end Cathode end Cathode end

Barrier layer
Copper Bismuth-cadmium alloy Magnesium

Barrier layer Barrier layer Barrier layer p–n junction

Cuprous oxide Selenium Cupric sulfide

Metal
Lead Aluminum Copper

Anode end Anode end Anode end Anode end

(a) (b)
Figure 1. Salient features of (a) metallic rectifiers and (b) a semiconductor diode (both not to
scale).
304 RECTIFYING CIRCUITS

Ac input Dc output
supply Transformer Rectifier Filter Regulator to load
Figure 2. Block diagram showing compo-
nents of power supply.

the diode. When not conducting, the diode has to withstand Similarly the dc voltage across the diode can be calculated
this peak inverse voltage (PIV) offered by the negative half mathematically. However, a simpler way is to apply Kirch-
cycle. In this case, the magnitude of PIV [also called peak hoffs voltage law. Since the sum of dc voltages should total
reverse voltage (PRV)] equals Vm. The output waveform ex- zero, it is easily observed that the dc voltage across the diode
tends to 2앟 radians; however, only one half of the sine wave Vdiode ⫽ ⫺ImR/앟 and the rms value of the current Irms ⫽ Im /2.
from 0 to 앟 is available across the load resistor. Expressed
mathematically, this means
FULL-WAVE RECTIFIER CIRCUIT

π
Idc = (1/2π ) Im sin ωt dt = Im /π The full-wave rectifier circuit can be visualized as comprising
0
two half-wave rectifier circuits, strategically connected to the
center top of a transformer secondary coil. Such a circuit is
The integration is carried out from 0 to 앟 because the current
shown in Fig. 4(a). Two semiconductor diodes are connected
between 앟 and 2앟 is zero. Across the output load resistance
to the two ends of the transformer secondary coil. The load
the dc voltage Vdc ⫽ IdcR ⫽ ImR/앟.
resistor is connected between the center tap of the trans-
former secondary coil and the junction of the negative elec-
trodes of the two diodes. The primary coil of the transformer
Rectifier receives the ac input supply. The output voltage of the trans-
diode former secondary coil is again represented as vi ⫽ Vm sin 웆t.
Here Vm represents the peak transformer secondary coil volt-
+ –
age from one end to the center tap. Furthermore, let us again
assume that the forward voltage drop of the diode is very
Ac Load small (this is normally represented as V웂) compared to the
supply resistor
input signal from the center-tapped transformer secondary
coil. We have the relations i1 ⫽ id1 and i2 ⫽ id2, where i1 is the
current in one half of the transformer secondary coil circuit,
Transformer i2 is and the current in the other half of the transformer sec-
ondary coil circuit, and id1 and id2 are diode currents. Also,
(a)
iR ⫽ i1 ⫹ i2, where iR is the current in the resistance. The dc
current can be calculated as in the previous case:

Idc = 2Im /π
Vdc = 2ImR /π
Vm

ωt where Im ⫽ Vm /Rf ⫹ R).

0 π 2π 3π 4π 5π 6π It must, however, be remembered that in this case, Vm rep-
resents the peak transformer secondary coil voltage from the
center tap to one end of the transformer. (The half-wave recti-
fier did not utilize a center-tapped secondary coil.) Figure 4(b)
(b) represents the input waveform. Figure 4(c) through 4(h) rep-
resent the output waveforms. It is observed that the load re-
sistance procures both halves of the sine wave. The output
Average value of waveforms are always positive, regardless of the fact that the
output voltage input waveform alternates between positive and negative
states every half-cycle. This is because when the top end of
–Vm
the transformer secondary coil is positive with respect to the
ωt center tap, diode D1 conducts and permits the flow of current
0 π 2π 3π 4π 5π from right to left in the load resistor R. Diode D2 is ‘‘open’’ or
‘‘off ’’ because the bottom end of the transformer secondary coil
must be negative with respect to the center tap. When the
bottom end of the transformer secondary coil is driven posi-
(c) tive with respect to the center tap, diode D2 conducts and
Figure 3. (a) Half-wave rectifier circuit; (b) input waveform shows again permits the flow of current from right to left in the load
both halves of sine wave; (c) output waveform across the load resistor resistor R. Diode D1 is open or off because the top-end of the
shows only positive half cycle and negative half cycle appears across transformer secondary coil must be negative with respect to
diode. the center tap. It can be seen that in this full-wave rectifier
 RECTIFYING CIRCUITS 305

D1 i1 circuit, the PIV across each diode is twice the maximum

transformer voltage measured from the center tap to either
+ – the top or bottom end. Voltages experienced by diodes D1 and
Vm D2 are shown in Figs. 4(g) and 4(h). In each case the voltages
R + iR
Ac
B – equal 2Vm, where Vm is the peak voltage corresponding to one
A half of the secondary coil.
supply
vo
Vm i2
D2
FULL-WAVE BRIDGE RECTIFIER CIRCUIT
+ –
Center-tapped transformer When a center-tapped transformer is not available, a bridge
rectifier circuit provides full-wave rectification. The bridge
(a)
consists of four diodes connected in a systematic loop as
shown in Fig. 5(a). This creates four junction points, a, b, c,
and d, as shown in the diagram. The transformer secondary
coil is connected between b and c, whereas the load resistor
Vm 4π is connected between a and d, as shown. Figure 5(b) repre-
(b) 0 ωt sents the top end of the transformer secondary coil being posi-
π 2π 3π
tive with respect to the bottom end. Only diodes D1 and D4
are capable of conducting. Diodes D2 and D3 are off. The
transformer secondary coil, diode D1, the load resistor R, and
the diode D4 all form a series circuit, permitting the current
(c) Vdc to flow in the load resistor from left to right. During the next
0 ωt half cycle, the top end of the transformer secondary coil is
π 2π 3π 4π
negative with respect to the bottom end. Therefore, only di-
odes D2 and D3 are capable of conducting. Diodes D1 and D4
are off. The transformer secondary coil, diode D2, the load
resistor R, and the diode D3 form a series circuit, permitting
(d) Idc
Im the current to flow in the load resistor, again, from left to
0 ωt
π 2π 3π 4π right. This is shown in Fig. 5(c). It is important to observe
that the current in the load resistor is always from a to d
regardless of whether b is positive or negative. The bridge
rectifier circuit is the best choice; however, it suffers from a
(e) minor disadvantage. It needs four diodes instead of two. How-
Vm
ωt ever, the PIV of each diode is only Vm and not 2Vm, as in the
0
π 2π 3π 4π case of full-wave rectifier. Currently, ready-made bridges are
mass manufactured and are available in an ‘‘encapsulated’’
form. A schematic is shown Fig. 5(d).

(f) Vm VOLTAGE REGULATION

0 ωt
π 2π 3π 4π
Voltage regulation provides the engineer a measure to study
the behavior of the circuit under changing load-current condi-
π 2π 3π 4π tions. The percentage of voltage regulation is defined as
0 ωt

2Vm VR% = [100(Vno load − Vfull load )]/Vfull load

(g)

Ideally, the voltage regulation of a well-designed power sup-

ply should be zero. In other words, the voltage delivered by
the power supply should be totally independent of the current
π 2π 3π
0 ωt drawn by the load. Suppose the supply is rated 12 V dc. The
instrument should deliver 12 V, whether it is delivering zero
2Vm
(h) load current (no load) or 600 A load current. Such stringent
specification require highly sophisticated electronic circuits.
It is possible to achieve VR% of less than 1%. An example of
a regulation curve is shown in Fig. 6. This graph indicates
Figure 4. (a) Full-wave rectifier circuit (ideal diodes); (b) input that the power-supply voltage drops from 12 V at zero current
waveform; (c) load voltage waveform; (d) load current waveform; (e)
to 8 V at full load of 5 A. The percentage of voltage regulation
current in diode D1; (f ) current in diode D2; (g) voltage across diode
D1; (h) voltage across diode D2.
can be calculated as follows:

VR% = [(12 − 8)/8](100) = 50%

306 RECTIFYING CIRCUITS

D1 D2

output voltage
Secondary
RLOAD
Ac input a d
supply + –

D3 D4

Transformer c

(a)

D1
Ac input
supply + RLOAD
(positive a d
+ –
half –
cycle) iR
D4

c
(b)

b
~ ~ + –
D2
Ac input iR
supply – + –
(negative a d
half + RLOAD
cycle)
D3
Ac input Dc output
Figure 5. (a) Bridge rectifier circuit; (b) current path, top supply
end positive; (c) current path, top end negative (observe that c delivery
leads leads
the current iR in the load resistance is always from a to d,
left to right); (d) encapsulated bridge rectifier. (c) (d)

The minimum load resistance that can be connected to the

power supply is calculated as

Rload (minimum) = Vfull load /Ifull load = 8/5 = 1.6 

14
RIPPLE
12
The output signal of a full-wave rectifier has a frequency
10 equal to twice the value of the input signal frequency. With a
60 Hz input, a 120 Hz unwanted signal appears at the output,
8
Vdc (V)

in addition to the dc output. This undesired ac component of

output is called ripple. In other words, ripple is small
6 amounts of alternating current waveforms superimposed on
the dc waveform. The ratio of the amount of ripple to the dc
4 value is called the ripple factor. It can also be expressed in
percent values and identified as percent ripple. The ripple fac-
2 tor provides the engineer with a measure to examine the ef-
fectiveness of the rectifier circuit. A ripple factor greater than
0 1 2 3 4 5
1 means that the amount of alternating current in the output
is greater than the amount of direct current in the output. It
Idc (A)
is imperative that rectifier circuits need to be appropriately
Figure 6. Regulation graph of a 12-V supply. designed to achieve ripple factors less than 1. The engineer
 RECTIFYING CIRCUITS 307

Vout all electronic circuitry demands a smooth dc voltage that is

constant in value and closely resembles the output voltage of
a good battery source. This conversion of half-wave and full-
120 Hz Ripple Vc wave signals to constant dc voltage values is accomplished
using a filter. Several types of filters are available, the sim-
Vdc
plest being a single capacitor. Other types include a choke
filter, 앟 filter, and double 앟 filter. The capacitor charges when
the diode is conducting and discharges via the load resistor
when the diode is off. The action of the capacitor can be exam-
ined by referring to Figs. 8(a) to 8(e). Let us choose a large
0 Time capacitor so that the capacitance sustains a voltage as defined
(a) by the point a or c as shown in Fig. 8(b). During the positive

A B B
+ –
Vc
Vdc +
Ac RLoad
supply C
–

0 0
0 0
(b)
(a)

VB
b d
Vm aa c

0 2π
0 ωt
π 3π 4π 5π 6π

(c)
(b)
Figure 7. (a) Output waveform of a power supply unit contains a
120 Hz ripple; (b) dc component of the output waveform; (c) ac compo-
nent of the output waveform.
b d

a c
can thus ensure that the amount of alternating current in the Dc voltage
output is less than the amount of direct current in the output. 0 ωt
Ripple is directly proportional to the load current Idc and in- (c)
versely proportional to the capacitance. However, capacitive
filters help provide ‘‘smooth’’ dc output waveforms. Let Fig.
7(a) represent the output waveform of a power-supply unit.
This waveform is made up of two components, a dc component b d
shown in Fig. 7(b), and an ac component, shown in Fig. 7(c).
A perfectly designed rectifier circuit should deliver a smooth a Dc current c
0 ωt
dc output. (d)
Mathematically, we can write this statement as

Va2 + Vb2 = Vc2

Ripple has been defined as the ratio of Vb to Va, Vb /Va. If the

rms value of the ripple voltage is given as Vr, then the ripple
factor is Vr /Vdc. a b c d ωt
0
(e)
FILTERS Figure 8. (a) Half-wave rectifier with a capacitor filter across the
load resistor; (b) capacitor must be large enough to ‘‘fill’’ in the ‘‘val-
The pulsating dc output signals from the half-wave, full-wave, leys’’ (shaded); (c) voltage across load resistor; (d) current through
and bridge rectifiers have very limited applications. Almost load resistor; (e) diode current.
308 RECTIFYING CIRCUITS

Iron core
inductance

Ac Ac L Dc
input input Full-wave output
C C
supply rectifier to
C RLoad RLOAD

Transformer Figure 11. Full-wave rectifier with 앟 filter (L–C combination) and
Bridge
rectifier load resistor R.

(a)

where f is the power line frequency and C represents the

Rsurge
Ac
input
C RLoad
Transformer Bridge
rectifier
(b)
Figure 9. (a) Bridge rectifier with load resistor RLOAD and filter capac-
itor C; (b) the addition of a surge resistance limits the sudden gush
of current that takes place during the instant the circuit is energized.
half of the supply cycle, when the diode is conducting, the
capacitor gets charged. This charging operation takes place
during the time interval between a and b. At point b the
charging current ceases because the diode is reverse biased
and has stopped conducting. But the load continues to receive
current from the discharging capacitor during the time inter-
val from b to c. Again, at point c the capacitor begins its
charging operation and the cycle repeats. The load resistor
voltage and current waveforms are shown in Figs. 8(c) and
8(d), respectively. A full-wave rectifier with a single capaci-
tance across the load is shown in Fig. 8(e). The corresponding
output waveform, with the action of its filter capacitor, is
shown in Fig. 8(f). An approximate analysis yields
Vdc = Vm − Idc /4 fC
D1
R R
Ac input supply
value of filter capacitor used.
Instead of using only a capacitance, sometimes a resis-
tance called the surge resistance is often used in addition to
the load resistance, as shown in Fig. 9(b). The filter capacitor
is initially uncharged and acts as a ‘‘short circuit’’ when the
circuit shown in Fig. 9(a) is energized. Therefore there is sud-
den inrush of current, and this is called the surge current. In
some cases this current surge may be large enough to destroy
the diodes. Therefore a current-limiting resistor is added in
series as shown in Fig. 9(b). Other combinations of resis-
tances and capacitances are also used. A two-section R–C fil-
ter used in conjunction with a full-wave rectifier is shown in
Fig. 10.
When the load current is heavy, an L–C filter, which is
also called a choke filter, is preferred to an R–C filter. The
ripple can be reduced by choosing the inductive reactance to
be much higher than the capacitive reactance. For example,
if XL is ten times as large as XC, then the ripple is attenuated
by a factor of 10. An example wherein a full-wave rectifier
employs one section in which L–C filters are used is shown in
Fig. 11. This is also called a 앟 filter. Using two sections re-
sults in an improvement in the value of ripple. Still further
reduction in ripple can be accomplished by using a double 앟
filter as shown in Fig. 12. However, the voltage regulation
may be poorer because of voltage drop in the choke filters.
Rectifier circuits combined with appropriate filter circuits pro-
vide a convenient method of converting ac to dc. However, the
proper choice depends upon the application desired. Some of
the factors that need to be considered are the permissible rip-
ple, the regulation required, the nature of load current de-
sired, the size and weight of the complete network, and the
cost of components. A choke filter should consist of pure in-
ductance; however, it possesses a small amount of resistance.
A 앟 filter that includes the choke resistance of the coil as well

C C C RLoad
Iron core
inductances

D1,D2 Rectifier diodes

D2
Ac L L Dc
input Full-wave C output
C
Center-tapped supply rectifier to
transformer RLOAD
Figure 10. Two-section R–C filter can reduce the ripple by a factor
of 움2 where 움 is the ripple factor for one R–C section. Figure 12. Full-wave rectifier with double 앟 filter.
 RECTIFYING CIRCUITS 309

L R
3 Vm

Input Output
Vm 2Vm
from C1 C2 to
rectifier load – + – +
C1 C3
Vm D1 D2 D3
C2
Figure 13. Capacitance input 앟 filter.
– +

is shown in Fig. 13. This is also called a capacitance input
filter. Another version, called a ‘‘Tee’’ filter or a choke input
filter is shown in Fig. 14. Under light load conditions, capaci-
tor input filters help rectifiers generate fairly smooth dc sig-
nals with small ripple. However, the regulation is relatively
poor. In addition, as the load currents increase ripple also in-
creases.
RATIO OF RECTIFICATION
The ratio of rectification is defined as the ratio of dc output
power delivered by the rectifier circuit to the ac input power
delivered to the rectifier circuit. It needs to be recognized that
the transformer is an ac apparatus and therefore it is possible
to calculate the rms value of the load voltage and the rms
value of the load current. The product of these two values
yields the total power delivered by the transformer. However,
the objective of the rectifier circuit is to provide direct current
to the load. Therefore one can calculate the dc voltage and
the dc current at the load resistor. The product of these two
quantities results in the dc load power. The ratio of rectifica-
tion can thus be determined. However, this ratio should not
be confused as an efficiency measure because efficiency calcu-
lations include the losses in the transformer as well as the
diodes.
Voltage Doublers
By suitably modifying the full-wave and the bridge rectifier
circuits, it is possible to create circuits that can provide twice
the peak supply voltage, or 2Vm. By cascading several voltage
doubler circuits suitably, it is possible to generate very high
dc voltages. The full-wave voltage doubler circuit is shown in
Fig. 13(a). Another interpretation of the circuit is shown in
Fig. 13(b) wherein the load resistor is omitted for sake of clar-
ity. Diode D1 charges the capacitor C1 when the top end of
2Vm
Figure 15. Voltage tripler.
the supply source is positive with respect to the bottom end.
Similarly, diode D2 charges the capacitor C2 when the bottom
end is positive with respect to the top end of the input source.
In this circuit, each capacitor is charged once per cycle, but at
different times. The capacitors therefore receive two charging
pulses per cycle. Furthermore it is observed that capacitances
C1 and C2 are in series. This results in a doubling effect.
Figure 13(c) shows the waveform across the two capacitors
and indicates how they add up. The load resistor may be con-
nected between the two extreme ends of the two capacitors
as shown in the diagram. The ripple frequency is twice the
frequency of the supply and the ripple is greater and the regu-
lation poorer compared with an equivalent full wave rectifier.
Figure 14(a) shows the half-wave voltage doubler circuit.
It is also called the cascade voltage doubler circuit. Diode D1
operates when the bottom end of the supply is positive and
charges the capacitor C1 to the maximum value of the supply
voltage Vm as shown. During the next half cycle, when the top
end of the supply is positive, the supply voltage is actually
‘‘aiding’’ the capacitor C1 because of the series connection of
the supply and capacitor C1. The maximum possible value is
2Vm, and therefore the capacitor C2 charges to the same value
of 2Vm via diode D2. The load need only be connected across
capacitor C2, unlike the previous case wherein the load was
connected across a series combination of capacitors C1 and
C2. Therefore the load receives only one charging pulse per
cycle. The ripple is very high, but its frequency in this case is
the same as the supply line frequency. The voltage regulation
of this circuit is also very poor.
Voltage tripler and voltage quadrupler circuits are shown
in Figs. 15 and 16. It is possible to design circuits that provide
more than 4Vm. However, the such circuits result in extremely
poor voltage regulation.

L1 R1 L2 R2 Vm 2 Vm

– + – +
C1 C3
Input Output D1 D2 D3 D4
from C to
rectifier load C2 C4
– + – +

2 Vm 2 Vm
4 Vm
Figure 14. Choke input tee filter.

Figure 16. Voltage quadrupler.

310 RECTIFYING CIRCUITS

Output
Input

RL 0
V Rs

Output
Input
V V

V
Output
Input

RL
Rs
V
V

Output
Input
0
V

V
Output
Input

RL 0 Rs V
V

Output
Input

V
Output
Input

RL
Rs
Output

V
Input

0 V
V

(a) (b)
Figure 17. Clipper circuits modify the sine wave input. (Input voltage waveform remains the
same for all circuits.) (a) Left: Rectifier diodes used as ‘‘clippers’’; Right: Waveform across output
load resistor RL. (b) Left: Rectifier diodes used as ‘‘clippers’’; Right: Waveform across, output,
diode–battery series combination where RS ⫽ series resistor.

Clippers ples of clamper circuits are shown in Fig. 18. The clamper is
also called a dc restorer, particularly when associated with
Many electronic circuits demand the removal of unwanted
television circuitry. All these circuits assume a sinusoidal in-
signals below or above a predetermined or specified voltage
put voltage of 50 V peak-to-peak magnitude (Vm ⫽ 25 V).
level. By suitably rearranging a diode rectifier circuit and a
dc battery power supply, it is possible to obtain a variety of
clipper circuits. A sample of selected clipper circuits along
with their output waveforms is shown in Fig. 17. All these APPENDIX 1. HALF-WAVE RECTIFIER CALCULATIONS
circuits assume a sinusoidal input voltage of 50 V peak-to-
peak magnitude (Vm ⫽ 25 V). The rms value of a complete sine wave is Vm / 兹2. The output
of the half-wave rectifier is only one half of a sine wave.
Clampers
Therefore, the rms value of the load voltage is equal to
A clamper adds a dc component to the signal. The principle is (1/ 兹2)(Vm / 兹2) ⫽ Vm /2. The average or dc value Vdc of this
to utilize the charging nature of a capacitor. Selected exam- rectified sine wave is Vdc ⫽ Vm /앟 ⫽ 0.318Vm. The rms value of
 RECTIFYING CIRCUITS 311

+2Vmax
C

Output
Input
R
0
C Output
0
Input

+2Vmax

C
VB

Output
Input
R +2Vmax
C 0
VB
Output
Input

R +2Vmax
0
VB VB

0
VB
C

Output
Input

C
+2Vmax R +2Vmax
Output
Input

R
VB 0
VB
VB

(a) (b)
Figure 18. (a) Clamper circuits retain shape of the input sine waveform, but add a dc ‘‘bias’’ to
the waveform. (b) Left: While designing clamping circuits, it is essential that 5 RC Ⰷ T/2, where
T ⫽ period of sine wave; Right: Output waveforms of clamping circuits obtained across resis-
tance, R (Input voltage waveform for all six clamping circuits).

the ripple voltage is Vr. Therefore (Vm /2)2 ⫽ (Vm /앟)2 ⫹ (Vr)2 ac power rating of the trans- (Vm / 兹2)[(Vm /2)/R] ⫽
Solving, Vr ⫽ 0.386Vm. former Vm2 /2兹2R W
The ripple factor is Vr /Vdc ⫽ 0.386Vm /0.318Vm ⫽ 1.21. Transformer utilization (dc load power)/(ac power
factor rating)
ac load voltage Vm /2 Transformer utilization (Vm2 /앟2R)/(Vm2 /2兹2R) ⫽
ac load current (Vm /2)/R factor 2兹2/앟2 ⫽ 0.287
ac load power (Vm /2)[(Vm /2)/R] ⫽ Vm2 /4R
dc load voltage Vm /앟
dc load current Vm /앟R APPENDIX 2: FULL-WAVE RECTIFIER CALCULATIONS
dc load power (Vm /앟)(Vm /앟R) ⫽ Vm2 /앟2R
In this case both halves of the ac input sine wave are rectified
The ratio of rectification is the dc load power divided by the and utilized. Therefore the magnitude of several of the values
ac load power, or (Vm2 /앟2R)/(Vm2 /4R). The ratio of rectification that were calculated for the half-wave rectifier gets multiplied
is 4/앟2 ⫽ 0.406. This is no indication of the efficiency; however, by a factor of 2. The rms value of a complete sine wave is
it can be stated that the overall operating efficiency of a half- Vm / 兹2. The average of dc value of the rectified sine wave
wave rectifier with a resistive load cannot be greater than Vdc ⫽ 2Vm /앟 ⫽ 0.636Vm. The rms value of the ripple voltage
40.6%. An ideal rectifier has no losses and has therefore a is Vr. Therefore (Vm / 兹2)2 ⫽ (2Vm /앟)2 ⫹ (Vr)2. Solving, Vr ⫽
100% ‘‘power’’ efficiency. 0.307Vm.
The rating of the secondary winding of the transformer is The ripple factor is Vr /Vdc ⫽ 0.307Vm /0.636Vm ⫽ 0.482.
Vm / 兹2 V.
ac load voltage Vm / 兹2
ac current in the secondary (Vm /2)/R A ac load current (Vm / 兹2)/R
winding the ac load ac load power (Vm / 兹2)[(Vm / 兹2)/R] ⫽ Vm2 /2R
current dc load voltage 2Vm /앟
312 RECTIFYING CIRCUITS

Table 2. Rectifier Circuit Terminology

Term Input (ac) Output (dc)
Half-wave rectifier a
VRMS ⫽ (Vm / 兹2) ⫽ 0.707Vm Vdc ⫽ VAVG ⫽ (Vm /앟) ⫽ 0.318Vm
IRMS ⫽ (Im /2) ⫽ 0.5Im Idc ⫽ IAVG ⫽ (Im /앟) ⫽ 0.318Im
Efficiency of HWR (purely
[(IDC)2RLOAD]/[(IAC)2RLOAD] ⫽ (0.318Im)2 /(0.5Im)2 ⫽ 0.406
resistive load)
VRMS ⫽ (Vm / 兹2) ⫽ 0.707Vm Vdc ⫽ VAVG ⫽ 2(Vm /앟) ⫽ 0.636Vm
IRMS ⫽ (Im / 兹2) ⫽ 0.707Im Idc ⫽ IAVG ⫽ 2(Im /앟) ⫽ 0.636Im
Efficiency of FWR (purely [(Idc)2RLOAD]/[(IAC)2RLOAD] ⫽ (0.636Im)2 /(0.707Im)2 ⫽ 0.812
resistive load)
a
It is important to observe that in a half-wave rectifier (HWR), the voltage is present during both half cycles.
Therefore, VRMS ⫽ 0.707 Vm; however, the current flows for only one half cycle. Therefore IRMS ⫽ 0.5 Im. For the
above calculations, an ideal rectifier has been assumed and therefore the internal resistance of the rectifier r웂
has been ignored.

dc load current 2Vm /앟R lations that were carried out for the full-wave rectifier are
dc load power (2Vm /앟)(2Vm /앟R) ⫽ 4Vm2 /앟2R still valid in this case. The rms value of a complete sine wave
is Vm / 兹2. The average or dc value of the rectified sine wave
The ratio of rectification is the dc load power divided by the Vdc ⫽ 2Vm /앟 ⫽ 0.636Vm. The rms value of the ripple voltage
ac load power, or (4Vm2 /앟2R)/(Vm2 /2R). The ratio of rectification is Vr. Therefore (Vm / 兹2)2 ⫽ (2Vm /앟)2 ⫹ (Vr)2. Solving, Vr ⫽
is 8/앟2 ⫽ 0.812. The overall operating efficiency is therefore
twice that of a half-wave rectifier, that is, 81.2%.
The full-wave rectifier utilizes the center-tapped secondary Vmax
winding of a transformer. But the primary coil has a single
winding. Therefore the calculations for the primary and sec-
ondary circuits must be done separately. The secondary coil
of the transformer actually contains two circuits. Each circuit
performs the function of a half-wave rectifier. Therefore the
transformer utilization factor for the secondary coil is twice
that of the half-wave rectifier. 0 π 2π
The transformer utilization factor for secondary winding is
2(0.287) ⫽ 0.574. Disregarding the center tap, we can calcu-
late the transformer utilization factor for the primary
winding.

dc load voltage Vdc ⫽ 2Vm /앟 (a)

dc load current Idc ⫽ 2Vm /앟R ⫽ 2Im /앟, Im ⫽ Vm /R.
Vmax
The rating of the transformer winding can be calculated using
the rms values of voltage and current:
√ √ VRMS VRMS =
Vmax
= 0.707 Vmax
Vrms = Vm / 2 V, Irms = Im / 2 A 2
VDC Vdc = 0.318 Vmax
Substituting and rearranging, we obtain
√ 0 π 2π
Vdc = (2 2/π )Vrms
√ (b)
Idc = (2 2/π )Irms

The dc power can now be determined in terms of the ac power: Vmax

Vdc Idc = (8/π 2 )Vrms Irms

The transformer utilization factor is the dc power divided by

the ac power or VdcIdc /VrmsIrms ⫽ 8/앟2 ⫽ 0.812. The average VDC = VAVG
transformer utilization factor is (0.574 ⫹ 0.812)/2 ⫽ 0.693.
0 π 2π
APPENDIX 3. BRIDGE RECTIFIER RIPPLE CALCULATIONS (c)
Figure 19. Half-wave rectification waveforms: (a) One full cycle of
Both halves of the ac input sine wave are rectified and uti- input sine wave; (b) Output waveform: half-wave rectifier; (c) Averag-
lized in a bridge rectifier as well. Therefore many of the calcu- ing over one full cycle.
 RECTIFYING CIRCUITS 313

Vmax siderable variation, or ripple in the rectified output. A ripple

factor is therefore defined, that helps in evaluating and com-
paring different rectifier circuits.

Effective value of alternating current

portion of rectified output wave
Ripple factor =
Average value of rectified output wave
0 π 2π
A filter is a circuit that is used to eliminate undesired ripple
from the output voltage of the rectifier. Normally, a well-
designed capacitor is used to obtain a smooth dc output from
a rectifier. The necessary capacitance can be calculated using
the following formula:
(a)
C = [(load current)(one full cycle of waveform)]/
[twice ripple voltage]
V
VRMS = max = 0.707 V
2 max
For example, using the frequency in the U.S., i.e., 60 Hz, pe-
Vmax
Vdc = 0.636 Vmax riod ⫽ 1/60 s. If the load current is 10 amperes and only 3
volts peak-to-peak ripple voltage is permitted, then capaci-
VRMS tance required will be [10(1/60)]/[(2)(3)] ⫽27,777.77 micro-
Vdc farads.
Table 2 and Figs. 19 and 20 help clarify the terminology
associated with rectifier circuits.

0 π 2π
(b)
Vmax
Vdc Vdc = VAVG
0 π 2π
(c)
Figure 20. Full-wave rectification waveforms: (a) One full cycle of
input sine wave; (b) Output waveform: full-wave rectifier; (c) Averag-
ing over one full cycle.
0.307Vm. The ripple factor is Vr /Vdc ⫽ 0.307Vm /0.636Vm ⫽
0.482. The ratio of rectification will not change and remains
0.812, as it was for the full-wave rectifier. There is no second-
ary center tap; therefore the transformer utilization factor is
0.812, as it was for the full-wave rectifier when we disre-
garded the center tap.
EPILOGUE
The main objective of a rectifier circuit is to convert alternat-
ing current/voltage into pure direct current/voltage. A recti-
fier diode accomplishes this. As an example, 1N4004 diode
has a rating of 1 ampere and 400 volts PIV. However, instead
of providing a steady output current/voltage, the rectifier cir-
cuit might be delivering a current/voltage that may have con-
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314 RECURSION

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Ohio: Merrill Publishing Co., 1990.

MYSORE NARAYANAN
Miami University
RELAXATION OSCILLATORS AND NETWORKS
Relaxation oscillations comprise a large class of nonlinear
dynamical systems, and arise naturally from many physi-
cal systems such as mechanics, geology, biology, chemistry,
and engineering. Such periodic phenomena are character-
ized by intervals of time during which little happens, in-
terleaved with intervals of time during which considerable
changes take place. In other words, relaxation oscillations
exhibit two time scales. The dynamics of a relaxation oscil-
lator is illustrated by the mechanical system of a seesaw
in Figure 1. At one side of the seesaw is there a water con-
tainer which is empty at the beginning; in this situation the
other side of the seesaw touches the ground. As the weight
of water running from a tap into the container exceeds that
of the other side, the seesaw flips and the container side
touches the ground. At this moment, the container emp-
ties itself, and the seesaw returns quickly to its original
position and the process repeats.
Relaxation oscillations were first observed by van der
Pol [1] in 1926 when studying properties of a triode circuit.
Such a circuit exhibits self-sustained oscillations. van der
Pol discovered that for a certain range of system parame-
ters the oscillation is almost sinusoidal, but for a different
range the oscillation exhibits abrupt changes. In the lat-
ter case, the period of the oscillation is proportional to the
relaxation time (time constant) of the system, hence the
term relaxation oscillation. van der Pol [2] later gave the
following defining properties of relaxation oscillations:
1. The period of oscillations is determined by some form
of relaxation time.
2. They represent a periodic autonomous repetition of
a typical aperiodic phenomenon.
3. Drastically different from sinusoidal or harmonic os-
cillations, relaxation oscillators exhibit discontinu-
ous jumps.
4. A nonlinear system with implicit threshold values,
characteristic of the all-or-none law.
A variety of biological phenomena can be characterized
as relaxation oscillations, ranging from heartbeat, neu-
ronal activity, to population cycles; the English physiologist
Hill [3] even went as far as saying that relaxation oscilla-
tions are the type of oscillations that governs all periodic
phenomena in physiology.
Given that relaxation oscillations have been studied in
a wide range of domains, it would be unrealistic to provide
an up-to-date review of all aspects in this article. Thus, I
choose to orient my description towards neurobiology and
Figure 1. An example of a relaxation oscillator: a seesaw with a
water container at one end (adapted from [4]).
J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright © 2007 John Wiley & Sons, Inc.
emphasize networks of relaxation oscillators based on the
following two considerations (the reader is referred to [4]
for an extensive coverage of relaxation oscillations). First,
as described in the next section, neurobiology has moti-
vated a great deal of study on relaxation oscillations. Sec-
ond, substantial progress has been made in understanding
networks of relaxation oscillators. In the next section, I de-
scribe a number of relaxation oscillators, including the van
der Pol oscillator. The following section is devoted to net-
works of relaxation oscillators, where the emergent phe-
nomena of synchrony and desynchrony are the major top-
ics. Then, I describe applications of relaxation oscillator
networks to visual and auditory scene analysis, which are
followed by some concluding remarks.
RELAXATION OSCILLATORS
In this section I introduce four relaxation oscillators. The
van der Pol oscillator exemplifies relaxation oscillations,
and has played an important role in the development of dy-
namical systems, in particular nonlinear oscillations. The
Fitzhugh-Nagumo oscillator and the Morris-Lecar oscilla-
tor are well-known models for the conductance-based mem-
brane potential of a nerve cell. The Terman-Wang oscillator
has underlain a number of studies on oscillator networks
and their applications to scene analysis. As demonstrated
by Nagumo et al. [5] and Keener [6], these oscillator models
can be readily implemented with electrical circuits.
Van der Pol Oscillator
The van der Pol oscillator can be written in the form
« ·
x + x = c(1 − x2 )x (1)
where c > 0 is a parameter. This second-order differential
equation can be converted to a two variable first-order dif-
ferential equation,
²
x = c[y − f (x)] (2)
²
y = −x/c (2)
²
Here f (x) = −x + x3 /3. The x nullcline, i.e. x = 0, is a cubic
²
curve, while the y nullcline, y = 0, is the y axis. As shown
in Fig. 2(a), the two nullclines intersect along the middle
branch of the cubic, and the resulting fixed point is unstable
as indicated by the flow field in the phase plane of Fig. 2(a).
This equation yields a periodic solution.
As c > 1, Eq. (2) yields two time scales: a slow time scale
for they variable and a fast time scale for the x variable.
As a result, Eq. (2) becomes the van der Pol oscillator that
produces a relaxation oscillation. The limit cycle for the van
der Pol oscillator is given in Fig. 2(b), and it is composed of
four pieces, two slow ones indicated by pq and rs, and two
fast ones indicated by qr and sp. In other words, motion
along the two branches of the cubic is slow compared to
fast alternations, or jumps, between the two branches. Fig.
2(c) shows x activity of the oscillator with respect to time,
where two time scales are clearly indicated by relatively
slow changes in x activity interleaving with fast changes.
2 Relaxation Oscillators and Networks
Figure 2. Phase portrait and trajectory of a van der Pol oscilla-
tor. (a) Phase portrait. The x nullcline is the cubic curve, and the y
nullcline is the y axis. Arrows indicate phase flows. (b) limit cycle
orbit. The limit cycle is labeled as pqrs, and the arrowheads indi-
cate the direction of motion. Within the limit cycle, qr and sp are
two fast pieces (indicated by double arrowheads), and pq and rs
are slow pieces. (c) Temporal activity of the oscillator. Here the x
activity is shown with respect to time.
FitzHugh-Nagumo Oscillator
By simplifying the classical Hodgkin-Huxley equations [5]
for modeling nerve membranes and action potential gener-
ation, FitzHugh [7] and Nagumo et al. [8] gave the follow-
ing two-variable equation, widely known as the FitzHugh-
Nagumo model,
² represents external stimulation to the oscillator. Thus x
x = c[y − f (x) + I] (3)
²
y = −(x + by − a)/c (3)
where f(x) is as defined in Eq. (2), I is the injected current,
and a, b, and c are system parameters satisfying the condi-
tions: 1 > b > 0, c2 > b, and 1 > a > 1 − 2b/3. In neurophys-
iological terms, x corresponds to the neuronal membrane
potential, and y plays the aggregate role of three variables
in the Hodgkin-Huxley equations. Given that the x null-
cline is a cubic and the y nullcline is linear, the FitzHugh-
Nagumo equation is mathematically similar to the van der
Pol equation. Typical relaxation oscillation with two time
scales occurs when c > 1. Because of the three parameters
and the external input I, the FitzHugh-Nagumo oscillator
has additional flexibility. Depending on parameter values,
the oscillator can exhibit a stable steady state or a stable
periodic orbit. With a perturbation by external stimulation,
the steady state can become unstable and be replaced by
an oscillation; the steady state is thus referred to as the
excitable state.
Morris-Lecar Oscillator
In modeling voltage oscillations in barnacle muscle fibers,
Morris and Lecar [9] proposed the following equation,
²
x = −gCa m∞ (x)(x − 1) − gK y(x − xK ) − gL (x − xL ) + I (4)
²
y = −ε[y∞ (x) − y]/τy (x) (4)
where
m∞ (x) = {1 + tanh[(x − x1 )/x2 ]}/2
y∞ (x) = {1 + tanh[(x − x3 )/x4 ]}/2
τy (x) = 1/cosh[(x − x3 )/(2x4 )]
and x1 x2 , x3 , x4 , gCa , gK , gL , xK , and xL are parameters.
Ca stands for calcium, K for potassium, L for leak, and I is
the injected current. The parameter ε controls relative time
scales of x and y. Like Eq. (3), the Morris-Lecar oscillator is
closely related to the Hodgkin-Huxley equations, and it is
used as a two-variable description of neuronal membrane
properties or the envelope of an oscillating burst [10]. The
x variable corresponds to the membrane potential, and y
corresponds to the state of activation of ionic channels.
The x nullcline of Eq. (4) resembles a cubic and the y
nullcline is a sigmoid. When ε is chosen to be small, the
Morris-Lecar equation produces typical relaxation oscilla-
tions. From the mathematical point of view, the sigmoidal
y nullcline marks the major difference between the Morris-
Lecar oscillator and the FitzHugh-Nagumo oscillator.
Terman-Wang Oscillator
Motivated by mathematical and computational considera-
tions, Terman and Wang [11] proposed the following equa-
tion,
²
x = f (x) − y + I (5)
²
y = ε[g(x) − y] (5)
where f (x) = 3x − x3 + 2, g(x) = α[1 + tanh(x/β)], and I
nullcline is a cubic and the y nullcline is a sigmoid, where α
and β are parameters. When ε  1, Eq. (5) defines a typical
relaxation oscillator. When I > 0 and with a small β, the
two nullclines intersect only at a point along the middle
branch of the cubic and the oscillator produces a stable pe-
riodic orbit (see Fig. 3(a)). The periodic solution alternates
between silent (low x) and active (high x) phases of near
steady-state behavior. As shown in Fig. 3(a), the silent and
the active phases correspond to the left branch (LB) and
the right branch (RB) of the cubic, respectively. If I < 0, the
two nullclines of Eq. (5) intersect at a stable fixed point
along the left branch of the cubic (see Fig. 3(b)), and the
oscillator is in the excitable state. The parameter α deter-
mines relative times that the periodic solution spends in
these two phases. A larger α results in a relatively shorter
active phase.
The Terman-Wang oscillator is similar to the afore-
mentioned oscillator models. It is much simpler than the
Morris-Lecar oscillator, and provides a dimension of flex-
ibility absent in the van der Pol and FitzHugh-Nagumo
equations. In neuronal terms, the x variable in Eq. (5) cor-

Figure 3. Nullclines and trajectories of a Terman-Wang oscilla-
tor. (a) Behavior of a stimulated oscillator. The x nullcline is a cubic
and the y nullcline is a sigmoid. The limit cycle is shown with a
bold curve, and its direction of motion is indicated by arrowheads.
LB and RB denote the left branch and the right branch of the cubic,
respectively, (b) Behavior of an excitable (unstimulated) oscillator.
The oscillator approaches the stable fixed point PI .
responds to the membrane potential, and y the state for
channel activation or inactivation.
NETWORKS OF RELAXATION OSCILLATORS
In late eighties, neural oscillations in the gamma frequency
range (about 40 Hz) were discovered to in the visual cortex
[12] [13]. The experimental findings can be summarized as
the following: (1) neural oscillations are triggered by sen-
sory stimulation, and thus the oscillations are stimulus-
dependent; (2) long-range synchrony with zero phase-lag
occurs if the stimuli appear to form a coherent object; (3)
no synchronization occurs if the stimuli appear to be un-
related. These intriguing observations are consistent with
the temporal correlation theory [14], which states that in
perceiving a coherent object the brain links various feature
detecting neurons via temporal correlation among the fir-
ing activities of these neurons.
Since the discovery of coherent oscillations in the visual
cortex and other brain areas, neural oscillations and syn-
chronization of oscillator networks have been extensively
studied. Most of the early models are based on sinusoidal
or harmonic oscillators and rely on all-to-all connectivity to
reach synchronization across the network. In fact, accord-
ing to the Mermin and Wagner theorem [15] in statistical
physics, no synchrony exists in one- or two-dimensional
locally coupled isotropic Heisenberg oscillators, which are
similar to harmonic oscillators. However, all-to-all connec-
tivity leads to indiscriminate synchrony because the net-
work is dimensionless and loses critical information about
topology. Thus, such networks are very limited in address-
ing perceptual organization and scene analysis – the main
motivations behind computational studies of oscillatory
networks – that appear to require topological relations.
Somers and Kopell [16] and Wang [17] first realized
that there are qualitative differences between sinusoidal
and non-sinusoidal oscillators in achieving emergent syn-
Relaxation Oscillators and Networks 3
chrony in a locally coupled network. Specifically, Somers
and Kopell using relaxation oscillators and Wang using
Wilson-Cowan oscillators [18] each demonstrated that an
oscillator network can synchronize with just local coupling.
Note that Wilson-Cowan oscillators in their normal param-
eter regime are neither sinusoidal nor relaxation-type.
Two Oscillators: Fast Threshold Modulation
When analyzing synchronization properties of a pair of
relaxation oscillators, Somers and Kopell [16] introduced
the notion of fast threshold modulation. Their mechanism
works for general relaxation oscillators, including those de-
scribed in the previous section. Consider a pair of identical
relaxation oscillators excitatorily coupled in a way mim-
icking chemical synapses. The coupling is between the fast
variables of the two oscillators, and can be viewed as binary,
resulting in the so-called Heaviside coupling. The two os-
cillators are uncoupled unless one of them is in the active
phase, and in this case the effect of the excitatory coupling
is to raise the cubic of the other oscillator by a fixed amount.
Let us explain the mechanism of fast threshold modula-
tion using the Terman-Wang oscillator as an example. The
two oscillators are denoted by o1 = (x1 , y1 ) and o2 = (x2 , y2 ),
which are initially in the silent phase and close to each
other with o1 leading the way as illustrated in Fig. 4. Fig-
ure 4 shows the solution of the oscillator system in the
singular limit ε → 0. The singular solution consists of sev-
eral pieces. The first piece is when both oscillators move
along LB of the uncoupled cubic, denoted as C. This piece
lasts until o1 reaches the left knee of C, LK, at t = t1 . The
second piece begins when o1 jumps up to RB, and the exci-
tatory coupling from o1 to o2 raises the cubic for o2 from C
to CE as shown in the figure. Let LKE and RKE denote the
left and right knees of CE . If |y1 − y2 | is relatively small,
then o2 lies below LKE and jumps up. Since these interac-
tions take place in fast time, the oscillators are effectively
synchronized in jumping up. As a result the cubic for o1
is raised to CE as well. The third piece is when both os-
cillators lie on RB and evolve in slow time. Note that the
ordering in which the two oscillators track along RB is re-
versed and now o2 leads the way. The third piece lasts until
o2 reaches RKE at t = t2 . The fourth piece starts when o2
jumps down to LB. With o2 jumping down, the cubic for o1
is lowered to C. At this time, if o1 lies above RK, as shown
in Fig. 4, o1 jumps down as well and both oscillators are
now in the silent phase. Once both oscillators are on LB,
the above analysis repeats.
Based on the fast threshold modulation mechanism,
Somers and Kopell further proved a theorem that the syn-
chronous solution in the oscillator pair has a domain of at-
traction in which the approach to synchrony has a geomet-
ric (or exponential) rate [16]. The Somers-Kopell theorem
is based on comparing the evolution rates of the slow vari-
able right before and after a jump, which are determined
by the vertical distance of an oscillator to they nullcline
(see Fig. 4).
A Network of Locally Coupled Oscillators
In the same paper Somers and Kopell suspected that their
analysis extends to a network of relaxation oscillators, and
4 Relaxation Oscillators and Networks
Figure 4. Fast threshold modulation. C and CE indicate the un-
coupled and the excited cubic, respectively. The two oscillators o1
and o2 start at time 0. When o1 jumps up at t = t1 , the cubic cor-
responding to o2 is raised from C to CE . This allows o2 to jump up
as well. When o2 jumps down at t = t2 , the cubic corresponding to
o1 is lowered from CE to C. This allows o1 to jump down as well.
In the figure, LK and RK indicate the left knee and the right knee
of C, respectively. LKE and RKE indicate the left knee and right
knee of CE , respectively.
performed numerical simulations with one-dimensional
rings to support their suggestion. In a subsequent study, by
extending Somers and Kopell analysis, Terman and Wang
proved a theorem that for an arbitrary network of locally
coupled relaxation oscillators there is a domain of attrac-
tion in which the entire network synchronizes at an expo-
nential rate [11].
In their analysis, Terman and Wang employed the time
metric to describe the distance between oscillators. When
oscillators evolve either in the silent phase or the active
phase, their distances in y in the Euclidean metric change;
however, their distances in the time metric remain con-
stant. On the other hand, when oscillators jump at the
same time (in slow time), their y distances remain un-
changed while their time distances change. Terman and
Wang also introduced the condition that the sigmoid for
the y nullcline (again consider the Terman-Wang oscilla-
tor) is very close to a step function [11], which is the case
when β in Eq. (5) is chosen to be very small. This condition
implies that in the situation with multiple cubics the rate
of evolution of a slow variable does not depend on which
cubic it tracks along.
Recently, Campbell et al. [19] showed that the definition
of a canonical relaxation oscillator can lead to qualitatively
different kinds of oscillation through parameter choices.
In addition, their numerical investigation indicates that a
network of relaxation oscillators in the relaxation regime
(the normal case) approach synchrony with an average
time that is a power relation of the network size with a
small exponent. On the other hand, relaxation oscillators in
the spiking regime, where the active phase is much shorter
than the silent phase, approach synchrony with an average
time that is a logarithmic relation of the network size, al-
though for the same network synchrony in the relaxation
regime is typically faster than that in the spiking relation.
Figure 5. Architecture of a two dimensional LEGION network
with nearest neighbor coupling. The global inhibitor is indicated
by the black circle, and it receives excitation from every oscillator
of the 2-D grid and feeds back inhibition to every oscillator.
LEGION Networks: Selective Gating
A natural and special form of the temporal correlation the-
ory is oscillatory correlation [20], whereby each object is
represented by synchronization of the oscillator group cor-
responding to the object and different objects in a scene are
represented by different oscillator groups which are desyn-
chronized from each other. There are two fundamental as-
pects in the oscillatory correlation theory: synchronization
and desynchronization. Extending their results on syn-
chronizing locally coupled relaxation oscillators, Terman
and Wang used a global inhibitory mechanism to achieve
desynchronization [11]. The resulting network is called LE-
GION, standing for Locally Excitatory Globally Inhibitory
Oscillator Networks [20].
The original description of LEGION is based on Terman-
Wang oscillators, and basic mechanisms extend to other
relaxation oscillator models. Each oscillator i is defined as
²
xi = f (xi ) − yi + Ii + Si + ρ (6)
²
yi = ε[g(xi ) − yi ] (6)
x
Here f( ) and g(x) are as given in Eq. (5). The parameter
ρ denotes the amplitude of Gaussian noise; to reduce the
chance of self-generating oscillations the mean of noise is
set to −ρ. In addition to test robustness, noise plays the
role of assisting desynchronization. The term Si denotes
the overall input from other oscillators in the network:


Si = Wik H(xk − θx ) − Wz H(z − θz ) (7)
k ∈ N(i)
where Wik is the dynamic connection weight from k to i, and
N(i) is the set of the adjacent oscillators that connect to i.
In a two-dimensional (2-D) LEGION network, N(i) in the
simplest case contains four immediate neighbors except on
boundaries where no wrap-around is used, thus forming a
2-D grid. This architecture is shown in Fig. 5. H stands for
the Heaviside function, defined as H(ν) = 1 and H(ν) = 0 if
ν < 0. θx is a threshold above which an oscillator can affect
its neighbors. Wz is the weight of inhibition from the global
inhibitor z, whose activity is defined as
²
z = φ(σ∞ − z) (8)
where φ is a parameter. The quantity σ∞ = 1 if xi ≥ θz for at
least one oscillator i, and σ∞ = 0 otherwise. Hence θz (see
also Eq. (7)) represents a threshold.

Figure 6. Selective gating with two oscillators coupled through a
global inhibitor. C and CZ indicate the uncoupled and the inhibited
cubic, respectively. The two oscillators o1 and o2 start at time 0.
When o1 jumps up at t = t1 the cubic corresponding to both o1 and
o2 is lowered from C to CZ . This prevents o2 from jumping up until
o1 jumps down at t = t2 and releases o2 from the inhibition. LK and
RK indicate the left knee and the right knee of C, respectively. PZ
denotes a stable fixed point at an intersection point between CZ
and the sigmoid.
The dynamic weights Wik ’s are formed on the basis of
permanent weights Tik ’s according to the mechanism of dy-
namic normalization [21] [22], which ensures that each os-
cillator has equal overall weights of dynamic connections,
WT , from its neighborhood. According to Ref. [11], weight
normalization is not a necessary condition for LEGION to
work, but it improves the quality of synchronization. More-
over, based on external input Wik can be determined at the
start of simulation.
To illustrate how desynchronization between blocks of
oscillators is achieved in a LEGION network, let us con-
sider an example with two oscillators that are coupled only
through the global inhibitor. Each oscillator is meant to cor-
respond to an oscillator block that represents a pattern in a
scene. The same notations introduced earlier are used here.
Again, assume that both oscillators are in the silent phase
and close to each other with y1 < y2 , as shown in Fig. 6. The
singular solution of the system consists of several pieces,
where the first one lasts until o1 reaches LK at t = t1 . When
both oscillators are on LB, z = 0. The second piece starts
when o1 jumps up, and when o1 crosses θz , σ∞ switches from
0 to 1, and z → 1 on the fast time scale. When z crosses θz ,
the cubic corresponding to both o1 and o2 lowers from C to
CZ , the inhibited cubic. The third piece is when o1 is the
active phase, while o2 is in the silent phase. The parame-
ters are chosen so that CZ intersects with the sigmoid at
a stable fixed point PZ along LB as shown in Fig. 6. This
guarantees that o2 → PZ , and o2 cannot jump up as long as
o1 is on RB, which lasts until o1 reach the right knee of CZ
at t = t2 . The fourth piece starts when o1 jumps down to
LB. When o1 crosses θz , z → 0 in fast time. When z crosses
θz , the cubic corresponding to both o1 and o2 returns to C.
There are now two cases to consider. If o2 lies below LK, as
shown in Fig. 6, then o2 jumps up immediately. Otherwise
both o1 and o2 lie on LB, with o2 leading the way. This new
silent phase terminates when o2 reaches LK and jumps up.
Relaxation Oscillators and Networks 5
The above analysis demonstrates the role of inhibition
in desynchronizing the two oscillators: o1 and o2 are never
in the active phase simultaneously. In general, LEGION
exhibits a mechanism of selective gating, whereby an os-
cillator, say oi jumping to its active phase quickly acti-
vates the global inhibitor, which selectively prevents the
oscillators representing different blocks from jumping up,
without affecting oi ’s ability in recruiting the oscillators
of the same block because of local excitation. With the se-
lective gating mechanism, Terman and Wang proved the
following theorem. For a LEGION network there is a do-
main of parameters and initial conditions in which the net-
work achieves both synchronization within blocks of oscil-
lators and desynchronization between different blocks in
no greater than N cycles of oscillations, where N is the num-
ber of patterns in an input scene. In other words, both syn-
chronization and desynchronization are achieved rapidly.
The following simulation illustrates the process of syn-
chronization and desynchronization in LEGION [20]. Four
patterns – two O’s, one H, and one I, forming the word
OHIO – are simultaneously presented to a 20 × 20 LE-
GION network as shown in Figure 7(a). Each pattern is
a connected region, but no two patterns are connected to
each other. The oscillators under stimulation become oscil-
latory, while those without stimulation remain excitable.
The parameter ρ is set to represent 10% noise compared to
the external input. The phases of all the oscillators on the
grid are randomly initialized. Figs. 7(b)–7(f) show the in-
stantaneous activity (snapshot) of the network at various
stages of dynamic evolution. Fig. 7(b) shows a snapshot of
the network at the beginning of the simulation, display-
ing the random initial conditions. Fig. 7(c) shows a snap-
shot shortly afterwards. One can clearly see the effect of
synchronization and desynchronization: all the oscillators
corresponding to the left O are entrained and have large
activity; at the same time, the oscillators stimulated by the
other three patterns have very small activity. Thus the left
O is segmented from the rest of the input. Figures 7(d)–(f)
show subsequent snapshots of the network, where differ-
ent patterns reach the active phase and segment from the
rest. This successive “popout” of the objects continues in an
approximately periodic fashion as long as the input stays
on. To provide a complete picture of dynamic evolution, Fig.
7(g) shows the temporal evolution of every oscillator. Syn-
chronization within each object and desynchronization be-
tween them are clearly shown in three oscillation periods,
which is consistent with the theorem proven in [11].
Time Delay Networks
Time delays in signal transmission are inevitable in both
the brain and physical systems. In local cortical circuits,
for instance, the speed of nerve conduction is less than 1
mm/ms such that connected neurons 1 mm apart have a
time delay of more than 4% of the period of oscillation as-
suming 40 Hz oscillations. Since small delays may com-
pletely alter the dynamics of differential equations, it is
important to understand how time delays change the be-
havior, particularly synchronization, of relaxation oscilla-
tor networks.
6 Relaxation Oscillators and Networks
Campbell and Wang [23] studied locally coupled relax-
ation oscillators with time delays. They revealed the phe-
nomenon of loose synchrony in such networks. Loose syn-
chrony in networks with nearest neighbor coupling is de-
fined as follows. Coupled oscillators approach each other so
that their time difference is less than or equal to the time
delay between them. They analyzed a pair of oscillators
in the singular limit ε → 0, and gave a precise diagram in
parameter space that indicates regions of distinct dynami-
cal behavior, including loosely synchronous and antiphase
solutions. The diagram points out that loose synchrony ex-
ists for a wide range of time delays and initial conditions.
Numerical simulations show that the singular solutions
derived by them extend to the case 0 < ε  1. Furthermore,
through extensive simulations they conclude that their pa-
rameter diagram for a pair of oscillators says much about
networks of locally coupled relaxation oscillators. In partic-
ular, the phenomenon of loose synchrony exists in a similar
way. Figure 8 demonstrates loosely synchronous behavior
in a chain of 50 oscillators with a time delay that is 3%
of the oscillation period between adjacent oscillators. The
phase relations between the oscillators in the chain become
Figure 7. Synchronization and desynchronization
in LEGION. (a) A scene composed of four patterns
which were presented (mapped) to a 20 × 20 LE-
GION network. (b) A snapshot of the activities of the
oscillator grid at the beginning of dynamic evolution.
The diameter of each black circle represents the x
activity of the corresponding oscillator. (c) A snap-
shot taken shortly after the beginning. (d) Another
snapshot taken shortly after (c). (e) Another snap-
shot taken shortly after (d). (f) Another snapshot
taken shortly after (e). (g) The upper four traces show
the combined temporal activities of the oscillator
blocks representing the four patterns, respectively,
and the bottom trace shows the temporal activity of
the global inhibitor. The ordinate indicates the nor-
malized x activity of an oscillator. Since the oscilla-
tors receiving no external input are excitable during
the entire simulation process, they are excluded from
the display. The activity of the oscillators stimulated
by each object is combined into a single trace in the
figure. The differential equations were solved using
a fourth-order Runge-Kutta method (from [20]).
stabilized by the third cycle.
Two other results regarding relaxation oscillator net-
works with time delays are worth mentioning. First, Camp-
bell and Wang [23] identified a range of initial conditions in
which the maximum time delays between any two oscilla-
tors in a locally coupled network can be contained. Second,
they found that in LEGION networks with time delay cou-
pling between oscillators, desynchronous solutions for dif-
ferent oscillator blocks are maintained. Thus, the introduc-
tion of time delays does not appear to impact the behavior
of LEGION in terms of synchrony and desynchrony.
Subsequently, Fox et al. [24] proposed a method to
achieve zero phase-lag synchrony in locally coupled relax-
ation oscillators with coupling delays. They observed that
different speeds of motion along different nullclines could
result in rapid synchronization. Their analysis in particu-
lar shows how to choose appropriate y nullclines to induce
different speeds of motion, which in turn lead to zero-lag
synchrony. Numerical simulations demonstrate that their
analytical results obtained in the case of two coupled os-
cillators extend to 1-D and 2-D networks. More recently,
Sen and Rand [25] numerically investigated the dynam-

ics of a pair of van der Pol oscillators coupled with time
delays. Their comprehensive analysis revealed regions in
the 2-D plane of coupling strength and time delay where
stable zero-lag synchrony occurs, as well as regions where
antiphase solutions exist. Interestingly, there is an over-
lap between synchronous and antiphase solutions; in other
words, the coupling and delay parameters can be chosen
so that the two modes of behavior are both stable, a phe-
nomenon of bi-rhythmicity.
APPLICATIONS TO SCENE ANALYSIS
A natural scene generally contains multiple objects, each of
which can be viewed as a group of similar sensory features.
A major motivation behind studies on oscillatory correla-
tion is scene analysis, or the segmentation of a scene into a
set of coherent objects. Scene segmentation, or perceptual
organization, plays a critical role in the understanding of
natural scenes. Although humans perform it with apparent
ease, the general problem of scene segmentation remains
unsolved in sensory and perceptual information process-
ing.
Oscillatory correlation provides an elegant and unique
way to represent results of segmentation. As illustrated in
Fig. 7, segmentation is performed in time; after segmen-
tation, each segment pops out at a distinct time from the
network and different segments alternate in time. On the
basis of synchronization and desynchronization properties
in relaxation oscillator networks, substantial progress has
been made to address the scene segmentation problem; see
Wang [26] for a comprehensive review.
Image Segmentation
Wang and Terman [22] studied LEGION for segmenting
real images. In order to perform effective segmentation,
LEGION needs to be extended to handle images with noisy
regions. Without such extension, LEGION would treat each
region, no matter how small it is, as a separate segment,
resulting in many fragments. A large number of fragments
degrade segmentation results, and a more serious prob-
lem is that it is difficult for LEGION to produce more than
several (5 to 10) segments. In general, with a fixed set of
parameters, LEGION can segment only a limited number
of patterns [11]. This number depends on the ratio of the
times that a single oscillator spends in the silent and ac-
tive phases; see, for example, Figs. 3 and 7. This limit is
called the segmentation capacity of LEGION [22]. Noisy
fragments therefore compete with major image regions for
becoming segments, and the major segments may not be
extracted as a result. To address this problem of fragmen-
tation, they introduced the notion of lateral potential for
each oscillator, which allows the network to distinguish be-
tween major blocks and noisy fragments. The basic idea is
that a major block must contain at least one oscillator, de-
noted as a leader, which lies in the center area of a large ho-
mogeneous image region. Such an oscillator receives large
lateral excitation from its neighborhood, and thus its lat-
eral potential is charged high. A noisy fragment does not
contain such an oscillator.
Relaxation Oscillators and Networks 7
More specifically, a new variable pi denoting the lateral
potential for each oscillator i is introduced into the defini-
tion of the oscillator (cf. (6)). pi → 1 if i frequently receives
a high weighted sum from its neighborhood, signifying that
i is a leader, and the value of pi determines whether or not
the oscillator i is a leader. After an initial time period, only
leaders can jump up without lateral excitation from other
oscillators. When a leader jumps up, it spreads its activ-
ity to other oscillators within its own block, so they can
also jump up. Oscillators not in this block are prevented
from jumping up because of the global inhibitor. Without
a leader, the oscillators corresponding to noisy fragments
cannot jump up beyond the initial period. The collection of
all noisy regions is called the background, which is gener-
ally discontiguous.
Wang and Terman obtained a number of rigorous re-
sults concerning the extended version of LEGION [22]. The
main analytical result states that the oscillators with low
lateral potentials will become excitable after a beginning
period, and the asymptotic behavior of each oscillator be-
longing to a major region is precisely the same as the net-
work obtained by simply removing all noisy regions. Given
the Terman-Wang theorem on original LEGION, this im-
plies that after a number of cycles a block of oscillators cor-
responding to a major region synchronizes, while any two
blocks corresponding to different major regions desynchro-
nize. Also, the number of periods required for segmentation
is no greater than the number of major regions plus one.
For gray-level images, each oscillator corresponds to a
pixel. In a simple scheme for setting up lateral connections,
two neighboring oscillators are connected with a weight
proportional to corresponding pixel similarity. To illustrate
typical segmentation results, Fig. 9(a) displays a gray-level
aerial image to be segmented. To speed up simulation with
a large number of oscillators needed for processing real
images, Wang and Terman abstracted an algorithm that
follows LEGION dynamics [22]. Fig. 9(b) shows the re-
sult of segmentation by the algorithm. The entire image
is segmented into 23 regions, each of which corresponds to
a different intensity level in the figure, which indicates the
phases of oscillators. In the simulation, different segments
rapidly popped out from the image, as similarly shown in
Fig. 7. As can be seen from Fig. 9(b), most of the major
regions were segmented, including the central lake, major
parkways, and various fields. The black scattered regions
in the figure represent the background that remains in-
active. Due to the use of lateral potentials, all these tiny
regions stay in the background.
Auditory Scene Analysis
A listener in an auditory environment is generally exposed
to acoustic energy from different sources. In order to un-
derstand the auditory environment, the listener must first
disentangle the acoustic wave reaching the ears. This pro-
cess is referred to as auditory scene analysis. According to
Bregman [27], auditory scene analysis takes place in two
stages. In the first stage, the acoustic mixture reaching the
ears is decomposed into a collection of sensory elements (or
segments). In the second stage, segments that likely arise
from the same source are grouped to form a stream that is
8 Relaxation Oscillators and Networks

Figure 8. Loose synchrony in a chain of 50 relax-

ation oscillators (from [23]). This network achieves
loose synchrony and stability by the third period of
oscillation.

Figure 9. Image segmentation (from [22]). (a) A

gray-level image consisting of 160 × 160 pixels. (b)
Result of segmenting the image in (a). Each segment
is indicated by a distinct gray level. The system pro-
duces 23 segments plus a background, which is indi-
cated by the black scattered regions in the figure.

Figure 10. Speech segregation (from [30]). (a) Peripheral responses to a mixture of voiced ut-
terance and telephone ringing. The 2-D response is produced by 128 auditory filters with center
frequencies ranging from 80 Hz to 5 kHz, over 150 time frames. (b) Segregated speech that is in-
dicated by white pixels representing active oscillators at a time. (c) Segregated background that is
indicated by white pixels representing active oscillators at a different time.

a perceptual representation of an auditory event.
Auditory segregation was first studied from the oscil-
latory correlation perspective by von der Malsburg and
Schneider [14]. They constructed a fully connected oscil-
lator network, each oscillator representing a specific audi-
tory feature. Additionally, there is a global inhibitory os-
cillator introduced to segregate oscillator groups. With a
mechanism of rapid modulation of connection strengths,
they simulated segregation based on onset synchrony, i.e.,
oscillators simultaneously triggered synchronize with each
other, and these oscillators desynchronize with those rep-
resenting another stream presented at a different time.
However, due to global connectivity that is unable to en-
code topological relations, their model cannot simulate the
basic phenomenon of stream segregation.
By extending LEGION to the auditory domain, Wang
proposed an oscillator network for addressing stream seg-
regation [28]. The basic architecture is a 2-D LEGION net-
work, where one dimension represents time and another
represents frequency. This network, plus systematic delay
lines, can group auditory features into a stream by phase
synchronization and segregate different streams by desyn-
chronization. The network demonstrates a set of psycholog-
ical phenomena regarding auditory scene analysis, includ-
ing dependency on frequency proximity and temporal prox-
imity, sequential capturing, and competition among differ-
ent perceptual organizations [27]. Brown and Wang [29]
used an array of relaxation oscillators for modeling the per-
ceptual segregation of double vowels. It is well documented
that the ability of listeners to identify two simultaneously
presented vowels is improved by introducing a difference
in fundamental frequency (F0) between the vowels. Prior
to the oscillator array, an auditory mixture is processed by
an auditory filterbank, which decompose an acoustic sig-
nal into a number of frequency channels. Each oscillator
in the array receives an excitatory input from its corre-
sponding frequency channel. In addition, each oscillator
sends excitation to a global inhibitor which in turn feeds
back inhibition. The global inhibitor ensures that weakly
correlated groups of oscillators desynchronize to form dif-
ferent streams. Simulations on a vowel set used in psy-
chophysical studies confirm that the results produced by
their oscillator array qualitatively match the performance
of human listeners; in particular vowel identification per-
formance increases with increasing difference in F0.
Subsequently, Wang and Brown [30] studied a more dif-
ficult problem, speech segregation, on the basis of oscil-
latory correlation. Their model embodies Bregman’s two-
stage conceptual model by introducing a two-layer network
of relaxation oscillators. The first layer is a LEGION net-
work with time and frequency axes that segments an au-
ditory input into a collection of contiguous time-frequency
regions. This segmentation is based on cross-channel corre-
lation between adjacent frequency channels and temporal
continuity. The second layer, which is a laterally connected
network, then groups auditory segments produced in the
first layer on the basis of common periodicity. More specif-
ically, dominant F0 detected within a time frame is used
to divide all frequency channels into those that are con-
sistent with F0 and the rest. As a result, the second layer
segregates the segments into a foreground stream and the
Relaxation Oscillators and Networks 9
background. Figure 10 shows an example of segregating a
mixture of a voiced utterance and telephone ringing. The
input mixture after peripheral analysis is displayed in Fig.
10(a). The segregated speech stream and the background
are shown in Figs. 10(b) and 10(c), respectively, where a
segment corresponds to a connected region.
CONCLUDING REMARKS
Relaxation oscillations are characterized by two time
scales, and exhibit qualitatively different behaviors than
sinusoidal or harmonic oscillations. This distinction is par-
ticularly prominent in synchronization and desynchroniza-
tion in networks of relaxation oscillators. The unique prop-
erties in relaxation oscillators have led to new and promis-
ing applications to neural computation, including scene
analysis. It should be noted that networks of relaxation os-
cillations often lead to very complex behaviors other than
synchronous and antiphase solutions. Even with identical
oscillators and nearest neighbor coupling, traveling waves
and other complex spatiotemporal patterns can occur [31].
Relaxation oscillations with a singular parameter lend
themselves to analysis by singular perturbation theory
[32]. Singular perturbation theory in turn yields a geomet-
ric approach to analyzing relaxation oscillation systems,
as illustrated in Figs. 4 and 6. Also based on singular so-
lutions, Linsay and Wang [33] proposed a fast method to
numerically integrate relaxation oscillator networks. Their
technique, called the singular limit method, is derived in
the singular limit ε → 0. A numerical algorithm is given for
the LEGION network, and it produces large speedup com-
pared to commonly used integration methods such as the
Runge-Kutta method. The singular limit method makes it
possible to simulate large-scale networks of relaxation os-
cillators.
Computation using relaxation oscillator networks is in-
herently parallel, where each single oscillator operates in
parallel with all the other oscillators. This feature, plus
continuous-time dynamics makes oscillator networks at-
tractive for direct hardware implementation. Using CMOS
technology, for example, Cosp and Madrenas [34] fabri-
cated a VLSI chip for a 16 × 16 LEGION network and used
the chip for a number of segmentation tasks. With its dy-
namical and biological foundations, oscillatory correlation
promise to offer a general computational framework.
ACKNOWLEDGMENTS
The preparation for this article was supported in part by
an AFOSR grant (FA9550-04-1-0117) and an NSF grant
(IIS-0534707).
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DELIANG WANG
Department of Computer
Science & Engineering
Center for Cognitive Science,
The Ohio State University,
Columbus, OH, 43210-1277

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 SAMPLE-AND-HOLD CIRCUITS 651

SAMPLE-AND-HOLD CIRCUITS

Sample-and-hold circuits were first introduced as a front end

for analog-to-digital data converters. Processing electrical in-
formation in a discrete or digital fashion appears to be more
reliable, repeatable, and accurate than in the analog domain.
However, converting analog signals to digital ones can be of-
ten disrupted if the input signal changes during the conver-
sion cycle. The exact moment in time when the input is
sensed and compared with a reference can be different across
the data converter, resulting in aperture errors. Conse-
quently, it appears useful to memorize the input signal and
hold it constant for the comparators that perform the conver-
sion to the digital domain. Among different data-converter ar-
chitectures, only the so-called ‘‘flash’’ ones can perform with-
out requiring a sample-and-hold circuit although its usage is
usually beneficial even in this case.
Another application for sample-and-hold circuits is as a
back end for digital-to-analog data converters. The analog
voltage generated by these converters is subject to glitches
due to the transitions occurring between consecutive digital
input codes. A sample-and-hold circuit can be used to sample
the analog voltage between the glitches, effectively smoothing
the output waveform between two held output-voltage levels.
Then, a low-pass filter following the sample-and-hold circuit
is able to restore the continuous-time analog waveform much
more efficiently than in the presence of glitches.
Switched-capacitor or switched-current signal processing
inherently requires the input signal to be sampled and held
for subsequent operations. There is a widespread usage of
this type of processing; hence a variety of applications employ
some sort of sample-and-hold circuit as a front end. It can be
inferred that any sampled-data system requires a sample-
and-hold operation at some point.
When used inside a larger system, the performance of a
sample-and-hold circuit could limit the overall performance.
Speed, accuracy, and power consumption are a few criteria to
be observed during the design process or simply from a user’s
perspective. This article is intended to describe and present
different implementations of sample-and-hold circuits as well
as associated nonidealities. The following section includes a
list of errors that make a real-life implementation different
from the ideal sample-and-hold circuit model. The third sec-
tion describes different implementations of these circuits
organized into metal oxide semiconductor (MOS) transistor-
based open-loop architectures, MOS-transistor-based closed-
loop architectures, bipolar-device-based architectures, and
current-mode architectures. The last section of the article out-
lines some conclusions and provides a brief overview regard-
ing modern applications of sample-and-hold circuits.

SAMPLE-AND-HOLD PERFORMANCE SPECIFICATIONS

A simplified model of a sample-and-hold circuit is a switch

connected between the input and one terminal of a holding
capacitor. The other terminal of the capacitor is tied to a ref-
erence voltage (ground), and the output of the sample-and-
hold is the voltage across the capacitor. The switch is con-
trolled by a digital signal that determines the sampling time
and the hold duration. Ideally, the output voltage tracks the
input exactly when the switch is closed (track or sample
mode) and stores a sample of the input voltage when the
J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.
652 SAMPLE-AND-HOLD CIRCUITS

Sampling moment
Error band

Error band
Input Output

Settling time Pedestal

error
Output
Offset Settling time

Figure 1. Offset and settling time during sample mode. The output Figure 3. Settling time and pedestal voltage during the sample-to-
of a sample-and-hold circuit settles to a step at the input. hold transition.

switch opens (hold mode). In reality the behavior of the circuit specification discussed in the preceding subsection. This non-
deviates from this ideal model affecting the performance. The ideal behavior is shown in Fig. 3. Another nonideal effect is
following subsections describe the specifications used to char- also presented in Fig. 3 and is called the pedestal error. This
acterize sample-and-hold circuits. error appears as an offset in the output signal and is due
to charge injected from the sampling switch, which could be
Sample-Mode Specifications dependent on the input signal, implying nonlinearity.
Aperture time is another important specification and is de-
The operation during the sample mode is similar to a voltage
fined as the amount of time it takes for the sampling switch
or current amplifier. Thus any specifications used to charac-
to open. This is attributed to the finite slope of the clock and
terize an amplifier can be used to characterize the sample-
a gradual transition of the sampling switch from a low-imped-
and-hold circuit in sample mode. Some of the key specifica-
ance (closed) to a high-impedance (opened) state. The signal
tions in this mode of operation are offset, settling time, gain
stored at the output is a function of the aperture delay ta, the
error, and nonlinearity. The offset is defined as the difference
analog delay tda of the signal through the sample-and-hold cir-
between the input and the output with no signal applied at
cuit, and the digital delay tdd of the clock signal that turns off
the input. This is shown in Fig. 1. The time it takes for the
the switch. It can be ultimately characterized as shown in
output to settle within a certain error band around its final
Fig. 4 by an effective aperture time teff . The analog delay is
value with a step applied at the input is called the settling
caused by the frequency response of the sample-and-hold cir-
time. The size of the step is usually full scale as shown in Fig.
cuit, and the digital delay is produced by any logic in the path
1 unless specified otherwise. Gain error and nonlinearity are
of the external clock to the switch. The aperture jitter is the
both steady-state errors that describe the deviation of the
variation in the hold signal delay. In some applications, such
magnitude transfer characteristic from a straight line with a
as analog-to-digital data conversion, a constant delay in the
slope of 1. As represented in Fig. 2, the gain error appears as
sampling time is not important. However, aperture jitter
the deviation of the slope of line P1P2 from 45⬚ and can be
could be extremely damaging, adding significant noise to the
expressed as Gerror ⫽ 1 ⫺ tan ␪. One definition of nonlinearity
output signal and effectively lowering the resolution of the
is the maximum deviation of the transfer characteristic from
system.
line P1P2. This is also shown in Fig. 2. Other sample-mode
specifications include bandwidth, slew rate, distortion, and
Hold-Mode Specifications
noise, which also characterize a general amplifier, are defined
in a similar fashion. Ideally, the holding capacitor should be completely isolated
from any interference during the hold mode and the output
Sample- to Hold-Mode Specifications signal should remain constant. In a real-life implementation
there is always a small current flowing across the holding ca-
The switching from sample to hold mode is accompanied by
transients that appear in the output. The time it takes for
these transients to settle within a given error bound is called
the settling time, similar to the corresponding sample-mode Input
Output

End point = P2
tda ta
Internal hold
Output

clock tdd
Nonlinearity
External hold
Gain error = 1 – tan θ clock
θ
teff
Start point = P1 Input

Figure 2. Gain error and nonlinearity. A sample-and-hold circuit ex- Figure 4. Time delays that determine the effective aperture time
hibits gain error as deviation of line P1P2 from a 45⬚ slope, and nonlin- during the sample-to-hold transition: ta, aperture delay; tdd, digital
earity as curvature in the input–output characteristic. delay; tda, analog delay; teff , effective aperture time.

Sampling
moment
Input
Droop Feedthrough
(peak-to-peak)
Output
Figure 5. Droop and feed-through errors during hold mode.
pacitor during the hold mode. This nonideal effect produces
droop in the output signal as shown in Fig. 5. As an example,
in an analog-to-digital data converter the droop should not
exceed one-half of the least-significant bit value during the
conversion cycle. Generally, the droop current could be a bipo-
lar base current or simply junction leakage. Another specifi-
cation during the hold mode is the feedthrough from the input
signal. This occurs through parasitic capacitance between the
input and the output nodes of a sample-and-hold circuit, al-
though it can occur between other nodes in the system and
the output. Figure 5 also presents this effect. Again, in refer-
ence to the data-converter example, the feedthrough peak-to-
peak amplitude should not exceed one least significant bit of
the converter.
There are a few other factors that influence the perfor-
mance during the hold mode. Nonidealities in the holding ca-
pacitor can cause dielectric absorption. Consequently, the ca-
pacitor exhibits a memorylike behavior, corrupting the newly
stored sample in the direction of the previous sample. Electri-
cal noise is also a factor, and the value of the capacitor plays
an important role since the kT/C term (k is the Boltzmann
constant, T the absolute temperature in kelvin, and C the
holding capacitor value) is usually the main contributor.
Hold- to Sample-Mode Specifications
When switching from the hold to sample mode, there is a de-
lay between the sampling edge of the clock and the moment
the output settles to the steady state when it tracks the input.
This time is known as the acquisition time and is also deter-
mined by an error band. Since the input can change signifi-
cantly while the circuit is in hold mode, the acquisition time
is usually specified for a full-scale change in the input unless
mentioned otherwise.
IMPLEMENTATION OF SAMPLE-AND-HOLD CIRCUITS
If one starts with the basic ideal model for a sample-and-hold
circuit, there are various ways to implement a switch and a
capacitor in either discrete or monolithic forms. The interface
between this model and the input signal or adjacent system
blocks implies the usage of additional circuitry. There is also
added complexity from dealing with different circuit nonideal-
ities, an increase in operating speed, or a decrease in power
consumption. The following subsections embrace this gradual
approach from a basic model to a more complex structure,
which provides an implementation that is close to real life. A
variety of topologies and implementations is presented includ-
ing open- and closed-loop, bipolar, and MOS-based, as well as
current-mode circuits.
SAMPLE-AND-HOLD CIRCUITS 653
Open-Loop Sample-and-Hold Circuits
The simplest voltage-mode sample-and-hold circuit requires
only two elements: a switch and a capacitor, as shown in Fig.
6 (1–3). The switch is controlled by a clock signal ␾ that is
turned on and off each sample period. When the switch is on,
the input voltage appears on the capacitor, and the circuit is
actually in track mode. When the switch is turned off, the
signal voltage at that instance is sampled on the capacitor,
which holds the voltage constant until the next track phase.
Although this ideally implements the desired sample-and-
hold function using only two elements, the difficulty in realiz-
ing an ideal switch severely limits the performance of such a
design. Real switches are implemented using MOS or bipolar
transistors or diode bridges, each of which has its own idio-
syncrasies. This subsection will primarily focus on the use of
MOS switches, while circuits utilizing bipolar transistors or
diodes will be discussed in the following subsection.
A MOS transistor deviates from an ideal switch in several
ways, the most obvious of which is in terms of on-resistance.
When the MOS switch is turned on, it typically will have a
low drain-to-source voltage (VDS) and a high gate-to-source
voltage (VGS) [n-type MOS assuming (NMOS), opposite polar-
ity for p-type MOS (PMOS)], causing it to operate in the tri-
ode or nonsaturation region, where the drain-to-source cur-
rent (IDS) is given by (4)
W
IDS = K
[(VGS − VT )VDS − 12 VDS
2
] (1)
L
which, when VDS Ⰶ (VGS ⫺ VT), can be approximated as
W
IDS ≈ K
(V − VT )VDS (2)
L GS
where VT is the threshold voltage. The large-signal on-resis-
tance of the switch is then given by the voltage across the
device, VDS, divided by the current through it, IDS, yielding

−1
W
Rswitch ≈ K
(VGS − VT ) (3)
L
The switch on-resistance is clearly nonzero, meaning that the
circuit will exhibit some transient exponential settling when
the switch first turns on and then a low-pass filtering re-
sponse during steady-state operation while it remains on (for
input signal frequencies greater than dc). Clearly the switch
resistance must be designed properly to provide sufficient lev-
els of settling and bandwidth for the speed and precision
needed.
φ
φ
In Out In
Out
Figure 6. Simple sample-and-hold circuit with example signals
shown. When ␾ is high, the output tracks the input and when ␾ is
low, the output is held.
654 SAMPLE-AND-HOLD CIRCUITS
Not only is the resistance of the switch nonzero and depen-
dent on the semiconductor process parameter K⬘ and device
size (W and L), but it also varies with the voltage on the
source of the transistor, which will be a function of the input
voltage. If, as is done in the simplest cases, the gate of the
transistor is tied to a constant-supply-voltage level while the
switch is on, then the switch resistance varies with the input
signal, causing nonlinear dynamic circuit operation. If an
NMOS switch is used, then its on-resistance will rise toward
infinity as the input voltage approaches VDD ⫺ VT,n, limiting
the input range to voltages well below this. Similarly, a
PMOS switch will limit the input to voltages well above
VSS ⫹ 兩VT,p兩. A wider input range is obtained by using a com-
plementary MOS (CMOS) switch, consisting of an NMOS and
a PMOS switch in parallel, with the PMOS device driven by
the inverted version of the sampling signal ␾. This configura-
tion enables sampling of an input range extending from VSS
to VDD, although on-resistance of the switch will still vary sig-
nificantly over the entire range, giving rise to nonlinear dy-
namic performance. This effect can be avoided by driving the
switch gates with a bootstrapped version of the input signal
while the switches are on, such that both gates and sources
will vary similarly with respect to the input (5). This removes
the input signal dependence from the VGS term in Eq. (3),
making the on-resistance independent of the input, at least
to first order. In reality, higher-order effects will eventually
come into play to limit the linearity, but this technique is use-
ful in gaining some performance improvement.
Another limitation of the MOS switch is charge injection
and clock feedthrough, which are sometimes used inter-
changeably to describe two effects that occur when the switch
is turned off. When the transistor is on, charge collects under
the gate of the transistor to form the channel from drain to
source. When the switch is turned off, this charge exits the
channel primarily to the drain and source, with the propor-
tional split depending on speed of the clock transition and the
impedance seen by the charge in each direction (6). The part
of the charge that exits toward the sampling capacitor will
cause the capacitor voltage to drop slightly (assuming an
NMOS transistor with negative channel charge) from its im-
mediately previous value. This would only create a constant
pedestal error in the sample-and-hold circuit output if the
packet of charge were always the same, but unfortunately
this is not the case. The channel charge is approximately
given by
Qchannel ≈ CoxWL(VGS − VT ) (4)
which reveals that, if the gate of the switch is tied to a con-
stant supply voltage while turned on, then the channel charge
will be signal dependent. In reality, this signal dependence of
the injected charge is a major source of nonlinearity in the
sample-and-hold circuit.
The second effect, often termed clock feedthrough, is caused
by the MOS overlap capacitance between the gate and source
or drain connected to the sampling capacitor. As the gate volt-
age is dropping from a high on-voltage to a low off-voltage, the
transistor actually shuts off when the gate is approximately a
threshold voltage above the source or drain voltage. As the
gate voltage continues to fall further, the voltage step is ca-
pacitively coupled onto the sampling capacitor through the
MOS overlap capacitance, causing the voltage on the sam-
pling capacitor to change. Both of these charge effects can be
φ
2W
–––
L
In Out
W
φ –
L
Figure 7. Simple sample-and-hold circuit with dummy-switch com-
pensation for reducing the charge injection. The dummy device is half
the size (W/L vs. 2W/L) of the series switch device.
reduced by driving the gate with a bootstrapped version of the
input signal, which makes the effects independent of signal to
first order, just as in the case of switch on-resistance. The use
of a full CMOS switch rather than only a single NMOS or a
single PMOS device also gives a very rough cancellation of
these effects. The NMOS device will inject negative channel
charge onto the sampling capacitor, while the PMOS switch
will inject positive channel charge. Similarly, the charge cou-
pled through the overlap capacitances will also be in opposing
directions. Unfortunately, these cancellations do not hold as
the input is varied over its input range and so give little
benefit.
Dummy-switch cancellation is another technique that can
be used, though generally with limited effectiveness, to re-
duce charge injection and clock feedthrough. As shown in Fig.
7, a dummy-switch device with half the gate area of the main
switch is placed on the capacitor side of the sampling switch
and is clocked with an inverted version of the sampling signal
␾. Thus, during acquisition, the main switch is on and the
dummy switch is off. At the sampling instant, the dummy
switch is turned on, causing it to pull charge from the sam-
pling capacitor to form the channel under its gate. This
charge approximately cancels that injected by the main
switch, assuming roughly half of the main switch charge was
injected toward the capacitor.
The simple sample-and-hold circuit using a MOS switch
can also experience input signal feedthrough during the hold
mode due to the MOS overlap capacitances, especially when
sampling high-speed inputs. When the circuit is in hold mode,
the MOS gate will be pulled to the low supply voltage (assum-
ing an NMOS switch), typically by a digital gate’s output. The
digital gate will have a finite, nonzero resistance from its out-
put to the low supply voltage, yielding an effective circuit
such as that shown in Fig. 8. Analysis of this circuit reveals
a nonzero transfer function from the input to the sampled
output node, causing the feedthrough. Care must be taken
during the design process to characterize the level of feed-
through that occurs and keep it sufficiently low through a
low-resistance gate drive or more elaborate design modifica-
tions.
Coverlap Coverlap
In Out
Rdriver
Figure 8. Effective circuit of the simple sample-and-hold circuit us-
ing an NMOS switch while in hold mode. The gate is driven low by a
circuit with nonzero output resistance, such as a digital gate or clock
driver. The MOS overlap capacitances couple the input signal to the
output even with the MOS switch turned off.
 SAMPLE-AND-HOLD CIRCUITS 655

φ
input voltage is sampled across the capacitor through the
φ
series resistances of the two switches. The actual sampling
In Buffer Buffer Out In instant occurs when ␾1 falls, open-circuiting the right side of
C the capacitor. ␾1d then falls immediately afterward, discon-
necting the capacitor from the input signal. When ␾2 goes
Out high, an inverted version of the sampled input voltage ap-
pears at the right side of the capacitor and is buffered to the
Figure 9. Simple sample-and-hold circuit with input and output output. Note that this circuit cannot be termed a track-and-
buffering. hold circuit, since the output never tracks the input directly,
but instead has its input grounded while the input capacitor
is being charged. The advantage of this design is its avoidance
of signal-dependent charge-injection effects. The ␾1d falling
A fundamental trade-off occurs in this simple sample-and-
edge is intentionally delayed from the ␾1 falling edge in order
hold circuit between speed and linearity. In order for the cir-
to make only the ␾1 switch’s charge injection important (oth-
cuit to have high bandwidth and fast settling, a large width
erwise ␾1d is the same as ␾1). After the ␾1 switch is off, any
transistor with low on-resistance is needed. However, larger
further charge injection or transients at the left-hand side of
width also means more channel charge, which then increases
the capacitor will not affect the charge that has been isolated
the charge injection and generally reduces the circuit’s linear-
on the node at the right-hand side of the capacitor. In addi-
ity performance. While the sampling switch must be designed
tion, because the ␾1 switch always operates at ground poten-
to meet the speed and settling requirements of the given ap-
tial, its channel charge (and on-resistance) will always be the
plication, it should not be unnecessarily overdesigned to have
same, without the need for a bootstrapped gate drive. The
excessively low on-resistance.
only signal dependence left in the charge injected by the ␾1
Yet another limitation of the design shown in Fig. 6 is its
switch is due to variations in the impedance looking back to-
lack of drive capability while in hold mode. If this circuit is
ward the input signal source as the input voltage varies.
loaded by a resistive or switched capacitive load, then the
While this sample-and-hold circuit has an advantage with
sampled signal voltage on the capacitor will leak off while the
respect to charge injection, it also has a disadvantage in that
sampling switch is off. This problem is easily addressed by
it is sensitive to parasitic capacitance at the right-hand side
adding a unity-gain buffer at the output. The loading that
of the sampling capacitor. Parasitic capacitance to ground at
this sample-and-hold circuit places on the input signal source
this point will lead to charge redistribution during ␾2, thereby
can also be a problem in some applications, particularly for
attenuating the sampled voltage and causing a gain error in
sources with large output resistance or limited slew rate. This
the system. In addition, if the parasitic capacitor happens to
is also easily remedied with another unity-gain buffer, now
be nonlinear, such as the reverse-biased diode junction capac-
placed at the input. The resulting design is shown in Fig. 9.
itance associated with the ␾1 switch, then nonlinearity will
While these buffers do solve the loading problems, in reality
also be introduced along with the attenuation. These effects
each will have some amount of dc offset, gain error (i.e., the
are reduced by making the sampling capacitor sufficiently
gain of the buffer is not exactly unity), and nonlinearity, all
larger than the parasitic capacitors, but then settling is af-
of which will directly affect the offset, gain error, and nonline-
fected, and another trade-off between speed and linearity can
arity of the overall sample-and-hold circuit. The dynamic per-
be seen. An alternative solution to these problems is to use a
formance of the buffers is also a concern. When the sampling
closed-loop architecture, which exploits the benefits of nega-
switch is turned on, the input buffer may have to supply a
tive feedback within its design. These architectures are dis-
sudden impulse of current to the sampling capacitor, typically
cussed in a following subsection.
causing a transient settling response at the buffer output.
From an ideal standpoint, one would prefer a sample-and-
This may include both slewing and linear settling behavior,
hold circuit that did not have any reset phases or a track
both of which must settle out to the desired level of precision
phase, but would instead only transition from one hold state
before the sampling switch is opened. The buffers will also
to the next hold state, thus giving the circuitry that follows
have limited bandwidth, creating a steady-state amplitude
the maximum time to utilize the held signal. Although the
and phase error that varies with input frequency, indepen-
circuits shown in Figs. 9 and 10 provide a valid output for
dent of whether the buffer transient responses have settled
approximately half of the sampling period, this can be ex-
or not.
tended to a full sampling period simply by using two or more
While the simple open-loop sample-and-hold circuit shown
parallel sample-and-hold circuits that operate on different
in Fig. 6 does have many performance limitations, some of
clock phases and multiplexing among their outputs, as shown
these can be reduced or avoided by modifying the circuit ar-
in Fig. 11 (7). This multirate polyphase design approach
chitecture. An alternative open-loop sampling using three
trades off power and circuit area in exchange for an increase
clocks is shown in Fig. 10. While ␾1 and ␾1d are high, the
in effective sampling rate and a maximized valid output time.
While this works perfectly in theory, practical issues such as
matching from channel to channel will limit its range of appli-
φ 1d C cation. For example, if four parallel channels are used, each
In Buffer Out with a different dc offset and different gain, then the single
φ2 φ1 output after multiplexing will contain pattern noise even
when a zero input is applied. In addition, a modulation effect
can occur between the pattern noise and the signal, mixing
Figure 10. Modified sample-and-hold circuit using additional high-frequency components to low frequency and vice versa.
switches and an output buffer. If the input is band-limited and sufficiently oversampled,
656 SAMPLE-AND-HOLD CIRCUITS

φ 1A φ 1B have double the input and output swing as the single-ended

VIn 1 1 VOut
φ 1A
C rather than Vplus ⫺ Vground. This helps keep the signal higher
φ 2A
φ 2A φ 2B
φ 3A
1 1
C φ 4A
φ 1B
φ 3A φ 3B
φ 2B
1 1
C high-performance analog circuitry have accepted the need for
φ 3B
φ 4A φ 4B φ 4B
1 1
C SAMPLE-AND-HOLD CIRCUITS USING
Figure 11. Polyphase sample-and-hold architecture demonstrated
using four parallel channels, each phased separately, to achieve a
fourfold increase in effective sampling rate.
then the pattern noise and modulation artifacts can be kept
spectrally separate from the signal component and thus fil-
tered out in a later stage.
While all of the designs shown thus far have used a single
input voltage relative to ground and have provided a single
output also relative to ground, each of the circuits can easily
be converted to a fully differential configuration. Figure 12
demonstrates a fully differential version of the circuit origi-
nally shown in Fig. 10, in which the input is applied as the
difference between two node voltages, and the output is sup-
plied as the difference between the two output node voltages.
Fully differential configurations are widely used in high-per-
formance analog designs due to a variety of advantages. If
one assumes that corresponding switches and components are
matched, a fully differential circuit will provide cancellation
of dc offsets associated with charge injection and clock feed-
through due to the (ideally) same charge being injected onto
both sampling capacitors. Because the output is used differen-
tially, only the difference between the sampling capacitor
voltages is important, and so the identical charge that was
injected into both capacitors cancels out. Fully differential cir-
cuits also have low (ideally zero) even-order harmonic distor-
tion components due to their symmetry if both sides of the
differential circuitry are matched. These designs also exhibit
higher power-supply rejection than single-ended designs due
to power-supply noise, causing a similar response on both
sides of the differential circuit, which then cancels out when
only the difference in the two output nodes is considered. In
addition, even though the voltage swing of the input and out-
put nodes remains the same, the fully differential circuit will
φ 1d C switch. The current source sinks a bias current I through T1,
+ φ2 φ1 ++
In Buffer
– φ2 φ1 ––
C The value of the voltage VB (voltage at the buffer output) dur-
φ 1d
Figure 12. Fully differential version of the sample-and-hold circuit
shown in Fig. 10.
design, due to the fact that the signals are now Vplus ⫺ Vminus
above the noise floor, thus maintaining a higher signal-to-
noise ratio. While fully differential circuits provide numerous
advantages, they also require approximately double the area
and power of a single-ended design, and extra circuitry and
complexity are needed to control the common-mode voltages
of nodes throughout the design. However, most designers of
differential circuitry and utilize it extensively.
BIPOLAR AND DIODE DEVICES
The basic components of sample-and-hold circuits can be also
implemented using bipolar technology. Semiconductor diodes
and bipolar transistors are potential candidates for per-
forming the switch function as well as input and output buff-
ering. The holding capacitor could be a metal-metal or a MOS
structure in the case of monolithic implementations or just a
discrete component otherwise. The first part of this subsection
will discuss sample-and-hold circuits in which the required
switching operation is implemented using bipolar transistors.
Following this, diode-bridge sample-and-hold circuits are in-
troduced and the subsection is concluded with a discussion
regarding performance comparison between MOS and bipolar
implementations.
Although the bipolar transistor exhibits similar behavior
to a MOS transistor, when used in amplifier configurations,
there are fundamental differences that prohibit its usage di-
rectly as a switch in the same fashion as a MOS-based one.
As an example, for an n–p–n bipolar transistor, when the
base voltage is lower or equal to its collector and emitter volt-
ages, the resistance seen between the emitter and collector is
high. When its base voltage is higher (both base–collector and
base–emitter junctions are forward biased), the resistance
‘‘seen’’ between the emitter and collector becomes low; how-
ever, it is very nonlinear. Consequently, an arrangement such
as that in Fig. 6 from the previous subsection, where the
switch was replaced with an n–p–n transistor, is not possible.
Consequently, bipolar transistors can be used as switches al-
though not in series with the holding capacitor. An alterna-
tive is to use bipolar transistors configured as source followers
in the signal path and employ bipolar-based switches to con-
trol their bias current.
Figure 13 presents a simple sample-and-hold circuit in
which the switch is constituted by the combination of bipolar
transistors T1–T3 and a current source I. When the clock sig-
nal is high, the circuit is in track mode. Transistors T2 and
T3 can be regarded, respectively, as a closed and an open
which behaves like an emitter follower, and the output volt-
age Vout tracks the input Vin. The buffer is assumed to have
+ unity gain. When the clock signal is low, transistor T2 be-
Out comes an opened switch and transistor T3 appears as a closed
–
one, and the current I flows entirely through transistor T3.
ing this state is determined by the buffer circuitry and the
value of current I, and is designed to be low enough such that
transistor T1 is turned off. This is the hold state, when Vout is
preserved on Chold until transistor T1 is reconfigured again as
 SAMPLE-AND-HOLD CIRCUITS 657

Vsupply the value of the current source I, since VT is the thermal volt-
age (VT ⫽ kT/q 앒 26 mV at 300 K, where k is Boltzmann’s
constant, q is the electron charge, and T is the absolute tem-
Hold Hold Hold perature). In the ideal case of an ‘‘on’’ switch in series with
Vin track track track
VB the holding capacitor (as in Fig. 6), the relation between the
Buffer
Clock input and the output voltages is
T1
Vout
Vout (s) 1
Clock = (7)
Clock Clock Vin (s) 1 + sCholdRswitch
T3 T2 Chold
From Eqs. (6) and (7) it can be inferred that the equivalent
I value of the ‘‘on’’ switch resistor for the circuit from Fig. 13 is
Vin
1 VT
Rswitch = = (8)
gm,T1 I
Vout

As discussed in the open-loop sample-and-hold circuit subsec-

Figure 13. Sample-and-hold circuit using bipolar transistors as
switches. Transistors T2 and T3 act like switches while transistor T1
and the buffer condition the signal from input to output.
an emitter follower. An example for the buffer circuit is
shown in Fig. 14. In track mode, the gain of the buffer is
gm,TB RC
GB = ≈1
1 + gm,TB RE
if RC ⫽ RE and gm,TB Ⰷ 1, where TB, RE, and RC are the transis-
tor (gm,TB is its transconductance) and respectively the resis-
tors from Fig. 14. The latter assumption is justified if the
transconductance value is large enough, or equivalently,
there is enough bias current flowing through transistor TB.
Unlike the MOS transistor case, the transconductance of a
bipolar device biased in the linear region is not dependent on
the process parameters and is determined solely by the bias
current, in a first-order approximation. This is advantageous
since the equivalent Rswitch value in the track mode depends
on the source-follower transconductance value. The relation
between input and output voltages of the sample-and-hold cir-
cuit from Fig. 13 can be expressed in the s-transform domain
as
Vout (s) gm,T1
= GB
Vin (s) gm,T1 + sChold
where gm,T1 ⫽ I/VT is the transconductance value of transistor
T1. As mentioned earlier, this value is dependent solely on
Vsupply
RC
Vb
Vin
TB
RE
Figure 14. An input buffer for the sample-and-hold circuit in Fig. 13.
tion, the nonlinearity of this equivalent Rswitch resistor is a ma-
jor contributor to the degradation in performance of the sam-
ple-and-hold circuit. Another contributor is the gain error
associated with the equivalent switch (source follower T1 on
Fig. 13) or the input and output buffering operations. Equa-
tions (6) and (8) suggest that in a first-order approximation,
there is no nonlinearity associated with transistor T1 and the
only dc gain error is generated by GB. However, the current
(5)
source that generates the current I does have finite output
impedance, and this introduces gain and linearity error. For
example, if RI is defined as the current-source output imped-
ance, the dc gain of the circuit in track mode acquires a new
term gm,T1RI /(1 ⫹ gm,T1RI), where gm,T1 is the transconductance
of transistor T1. Also, the equivalent ‘‘on’’ switch resistance
becomes
RI
Rswitch = (9)
1 + gm,T1RI
A given linearity requirement will constrain the input signal
range such that there are small enough variations in the bias
current I due to changes in the input.
There is no buffering at the output shown in Fig. 13, al-
though the circuit would require it for driving a low imped-
ance. Besides gain error, the output buffering introduces
droop errors when implemented with bipolar transistors. The
(6)
base current has significantly larger values than the gate cur-
rent associated with MOS-transistor-based buffers. This ef-
fect can be alleviated by using differential topologies in which
the base current produces a shift in the common mode but
leaves the differential voltage across holding capacitors unaf-
fected. Charge injection in bipolar implementations of
switches is less destructive than that in the MOS transistor
case. The reason is a smaller dependency between the amount
of charge dumped into the holding capacitor at the transition
moment from track to hold and the input voltage. Differential
topologies also attenuate this effect as in the droop error case.
Ultimately, the hold-mode feed through, from the Vb voltage
(in Fig. 13) to Vout through the base-emitter capacitance of
transistor T1 can seriously affect performance. Ways to cope
with this are reducing the size (area) of transistor T1 and,
again, employing differential structures that allow placing
cross-coupled capacitors from the input to the output as de-
scribed in Ref. 8.
Another sample-and-hold circuit based on bipolar transis-
tors is shown in Fig. 15 (9). Transistors TN1, TN2, and TN3
658 SAMPLE-AND-HOLD CIRCUITS

Vsupply

I1 I2

Clock
TN3
Chold
Vin Vout
Input Output
buffer buffer

Clock Clock
TN1 TN2

TP1 TP2

Rb1 Rb2 Clock

Clock

(a) Basic schematic

Chold Chold
Vin Vout Vin Vout
Input Output Input Output
buffer buffer buffer buffer
Figure 15. Sample-and-hold circuit where the hold-
ing capacitor is connected in series between input and
output; (a) detailed schematic with TN1, TN2, TP1,
TP2 as switches, and input–output buffering; (b) sim- Vr2 Vr1
plified schematic during track mode; (c) simplified
schematic during hold mode. (b) Track (sample) mode, clock low (c) Hold mode, clock high

are n–p–n devices that function as series switches for steer- tor Rb2, which is designed in a similar fashion as Rb1 such that
ing bias currents. Transistors TP1 and TP2 are p–n–p devices the voltage drop on it, IRb2, turns off transistor TP2. The sche-
and work in either linear region or are turned off. For simplic- matic, again, can be simplified as in Fig. 15(c). The input
ity, it is assumed that the input and output buffers have unity buffer provides some current IB, which flows through transis-
gain. When the clock signal is low, transistor TN2 is turned tor TP1 biasing it in the linear region. Vr1 can be also ex-
off, and transistors TN1 and TN3 are turned on. Current I1 pressed as in Eq. (10)
[generated by the current source as shown in Fig. 15(a)] flows
entirely through resistor Rb1, which is designed such that the IB I
Vr1 = Vbe,TP1 + VR = VT ln + B Rb1 (11)
voltage drop on it, IRb1, turns off transistor TP1 (p–n–p type). b1 IS,TP1 βTP1
Also, current I2 [generated by a current source as shown in
Fig. 15(a)] flows through transistor TP2 ( p–n–p type), which
with similar meanings applied to transistor TP1. The output
is biased in the linear region. Removing all transistors that
voltage becomes
are turned off, the schematic can be simplified as in Fig.
15(b). The voltage Vr2 shown on this figure can be expressed
Vout = Vr1 − VC | = Vr1 + Vr2 − Vin |sampled (12)
as hold sampled

I2 I2 It is worth mentioning that the output voltage holds a value

Vr2 = Vbe,TP2 + VR = VT ln + R
b2 IS,TP2 βTP2 b2
where Vbe,TP2 is the base-emitter voltage of transistor TP2, VT
is the thermal voltage, IS,TP2 is a constant current related to
transistor TP2, and 웁TP2 is the forward gain factor for transis-
tor TP2. In other words, voltage Vr2 is independent of the in-
put signal and is equal to the sum of the base-emitter voltage
of transistor TP2 and the voltage drop across resistor Rb2. The
voltage on the capacitor is VChold ⫽ Vin ⫺ Vr2, which is basically
a shifted version of the input. The output voltage Vout is reset
to Vr2 during this track or sample phase. When the clock sig-
nal goes high transistors TN1 and TN3 turn off and TN2
turns on. Current I1 is steered to flow entirely through resis-
(10)
of the input sampled when the clock goes high, and it is reset
to Vr2 when the clock goes back to the low state. This puts an
additional bandwidth requirement on the output buffer,
which needs to settle more than the full range of the input
signal. Also, assuming unity gain buffers, as stated initially,
the output is a shifted version of the input taken with oppo-
site sign. To achieve a perfect copy of the sampled input, a
differential topology should be employed (to eliminate the
shift) and either the input or output buffer should have a neg-
ative gain. Since there is no true track mode at the output,
one could consider the voltage on the capacitor as a function
of the input when clock is low, and derive the equivalent ‘‘on’’
switch resistance. However, this requires taking into account
 SAMPLE-AND-HOLD CIRCUITS 659

the design of the buffers and the parasitic effects of bipolar Vsupply
devices, which becomes rather involved.
The most common high-speed sample-and-hold circuits em-
ploy semiconductor diode bridges. The switching times for I3 I2 D5
semiconductor diodes are inversely proportional to the cutoff
frequency characteristic to a given bipolar or bipolar CMOS A
D1 D2
process. Also the ‘‘on’’ resistance for these devices is very low
compared to MOS-based switches. For a given current and Vin
Input Output
reasonable sizes, the transconductance of bipolar transistors Vout
buffer buffer
is significantly higher than that for their MOS counterparts.
D4 D3
Since semiconductor diodes can be considered as bipolar de- D6
B
vices with the base shorted to the collector, their ‘‘on’’ resis-
tance is Rswitch ⫽ 1/gm ⫽ VT /I, where VT is the thermal voltage
Chold
and I is the bias current flowing through the diode. The small Clock Clock
‘‘on’’ resistance and short switching times make the diode- T2 T1
bridge-based sample-and-hold circuits attractive for very-
high-speed applications. Figure 16 presents such a basic sam- Clock
I1 = I2 + I3
ple-and-hold circuit without input and output buffering. The
switch is implemented using a diode bridge and two switched
current sources. When the clock is low, the switched current Clock
sources do not generate any current and present a very high
impedance at their output such that the diodes turn off. This Figure 17. Diode-bridge-based sample-and-hold circuit with buff-
is the hold mode, when in the absence of parasitic effects such ering and clamping to the output voltage.
as diode leakage, feedthrough due to diode junction capaci-
tance, or droop due to the output buffer, the output voltage
preserves the sampled input voltage. When the clock goes parasitic effects mentioned earlier impact the performance of
high, current I starts flowing through the diodes and the out- the sample-and-hold circuit from Fig. 16 by introducing non-
put voltage is following the input after a short settling period. linearity and gain error. Fortunately, there are circuit tech-
Since the resistance through the diode is fairly low, the series niques that alleviate these effects and one of them is pre-
terminal contact resistance rb of the diode becomes significant sented later. The voltage at nodes A and B during the track
and should be taken into account. The equivalent ‘‘on’’ switch mode is input dependent. However, during hold mode these
resistance can be expressed as voltages change to some value independent of the input, and


 this change couples to the output node through the diode D2
1 1 1 1 and D3 junction capacitance, creating nonlinearity. This ef-
rb1 + + rb2 + rb4 + + rb3 +
gm1 gm2 gm4 gm3 fect can be virtually eliminated during the hold mode by
Rswitch =
1 1 1 1 clamping nodes A and B to a value dependent on the input
rb1 + + rb2 + + rb4 + + rb3 +
gm1 gm2 gm4 gm3 sample. This creates a constant voltage change at these nodes
1 VT from track to hold, and consequently, a constant perturbation
= rb + = rb + (13) of the held voltage, which results in offset but no nonlinearity.
gm I
Figure 17 presents a circuit that performs the described
clamping operation and includes input and output buffers
if rb1 ⫽ rb2 ⫽ rb3 ⫽ rb4 ⫽ rb and gm1 ⫽ gm2 ⫽ gm3 ⫽ gm4 ⫽ gm,
that are assumed to have unity gain. When the clock signal
which is equivalent to state that there are no mismatches
is high, transistor T2 is turned off and current I2 flows through
among diodes D1–D4. Mismatches among diodes as well as
the diode bridge, generating a low-resistance path between
the input and the holding capacitor Chold. This is the track
mode when the voltage on Chold and the output voltage are
Vsupply
following the input voltage. When the clock goes low, during
Clock the hold mode, transistor T1 turns off and transistor T2 turns
I
on, bypassing the diode bridge. Current I3 is necessary to
A clamp the voltage at node B to Vin兩sampled ⫹ Von,D6. Meanwhile,
D1 D2 Hold Hold Hold node A is clamped to Vin兩sampled ⫺ Von,D5. So the voltage at nodes
track track track
Vin A and B changes from track to hold by ⫺Von,D1 ⫺ Von/D5 and
Vout Clock Von,D3 ⫹ Von,D6, respectively. These Von voltages are dependent
on the diode sizes and bias current [Von ⫽ VT ln(Ib /IS)] so the
D4 D3 coupling from nodes A and B to the voltage on Chold through
B Chold the junction capacitance of diodes D2 and D3 is signal inde-
Clock Vin pendent. Also, during the track mode diodes D5 and D6 are
I
turned off since the output voltage follows the input and the
voltages at node A and B are Vin ⫹ Von,D1 and Vin ⫺ Von,D4, re-
Vout spectively. It is important to note that the range of the input
signal is limited to keep the diodes and current sources in
Figure 16. Basic sample-and-hold circuit using a diode bridge. their desired regions of operation.
660 SAMPLE-AND-HOLD CIRCUITS

There are various architectures (10–12) based on Fig. 17 φ2

that deal with alleviating undesired effects including those
mentioned earlier as well as input and output buffer linearity
and speed. Ultimately, the trade-offs made to improve the
performance of the sample-and-hold circuit need to be tailored
according to the overall application requirements. Bipolar-
transistor- or diode-based switches appear as a viable option;
however, there are a few key issues that can tip the balance
between a MOS and a bipolar implementation (2). The equiv-
alent ‘‘on’’ resistance is more linear and potentially smaller in
the bipolar case. Also, bipolar transistors require a smaller
clock voltage swing to be controlled as switches, which results
in a more accurate sampling instant. On the negative side,
they limit significantly the input range and generally create
an offset (eventually due to mismatches) between the input
and output voltages.
Closed-Loop Sample-and-Hold Circuits
Several of the problems that plague open-loop sample-and-
hold circuits can be avoided through the use of closed-loop
negative feedback in the design. Some of the circuits included
here still perform an open-loop sampling operation, but they
utilize negative feedback in the buffer stage that follows. One
of the simplest configurations that is often used in switched-
capacitor circuitry is the reset integrator, shown in Fig. 18
(13). During ␾1, the input is sampled onto C1 and the
switched-capacitor integrator is reset to zero by discharging
CF. On ␾2, the charge on C1 is integrated onto CF, yielding
Vout ⫽ ⫺(C1 /CF)Vin. Note that, as discussed in the subsection
concerning open-loop topologies, the switches at the virtual
ground side of the sampling capacitor open slightly before
those on the opposite side. The use of the switched-capacitor
integrator also avoids problems associated with the parasitic
capacitance at the right-hand side of the sampling capacitor
to ground, since this node always returns to the same virtual
ground potential during both sample and hold modes. Clearly,
the design of an operational amplifier with sufficient gain and
bandwidth is critical to the circuit’s performance. Droop dur-
ing the hold mode is typically low in this design and is signal
independent, caused by the leakage current through reverse-
biased source- or drain-to-bulk diodes associated with the
turned-off switches at the operational amplifier input. A dis-
advantage of this approach is that the output is not valid un-
til near the end of ␾2, so an extra clock phase is often needed
after ␾2 (shown by ␾3 in Fig. 18) for the circuitry that follows
this stage to utilize the output.
φ1
φ 1d C1
–
Vin OA Vout
+
Figure 19. A sample-and-hold circuit based on switched-capacitor
techniques and using a single capacitor both for sampling and in feed-
back around the operational amplifier.
A similar circuit that avoids the extra clock phase is shown
in Fig. 19. The input is sampled onto C1 relative to the virtual
ground of the operational amplifier on ␾1, and then is placed
in feedback around the amplifier during ␾2, yielding Vout ⫽
Vin. Thus, C1 serves as both sampling and feedback capacitor.
An advantage of this technique is that the dc offset and low-
frequency noise of the amplifier (such as 1/f noise) is removed
by this sampling scheme. The disadvantage is that the opera-
tional amplifier is required to sink the input current needed
to charge C1 initially, potentially increasing the operational
amplifier power dissipation, but it still does not offer any in-
put buffering to the driving source.
Another approach to a switched-capacitor sample-and-hold
circuit is shown in Fig. 20 in fully differential form and con-
sists of a simple first-order all-pass filter, with a z-domain
transfer function given by
Vout z−1C1 /C2
= (14)
Vin 1 − z−1 (1 − C1 /C2 )
which, when C3 ⫽ C2, reduces to Vout /Vin ⫽ z⫺1C1 /C2. Therefore,
the input can be simply sampled and scaled by C1 /C2, or a
single-pole discrete-time filter can also be included if so de-
sired. This circuit can easily be utilized with conventional
switched-capacitor design and has even been successfully
used for subsampling a 910 MHz input at a 78 ⫻ 106 samples/
s rate (14).
C3
φ2 φ 1d
φ1 φ 2d
C2
C1
φ 1d φ2

+
φ 2d φ1 –+ +
φ1 VIn OA VOut
+– –
φ 2d φ1
CF – C2
φ1
φ 1d φ 1d φ2
C1
C1 φ2
φ 1d φ2 –
φ 2d C3
Vin OA Vout φ2 φ 1d
φ 2d φ1 + φ3
φ1 φ 2d

Figure 18. A reset integrator sample-and-hold circuit, which uses

open-loop sampling and an operational amplifier in closed-loop feed- Figure 20. A first-order all-pass switched-capacitor filter used as a
back as an integrator. sample-and-hold circuit.
 SAMPLE-AND-HOLD CIRCUITS 661

The sample-and-hold circuit shown in Fig. 20 differs from R1 R2

those shown in Figs. 18 and 19 in that the circuit’s output is
not reset during a clock phase. The output transitions from
C2
its previous value to its new value during ␾2 and then re-
C1 φ1
mains constant on ␾1, thus giving circuitry that follows longer
time to process the signal. Another switched-capacitor sam- +
ple-and-hold circuit with this same property is shown in fully –+ +
differential form in Fig. 21 and utilizes both positive and neg- VIn φ2 OA VOut
ative feedback during ␾2. On ␾1, the input is sampled onto C1
+– –
C3, and the present output is sampled onto C1. At ␾2, the C3 – C2
capacitors are switched in parallel with the C2 feedback ca- φ1
pacitors, and the C1 capacitors are switched in positive feed-
back around the amplifier. Using C1 ⫽ C3 results in Vout /Vin ⫽ R1 R2
z⫺1, again without any reset phase necessary (15,16).
While the architectures discussed above all require at least
two or three clock phases to function properly, in high-speed Figure 22. A sample-and-hold circuit design using closed-loop feed-
back during both sampling and hold modes and needing only a single
applications it is desirable to use as few clocks as possible,
clock phase (␾2 is not necessary).
preferably just one. Figure 22 shows such a circuit that has
achieved 150 ⫻ 106 samples/s operation in a 0.7 애m bipolar
CMOS process (17). While ␾1 is high, the circuit operates as
tors. This is only a concern if the operational amplifier’s out-
a continuous-time amplifier with transfer given by
put resistance is too low, but the effect can still be reduced by
Vout R 1 + jωR1C1 adding an extra switch to short out the differential input volt-
=− 2 (15) age during the hold mode, as shown by the dashed line in Fig.
Vin R1 1 + jωR2C2
22. While this makes a two-phase clocking scheme necessary,
it may be required depending on the operational amplifier de-
which reduces to Vout /Vin ⫽ ⫺R2 /R1 when R1C1 ⫽ R2C2. When
sign and the hold-mode feed-through requirements.
␾1 falls, the input voltage is sampled and buffered to the out-
A similar design that also provides input buffering is
put. As in the switched-capacitor designs, the sampling
shown in Fig. 23 and replaces the resistors in the previous
switch operates at the operational amplifier virtual ground
design with a differential input transconductance amplifier
voltage at all times and thus (to first order) does not introduce
with gain G (18,19). During acquisition mode, the system has
signal-dependent charge injection at sampling. A danger with
a transfer function of
this design is that the input may still feed through to the
output even during hold mode via the capacitors and resis- Vout 1
= (16)
Vin 1 + jωC/G

φ1
C3
φ 1d that results in Vout 앒 Vin for frequencies well below 웆0 ⫽
G/C. The sampling switch isolates the integrator from the
+ transconductance amplifier during the hold mode, so the inte-
φ2 φ 2d VIn
C1 grator holds its state until the switch is turned on again. As
in the circuit of Fig. 22, the sampling switch always operates
at an approximately constant virtual ground voltage (assum-
C2
φ2 ing the operational amplifier has sufficient gain and band-
width for the application), so its charge injection and clock
φ1 feed-through will be signal independent to first order. The
closed-loop negative feedback reduces system nonlinearity
–+ + caused by that of the open-loop transconductance amplifier
OA VOut and operational amplifier. An extra switch at the transcon-
+– –
C
φ2 2
C
φ1
+ I0 φ1
C1
G –
Vin –
OA Vout
φ2 +
φ2 φ 2d
C3 VIn
–
φ1 φ 1d Figure 23. A closed-loop sample-and-hold circuit with both input
and output buffering, using a differential input transconductance am-
Figure 21. Another switched-capacitor circuit used as a sample-and- plifier and a switched-capacitor integrator. The switch shown with
hold circuit, now using both positive and negative feedback around the dashed line is recommended to prevent the transconductance am-
the operational amplifier. plifier output from saturating while ␾1 is off.
662 SAMPLE-AND-HOLD CIRCUITS

ductance amplifier output to ground is also recommended, in Vsupply

order to prevent that node from saturating high or low while
the sample-and-hold circuit is in hold mode. Without this φ1 φ2 Sample Sample Sample
switch, the transconductance amplifier may experience a I
longer recovery time when the circuit returns to acquisition Iin Iout
φ1
mode, thus lowering the circuit’s maximum sampling rate.
SW1 SW3
In general, sample-and-hold circuit designs that utilize
closed-loop feedback during sampling, such as that shown in φ1
SW2
φ2
Fig. 23, are not widely used. Input buffering can be achieved
at very high linearity albeit moderate speed using a high-gain M1
operational amplifier in unity-gain configuration, and open-
Chold
loop sampling at the input of a switched-capacitor integrator
can achieve linearity in excess of 100 dB when designed care- Iin
fully. The use of an operational amplifier in closed-loop feed-
back in an integrator configuration is very common, with a
variety of switching configurations possible, and is widely Iout
used to also provide output buffering. Closed-loop designs like
that shown in Fig. 22 are often used not for the increased
Figure 24. Current-mode sample-and-hold circuit (current copier).
linearity of a feedback configuration but instead for the need
Capacitor Chold is charged during ␾1 and holds its charge during ␾2
of a phase with only a single clock, an advantage in high- generating the output current Iout through transistor M1.
speed design. Interestingly, a closed loop sample-and-hold to-
pology as described in Ref. 20 can be even used to perform a
single-ended to differential voltage conversion.
the voltage on the holding capacitor Chold is

Current-Mode Sample-and-Hold Circuits 

2(I + Iin )
Current-mode sample-and-hold circuits provide an alterna- VC = VGS,M1 = VT + (17)
hold µnCoxW/L
tive to voltage-mode implementations described so far. Con-
versions between current and voltage usually influence the
where VTh and W/L are the threshold voltage and the size
performance of the overall circuit, and selecting between the
ratio of transistor M1, respectively, 애n is the electrical mobil-
two types of sampling provides an additional degree of free-
ity corresponding to n-channel devices, and Cox is the oxide
dom during design. Currents could be stored using inductors
capacitance. When ␾1 goes low, the input current value at
similar to voltages being stored on capacitors. However, mo-
that instant is sampled as a voltage on Chold, according to Eq.
nolithic implementation of inductors is not practical in today’s
(17). When ␾2 goes high, switches SW1 and SW2 are opened
technologies and even discrete components do not offer a via-
and switch SW3 is closed. This is the hold phase, when the
ble solution due to their nonzero series resistance, which
output current can be expressed as
leads to loss. Also, switching inductors without generating
significant transients appears as extremely challenging.
Iout = 12 µnCox (VGS,M1 − VT )2 − I = Iin |sampled (18)
The easiest and most common method for storing currents
is to convert the current to a voltage or charge and store that
on a holding capacitor. During the hold mode, the current can since VGS,M1 ⫽ VChold as it was stored when ␾1 went low. It can
be restored through an inverse voltage-to-current conversion. be seen that the output current is a perfect copy of the sam-
Since the same transconductance element can be used for the pled input current in the absence of nonidealities. However,
current-to-voltage and the voltage-to-current conversions, the charge injection from switches and finite output impedance of
overall performance is not affected in a first-order approxima- transistor M1 can seriously affect the performance. Also, it is
tion. This subsection will discuss some basic topologies for important that ␾1 and ␾2 do not overlap since the sample
current-mode sample-and-hold circuits as well as their non- stored on Chold is corrupted if switches SW2 and SW3 are
idealities. closed at the same time. Figure 25 shows a simple circuit that
Most current-mode circuits including sample-and-hold cir- generates a two-phase nonoverlapping clock. The nonoverlap
cuits are implemented using MOS technology. Very small duration is given approximately by three logic gate delays.
gate currents (compared to significant base current in the bi-
polar case) combined with the existence of gate capacitance
that could be used as a holding capacitor, easy switch, and φ2
logic function implementation are a few reasons behind this
Clock Clock
selection. For monolithic implementations, MOS technology is
also less expensive. Figure 24 presents a basic current-mode
sample-and-hold circuit called the alternatively current
copier. Two phases of a clock control the circuit functionality. φ1
When ␾1 is high, switches SW1 and SW2 are closed and the
input current Iin flows into transistor M1 together with the φ2
bias current I. During this period switch SW3 is opened and φ1
there is no current generated at the output Iout ⫽ 0. Since
transistor M1 is configured as a MOS diode during this phase, Figure 25. Circuit for generating nonoverlapping phases of a clock.

There are circuit techniques and topology variations that
can be employed to attenuate the effect of nonidealities or to
improve the speed. When the switch SW1 in Fig. 24 is turned
off, a part of the charge stored in its channel is dumped into
the holding capacitor. This charge is signal dependent and
results in nonlinearity at the output. One method to alleviate
this effect was described in the subsection concerning open-
loop sample-and-hold circuits and relies on dummy-switch
cancellation (21). If the clock edges are steep enough and
switches are implemented using MOS transistors, half of the
charge from switch SW1 appears on Chold when this switch is
turned off. Consequently, a dummy switch with half the
width of switch SW1 can be turned on at the same time,
which would attract the parasitic charge from Chold generated
by switch SW1. Figure 26 shows the dummy-switch cancella-
tion technique. The size ratio of transistor Mdummy is half that
of M1 since the parasitic channel charge of a MOS device is
proportional to this ratio, as described in Eq. (4). Also,
switches SW1 and SW3 were replaced with NMOS transistors
M3 and M4 such that for the shown level of clock phases ␾1
and ␾2 they preserve the switch functionality from Fig. 24.
For low and medium resolution (less than 8 bits) the dummy-
switch cancellation provides a reliable solution and allows
fast operation due to the small number of components, hence
parasitics, involved. However, mismatches between the
dummy and main switches, nonideal clock edges, and ulti-
mately process-dependent channel charge present a serious
challenge for higher-resolution designs. Employing differen-
tial topologies can alleviate the effect of the mismatches. Also,
since the current error due to charge injection is inversely
proportional to the holding capacitor, making Chold larger im-
proves accuracy at the expense of speed. This could be circum-
vented using Miller-type closed-loop structures that increase
the effective capacitance value with a negligible penalty in
speed performance (2).
Another way of reducing the effect of signal dependent par-
asitic charge injection is to perform a multiple-step cancella-
tion. Figure 27 shows a two-step cancellation technique that
uses multiple phases of a clock and was first described in Ref.
22. Phase ␾1 is split into ␾11 and ␾12, which contribute to the
Vsupply
φ1 φ2
Sample Sample Sample
I mained as Iref ⫹ Iin ⫹ Ierr, the output current during the hold
Iin Iout
φ1
M3 M4
φ1
M2
φ2
φ2 Mdummy
M1
Chold Iin
Iout
Figure 26. Charge-injection error cancellation using a dummy
switch. The circuit is similar to the one described in Fig. 24, except
switches were replaced by transistors M2, M3, M4, and a dummy
(Mdummy) was added.
SAMPLE-AND-HOLD CIRCUITS 663
Sample Sample Sample
Vsupply
φ1
φ 11
Cp
Vref
M2 φ 11
SW5
φ 12 SW4
φ1 φ2 φ 12
Iin Iout
SW1 SW3 φ2
φ1
SW2
M1
Chold Iin
Iout
Figure 27. Two-step charge-injection error cancellation using multi-
ple clock phases.
cancellation process. When ␾11 is high, ␾1 is also high and the
circuit behaves similarly to that in Fig. 24. Also, during this
phase Vref is connected to the gate of the PMOS transistor M2,
which acts as a current source with the value Iref . When ␾11
goes low, the voltage on the holding capacitor Chold corre-
sponds to a current of Iref ⫹ Iin ⫹ Ierr through transistor M1,
where Ierr is due to the charge injection from SW2. Ierr exhibits
a strong input signal dependency and if left uncanceled it
would introduce nonlinearity in the output current. Phase
␾12 goes high immediately following ␾11. During this, transis-
tor M2 becomes diode connected and generates a current of
Iref ⫹ Ierr. The corresponding voltage is stored on capacitor Cp
(see Fig. 27). When ␾12 goes low, ␾1 also goes low and transis-
tors M1 and M2 remain with their gates connected only to
Chold and Cp, respectively. This is the hold phase: ␾2 is high
and the output current is generated as a difference between
the current through M1 and the current through M2. The cur-
rent through M2 is Iref ⫹ Ierr ⫹ Ioff , where Ioff is due to the
charge injection on Cp from switch SW4 being turned off and
the end of ␾12. Since the current through transistor M1 re-
phase becomes Iin ⫹ Ioff . The channel charge from switch SW4,
which produces Ioff , contains very little input signal depen-
dency because the voltage across switch SW4 during ␾12 is
almost constant with respect to the input signal. This is valid
only if the frequency of the clock that generates ␾1, ␾11, ␾12,
and ␾2 is low enough compared to the signal bandwidth and
the input current Iin varies very little during ␾12. As a result
the output current is an accurate copy of the input plus an
offset component.
A major performance degradation in current-mode sample-
and-hold circuits is due to the finite input resistance of MOS
transistors. This introduces nonlinearity since the current
stored and generated by a MOS device acquires a component
that is a function of the drain-to-source voltage. This voltage
is more often signal dependent unless some precautions are
employed. Cascode structures and differential topologies can
be used to reduce this nonideality. Also, Ref. 23 shows the
664 SAMPLE-AND-HOLD CIRCUITS

φ 1, φ 2 φ 2, φ 3 able during ␾2 and the input is sampled at the end of ␾1. Any
φ1
error in the current copier can be mapped as E(z) and added
φ5
into the signal path as shown in Fig. 28. The transfer func-
Iin Iout φ2 tions from the input Iin(z) and E(z) to the output Iout(z) can be
Current
+
+ copier expressed as
–
φ4 Iout (z) Iout (z)
H(z) = = z−1 , H = = 1 − z−1 (19)
Iin (z) E(z)
φ4
It can be seen that the input transfer function H(z) is just a
φ5 delay as in the case of any sample-and-hold circuit. On the
other side, the error transfer function H⑀ has a zero at dc
(a) (when z ⫽ 1) similar to the noise-shaping performed by a
first-order ⌬–⌺ data converter. As a result, H⑀ is a high-pass
characteristic and the amount of error at the output is propor-
Intregrator Current E(z)
copier
tional to the ratio of the input frequency f input to the frequency
+ of the clock f clock. The errors associated with the integrator are
Iin(z) Iout(z)
z–1/2 also attenuated by the aforementioned oversampling ratio
+ –1 z–1/2 +
+
–
1–z + (OSR ⫽ f clock /2f input) as discussed in Ref. 24. By increasing the
number of integrators and feedback loops, the analogy to ⌬–⌺
modulation can be continued and the accuracy of the output
(b) current increases accordingly. The speed can be also improved
using parallel architectures based on the same circuit from
Fig. 28(a) clocked on alternate phases.
Vsupply Vsupply Vsupply Figure 28(c) shows a MOS transistor implementation of
the diagram from Fig. 28(a). The difference between the input
φ1 φ2 φ3 φ5
I I I current Iin and the feedback current Ifeed is applied to the inte-
Iin Iout grator during ␾1. The functionality of the current-mode inte-
grator can be easily explained assuming a constant input cur-
Ifeed rent Ict. Assuming that initially the same current I/2 flows
φ1 φ2
through both transistors M1 and M2, when ␾1 goes high tran-
φ4
M1 M2 M3 M4 sistor M1 will conduct I/2 ⫹ Ict. When ␾1 goes low and ␾2 goes
high transistor M2 will conduct I/2 ⫺ Ict. When ␾1 goes high
C1 C2 C3
again, M1 will conduct I/2 ⫹ 2Ict and correspondingly when
␾2 goes high transistor M2 will conduct I/2 ⫺ 2Ict. Clearly, the
left-hand branch containing transistor M1 will conduct more
and more current, while the right-hand branch including
(c)
transistor M2 will conduct less and less. Transistor M3 mir-
Figure 28. Current-mode sample-and-hold circuit using negative rors out the current resulting from the integration process.
feedback and oversampling. (a) Conceptual diagram; (b) z-domain Then, transistor M4 is used to create a current copier as in
block diagram; (c) transistor level implementation. Fig. 24, which generates alternatively the output and the
feedback currents.
Another circuit that uses feedback to provide an accurate
usage of negative feedback to increase the output resistance sample of the input current is shown in Fig. 29 (25). This is
of a MOS device. similar to Fig. 23 except that instead of a voltage at the input
Negative feedback and oversampling of the input signal of the transconductance, a current at its output is sampled.
can be used to reduce the effect of all types of errors described
so far and implement a highly accurate current-mode sample-
and-hold circuit at the expense of more hardware. Figure
28(a) presents a conceptual diagram for such a circuit (24). Chold
The difference between the input and output currents is fed
+
into a current-mode integrator clocked by ␾1 and ␾2. Its out- gm1 –
Clock
put is copied to the overall circuit output if ␾5 is high or fed – T3 SW1 OA + Iout
back to create the aforementioned difference during ␾4. + gm2
Clearly, the output is an accurate copy of the sampled input Iin – Iin
since the integrator and the closed loop would force their dif-
ference to zero. Before describing the functionality in more
detail, it is useful to observe the circuit from a z-domain per- Iout
spective as in Fig. 28(b). The integrator and the current copier
are assumed to be ideal and their z-domain transfer functions Figure 29. Closed-loop current-mode sample-and-hold circuit. This
are z⫺1/2 /(1 ⫺ z⫺1) and z⫺1/2, respectively. The term z⫺1/2 in the circuit resembles the one in Fig. 23, except that a current is stored
integrator transfer function signifies that its output is avail- as opposed to a voltage.

When the clock is high the input current is stored as a voltage
on Chold. Since the negative input to the operational amplifier
OA is preserved as a virtual ground, the feedback loop con-
taining gm1, switch SW1, and the operational amplifier OA
forces the voltage on the holding capacitor to VChold ⫽ Iin /gm1
where gm1 is the transconductance value. During the hold pe-
riod when the clock signal is low, the output is maintained at
gm2
Iout = I | (20)
gm1 in sampled
It is worth mentioning that gm2 and gm1 are physically differ-
ent elements and their mismatches as well as nonlinearity
impact the performance of this sample-and-hold circuit. Also,
the speed of the circuit depends largely on the operational
amplifier settling time.
Real-life implementations of the current-mode sample-and-
hold circuits described so far include usually more elaborate
structures that are targeted at cancelling parasitic effects.
Some of them employ differential topologies or improvements
related to the finite output impedance of MOS transistors.
Other structures employ more sophisticated clocking schemes
or feedback to cancel charge-injection errors. Furthermore,
closed-loop architectures must deal with stability issues that
come into play as a trade-off regarding the accuracy (in the
case of discrete-time feedback as in Fig. 28) or the speed (for
the continuous-time feedback as in Fig. 29) of the circuit. Al-
though there are advantages in using current-mode sample-
and-hold circuits particularly regarding operating speed,
their widespread usage was hampered by the need of voltage-
to-current and current-to-voltage conversions as well as im-
plementation difficulties when higher accuracy is required.
CONCLUSIONS
Sample-and-hold circuits are widely used in a broad variety
of circuits and systems, from sensor-conditioning applications
to communications designs to data-conversion systems. In
many cases the whole system design starts with specifying
the sample-and-hold operation, and its implementation can
even dictate a specific overall architecture. While the concept
of a sample-and-hold circuit seems quite simple in its ideal-
ized form, the previous sections have shown how complex and
detailed the designs and requirements can become. The vari-
ous performance metrics that have been established for evalu-
ating sample-and-hold operation are useful in setting specifi-
cations for a design to be used in particular applications.
These specifications then allow the designer to survey the
many techniques and architectures that exist for sample-and-
hold circuits and focus on the one that best meets these re-
quirements and is most efficient for implementation. The
broad variety of design topologies available is evidence itself
of their differing advantages and disadvantages, all of which
must be considered when determining the suitability of a de-
sign for the given application.
The designs discussed here were chosen as a representa-
tive subset of the many sample-and-hold architectures that
exist, and myriad variations and modifications on these can
be found. The techniques used in the designs depend heavily
on the integrated-circuit technology, with series switches and
switched-capacitor-based designs most prevalent in MOS
technologies, while current steering and diode bridges are
SAMPLE-AND-HOLD CIRCUITS 665
common in bipolar designs. Current-based designs, as dis-
cussed earlier, are attractive for applications involving cur-
rent-output sensors and current-mode signal processing, and
have given rise to several innovative design concepts. Higher-
speed and finer-line integrated-circuit processes will continue
to push existing design techniques to higher and higher per-
formance levels, and innovative conceptual and architectural
breakthroughs will provide an extra boost to exceed the per-
formance barriers that rise as time goes on.
BIBLIOGRAPHY
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3. A. Sanchez, Understanding sample-hold modules, in Analog De-
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lando, FL: Saunders HBJ, 1987.
5. T. L. Brooks et al., A 16b ⌺⌬ pipeline ADC with 2.5 MHz output
data-rate, ISSCC Dig. Tech. Papers, San Francisco, 1997, pp.
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6. G. Wegmann, E. A. Vittoz, and F. Rahali, Charge injection in
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9. B. Razavi, Design of a 100-MHz 10-mW 3-V sample-and-hold am-
plifier in digital bipolar technology, IEEE J. Solid-State Circuits,
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666 SATELLITE ANTENNAS

19. K. R. Stafford, A complete monolithic sample/hold amplifier,

IEEE J. Solid-State Circuits, SC-9 (6): 381–387, 1974.
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IURI MEHR
Analog Devices, Inc.
TERRY SCULLEY
ESS Technology, Inc.
NADI ITANI
Cirrus Logic, Inc.

SAMPLED-DATA CONTROL. See DIGITAL CONTROL.

SAMPLED-DATA SYSTEMS. See SWITCHED CAPACITOR
NETWORKS.
SAMPLING WATTMETERS. See WATTMETERS.
192 SEQUENTIAL CIRCUITS
SEQUENTIAL CIRCUITS
DEFINITION AND STRUCTURE
Logic circuits are classified into combinational and sequential
circuits. The classification has no ambiguity, because there
are two qualitatively different digital circuit elements in their
idealized model: logic gates, which respond instantaneously to
the inputs, and memories, which retain the past input data. A
combinational circuit is made of logic gates only. A sequential
circuit is made of combinational circuits and memories, and
some inputs to the combinational circuits are driven by the
outside signal and the rest by the memory outputs. The com-
binational circuits drive the memories and store the logic op-
eration results in them. The signal paths of a sequential cir-
cuit make a closed loop, as schematically shown in Fig. 1. As
the digital signals circulate the loops, the processing is car-
ried out in sequence. That is why the circuit is called sequen-
tial. Since some of the input signal to the combinational cir-
cuit comes from the memories that hold the data previously
processed by the circuit, it is able to produce a logic answer
not only from the present input data, but also using the past
input data. If intelligence is defined as the capability of using
experience for present decision making, a sequential circuit
Inputs Outputs
Combinational
circuit
Memory
Figure 1. Structure of a sequential logic circuit.
J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.
VDD CK
S
Q
Q D Q
R
CK
(a) (b)
Figure 2. (a) Set-reset latch, (b) half (master) of D latch.
has elementary intelligence. The experience of a sequential
circuit is the processed data of the past inputs. This is the
most fundamental significance of a sequential circuit. A com-
binatorial circuit driven by uniformly delayed input signals is
not a sequential circuit, even if it has memories. Since the
combinatorial circuit is known (1,2), we consider the memo-
ries first. The sequential circuit memories have subtle details
that characterize the circuit. In recent years, most of the logic
circuits have been built as integrated circuits, and for a large-
scale integration, CMOS is the preferred technology. The cir-
cuit examples are mostly CMOS circuits.
MEMORIES
Memory devices used in a sequential logic circuit are of two
different types. One type has positive feedback controlled by
signals from the outside, and its memory retention time can
be controlled by the control signals or by a clock. The clock is
a systemwide memory control signal by which the processing
proceeds in regular steps, and the memory is able to retain
the data for any length of time. This type of memory is called
a latch or a flip-flop. The other type of memory is either a
cascaded chain of gates or some other continuous physical
structure that is able to delay the input signal to the output.
The output signal of the delay circuit at time t is the input
signal at time t ⫺ ␶, where ␶ is the delay time.
The memory devices of the first type have popular names.
The conventionally used devices are as follows: (1) set-reset
latch, (2) D latch, (3) T flip-flop, and (4) J-K flip-flop. The T
flip-flop changes the state every time the input makes a tran-
sition. The J-K flip-flop has several combinations of these fea-
tures. All of the memory devices come in clocked and un-
clocked versions. The D- and the set-reset latches are
preferentially used in integrated circuits, and the other types
are referred to in McCluskey (3), Nagle (1), and Mano (2). In
CMOS VLSI circuits, two types of latches—the set-reset latch
and the D-latch—are most frequently used. Although there
are several variations of latch circuits, a typical circuit used
for ultra-high-speed CMOS circuits is shown in Figs. 2(a) and
2(b). In Fig. 2(a), if S is HIGH and R is LOW, the set-reset
latch stays in the state it was previously forced into. Subject
to this condition, if S is temporarily pulled down to LOW
while R is kept LOW, the latch is set, or Q output becomes
LOW if it has not been in the set state. Subject to the same
condition, if R is temporarily pulled up to HIGH while S is
kept HIGH, the latch is reset, or Q output becomes HIGH. If
S is LOW and R is HIGH simultaneously, the latch’s subse-
quent state is unpredictable. In a VLSI circuit such a conflict
can be prevented by adding an extra logic circuit. J-K flip-
flop, originally intended to avoid the control input conflict, is
used infrequently. The circuit of Fig. 2(b) is the half of the D

latch. In a sequential logic circuit the second stage, in which
the control clock CK and CK are exchanged, is directly cas-
caded to it, and the pair is called a master-slave D-latch pair.
The circuit of Fig. 2(a) or 2(b) has a strong output driver
(shown by the large inverter sign) that drives the output, and
a weak driver (shown by the small inverter sign) that holds
the input of the strong driver. The set/reset FET of Fig. 2(a)
and the transmission gate of Fig. 2(b) must be able to over-
power the output node held by the small inverter. This type
circuit is faster than the conventional latch circuit using the
tristable inverters.
The delay device used instead of the controllable memory
device is generally called a delay line. In spite of the name,
the traditional LC or the acoustic-delay lines are not used
anymore. Rather, the natural delays of the cascaded logic
gates, especially of simple inverters, are used. In this type of
delay-memory circuit, certain requirements exist for the cir-
cuit’s operational integrity. Figure 3, curve A, shows the input
waveform to a delay line. If the delay line outputs a slowly
rising (or falling) waveform like curve B, the delay line as a
memory device is not acceptable. This is because the delay
time of signal B referenced to signal A depends on where the
logic threshold voltage, the boundary between the Boolean
HIGH and LOW levels, is set. Depending on the logic gate
driven by the delay line output, as well as the gate’s operating
condition (e.g., the timing of the other input signal), the delay
time varies over a wide range. Since the delay line does not
have a definite delay time, the circuit’s operational integrity
is compromised. A signal like curve C has a clearly defined
delay time, and the delay line is acceptable as a memory. To
create a waveform like C, the delay line circuit must have a
crisply switching buffer at least at the output stage, or LC
delay line structure. A passive RC low-pass filter is not ac-
ceptable, because the output waveform looks like curve B. A
confusing issue in sequential circuit classification is that if a
chain of logic gates makes a closed loop, the loop works as a
memory device as well as a combinational logic circuit. It is
impossible to separate the loop circuit into combinational and
memory parts. From this viewpoint, any logic circuit that has
a closed loop of gates is a sequential circuit, and this is its
widest definition based on the circuit structure. The sche-
matic of Fig. 1 cannot be used to characterize this type of
circuit directly without further interpretation, which will be
provided later.
CLASSIFICATION OF SEQUENTIAL CIRCUITS
In a sequential circuit, the combinational logic part has no
feature to distinguish one circuit from the other. To classify a
sequential circuit, we observe the structure of the loops. The
key features by which to classify sequential circuits are (1) if
a loop is a single loop or a multiple loop, and (2) how the loops
are controlled. The most convenient means of classification
is to single out the most convenient and most widely used
Voltage
A B C uniform design discipline is followed. Furthermore, the data
Time
Delay time
Figure 3. Delay line memory waveform requirement.
SEQUENTIAL CIRCUITS 193
synchronous sequential circuit by focusing attention on the
function of the clock, and then to discuss the other, asynchro-
nous sequential circuits, in regard to their special features.
The memory device used for a conventional synchronous
sequential circuit is a pair of D latches (Fig. 2) connected in
the master-slave configuration. The rectangular box repre-
sents the latch. The symbols in the box, D is the input, C is
the clock, and Q and Q are the normal and the inverted out-
puts [see Fig. 2(b)]. The latch pair replaces the memory block
of Fig. 1. The combinational logic circuit is driven by outputs
from the slave latches and by external signals. The external
signals must be synchronized to the clock, to fit into the ap-
propriate timing window. The master latch receives the signal
processed by the combinational circuit. In the simplest imple-
mentation, all the master and all the slave latches are driven
by a clock and its complementary, respectively. When the
master latches are transparent (input open), the slave latches
are their inputs closed, and vice versa. The clock transition
must be fast to ensure that either the master latch is trans-
parent and the slave latch is closed, or the master latch is
closed and the slave latch is transparent. This is called an
edge-triggered timing scheme.
At the beginning of a process cycle, the clock transition
effects disconnection between the logic circuit and the master
latches. The source data to the combinational logic circuit are
secured first by the positive feedback retention mechanism of
the master latches, to the designated Boolean levels. The
Boolean levels are transferred to the slave latches that are
transparent and to the combinational circuit; while that is
going on, the combinational logic circuit has already started
processing the data. Then the second clock transition effects
disconnection between the master and the slave latches, and
the slave latches apply positive feedback to retain the ac-
quired data. The master latches are now open and are ready
to accept the processed data as they arrive at the master
latch’s input terminals. During the data acquisition process
by the master latch, the latch circuit’s delay exercises intelli-
gence to filter out the noise and the spurious pulses. At the
end of the logic operation period set by the clock, the master
latch is disconnected from the combinational logic circuit, and
its output is connected to the slave latch. The master latches
exercise intelligence to decide the Boolean level of the output
of the combinational circuit by eliminating the spurious noise,
and then by quantizing to generate the Boolean level. The
processed data, or the answer of the cycle’s logic operation, is
now available to the slave latch. The synchronous sequential
circuit is now ready to start a new clock cycle with new in-
put data.
Synchronous sequential logic circuits have a number of ad-
vantages. Their step-by-step operation timed by the system-
wide clock is easy to understand, design, and simulate, since
the electrical phenomena in different cycles can be studied
independently. This is perhaps the most important reason for
their preferred use. Asynchronous sequential circuits are dif-
ficult to understand, design, and verify. Some of the problems
of asynchronous sequential circuits, such as the race condi-
tion, do not exist in synchronous circuits, and in a synchro-
nous system metastability failure does not occur if simple and
processing load can be optimally distributed over the clock
cycles to attain the maximum throughput. Based on these ad-
vantages, synchronous sequential circuits are the predomi-
194 SEQUENTIAL CIRCUITS

nant choice in implementing high-performance systems. The

clock required to drive the system is simple. This scheme has
a variation: The combinational logic circuits are inserted be-
tween the master and the slave latches, as well as between
the slave and the master latches. This variation has more
flexibility than the simplest scheme and is more tolerant to
the rise/fall time requirement of the clock, but it requires a
four-phase clock.
A sequential circuit that does not have the features of the
previously defined synchronous sequential circuit belongs to
a loosely defined group of asynchronous sequential circuits.
Existence of the system-wide clock is crucial, but the choice
of memory is also an issue: Specifically, a circuit using set-
reset latches instead of D latches, or a circuit using the delay
element as a memory device belong to asynchronous circuits.
Practically, a large-scale synchronous sequential circuit may
have an asynchronous sequential circuit as part of it, and
clear distinction between them is impossible. Asynchronous
sequential circuits are convenient for implementing simple
function directly interfacing to the human hand.
REPRESENTATION OF SEQUENTIAL CIRCUIT OPERATION
Sequential circuits carry out the most complex signal pro-
cessing operations in electronics. It is necessary to have a
simple and intuitive way to represent their operation in
graphical or tabular form. The circuit shown in Fig. 4 has two
inputs, one output, and two D latches. The D latches are in
the master-slave configuration, or the two cascaded stages of
the simple latch circuit shown in Fig. 2(b) and driven by the
complementary pair of clocks. The two latch outputs (y1, y2)
can be any of the four combinations, (0,0) through (1,1). The
input variables x and w, and the two outputs of the latches
y1 and y2, determine the present state of the circuit at the
clock phase in which the master and the slave latches are
disconnected. The set of variables x, w, y1, and y2 (not the
complemented form y2) define the total state of the sequen-
tial circuit.
The next states Y1 and Y2, and the output z of the circuit
of Fig. 4, are written by Boolean algebra as follows:
Y1 = y2 + x Y2 = y1 + w z = wy1 + xy2
The output of latches 1 and 2 determines the present internal
state of the circuit. The Boolean levels are written in a vector
format (y1, y2), as (0,0) or (0,1), to designate the internal state.
As the HIGH to LOW clock transition occurs, the connection
to the master latches is closed, and the state of the master
latches is transferred to the slave latches to become the next
state of the circuit. The sequence of transitions caused by the
clock transition and by the input signal describes the opera-
01/1
11/1
00 01
10/1
11/1 00/0 00/0 10/0 11/0
01/1
00/0
10 11
11/1
10/1
10/1 01/0
00/0 00/0
Figure 5. State transition diagram.
tion of the circuit. One convenient way to describe the circuit
operation is to use the state transition diagram shown in Fig.
5. In this figure the four internal states of the circuit are
shown within the circles. The arrowed curves connecting the
circles are the state transitions caused by the clock and the
input signals. The indications associated with the curves, **/
*, show the input signal Boolean levels in the order of (w-x)
in front of the slash, followed by the Boolean level of the out-
put z.
The state diagram of Fig. 5 is the Mealy-type state dia-
gram (2), by which the input signals and the present internal
state determine the output signals and the next internal
state. In the Mealy diagram the clock of the memories affects
the state transition and the output change, but, in addition,
an asynchronous input change may affect the output. To
make a completely synchronous representation of the system,
the input signals must be assumed to have been delivered
from the outside memories, which are driven by the same
clock. There is a second, Moore-type, state diagram, in which
only the present state and the inputs creating a transition to
the next state are shown. The present outputs are determined
by combinational circuits from the present internal state. In
the Moore diagram the outputs are synchronized to the mem-
ory clock.
A second way of describing the circuit operation is to use
the state transition table shown in Table 1. In this table, the
columns are the four possible combinations of the input sig-
nals w and x, and the rows are the four possible present inter-
nal states of the circuit [as defined before, the vectorical com-
bination of the latch outputs (y1, y2)]. The entries of the table
are the next state of the circuit upon the clock transition fol-
lowed by the output(s). Both the state diagram and the state
table describe the circuit operation independent of the input
signal sequence, and this compactness is the convenient fea-
ture of the two representations.

Latch 1 Latch 2 Table 1. State Transition Table

y2 Present State Input w and x

x D Q D Q z y1 y2 00 01 11 10
Y1 Y2
C Q C Q 00 11/0 01/1 01/1 11/0
01 11/0 11/0 11/0 11/0
w
11 11/0 11/0 10/1 10/1
y1 CK
10 11/0 01/1 00/1 10/1
* Next state Y1 , Y2 /output
Figure 4. An example of a synchronous sequential circuit.

The state transition diagram and the state transition table
give the peculiarities of the circuits. The circuit has two inter-
nal states, (00) and (01), which are transitory; if the clock
edge arrives, the state changes to other state. The states (10)
and (11) are not transitory; if in the state (10) and if the input
is (10), the circuit returns to the same state after a clocktick.
The state (11) has two possible inputs, (01) and (00), that
bring the circuit back to the same state after a clocktick. If
(01) and (00) input alternate and if the circuit is originally in
the internal state (11), the circuit is stuck at state (11) for-
ever. The circuit has no stable state. The circuit has instabil-
ity: If the input is (11), the circuit goes through a sequence
(00) 씮 (01) 씮 (11) 씮 (10) and back to (00). The circuit works
as a ringoscillator. As observed from this example, the input
sequence independent representation provides many insights
into sequential circuit operation.
MODEL OF ASYNCHRONOUS SEQUENTIAL CIRCUITS
Definition of asynchronous sequential circuits is not a simple
matter, because the memory device, a latch, is not an atom-
like building block of a logic circuit: Either it is a uniform
delay line, or it consists of atomlike gates, and a memory can
be built by connecting any number of logic gates in a closed
loop. Such a generalized data storage device has a built-in
data processing capability as well, and the inputs to the loop
cannot be named by descriptive names, such as set, reset, and
clock. This complication makes design, analysis, and repre-
sentation of the operation of an asynchronous sequential cir-
cuit complex and its subclassification arbitrary. A simple
memory device like a set-reset latch is used in asynchronous
sequential circuits. Asynchronous sequential circuits that use
unclocked set-reset latches, shown in Fig. 2(a), are often used
to implement a simple state machine that accepts inputs di-
rectly from a human operator. The debounce circuit, which
reshapes the pulse from toggling a mechanical switch, is per-
haps the most popular use of a set-reset latch.
To design a sequential logic circuit that has specified func-
tionality is the problem of synthesis. Circuit synthesis re-
quires analysis methods, a few general methods to convert
the functionality specifications to the best form for implemen-
tation, and a lot of insight and experience in system-level op-
eration. We discuss the first two, the analysis methods and
design specifications that are common to synchronous and
asynchronous circuits, while using an asynchronous circuit as
an example.
The circuit shown in Fig. 6 is an asynchronous sequential
circuit having two loops made by conventional logic gates. The
objective of the following analysis methods is to find out the
peculiarities of operation of the circuit: If the peculiarities are
found, we may say that we understand the circuit. The first
x1 Y1
y1
M1
y2
x2
M2 Y2
Figure 6. An example of an asynchronous sequential circuit.
SEQUENTIAL CIRCUITS 195
Table 2. State Transition Table
* Inputs x1 and x2
y1 y2 00 01 11 10
00 01 00 00 01
01 11 11 11 11
11 11 11 00 01
10 01 00 00 01
* Y1 and Y2
analysis step is to separate the logic operation and the delay
of the gates. The logic gates in the figure are idealized logic
gates that execute the logic operation instantly. The delay
times of all the gates of the two loops are lumped into the
fictitious delay elements M1 and M2 shown in the figure,
which work as delay line memories. A digital signal propa-
gates from the right to the left through the fictitious delay
elements, and the input and the output have different node
variable names. The outputs of the delay elements have node
Boolean variables y1 and y2, and inputs Y1 and Y2, respec-
tively. The input signals x1 and x2 and y1 and y2 define the
total states of the asynchronous sequential circuit.
In a synchronous sequential circuit the one clock for all the
memories has the function of pushing the state of the circuit
forward. In an asynchronous sequential circuit any input sig-
nal may control the state of the memories, which are most
often complex loops of gates. Then for the following analysis,
as well as in the real operation of the circuit, only one input
variable is allowed to change at a time. When the input vari-
able changes, the circuit must have arrived at the steady
state already, determined by the previous input signal
change. An asynchronous sequential circuit operates subject
to this stronger condition than a synchronous sequential cir-
cuit, and therefore the processing power and the operational
flexibility are less than for a synchronous circuit.
Using the total state (x1, x2, y1, y2), the next state variables
Y1 and Y2 are determined by the Boolean logic equations
Y1 = x1 y2 + y1 y2 Y2 = x1 y2 + y1 y2 + x2
and the state transition table is made, as shown in Table 2.
In this example, Y1 is the output.
The transition table shows various peculiarities of the cir-
cuit. If the input signal (x1, x2) is either (0,0) or (0,1) and if
the initial internal state (y1, y2) is (1,1), the next internal
state (Y1, Y2) is (1,1), or the internal state never changes. The
circuit is in a steady state if x1 ⫽ 0. Similarly, if the input
signal is either (0,1) or (1,1) (or if x2 ⫽ 1) and if the initial
internal state is (0,0), the state never changes. In the two
conditions the circuit is in a steady state that does not change
with time. If the input signal is held at (0,0) and if the initial
internal state is (0,0), the next internal state is (0,1), followed
by (1,1), and the circuit arrives at the steady states for x1 ⫽ 0
and x2 ⫽ 0. If the internal state immediately after the input
signal change is not one of the steady state, the circuit takes
several steps to one of the steady states. This is not the only
mode of operation of the circuit. If the input signal is held at
(1,0) and if the initial internal state is (0,1), the next internal
state is (1,1), and the next to the next internal state is (0,1),
the same internal state as the initial internal state. The cir-
cuit oscillates between the two internal states. In this case
196 SEQUENTIAL CIRCUITS

the circuit is equivalent to a three-stage cascaded enabled in-
verting gate, which works as a ringoscillator.
The state transition diagram or state transition table pro-
vides many details of asynchronous sequential circuit opera-
tion, other than those discussed before. For the purpose of
circuit synthesis, it is convenient to represent the internal
state not by a preassigned Boolean vector form like (0,0), but
by a symbolic character A, B, . . .. Here we use identification
like A: (0,0), B: (0,1), C: (1,1), and D: (1,0) in the state transi-
tion table, as in Fig. 7. This figure is to show various struc-
tures of a state transition table, and it is not related to the
last example. Figure 7(a) shows that the next state of B for
any value of input x is B. This means that state B is a state
if, once entered, the circuit stays in forever. The state can be
entered from another state, or it can be initially set. If the
other entries *’s of Fig. 7(a) have no B state, the B state is an
isolated internal state, and if the state transition table has
an isolated internal state, the state diagram is separated to
two independent parts. Figure 7(b) shows that as long as x is
1 the next state of B is C, and the next state of C is B. The
states B and C alternate, and the circuit oscillates. This is an
unstable circuit that is not practically usable as a logic circuit.
In Fig. 7(c) the oscillation goes over the entire state as x
makes a transition from 0 to 1 and stays at the value: The
state sequence is A, D, B, C, and back to A.
The entries of the state transition table can be any of the
four internal states, A, B, C, or D, in any order and in any
number of duplications, although many of such randomly gen-
erated tables do not carry out useful functions. This great
variability creates many other strange, often practically unde-
sirable behaviors. In Fig. 7(d) we note the internal state A ⫽
(0,0), B ⫽ (0,1), C ⫽ (1,1), and D ⫽ (1,0). If the initial state is
A, the two memory outputs that determine the internal state
of the circuit both flip if x changes from 0 to 1. If the timing
sequence is included in consideration, the change may take
place in three different ways: (1) a simultaneous change, A 씮
C, (2) A 씮 B 씮 C, and (3) A 씮 D 씮 C. In the state transition
table of Fig. 7(d), all the three changes end up with the same
final state C. The circuit executes the logic operation cor-
rectly. If the state transition diagram is as shown in Fig. 7(e),
however, the final state depends on the timing sequence: (1)
A simultaneous change, A 씮 C, ends up with state C; (2) if
A 씮 B occurs first, the circuit settles at state B; (3) if A 씮 D
occurs first, the circuit settles at state D. Since the order of
occurrence of the state change is not indicated in the logic
diagram, the final state cannot be determined from the logic
diagram alone. The problems discussed in relation to Figs.
7(d) and 7(e) are called the race condition, since the final des-
tination depends on the order of the state change (5). Figure
7(d) is called a noncritical race, since the final state does not
depend on the order. Noncritical race is usually harmless for
logic circuit operation. Figure 7(e) is called a critical race,
since the final state is determined by the order. A critical race
condition can be avoided if there is a state sequence that
leads to the correct final state, if the state change sequence
occurs in an arbitrary order. In Fig. 7(f), if the state sequence
occurs simultaneously, the circuit ends up with state C. The
critical race condition is avoided by the intermediate state B,
which has the right destination state C. If A 씮 B occurs first,
the sequence B 씮 C follows, and the circuit ends up with a
correct state. If A 씮 D occurs first, however, the circuit ends
up with state D, which is not the state the designer intends.
From these observations, the critical race condition can be
avoided in several ways: by providing an intermediate inter-
nal state like B, through which the circuit ends up with the
correct final state, or by assigning proper binary state vectors
to the symbolic internal states A, B, C, and D such that only
one latch changes the state upon input transition. A number
of possibilities of circuit operation exist, and the state table is
a simple method by which to analyze complex cases.
OPERATION ON THE SET OF INTERNAL STATES
State is the central concept of sequential circuits. Operations
on a set of states, such as simplification, choice of a better set
of states for hardware minimization or for high reliability, or
assigning binary vectors to a symbolic state, as we saw before
are an important issue, both for circuit analysis and synthe-
sis. If a sequential circuit is considered as a black box accessi-
ble only from the input and output terminals, the set of inter-
nal states within the black box creating the functionality may
have many alternatives. If a circuit design already exists, the
choice of internal states may not be the simplest or most de-

x x x
0 1 0 1 0 1
y1 y2 y1 y2 y1 y2
A * * A * * A * D
B B B B B C B B C
C * * C * B C * A
D * * D * * D * B

(a) (b) (c)

x x x
0 1 0 1 0 1
y1 y2 y1 y2 y1 y2
A A C A * C A * C
B B C B * B B * B
C * C C * C C * C
D * C D * D D * D
Figure 7. State transition diagram and asynchronous se-
quential circuit operation. (d) (e) (f)

Table 3. Original State Transition Table
Initial State Input x
* x⫽0
A F/0
B D/0
C F/1
D E/1
E E/0
F E/0
G A/1
* Final state/the output
sirable. The first of such issues is simplification of the circuit
by reduction of the number of internal states of a sequential
circuit while maintaining the same input-output functional-
ity. This is the first step to sequential circuit synthesis.
Suppose that the state transition table, Table 3, is given.
State reduction can be carried out by several methods: (1) by
inspection, (2) by partition, and (3) by using an implication
table (1,2). By inspection, for input x ⫽ 0 and x ⫽ 1, states E
and F go to the same state, E and C, respectively, and the
outputs for the two cases are also the same at 0. Then the
two states E and F are equivalent. Further reduction of the
number of states, however, is not obvious by an inspection. As
for the systematic methods useful in such cases, the partition
method is referred to in the references, and a versatile and
simple implication table method is briefly summarized here.
To display the equivalent/nonequivalent relationship of a
pair of internal states, we make a diagram by stacking the
boxes, as shown in Fig. 8. If two internal states are equiva-
lent, the sequential circuit must generate the same output(s)
for all the combinations of the input variable values. Any pair
of internal states having at least one different output for a
combination of inputs are not equivalent. The box at the col-
umn index B and the row index D, for instance, contains an
indicator ⫻ since the two internal states are not equivalent
by this criterion. Most of the boxes get ⫻ marks, and the in-
ternal state pairs are removed from further consideration.
This table is called an implication table because of the inter-
nal states A through G, there can be internal states that are
equivalent but are named by different symbolic indicators.
B
C (z1, z2, . . .), and the next internal states (Y1, Y2, . . .) from
D set up. The required combinational circuits are then synthe-
E (E,F)
F (E,F) E=F
G (A,F)
A B C D E F
Figure 8. Implication table to find equivalent states.
SEQUENTIAL CIRCUITS 197
Table 4. Simplified State Transition Table
Initial State Input x
x⫽1 * x⫽0 x⫽1
C/0 A A/0 C/0
F/1 B D/0 A/1
B/1 C A/1 B/1
A/0 D A/1 A/0
C/0 * Final state/the output
C/0
B/1
Some of them are equivalent if the following situation occurs:
If internal states A and E are to be equivalent, the internal
states E and F must be equivalent for x ⫽ 0. As for x ⫽ 1, the
equivalence condition is already satisfied by the same inter-
nal state C. The equivalency requirement of internal states A
and F (namely, E ⫽ F) is written in the box at column A and
row E, by a sign (E,F). Since internal E and F being equiva-
lent implies internal states A and E being equivalent, the ta-
ble is called an implication table. If the same procedure is
repeated for the other empty boxes, that internal states A and
E and internal states C and G are equivalent is implied by E
and F and A and F being equivalent, respectively. The equiva-
lence of states E and F is already established by inspection
and is indicated by E ⫽ F.
Since states E and F are equivalent, the completed impli-
cation table shows that states A and E are equivalent, and
states A and F are also equivalent. Then internal states C
and G are also equivalent. The original seven states are
grouped into equivalent states (A,E,F), B, (C,G), and D. The
seven-state table is simplified to the four-state table shown in
Table 4. Obviously, the circuit having four states is easier to
implement than the circuit having seven states, yet the two
implementations are functionally equivalent. Since m memo-
ries create a maximum of 2m internal states, the number of
the memories is reduced from 3 to 2 by the reduction process.
Synthesis of a sequential circuit having the specified func-
tionality begins with conversion of the requirement in the
common language into a state transition table or diagram. In
this phase of the work the states carry symbolic names, such
as A, B, C. The state transition table is then examined by the
procedure described in this section if the equivalent states
can be found, and if the total number of states can be reduced,
to make the circuit simpler. In the next step the binary num-
bers are assigned to each state A, B, C, . . ., such that the
circuit is race free. Then, using the simplified and the state-
assigned transition table, the logic function tables for the
combinational logic circuit, which creates the required output
the inputs (x1, x2, . . .) and the present state (y1, y2, . . .) are
sized using the standard technique (1,2) and they are inte-
grated with the memory circuit. This process completes the
synthesis procedure.
A NEW LOOK AT SEQUENTIAL LOGIC CIRCUITS
Synchronous sequential circuits have the merits of easily un-
derstood operation, simple and systematic design procedure,
efficient use of combinational hardware, ability to carry out
varieties of operation by adding small amounts of logic gates
198 SERVOMECHANISMS
and control signals (as in the processor datapath), and easy
interfacing to the external circuits that have the same sys-
temwide clock signal. These merits of synchronous sequential
circuits are especially advantageous to the large-scale inte-
grated circuit environment, and they have been the driving
force of the rapid growth of microprocessor technology. Al-
though these advantages will be exploited actively in the fu-
ture, there are other advantages of synchronous sequential
circuits that are clearly visible (e.g., ultra-high-speed elec-
tronics from the electronic circuit theorist’s viewpoint).
The basic structure of the synchronous sequential circuit
shown in Fig. 1 using the edge-triggered master-slave D-latch
pair allows us, conceptually, to cut the circuit loop open be-
tween the master and slave latches. Then the slave latch pro-
vides the digital information to the combinational circuit, and
the master latch receives the information processed by it. A
digital signal is an object, very similar to an elementary parti-
cle in quantum mechanics, and the slave latch-combinational
logic-master latch combination is equivalent to a measure-
ment setup to determine the velocity of the pseudoparticle
that carries the digital information. We note here that the
quantum mechanical nature of the digital circuit originates
from the impossibility of setting a clear threshold voltage that
distinguishes the Boolean HIGH and LOW levels. Since the
threshold voltage is uncertain, or hidden from the digital cir-
cuit theory, the digital circuit becomes a quantum mechanical
object, very similar to what has been envisioned by Einstein,
Podorsky, Rosen (4), and Shoji (6).
From this viewpoint a new idea of increasing the speed
of digital signal processing to the limit emerges. By properly
choosing the circuit between the latches, the quantum me-
chanical information-carrying particle can be transferred by
the equivalent to the quantum mechanical tunnel effect,
which takes, in its purely physical model, a short time. This
new viewpoint suggests that the combinational circuit be-
tween the two latches need not be constructed from logic
gates, but can and should be constructed from varieties of cir-
cuits including analog circuits. It is my belief that the advan-
tage of a synchronous sequential circuit originates from its
basic structure, the pair of information source and observa-
tion setup. The structure, once considered as the basic quan-
tum mechanical arrangement, should be able to provide the
fastest circuit we can build, yet it satisfies the basic require-
ment of digital circuits—the step function signal format—
generated by clocked latches. From this viewpoint a sequen-
tial circuit will be a rich source of research in future electronic
circuit theory.
The quantum mechanical nature of a digital signal shows
up most clearly when, against the circuit designer’s intention,
a narrow isolated pulse is generated, or a simple step function
waveform is converted into a multiple transition, a wavy step
function wavefront during the combinational logic operation.
The narrow isolated pulse is called a static hazard, and the
multiple transition step function a dynamic hazard (3). A haz-
ard is an essential mode of operation of a combinational logic
circuit built from gates having nonzero delay, and this is clear
from the following example. Suppose that a synchronous se-
quential circuit includes a NAND gate, whose two inputs A
and B were the HIGH and the LOW logic levels, respectively.
The output is at the default HIGH level. After the slave
clocktick, the step function signal fronts arrive sometime
later at A and B to make a HIGH to LOW transition at input
A and a LOW to HIGH transition at input B. After the transi-
tions are over, the output of the NAND gate is at the same
HIGH logic level as before. The problem is that the timing
relation of the wavefront is not always subjected to the con-
trol of the designer. If the LOW to HIGH transition of the B
input occurs earlier than the opposite polarity A input transi-
tion, both inputs of the NAND gate become temporarily
HIGH, and the output of the gate is a temporarily LOW logic
level. A downgoing isolated pulse whose width is the time be-
tween the input B transition to the input A transition is gen-
erated. Hazard is an unexpected and unwelcome guest to a
circuit designer, and it is significant in state-of-art high-speed
CMOS logic circuits. One way to describe a high-frequenty
logic circuit operation is as a continuous sequence of genera-
tion and erasure of hazard pulses. The hazard pulse is usually
narrow, and it may or may not be wiped out as the signal
further propagates the gate chain. Some hazard features sur-
vive and arrive at the destination latch. The latch is the final
measure to screen all the extra features of the step function
front, by cleaning up the deformed pulse from the combina-
tional circuit at the clocktick. This function is an elementary
intelligent function of a digital circuit, and thus the synchro-
nous logic circuit does have the minimum required and funda-
mentally necessary features of intelligent signal processing.
That is why the circuit is so widely used. In an asynchronous
sequential circuit, this function is distributed over the circuit,
and this confuses the issue.
BIBLIOGRAPHY
1. H. T. Nagle, Jr., B. D. Carroll, and J. D. Irwin, An Introduction to
Computer Logic, Englewood Cliffs, NJ: Prentice-Hall, 1975.
2. M. M. Mano, Digital Design, 2nd ed., Englewood Cliffs, NJ: Pren-
tice-Hall, 1991.
3. E. J. McCluskey, Logic Design Principles, Englewood Cliffs, NJ:
Prentice-Hall, 1986.
4. D. Bohm, Quantum Theory, Englewood Cliffs, NJ: Prentice-Hall,
1951.
5. M. Shoji, Theory of CMOS Digital Circuits and Circuit Failures,
Princeton: Princeton Univ. Press, 1992.
6. M. Shoji, Dynamics of Digital Excitation, Norwell, MA: Kluwer,
1998.
MASAKAZU SHOJI
Bell Laboratories
SEQUENTIAL CIRCUITS AND FINITE STATE AU-
TOMATA, TESTING. See LOGIC TESTING.
SERVICES, HOME COMPUTING. See HOME COMPUT-
ING SERVICES.
400 SMOOTHING CIRCUITS

of constancy do not exist, although expensive laboratory

power supplies strive to approximate them.
When any electronic circuit is incorporated into end-use
equipment, the available dc supply has imperfections that can
interfere with the proper operation of the circuit. A realistic
model of a practical dc voltage supply is shown in Fig. 1. It
comprises an ideal dc voltage source Vdc, an alternating cur-
rent (ac) voltage source vr(t) that represents superimposed
ripple, and a generalized series impedance Zs, which repre-
sents the supply’s internal impedance and that of wires, PCB
traces, and connections. In the ideal case, vr(t) and Zs are both
zero, but they take on nonzero values for a real supply. In a
typical power supply, the dc source Vdc ultimately derives
from a wall plug or similar electric utility line source with its
own variations.

What is Smoothing?
It is possible to design an electronic circuit to withstand some
variation at the dc supply. However, high-performance cir-
cuits such as audio amplifiers or precision sensors require a
supply of the highest possible quality, and almost any design
can benefit from a clean supply. The concept of a smoothing
circuit is to add extra elements to Fig. 1 to provide an equiva-
lent dc output that approaches the ideal. A smoothing circuit
provides an interface between the nonideal supply and the
intended electronic load. In power supply practice, it is usual
to distinguish between a smoothing circuit, which has the
primary function of eliminating effects of the ripple voltage
vr(t) and the source impedance Zs, and a regulation circuit,
which has the primary function of enforcing a constant Vdc.
However, many smoothing methods incorporate regulation
functions.
Smoothing can take the form of a passive circuit, con-
structed mainly from energy storage elements, or an active
circuit that corrects or cancels supply variation. Both of these
major topics are discussed in this article. We begin with defi-
nitions, then consider fundamental issues of smoothing. Fol-
lowing this, we present passive smoothing methods in depth.
Active smoothing methods are described after passive
methods.
It is important to point out that an ideal dc voltage supply
is not the only possibility for circuit power. In a few cases, an
ideal dc current supply or a specific ideal ac supply is needed
instead. The reference materials provide additional informa-
tion about smoothing of current sources and ac supplies.

Ls Rs
SMOOTHING CIRCUITS +

Most electronic circuits are designed to operate from a perfect vr(t) Zs

Smoothing
constant-voltage direct-current (dc) supply. This is often circuit Load

shown on a schematic diagram as VCC, VDD, or ⫹12 V, for in- Vdc

stance. Ideally, the supply voltage would remain constant –

despite all disturbances: It would never show any spikes,
Imperfect dc supply
ripples, or variations of any sort. It would not change in the
face of variations at its input, and it would not be altered no Figure 1. Model of an imperfect dc supply, smoothing circuit and
matter how high the load current. In practice, such paragons load.

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

Definitions
The following definitions are in common use.
The ripple factor r provides a measure of the ripple voltage
vr relative to Vdc. It is usually defined in terms of peak-to-peak
variation:
Peak-to-peak supply voltage excursion
r=
Average voltage
If vr is sinusoidal, with vr(t) ⫽ Vpk cos(웆r t), then the ripple
factor is r ⫽ 2Vpk /Vdc. An oscilloscope can be used in ac-cou-
pled mode to measure the numerator of Eq. (1), and a dc volt-
meter can measure the denominator. The ripple factor should
be as small as possible.
A smoothing circuit should provide a lower value of r at its
output than at its input. This is the basis for an important
figure of merit.
Ripple attenuation is the ratio of the smoothing circuit’s
input ripple voltage to its output ripple voltage. It is often
expressed in decibels:
Ripple attenuation

Peak-to-peak voltage excursion at input
 comes VO ⫽ ⫺gm (R ⫹ Zs)Vi ⫹ Vr. Since Zs most likely depends
= 20 log10
Peak-to-peak voltage excursion at output
The ripple attenuation should be as large as possible.
When a smoothing circuit is not present, the output imped-
ance of a power supply is the source impedance Zs. Therefore,
output impedance provides a second helpful figure of merit.
The objective is to provide as low an impedance as possible
over a wide frequency range.
The end-use application has certain important measures
as well. The sensitivity of the load to supply variation is mea-
sured in terms of power supply rejection.
The power supply rejection ratio (PSRR) is a measure of the
ultimate effect of supply variation at the point of end use.
Given a final output voltage magnitude VO and power supply
ripple voltage magnitude Vr, the rejection ratio is given by
Power supply rejection ratio = −20 log10 (VO /Vr )
Here VO is that portion of the output voltage that is related
to supply ripple (excluding signals, random noise, and other
disturbances). The PSRR value should be as high as possible.
The frequency of the ripple waveform is important for
smoothing circuit design.
The ripple frequency is defined as the fundamental fre-
quency of the ripple waveform, whether or not the waveform
is sinusoidal. In many cases, the ripple frequency is a multi-
ple of the ac line frequency that provides the energy. In
switching power supplies, the ripple frequency is usually
much higher.
Example: Amplifier Load
Figure 2 shows an inverting amplifier supplied from a noni-
deal source, and will serve to illustrate the need for smooth-
ing. In the case of a perfect voltage source with vr(t) ⫽ Zs ⫽
0, the amplifier’s intended output voltage is VO ⫽ ⫺gmRVi,
where gm is the transistor’s transconductance. However, the
supply ripple voltage feeds directly through R to the output,
and it modifies the output voltage to VO ⫽ ⫺gmRVi ⫹ Vr. The
SMOOTHING CIRCUITS 401
Ls Rs
A
Vr Zs R
V0
g mV i C
(1) Vdc Vi
B
Imperfect dc supply Amplifier To other
circuitry
Figure 2. Imperfect dc supply feeding a simple amplifier and other
circuitry.
circuit in Fig. 2 is poor in this respect. Its PSRR is unity, or
0 dB, and therefore it relies entirely on smoothing within the
power supply for its function. Well-designed amplifiers, such
as IC operational amplifiers, can have PSRR levels of 60 dB
or greater.
Furthermore, the imperfect dc supply has impedance Zs,
which appears in series with R, so the output voltage be-
(2) on frequency, the amplifier’s frequency response (the varia-
tion of VO /Vi with frequency) is no longer flat. In addition, an
alternating-current (ac) voltage develops across Zs, equal to
gmZsVi. If another circuit is powered from points A and B in
Fig. 2, considered as dc supply rails, this extra ac voltage ap-
pears as superimposed ripple. Thus the supply impedance Zs
provides a mechanism by which signals in one circuit can cou-
ple into another. Under certain conditions, the cross-coupling
can be strong enough to produce large-amplitude, self-sus-
taining oscillations.
A remedy for the impedance and cross-coupling effects is
to connect a large capacitor between A and B. This is known
as decoupling the circuits from each other. A ‘‘large capacitor’’
means one with impedance 兩ZC兩 ⫽ 1/(웆C) that is much smaller
than the impedances R and Zs at all frequencies of interest.
The idea is that the signal current in R should flow mostly
through C rather than Ls. It will then develop a small voltage
(3) of approximately gmVi /(웆C) between points A and B. When
Rs is small, a ripple current of approximately Vr /(웆Ls) will
flow through Ls and C; this current will produce a ripple volt-
age Vr /(웆2LsC) between A and B. The larger the value of C,
the smaller the unwanted voltage gmVi /(웆C), and the better A
and B approach ideal voltage rails. Higher values of Ls will
also help reduce the ripple voltage between A and B once a
capacitor is present. Rather than being an unwanted element,
the source inductance becomes useful. In fact, extra induc-
tance might be added in series to increase the smoothing
effect.
This example shows the basis of a general passive smooth-
ing circuit: Ls and C form a second-order low-pass filter be-
tween the ripple voltage source and the amplifier circuit. The
filter passes dc unaffected. Well above the cutoff frequency of
the filter at approximately the resonant frequency, 웆0 ⫽
1/ 兹LC, ripple is attenuated by about 40 dB/decade.
SMOOTHING FROM AN ENERGY PERSPECTIVE
Before discussing practical smoothing techniques, we look at
power and energy relations, which define fundamental physi-
cal limitations associated with smoothing.
402 SMOOTHING CIRCUITS

Power and Energy This average power balance equation leads to the definition
of efficiency, ␩ ⫽ PO /PI —that is, the ratio of average output
Let work or energy be denoted as a function w(t). Instan-
power to average input power, usually expressed as a percent-
taneous power is the rate of change of energy, p(t) ⫽ dw/dt.
age. An important design aim of a smoothing circuit should
The first law of thermodynamics states that energy is con-
be to attain a high efficiency—that is, approaching 100%.
served: ⌺w ⫽ constant, and after differentiating we obtain
If we take the full-power balance equation and subtract
⌺(dw/dt) ⫽ 0. Therefore, the energy supplied to a system
the average-power balance equation, we arrive at the ripple-
must match the energy output, plus any energy that is stored
power balance equation:
internally. In terms of power, we can identify a power balance
equation: dw̃
p̃I = p̃O + + p̃H (9)

d

dt
pin (t) = wstored + pout (t) (4)
dt The aim of smoothing is to make p̃O close to zero. We can try
to accommodate the input ripple power either by a change in
That is, the total power flowing into any system equals the
stored energy, by dissipation, or by a combination of these.
total power flowing out, plus the rate of change of internally
stored energy.
Nondissipative Smoothing
In a typical electronic system, there are unwanted losses
that constitute an output heat flow, and it is convenient to Internal energy storage is used in smoothing circuits such as
consider this heat output separately. Figure 3 shows a LC filters, which in theory can be 100% efficient. There are
smoothing circuit that has instantaneous input power pI(t), only two basic ways of storing energy in a circuit: electrically
electrical output power pO(t), internal energy storage w(t), and and magnetically. A capacitor provides electric storage based
heat output power (losses) pH(t). The power balance equation on its stored charge, q ⫽ CV. The derivative of this for con-
for this circuit is stant capacitance provides the familiar property i ⫽
C(dv/dt). At any point in time, the power into the device is
dw v(t)i(t), and the capacitive stored energy is
pI (t) = pO (t) + + pH (t) (5)
dt   
t t v
dv(t) 1 2
So, in general, the power entering a smoothing circuit at any wC (t) = v(t)i(t) dt = v(t)C dt = Cv dv = Cv (t)
0 0 dt 0 2
instant undergoes a three-way split: Some power leaves via (10)
the electrical output, some increases the internal stored en-
ergy, and the remainder is dissipated as heat. This power bal- The other way of storing energy is in a magnetic field. An
ance equation identifies two techniques available for realizing inductor provides magnetic flux linkage ␭ in its core propor-
smoothing circuits: energy storage and dissipation. Both will tional to the current i flowing in a coil around the core, with
be considered shortly. ␭ ⫽ Li. The time derivative of this for constant inductance,
Let pI(t) ⫽ PI ⫹ p̃I(t), where PI is a constant (dc) term and combined with Faraday’s law by which d␭ /dt is equivalent to
p̃I(t) is the ripple component (ac term), and similarly for the voltage, gives the conventional property v ⫽ L(di/dt). The
other variables. The power balance equation becomes same procedure as for the capacitor yields the inductive
stored energy:
d(W + w̃)
(PI + p̃1 ) = (PO + p̃O ) + + (PH + p̃H ) (6)
dt 1 2
wL (t) = Li (t) (11)
2
Since W is constant, an immediate simplification is that the
dW/dt term is zero. Furthermore, we are interested in the Capacitance and inductance are electric duals: An expres-
long-term average power flows: sion concerning capacitance can be transformed into an ex-
 pression about inductance by swapping the roles of v and i
T
1 and then replacing C by L and q by ␭. For a capacitor we can
P = lim p(t) dt (7)
T →∞ T 0 write dv/dt ⫽ i/C, so the larger the value of C, the smaller
the rate of change of voltage—that is, the more constant the
By definition, the ripple components have zero average, so the voltage remains. For an inductor we can write the dual ex-
long-term result is pression di/dt ⫽ v/L. From an energy storage perspective, we
deduce that capacitors act to maintain constant voltage; in-
PI = PO + PH (8) ductors act to maintain constant current.
With finite capacitance and inductance, true constancy
cannot be achieved. The basis of nondissipative smoothing cir-
cuits is to alternate capacitors and inductors, progressively
pH smoothing voltage and current in turn.
i0 Figure 4(a) shows an input power with sinusoidal varia-
+ + tion. Nondissipative smoothing circuits attempt to store rip-
vI pI Internal stored p0 v0 ple energy during the high parts of the cycle, and then they
energy w
– – dispense this energy during low parts of the cycle to smooth
the overall flow. The available power becomes PI, the dashed
Figure 3. Power flows and energy in a smoothing circuit. line in Fig. 4(a).

pI(t)
PI
Power
∆ PH
t can achieve zero ripple, in principle.
;;;;;
(a)
Power here must
be dissipated
Power
Maximum possible Minimum possible
value of P0 value of PH
t

(b)
Figure 4. Hypothetical ripple power waveform. In (a), average
power PI is available with nondissipative smoothing. In (b), dissipa-
tive smoothing delivers a lower value.
Dissipative Smoothing
Dissipation is used in circuits such as linear voltage regula-
tors and linear active smoothing filters. These devices are in-
herently less than 100% efficient. Their basic operation is to
enforce constant output power by treating ripple as excess
energy.
Recall the ripple-power balance equation,
dw̃
p̃I = p̃O + + p̃H
dt
If there is no stored energy, the term dw̃/dt is zero. The objec-
tive of p̃O ⫽ 0 can be achieved only if we make p̃H ⫽ p̃I —that
is, if we convert all the input ripple power into heat power
(loss). The lost energy is actually higher than this, and we
should consider the implications for efficiency. Consider again
an input power with ripple as in Fig. 4(a). Suppose p̃I(t) has
a maximum downward excursion ⌬PH; this means that the
total heat power pH(t) has a minimum value of PI ⫺ ⌬PH. By
the second law of thermodynamics, this value must be posi-
tive: Heat power always flows out of the circuit (excluding
heat engines). This forces us to set a positive value of PH to
account for correct heat flow. The implications can be seen in
Fig. 4(b). Here the value of PO is set as high as possible—to
the minimum of the input power excursion—and all power in
the shaded region must be thrown away as heat to meet the
zero p̃O objective. Since PH is positive in a dissipative smooth-
ing circuit, the efficiency is less than 100%.
In a case with sinusoidal ripple power, such that pI(t) ⫽
PI ⫹ pi cos(웆t), the highest output power with p̃O ⫽ 0 will be
PO = PI − pi
SMOOTHING CIRCUITS 403
The highest possible efficiency PO /PI gives
pi
η ≤1− (14)
PI
Recall that nondissipative smoothing circuits cannot achieve
zero ripple with finite component values. Although dissipative
smoothing circuits can never achieve 100% efficiency, they
Waveform Considerations and Frequency-Domain Analysis
The implications of ripple factor, regulation, and many mea-
sures of smoothing performance depend on the nature of the
ripple waveform. Ripple waveforms in conventional power
supplies can be sinusoidal or triangular, or they can take the
form of narrow spikes. We can consider ripple as a periodic
signal with a particular spectrum and then apply frequency-
domain analysis. Formally, we represent a ripple signal vr(t)
by its Fourier series,
∞
vr (t) = a0 + an cos(nωt) + bn sin(nωt) (15)
n=1
where the radian frequency 웆 is related to the frequency f
and the time period T of the signal as 웆 ⫽ 2앟f ⫽ 2앟/T. The
time function a1 cos(웆t) ⫹ b1 sin(웆t) is defined as the funda-
mental of ripple, while terms at higher values of n are har-
monics. Because most smoothing filters have a low-pass na-
ture, they attenuate the harmonics more than the
fundamental. For design purposes, it is often sufficient to con-
sider the gain at the fundamental ripple frequency, 웆 ⫽ 웆r.
Consider input and output voltage phasors taken at this fre-
quency. We will express the gain in decibels:
 
 V ( jωr ) 
Gain (dB) = 20 log10  O  (16)
(12) VI ( jωr ) 
For arbitrary complex frequency s, the transfer function can
be written as
VO (s)
A(s) = (17)
VI (s)
PASSIVE SMOOTHING FILTERS
Let us now approach the design of passive filters for smooth-
ing. In principle, smoothing filters might be designed like the
low-pass filters employed for signal processing (1,2). But un-
like signal filters, where existing source and load impedances
can be augmented with resistance to the desired value,
smoothing filters must avoid resistance wherever possible in
the interest of efficiency. Therefore they generally have ill-
defined source and load impedances, and standard low-pass
filter tabulations are inapplicable except in special circum-
(13) stances.
404 SMOOTHING CIRCUITS

consider the situation with an input voltage source and a cur-

rent-source load. When fed from a voltage source vI and deliv-
ering an output current IO, the filter output voltage is vI ⫺
VI(t) IOR, and its efficiency is
Smoothing Load
circuit IO R
η=1− (18)
VI

The value of R should be chosen to give an acceptable effi-

ciency. The voltage gain transfer function is
Figure 5. Diode bridge with output smoothing filter and load.

1
A(s) = (19)
To illustrate the point, consider a smoothing filter fed from 1 + sCR
a diode-bridge rectifier, as shown in Fig. 5. The rectifier’s ef-
fective output impedance is not clear, and in fact it can vary The gain at the ripple radian frequency 웆r is
considerably, even within a cycle. Even the basic circuit ac-
tion is unclear, since the timing of diode turn-on and turn-off
p
Gain (dB) = −20 log10 1 + (ωrCR)2
will depend on the smoothing circuit and the load. Conven-
≈ −20 log10 (ωrCR) if ωrCR  1 (20)
tional circuit theory is difficult to apply in such circum-
stances.
In almost any practical smoothing application, the dy- The one-section filter has a corner frequency at 웆0 ⫽ 1/(RC),
namic characteristics of the load are unknown or poorly de- and the gain falls asymptotically (i.e., for 웆 ⬎⬎ 웆0) at 20 dB/
fined. Given a dc load specified as drawing current I at volt- decade, or 6 dB/octave. Thus, with R selected on efficiency
age V, one might assume a resistive load, with R ⫽ V/I. In grounds, the value of C is chosen to give the desired attenua-
reality, this may not be the case: At one extreme, the load tion of the fundamental ripple frequency.
could approximate a constant current of I (a linear voltage Two or more RC networks can be cascaded to form a multi-
regulator tends to behave this way); at the other it might ap- section filter, as in Fig. 6(b). A two-section filter, with each
proach a constant voltage of V (a battery to be charged is one section comprising R/2 and C/2, provides
common case). In between, the load could be resistive, capaci-
tive, or inductive, with the possibility of nonlinear behavior 1
A(s) = (21)
or time variation. If information about the source and load 1+ + 16 (sRC)
3 1 2
4 sRC
impedances is available to the filter designer, it should be uti-
lized. Otherwise, assumptions must be made, with an attempt
toward worst-case analysis. The gain is


RC Smoothing Gain (dB) = −20 log10 1+ 16 (ωr RC)
7 2
+ 256 (ωr RC)
1 4

The simplest type of passive smoothing filter is the single-
section RC low-pass filter of Fig. 6(a). This is widely used for
decoupling purposes at low power levels, where its limited ef-
ficiency is not a concern. For this filter, worst-case design can
≈ 24 − 40 log10 (ωr RC) if ωr RC  1 (22)
The corner radian frequency is 웆0 ⫽ 4/(RC), and the gain falls
asymptotically at 40 dB/decade or 12 dB/octave. A three-sec-
tion filter, with R/3 and C/3 in each section, has

R I0 1
A(s) = (23)
1 + 23 sRC + 81 (sRC)
5 2
+ 729 (sRC)
1 3

VI C V0
and gain of

(a)
Gain (dB)


= −20 log10 1+ 26
81
(ωr RC)2 + 13
6561
(ωr RC)4 + 1
531,441
(ωr RC)6
R/2 R/2 I0 ≈ 57 − 60 log10 (ωr RC) if ωr RC  1 (24)

The corner frequency is now 웆0 ⫽ 9/(RC), and the gain falls

VI C/2 C/2 V0 at 60 dB/decade or 18 dB/octave. It is rare to encounter more
than three sections in practice. The efficiency of these multi-
section filters depends only on the total resistance R, so it is
the same as for a single section.
(b)
We can represent the gain conveniently with a Bode plot,
Figure 6. RC smoothing filters, single section and multisection. which shows gain in decibels as a function of frequency (on a
 SMOOTHING CIRCUITS 405

log scale in hertz) over the range of interest. The Bode plots L I0
in Fig. 7 represent RC filters with one to three sections.
Given a total resistance R and a total capacitance C, what
is the best number of sections to use? For n sections, the cor- VI C V0
ner frequency is proportional to n2, while the slope of the high
frequency asymptote is ⫺20n dB/decade. A two-section filter (a)
gives greater attenuation than one section if 웆rRC ⬎ 12.0;
otherwise it is more effective to use one section. Similarly,
three sections are better than two if 웆rRC ⬎ 32.9 (with analy-
sis based on the fundamental). When deciding on the number L/2 L/2 I0
of sections, practical factors should also be taken into account,
such as availability of suitable components, their size, cost, VI C/2 C/2 V0
PCB area occupied, and the effect upon reliability.
As an example, let us consider the design of a filter with
the following specifications: VI ⫽ 12 V, IO ⫽ 10 mA, ␩ ⫽ 98%, (b)
f r ⫽ 웆r /(2앟) ⫽ 120 Hz, gain ⱕ ⫺30 dB. From the efficiency
formula, Eq. (18), we find R ⫽ 36 ⍀. Using the approximate Figure 8. LC smoothing filters, single section and multisection.
gain formulae, we obtain the following values:

n 웆rRC C Practical Component Values The gain is

1 31.62 1165 애F 36 ⍀, 1200 애F
2 22.39 825 애F 2 ⫻ 18 ⍀, 2 ⫻ 470 애F Gain (dB) = −20 log10 |1 − ωr2 LC| (26)
3 28.18 1038 애F 3 ⫻ 12 ⍀, 3 ⫻ 330 애F
The LC product is associated with a resonant frequency 웆0 ⫽
The two-section filter might be considered the best because it 1/ 兹LC. With this in mind,
has the lowest value of 웆rRC and therefore the lowest total
capacitance. But a single-section filter is simpler, and it might Gain (dB) = −20 log10 |1 − (ωr /ω0 )2 |
be the preferred design solution in practice. ≈ −40 log10 (ωr /ω0 ) if ωr /ω0  1 (27)
There are more sophisticated RC smoothing circuits (3,4),
including the parallel T notch network (4,5). These were used
in the past when low ripple was essential. Today, active It is essential that the resonant frequency be significantly
smoothing methods are a better alternative to these rather lower than the ripple frequency; otherwise, the filter could
sensitive circuits. actually increase the ripple.
When two LC networks are cascaded to form a multisec-
tion filter, additional resonances are created, and it becomes
LC Smoothing even more important to ensure that 1/ 兹LC is well below the
Single-stage and two-stage LC smoothing filters are shown in ripple frequency. The two-section filter with component val-
Fig. 8. For these filters, the efficiency is 100% in principle, ues L/2 and C/2 has the transfer function
although in practice it will be limited by parasitic resistances
within the components. For the single-stage circuit, the volt- 1
A(s) = (28)
age gain transfer function is 1 + 34 s2 LC + 16 (s LC)
1 2 2

1
A(s) = (25) The gain is
1 + s2 LC

Gain (dB) = −20 log10 |1 − 34 ωr2 LC + 1

16
(ωr2 LC)2 | (29)

0 With 웆0 ⫽ 1/ 兹LC once again, the gain becomes

Gain (dB) = −20 log10 |1 − 34 (ωr /ω0 )2 + 1

16
(ωr /ω0 )4 |
–20 ≈ 24 − 80 log10 (ωr /ω0 ) if ωr /ω0  1
Gain (dB)

(30)
1 section
2 sections
3 sections The filtering effect as frequency increases is much larger than
–40
for a two-section RC smoother. However, the frequency be-
havior is more complicated, having two resonant peaks. A
Bode diagram for one-, two-, and three-section LC filters with
–60 no load is shown in Fig. 9. For the single-section filter, the
0.01 0.1 1 10 100
Frequency × 2π RC
ripple frequency must be at least 兹2 times the resonant fre-
quency to ensure some reduction. Frequencies more than
Figure 7. Frequency response for multisection RC filters. about five times the resonant value are strongly attenuated.
406 SMOOTHING CIRCUITS
0 I0
Gain (dB)
–50
1 section
2 sections
3 sections
–100
–150
0.01 0.1 1 10 100
Frequency × 2π LC
Figure 9. Frequency response for multisection LC filters.
For the two-section filter, the ripple will increase without
bound if the ripple frequency is 1.23 or 3.24 times the reso-
nant frequency 웆0 ⫽ 1/ 兹LC, but again the filter is effective if
the ripple value is at least five times the resonant value. The
two-section filter gives better results than the single-section
filter provided that 웆r兹LC ⬎ 5.2. The three-section filter has
peaks near 1.34웆0, 3.74웆0, and 5.41웆0, and it is better than
the two-section filter only if 웆r兹LC ⬎ 8.8. The resonance
problems make even the three-section filter rarely used for
smoothing except at extreme power levels (several kilowatts
or more).
The gain parameters for Fig. 9 depend only on the LC
product, but do not give guidance on the selection of L and
C. One general rule is to choose 웆r兹LC ⬎ 5. A second require-
ment can be generated based on the impedance needs of an
ideal dc supply: The output impedance should be much lower
than the load impedance. This implies that the impedance of
the capacitor across the output terminals should be much
lower than the effective load impedance, ZL. The single-sec-
tion LC filter thus requires
1 1
 |ZL | or C 
ωrC ωr |ZL |
In the preceding RC example, the load draws 10 mA from a
12 V source. The effective load impedance is 12 V/10 mA ⫽
1200 ⍀. For a single-stage LC filter with ripple frequency of
120 Hz, this requires C ⬎⬎ 1.1 애F. A value of 100 애F will be
suitable. With the resonance requirement 웆r兹LC ⬎ 5, we find
L ⬎ 0.44 H.
The actual performance of LC smoothing circuits is closely
linked to the quality of their components. Any real inductor
or capacitor has its own internal equivalent series resistance
(ESR). In smoothing circuits, ESR values are often not much
different from the intended filter component impedance lev-
els. For example, ESR in the output capacitor of an LC net-
work can limit the ability to provide low output impedance.
Discussion of the nature of ESR and its effect on filters can
be found in Ref. 2.
LC Blocking and Traps: Resonant Smoothing
Since the ripple frequency is well-defined in many systems,
there are certain circumstances in which resonance can be
used to advantage. Consider the series blocking circuit of Fig.
L
VI C0 V0
C
Figure 10. LC filter with blocking pair.
10. This combination blocks all flow at 웆0 ⫽ 1/ 兹LC. The
transfer function is
1 + s2 LC
A(s) = (32)
1 + s2 L(C + CO )
At high frequency, A(s) 앒 C/(C ⫹ CO), so the design requires
CO ⬎⬎ C to give useful high-frequency attenuation. The un-
wanted high-gain resonance then occurs at a relatively low
frequency 1/ 兹L(C ⫹ CO). If LC ⫽ 1/웆r2 and CO ⫽ 10C, this
combination will give excellent ripple attenuation at 웆r, and
more than 20 dB of attenuation at higher frequencies. As in
the basic LC filters, the value of CO is chosen to provide a low
output impedance.
Consider again the previous power supply example with
1200 ⍀ load impedance. With a blocking filter, it is likely that
the largest remaining ripple component will appear at 3f r, or
360 Hz. An output capacitor value of 5 애F will make the im-
pedance sufficiently low at this frequency. This suggests a ca-
pacitor value of 0.5 애F for the blocking pair. The inductor is
selected based on 1/ 兹LC ⫽ 240앟 rad/s, giving L ⫽ 3.5 H.
Blocking filters are most useful when specific high frequencies
are involved, rather than power line frequencies. A similar
design procedure to block 20 kHz ripple in a switching power
supply will lead to a smaller inductor.
Figure 11 shows a shunt trap filter. In this case, the load
will not see any ripple at the single frequency 웆0 ⫽ 1/ 兹LC
except owing to component ESR values. The transfer function
is
(31) 1 + s2 LC
A(s) = (33)
1 + s2 (L + LI )C
At very high frequency, A(s) 앒 L/(L ⫹ LI), so the circuit
should have LI ⬎⬎ L to provide good high-frequency attenua-
tion. This circuit acts as the dual of the blocking circuit. The
impedance of the inductor LI should be much higher than that
of the load to prevent flow of unwanted frequencies. Like
blockers, traps are used to eliminate specific high frequencies.
In high-power supplies, traps are often used to eliminate par-
ticular strong harmonics rather than for broad ripple smooth-
ing. Additional discussion of tuned traps can be found in
Ref. 6.
LI I0
L
VI V0
C
Figure 11. LC filter with a trap.

1,1 1,2
C
vI(t)
2,1 2,2
+ V0 – while the diodes are off. This means ␶ ⬎⬎ ton ⫺ toff to keep the
To load
Figure 12. Full-bridge rectifier with capacitive filter.
Capacitive Smoothing for Rectifiers
A rectifier can be used with a purely capacitive smoothing
filter. With a resistive load, the structure becomes an RC com-
bination of the filter element and the load. This arrangement,
shown in Fig. 12, is sometimes called the classical rectifier
circuit. It is very common for filtering rectifiers below 50 W,
and it is used widely at higher power ratings as well.
In the classical rectifier, the shape of the ripple combines
a sinusoidal portion during times when the diodes conduct,
and an exponential decay during times when the diodes do
not conduct. The nature of the waveform supports useful ap-
proximations to the shape without resorting only to the fun-
damental frequency (6). The circuit output waveforms are
given in Fig. 13. The waveform 兩vI(t)兩 is shown as a dotted line
for reference. When a given diode pair is on, the output is
connected directly, and vO ⫽ 兩vI兩. When the diodes are off, the
output is unconnected, and vO decays exponentially according
to the RC time constant: assuming a resistive load, R. Con-
sider the time of the input voltage peak, and assume that the
diodes labelled 1,1 and 2,2 are on. In this arrangement, the
output voltage matches the input apart from the diode for-
ward drops (which are assumed to be small for the moment)
and the input current is iI ⫽ iC ⫹ iR. The arrangement will
continue until the diode current drops to zero and the devices
turn off. This time toff occurs shortly after the voltage peak,
and the time of the peak is a good approximation to the turn-
off point.
Once the diodes are off, the output decays exponentially
from its initial value. The initial voltage will be vI(toff ), and
the time constant ␶ will be the RC product, so
Diodes off: vO (t) = Vpk sin ωItoff e−(t−t off )/τ
Vpk
Voltage
Vpk/2
0 factors of 2 in Eq. (36) will not be present.
0 TI/2 TI 3TI/2
Time
Figure 13. Output voltage of classical rectifier.
SMOOTHING CIRCUITS 407
This decay will continue as long as the diodes are reverse-
biased, that is, vO ⬎ 兩vI兩. When the full-wave voltage increases
again during the next half-cycle, two diodes will turn on at
time ton as the full-wave value crosses the decaying output.
The output voltage maximum is the peak input Vpk, while the
minimum output occurs at the moment of diode turn-on, ton.
Thus the peak-to-peak output ripple is Vpk ⫺ 兩vI(ton)兩. To guar-
antee small ripple, the output voltage should decay very little
ripple low. For small ratios of (ton ⫺ toff )/ ␶, the exponential can
be represented accurately by the linear term from its Taylor
series expansion,
ex ≈ 1 + x, x1 (35)
The time difference ton ⫺ toff cannot be more than half the
period of vI(t), so the low ripple requirement can be expressed
as RC ⬎⬎ TI /2 if TI is the input period.
The details of the output voltage waveform and the target
of having low ripple lead to several reasonable assumptions
that can be made for the smoothing filter, leading in turn to
a simplified design framework:
1. The turn-off time occurs close to the voltage peak. It can
be assumed to coincide with the peak input voltage, and
the output voltage at that moment will be Vpk.
2. The voltage decay while the diodes are off is nearly lin-
ear, as in Eq. (35). Thus after toff , the voltage falls lin-
early as Vpk(1 ⫺ t/RC), with t being measured from the
voltage peak.
3. Since the total time of voltage decay never exceeds half
the period (for the full-wave rectifier case), the voltage
will not be less than Vpk[1 ⫺ TI /(2RC)]. The peak-to-
peak ripple ⌬VO will be no more than VpkTI /(2RC).
4. The diodes are on just briefly during each half-cycle.
The input current flows as a high spike during this in-
terval. Given a turn-on time ton, the peak input current
is approximately C(dv/dt) ⫽ 웆CVpk cos(웆Iton).
All these simplifications require RC ⬎⬎ TI /2, the usual case
to produce low ripple.
These simplifications are equivalent to assuming that the
output waveform is a sawtooth, with a peak value of Vpk and
a trough value of Vpk[1 ⫺ TI /(2RC)]. Therefore, the ripple is
(34) also a sawtooth, with a peak-to-peak value of ⌬VO ⫽
VpkTI /(2RC). This shape yields a simple design equation.
Given an output load current IO (approximately equal to
Vpk /R if the load is resistive), a desired ripple voltage ⌬VO,
and input frequency f I ⫽ 1/TI, we have
IO IO
VO = , or C = (36)
2 f IC 2 f I VO
The capacitance is selected based on the highest allowed load
current. Notice that if a half-wave rectifier substitutes for the
bridge, the basic operation of the circuit does not change, ex-
cept that the maximum decay time is TI instead of TI /2. The
The sawtooth waveform can be filtered further by connect-
ing an LC or RC passive circuit after the smoothing capacitor.
Sawtooth ripple with a peak-to-peak value of ⌬VO corresponds
408 SMOOTHING CIRCUITS
iI
C 12
120 V
60 Hz
120:10 6Ω
+ –
V0
Figure 14. Circuit to provide 12 V output from a smoothed rectifier.
to a ripple waveform fundamental of
VO
sin ωr t
π
and this ⌬VO /앟 amplitude provides a good basis for design of
further filtering.
The capacitor handles a substantial ripple current, and
this should be considered when choosing the component. Once
the peak input current Ipk ⫽ 웆CVpk cos(웆Iton) is determined,
the rms current in the capacitor can be estimated. The capaci-
tor current will be a series of approximately sawtooth spikes
of height Ipk and a narrow width TI ⫺ ton, and this waveform
has an rms value IC given by

3
Ipk
IC ≈
3πωICVpk
This expression can be used to determine the ripple current
rating requirement of the capacitor.
Capacitive Smoothing Example
Let us illustrate capacitive smoothing by choosing a suitable
capacitor for a classical rectifier. The rectifier is to supply 12
V ⫾ 3% to a 24 W load, based on a 120 V, 60 Hz input source.
The arrangement needed to solve this problem is shown in
Fig. 14.
A transformer will be needed to provide the proper step-
down ratio for this design. For completeness, let us include a
typical 1 V diode on-state forward drop. The load should draw
24 W/12 V ⫽ 2 A, and therefore it is modeled with a 6 ⍀
resistor. When a given diode pair is on, the output will be two
forward drops less than the input waveform, or 兩vI兩 ⫺ 2 V. We
need a peak output voltage close to 12 V. Therefore, the peak
value of voltage out of the transformer should be about 14 V.
The root mean square (rms) value of vI is almost exactly 10 V
for this peak level. Let us choose a standard 120 V to 10 V
transformer for the circuit on this basis.
To meet the ⫾3% ripple requirement, the output peak-to-
peak ripple should be less than 0.72 V. The capacitance
should be
IO 2A
C= = = 23 mF
2 f I VO 2(60 Hz)(0.72 V)
The approximate methods overestimate the ripple slightly,
since the time of the exponential decay is less than TI /2, so a
18 36
24
Output voltage (V)
Input current (A)
6 12
0 0
–6 v0(t) –12
vI (t)
–12 iI(t) –24
–18 –36
0 0.005 0.01 0.015 0.01 0.025 0.03
Time (s)
Figure 15. Output voltage and input current for rectifier example.
(37)
standard 22 mF capacitor will meet the requirements. The
waveforms that result from these choices are shown in Fig.
15. Notice that the current into the rectifier bridge does in-
deed flow as a series of spikes—with a peak value of about 36
A. The rms capacitor current is about 7 A.
The assumptions used for simplified rectifier design yield
excellent end results, compared with more precise calcula-
tions. For example, precise calculation shows that a 22 mF
capacitor yields 0.66 V ripple instead of 0.72 V. The linear
ripple assumption is a conservative approximation: It always
overestimates the actual ripple when exponentials are in-
(38) volved.
Current Ripple Issues
The narrow input current spikes in Fig. 15 beg the question
of whether smoothing will be needed for the input current.
The high current will produce significant voltage drops in any
circuit or device impedances, and it raises issues of coupling
through an imperfect ac source. To improve the input current
waveform, inductance can be placed in series with the recti-
fier input. With added inductance, the moment of diode turn-
off will be delayed by the inductor’s energy storage action.
When the diodes are on, the new circuit is a rectified sine
wave driving an inductor in series with the parallel RC load.
To analyze the situation, it is convenient to use the funda-
mental of the ripple voltage expected to be imposed on the
inductor-capacitor-load combination. For large inductor val-
ues, this ripple will not exceed that of the rectified sinusoid.
For small inductor values, this ripple is approximately the
sawtooth waveform with the capacitor alone. The function
兩Vpk sin(웆It)兩 has a fundamental component of amplitude
4Vpk /3앟, while the sawtooth has the fundamental amplitude
given in Eq. (37). Figure 16 shows an equivalent circuit based
on the fundamental of the imposed ripple voltage.
∆i(t) jω L +
∆VI 1 R ∆V0
sin (ω t)
(39) 2 jω C
–
Figure 16. Fundamental equivalent circuit for ripple evaluation in
a rectifier.
 SMOOTHING CIRCUITS 409

From the circuit in Fig. 16, we can compute the current iL L L2

V1 iL2
drawn from the fundamental source, and then we can use a + –
current divider computation to find the ripple imposed on the VI VL +
load resistance. The result for the peak-to-peak output ripple R V0
voltage as a function of the input peak-to-peak ripple voltage C C2 –
⌬VI (estimated based on the fundamental) is

VI Figure 18. A dc–dc buck converter with two-stage LC output filter.
VO = (40)
(1 + jωL/R − ω2 LC)

To make sure the inductor gives a useful effect, it is impor-
tant that 웆0 ⫽ 1/ 兹LC be significantly less than the ripple
frequency 웆r.
Consider again the example 12 V supply described pre-
viously. The ripple frequency is 240앟 rad/s. Inductor values
up to about 100 애H have little effect, or could even increase
the ripple, owing to resonance. An inductance of 200 애H
yields a value of 兩⌬VO /⌬VI兩 ⫽ 0.67. What value of imposed in-
put ripple should we use? The value 웆r2LC in the denominator
of Eq. (40) is 2.5, which is only a little larger than 1. The
input ripple will be nearly that of the capacitor alone, and the
inductor would be expected to reduce ripple by about 30%.
Simulation results were computed for the complete rectifier,
and they showed a reduction by 28% to 0.042 V. At the same
time, the peak value of iI dropped from almost 36 A to only
8.2 A.
Figure 17 shows the current iI for no inductance, for 200
애H, and for a 2 mH inductor. The current waveforms show
how the turn-off delay brings down the peak value and makes
the current smoother. One important aspect is that the turn-
off delay decreases the peak voltage at the output. For exam-
ple, the 2 mH case provides a 9 V output instead of the re-
quired 12 V. For a larger inductor, the actual output voltage
would be the average of the rectified sine wave, equal to
2Vpk /앟. In the limit of L 씮 앝 the current iI becomes a square
wave with a peak value equal to the load current. More com-
plete discussion of designs of LC filters for rectifier smoothing
can be found in Refs. 3, 4, and 6.
Example: Smoothing for dc–dc Converters
A dc–dc converter application will help illustrate LC smooth-
ing design and a simplified approach. A typical switching
dc–dc converter, with a two-stage LC output filter, is shown
in Fig. 18. The semiconductor devices act to impose a voltage
square wave at the filter input terminals.
The key to a simplified approach is this: At each node
within the filter, it is desired that the ripple be very low. This
simple concept means, for instance, that the voltage V1 in Fig.
18 should be nearly constant. If that is true, the inductor L is
exposed to a square voltage waveform. The various wave-
forms are given in Fig. 19. Since the inductor voltage vL ⫽
L(di/dt), the inductor current in Fig. 19(b) can be determined
from

vL (t)
iL (t) = dt (41)
L
The integral of a square wave is a triangle wave. This sup-
ports a linear ripple assumption for further analysis.
With linear ripple, the inductance L becomes relatively
easy to select. Consider a case in which an inductor is exposed
to a square wave of amplitude Vpk, a frequency of f, and a
pulse width of DT, as illustrated in Fig. 19(a). In the step-
down circuit of Fig. 18, this would lead to an average output
voltage of DVpk. While the voltage is high, the inductor is ex-
posed to (1 ⫺ D)Vpk ⫽ L(diL /dt). Since the ripple is linear, this
can be written vL ⫽ L(⌬iL /⌬t), with ⌬t ⫽ DT. Now, the induc-
tance can be chosen to meet a specific current ripple require-
ment,

36 vL DT vL DT
L= and iL = (42)
iL L

24
This simple but powerful expression leads to a quick selection
of values once the circuit requirements are established.
12 A special value of inductance from Eq. (42) is the one that
sets current ripple to ⫾100%. This is the minimum induc-
Current (A)

tance that will maintain current flow iL ⬎ 0 and is termed the

0 critical inductance, Lcrit. Setting a specific ripple level is equiv-
alent to setting the ratio L/Lcrit. For example, if the current
i I, L = 0 ripple is to be ⫾10%, the inductance should be ten times the
–12
iI, L = 0.2 mH
critical value, and so on.
Now consider the capacitor C that follows the inductor.
iI, L = 2 mH
–24 The desire for low ripple means that the current in inductor
L2 should be almost constant. The current in the capacitor C
will be very nearly the triangular ripple current flowing in
–36
0 0.005 0.01 0.015 0.02 0.025
L. Since iC ⫽ C(dvC /dt), we have

Time (s) iC (t)
vC = dt (43)
Figure 17. Rectifier input current when inductance is added. C
410 SMOOTHING CIRCUITS

To provide low relative ripple ⌬v1 /vL, the resonant radian fre-
Vpk quency 1/ 兹LC must be well below the square-wave radian
Voltage at diode

DT
frequency 2앟/T. This is easy to see by requiring ⌬v1 /vL ⬍⬍ 1
in Eq. (45). Then

DT 2 1
r8
 1, √  f (46)
8LC LC D

The next inductor L2 should provide almost constant out-

0 T = 1/f 2T 3T put vO, so it is exposed to the piecewise quadratic ripple volt-
age from capacitor C. Analysis of this waveform is more com-
(a)

;;
plicated, but it can be approximated well as by a sine wave
with peak value ⌬v1 /2. The fundamental should provide a
good basis for further stages. Then the approximate sinusoi-
VL(t) dal waveform appears entirely across L2. The ripple current
in L2 is

1 v1 v1
iL2 = sin(ωrt) dt = cos(ωrt) (47)
L2 2 2L2 ωr

Since 웆r ⫽ 2앟/T, the peak-to-peak current ripple in L2 is

Area 5iL(t)L/T
v1 T vL DT 3
iL2 = = (48)
2πL2 16πL2 LC

By a similar process, the final output voltage ripple is

Voltage or current

25v1(t)LC/T 2 iL2T vL DT 4
vO = = (49)
2πC2 32π 2 L2C2 LC

Since these relationships are based on ideal results for each

part, the assumption here is that the ripple is reduced sig-
100iL2(t)L2LC/T 3 nificantly at each stage. This requires 1/ 兹L2C2 ⬍ 2앟/T, and
so on.
Actually, it is unusual in the context of dc–dc conversion
to reduce the ripple substantially in each LC filter stage.
More typically, the first stage performs the primary ripple re-
duction, while the second stage uses much smaller compo-
500v0(t)L2C2LC/T 4 nents to filter out the effects of ESR in C.

ACTIVE SMOOTHING
0 T 2T 3T
Time In active smoothing, circuits that resemble amplifiers are
used in addition to storage elements for the smoothing pro-
(b) cess. Both dissipative and nondissipative approaches exist,
Figure 19. Current and voltage waveforms at points within the LC but dissipative methods are the most common. The energy
filter of Fig. 18. (a) Diode voltage. (b) Voltages and currents in the arguments require dissipative active smoothers to deliver out-
smoothing filter. put power below the minimum instantaneous input power.
For this reason, most dissipative active methods combine
smoothing and regulation. Voltage regulators are covered in a
The integral of a triangle is a piecewise-quadratic waveform. separate article, so just a short introduction is provided here.
Of more immediate concern is the effect on voltage ripple, as
shown in Fig. 19(b). When the capacitor current is positive, Series-Pass Smoothing
the voltage will be increasing. The total amount of the voltage Figure 20 shows a simple series-pass circuit for smoothing
increase, ⌬v1, will be proportional to the shaded area under and regulation. In the arrangement shown, a constant low-
the triangle, and
1 1 T iL iL T
v1 = = (44) –
C2 2 2 8C iI = ic +
Imperfect +
iB VBE To
With the ripple current value from Eq. (42), this means that dc VI V0 load
the ripple on voltage V1 is supply VR
–
v DT 2
v1 = L (45)
8LC Figure 20. Series-pass active smoothing and regulating circuit.

B RB RC C
Cµ
rπ r0
Cπ gmvbe
RE
E RI. The fixed voltage delivers the desired output current IO.
Figure 21. Hybrid-앟 transistor model.
power reference voltage VR is produced and is then used to
drive the base of a pass transistor. In its active region, the
transistor exhibits a nearly constant base–emitter voltage
drop, and the current iC equals 웁iB. The emitter voltage will
be VR ⫺ VBE, which is nearly constant. If 웁 is high, the base
current will be low, and the voltage VBE will change little as
a function of load.
From a smoothing perspective, the interesting aspect of
the series-pass circuit is that the output voltage is indepen-
dent of the input voltage, provided that the input voltage is
high enough for proper biasing of the transistor. This is ex-
actly representative of the dissipative smoothing concept. For
example, if the output is intended to be 5 V and if the transis-
tor voltage VCE should be at least 2 V for proper bias in the
active region, then any input voltage higher than 7 V will
support constant 5 V output. The input voltage can vary arbi-
trarily, but the output will stay constant as long as it never
dips below 7 V.
The efficiency of a series-pass circuit is easy to compute. If
웁 is very large, the emitter current IE ⫽ IO will equal the col-
lector input current IC ⫽ II. The efficiency is
PO V I V
η= = O O = O (50)
PI VI II VI
High efficiency demands that the input and output voltages
be as close as possible.
A real series-pass circuit will still exhibit a certain level of
ripple. The basis for this can be seen in the small-signal hy-
brid-앟 model of a bipolar transistor (7), shown in Fig. 21. In
the case of fixed voltage at the base terminal and voltage with
ripple at the collector terminal, the stray elements r0 and C애
both provide a path by which ripple current can reach the
output. In a good-quality transistor, r0 can be made very high,
so internal capacitive coupling to the base terminal is the
most important leakage path. In practical applications, it is
common to provide a passive smoothing filter stage at the se-
ries-pass element input to help remove high-frequency har-
monics. The output of the regulator is provided with capaci-
tive decoupling to prevent loop problems such as those
described in the Introduction. With these additions, a series-
pass smoother can reduce ripple to just a few millivolts even
with several volts of input ripple. That is, ripple reductions
on the order of 60 dB or more can be achieved. Discussions of
integrated circuits that implement series-pass circuits can be
found in Refs. 8 and 9.
SMOOTHING CIRCUITS 411
Shunt Smoothing
Series smoothing makes use of the ability of a bipolar transis-
tor to establish an emitter current that depends on the base
input rather than on the input source. Shunt smoothing is a
dual of this in certain respects: It makes use of the ability of
certain elements to establish a voltage that is independent of
the source. In Fig. 22, a basic form and a typical implementa-
tion of a shunt regulator are shown. The imperfect dc supply
provides energy flow and current iI through the resistance
The fixed element makes IO independent of iI, and smoothing
is accomplished.
The simple circuit of Fig. 22(a) is actually very common in
battery-powered devices. When a charger is connected, it is
only necessary to make sure that the average value of iI is
greater than IO to provide both regulation and charging. With
the charger is disconnected, the battery continues to maintain
operation of the load. In this case, the storage action of the
battery means that the instantaneous value of iI is unimport-
ant; an unfiltered rectifier can be used as the imperfect dc
supply, for example. The actual level of output ripple depends
on the quality of the battery as a dc source.
The Zener diode circuit of Fig. 22(b) is common for use in
generation of reference voltages, and it is also widely used for
low-power sensor supply requirements and similar applica-
tions. Since the diode does not have any energy storage capa-
bility, this smoother requires that the instantaneous value of
iI must always be greater than the desired IO. If the output
current is not well-defined, a worst-case design must estimate
the highest possible output current as the basis for the mini-
mum iI.
In a shunt regulator, there is power loss in the resistor:
the square of the rms value of iI times the input resistance
RI. There is also additional power in the fixed voltage ele-
ment: the difference iI ⫺ IO times VO. The power in the voltage
element is lost in the Zener circuit, or it serves as charging
power in the battery circuit. The output power PO is VOIO. If
we could select a value of input current to exactly match the
output current (the best-case situation with minimum input
iI RI l0
Imperfect To
dc VI V0
load
supply
(a)
iI l0
Imperfect
VI V0 To
dc
load
supply
(b)
Figure 22. Shunt smoothing alternatives.
412 SMOOTHING CIRCUITS

function of the selected reference value, and it is independent

of the input. Large voltage ratios are troublesome for the lin-
Imperfect Power High Active Low
ear smoothers. For example, if either type is used for 48 V to
dc supply conversion ripple smoothing ripple 5 V conversion, the best possible efficiency is only about 10%
port circuit port even if ripple is not an issue.
Both series and shunt smoothers benefit if the input source
ripple is relatively low, provided that this is used to advan-
tage to keep the voltage ratio low as well. For example, a
series smoother with an input voltage of 7 V ⫾ 0.1 V and an
ac current sensors output voltage of 5 V can produce an output with less than 1
mV of ripple with efficiency of about 70% if the series-pass
element can work with bias levels down to 1.9 V. A shunt
smoother can function with even lower bias. With a fixed load
level of 100 mA, an input voltage of 5.5 V ⫾ 0.1 V, and an
~ ~
High iI i0 Low output voltage of 5.00 V, a shunt regulator with efficiency up
ripple ic ripple to about 85% can be designed.
port port

Feedforward Feedback path Cancellation Smoothers

path
Cancellation current driver In cancellation smoothing (10,11), methods similar to series
and shunt circuits are used, but handle only the ripple itself.
This avoids the dc dissipation inherent in both of the linear
Figure 23. A general active smoothing system and its generic imple-
mentation.
methods, since the dc input to output voltage ratio becomes
irrelevant. The general principle of cancellation smoothing
can be observed in Fig. 23, which shows a shunt-type current
current and minimum loss), the loss power PL would be IO2 RI.
injection cancellation smoother. In such a system, the input
Since the input current is (VI ⫺ VO)/RI, the efficiency would
ripple current ĩI is sensed, and the controller creates a cancel-
be
ling current iC as close as possible to ⫺ĩI. The practical version
PO VO IO
η= =
V − V  = VO (51)
in Fig. 24 shows an input filter inductor and a transformer-
PO + IO2 RI VI based amplifier coupler. With these additions, the current
VO IO + IO I O
RI
RI amplifier handles none of the dc current or power, and there
is very little dissipation.
Any realistic design must have higher input current. For this Cancellation smoothing can work either on feedforward or
reason, a shunt smoother is always less efficient than a series feedback principles (or with a combination of these). In feed-
smoother for given input and output voltages. It is a very sim- forward cancellation, the input ripple current is sensed, and
ple circuit, however, which explains its wide use, especially at an amplifier with good bandwidth and a gain of exactly ⫺1 is
low power levels. needed. The ability of such a system to produce smooth out-
put depends on the accuracy of the gain. For example, if the
Summary of Linear Smoothing
actual gain is ⫺0.99 instead of ⫺1.00, then the output ripple
Series and shunt smoothers are termed linear active circuits will be 0.01 times that at the input—a reduction of 40 dB. It
because they function as amplifiers. The output is a linear is not trivial to produce precise gain over a wide frequency

Low ripple here

VI iI I0 V0
L
Dc – dc
converter Current
with transformer Load
iC
imperfect C0
input Dc blocking
CC

CF Feedback
path
~ +
Feedforward vL
Current
path driver Gain
~
iI – correction
RF to minimize
ripple
Integration
~
Figure 24. Implementing a feedforward to provide iI
~
from vL
ripple current canceler.
 SOCIAL AND ETHICAL ASPECTS OF INFORMATION TECHNOLOGY 413

range, but even 10% gain error can provide a useful 20 dB of 14. L. E. LaWhite and M. F. Schlecht, Active filters for 1 MHz power
current ripple reduction. circuits with strict input/output ripple requirements, IEEE
In feedback cancellation, the operating principle is to mea- Trans. Power Electronics, 2: 282–290, 1987.
sure and amplify the output ripple signal ĩO and use this to
develop a correction current equal to the gain k times the out- PHILIP T. KREIN
put ripple. Feedback cancellation has the advantage of cor- University of Illinois
recting ripple caused by noise at the output as well as ripple DAVID C. HAMILL
derived from the imperfect dc supply. High gain is required. University of Surrey
For example, if k ⫽ 100, the output ripple ideally is a factor
of 100 lower than the input ripple, and the ripple is reduced
by 40 dB. Gain of k ⫽ 1000 reduces current ripple by up to
60 dB, and so on. This is too simplistic, however. The sensing
device for ĩO has an associated time lag. If the gain is too high,
this time lag will lead to instability. Feedback cancellation is
extremely effective in systems with low ripple frequencies (be-
low about 10 kHz), since a brief time lag in the sensor will
not have much effect at low speeds.
Cancellation methods, often combining feedforward and
feedback techniques, have been used in power supplies at 50
Hz and 60 Hz (12,13), spacecraft systems switching at up to
100 kHz (11), and a variety of dc–dc conversion systems
(10,14).

ACKNOWLEDGMENT

P. Krein participated as a Fulbright Scholar, supported

through the joint United States–United Kingdom Fulbright
Commission during a visiting appointment at the University
of Surrey.

BIBLIOGRAPHY

1. A. I. Zverev, Handbook of Filter Synthesis, New York: Wiley, 1967.

2. A. B. Williams, Electronic Filter Design Handbook, New York:
McGraw-Hill, 1981.
3. P. M. Chirlian, Analysis and Design of Integrated Electronic Cir-
cuits, London: Harper and Row, 1982, p. 1011.
4. R. J. Rawlings, Parallel T filter networks, in F. Langford-Smith
(ed.), Radio Designer’s Handbook, 4th ed., London: Iliffe Books,
1967, pp. 1194–1196.
5. Anonymous, High Q notch filter, linear brief 5, in Linear Applica-
tions Databook, Santa Clara: National Semiconductor, 1986, p.
1096.
6. P. T. Krein, Elements of Power Electronics, New York: Oxford
Univ. Press, 1998.
7. A. Vladimirescu, The SPICE Book, New York: Wiley, 1994.
8. R. J. Widlar, A versatile monolithic voltage regulator, National
Semiconductor Application Note AN-1, 1967.
9. R. J. Widlar, IC provides on-card regulation for logic circuits, Na-
tional Semiconductor Application Note AN-42, in Linear Applica-
tions Databook, Santa Clara: National Semiconductor, 1986.
10. P. Midya and P. T. Krein, Feedforward active filter for output
ripple cancellation, Int. J. Electronics, 77: 805–818, 1994.
11. D. C. Hamill, An efficient active ripple filter for use in dc–dc con-
version, IEEE Trans. Aerosp. Electron. Syst., 32: 1077–1084, 1996.
12. L. Gyugyi and E. C. Strycula, Active ac power filters, Proc. IEEE
Industry Applications Soc. Annu. Meeting, 1976, p. 529.
13. F. Kamran and T. G. Habetler, Combined deadbeat control of a
series-parallel converter combination used as a universal power
filter, IEEE Trans. Power Electron., 13: 160–168, 1998.

SUMMING CIRCUITS
Electronic systems perform operations on information signals
represented by electrical variables. Among these operations,
one of the most simple, and therefore most common and
widely used, is the summation or addition of signals, with a
large range of variations.
Signal addition is a fundamental operation upon which
many other simple and complex operators are based. For ex-
ample, digital processing circuits perform most of their opera-
tions from some combination of addition and shifting.
Signal-processing circuits can be classified into two large
groups, according to the way in which they perform their pro-
cessing function: analog and digital processing systems. Ana-
log processing systems operate on signals defined over a con-
tinuous range or interval. These signals are generally
associated with the continuous value of some electrical mag-
nitude of the circuit, like a voltage, current, charge, or mag-
netic flux defined in connection with some element or electri-
cal nodes in the network. Analog summing operations emerge
from the basic laws of electromagnetism, Maxwell equations,
and in particular their derived result in circuit theory (Kirch-
hoff ’s Laws). On the other hand, digital processing systems
operate over abstract number representations, generally codi-
fied as a sequence of digits, without a direct connection to a
physical magnitude in the network. Possible values of each
digit are discrete (two in the typical binary case), and each
value is associated to some range of an electrical variable. In
these cases, summation follows algorithmic rules not related
to circuit theory.
ANALOG ADDERS
Introduction
An electronic analog adder operates over two or more electri-
cal input signals (x1, x2, . . ., xN), providing an electrical out-
put signal xs, which is the sum of the former
xS = x1 + x2 + · · · + xN (1)
The electrical signals involved may be of the same or different
nature (voltage, current, charge, flux). Often, input signals
are all of the same type. If signals of different nature are com-
bined, appropriate constants must be introduced to maintain
a proper dimensionality (1). Such signal multiplication by a
constant or scaling, is often found as a constitutive operator
of analog summing circuits, as shall be seen, even when all
input signals are of the same nature. The involved constants
J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.
SUMMING CIRCUITS 633
are always related to physical properties of one or more cir-
cuit elements and, in some cases, to other electrical signals.
The number of analog summing circuits reported in the
literature is extremely large. Therefore, a classification is
mandatory for their discussion. This classification can be
made according to the nature of the signals to be added (cur-
rent or voltage) and also by the nature of the output signal.
Another distinctive property is the way in which the time
evolution of the input signals is taken into account: continu-
ous-time or sampled-data systems. Although in either case
the expected input and output signals are continuous in am-
plitude (i.e., analog), continuous-time signals are defined at
any instant within some time interval, and the corresponding
systems operate continuously in time. On the other hand, the
information carried by discrete-time signals is defined only for
discrete-time instants, and the corresponding sampled-data
systems operate under the control of one or more periodic
clock signals.
An alternative form of classification refers to the circuit
technique employed to find the summing circuit, in particular
to the type of elements required for its implementation: resis-
tors, capacitors, analog switches, operational amplifiers, cur-
rent conveyors, transistors, operational transconductance am-
plifiers, and the like.
Analog Summation Fundamentals
Analog summing circuits are essentially based on Kirchhoff
Laws. To be precise, most analog summing circuits rely on
Kirchhoff Current Law (KCL), which can be formulated as
follows: The algebraic sum of currents flowing into any net-
work node is zero. According to this law, the summation of
any number of current signals is straightforward. It can be
obtained by simply connecting the circuit branches carrying
the currents to be added to a common node and allowing an
additional branch for the sum of the currents to flow out of
the node. Obviously, the current branches must have one of
the nodes available to be connected to the summing node.
The Kirchhoff Voltage Law introduces a similar tool for
voltage signals. It can be formulated as follows: The algebraic
sum of the potential drops around any loop is zero. According
to this law, the summation of voltage signals is also straight-
forward and can be obtained from a series connection of the
pair of terminals between which the incoming voltage signals
are defined. Because the incoming voltage sources are con-
nected in series, they must be ‘‘floating,’’ that is, the voltage
drops must be insensitive to a shift of their terminal voltages
with respect to an arbitrary reference level.
Although summing circuits based on either of the two ap-
proaches are possible, voltage signals found in most electronic
circuits are defined as the potential at a particular node mea-
sured from a common ground reference: therefore, floating
voltage signals are not usual. For this reason, most analog
summing circuits rely on KCL, as stated previously.
Still, KCL-based summing circuits can operate on voltage
signals, as long as the incoming voltages are transformed into
currents, added at a common node, and the resulting current
transformed again into a voltage. This is the most common
operation principle of summing circuits, found in traditional
and well-known structures.
Because summation is linear by definition, voltage-to-cur-
rent and current-to-voltage transformations should be linear.
634 SUMMING CIRCUITS

In its simplest form, these transformations can be obtained I1

from linear two-terminal elements, whose constitutive equa- V1 Z1
tions are defined as I2 IS
V2 Z2 Vo
V =Z·I or I =Y ·V (2) .
. . Ns
. .
. . ZF
. .
. .
where Z and Y are the impedance and admittance of the two- . IN
.
terminals element, respectively. It is obvious that Z ⫽ 1/Y. VN ZN
Figure 1 shows a conceptual example of voltage-signals
summation based on KCL. Simple analysis results in the fol- Figure 2. Voltage-signals summation without active element. Scal-
lowing expression for the output voltage: ing factors become interdependent.

N
Z
N
Yi
Vo = F
Vi = Vi (3)
i=1
Zi Y
i=1 F
Ii. This will be illustrated in connection with Fig. 2, a simpli-
fied version of Fig. 1 in which the active element has been
eliminated. Simple analysis results in the following expres-
Elements Z1 to ZN perform a linear transformation of the in- sion for the new output voltage:
put voltages into currents. These currents are added at node
Ns according to KCL. The resulting current Is is reproduced

N
by the current-controlled current-source (CCCS) and linearly YiVi
transformed into the output voltage Vo with the help of ele- Vo =
i=1
(6)
ment ZF. Note that the output voltage represents a weighted

N

summation of the input voltage signals, all of them defined Yi + YF

i=1
with respect to a common voltage reference.
The intermediate transformation into currents results in
which is still a weighted summation of the input voltages.
different scaling factors or weights Wi for each input signal
Now, however, the scaling factors associated with the differ-
ent input signals cannot be controlled independently. Fur-
Yi Z thermore, in the simplest case in which all elements are resis-
Wi = = F (4)
YF Zi tors, the weighting factors will all be smaller than one. In
addition, the effect of the external load on the output voltage
must be carefully considered. Because of these and other re-
allowing the output voltage to be expressed as
lated reasons, most analog summing circuits employ some
type of active element.


N
Vo = WiVi (5)
i=1
Analog Summing Circuits with Operational Amplifiers
A simple and well-known alternative for a practical imple-
The impedance ZF of the output element provides a ‘‘gain’’ mentation of Fig. 1 uses operational amplifiers as active de-
control for the output signal. Scaling weights and global gain vices and linear resistors as two-terminal elements. Other
control introduce a large flexibility in these summing opera- simple two-terminal elements can also be employed (e.g., ca-
tors. Some of these capabilities rely on an active element (in pacitors), although special considerations are required. In
this example a CCCS) to implement a virtual ground at node what follows, we assume the use of linear resistors R ⫽ 1/G
Ns, which in turn allows the transformation of current Is into for simplicity.
the output voltage without altering the individual currents The resulting circuit is shown in Fig. 3. In this circuit, cur-
rent Is flows from the virtual ground node toward the output
terminal, resulting in a sign inversion in the summing opera-
tion. This summing circuit, in which all weights are negative,
is commonly referred to as an inverting configuration.
I1
Positive weights can be achieved by several means, the
V1 Z1 simplest of them being the use of an additional inverting con-
I2 IS
figuration with a single input (i.e., an inverting amplifier), as
V2 Z2 shown in Fig. 4.
. Vo
. . Ns Another alternative results from the combination of the
. .
. . circuit in Fig. 2 with a noninverting amplifier. This solves the
. . ZF
. . restriction on the weights to values smaller than unity and
. IN IS
.
provides the necessary driving capability for the output volt-
VN ZN
age. The resulting circuit, commonly known as a noninverting
configuration, is shown in Fig. 5. Note that the grounded in-
Figure 1. Conceptual example of voltage-signals summation based put element is used as an additional input.
on KCL. This is the underlying fundamental of most analog sum- The circuits in Figs. 3–Fig. 5 are restricted to ‘‘same-sign’’
ming circuits. weights. When a summing circuit with both positive and neg-
 SUMMING CIRCUITS 635

I1
V1 Z1 ZF
I2 IS
V2 Z2 –
.
. . Ns Vo
. .
. .
. . +
. . N
RF
N
Gi
N
. IN
. Vo = – Σ Vi = – Σ Vi = – Σ Wi Vi
i = 1 Ri i = 1 GF i= 1 Figure 3. Voltage-summing circuit using oper-
VN ZN
ational amplifiers (inverting configuration).

I1
V1 Z1 N
ZF
I2 IS Vo = Σ Wi Vi
Z i= 1
V2 Z2 –
.
. . Ns Z
. . –
. .
. . +
. . Vo
. IN Gi Z
. Wi = = F
VN ZN GF Zi

Figure 4. Positive-weight summing circuit using two inverting configurations.

N
Σ
Gi Vi
Z– ZF G– i = 1
Vo = 1 +
I1 GF N
V1 Z1 – Σ Gi
i=1
I2 Vo
V2 Z2 +
.
. .
. .
. .
. . G– Gi
. . Wi = 1 +
. IN
. GF N
VN ZN Σ Gi Figure 5. Positive-weight summing cir-
i =1 cuit using a noninverting amplifier.

V1– Z1– Z 0–

V2– Z2– M
. GF + Σ Gj–
. .
. . N G+ M G–
. . j= 0
Σ Vi+ – Σ
. i j –
. . Vo = V
. . N GF GF j
. + i =1 j= 1
VM– ZM
–
ZF
Σ Gi
i= 0

V1+ Z1+ –
Vo
V2+ Z2+ +
.
. .
. .
. .
. .
. .
.
.
+
VN+ ZN Z 0+

Figure 6. Generalized summing circuit based on an operational amplifier.

636 SUMMING CIRCUITS

ative weights is required, some of the input signals can be circuits are in fact direct implementations of Fig. 1. As in the
inverted at the expense of an additional active element per previous case, different configurations with positive and nega-
inverted input. Another alternative is the use of the so-called tive weights can be obtained.
generalized adder, obtained from a combination of the in- Figure 7 shows a noninverting [Fig. 7(a)] and an inverting
verting and noninverting configurations in Figs. 3 and 5. The [Fig. 7(b)] configuration. Both of them are possible with either
resulting circuit and its transfer function are shown in Fig. 6. type I or type II CCs. The two configurations differ only in
As with Fig. 3, negative weights are given by the ratio of the ‘‘sign’’ of the CCs: CC⫹ for the noninverting configuration
the input Gj⫺ to the feedback GF conductances and are inde- and CC⫺ for the inverting counterpart.
pendent of each other. On the other hand, positive weights If either CC⫹ or CC⫺ are not available, the necessary sign
depend on all input conductances. In order to eliminate this inversion can be achieved at the expense of an additional CC
drawback, two additional elements Z0⫹ and Z0⫺ are introduced of either sign, as shown in Fig. 8. Note that the sign-inverter
to allow for the possibility of making in Fig. 8(a) operates on a voltage signal. Its input impedance
is high; therefore, it may be connected to any circuit node


M
GF + G−j without affecting its behavior. On the other hand, inverting
j=0 stages in Fig. 8(b, c) operate on currents and thus should be
=1 (7) inserted in series at the output of the CC in Fig. 7, whose


N
G+
i
loading element ZF must be eliminated.
i=0 The combination of the circuits in Figs. 7 and 8 results in
either inverting or noninverting summing circuits realizable
which allows the transfer function of the generalized adder to with any type of CC. If positive and negative weights are re-
be expressed as quired on the same summing device, we can use inverters at
specific inputs, or a generalized adder architecture based on


N

M
Vo = Wi+Vi − W j− V j− (8) CCs. Figure 9(a) shows an implementation based on CCI of
i=1 j=1 either sign. Indeed, the output of the CCI is not used. Note
that its transfer function would be identical to Eq. (8) if
with positive and negative weights having similar expressions


N

M
G+ G−j G+
i − G−j = GF (14)
Wi+ = i and W j− = (9) i=0 j=0
GF GF

Note that Eq. (7) can also be written as where GF is an arbitrary normalization conductance, not asso-
ciated to any element, that plays the role of GF in Eq. (9).


M
G−
N
G+ Elements Z0⫹ and Z0⫺ in Fig. 9(a) serve the purpose of achieving
1+ W j− + 0
= Wi+ + 0 (10) Eq. (14). As with opamp-based adders, only one of these ele-
j=1
GF i=1
GF
ments is required.
The design equations required to obtain the different Gi
Therefore, if
values are identical to those obtained for the generalized


M

N adder in Fig. 6.
1+ W j− < Wi+ (11) Figure 9(b) shows a generalized adder based on a CCII and
j=1 i=1 its transfer function. The positive signed expression is ob-
tained if a CCII⫹ is employed, whereas the negative sign cor-
we can select G0⫹ ⫽ 0 and responds to the use of a CCII⫺. In either case, the transfer
  function can again be expressed in the form of Eq. (8) if Z0⫹


N

M
G− Wi+ − W j− − 1 and Z0⫺ are chosen to verify
0 = GF (12)
i=1 j=1


N

M

On the other hand, if Eq. (11) is not true, we can select G0⫺ ⫽ G+
i = G−j (15)
i=0 j=0
0 and
 


M

N As in the previous case, only one of both impedances are
G+
0 = GF 1 + W j− − Wi+ (13) needed. If
j=1 i=1

M

N
Therefore, only one element among Z0⫹ and Z0⫺ is actually re- W j− < Wi+ (16)
quired. j=1 i=1

Summing Circuits Using Current Conveyors

we can select G0⫹ ⫽ 0 and
The use of current conveyors (see CURRENT CONVEYORS) as the
 
required active element in Fig. 1 results in a new family of

N

M
summing circuits. Indeed, because current conveyors (CC) G−
0 = GF Wi+ − W j− (17)
perform as current-controlled current-sources, the resulting i=1 j=1
 SUMMING CIRCUITS 637

I1 I1
V1 Z1 V1 Z1
I2 IS I2 IS
+
V2 Z2 x CCI V2 Z2 x CCI–
. or z Vo . or z Vo
. . Ns y . . Ns y
. . CCII+ . . CCII–
. . . .
. . . . IS ZF
.
. IN . IS ZF .
. IN .
. .
VN ZN VN ZN

N G N N G N
Vo = Σ i
GF
Vi = Σ Wi Vi Vo = – Σ i
GF
Vi = – Σ Wi Vi
i=1 i=1 i=1 i=1
(a) (b)

Figure 7. Summing circuits using a single current conveyor: (a) noninverting configuration and
(b) inverting configuration.

Otherwise, we can select G0⫺ ⫽ 0 and ential input of the OTAs allow the realization of either-sign
  weights by simply swapping the input nodes.

M

N
Figure 11 shows a generalized adder structure, whose
G+
0 = GF W j− − Wi+ (18) transfer function is given by
j=1 i=1

N

M
An important remark concerning the presented summing cir- Vo = Wi+Vi − W j− V j− (19)
cuits with CCs is that, because the output impedance of the i=1 j=1
current conveyor is high, any current drain from the output
node Vo would result in deviations from the expected behav- where the weights are given by transconductances ratio
ior. If a low impedance load is to be driven by Vo, a buffer will
be required. g+ g−
Wi+ = W j− =
mi mj
and (20)
gmF gmF
Summing Circuits Using Operational
Transconductance Amplifiers which can be made highly insensitive to variations in the IC
fabrication process. As with CC-based realizations, an output
The use of operational transconductance amplifiers (OTA) as
buffer will be required if low impedances are to be driven.
active elements constitutes by itself a general technique for
the realization of analog circuits, with special relevance in
Discrete-Time Summing Circuits
integrated circuit (IC) realizations. Summing devices are eas-
Using Switched-Capacitors Techniques
ily realized with this circuit technique.
Figure 10(a) shows the symbol and transfer function of an Switched-capacitor (SC) techniques substitute continuous-
OTA. Its differential input provides a large flexibility in the time current flow by periodic charge-package transferences.
realization of most operators, including positive and negative In their simplest and most common form, SC circuits are con-
resistors, as shown in Figs. 10(b, c). OTAs by themselves pro- trolled by a pair of nonoverlapped clock signals defining two
vide a direct transformation of voltages into currents, alternating configurations of the circuit. These two ‘‘phases’’
whereas the ‘‘resistor’’ configurations in Fig. 10 allow the in- are often referred to as even and odd.
verse transformation. Therefore, we have all elements re- The operation of an SC summing circuit can be described
quired to realize a summing structure. In addition, the differ- in general as follows: given a set of voltage signals to be

IS IS
V01 y V0 = – V01 x Vo = – Is ZF y CCI+
CCII+ z CCII – z or z
x y x CCI–
IS Vo = – Is ZF
Z ZF
Z ZF

(a) (b) (c)

⫹
Figure 8. Sign inverters using current conveyors: (a) inverter using a CCII , (b) inverter using
a CCII⫺, and (c) inverter using either a positive or a negative CCI.
638 SUMMING CIRCUITS

V1– Z1– Z 0– V1– Z1– Z 0–

– –
V2 Z2 V2– Z2–
. .
. . . .
. . . .
. . . .
. . . .
. . . .
. .
. .
– –
VM ZM VM– ZM–
y y
CCI z V0 CCII z Vo
x x
+ +
V1 Z1 V1+ Z1+
ZF

+ +
V2 Z2 V2+ Z2+
. .
. . . .
. . . .
. . . .
. . . .
. . . .
. .
. .
+ + +
VN ZN Z0 VN+ ZN+ Z +0

N
N M
Σ Gi+ Vi+ – Σ Gj– Vj– N G+
Σ Gi+ M G–
+ i= 0
Σ Σ GF Vj–
i j
i=1 j=1 Vo = – V+–
Vo = GF i M
N M i= 1 j= 1
Σ Gj
–
Σ
Gi+ – Σ Gj–
j= 0
i=0 j= 0
(a) (b)

Figure 9. Generalized adders using current conveyors: (a) using CCI and (b) using CCII.

added, each of them is periodically sampled, during one of

N
 
the clock phases, in a linear capacitor. The resulting charge
Qoe = Qe − Qo = Ci Vi2e (n) + Vi3o (n − 12 ) − Vi1o (n − 12 )
packages are added in a common node and transformed into a i=1
(21)
voltage during the same or the next clock phase using another
capacitor. Note that the underlying operation principle is
Note that signal information is conveyed in the difference of
identical to that of the previous continuous-time circuits, ex-
capacitor charges at the end of two consecutive odd and even
cept that current flows are replaced by periodic discrete-time
charge transferences, which indeed may be considered as a
current flow from a time-averaged perspective.
Figure 12(a) shows a set of SC input branches. In the odd- + –
V1 + – V1
to-even phase transition, a charge package ⌬Qoe, equal to the +
gm1 –
gm1
sum of the charge variations in each capacitor, flows to a vir- –
tual ground node. The value of ⌬Qoe is easily obtained
applying the charge-conservation principle, yielding
+ Vo –
V2 + – V2
+
gm2 –
gm2
I I –
. .
. .. .. .
. .
. .. .. .
I . .
– . . . .
. – .
gm V gm V gm . – .
V + gmF –
– – – VN + – VM
– – + –
gmN gmM
1 1 –
I = gm V V= V= –
gm I gm I
(a) (b) (c)
N g+ M g–
Vo = Σ mi Vi+ – Σ mj Vj
Figure 10. (a) Symbol and transfer function of an operational trans- –

conductance amplifier. (b) Implementation of a grounded resistor us- gmF gmF

i= 1 j= 1
ing an OTA with negative feedback. (c) Implementation of a grounded
negative resistor using an OTA with positive feedback. Figure 11. Generalized adder circuit based on OTAs.
 SUMMING CIRCUITS 639

o
V11 o o o V1o o
C1 o
V13 C1

e
V12 e e e V1e e

o V2o o ∆Qoe
V21 o o C2
C2 e
V23
∆Qoe
e
V22 V2e e
.. e e ..
.. .. .. ..
.. .. .. ..
.. . .. .
o
VN1 o o VNo o
CN o
VN3 CN
e
VN2 e e VNe e

(a) (b)

Figure 12. (a) Generic input branch of a SC summing circuit. (b) Input branch for SC structures
insensitive to opamp offset-voltage.

phases, represented by time-instants (n ⫺ 
)T and nT, respec-
tively, where T is the clock-signal period. The discrete-time
nature of the processing is therefore evident.
Each term in Eq. (21) is given by voltage differences at the
two plates of the corresponding capacitor. Although the vir-
tual ground node is nominally equivalent to ground, the in-
put-referred offset voltage of the required active element in-
troduces a small error. This error will be relevant if the
required accuracy is in the range of 7–8 equivalent bits or
above. Offset-voltage effects can be avoided if one of the plates
of the capacitor is permanently connected to the virtual
ground node, as shown in Fig. 12(b), which results in the fol-
lowing expression for ⌬Qoe,


N sensing stages in Fig. 13 result in summing structures insen-

Qoe = Qe − Qo = Ci [Vie (n) − Vio (n − 12 )]
i=1
Results similar to Eqs. (21) and (22) can be obtained for the
charge package ⌬Qoe originated just after the even-to-odd
transition.
The transformation of these charge signals into a voltage
requires a linear capacitor and an active element to imple-
ment the required virtual ground. An operational amplifier
with capacitive feedback is the most common choice, as shown
in Fig. 13(a). Note that one of the clock phases is used to
discharge the feedback capacitor and to provide a current
path to the virtual ground node. Therefore, only one of the
charge packages originated by the input branches, ⌬Qoe in the
example, is actually transformed into a voltage, and the out-
put signal is valid only during one of the clock phases. Indeed,
during the other clock phase, the output voltage is equal to
the opamp offset voltage, resulting in large slewing require-
ments from the opamp. Figures 13(b, c) present alternative
charge-sensing stages with lower slewing requirements at the
expense of an increased complexity. Other relevant differ-
ences are related to their particular sensitivity to the finite
gain and bandwidth of the opamps (1).
Combinations of the input branches in Fig. 12 and the
(22) sitive to parasitic capacitances. If Fig. 12(b) is employed, the
result is also insensitive to the opamp offset, but only during
one of the clock phases.
In every case, the output voltage can be obtained from
Vie = −
Qoe /Co (23)
Note that a sign inversion takes place in the charge-sensing
stage. The underlying voltage-charge-voltage transformations
using capacitors result in the following expression for the ab-

o o oo
∆Qoe Co ∆Qoe Co ∆Qoe Co
e e Co′′ e
– – –
o o o
+ Vo + Vo + Vo

o
e e
Co′ Co′

(a) (b) (c)

Figure 13. Charge-sensing stages insensitive to opamp offset-voltage and stray capacitances:
(a) Gregorian stage (2), (b) Maloberti stage (3), and (c) Nagaraj stage (4).
640 SUMMING CIRCUITS

solute value of the weighting coefficients: weight will be equal to 兹2 times the tolerance of the resis-
tors. This is a reasonable assumption when discrete compo-
Ci nents are being employed. However, when integrated circuits
Wi = (24)
Co are being formed, same-type components are fabricated si-
multaneously under extremely similar conditions; therefore,
which can be made highly independent of IC fabrication tech- appreciable correlation exists. In this case, the two error
nology variations. As seen from Eqs. (21) and (22), contribu- terms tend to cancel each other, and it is not rare to obtain
tions of either sign are possible, depending on the particular accuracies in the order of 0.1% with absolute value tolerances
switching configuration of the input branch. Note also that a of about 20%.
delay of T/2 exists for some of the input signals. The delay is
related to the sign of the weighting factor, in particular if the Active Element Offset Voltage. Mismatch among ideally
offset-insensitive branch is used. identical devices within active devices (opamps, current con-
The operational amplifiers in Figs. 12 and 13 can be re- veyors, OTAs) produce deviations in their performance as
placed by operational transconductance amplifiers whenever well. One of the most representative is the so-called input-
the SC circuit drives a capacitive load. This is in fact a com- referred offset voltage. Its effect can be analyzed using a ran-
mon practice in IC realizations, in which OTAs are usually dom-value dc (direct current) voltage source at one of the in-
advantageous in terms of area and power as compared to tra- put terminals. In analog summing structures, it produces at
ditional, low output-impedance opamps. the output an additional term that is independent of the input
signals (output offset). As an example, the analysis of the gen-
Advanced Considerations in the Design eral adder in Fig. 6 results in the following expression for its
of Analog Summing Circuits output voltage:
The discussion of the preceding circuits has been made, as  
usual, on the basis of idealized descriptions of circuit ele-

N

M

M
Vo = Wi+Vi − W j−V j− − 1+ W j− Eos (26)
ments: models. Practice, however, shows that real circuits op- i=1 j=1 j=1
eration is affected by several ‘‘second-order’’ effects. These in-
clude qualitative deviations of components behavior from where Eos is the opamp offset voltage.
their ideal model, systematic and random variations of elec-
trical parameters from their nominal values, additional para- Active Elements Dynamic Response. The dynamic response
sitic elements, and external interferences. Some of these error of active elements is reflected in the dynamic behavior of ana-
sources and their effects on analog summing circuits are de- log summing circuits. The corresponding analysis requires a
scribed next. dynamic model of the specific active device. We will consider
again the opamp-based generalized adder in Fig. 6 as an ex-
Element Tolerances. Electrical parameters of real circuit ample. Using a dominant-pole linear model for the opamp, we
components differ from their nominal values as a result of obtain the following expression:
unavoidable manufacturing process inaccuracies. Such devia-
 
tions are generally unpredictable and, therefore, commonly 1
N
M
+ − −
treated as statistical variables. In general, manufacturers Vo (s) =   Wi Vi (s) − W j V j (s) (27)
s
provide a tolerance range for representative parameters of 1+ i=1 j=1
electronic components. Typical discrete-component tolerances sp
are in the range of 1 to 20%.
Inaccuracies in component values result in deviations in where sp is the dominant pole of the summing circuit given by
circuit performances, which may be critical or not depending
−GB
on specific sensitivities and acceptability margins. sp =   (28)
Concerning analog summing circuits, element tolerances

M
−
1+ Wj
result in deviations from the desired weighting factors. In j=0
particular, we have seen that weighting factors are generally
given by parameter ratios of same-type elements. Using the and GB is the gain-bandwidth product of the opamp (see OP-
case of a resistor ratio Ro /Ri as an example, the actual weight ERATIONAL AMPLIFIERS).
value can be expressed as The application of a step voltage at one of the input signals
  will thus result in an exponential response characterized by

Ro
1+   a time constant
Ro +
Ro Ro 
 Ro 
∼ Ro
Ro
Ri
Wi = = = 1 + −  
Ri +
Ri Ri 
Ri  Ri Ro Ri

1+ −1 1 M
− 1
N
Ri τ= = 1+ Wj = Wi+ (29)
(25) sp GB j=0
GB i=0

Note that relative weight deviations are given by the differ-
ence of the relative error of the two resistors. Therefore, ex-
treme deviations may be as large as twice the tolerance of the
components (assumed equal for simplicity), but they can also
be extremely low. Assuming uncorrelated errors in the two
resistors, it is easy to show that the standard deviation of the
where we have used the design Eq. (7). Note that system re-
sponse-time increases with the sum of either positive or nega-
tive weights. This is a general statement valid for analog
summing circuits based on other active devices.
An important nonlinear limitation of operational amplifi-
ers, known as slew rate, establishes an upper bound for the
 SUMMING CIRCUITS 641

slope of the output voltage waveform. In cases where the lin- vices. Input (and output) impedance of active devices results
ear model predicts faster variations, the opamp will respond in uniform weight deviations. Opamp input bias-currents pro-
with a constant slope independent of the input signal. duce output offset, and finite power-supply rejection-ratio
(PSRR) and common-mode rejection-ratio (CMRR) result in
Finite Opamp Open-Loop Gain. Opamps finite low-fre- spurious components at the output signal due to power-sup-
quency gain A0 produces a uniform attenuation of summing- ply and common-mode signals coupling. High-order parasitic
circuit weight values. As an example, analysis of the general- dynamic effects of active devices could produce stability prob-
ized adder in Fig. 6 yields the following result: lems. Finally, electronic noise from active devices and resis-
tors may be relevant in certain applications cases.


N

M
Wi+Vi − W j− V j−
i=1 j=1 DIGITAL ADDERS
Vo =   (30)
1

M
1+ 1+ W j− Introduction
A0 j=0
Previous sections focused on analog summing circuits. Digital
adders operate with an essentially different codification of sig-
Finite Output Impedance of CCs and OTAs. When current nals and are, therefore, different from their analog counter-
conveyors or operational transconductance amplifiers are parts in practically every aspect.
used, their finite output impedance produces a result similar Digital addition follows strict algorithmic rules on abstract
to that of the finite open loop gain of operational amplifiers. numbers represented by a sequence of digits. In many senses,
An analysis of the generalized OTA-based adder in Fig. 11 the process is identical to ‘‘human’’ summation of magnitudes
results in represented by decimal (base 10) numbers. One major differ-
ence is the numerical base, which in the vast majority of digi-


N

M
tal systems is base 2. Numbers are therefore represented by
Wi+Vi − W j− V j−
i=1 j=1
strings of bits (i.e., digits), whose possible values are either 0
Vo =   (31) or 1. The most common form of representation of unsigned


N

M
1+α 1+ Wi+ + W j− numbers is binary magnitudes, which follows the same con-
i=1 j=1 ceptual rules as decimal representation. An additional differ-
ence is related to the representation of signed numbers. For
where 움 is the ratio of OTAs output-conductance to transcon- the purpose of arithmetic operations, the so-called two’s com-
ductance, which is assumed equal for every OTA for simplic- plement notation is the most widely used. Finally, an impor-
ity. This is indeed a correct assumption on most practical tant constraint on digital summing circuits is their fixed
cases. Similarly, the analysis of the generalized CC-based word-length, imposed by hardware realizations, which may
adder in Fig. 9(b) yields result in truncation or round-off errors depending on the rep-
resentation employed: fixed-point or floating-point (see DIGI-


N

M TAL ARITHMETIC). In what follows, fixed-point arithmetic is as-
Wi+Vi+ − W j−V j− sumed.
i=1 j=1
Vo = (32)
1 + Gp /GF Binary-Magnitudes Arithmetic
The addition of two (positive) binary magnitudes A and B can
where Gp is the output conductance of the CCs.
be performed following the same conceptual rules employed
in ‘‘hand’’ addition of decimal numbers. Fig. 14(a) illustrates
Parasitic Devices. Any real circuit includes, in addition to the procedure, beginning from the right-hand side column,
the devices employed to implement the desired function, which represents the least significative bit (LSB) and proceed-
many other unwanted "devices" such as wiring and contact ing toward the most significative bit (MSB) on the left-hand
resistances, self and mutual inductances among wires, capaci- side.
tive couplings, and transmission-lines. These parasitic ele- The sum of any pair of bits ai and bi, each with values 0 or
ments may become relevant in certain circumstances, like 1, ranges from 0 to 2 and must be represented by a two bits
high-frequency operation; in integrated circuit design; and, in number commonly denoted as (Ci⫹1 Si), as shown in Fig. 14(b).
general, whenever their electrical parameters are in the The sum-bit Si is already part of the result S ⫽ A ⫹ B,
range of nominal devices. In these cases, special circuit tech- whereas the carry-bit Ci⫹1 must be added to the next column.
niques and careful routing should be considered. Therefore, three bits must be added at each column i: ai, bi
and the carry-bit from the previous column Ci. The sum of
Feedthrough. In switched-capacitor circuits, the MOS tran- three bits ranges from 0 to 3 and can still be represented with
sistors employed as analog switches produce charge-injection a two-bits number (Ci⫹1 Si), as shown in Fig. 14(c). Thus, the
effects on the capacitors employed for charge storage. These process can start from the LSB column, for which C0 ⫽ 0 is
effects can be attenuated using small switches and large ca- assumed, and proceed toward the MSB in a repetitive man-
pacitors. ner. This procedure is the underlying fundamental of binary
digital adders.
Other Error Sources. Nonlinearity of passive and active ele-
ments produce distortion on the output signal. A clear exam- Basic Circuit Blocks. A digital circuit block realizing the
ple is the output voltage- and current-saturation of active de- truth table in Fig. 14(b) is commonly known as a half-adder
642 SUMMING CIRCUITS

ai ai
0 0 bi 0 0 01 11 10
0 1 1 Carry bi Ci
1 0 0 1 A 0 00 01 0 00 01 10 01
0 0 1 1 B
Figure 14. Examples of (a) binary addi- 1 01 10 1 01 10 11 10
tion process, (b) arithmetic addition of two 1 1 0 0 Sum
(Ci + 1 Si)2 = ai + bi (Ci + 1 Si)2 = ai + bi + Ci
bits, and (c) arithmetic addition of three
bits. (a) (b) (c)

(HA), whereas that defined by Fig. 14(c) is referred to as a
full-adder (FA). Fig. 15(a, b) contain representations for these
two basic building blocks of digital adders. Their implementa-
tion can be carried out following any general procedure for
Boolean functions realization.
The functionality of a HA can be expressed as two Boolean
functions:
SHA = ai · b i + ai · b i = ai ⊕ b i HA
Ci+1 = ai · b i
i
from which an implementation using two digital gates, an
XOR and an AND, is straightforward, as shown in Fig. 16.
Because the input-to-output signal path goes through just one
gate, the propagation delay of this realization corresponds to
one ‘‘gate level.’’
An FA can be implemented using two HAs and one OR
gate, as shown in Fig. 17(a). This realization requires a re-
duced number of gates but, on the other hand, exhibits a de-
lay of three gate levels. Other implementations can be built
on the basis of the Boolean expressions for the two outputs of
a FA,
Serial and Parallel Adders. The addition of two n-bit binary
numbers can be carried out serially or in parallel. A serial
adder, shown in Fig. 18, contains one single FA and a flip-
flop and is controlled by a clock signal. The two words A and
B are sequentially added on a bit-to-bit basis, beginning with
the LSB, for which the flip-flop must be initially set to zero.
Consecutive clock cycles produce consecutive bits of the re-
sulting sum S, as well as a carry-bit, which is stored in the
(33) flip-flop and employed as input to the FA in the next clock
cycle. The summation of the two words requires n clock cycles.
Therefore, serial adders constitute a slow solution in general.
On the other hand, they are highly efficient in terms of
hardware.
Parallel adders can be regarded as the opposite alterna-
tive, realizing fast additions at the expense of an increased
hardware cost. Figure 19 shows an intuitive realization of a
parallel adder, commonly known as serial-carry and also as
ripple adder. Its hardware cost is of n full adders. The carry-
bits are transmitted in a chain from the FA corresponding to
the LSB toward the MSB. This signal path determines the
response time of the parallel adder, which can be described
as

i = ai · bi · Ci + ai · bi · Ci + ai · bi · Ci + ai · bi · Ci
SFA
= ai ⊕ bi ⊕ Ci
FA
Ci+1 = ai · bi + bi · Ci + ai · Ci
Figure 17(b) shows an implementation using double-rail input
signals and two levels of NAND gates, and Fig. 17(c) shows
an implementation using single-rail signals using just two-
input NAND gates, with a propagation delay of six gate lev-
els. Many other alternatives exist.
A careful evaluation of these alternatives in terms of cost
and speed should take into account the diverse complexity
(transistor count) and propagation delay of different gates. In
general, NAND, NOR, and INV gates are faster and simpler,
whereas AND, OR, and especially XOR and NXOR gates are
more complex and slower. The requirement of double-rail in-
puts signals may result in additional cost and delay, de-
pending on the specific case.
tsp = ntFA (36)
(34)
where tFA is the response time of one FA. The response times
(35) of both the serial and the parallel adders are proportional to
the number of bits. However, because the period of the clock
signal employed in the serial adder must be at least several
times larger than tFA, it is clear that parallel adders are
faster. Still, parallel adders may be too slow for certain appli-
cations, especially for long digital words (large n). Certain ad-
vanced architectures overcome these problems at the expense
of additional hardware (see ‘‘High-Performance Digital
Adders’’).
Addition and Substraction of Signed Numbers
Addition-Substraction Equivalence. The addition and the
substraction of two signed numbers can both be formulated
on the basis of a summing operation, by simply changing the
sign of one of the operands when needed. Fig. 20 shows a
conceptual flow diagram of an adder/substracter circuit based

ai
ai Si Si
HA bi FA Ci + 1
bi Ci + 1 Ci + 1 ai
Ci
bi
(a) (b) Si

Figure 15. Basic digital-adder modules representation: (a) half

adder and (b) full adder. Figure 16. Half adder implementation.
 SUMMING CIRCUITS 643

ai
Si Si bi
HA HA Si Ci ai
i
Ci+1 Ci+1 ai bi
bi
i
Ci ai
Ci +1 Si Ci +1
ai Ci
bi
(a) bi
Ci
Ci
ai
bi
Ci
(b)
Ci

ai
Si
bi

Ci +1

(c)

Figure 17. Alternative implementations of a full adder: (a) with two HAs and one OR gate, (b)
with double-rail inputs and two levels of NAND gates, (c) with two-input NAND gates and six
levels of delay.

on this approach. Signal a/s controls whether the sign of op-
erand B is changed or not before the summation is performed.
The specific meaning of a sign-inversion operation depends
on the representation being used for the signed numbers, as
described in Fig. 20.
In a sign-magnitude (SM) representation, a sign inversion
is achieved by complementing just the sign bit, whereas the
rest of the bits remain unchanged. In one’s complement (C1)
arithmetic, a sign inversion is obtained complementing every
bit in the word. Finally, in two’s complement (C2) arithmetic,
a sign inversion requires adding one unit to the word obtained
by complementing every bit.
Signed-Numbers Addition in Two’s Complement Arithmetic. It
can be shown that the addition of signed numbers in two’s
complement representation coincides with the (positive) bi-
nary magnitude summation of their digital codes. Fig. 21
shows examples covering the four possible cases of operand
signs. The final (MSB) carry-bit Cn is neglected for the pur-
pose of evaluating the result. It may be used, however, to-
gether with Cn⫺1 to detect overflow. The possibility of using
simple binary adders, like those described previously, for the
summation of signed number has turned two’s complement
arithmetic the most widely used in digital operators, and the
only one considered in what follows.
Two’s Complement Adder-Subtracter Circuit. Figure 22(a)
describes a digital adder-subtracter, controlled by signal a/s,
following the diagram illustrated in Fig. 20. It is based on
a parallel binary-magnitude adder, and a parallel transfer/
complement (B/B) block. The realization and functionality of

. . . 0 1 1(0) C . . . 0, 1, 1, (0)
. . .1 0 0 1 A t Ci Si
+ . . . 1, 1, 0, 0
. . .0 0 1 1 B . . . 0, 0, 1, 1 FA
bi
Ci +1 D q
. . .1 1 0 0 S . . . 1, 0, 0, 1 ai
Figure 18. Serial adder and summation
. . . 0, 1, 1 example. t indicates increasing time se-
Ck quence.
644 SUMMING CIRCUITS

an –1 bn –1 Cn –1 a2 b2 C2 a1 b1 C1 a0 b0 C0 = Cin

FA FA FA FA
⋅⋅⋅⋅

Figure 19. Parallel adder with serial carry (ripple

adder). Cout = Cn Sn –1 C3 S2 C2 S1 C1 S0

A, B

a(0) s(1)
(a/s)
SM: yn – 1 = bn – 1; yi = bi, i = 0, 1, ..., n – 2
Y= B Y=–B C1: Y = C1(B); yi = bi, i = 0, 1, ..., n – 1
C2: Y = C2(B) = C1(B) + 1 = B + 1
Figure 20. Flow diagram of a signed-number adder/sub-
F = A +Y
tracter circuit.

A = 0100 B = 0010 A = 0010 B = 1100

Cn Cn – 1 0100 (+ 4) 0010 (+ 2)
0010 (+ 2) 1100 (– 4)
an – 1 an – 2 ... a1 a0
bn – 1 bn – 2 ... b1 b0 0110 (+ 6) 1110 (– 2)

Fn – 1 Fn – 2 ... F1 F0 A = 0100 B = 1110 A = 1100 B = 1110

11 11
F=A+B
0100 (+ 4) 1100 (– 4)
1110 (– 2) 1110 (– 2)

0010 (+ 2) 1010 (– 6)

Figure 21. Four possible cases of arithmetic addition of signed numbers addition in two’s com-
plement representation. The result is correct in every case after neglecting the carry bit.

n a/s

B/B circuit a/s Bn – 1 Bn – 2 B0

A

n n Y ⋅⋅⋅
Yn – 1 Yn – 2 Y0
Co Parallel adder [n] Ci a/s
a/s = 0 Y=B
a/s = 1 Y=B
n (b)

F
(a)

Figure 22. (a) Adder/subtracter circuit for signed numbers in two’s complement notation and
(b) transfer/complement (B/B) circuit.

this last circuit block is described in Fig. 22(b). If a/s ⫽ 0, the
B/B circuit simply transfers its input B to its output, and the
parallel adder, with the initial (LSB) carry-bit Ci set to 0, per-
forms the addition of the two operands A ⫹ B. The result is
correct for signed two’s complement numbers and also for bi-
nary magnitudes. On the other hand, if a/s ⫽ 1, the B/B cir-
cuit complements every bit bi of operand B and transmits the
result to the full adder, which now sees a 1 at Ci. The result
is that A is added with B ⫹ 1, that is, ⫺B in two’s complement
representation; therefore, the full adder produces the differ-
ence A ⫺ B as expected.
Overflow Problems
An n-bits binary magnitude may take values ranging from 0
to 2n ⫺ 1, and the sum of two such magnitudes from 0 to
2n⫹1 ⫺ 2. Similarly, the possible values of an n-bits signed-
number in two’s complement representation range from
⫺2n⫺1 to 2n⫺1 ⫺ 1, and the sum or difference of two such num-
bers from ⫺2n to 2n ⫺ 2. This means that the n-bits output of
the adder-subtracter circuit in Fig. 22 will be unable to show
the correct result in certain cases. This phenomenon is com-
monly known as overflow and is obviously something that
should be detected. Furthermore, it would be convenient to
determine the correct result also in these cases.
When unsigned binary magnitudes are being added, the
MSB carry-bit Cn provides a flag-signal for overflow occur-
rences. It can also be shown that function
V = Cn ⊕ Cn−1 (37)
which can be obtained at the expense of an additional XOR
gate, constitutes a valid overflow flag for the addition and the
subtraction of signed numbers in two’s complement represen-
tation. Both signals are active when high.
In the event of overflow, and regardless the operation be-
ing performed, the correct result can be obtained, in its proper
representation (binary magnitude or two’s complement), from
the n ⫹ 1 bits number compound by Cn (the new MSB or the
new sign bit) and the n-bits output-word of the circuit in
Fig. 22.
High-Performance Digital Adders
As in most digital processing circuits, the main concern in the
optimization of digital adders is to increase their operation
speed. Response time reductions can be achieved through im-
provements in the basic digital adder circuit block (the FA),
through algorithmic or architectural modifications, or a com-
bination of both. Parallel ripple adders are often used as a
reference for the evaluation of advanced solutions, which in
general focus on the elimination or at least the attenuation of
the constraint imposed by the long signal path of carry sig-
nals from the least to the most significative bit.
Most modifications to the conventional implementations of
the FA circuit block involve a reduction of the capacitive load
of the carry signal [e.g., the so-called mirror, dynamic, and
Manchester-adders (5)]. FA blocks with modified I/O signals
are employed in the carry-completion adder architecture (6),
yielding a reduced ‘‘average’’ response time.
Most architectural modifications rely on a segmentation of
the bit-chain in smaller groups. One alternative, known as
the carry-bypass adder (5), is based on evaluating within each
SUMMING CIRCUITS 645
group whether an eventual carry input Ci would propagate
through the group. If it does, Ci is directly transferred to the
carry output Co. Otherwise, Ci can be ignored, and Co is com-
puted from the group input bits. A similar strategy results in
the so-called carry-skip adder (6). An alternative architecture,
the linear carry-select adder (5), computes within each group
two results corresponding to the two possible values of Ci, and
selects one of them after receiving its actual Ci value. A modi-
fication of this last architecture, the square root carry-select
adder (5), employs increasing-length groups and results in a
propagation type proportional to the square root of the num-
ber of bits.
Carry look-ahead adders (6,7) employ a significative differ-
ent approach. Their architecture allows all carry-bits to be
obtained simultaneously at the expense of a rapidly increas-
ing complexity with the number of bits. In practice, this limits
the number of bits to about four, forcing the use of combined
approaches for larger word lengths.
Finally, a pipeline adder architecture (5) results in a high
summing throughput, although the propagation time of indi-
vidual summations may be larger than with the standard rip-
ple adder.
Other alternatives relying on innovative circuit techniques
(e.g., threshold gates, multivaluated-logic) or technologies
(e.g., optical processors) do exist, but they will not be treated
here.
BIBLIOGRAPHY
1. R. Unbehauen and A. Cichocki, MOS Switched-Capacitor and Con-
tinuous-Time Integrated Circuits and Systems, New York: Springer-
Verlag, 1989.
2. R. Gregorian and G. C. Teme, Analog MOS Integrated Circuits for
Signal Processing, New York: Wiley-Interscience, 1986.
3. F. Maloberti, Switched-capacitor building blocks for analogue sig-
nal processing, Electronics Lett., 19: 263–265. 1983.
4. K. Nagaraj et al., Reduction of finite-gain effect in switched-capaci-
tor circuits, Electron. Lett., 21: 644–645, 1985.
5. Jan M. Rabaey, Digital Integrated Circuit: A Design Perspective,
Upper Saddle River, NJ: Prentice-Hall, 1996.
6. Amos R. Omondi, Computer Arithmetic Systems. Algorithms, Archi-
tectures and Implementations, Upper Saddle River, NJ: Prentice-
Hall, 1994.
7. N. Weste and K. Eshraghian, Principles of CMOS VLSI Design. A
Systems Perspective, Reading, MA: Addison-Wesley, 1985.
RAFAEL DOMÍNGUEZ-CASTRO
SERVANDO ESPEJO
ANGEL RODRÍGUEZ-VÁZQUEZ
CARMEN BAENA
MANUEL VALENCIA
University of Seville, IMSE-CNM-
CSIC
SUNPHOTOMETERS. See PHOTOMETERS.
SUPERCAPACITORS. See CAPACITOR STORAGE.
SUPERCONDUCTING ANALOG AND DIGITAL MI-
CROWAVE COMPONENTS. See SUPERCONDUCTING
MICROWAVE TECHNOLOGY.
 SWITCHED CAPACITOR NETWORKS 165

SWITCHED CAPACITOR NETWORKS

The requirement for fully integrated analog circuits prompted

circuit designers two decades ago to explore alternatives to
conventional discrete component circuits. A sound alternative
was developed, a switched-capacitor (SC). The basic idea was
replacing a resistor by a switched-capacitor CR simulating a
resistor. Thus, this equivalent resistor could be implemented
with a capacitor and two switches operating with a two-phase
clock. This equivalent resistor is equal to 1/f CCR, where f C is
the sampling (clock) frequency. SC circuits consist of
switches, capacitors, and operational amplifiers (op amps).
They are described by difference equations in contrast to dif-
ferential equations for continuous-time circuits. Concurrently

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.
166 SWITCHED CAPACITOR NETWORKS

the mathematical operator to handle sample-data systems, approach. Furthermore, many practical analog/digital
such as switched-capacitor circuits is the z-transform, and the (A/D) converters use SC implementations.
Laplace transform for continuous-time circuits. A host of
practical properties of SC circuits have made them very popu-
FUNDAMENTAL BUILDING BLOCKS
lar in industry:

1. The time constants (RC products) from active-RC cir- The fundamental building blocks in SC circuits are voltage-
cuits become capacitor ratios multiplied by the clock pe- gain amplifiers, sample/holds integrators, and multipliers. A
riod TC, that is, combination of these blocks is interconnected to yield a num-
ber of useful circuits.


1 C C
τ= = TC (1a) Gain Amplifiers
fC CR CR
The gain amplifier is a fundamental building block in
where T ⫽ Tc ⫽ 1/f C is the sampling frequency. The switched-capacitor circuits. A voltage amplifier is imple-
accuracy of ␶ is expressed as mented as shown in Fig. 1(a). The switched-capacitor resistor
dτ dTC dC dCR gives a dc path for leakage current but reduces further the
= + − (1b) low-frequency gain. A detailed analysis of this topology shows
τ TC C CR
that the dc output voltage is equal to ⫺Ileak T/CP, with CP the
parasitic capacitor associated with the feedback path. The
Assuming that TC is perfectly accurate gives
leakage current Ileak in switched-capacitor circuits is a result
dτ dC dCR of the diodes associated with the bottom plate of the capaci-
= − (1c) tors and the switches (drain and source junctions). This leak-
τ C CR
age current is about 1 nA/cm2. Using typical analytical meth-
ods for switched-capacitor networks, it can be shown that the
Because the two capacitors C and CR are built close to-
z-domain transfer function of this topology becomes
gether, d␶ / ␶ compatible with conventional CMOS tech-
nologies is in the neighborhood of 0.1%.
V0 (z) ∼ CS 1 − z−1
2. Ordinarily the load of an SC circuit is mainly capaci- H(z) = =−  
Vi (z) CI 1 − 1 − C P z−1
tive. Therefore the required low-impedance output- C I (2)
stage op amp is no longer required. This allows the use C z−1
of a single-stage operational transconductance amplifier =− S
CI z − (1 − CP /CI )
(OTA) which is especially useful in high-speed applica-
tions. Op amp and OTA are not differentiated in the
with z ⫽ ej2앟fT. For low frequencies, z 앒 1, the transfer function
rest of this article.
is very small, and only for higher frequencies does the circuit
3. Reduced silicon area, because the equivalent of large re- behave as a voltage amplifier.
sistors is simulated by small capacitors. Moreover, posi- A practical version is shown in Fig. 1(b). During ⌽2, the op
tive and/or negative equivalent resistors are easily im- amp output voltage is equal to the previous voltage plus the
plemented with SC techniques. op amp offset voltage plus V0 /AV, where AV is the open-loop dc
4. Switched-capacitor circuits are implemented in a digital gain of the op amp. In this clock phase, both capacitors, CI
circuit process technology. Thus, useful mixed-mode sig- and CS, are charged to the voltage at the inverting terminal
nal circuits are economically realized in standard MOS of the op amp. This voltage is approximately equal to the op
technology with available double-poly. amp offset voltage plus V0 /AV. During the next clock phase,
5. The SC design technique has matured. In the audio the sampling capacitor is charged to CS(VI ⫺ V⫺), but because
range, SC design techniques are the dominant design it was precharged to ⫺CSV⫺, the injected charge to CI is equal

φ1 φ2 Cl φ1
Cp
φ2

φ2 CH

Cs Cl
Vi φ1
–
Vo Vi φ1 Cs
+ –
Vo
φ2 +

Cspike
Figure 1. Voltage gain amplifiers: (a)
with dc feedback; (b) available during both
clock phases. (a) (b)
 SWITCHED CAPACITOR NETWORKS 167

simplicity and potential speed. It is often convenient to add

– input buffer, the on-resistance of the switch, and the value of
Vin φ1
+ the settling behavior of the buffer. A drawback of this archi-
CH
(a)
φ2 φ1
Time (T)
(n–1) (n–1/2) n switches associated with ␾1⬘ and ␾1 turn off one after the
(b)
Figure 2. Open-loop S/H: (a) simple S/H buffer; (b) timing diagram.
to CSVI. As a result of this, the op amp output voltage is equal
to ⫺(CI /CS)VI. Therefore, this topology has low sensitivity to
the op amp offset voltage and to the op amp finite DC gain. A
minor drawback of this topology is that the op amp stays in
the open loop during the nonoverlapping phase transitions,
producing spikes during these time intervals. A solution for
this is to connect a small capacitor between the op amp out-
put and the left-hand plate of CS.
Sample-and-Hold
The function of a sample/hold (S/H) is to transform a continu-
ous-time signal into a discrete-time version. A simple S/H cir-
cuit is shown in Fig. 2(a). Its clock phases are shown in Fig.
2(b). This open-loop architecture is attractive because of its
an input buffer stage to the S/H circuit. The acquisition time
depends on the tracking speed and input impedance of the
the holding capacitor. The hold settling time is governed by
tecture is the linearity requirements imposed on the buffers
as a consequence. This limits the speed. Moreover, the input-
dependent charge injected by the sampling switch onto the
hold capacitor yields an undesirable source of nonlinearity.
This type of S/H architecture achieves a linearity to nearly 8
bits. A full-period S/H signal is obtained by either a cascade
of two S/H circuits of Fig. 2, driven by opposite clock phases,
or by a parallel connection of two simple S/H circuits, output
sampling switches, and a third (output) buffer as illustrated
in Fig. 3. Structures with closed-loop connections are also
used. Figure 4(a) illustrates a popular architecture often en-
countered in pipelined A/D converters. In the acquisition
mode, switches associated with ␾1 and ␾1⬘ are on whereas ␾2
is off, and the transconductance amplifier acts as a unity-gain
amplifier. Thus the voltage across CH is the input voltage and
the virtual ground. In the transition to the hold mode, the
other. Then ␾2 turns on. One advantage of this architecture
is that because ␾1⬘ turns off first, the input-dependent charge
injected by ␾1 onto CH does not appear in the held output volt-
age. Besides, because of the virtual ground, the channel
charge associated with ␾1⬘ does not depend on the input signal.
Yet another advantage is that the offset voltage is not added
to the output. A disadvantage is that a high-slew-rate trans-
conductance amplifier is required. Figure 4(b) shows a double-
sampling S/H circuit. The S/H operation is valid for both
clock phases.
Multipliers
One difficulty in an SC multiplication technique is that con-
tinuous programmability or multiplication of two signals is
not available. A digitally programmable coefficient is realized
with a capacitor bank, as shown in Fig. 5. The resolution of
this technique is limited because the capacitor size increases
by 2k where k is the number of programming bits.

– φ2
φ1
+

–
C1
V0
+

Vin
CH

– φ1
φ2
+

C2
Figure 3. Double-sampling S/H archi-
tecture.
168 SWITCHED CAPACITOR NETWORKS
φ2
φ 1'
Vin φ1
– Vin
Gm
CH
+
(a)
Figure 4. (a) SC S/H single-ended. (b) Double-sampling S/H.
When continuous programmability is required, a continu-
ous multiplier is used. Despite many reported multiplier cir-
cuits, only two cancellation methods for four-quadrant multi-
plication are known. Because a single-ended configuration
does not completely cancel nonlinearity and has poor PSRR,
a fully differential configuration is often necessary in a sound
multiplier topology. The multiplier has two inputs. Therefore
there are four combinations of two differential signals, that
is (x, y), (⫺x, y), (⫺x, ⫺y), and (x, ⫺y). The multiplication and
cancellation of an unwanted component are achieved by ei-
ther of the following two equalities:
4xy = [(X + x)(Y + y) + (X − x)(Y − y)]
− [(X − x)(Y + y) + (X + x)(Y − y)]
or
8xy ={[(X + x) + (Y + y)] + [(X − x) + (Y − y)] }
2 2
− {[(X − x) + (Y + y)]2 + [(X + x) + (Y − y)]2 }
C weighted integrator. The output of the multiplier is a voltage
2 1C
2 2C
2 kC
Figure 5. Digitally programmable capacitor bank.
CH
φ2
φ1 φ2
φ1
φ2
V0
–
+
V0
φ1 φ1
φ2
(b)
These two approaches are depicted in Fig. 6. The topology of
Fig. 6(a) is based on two-quadrant multipliers. Fig. 6(b) is
based on square law devices. X and Y are arbitrary constant
terms and are not shown in Fig. 6.
MOS transistors are used to implement these cancellation
schemes. Let us consider a simple MOS transistor model
characterized in its linear and saturation regions, respec-
tively by the following equations:


V
Id = K Vgs − VT − ds Vds
2
for |Vgs | > |VT |, |Vds | < |Vgs − VT | (4a)
(3a) K
Id = (Vgs − VT )2 for |Vgs | > |VT |, |Vds | > |Vgs − VT | (4b)
2
where K ⫽ 애oCox W/L and VT are the conventional notations
for the transconductance parameter and the threshold voltage
of the MOS transistor, respectively. The terms VgsVds in Eq.
(3b) (4a) or Vgs2
in Eq. (4b) are used to implement Eqs. (3a) and
(3b), respectively. Next we discuss a sound combination of a
continuous-time multiplier and an SC integrator. In an SC
circuit, the multiplier precedes the integrator, thus forming a
signal or a current signal. In the case of a voltage-mode multi-
plier, the configuration of the SC integrator is identical with
a conventional integrator, as shown in Fig. 7. The transcon-
ductance multiplier is connected directly to the op amp, as
shown in Fig. 8. A common drawback in a weighted integrator
is the multiplier offset because it is accumulated in the inte-
grator. This problem is more serious for the transconduc-
tance mode.
The topology in Fig. 8 with the multiplier implemented by
a FET transistor operating in the linear region is known as
MOSFET-C implementation. Instead of using a single tran-
sistor, a linearizing scheme uses four transistors as shown in
Fig. 9.
The four FETs in Fig. 9(a) are operating in the linear re-
gion, and depletion FETs are often used in many cases to
 SWITCHED CAPACITOR NETWORKS 169

xy x2 + 2xy + y2
Σ x+y ( )2 Σ
+ +
x – xy x2 – 2xy + y2
–x + y ( )2
–y 4xy 8xy
xy x2 + 2xy + y2
–x – y ( )2
–x – xy –
Σ x2 – 2xy + y2 –
x–y ( )2 Σ
y Figure 6. Four-quadrant multiplier topol-
ogies: (a) using single-quadrant multipli-
(a) (b) ers; (b) Using square devices.

overcome the transistor threshold limit. The drain current of Several modifications are possible from this prototype. In
each FET is given by the balanced differential op amp, the drain voltage vd is virtu-

 ally grounded because the common-mode voltage is fixed to
v+ − v+ ground. In this case, only two FETs are required, as shown in
id1 = K v+ +
(v+ +
x
y − vx − VT − d − vx )
d
2 Fig. 9(b). The drain current of each FET is given by


v− − v+

id2 = K v− +
(v− +
x
− v − V − d
d − vx )
−vx
y x T
2 id1 = K v−