Layout Design Entry, Verification, and Automation User Guide

Layout Design Entry,
Verification, and Automation

User Guide
Page 2 last modified 6/27/05
Table Of Contents
Layout Design Entry,

Verification, and Automation
User Guide 1
Chapter 1 Overview of the Layout Design Flow 4
Overview of the Design Flow 4
Generate Layout 5
Check Nets and Pins 7
DRC 7
LVS 8
Netlist and Simulate 8
Chapter 2 Virtuoso 10
Suggested Settings 10
The Device Library 11
display.drf 12
SDL 12
Pins/Labels from Schematic 13
Iterated Pin Creation 16
Iterated Selection 18
Place Bus 22
Pin Check and Fix 24
Leadframe Tool 27
Chapter 3 Design Entry Layers 28
Opus 4.4 Layer List 28
Pins 35
Net Labels 36
Resistor 37
Fuse 37
Short 38
Options 38
Mask Layers 39
BJT Devices 41
Special Areaid Layers 42
Unusual Transistors 43
Boundary Layers 44
Chapter 4 Created Layers 45
Overview 45
Modifying Created Layers Directly 46
Created Layers Algorithms 47
Waffling procedure 51
Chapter 5 VCR User’s Guide 54
Introduction 54
VCR Design Flow 59
Prepare design for Translation 60
Translate from Virtuoso to VCR 62
VCR data structure 66
VCR environment 69
Placement Mode 73
Interactive Routing Mode 78
Set Rules For Auto-Route 88
Advanced Rule Setting 95
Auto-router 109
Using VCR reports to check routing results 117
Introduction to Cadence Chip Assembly Router 122
Save Result and Translate back to Virtuoso 127
Further Reading 130
Chapter 6 Calibre 131
Page 4 last modified 6/27/05 Overview of the Layout Design Flow
Chapter 1: Overview of the Layout Design Flow
This chapter provides an overview of the layout entry design flow. This chapter does not provide
details on how tools work, only a high level ordering of tasks and a description of each task. At any
point, if a problem is detected, it means going all the way back to the generate layout step and re-
quires running every subsequent step after any change to the layout.
Each of these chapters has a more detailed breakdown in a subsequent chapter.
Section 1: Overview of the Design Flow
Layout design is the process of creating an electrically equivalent, physical, transistor level repre-
sentation of a circuit. Generally, a schematic must exist for each layout and vice versa. In some
cases, however, a layout may have more or less hierarchy than its corresponding schematic. Fol-
lowing is the flowchart for the layout design flow.
Figure 1.1.1: Layout Design Flowchart
Generate
Circuit Design
Layout Bad LVS
Go Back To
Check Nets Netlist Layout
& Pins for Hspice
Bad
DRC Simulate Extremely

Bad
Created Layer Move On to the

DRCs Parent Cell
Section 2: Generate Layout
In its simplest form, layout creation involves editing polygons which form devices and routing.
This is called full custom layout, where every polygon is hand edited to minimize size and maxi-
mize speed.
There are a number of tools which speed layout creation by using information in the schematic and
by using layout pcells. The Cypress design flow supports a number of layout methodologies rang-
ing from full custom to standard cell place and route.
Table 1.2.1: Layout Automation Tools
Tool Name Description
Pins/Labels from Sch... Speeds pin placement in the layout.

Pin Check and Fix Allows modifying pin shapes, fixing nets, deletion of unused pins
Place Bus Interactively draws a bus on grid.
Iterated Pin Creation Speeds pitch matched pin placement.
Iterated Selection Allows selection of regularly placed objects in a layout
Schematic Driven Layout Speeds creation of layout by placing layout building blocks in the
(SDL) layout. The user must arrange these blocks manually and then
route them together.
ICcraftsman Used to route together user blocks. Works well with SDL and can
be used for top level chip routing. Can be used in an interactive or
automatic mode.
Silicon Ensemble Automatically generates a layout from a schematic using fixed
standard cells with a place and route algorithm. Handles much
larger circuits than LAS but with reduced efficiency. This is nor-
mally used in a logic engine design flow.
IP Library Borrowing The fastest way to enter a layout is to borrow it from someone else.
Section 3: Check Nets and Pins
In the Layout Editor, the program Pin Check and Fix is available from the Cypress pulldown menu.
This program should be run on all full custom layout blocks to verify that the pins are formed well.
Also, from the symbol editor, there is a cross view check utility which will verify that the terminals
of various views match. By default, the layout is not included in this list. It is often useful to add
the layout to this list where the terminals in the layout are important.
Section 4: DRC
Each technology has a TDR spec (Technology Design Rules). This spec is verified through a De-
sign Rule Check rules file.
It is recommended to run DRC after each layout cellview is created. This allows a designer to deal
with errors early in the design.
It is required to run DRC on the full chip layout before tapeout. Errors must be either fixed or
signed off.
Created Layers DRC must also be run for the full chip. This is largely the same as DRC, but it in-
volves generating created layers first and then verifying the created layers for errors. This is not
normally run for each cellview, but is required to be run at block level before the block is consid-
ered clean.
Section 5: LVS
LVS is a check which verifies the Layout Versus the Schematic. It extracts devices and nets in the
layout and compares them to the schematic to ensure that the same number of devices exist, the
same number of nets exist, and the connectivity of the devices and nets are identical, and the de-
vices themselves are identical.
This check is required for the top level layout and schematic of a chip before tapeout.
After verilog netlisting and clean LVS, you can run fuseGen to dump a fuse table. Then use fuseapp
to perform ad-hoc queries and to program fuses specified by location or name or description match-
ing.
Section 6: Netlist and Simulate
The backend simulation flow is undergoing a lot of work. There are two basic models currently
supported. Either way, Vampire is used to generate an Hspice netlist of a layout.
❒ Extract key leaf cells for a hand built critical path Hspice simulation.
The netlist is used as part of a simulation schematic which models a specific critical path with great
accuracy. Hspice cannot handle a full chip simulation, but a simulation schematic can be built
which includes extracted hspice netlists for critical path simulations.
❒ Extract the full chip for a Timemill simulation.
In this methodology, the full chip is verified for functionality and speed, but Timemill is not as ac-
curate as Hspice. In areas where Timemill says the chip is very close to its spec, Hspice should be
used to obtain a more accurate measurement to make sure the chip is within spec.
Page 10 last modified 6/27/05 Virtuoso
Chapter 2: Virtuoso
Virtuoso is the name of the Cadence Layout Editor. This editor is documented in Cadence open-
book. This chapter provides:
• provides a quick overview of differences between Opus 4.3.4 and Opus 4.4
• highlights Cypress customizations to Virtuoso
Section 1: Suggested Settings
There are a few settings which many users will want to put in their .cdsenv file.
By default, pin names in a layout are hidden. This tells opus to show them.
layout displayPinNames boolean t
These two lines set the snap spacing in the layout. This can vary from one technology to another.
If geometries are placed off grid, DRC will generate errors.
layout ySnapSpacing float 0.025
layout xSnapSpacing float 0.025
In order to select the edge of a geometry or a set of geometries to stretch them, this option must be
set.
layout partialSelect boolean t
This option enables the infix user entry mode. With this mode of operation, whenever possible, Ca-
dence will use the mouse location when a command is executed as the first entry point.
ui infix boolean t
Section 2: The Device Library
Creation of the device library and a detailed description of how technology information is managed
is found in Chapter 11 of the Design Management User Guide.
The device library is used by layout automation tools to create a symbolic layout. The device li-
brary is also used by designers directly to speed the creation of often used devices.
The device library is broken into the following categories:
Capacitors Contains the poly capacitor devices.
Contacts Contains various contact structures.
LAS Contains pcells which LAS uses. These are not meant to be placed
by a user.
Misc Contains various pcells such as the metop, short, die seal ring, and
pad.
Pins Contains symbolic pins. These are normally only used by layout au-
tomation tools.
Resistors Contains the resistor devices.
SD Contains special contact structures meant to be used as transistor
source or drain regions.
Transistors Contains the transistor pcells.
Unknown Contains additional pcells which could not be categorized.
Unsupported Contains pcells which are used by other pcells, and are not meant to
be placed by a user.
Section 3: display.drf
In Opus 4.4, the color patterns used to represent layers on the screen are separate from the techfile.
They are stored in a Display Resource File (DRF). This file is user customizable. The default file
is stored in $DESIGN/config/cydir/v/4.4/etc/display.drf. This file can be copied to a user’s home
directory and modified. In order to override the CAD supplied default, the user’s display.drf file
must either be in his home directory or in the directory from which he starts Cadence.
Section 4: SDL
Schematic Driven Layout (SDL) is a collection of programs designed to aid custom layout at both
the device level and the block level. The program collection enables the following utilities and their
functions, within the Cypress menu of Virtuoso.
Table 2.4.1: SDL Utilities
SDL Utilities Function

Schematic to Layout Places devices in layout for each instance in the schematic
Cross-Probe Maps elements from Schematic to Layout for comparative purposes
Placement Optimizes device placement in layout
Select Net Instances Part of the Cross Probe Utility, enumerates a list of nets to be selected
for comparative purposes
Select Instances Part of the Cross Probe Utility, enumerates a list of instances to be
selected for comparative purposes
SDL has the following capabilities.

• Automatically places size correct devices in the layout based on the hierarchical schematic, the
Device Library, and the user’s own completed layout cells or layout abstracts.
• Adds net connectivity to the layout allowing Cadence’s ICCraftsman to be used for device and
block level routing.
• Provides cross probing between the schematic and the layout.
• Provides flight lines within the layout.
• Checks for differences in number and size of devices between layout and schematic.
• Aids in folding transistors, merging transistors in series and in parallel, and setting the contacts
on the transistors based on the transistor’s connections.
• Aids in the addition of isolation devices in both the layout and schematic.
This tool is fully documented in the Layout and Verification reference manual.
Section 5: Pins/Labels from Schematic
❒ Overview
Pins/Labels from Schematic allows the user to quickly list all the pins found in a schematic cell
view, and then create and place these pins into a corresponding layout.
It utilizes the SKILL program P2L to open the schematic and build a list of pins that exist in the
schematic but do not exist in the layout. It then allows the user to create these pins in the layout
interactively.
The Pins/Labels from Schematic tool is used by choosing “Pins/Labels from Schematic” from the
Cypress menu bar within the Virtuoso layout editor.
Once started, the tool will synchronize the layout with the corresponding schematic whose pins
will be created, and then pin creation and placement proceeds interactively.
This tool is fully documented in the Layout and Verification Reference Manual.
❒ Example
We will place schematic pins and their labels into a corresponding layout.
Step 1: Run Pins/Labels from Schematic from the Cypress menu bar in Virtuoso, to start the pin
label placement process.
Figure 2.5.1: Pins/Labels from Schematic from Cypress Menu
When launched, the user will first verify the schematic cellname to use, then P2L synchronizes the
layout with this corresponding schematic. The P2L main form will pop-up listing in the Pin Name
field the pins to be placed.
Step 2: For this example, rail pins (vgnd and vpwr) will be placed using the metal-1 pin layer by
selecting the met1 layer in the Pin Layer field. Fill in the pop-up form as shown in Figure 1.5.2.
Figure 2.5.2: P2L Main form to Place Rail Pins
Step 3: Once the first pin in the list (vgnd) is located in layout, draw a shape at its layout locale to
place the pin with its pin label. (Note: Locating pins is aided by the SDL utility Cross-Probe).
Figure 2.5.3: Drawing Placement Shape and Final Pin Placement of Pin
Step 4: Pin vpwr is placed in the same manner, and its placement completes the process.
Section 6: Iterated Pin Creation
❒ Overview
Many Cypress layouts are pitch matched against a memory core and are therefore very regular. The
Iterated Pin Creation tool is designed to make pin modifications to a regular structure easier.
Iterated Pin Creation Tool is a SKILL program used to create regularly placed pins in a layout. The
tool will find pins in a schematic cell view and then allow the user to quickly generate those pins
in an iterative fashion into a corresponding layout.
The Iterated Pin Creation tool is used by choosing “Iterated Pin Creation” from the Cypress menu
bar within the Virtuoso layout editor. Once started, the tools GUI form pops up and the tool is driv-
en interactively.
The tool is fully documented in the Layout and Verification Reference Manual.
❒ Example
We have a layout that we need to add/create multiple pins. For this example, the pins are metal-1
input pins (row0, row1, row2, row3) that will placed vertical along a block.
Step 1: Run Iterated Pin Creation from the Cypress menu bar in Virtuoso, to create the above input
pins.
Figure 2.6.1: Iterated Pin Creation from Cypress Menu
Step 2: Within the Iterated Pin Creation Form, set the Pin Expression field with inputs row0-
row3 and choose the options to create pins on metal-1 pin layer, with centered labels, and a Yoffset
of 2 pin spacings. (Note: the ‘|’ character prefixes the directional specifier “input”)
Figure 2.6.2: Iterated Pin Creation Form

Step 3: Once the form is applied, input pins are created and placed in the layout with equal spacing.
Figure 2.6.3: Row Pins Iteratively Created and Placed
Section 7: Iterated Selection
❒ Overview
Like the Iterated Pin Creation tool, Iterated Selection is also designed to make modifying regular
structures easier. The Iterated Selection Tool is a SKILL program used to select regularly placed
objects in a layout. The tool is fully documented in the Layout and Verification Reference Manual.
❒ Example
You want to select all objects except rectangles in a specified area of a layout. You will use Iterated
Selection and a SKILL routine you’ve created that defines object selection.
Step 1: Run Iterated Selection from the Cypress menu bar in Virtuoso, to bring up the Iterated Se-
lection Form for the selection process.
Figure 2.7.1: Iterated Selection from Cypress Menu
Step 2: Next, (or prior to invoking the tool) load your SKILL routine within the CIW window (for
this example “YourSKILLSelection” file).
load “YourSKILLSelection”
The SKILL file “YourSKILLSelection” defines what objects will not be selected (rectangle ob-
jects). This file is shown below.
(defun YourSKILLSelection(arg “l”)

(let ((iteration (car arg))
(shapes (cadr arg))
)
(foreach shape shapes
(when
(equal shape~>objType “rect”)
(geDeselectFig shape)
)
)
)
)
Step 3: The selected area will be set to an area of a single NAND block in the layout. This area
will be iterated 3 times to allow a selection area that will capture (horizontally) all objects except
rectangle objects (those of type “rect”). Within the Iterated Selection form, all fields are set by the
user to achieve this selection.
Figure 2.7.2: Iterated Selection Form with SKILL Routine and Selection Area
Step 4: Once the form is applied, objects (except rectangles) in the selected area will be highlighted
within the layout. For this example, all objects (except rectangles) within the horizontal area of the
first 3 NAND blocks are selected (highlighted). The “vgnd” label is not fully within the selected
area, and thus is not selected.
Figure 2.7.3: Objects Captured with Iterated Selection

Section 8: Place Bus
❒ Overview
Place Bus allows the user to quickly generate layout routes with various options for routing layers,
number of routes, and their sizings.
The tool utilizes the SKILL program placeBus to provide an interactive layout routing aid. It is ca-
pable of creating a route consisting of multiple signals and with various layer and sizing options.
The tool and is used interactively, and can be run with or without the use of its pop-up GUI form.
Key features include:

• The route can change layers in mid route (three layer contacts are not supported). The previous
and next routing segments around the layer change must be manhattan route segments.
• The signal order can be switched in a 90 degree manhattan corner where a layer change is
made.
• Layer width, spacings, numbers of contacts, and contact grid configuration is all user con-
trolled.
• Routes can be drawn with a left justification, right justification, or center justification.
• Everything is drawn on grid.
The Place Bus tool is used by choosing “Place Bus” from the Cypress menu bar within the Virtuoso
layout editor.
Once started, the tool will prompt the user to start a path for the route, and routing then proceeds
interactively. By default it will use the current entry layer selected in the LSW. The GUI form is
accessed from the F3 key to allow option changes while routing.
❒ Example
Creating a basic metal-2 route within a layout

Step 1: Run Place Bus from the Cypress menu bar in Virtuoso to begin the routing process.
Figure 2.8.1: Place Bus from the Cypress Menu
Step 2: The default routing layer used, is the current entry layer selected in the LSW. For this ex-
ample, you should select metal-2 (dg) in the LSW layer palette.
Place Bus will prompt you in the Virtuoso window, to begin a path for the desired route. By default
the placeBus form does not pop-up, however it is accessible by using the F3 key to bring up the
placeBus form for changes during routing.
Step 3: Use the mouse to begin the route (by default the route is centered at the mouse point). Click
once to change direction and establish the path drawn so far. Double click completes your route.
Figure 2.8.2: Initial “Rubberband” Routing Segment and Continued Horizontal Routing
Section 9: Pin Check and Fix
❒ Overview
Pin Check and Fix is a tool used to check a layout for pin related errors. It builds an internal lookup
table of these errors and then allows the user to select or fix them.
Pin Check and Fix utilizes the SKILL program PINfixTool to search the current layout cell view
for any pin errors and allow the user options to select those errors for easy identification. The tool
also offers options to fix the specific pin errors it has found.
The Pin Check and Fix tool is used by choosing “Pin Check and Fix” from the Cypress menu bar
within the Virtuoso layout editor.
Once started, the tool GUI form will pop up. With nothing selected the tool will simply check the
layout for any pin errors and return any error messages within the CIW window. Further identifi-
cation and correction of any errors found, can be done by selecting options within the GUI form.
❒ Example
You have created or placed pins within your layout, and proceed to check for any pin errors.
Step 1: Run Pin Check and Fix from the Cypress menu bar in Virtuoso, to check pins in the layout.
Figure 2.9.1: Pin Check and Fix from Cypress Menu

Step 2: The PINfixTool Main Form appears, and you press OK with nothing selected to check the
layout. Within CIW, PINfixTool returns the single warning:
“PINcheck: The following pin shapes are used as a pin but are not drawn in a layer whose purpose
is "pin" ("rosc_h")”
Step 3: You run Pin Check and Fix again and select the Pin shapes used as a pin but not
drawn on a pin layer option, then press OK. This will identify the pin by highlighting it in lay-
out.
Figure 2.9.2: PINfixTool GUI Form with a selected set
Step 4: Pin Check and Fix returns the selected set highlighted in the layout to help distinguish it
from other pins shapes. The PINcheck warning is also given in CIW. After inspecting the pin, you
change the current layer [li drawing (dg)] to the proper pin layer [ li pin purpose (pn)].
Figure 2.9.3: Pin Highlighted with “li” (dg) layer and Corrected Pin with “li” (pn) layer
Step 5: Re-run Pin Check and Fix and view the CIW for any remaining errors. When there are no
errors PINfixTool returns the following message in CIW: “PINfixTool: everything checks out OK”
Section 10: Leadframe Tool
Leadframe matching tool (LMT) is a C program used to programmatically search for the appropri-
ate leadframes given a set of criteria. After the matching leadframes are found, the user is also able
to select certain leadframe(s) to view or stream in to the designated Opus library.
Page 28 last modified 6/27/05 Design Entry Layers
Chapter 3: Design Entry Layers
This chapter lists all Opus 4.4 layers, describes how each layer is to be used, and provides some
examples of how layers are used to extract devices and nets.
Section 1: Opus 4.4 Layer List
Table 3.1.1 shows the layers in V4.4 added by CAD with a description of what that layer is used
for. Table 3.1.2 shows purposes in V4.4 added by CAD with a description of what the purpose is
used for. The abbreviations for purposes in the LSW are the Cadence default, which uses the first
and last letter of the purpose name. Neither default Cadence layers nor purposes are not shown
here. Cadence reserved layers and purposes can be found in Cadence openbook under Custom IC
Layout -> Technology File -> Technology File and Display Resource File User Guide, Appendix
A.
Table 3.1.1: Layer List in V4.4
Layer Layer
Description
Name Number
nwell 0 Drawing layer for N- Doped well
pwell 1 Drawing layer for P- Doped well
diff 2 Drawing layer for diffusion (N+ or P+ depending on context)
tap 3 Drawing layer for tap (N+ or P+ depending on context)
poly 4 Drawing layer for gate poly
mcon 5 Contact from metal1 to a lower level
Layer Layer
Description
Name Number
met1 6 First layer of metal routing
via 7 Contact from first layer of metal to the second layer of metal.
met2 8 Second layer of metal routing
via2 9 Contact from second layer of metal to the third layer of metal.
met3 10 Third layer of metal routing.
pad 11 Drawing layer to identify chip pads
via3 12 Contact from third layer of metal to the fourth layer of metal.
met4 13 Fourth layer of metal routing
via4 14 Contact from fourth layer of metal to the fifth layer of metal.
met5 15 Fifth layer of metal routing
fpcon 16 Prom26 and NV40 related layer
fpoly 17 Famos device poly
array 18 Prom Related
pwpm 19 Pwell Protect Mask used in high voltage transistors
dimp 20 Depletion Implant. Used to make Depletion devices
pimp 21 Programmed implant layer
li1 22 Local interconnect routing layer.
dnwell 23 Deep Nwell used in SONOS
lvnm 24 Low Voltage N-channel
rpoly 27 Emitter poly used in b53
vte 28 E30 specific layer
maxvpoly 29 high voltage poly
nsdm 30 N+ Implant
psdm 31 P+ Implant
silm 32 Silicide
maxvmet1 38 high voltage metal 1
Layer Layer
Description
Name Number
maxvmet2 39 high voltage metal 2
tunm 41
hvi 42 High Voltage Identification layer
licon1 43 Contact from local interconnect to a lower layer.
bnm 45 E30 specific layers
famossd 47 L28 specific device layer
cbnm 48 Created Buried N+ Mask (E30 specific)
calp 49 tsmc18* specific layer
cnwm 50 Created N-Well Mask
cpwm 51 Created P-Well Mask
cfom 52 Created Field Oxide Mask
cfim 53 Created Field Implant Mask
cputm 54 P-Channel Punchthrough Implant
cp1m 55 Created Poly 1 Mask
cnsdm 56 Created N+ Implant Mask
cpsdm 57 Created P+ Implant Mask
cntm 58 Created N Tip Implant Mask
cctm1 59 Created Contact Mask
cmm1 60 Created Metal 1 Mask
cviam 61 Created Via Mask
cviam2 63 Created Via2 Mask
cmm3 64 Created Metal3 Mask
clvnm 65 Created Low Voltage N Mask
cpdm 66 Created Pad Mask
cviam3 67 Created Via 3 Mask
Layer Layer
Description
Name Number
cviam4 69 Created Via 4 Mask
cpwpm 71 Created Pwell Protect Mask
cprim 72 Created Program Implant Mask
crfam 73 Created Read Famos Implant Mask
cfpm 74 Created Floating Poly Mask
capm 75 Created Array Protect Mask
ccpm 76 Created Core Poly Mask
cgpm 77 Created Gate Poly Mask
cblm 78 Created Buried Layer Mask. Used in the starm* technologies.
cdnm 79 Created Deep N+ Mask. Used in the starm* technologies.
cpbm 80 Created P Base Mask. Used in the starm* technologies.
chvi 81 Created High Voltage Implant (E30 specific)
chvptm 82 Created High Voltage P-Tip Mask
cli1m 83 Created Local Interconnect 1 Mask
cdnwm 84 Created Deep Nwell Mask
clvtm 85 Created Low Threshold Voltage Mask
cdpm 86 Created Depletion Implant Mask
cvte2 87 Created VTE2 Implant Mask. (E30 Specific)
cpf 88 Created P Field Implant Mask - TSMC E30 specific mask
cvte1 89 Created High Voltage (E30 Specific)
cfsdm 90 Used in L28
ctunm 91 Created Tunnel Mask (E30 Specific)
lvt 92 For low vt PMOS
conom 93 Created Oxide-Nitride-Oxide Mask
Layer Layer
Description
Name Number
crwm 94 Created Resistor Protect Mask
clicm1 95 Created Local Interconnect Contact 1 Mask
crem 96 Resistor Emitter Mask - SM42d
cfwm 97 tsmc18* specific layer
cpsm 98 Created Oversize Pad Layer (Prom26 specific)
cpw 99 Pwell Mask - E30
npn 100 Used for recognition and extraction of an NPN transistor
pnp 101 Used for recognition and extraction of a PNP transistor
inductor 102 For Inductors
via5 103 Contact from fifth layer of metal to sixth layer of metal
met6 104 sixth layer of metal routing
cviam5 105 Created Via 5 mask
cmm6 106 Created Metal 6 mask
target 107 Fuse Target Layer
maxv 108 maximum voltage
rimp 109 Poly Resistor implant layer (L27 specific)
areaid 110 Miscellaneous area identification layer
cmvi 111 e35 specific layers
cphvi 112
cesd 113 tsmc18*specific layers
cpm 114
npc 115 nitride poly contact cut
cnpc 116 created nitride poly contact cut
cnpm 117 created n plus mask (for n plus poly)
cptm 118 created p tipmask
Layer Layer
Description
Name Number
czrm 119 created zero mask
zrm 120 zero mask
Table 3.1.2 lists all the purposes in V4.4 with a description of how the purpose is used. V4.4 uses
purposes more effectively than V2.0 to eliminate ambiguity in device extraction and labeling lay-
ers.
Table 3.1.2: Purpose List in V4.4
V4.4 Purpose Purpose

LSW Description
Name Number
seal sl 1 areaid purpose painted over the seal ring all the way around the
chip. Created layers stays within the sealring with not opera-
tions, and the extent of the die is determined by Chip Abstract
using this layer.
core ce 2 areaid purpose which identifies the memory core
frame fe 3 areaid purpose which DRC uses to identify pads in the frame
waffleDrop wp 4 Specifies an additional keep out regions for waffling
standardc sc 5 areaid purpose which identifies standard cells
moduleCut mt 10 areaid purpose which identifies location of etest modules
within the frame
dieCut dt 11 areaid purpose which identifies the location of dice in the frame
frameRect ft 12 areaid purpose which identifies the boundary of the frame
cut ct 15 Used to separate terminals on a resistor
res rs 16 Used to identify a resistor device
esd ed 17 areaid purpose used to identify ESD devices for rule checking
short st 19 Specifies a short device
mask mk 20 Mask data
V4.4 Purpose Purpose

LSW Description
Name Number
maskAdd md 21 Polygons which are drawn on these layers are added to or
maskDrop mp 22 deleted from the final mask before it is saved and after the
mask’s DRC rules are checked.
diode de 23 areaid purpose to identify an LVS diode device
fuse fe 24 Used to recognize a fuse device.
gate ge 25 Used to identify a transistor gate in unusual devices.
hv hv 28 High Voltage recognition purpose
probe pe 29 Used to identify areas that need to be left open on higher layers
to allow probe access for debugging chips.
option0- o0- 30-49 These are treated as drawing purpose when the specified option
option9, oJ is enabled for DRC and created layers. LVS extracts these lay-
optionA-J ers as a device.
deadZon dn 50 areaid deadzone identifies “deadzone” area in the DieSealR
pcell for metal stress relief rule checks
critCorner cr 51 areaid critical corner identifies “critical corner” area in the
DieSealR pcell for metal stress relief rule checks
critSid cd 52 areaid criticalsid identifies “criticalsid” area in the DieSealR
pcell for metal stress relief rule checks
substrateCut st 53 areaid substrateCut is used to have multiple substrates in layout
which can be connected to different potentials.
opcDrop op 54 areaid opcDrop is used to specify areas to exempt from auto-
matic Optical Proximity Correction
artisan an 55 areaid artisan is used to identify cells in artisan libraries
label ll This is used to label nets, pins, pads, and BJT devices.
Section 2: Pins
A pin in Opus must be a shape having a net database object attached to it. The net is in turn attached
to a terminal. There is no Opus requirement for the terminal name to match the net name. Opus
completely ignores a label placed over a pin geometry. Opus allows the pin geometry to be drawn
in any layer.
The Cypress design flow requires the following things for a well formed pin. Some of these items
are required for the design flow to work, others are simply good layout practices.
• The pin geometry is drawn on the same layer as the drawn data only on the “pin” purpose.
• A pin label is required.
• The pin label matches the pin net name.
• The net name matches the terminal name.
• The pin label is drawn on the same layer as the drawn data only on the “label” purpose.
• The pin geometry must be completely covered by drawn data.
• The terminal direction in the layout should match the schematic. This can be verified using the
cross view checker in Cadence.
A complete metal 1 pin named “ctl” with a net direction of “input” would consist of:
• A shape of drawn data on the (met1 drawing) layer
• A pin shape on the (met1 pin) layer
• A terminal and a net database object connected to the pin shape and having the name “ctl”
• A text label drawn on the (met1 label) layer with its origin over the pin shape and having the
label value of “ctl”,
Or,
A text display attached to the pin shape and associated with the terminal name, drawn on the
(met1 label) layer, with its origin over the pin shape.
A program is available to check all pins in a layout to make sure they conform to these rules, and
to aid in finding and fixing problems with pins. From the layout editor, use the Cypress pulldown
menu and select “Pin Check and Fix...”
Pins can be created using the schematic database as a guide by using the Cypress pulldown menu
and selecting “Pins/Labels from Sch...” This will check the schematic database for net labels and
pins and aid the user in placing net labels and pins in the layout database.
If a bus is being created with a regular pin pattern, the Cypress pulldown menu item “Iterated Pin
Creation...” can be used to quickly create the pins.
The Opus Create->Pin pulldown menu can be used. This form allows placement of symbolic pins
as well as shape pins. Before completing a shape pin, make sure the Create Label boolean button
is turned on and the Text Style is set to use a pin layer whose purpose is “pin”. After completing
the pin shape, change the entry layer to the corresponding “label” purpose lpp (Layer Purpose Pair)
to complete placement of the label.
It is also possible to draw shapes on the pin purpose, draw labels on the label purpose over the pins,
and run “Pin Check and Fix...” to create the pin database information for these pins.
If you cannot see pin labels, it is probably because you have pin label viewing turned off on the
layout editor (this is the default). You fix this by selecting Design->Options->Display... and
turning on Pin Label viewing, or by adding the following line to the ~/.cdsenv file.
layout displayPinNames boolean t
Section 3: Net Labels
Net labels are on the same layer as pin labels. The difference is only whether or not the label is over
a pin. Any drawing layer which has a label purpose can be labeled using that label purpose. Label-
ing a net can help LVS when binding nets by name between the layout and schematic, and will also
improve the readability of a spice netlist.
Section 4: Resistor
A resistor device is identified with the res purpose. The res lpp shape covers the drawn data. Only
what is covered by res is extracted, so if the res does not cover the resistor from contact to contact,
only part of the resistor is extracted and the resistance value will be incorrect. The res purpose is
normally used only for identifying the extent of the resistor. The drawing layer is what determines
the mask.
The cut purpose must be drawn (as thin as possible) through the middle of the resistor. This is re-
quired by the extraction rules to separate the two terminals of the device.
There are several resistor pcells in the device library. When possible, use these pcells to ensure that
all layers are drawn properly. Figure 3.4.1 shows an example layout for a poly resistor.
Figure 3.4.1: Example Resistor Layout
Section 5: Fuse
A fuse device is identified with the fuse purpose. The fuse lpp shape covers the drawn data identi-
fying the fuse for extraction. A target layer is also drawn on a fuse. This is used to identify the co-
ordinates which the laser uses to blow the fuse. Follow TDR rules for placement of the target.
There is a device library pcell for a fuse which allows easy placement of this device. Figure 3.5.1
shows an example layout of a met2 fuse.
Figure 3.5.1: Example Fuse Layout
Section 6: Short
A short device is identified by an lpp shape on the short purpose. This recognition layer separates
a net into two nets with a short device between them. The drawn data under the short recognition
layer is ignored in parasitic computation, so it should be kept small. There is a device library pcell
for the short device. Figure 3.6.1 shows an example layout of a met2 short.
Figure 3.6.1: Example Short Layout
Section 7: Options
Option purposes provide the designer with the ability to change a mask layer by specifying addi-
tional layers which may be optionally included with the drawn layer. Option purpose shapes are
not recognition layers. They are actual drawn data. There is a device library pcell for the metop
device. Figure 3.7.1 shows a met2 metop2 connecting two pieces of met2.
For most verification tools, a shape drawn on the option layer is treated as drawing purpose data
when the option is included.
For LVS, a shape drawn on the option layer is extracted as a metop device connecting two distinct
nets.
The following limitations exist:
• Only one option can be used at a time.
• All options must exist on the same layer.
• Valid option layer(s) are specified in the TDR.
• Options cannot form devices.
• Options cannot have contacts.
Figure 3.7.1: Example Metop Layout
Section 8: Mask Layers
Mask layers are generated using drawn data. These mask layers are generated on the mask purpose
and the shapes generated are the shapes sent to the mask vendor to create photoresist masks. These
are often called created layers.
In special circumstances, these mask layers can be operated on through the created drawing layer
and the created maskAdd and created maskDrop layers.
Drawn layers are generally drawn at the size of the final feature after fabrication. Meaning if a met-
al bus is drawn two microns wide, after it is fabbed, it should be two microns wide. Because of
processing effects, the photoresist mask is normally either larger or smaller than the desired final
feature size. For this reason, the mask layers are created from drawn data.
The terms created layers and mask layers are often used interchangeably.
Created layers are normally given a name in opus which begins with a “c” and is followed by the
fab acronym for the mask layer. Each created layer name must have a mask purpose in order to be
a created layer. It may have a drawing purpose, and it may have the maskAdd and maskDrop pur-
poses.
❒ Created Drawing Purpose Layers
The created drawing purpose is drawn data much like any other drawn data. A shape drawn on this
lpp goes through a final sizing and is used to create the mask lpp. This layer normally overrides the
normal layer creation process and is used to get around a created layer algorithm problem.
❒ Created maskAdd and maskDrop Purpose Layers
These layers are normally used to create serifs in the corners of a layout. These serifs are used to
prevent corner rounding. These layers modify the mask layer after drc rules are complete, which
means they can cause serious problems if not used carefully.
The example shown in Figure 3.8.1 shows little more than the concept. The shape and size of serifs
may differ as we learn more about this problem.
Figure 3.8.1: Example Serif Usage

maskDrop
maskAdd
drawn data
It is recommended that users check their database for unwanted maskAdd and maskDrop layers.
Use the Cadence Edit/Search layout editor menu command before tapeout to show where these lay-
ers are being used.
Section 9: BJT Devices
The npn and pnp drawing layers are used to recognize and extract npn and pnp devices, but these
layers (depending on the technology and the device) may also influence created layer generation.
Reference the TDR for the technology for more information.
Either way, BJT devices (this includes npn, pnp, and bcdiode devices) have strict layout require-
ments and it is best to use the technology supplied layout cell to place these devices.
The npn and pnp label layers are also used to extract these devices. This layer is not a net label
layer.
Section 10: Special Areaid Layers
The areaid layer is generally used to identify an area on a chip. Often, DRC rules vary depending
on where a feature is on the chip. These layers should be drawn at the lowest level of hierarchy
possible to prevent excessive flattening during the various rule checks.
Table 3.10.1: Areaid Layer Descriptions
Purpose LSW Description
core ce DRCs use this layer purpose pair to identify the memory core.
seal sl The created layer algorithms use the holes in this layer purpose pair to constrain
any created layers that are created by a ‘not’ operation. The ‘not’ created layer is
drawn to the extent of the region defined by the hole. This layer purpose pair is
usually drawn in a ring configuration around the outside of the full chip layout,
and covering the seal ring by the required amount. The outside of this ring is
used to determine the extent of the die when creating a Chip Abstract to be used
in bonding diagrams.
frame fe DRCs use this layer purpose pair to identify pads in the frame.
moduleCut mt Technology uses this layer purpose pair to identify the location of e-test modules
within the frame.
dieCut dt Technology uses this layer purpose pair to identify the location of the dice within
the frame.
frameRect ft Technology uses this layer purpose pair to identify the boundary of the frame.
esd ed DRCs use this layer to identify ESD devices.
standardc sc Identifies cells in the standard cell library.
Section 11: Unusual Transistors
The gate recognition layer (poly gate) is used to identify the gate on devices where it is not obvious
to the extraction rules what is gate and what is not.
Parallel slots (holes) in poly over diffusion, in which the outer poly ring extends beyond the diffu-
sion, form a field-less transistor gate only in the pillar region between adjacent slots. Layout
extraction cannot ordinarily correctly handle these devices.
Therefore, it is a requirement to paint poly gate over the central gate pillar of poly. If there are par-
allel poly slots, there will be poly pillars between them, each covered by poly gate to identify it as
a gate. poly gate explicitly confines the extracted gate to the area it is painted on.
Typically, field-less (slotted) devices incorporate bevelled corners flared at the top and bottom. In
this case, poly gate is normally drawn to exclude the flaring; otherwise, the flared gate ends will
cause unwanted bend corrections. The remaining poly over diffusion will not contribute to the gate
but will be extracted as a parasitic capacitance.
Unlike in the field-less devices described above, diffusion in ring transistors extends beyond the
poly. The hole in the poly forms one source/drain terminal and the surrounding diffusion forms the
other. The poly ring must have one or more necks of poly exiting the diffusion. To measure the
ring and neck separately and accurately, poly gate must be painted on the ring portion in a specific
manner. Two styles are supported.
The traditional style leaves a gap in the poly gate forming a C-shape in the poly gate. The gap is
centered on one side of the ring and aligned with the neck. Since the poly gate gap edges cut
through the poly ring, those cut lines are used to measure the length of the ring device. The width
of the device before bend corrections is the center line length around the ring from one poly gate
cut line to the other. The poly in the gap area contributes to the neck device’s width.
In the other style ring, the poly gate forms a closed ring. In this case, the distance between the inner
and outer ring perimeter with slight adjustments for bends is used to derive the length of the device.
Section 12: Boundary Layers
These layers are used to control routing for IC Craftsman.

Page 45 last modified 6/27/05 Created Layers
Chapter 4: Created Layers
This chapter defines created layers, explains how they are used, and how they are created.
Section 1: Overview
During layout, designers draw polygons on layers known as “drawn” layers. Although, these layers
are similar in size and shape to the materials present on the final silicon wafer, they must first be
manipulated (normally in size) to shapes which match the dimensions of the photoresist added/re-
moved during each mask etch phase of the die manufacture. These modified layers are interchange-
ably called “created” or “mask” layers; “created” because they are generated from drawn layers
and “mask” because they represent a photoresist mask.
During created layers, many drawn layers convert directly to mask layers by an undersize or over-
size operation while others must go through a complex algorithm before the final sizing. Since it
is sometimes necessary to view/modify/append the output of the complex algorithm before the fi-
nal sizing, “drawn compatible created layers” were developed. Like drawn layers, drawn compat-
ible layers closely represent the appearance of a material on the wafer; and like drawn layers,
drawn compatible layers must be sized to created the final mask layer used in die manufacture.
Many times when people refer to created layers, they are referring to both drawn compatible cre-
ated layers and the final mask layers.
Section 2: Modifying Created Layers Directly
For every drawn compatible created layer, there exists a corresponding mask layer. The inverse,
however, is not true. Mask layers which are generated directly from a drawn layer do not have cor-
responding drawn compatible layers. In the Cypress design flow, mask layers and drawn compat-
ible created layers have the same Cadence layer name but different Cadence layer purposes. The
drawn compatible layers are stored with the purpose “drawing” whereas the final mask layers are
stored with the purpose “mask”. Layer names are usually determined by prepending a “c” to the
beginning of the fab acronym for that mask layer. Normally, fab acronyms are listed in the process
bias table of each TDR.
Serifs are features in a chrome mask which are designed to prevent square corner rounding of pho-
toresist and, subsequently, of silicon. Since serifs do not follow standard mask layer design rules,
either generating them from drawn layers or hand drawing them on the final mask layer can lead
to potentially thousands of DRC errors. To overcome this problem, each mask layer in the design
flow has two layer purposes which are used exclusively for drawing unchecked mask features.
These purposes are maskAdd and maskDrop. Polygons which are drawn on these layers are added
to or deleted from, respectively, the final mask before it is saved and after the mask’s rules are
checked. Processing these polygons at this time insures that the taped-out mask includes these fea-
tures but does not flag the DRC errors these features introduce.
Note: Even though ignoring DRC errors created by these layer purposes is desirable, users must
make sure that unwanted polygons do not exist in their layout hierarchy. Such unwanted shapes
can invalidate a mask forcing an additional costly tapeout. As a precaution, users should use the
Cadence Edit/Search… layout editor menu command before they tapeout to show them where each
of these shapes is being used.
Section 3: Created Layers Algorithms
Drawn compatible created layer algorithms are defined, in summary form, in each technology’s
TDR. Because of the complexity required to generate DRC correct output, TDRs do not normally
contain detailed algorithm information showing the exact creation process. For example, after first
phase creation through the basic created layer algorithm, many drawn compatible created layers
may need to go through complex merging and/or sizing operations to prevent width violations,
sliver formations, and to eliminate false errors. These operations are often constrained by opposing
requirements, sometimes not fully considered when the drawn TDRs are written. To enable timely,
unsupervised correction of created layer errors, it is important for a designer to understand how
created layer algorithms work. Following is a description of the basic techniques used during cre-
ated layers.
Below is a definition of the colors and fill patterns used in describing the created layer algorithms.
Figure 4.3.1: Layer Pattern Table
nwell tap
diff NSDM
poly added layer
In general, when a drawn compatible created layer must be manipulated to meet TDR require-
ments, it is subject, after its initial creation outlined by the TDR, to a two phase algorithm: intra-
layer space/notch violation correction, and intralayer notch violation correction. Each of these
corrections requires adding more of the drawn compatible created layer to eliminate minimum
space and size errors. Care must be taken by these phases, however, to ensure that the added poly-
gons are not placed too close to other materials. For example, the n-diffusion source/drain mask
must not overlap a p-diffusion region or come too close to the drain of a p-channel enhancement
device. For this reason, each phase of the merge-fill algorithm uses a protection mask layer created
by sizing forbidden overlap layers by interlayer spacing amounts. Following is a step by step de-
scription of how the merge-fill algorithm works for the NSDM layer after NSDM’s initial genera-
tion. (It should be noted that this is not the complete NSDM generation algorithm. The full NSDM/
PSDM algorithm is described in the next section.)
In the first phase, spacing and notch errors in the input data are identified as errors with positive
projections in which a line perpendicular to one edge intersects both edges of the space error. The
error type is replaced by the polygon required to fill the error. (Note that it is possible for this error
correction to create minimum width errors.) The shapes used to fill the error regions may not over-
lap the protection mask.
Figure 4.3.2: Created Layers Fill Example
In the second phase, any notch errors left after or created by phase 1 are filled. Any notch errors
that overlap the protection mask cannot be fixed because of overconstraints. These errors will be
flagged during DRC checks.
Figure 4.3.3: Created Layers Notch Example
NSDM and PSDM are probably the most complex created layers to generated. They represent the
masks used during n and p source/drain implantation. Not only do they have to be merged and sized
as described by the merge fill algorithm, the initial sizing must be specially handled to prevent
DRC errors.
Current TDRs do not completely define the rules for how NSDM and PSDM should be generated.
After several discussions with the Technology group, the following assumptions have been made
with respect to NSDM and PSDM generation.
• NSDM and PSDM may overlap. However, NSDM may not overlap p-diffusion/p-tap and
PSDM may not overlap n-diffusion/n-tap.
• NSDM may be separated by a distance of 0 or more from both p-diffusion-which-abuts-n-tap
and p-tap-which-abuts-n-diffusion.
• PSDM may be separated by a distance of 0 or more from both n-diffusion-which-abuts-p-tap
and n-tap-which-abuts-p-diffusion.
(Both of the previous assumptions assume that the current is determined by the drain side of
the device and that a source surrounded by tap will contain enough properly doped diffusion to
create a working device.)
• NSDM must be at a distance of X or more away from p-diffusion which does not abut n-tap.
• PSDM must be at a distance of X or more away from n-diffusion which does not abut p-tap.
• The minimum extension of NSDM beyond n-diffusion and n-tap must be satisfied for all edges
and edge portions of n-diffusion and n-tap which do not abut p-diffusion or p-tap.
• The minimum extension of PSDM beyond p-diffusion and p-tap must be satisfied for all edges
and edge portions of p-diffusion and p-tap which do not abut n-diffusion or n-tap.
• NSDM may come as close to a p-type gate as needed and even overlap the poly end-cap as long
as the NSDM maintains its required distance from the p-diffusion drain.
• PSDM may come as close to an n-type gate as needed and even overlap the poly end-cap as
long as the PSDM maintains its required distance from the n-diffusion drain.
• Minimum width errors do not matter because they translate to minimum resist spacing errors.
• Minimum spacing errors could be ignored in corner to corner circumstances.
• No other restrictions apply.
NSDM and PSDM generation is a 5 phase process. The generation process of these two layers is
identical except for dopings and areas covered. For this reason, only NSDM generation will be de-
scribed.
In phase 1, the drawn data is identified as one of two types: the base layer used to generate the ini-
tial mask and the protection layer identifying the region into which the mask layer may not en-
croach. For NSDM, the base layer is simply all n-type tap plus all n-type diffusion. The protection
layer is generated from the combination of four layers: all p-type tap, all p-type diffusion, oversized
p-type unstrapped source/drain diffusion, and oversized p-type nonstrapping tap. The oversize
amount for the latter two layers is the spacing of NSDM to unrelated p-type tap and diffusion.
In phase 2, the base layer is grown such that the minimum extension of NSDM beyond n-diffusion
and n-tap is satisfied for all edges and edge portions of n-diffusion and n-tap which do not abut p-
diffusion or p-tap. The NSDM must also not overlap the protection region.
Figure 4.3.4: NSDM/PSDM Example
In the third, fourth, and fifth phases, the merge fill algorithm is followed.
If the layer growth of NSDM is negative, it also performs a special case of notch filling. This spe-
cial case handles the extra space that is needed in a notch when one side of the notch is orthogonal,
and the opposite side is at 45 degrees.
Section 4: Waffling procedure
Waffling needs to be enabled during Created Layers generation if it is specified in the TDR as ap-
plicable to the technology (Refer to “Created Layers Algorithms” table under “add waffle pattern”
column). To enable waffling on the die, the switch “waffle_chip” needs to be set. If the waffling is
needed on the frame, the switch “waffle_frame” needs to be set. The waffles are added in the empty
spaces of the base layer and related keepout layers. In the frame regions, a region can be marked
with the layer’s waffledrop purpose (E.g.: poly:wp) to exclude the region from waffles. The kee-
pout layers and distances from waffle pattern are also specified in the TDR.
The boundary for the waffling region is determined by the areaid seal (in the case of die) and areaid
framerect (in the case of frame). It is also important to run waffling on all dependent layers together
(E.g.: p1m and fom need to be specified in the same run if both need waffles).
The resultant waffles can be seen (along with mask generated from drawn layers) by turning on the
display for the mask in the VLW. Figure below shows an example of the composite waffle pattern.
Figure 4.4.1: Waffle pattern generated on FOM (larger) and P1M masks (smaller squares)
Page 54 last modified 6/27/05 VCR User’s Guide
Chapter 5: VCR User’s Guide
User’s guide provides a manual for designer’s daily usage. Most functions of VCR will be de-
scribed in user’s guide.
Section 1: Introduction
❒ What is VCR
Virtuoso Custom Router, is a shape based routing tool. It has two main routing modes: assisted-
interactive and the auto routing modes.
In 1989, a company called Cooper & Chyan Technology, Inc, introduced first IC shape Based rout-
ing tool into the market, it was called CCT. CCT was later developed to an IC routing tool called
IC Craftsman in 1994. Cadence acquired Cooper & Chyan Technology, Inc in 1997 and updated
IC Craftsman, changed it name to Virtuoso Custom Router and released VCR Version 5 in 1999.
This manual is based on VCR version 10.0.14.
❒ What VCR can do?
VCR helps layout designer by its powerful routing function, but VCR can not totally replace layout
designer.
First, VCR reads data inputs translated from other layout electronic design automation tools, Vir-
tuoso, for example. Data inputs contain information about cells placement, net connections among
cell pins, DRC and other technology related rules, etc. VCR then establishes shapes based on these
input files.
VCR can fine tune cell placement in placement mode, functions include move, push, pivot and
align cells.
User can route design using VCR’s interactive routing function. VCR can assist designer in fol-
lowing aspects:
• On-line flight line direction/LVS check
• On-line DRC check
• Automatic insert via and contact, change layer
• Route multiple path, like data bus, all at once
VCR can auto route design by using algorithm based on simulated annealing. Basically, VCR will
first route the connections as much as possible, then fix the routing error pass by pass. Auto router’s
performance really depends on cell placement / floor plan and user’s rule setting.
❒ Terminology:
.do file and .did file They are actually same. User can operate VCR by either GUI menu
or command line input, every GUI menu input has a command line
input associated with it. A do file is just a series user defined com-
mand line input; and a did file is the automatic record, in command
line format, of every function performed while using VCR. User can
extract useful parts in did file and compile his/her own do file.
Host CAD system The layout tool from which the physical design originated.
Translator One of various tools used to move physical layout data and schemat-
ic interconnect data into and out of VCR.
Keepout A layer shape that is either a piece of layer translated from host CAD
system or a user defined polygon. This shape is used to exclude
routes, via, etc. VCR recognizes keepout shapes and applies clear-
ance rule from these shapes, so that design is DRC clean after trans-
late back to Virtuoso. User can also define keepouts to impose
routing rules.
Conductor A layer shape in host CAD system is either translated to VCR as kee-
pouts or conductors. They are the two basic kind of shapes in Shape
Based technology. Keepouts are recognized as shapes to keep away
from, while conductors are recognized as pieces that conduct elec-
trical current. The actual net a conductor connecting to is defined by
vias instances and pins attaching to it.
Boundary A perimeter which routes and cell placements are not allowed to ex-
ceed. This perimeter can either be user defined or automatically cal-
culated by translator.
Net, Fromto, wire, segment A net is the entirety of a single named net. A selected net shows all
wires and pins connected to that net.
Fromto is a portion of a net originating from one pin and terminating
at another pin.
A wire is a portion of a net, either physical or guides. A selected
physical wire displays all pins and segments up to any T-junction on
the net.
A segment is a single, straight part of a physical wire.
Same net check Same net check is a setting to control rule checking for gap and
notch violations between objects on the same net. The default setting
is OFF. That means, by default, VCR will NOT check gap and notch
violations on the same net.
Pin escape When a need-to-connect pin is on a forbidden routing layer, VCR
will route a short escape wire on this forbidden routing layer. Escape
wire is routed from the pin to a place where a via connecting to rout-
ing layer can be placed. A variable escape_distance is used to con-
trol the maximum allowable length of the escape wire. The default
setting is -1, that means length allowed for escape wire is unlimited.
Guide Also called flight line, used to mark un-connected fromto.
Conflicts Layout errors are called conflicts in VCR. Conflicts include DRC er-
rors (clearance, minimum width, enclosure, etc), shorts and other
layout rule violation.
I/O Ports I/O ports is the name of top level pins in VCR. I/O ports can either
be deifined in VCR or translated from stand alone top level pins in
Vrituoso.
Clearance and Gap These are terms about distance rule between routing objects. Clear-
ance means two routing objects must be separate at least by this
clearance rule. Gap means two routing objects (wire for most of
time) must be separate by this gap rule and only by this gap rule.
Must Join, Strong and Weak Connections
Figure 5.1.1: Must Join, Strong and Weak connected pins
A B A B A B
Must Join Pins Weak Connected Pins Strong Connected Pins
These terms are about identical pin connection requirments.

Must Join identical pins of a cell requires to be connected by exter-

nal wires individually. In other words, if a cell has several identical
pins, router must route wire to every single of them.
Weak Connected identical pins of a cell are normally connected in-
ternally by wires on resistive layers such as polysilicon. There is no
need to connect every single of them, but internal wires can not be
used as feedthrough. In this situation, router can just route wire to
one of the identical pins of a cell.
Strong Connected identical pins of a cell are normally connected in-
ternally by wires on nonresistive layers such as metal. Internal wires
can be used as feedthrough. In this situation, router can just route
wire to one of the identical pins and use other identical pins as
feedthroughs.
Section 2: VCR Design Flow
Figure 5.2.1: Typical VCR design flow:
Host CAD System (Virtuoso)
DRC check
Translation(Export)
Input VCR Design Files
Set Rules
Fine Tune Placement
Route (Interactive/Auto)
Clean
Translation (Import)
Host CAD System (Virtuoso)

❒ On-line help usage
VCR has a powerful on-line help system.

• Open on-line help system
On the right upper corner of VCR window, click Help.
• Help on menus
If one has questions about settings on a menu or a dialog box, click on the Help button and on-
line help system will display information about that menu or dialog box.
Section 3: Prepare design for Translation
❒ Run Cypress Schematic Driven Layout (SDL) to place cells in layout
Run SDL not only places instances in layout and match instance names with schematic, but
also establishes net connectivity information, i.e. netlist, into layout cell view.
For more information about run SDL, please refer to SDL user’s guide.
❒ Define prBoundary, floor plan the placed cells
User can define a Place and Route Boundary before translate to VCR. If this boundary is de-
fined, VCR translator will recognize it as the routing boundary, other wise, VCR translator will
calculate a default boundary based on cell placement.
VCR has a function to align standard cells in its placement mode. User can just rough place the
cells in Virtuoso or do the floor planning in VCR.
❒ Draw top level pins
User has the option to draw the top level pins and plan their placement before translation to
VCR. Stand alone pin purpose polygon will be translated to VCR as I/O ports, pins attached to
components and existing wires will be translated as pin polygons.
❒ Run DRC
Run DRC before translating to VCR and make sure design is DRC clean. Translator will trans-
late the existing cells into VCR as “protected” cells. By default, VCR will not check protected
cells for DRC errors.
❒ Back up placement
Please back up the layout cell view at this point, either save it as “placement” cell view or save
it as another cell: design_base_placement. If there is anything wrong with VCR, user can re-
start from this backup.
Section 4: Translate from Virtuoso to VCR
❒ Translation Flow
Figure 5.4.1: DFII to ICC Translation Flow

Design Framework II VCR
Design Framework II ICC2CDBA

Virtuoso Layout View Translator Design Files
.ses
Schematic/Netlist CDBA2ICC .img .dsn
Translator .lib
.net
Translation Rule .pla
Technology Files Editor .w
.str
Translation Rule File
CDBA2ICC needs 3 kinds of information to finish translation: placed layout cells, netlist and tech-
nology rules. If you run SDL, placed cells and netlist are saved in one layout file. Technology rules
normally come from technology file, but you can customize technology rules using Translation
Rules Editor or write your own translation rules.
After routing in VCR, the result must be saved in session file (.ses) which includes wire and cell
placement, then use ICC2CDBA translator import back to DFII environment.
❒ Export to Router Window
In the layout view window, click Route -> Export to Router to bring up Export to Router menu:
Figure 5.4.2: Export to Router Menu:
Export Layout Cell View Make sure library, cell and view corresponds to the placed layout de-
sign. In the Area field, coordinates of rectangular place and routing
boundary are automatically generated. User can choose to only ex-
port a part of the design or whole design. Click Whole Area, and
the tool will automatically set the whole design bounding box.
Export Netlist From User can choose to export netlist from Layout Cellview, Schematic
Cellview or Netlist File.
Normally layout view is used, one have to run SDL to save the
netlist into layout view. Manually place instances in layout and
match instance names with schematic is not enough for this option.
If user wants to use schematic view, make sure instance names in
layout match those in schematic. If user wants to use netlist file,
name matching is required between layout and netlist file, also user
has to specify the name and path of the netlist file.
Export Alternate Views Translates abstract or other views rather than layout views of cells.
Type a list of views separated by space. The translator uses the first
view found in the list for each particular cell.
Conductor Depth and Keepout Depth
Specifies how many levels down in the hierarchy to expand when
generating conductors and keepouts. Layer shapes below the depth
setting will not be exported. Deeper conductor depth setting will
considerablly slow down the VCR autorouter, deeper keepout depth
will not.
Default Pin Connection Sets a global rule for handling identical pins. The default setting is
Strong Connection.
Must Join tells the router to connect all identical pins on each net.
Strong Connection tells the router to connect only one of the identi-
cal pins on each net and other pins can be used as feedthroughs.
Weak Connection tells the router to connect only one of the identical
pins on each net, but not to use other pins as feedthroughs.
For more information about weak, strong and must join connection,
please see Figure 5.1.1, “Must Join, Strong and Weak connected
pins”, on page 57.
Options
Full Connectivity Controls how identical pins are treated. If this option is OFF, identi-
cal pins will follow Default Pin Connection setting. If this option is
ON, identical pins will be treated based on whether they are connect-
ed by a polysilicon or metal conductor.
Cut Pins to Edge Cuts a path through the keepout from the pins to the edge of the cell.
Interlayer Rules Creates interlayer rules for VCR.
Incremental Update: Exports only the cells that have changed since the last export of this
layout cell view into the current export directory. Mosaic, via and
pcell variant image files are always regenerated.
Use Rules File Lets user enter a rules file name to use for translation. By default, the
translator uses the rules in the technology file.
Export to Directory Put the full path of your export directory.
This is normally ~/WA/<ddc>/cct.
Export Mode User can chose translation running as foreground or background. If
running forground, translation process will occupy Design Frame-
work II process and user cannot enter other commands. If running
background, translation will be run as a separate process and will not
block other user commands.
Start Router with Options Select if user wants to run VCR after translation. User can also spec-
ify VCR options.
Section 5: VCR data structure
❒ VCR design file structure
Figure 5.5.1: VCR design file structure
Structure File filename.str

Design file
Placement File filename.pla
Network File filename.net
Wiring File filename.w
Color Map filename.clr
Image File filename.img
Subcell Images *.i
❒ Design File
Design file (*.dsn) contains general informations like host CAD system type and version, design
area, resolution, etc. Design file also contains file pointers to sub-level files from structure file to
color map file.
❒ Structure File
The structure file defines layers, IC boundary, via image names, global rules, and grids. The via
and wire grid definitions are optional.
❒ Placement File
The placement file defines component locations.
❒ Network File
The network file defines netlist. In VCR, a net is defined by a net name and a list of component
pins.
❒ Wiring File
Wiring file defines all the pre-routed wires. The wires translated from Virtuoso are protected: VCR
can not edit or delete these wires, but other wires can connect to these wires.
❒ Color Map File
The color map file defines the colors used in VCR. You can change the default color map using
color palette in Layers Menu.
❒ Image File
The image file defines via images used for routing and a pointer to directory containing sub-cell
image files (*.i).
Symbolic vias are translated as via_arrary_template. Other via instances will be translated as via
images.
Section 6: VCR environment
❒ VCR Window
Figure 5.6.1: VCR Window
Menu Bar Help button
Work Area
Design
Toolbar Icons
Message display Active layer
Mode Status Measurement display
Checking
Command input field Command Status
Placement and routing Mode VCR has two major modes: Placement mode and routing mode.
VCR is always in either one. The default is Routing mode.
Menu Bar Menu Bar give access to pull down menus. Placement mode and
routing mode have different menu bar contents.
Tool Bar Icons The Tool Bar Icons are put into groups and have different set of but-
tons in placement and routing modes.
From top to bottom, the first two icons switch between placement
and routing mode, click switch to placement mode and click
switch to routing mode.
Next group of icons are buttons for general operations:

Repaint: to refresh the work area
View all: to fit all design into work area
Layer panel: to setup layer property and color palette
Status Report: to generate current status report
Check: to check work area
Measure: to switch to measurement mode
When in Routing Mode, 3rd group contains route selection functions:
Select component mode: to select component in design
Select net mode
Select wire mode
Select guide mode
The 4th group in Routing Mode are interactive routing functions:

Edit Route mode: to start routing interactively

Move Route mode: to move, stretch existing wire interactively
Copy Route mode: to route a wire with similar topology of an existing wire
Critic Route mode: to remove unnecessary bends, acute angles and notches
Cut Segment mode: to split a segment into two segment at the clicking point
Delete Segment mode: to delete a wire segment
Placement mode has different 3rd group and 4th group, for more in-
formation, See “Placement Mode Tool Bar Icons” on page 77.
Command input field Use this area to type in commands.
Mode Status Displays which function mode (select net/component, Edit Route...)
is active. The default mode is measurement mode.
Command Status In Interactive Routing Mode, displays how many connections are
not connected, how many conflicts (DRC, LVS error, etc) are in de-
sign, calculated completion rate and the net name presently working
on.
In Auto-Routing Mode, displays routing passes, routing attempts,
re-routed nets in present routing pass, not connected nets, conflicts
and completion rate.
In Placement Mode, displays number of placed components, select-
ed components, locked components, number of violations and total
Manhattan length estimation.
Measurement display Displays present mouse coordinates and measured length. You can
change display unit to inch, mm, um, etc.
Active(Primary) layer In interactive routing mode, displays the present active routing lay-
er. It is also called Primary Layer.
Checking To turn on/off online check. If check is ON, cell movement and wire
adjustment must meet DRC/LVS rules, otherwise VCR will not
complete the editing.
If check is OFF, user can make any edit/movement. If there are con-
flicts, VCR will mark the error in work area. The conflict markers
may not be updated, user can run check command to update mark-
ers.
Design User can see design in the working area. Every design has a bound-
ary, no routing and placement is allowed outside boundary.
Help button Click to turn up on-line help system.
Message Display Display various messages from command result.
❒ Run VCR from command line
If VCR did not turn up after translation, simply go to export directory, and you will find a design
file with .dsn extension. For example, if your design file is named design.dsn, just type:
vcr design.dsn
❒ Basic Operations
Zoom in and zoom out: in the working area, press down the middle mouse button then drag up-
wards will zoom in, drag downwards will zoom out. Middle-click without dragging will center
work area to the middle-clicked point.
Press down Shift or Caps Lock and middle click and drag, usr can move the work area. Release
Shift or turn off Caps Lock to switch back to zooming.
Measurement function: first click measure button, then left click and drag from start point to the
end point, release the left mouse button. Message Display will show x and y distance between the
starting point and the end point, also the length between the start point and the end point.
Draw Ruler: Click Define -> Ruler -> Draw Mode switching to draw ruler mode. Click Define -
> Ruler -> Forget All to remove all rulers in design. User can also define bindkeys to avoid multiple
clicking.
Section 7: Placement Mode
VCR helps user fine tune floor planning in placement mode. Unlike route mode, you can only in-
teractively change floor planning/placement. There is no auto-placement function in VCR.
❒ Interactive Placement Setup
In placement mode, right click mouse and the Interactive Placement Menu will show up:
Figure 5.7.1: Interactive Place Menu
You can switch to different placement editing modes and selection modes in this menu.
Select Setup in Interactive Placement Menu to bring up Interactive Placement Setup Menu.
Figure 5.7.2: Interactive Placement Setup Menu - General
Pointer Style Sets the pointer style.

Skip I/O Frame Controls whether you can manipulate I/O pad/frame components
during interactive placement operations. It is turn ON by default.
Check component Controls how the interactive placer checks for clearance violations
between components and other objects. Pins/Conductors/Keepouts
checks these objects inside components against placement keepouts.
Outline checks only component outlines against keepouts.
Figure 5.7.3: Interactive Placement Setup Menu - Alignment
Alignment Mode Controls selection of component alignment lines.

Direction Controls how components or I/O ports are aligned, you can align to
Closest (either Row or Column), Row or Column.
For example of component alignment, please see Figure 5.7.6, “Alignment Marks:”, on page 78.
Figure 5.7.4: Interactive Placement Setup Menu - Move
This menu controls the cell movement.

Move With Wires will automatically adjust the wires connecting to the moved component. The
automatic wire adjustment function is not very perfect, the result may not be desirable to users. It
is suggested to rip off all the wires connecting to moved components and re-route the wires after
movement.
The Measurement option setting is same as in Figure 5.8.2, “Interactive Routing Setup - Measure”,
on page 81
❒ Placement Mode Tool Bar Icons
Select Component mode: to select component in design

Select Net mode: to select an entire net
Lock Component mode: to lock component. In placement mode, you can move compo-
nent in work area. To avoid accidental move, a component needs to be locked
Move Component mode

Push Component mode: push to automatically avoid overlap during movement
Pivot Component mode
Trade Component mode: to swap component locations
Align Component mode
Space Component mode: Evenly distribute rows and columns of components
❒ Move Components
Left click Move Component mode icon then select component to move. You can mirror, pivot
components while moving by right click mouse and Move Comp menu will show up.
Figure 5.7.5: Move Comp Menu
❒ Aligning Components
The components can be aligned by center, origin, pin or edge. First click the alignment icon to
switch to alignment mode. Alignment mark will show up when the pointer moves over compo-
nents. Align component by first click an alignment mark on the component you want to move
(press down Shift and click to select multiple components), then click an alignment mark on the
component you want align to.
Figure 5.7.6: Alignment Marks:
Align by pin edge Align by pwr edge
Align by center Align by cell origin Align by pin center Align by cell edge
Section 8: Interactive Routing Mode
VCR has a powerful interactive routing capability. Features include:

• Real-time DRC check

• Real-time LVS check with flight line guidance
• Automatic insert via/contact instances
• Automatic changing layers
❒ Interactive Routing Setup
Move pointer to working area and right click the mouse, Interactive Routing Menu will show up.
Then click Setup to bring up the Interactive Routing Setup menu:
Figure 5.8.1: Interactive Routing Setup - General
Via Assistance Specifies how to assist via placement : snap to valid grid or display.
Allow Jogs Sets route segment style, either permits intra_segment jogs or whole
segment movement.
Show Timing/Length Rule Constraints

Sets units to display Timing/Length rule constraints, this is for wire
matching functions.
Others
Snap to Pin Origin Allows wires to connect to the center of a shape pin.
Push Routing Enables wires to be pushed aside when moving vias or wires to com-
ply with minimum width and clearance (DRC) rules.
Allow Floating Nets Allows start routing wire not from an existing net. By default, user
needs to start routing either from a pin or an existing wire/conductor.
A wire routed not from an existing net will be assigned a random net
name.
Auto Shield Auto route shielding wire while routing.
Allow Redundant Wiring Allows extra wiring for shields and power routing.
Same Net Checking Turns on/off same net clearance rule check.
Check Region Permits interactive entry of wires into previously defined regions.
Push Components Enables components to be pushed aside when moving vias or wires.
Auto Polygon Merge Merges same-net keepouts and wiring polygons that touch or over-
lap.
Auto Adjust length Completes the wire to required minimum length when Finish Route
command in route menu is used.
Figure 5.8.2: Interactive Routing Setup - Measure
Alignment Marks If set, alignment marks will snap to shape edges and/or wire centers
as you move the pointer. These marks help you to make accurate
measurements.
Snap Angle Controls mouse movement in Measure mode. You can choose either
All Angle which allows unrestricted mouse movement, or 45 Degree
snap angle.
Output To Controls where and how measurement information displays. If you
select Dialog Box, a Measurement Dialog Box will turn up once you
finish the measurement. Default setting is on.
Figure 5.8.3: Interactive Routing Setup - Bus
This menu setups the behavior of interactive bus routing.

Enable Bus Routing Turns on and off Bus Routing
Enable Tandem Pair Routing Turns on and off differential pair tandem routing. Default is off. It is
necessary if you use different layers for differential pairs.
Fit Via Pattern Forces VCR to insert Vias in available space rather than engineer the
bus to accommodate the vias.
Spacing for Gathering Wires Sets the minimum wire clearance during bus routing. The default is
wire-wire, which is the tightest. Using wire-via clearance will help
to meet the diagonal, stagger, and taper via patterns. And using via-
via clearance will help to meet the perpendicular via pattern.
Figure 5.8.4: Interactive Routing Setup - Style
Pointer Style: Sets pointer style.

Routing Style: Controls the style of your route.
One-Segment: To route a single segment at a time.
Two-Segment: To route two segments a time, shared by a common vertex.
Route to Cursor: VCR will automatically route to cursor/pointer position during rout-
ing, also automatically insert vias. Route to Cursor automatically
disables component/wire push.
For more information about Bus Routing, please See “Bus Routing” on page 87.
Figure 5.8.5: Interactive Routing Setup - Move/Copy
This menu sets options for moving objects in Move mode and for copying polygons in Copy Poly-
gon Mode.
Rotate Default field sets the default rotation angle and mirroring axis for
automatic object rotation and mirroring during move or copy opera-
tions. Increment field sets the incremental rotation angle.
Copy Net Assignment Controls whether copies of wiring polygons have the same net as-
signment as the original or are unassigned.
Edit Slide Controls whether the tool slides the objects, attempting to push ob-
stacles out of the way or moves them over obstacles and drops them
in the new location.
❒ Interactive Route
Figure 5.8.6: Interactive Route a wire
Target Pin
Click on a pin to start

Alignment Marks
New Wire
Direction Arrow Clearance

Guideline
First click Edit Route Mode icon to switch to edit route mode. Click on a pin or existing net and
begin to draw wires. New wires will show up with clearance guideline and direction arrow. In the
Command Status bar, the net name of current net will show up.
You can alter the wire path while editing by tracing back and clicking on the new vertex.
You can change wire width, add via and edit other wire attributes during routing by click the right
mouse button.
Alignment marks appear at edges and center points of all routing layers. Arrows appear at route
ends and indicate aligning with alignment marks. If you route close to the target pin and see arrow
aligning with target pin, right click mouse then select Finish Route, VCR will automatically finish
the route with a perfect alignment.
To add via while routing, left-click on the point you want to add the via then right-click, Edit
Route menu will show up. Then left-click Add Via to bring up Switch to Layer menu. Now you
can left-click the layer you want to switch to, and a via will be automatically inserted in the layout,
also your active routing layer (or primary layer) will chang to the layer you selected.
Via can also be added by: route to a point to add via -> double left-click -> Switch to Layer menu
-> select layer switching to.
Figure 5.8.7: Interactive Routing - add via
select the layer to switch to
different vias to select
Layer2
Layer1
Click
to add
Via
❒ Interactive Edit Route
Click Move icon to change to move/stretch wire mode. If Checking is turned on, every move
must meet clearance rule. This will block some movement, you can turn off Checking at the mo-
ment to move the wire over the nearby wire then turn on Checking after movement.
Click Delete Segment to change to delete wire segment mode. If you only want to delete a part of
a wire segment, first use Cut Segment mode to split the segment then delete the part you want to
delete. Please see Figure 5.8.8 on page 87.
Figure 5.8.8: Interactive Edit Route
(1)
Use Cut Segment to segment wire
Use Delete Segment

(2) to delete wire
Use Move to move wire
❒ Bus Routing
Bus routing is to route a group of nets at once. The wires of these nets will follow similar topology.
Bus routing is very useful for interactively routing differential pairs and bundles.
To use Bus Routing, the nets must be defined either as pairs (2 nets bundle) or bundles, and Bus
Routing must be enabled in Interactive Routing Setup - Bus menu.
In Edit Route Mode, just click on one net in the bundle and start route, VCR will route the whole
bus at the same time.
❒ Preserve Interactively Routed Wires
Normally the critical wires are routed manually using interactive routing and non-critical wires are
routed by auto-router. To prevent auto-router changing the interactively routed critical wires, these
wires need to be either protected or fixed.
Protecting a wire makes the wire polygons not changeable, but other wires of the same net can
still connect to the protected wire. Soft Protecting will preserve the connection, but allow the wire
polygon to be pushed and shoved by auto-router.
Fixing a wire makes the wire polygon not changeable, and other wires of the same net cannot con-
nect to the fixed wire.
Click Edit -> [Un] Fix Nets to fix and unfix nets.
Click Edit -> [Un] Protect to protect and un-protect wire polygons, nets and other routing ob-
jects.
❒ Check Command
Check command checks the design without changing it. Conflict markers in working area may not
be updated during interactive routing/editing, it is a good practice for user to run a check after in-
teractive routing/editing:
check
Section 9: Set Rules For Auto-Route
The result and quality of auto-route really depends on floor planning and rule setting. User can set
rules through pull down menus, by running .do file and by typing commands in command input
field. Once a rule is set by click GUI menu, its command line format will be displayed in either the
terminal window, if you run VCR from terminal, or CIW window, if you run VCR from Design
Framework II.
❒ Layer setting
Click Layers icon to turn up Layer Panel:

Figure 5.9.1: Layer panel
Layer Namees Selectability

Visibility
Layer cannot be used for Routing
Orthogonal Routing direction Primary(active) layer
Horizontal Routing direction
Vertical Routing direction Routing Direction
Primary (active) layer The primary layer is the layer actively used for routing and the layer
shows on the active layer status bar. All other layers are secondary
layers. When you add via and switch to a secondary layer, that sec-
ondary layer becomes primary layer.
Routing direction Sets layers to be allowed routing on horizontal, vertical, orthogonal
(permits routing on both directions) directions, or forbiden routing.
All the cut layers (via, mcon, licon1) must be set forbidden for rout-
ing.
Selectability Sets a layer to be selectable or non-selectable. If a layer is non-se-
lectable, you can not route on that layer during interactive routing.
Visibility Turns on and off layer display.
These settings can also be done in command line and .do file. Command example:
To turn off visibility of poly layer:
vset poly off
To turn off poly selectability:
sset poly off
To forbidden routing on li:
unselect layer li
To set met1 to route horizontally and selectable:
direction met1 horizontal
select layer met1
To set met1 as primary layer:
edit_active_layer met1
❒ Pin Escape and Preventing Routing on Certain Layers
In some situations, routing on certain layers are unwanted, for example, high resistive layer poly
and li. These layers need to be set forbidden for routing.
If all the sub-cell pins are on permit-to-route layers (for example, metal 1 and metal 2), this setting
is good enough to avoid routing on forbidden layers.
But if some sub-cell pins are on forbidden routing layers, for example, poly or li, user needs to set
pin escape distance.

Pin escape happens when via/contact needs to be added for VCR to connect to pins on forbidden
routing layers. Sometime clearance rules may limit the space available for these contacts, auto-
router will route a short length wire on these forbidden routing layers and "escape" to a place where
a via/contact can be placed. The maximum routing distance from pin origin to via is called "pin
escape distance", its default setting is -1, means pin escape distance by default is unlimited.
So if you want to avoid routing on those forbidden-routing layers, this pin_escape_distance needs
to be set to a small positive value. This value is really design depended, it will be affected by floor
planning, technology clearance rule, etc.
To summarize forbidden layer control:
1. Correctly turn on/off routing layers
2. Set pin escape if necessary.
Command line Example: To change pin escape distance to 1 um
change escape_distance 1
❒ Auto-routing Cost/Tax Setting
When routing a design, many requirments need to be taken into account. For example, minimum
number of via usage, metal 1 routing horizontally and metal 2 routing vertically, route as fast as
possible, etc. Some requirements are conflicting to each other, for example, a wire can be jogged
a little to avoid using an unnecessary via. So VCR actually needs to evaluate these requirements
and make trade offs.
User needs to tell auto-router how to evaluate these factors and make trade-offs by set routing tax-
es. From the menu bar, click Rules -> Costs and Costs Menu will show up:
Figure 5.9.2: Costs Menu
Cost menu shows two columns of inputs, cost and Multiplier (taxes).
By default values in cost column are not fixed, but change over a series of routing passes. If you
set Costs, the costs will be fixed. Fixing cost value will limit the auto-router capability. So change
of cost is not recommended. Instead, setting taxes can achieve fine degree of control.
Auto-router evaluates designer’s routing requirements by comparing different taxes. So what real-
ly matters are not taxes’ absolute value, but their relative value. By default, taxes are all set as 1.
For example, if you want wires to follow layer routing direction setting strictly, Wrong-way rout-
ing tax needs to be set much higher than other taxes, for example, set Wrong-way routing tax to
100 while keep other taxes as 1.
There is no clear specification on how much tax will affect routing, designers can set a value and
route design then check the result to determine if the tax setting is proper.
Setup routing taxes using command line:
tax way 100
tax via 20
tax off_grid 100
❒ Auto-routing Rules check Setting
From menu bar click Rules -> Check Rules -> Setup and check to bring up Setup/Check
Rules menu.
Figure 5.9.3: Setup/Check Rules Menu
Antenna Rule Controls if antenna rule is checked.

Conflict Controls whether conflicts are considered during route passes and
whether they display.
Crosstalk Controls whether crosstalk rule violations are graphically marked.
Length Controls whether length rule violations are graphically marked.
Minimum Process Wire Width

Controls whether a minimum process width rule violation is graph-
ically marked. This rule is set in the Layer Clearance Rules dialog
box.
Max Total Via Controls whether the maximum via rules for nets, classes, groups,
and fromtos are checked.
Polygon Wire Controls whether clearance violations are checked from polygon
wire shapes to pins, fixed wires, protected wires, and fixed or pro-
tected vias. Polygon wire clearance violations are included in the
status report.
Protected Controls display of clearance violations between protected wires or
vias and other protected or fixed objects. By default, VCR will not
check protected parts of design.
Re-Entrant Path Controls whether wire loops created by interactive routing or editing
are checked and graphically marked.
Same Net Controls whether same-net notch violations are checked and graph-
ically marked. By default, VCR will not check same net violations.
Segment Controls whether maximum segment rule violations are checked.
max_segment rules control the total routed length on a layer.
Use Layer Controls whether use layer rule violations are highlighted.
Use Via Controls whether use via rule violations are highlighted.
Wire Extension Controls whether wire extension rules are checked.
Setup and Check Sets the selected rules for checking and performs an immediate
check.
Reset To Default Returns the checking status of all items to the default condition,
which specifies checking for conflicts, crosstalk rules, length rules,
minimum process wire width, polygon wire clearances, and re-en-
trant wire rule violations. Rule violations that are graphically
marked are included in the conflict report. Normally, default checks
and same net check is required for auto-router.
Section 10: Advanced Rule Setting
❒ Description of different rule levels
Rules used in VCR are organized in priority levels. A higher level rule overrides lower level rules
if they are applied on same routing objects. IC level rules have the lowest priority and region level
rules have the highest priority.
IC Global and process related rules.
Class A class is a set of nets.
Class Layer Set rules for layers used for a certain class.
Group Set A group set is a set of groups. Set Rule for sets of groups.
Group Set Layer Set rules for layers used for a certain group set.
Net Set rules for certain nets.
Selected Net Set rules for selected nets.
Net Layer Set rules for layers used for a certain net.
Group A group of fromtos. Set rules for groups.
Group Layer Set rules for layers used in a certain group.
Fromto Set rules for fromtos.
Fromto Layer Set rules for layers used for a certain fromto.
Class to Class Set rules for interactions between classes.
Class to Class Layers Set rules for layers used for two classes.
Via Image/Array Set rules for Via image and via arrays.
Region Set rules for a defined area in design.
❒ Description of different kinds of rules
• Clearance Rule
Clearance rule specifies wire width and clearance between different routing objects.
Figure 5.10.1: Clearance Rules Menu
Pick Layer Pick routing objects to apply clearance rules

Taper Wire Taper wire is the first wire segment entering/exiting a pin. This set-
ting enlarges or reduce the taper wire width to pin width and taper
wire length.
Area/Pin/Via/Wire Set clearance rules to different routing objects.
Pin-Via Same Net Set same net clearance rules.
Figure 5.10.2: Wiring Rules Menu
Wiring Rules control net routing.

Junction Controls whether T-junction is allowed in routing.
Vias Controls escape via placement
Priority Set routing object priority.
Limit Vias/Way Limit Via/Bends/Wrong Way routing.... in routing object.
Use Vias/Layers Specify via/layer usage for certain routing object
Max Total Vias Limit total via usage
Effective Via Length Set effective length for a via, use for length and timing matching.
Figure 5.10.3: Timing Rules Menu

Timing Rules set routing object timing specifica-
tions such as delay, capacitance, resistance, etc. All
these electrical specification calculations are based
on length and geometric calculation, then multiply
coefficients like timing/length factor. All the capac-
itance/Resistance coefficients are defined in De-
fine -> Properties -> Layer/Via Menu. These
coefficients are not set by default. User has to set
these coefficients before using Capacitance/Resis-
tance/Delay matching.
Figure 5.10.4: Shielding Rules Menu

Shielding Rules Menu sets rules for shielding wires.
Properties of shielding wire include shielding wire
type (parallel/coax/tandem), net used for shielding
wire, shielding wire width and gap.
Figure 5.10.5: Crosstalk Rules Menu

Crosstalk and noise rules set routing objects
gap by length. For example, if two wires run
together longer, they should be separated
farther apart to avoid crosstalk/noise. This
menu sets a table to determine gap by
length.
You can also set Net Switching/Sample
Window for a certain routing object.
Figure 5.10.6: Switch/Sample Window Menu

Figure 5.10.7: Layer Cost Rules Menu

Sets layer routing cost. A layer can be set as free for
route to forbidden for route. Use this menu to persuade
auto router to use/not use certain layers.
Figure 5.10.8: Setup Noise/Crosstalk Rules Menu

Set VCR how to check noise/crosstalk rules.
❒ Define Menu
Use Define Menu to define routing objects, design properties, wiring polygons, keepouts/fences/
boundaries, etc. From the menu bar, click Define to bring up Define pull down menu:
Figure 5.10.9: Define Menu
Define I/O Port and other wiring polygons
Class: a set of nets

Group set: a set of group
Define routing objects Group: a set of fromto
Region: a certain area
Net pair: a pair of nets
Bundle: a set of nets
Define design properties
Define Fence/Keepout/Boundary
Define Bindkeys/Rulers and forget net rules
Figure 5.10.10: Define I/O Port Exact Menu

Define I/O ports by coordination in this menu.
User can also select to draw a wire polygon, then define
it as an I/O port.
Figure 5.10.11: Define/Forget Class by List Menu
Define and undefine class by this menu. First click Create Class to specify class name, then click
to select nets from the list. The define menus for other routing objects are similar.
Figure 5.10.12: Design Grids Menu:
Use this menu to set design grids and grids for other routing objects.
Figure 5.10.13: Define/Forget Layer Properties Menu
Use Define/Forget Layer Propertied Menu to set electrical and other properties for layers. By
default, VCR and translator will not get capacitance and resistance and other properties from tech-
nology file. If user sets capacitance and resistance matching for routing, user has to set capacitance
and resistance property of layers. User can also add User Defined Properties for layers in this menu.
Figure 5.10.14: Define Keys Menu
Use this menu to define bindkeys, user can also collect all the bindkey setting commands and save
them into a do file.
Command Example:
Define a class named addr consisting of nets addr0, addr1, addr2 and addr3:
define (class addr (add_net addr0 addr1 addr2 addr3))
Define a group named bbgrp consisting of two fromtos from different nets:
define (group bbgrp (fromto |Ipua-pinp |Ipub-pinn)
(fromto |Ipua-pinn |Ipub-pinp))
Define a net pair and set their metal 1 wire spacing as 0.9 um:
define (pair (nets net_p net_n (gap 0.6(layer met1))))
User can also define pair by wild card matching:
define (pair (nets ?_p ?_n))
define (pair (nets ??_p ??_n))
define (pair (nets ??????_p ??????_n))
Define a wire keepout by (XL YL XH YH) coordinates:
define (wire_keepout keepout1 (rect met1 0 40 20 50))
Two classes, rdata and addr, need to be separated at least 2 um:

define (class_class (classes rdata addr) (rule (clearance

2)))
Define bindkeys: control-4 as zoom in and control-3 as zoom out.
defkey (4 ctrl) (zoom in)
defkey (3 ctrl) (zoom out)
❒ Net Ordering and Virtual Pin
A net in VCR is saved as a net name and a set of component pins and I/O ports connecting to this
net. For a net with more than 2 pins, there can be multiple ways to connect these pins together. The
way to set the sequence of connecting these pins is to set net order property. There are two major
types of net ordering: Starburst and Daisy.
By default, all nets are ordered as starburst. Starburst order permits multiple entries and exits on
each pin, so it is the most flexible order of nets and easiest for auto-router to find a routing solution.
The other type of net order is Daisy. User can also set a net to be Mid-Driven Daisy or Balanced
Daisy. When a net is set to be routed as a daisy-chain, pins in the net need to be specified as sourc-
es, loads, or terminators. If user does not assign these pin properties, the auto-router treats all pins
on a daisy-chain net as loads and routes them in a chained fashion in an optimum order.
Use GUI menu to set net ordering and pin attributes:
To set net ordering: Click Rules -> Net -> Wiring
To set pin attributes: Define-> Pin Attributes
Figure 5.10.15: Net Order

Source
Terminator
Load Terminator Load
Load
Load Load Load
Starburst Daisy
Source
Source
Load Load Terminator
Load Load
Source Source Load Load Terminator
Load Load Terminator Load Terminator
Balanced Daisy Mid-Driven Daisy
Use command line to set net ordering and pin attributes:

To order net clk as daisy and a class data as daisy:
rule net clk (reorder daisy)
rule class data (reorder daisy)
To order all nets as starburst:
order starburst all_nets
Set pin b_p on cell I12 to be source:
assign_pin source I12 (pins b_p)

Using define command to set net clk to be routed starting from cell Idiff1 pin b_p, going through
cell Idiff2 pin a_p, finishing at cell Iload pin b_p:
define (net clk (order Idiff1-b_p Idiff2-a_p Iload-b_p))
Other than set nets as daisy chain, user also re-order nets by defining fromto:
define (net clk (fromto Idiff1-b_p Idiff2-a_p) (fromto

Idiff2-a_p Iload-b_p))
User can also set net ordering by component sequence:
define (net clk (comp_order Idiff1-b_p Idiff2-a_p Iload-

b_p))
Define Virtual pin to split a fromto:

Figure 5.10.16: Virtual Pin
A B
B
Component
A
Virtual Pin
C C
Add virtual pin to net
Use command line to add a virtual pin to net clk and reorder clk:
define (net clk (fromto CELL1-a_p (virtual_pin VP1))

(fromto (virtual_pin VP1) CELL2-b_p) (fromto
(virtual_pin VP1) CELL3-a_p))
If length matching between multiple clock branches is required, user can do this by:
1. Set the net starting from source pin, connecting to a virtual pin, then distributing to multiple load
pins.
2. Set group (fromto) matching rule to match the wire length.
Caution: Do not define virtual pin for differential pairs/bundles. Auto-router can not route differ-
ential pairs with virtual pin definition.
Section 11: Auto-router
❒ How does auto-router work?
There are two routing phases:

• Initial phase
• Convergence phase
Auto-router tries to route the design by 5 different kinds of algorithms. Each kind of algorithm is
run for a “pass”, then the next algorithm, until all the nets are routed, all the conflicts are cleaned
and all the layout rules are met, or if VCR can not find a routing solution, it will stop if number of
passes reaches route command setting.
The initial phase runs for 5 passes. During initial phase:
• The conflict cost is set to low by the auto-router, so connecting all the nets has a higher priority
than having a clean route.
• In the next pass, all routed nets are ripped up then rerouted for the best solution.
The convergence phase starts at pass 6:
• Router will run pass by pass until all nets are connected and all conflicts are fixed (0 uncon-
nects, 0 conflicts) or routing pass counter reaches user set limit.
• Only the nets close to conflicts are rerouted.
• The cost of conflicts increases every five passes. That means auto-router will focus more and
more on fixing conflicts.
• Previously routed nets and vias may be shoved to open space for route.
Clean passes are normally run after route passes. Clean is nothing special but another kind of route
algorithm. Clean passes reroutes every wire to:
• Change wire path to make wire shorter.
• Remove excess bends and jogs
• Reduce via usage
• Fix clearance violations and other conflicts.
If auto-router can not reach a satisfied result, user can try more passes. The rule of thumb is if the
auto-router can not find a routing solution after 75 passes, include auto-route and clean passes, the
result is the best auto-router can achieve. There is no meaning for user to try more. If user is still
not satisfied with the result, try to adjust the floorplan or manually fix some critical nets, then re-
run auto-router.
❒ Route Command
To run auto-router, user can specify route passes, start pass and -remove option:
route 25
route 25 16
route 25 16 -remove
Here 25 is the number of passes to run, 16 is the start pass, -remove option tells router to delete
conflicting wire and mark unconnects with flight line.
There is an exception about -remove option. If user defines some nets as bundles/pairs then auto-
routes with -remove option, conflicts on these nets will not be removed.
If user doesn’t specify start pass, auto-router will determine the start pass based on current com-
pletion level. That means if you run:
route 25
route 25
The second route 25 will not start from pass 1, but will start from a pass calculated from completion
level after first route 25.
❒ Clean Command
User can specify number of passes to run clean. For example:
clean 4
The number must be a positive integer.
❒ Post Route touch-up
Use post route function sto improve routing quality. Click Autoroute->Post Route to bring up
the post route menu:
Figure 5.11.1: Post Route Menu
Critic Removes extra bends without performing rip-up and reroute opera-
tions.
Shield Routes shield wires around wires of nets that have a shielding rule.
Filter Routing Removes final routing conflicts by executing route passes that in-
crease the conflict cost and minimize the number of unconnected
wires.
Center Wires Moves single wire segments so that they are equidistant between ad-
jacent pins of a component.
Spread Wires If space is available, adds space between wires, and between wires
and pins.
Testpoints Controls test point insertion.
[Un] Miter Corners Changes 90 degree wire corners to 135 degrees
Remove Notches Eliminates same net notch violations. Instead of “remove” the notch,
it actually “fill” up the notch.
End Cap Corrects end cap and minimum area violations if there is sufficient
space
Fix Wire Extension Violations
Fix wire extension rule violation. Wire extension rule is for wire ex-
tension over contact. This is a new function in version 10.0.14.
❒ Advanced Routing Topic
Differential pair/Bundle/Bus Routing:

User can define differential pairs and/or bundles with the Define menu. Wires of differential pair
and bundles will be routed with same topology and spaced by gap setting or default layer clearance
rule. If design has a congested floorplan, auto-router will generate crossings and clearance rule
conflicts, because of the requirement to route two or a bunch of wires with the same topology. User
needs to manually fix these conflicts using interactive routing function.
As discussed before, auto-router honors routing rules by level. If a higher level rule collides with
lower level rule, auto-router will discard lower level rule and honer higher level rule. Differential
pair and bundle routing rules are apart from these rule levels. There is not a specific level that pair/
bundle rules reside. If a net pair is set both as a class and a pair, and length matching rule is also
set for the class, auto-router can not determine which rule to follow in times of rule conflicting, for
example, same topology or length matching. If more rules were specified for a differential pair,
auto-router may end up not routing this differential pair.
The limitations with differential pair/bundle routing are:
• If you define pair/bundle and route with -remove option, crossing and clearance rule conflicts
will not be removed on pair/bundle wires.
• If some nets were defined both as differential pair/bundle and class, class length matching rules
were also set for these pair/bundle nets, many unnecessary conflicts will be generated on these
nets. User have to loose the length matching limitation to avoid conflicts.
• If user defines Virtual Pin on differential pair/ bundle, auto-router will not route pair/bundle at
all.
• If user draws top level pins in Virtuoso with dg/pn layer pairs, then defines two pins to be part
of a differential pair, auto-router will not route to these two pins.
• There is no way to automatically run parallel shielding wires for differential pairs/bundles.
If gap rule is not specified, differential pair wire will be spaced by default minimum wire spacing
rule. That will generate unnecessary jogs while changing layers.
Figure 5.11.2: Set larger gap for differential pair/bundle
Via Contact
met1 to met1 spacing: 0.6um
Jog
Gap Setting to avoid jog
Metal1 Metal2
Figure 5.11.2 shows for a certain technology, minimum metal1 to metal1 spacing is 0.6 um. Auto
router will by default, route differential pair by this gap. Because metal1 extends over via contact,
auto-router has to add a jog to walk around via contact to avoid clearance rule violation. To avoid
this jog, you can specify larger gap spacing for differential metal1 wires. For example:
define (pair (nets net_p net_n (gap 0.9 (layer met1))))
Wire Shielding
There are three types of shielding, parallel, tandem and coax. Parallel shielding is the mostly used.
Shielding wire encloses the entirety of the net you specify. You can also specify shielding width
and overhang values, as well as specify spacing between shielding wire and shielded wire. Limi-
tations of using shielding wire are:
• VCR can only automatically route shielding wire for one net. There is no algorithm to shield
differential pairs or bundles.
• You have to specify shielding net. Most of time, shielding net can be either vpwr or vgnd. There
is no way to automatically select closest net for shielding.
• You can not shield a supply line.
• You can not use noise rules with any net that is shielded.
• Shielding wire imposes a lot of space penalty.
Wire Extension
Some technologies requires metal wire to extend beyond the center of the contact/via cell for a cer-
tain amount, or use different kind of vias according to the direction the wire enters and leaves the
contacts. VCR can not automatically change a via instance after it has been placed in layout, so this
requirement has to be met by automatically extend wire beyond a square via instance.
Figure 5.11.3: Wire Extension Rule

Wire Extension over square via Two kinds of via
Metal 2 direction
Wire Extension
Metal 1 direction
Metal 1 direction
Metal 2 direction
Via Metal 1 Metal 2
Wire extension was first implemented in VCR V10.0.14 under menu Route->Post Route.
The limitations of Post-Route wire extension:
• Post-Route wire extension can only make wire extension if there is space available. Auto-rout-
er will not honor wire extension rule during routing, thus will not keep space for wire extension.
The work around for this limitation is to set larger wire-contact clearance rule or manually fix
the remaining wire-extension violations. VCR does have the reporting capability of wire-ex-
tension rule violations.
• Wire extension rule currently only works with via_images, not via_arrays. This means it only
work with single cut contact layout views, not symbolic vias or Pcell vias. So user has to define
via image contact cell in Virtuoso and via image definition in .img file.
• Wire extension rule only applies to layer level. For example, user can only set wire extension
rule for metal 1 layer, not for li/metal1 contact. There is no way to set wire extension rule to
make metal1 extend only on li/metal1 contact and not extend on metal1/metal2 contact.
Wire_extension rule usage:

• Define wire_extension rule
Click Rules->Layer->Wiring to bring up the Layer Wiring Rules dialogue box.
Click Pick Active Layer field to select applying layer.
Type wire-extension length setting in Wire Extension field in Layer Wiring Rules dialogue
box. This length is the wire extension length from the center of via contact. So you have to cal-
culate this distance if only the requirements of wire extension from edge of the via contact is
known.
Click OK or Apply.
• Set check wire_extension rule

Click Rules -> Check Rules -> Setup and Check to bring up the Setup/Check Rules di-
alogue box.
Select Wire Extension check box.
Click OK or Apply.
• Post-Route wire_extension
Click Autoroute -> Post Route -> Fix Wire Extension Violations to bring up Fix Wire
Extension Violations dialogue box.
Select Check Clearance Violations and Push Wire and Via During Fix.
Click OK or Apply.
• Check wire_extension rule violation

Click Report -> Specify to bring up Report Specify window. Then select
Wire Extension Violation to report wire extension violation in a list.
Or:
Click View -> Visit to bring up Visit window. Then user can use visit function zooming to
every single error spot.
Section 12: Using VCR reports to check routing results
VCR has a great reporting function for designers to check routing result.
❒ Report Menu
Click Report to bring up Report menu:

Figure 5.12.1: Report Menu
Various reports can be generated from this menu. When viewing a report in the report window, the
tool creates a temporary file for the report in user’s temporary directory.
Figure 5.12.2: Route Status and Wiring Statistics Report
Status
Summary
Routing
Perform
-ance
of each
pass
Wiring
Status
Summary
Layer
Usage
Table
Routing Status report provides a comprehensive routing status with following information:
• Status summary
• Auto-routing pass names or functions
• Routing performance and result of each pass
• Wiring Statistics summary
• Layer Usage Table
Figure 5.12.3: Network Report
Network Report presents the wiring summary of all the nets in the design. User can browse this
report to check the length matching between different nets.
Net Report presents the detailed information of each net, includes: net statistics summary, differ-
ent level of rules applied on each net and detailed information of each single wire segment of net.
Rules Report lists all the rules applied in the design and their detailed information. User can check
rules report to make sure rules are set correctly.
❒ Highlighting
Click View-> Highlight to bring up Highlight menu:

Figure 5.12.4: Highlight Menu
Use highlight menu to highlight routing objects.
User can also select different highlight colors when high-
lighting “By List”. For example, highlight different nets
with different colors in Nets By List... mode.
Click Off to turn off highlights.
Other than highlighted by highlight menu, a selected rout-
ing objects will always be highlighted.
❒ Visit Menu
Click View-> Visit to bring up Visit Menu:

Figure 5.12.5: Visit Menu
Use Visit Menu to zoom to different layout errors in design. Errors includes:
• Various conflicts and rule violations
• Wire bends, incomplete wires, redundant wires, wires less than minimum process width
• Pins without escape, inaccessible pins, off grid pins, pins smaller than process requirements
• Off grids and off manufacturing grids routing objects
User can also set the zooming scale to visit the errors.
Section 13: Introduction to Cadence Chip Assembly Router
Cadence Chip Assembly Router (CCAR) adds global planning capability onto VCR to deal with
larger scale whole chip level hookup.
❒ How CCAR differs from VCR
CCAR is just VCR plus global planner. CCAR design flow has two parts: global pre-route and de-
tail route. CCAR’s detail route flow is exactly the same as VCR.
CCAR has global planning capability. Global planner divides the whole design into global cells
(gcells) and uses a channel router based algorithm to analyze these gcells, it then returns the global
planning information to detail router. This global information will guide the detail router into a
quicker routing solution. Global planner has two major parts: global router (groute) and track rout-
er (troute).
❒ Run CCAR
Groute and troute licences are only available in CCAR. Although they are listed in VCR Autor-
oute menu, user can not use them in VCR.
To run CCAR, go to exported design directory and type:
ccar ****.dsn
CCAR window is identical to VCR window. The only difference is you have more effective func-
tion in CCAR.
❒ Groute and Troute
Global planner has two major parts: global router and track router. Global router (groute) just an-
alyzes the design and determines a path using gcells, Groute does not route any wire into design.
Track router (troute) must run after groute. Troute uses the result from groute and pre-routes tracks
into design, detail router will then use these tracks to finish routing.
Groute and Troute use channel router type algorithm to analyze the whole design. Their analysis
is based on routing direction setting and other routing rules.
Groute and troute do not consider differential pair/bundle rule setting. If there are many differential
pair/bundle nets to route in design, user can still use groute, but do not use troute in this kind of
design. Troute will route tracks regardless of differential pair/bundle setting, then detail router will
use these tracks to find a routing solution quickly and forget about pair/bundle rule setting. Pair/
bundle rule setting are only recognized during routing/re-routing.
Groute Usage:
Before run groute, user must set CCAR local layer routing direction, by click Autoroute -> Set-
up -> Chip Assembly:
Figure 5.13.1: Local Layer Directions for Chip Assembly
Set groute to follow either layer panel routing direction setting or conduit routing direction setting.
Select Layer Panel means set preferred layer global routing directions same as those setting in layer
panel, and conduit routing direction is explained below:
Figure 5.13.2: Conduit Local Layer Direction Setting

Horizontal Conduit
Conduit
Vertical Conduit
Metal 2
Metal 1
Via
In Figure 5.13.2, Preferred global routing direction of Metal 2 is set perpendicular to conduit and
Metal 1 is set parallel to Conduit.
User can also set conduit routing direction by command line:
local_direction layer_panel
local_direction conduit (parallel_layer poly met1)
(perpendicular_layer li met2)
To run groute, click Autoroute-> Global -> Global Route to bring up Global Route menu:
Figure 5.13.3: Global Route Menu
Specify passes to run groute, then click OK.

Or user can run groute by command line:
groute 3
To run troute, click Autoroute-> Global -> Track Route to bring up Track Route menu:
Figure 5.13.4: Track Route Menu
User can specify an area to run troute. If area is not specified, default is whole design.
Click OK to run troute.
Or user can run troute by command line:
troute
In the design window, you will see pre-routing tracks.
❒ Detail Route after global route
After global route, user can use normal auto-route command and interactive routing function to fin-
ish routing. User will see auto-router finding a routing solution much faster than without running
global router.
Figure 5.13.5: Typical Design Flow with Global Routing
Placement
Interactive route (critical nets)
Groute
Troute
Auto-route
Interactive route (touch up)

Section 14: Save Result and Translate back to Virtuoso
❒ Files VCR Reads and Writes
Figure 5.14.1: Files VCR Reads and Writes

Place and route
Session
Keepouts Wire
Wire and via
Routes
DFII VCR
Network
Conflicts
Design Image ViaImage/Arrays

Subcell for higher Did File
level design log file Wire Load
Environment Report & documentation
Environmental setting
VCR saves results by “writing” files. Click File->Write to write various result files.
The session file can be imported back to Virtuoso, it contains the original design file name as well
as placement, floor plan, swap, netlist, and route data generated during a session. VCR can read
the keepout information from session file.
Wire and route files can be used to save intermediate routing result and reload the files to finish
routing. They contain wire and via information. Route files can also save guides and global paths.
VCR can also write files for report and documentation purposes. Network file saves all the netlist.
Conflict file records all the routing errors. Via Image/Arrays file records all the via image and via
array used in design. Wire Load file lists lumped capacitance and lumped resistance values for nets.
VCR records every operation in a did file. It is the same as the CDS.log file for icfb.
You can also save all your VCR environment setting, such as color map and bind key setting, in
an environment file.
The design image file contains image data about the current design layout in a library format. You
can use this file for the next higher level design.
❒ Best Save
Best save function will automatically write the routing result into a wire file whenever routing re-
sult improves.
Click File -> Best Save to bring up Best Save Menu.
Figure 5.14.2: Best Save Menu
By default, best save will write the current best wiring into ./bestsave.w file. Other than default,
user can specify a filename for best save to use. User can select Enable or Disable best save, then
click OK or Apply.
❒ Translate back to Virtuoso
After routing in VCR, you should save the result into a session file, click File->Write->Session.
Then go back to Virtuoso layout window, click Route->Import from Router to bring up Import
from Router menu:
Figure 5.14.3: Import from Router Menu
Make sure Import Layout Cellview field lists the correct library, cell and view name.
Make sure Import Router File field lists the session file you want to import back to Virtuoso.
Click OK to translate back to Virtuoso. Layout view will be automatically updated and saved.
Caution: Layout view will be automatically saved (overwritten) after Import from Router.
Once the session is imported into Opus, user can not undo the import operation. It is always a good
paractice to backup the layout view before import.
Section 15: Further Reading
If you have any questions about any menus in VCR, just click Help button on the menu, a detailed
explanation will show up.
For more information about command line inputs, please read Design Language Reference under
Online Books in the help menu.
Page 131 last modified 6/27/05 Calibre
Chapter 6: Calibre
All Calibre documentation is found at the path http://www.miss.cypress.com/doc_4.4/layout/

layout.html.
List of Figures
1.1.1 Layout Design Flowchart 5

2.5.1 Pins/Labels from Schematic from Cypress Menu 14
2.5.2 P2L Main form to Place Rail Pins 15
2.5.3 Drawing Placement Shape and Final Pin Placement of Pin 15
2.6.1 Iterated Pin Creation from Cypress Menu 17
2.6.2 Iterated Pin Creation Form 17
2.6.3 Row Pins Iteratively Created and Placed 18
2.7.1 Iterated Selection from Cypress Menu 19
2.7.2 Iterated Selection Form with SKILL Routine and Selection Area 20
2.7.3 Objects Captured with Iterated Selection 21
2.8.1 Place Bus from the Cypress Menu 23
2.8.2 Initial “Rubberband” Routing Segment and Continued Horizontal Routing 24
2.9.1 Pin Check and Fix from Cypress Menu 25
2.9.2 PINfixTool GUI Form with a selected set 26
2.9.3 Pin Highlighted with “li” (dg) layer and Corrected Pin with “li” (pn) layer 27
3.4.1 Example Resistor Layout 37
3.5.1 Example Fuse Layout 38
3.6.1 Example Short Layout 38
3.7.1 Example Metop Layout 39
3.8.1 Example Serif Usage 41
4.3.1 Layer Pattern Table 47
4.3.2 Created Layers Fill Example 48
4.3.3 Created Layers Notch Example 49
4.3.4 NSDM/PSDM Example 51
4.4.1 Waffle pattern generated on FOM (larger) and P1M masks (smaller squares) 53
5.1.1 Must Join, Strong and Weak connected pins 57
5.2.1 Typical VCR design flow: 59
5.4.1 DFII to ICC Translation Flow 62
5.4.2 Export to Router Menu: 63
5.5.1 VCR design file structure 66
5.6.1 VCR Window 69
5.7.1 Interactive Place Menu 73

5.7.2 Interactive Placement Setup Menu - General 74
5.7.3 Interactive Placement Setup Menu - Alignment 75
5.7.4 Interactive Placement Setup Menu - Move 76
5.7.5 Move Comp Menu 77
5.7.6 Alignment Marks: 78
5.8.1 Interactive Routing Setup - General 79
5.8.2 Interactive Routing Setup - Measure 81
5.8.3 Interactive Routing Setup - Bus 82
5.8.4 Interactive Routing Setup - Style 83
5.8.5 Interactive Routing Setup - Move/Copy 84
5.8.6 Interactive Route a wire 85
5.8.7 Interactive Routing - add via 86
5.8.8 Interactive Edit Route 87
5.9.1 Layer panel 89
5.9.2 Costs Menu 92
5.9.3 Setup/Check Rules Menu 93
5.10.1 Clearance Rules Menu 96
5.10.2 Wiring Rules Menu 97
5.10.3 Timing Rules Menu 98
5.10.4 Shielding Rules Menu 98
5.10.5 Crosstalk Rules Menu 99
5.10.6 Switch/Sample Window Menu 99
5.10.7 Layer Cost Rules Menu 100
5.10.8 Setup Noise/Crosstalk Rules Menu 100
5.10.9 Define Menu 101
5.10.10 Define I/O Port Exact Menu 101
5.10.11 Define/Forget Class by List Menu 102
5.10.12 Design Grids Menu: 102
5.10.13 Define/Forget Layer Properties Menu 103
5.10.14 Define Keys Menu 103
5.10.15 Net Order 106
5.10.16 Virtual Pin 107
5.11.1 Post Route Menu 111
5.11.2 Set larger gap for differential pair/bundle 113
5.11.3 Wire Extension Rule 115
5.12.1 Report Menu 117

5.12.2 Route Status and Wiring Statistics Report 118
5.12.3 Network Report 119
5.12.4 Highlight Menu 120
5.12.5 Visit Menu 121
5.13.1 Local Layer Directions for Chip Assembly 123
5.13.2 Conduit Local Layer Direction Setting 124
5.13.3 Global Route Menu 125
5.13.4 Track Route Menu 125
5.13.5 Typical Design Flow with Global Routing 126
5.14.1 Files VCR Reads and Writes 127
5.14.2 Best Save Menu 128
5.14.3 Import from Router Menu 129
List Of Tables
1.2.1 Layout Automation Tools 6

2.4.1 SDL Utilities 12
3.1.1 Layer List in V4.4 28
3.1.2 Purpose List in V4.4 33
3.10.1 Areaid Layer Descriptions 42
Index
Symbols
~/.cdsenv 36
A
areaid 32, 42
array 29
B
bcdiode 41
bnm 30
bus 6
C
capm 31
cblm 31
cbnm 30
ccpm 31
CCT 6
cctm1 30
cdnm 31
cdpm 31
cfim 30
cfom 30
cfpm 31
cfsdm 31
cgpm 31
chvi 31
cli1m 31
clicm1 32
cmm1 30
cmm2 30
cmm3 30
cmm4 31
cmm5 31
cnsdm 30
cntm 30
cnwm 30
colors 12
contact 22
core 33, 42
cp1m 30
cpbm 31
cpdm 30
cpf 31
cprim 31
cpsdm 30
cpsm 32
cputm 30
cpw 32
cpwm 30
cpwpm 31
created layer 45
created layers 7, 39
crem 32
crfam 31
cross view check 7
Cross-Probe 12
crwm 32
ctunm 31
cut 33
cviam 30
cviam2 30
cviam3 30
cviam4 31
cvte1 31
cvte2 31
D
device library 11
dieCut 33, 42
diff 28
dimp 29
diode 34
display.drf 12
displayPinNames 10, 36
drawn 45
DRC 7
E
edge 10
esd 33, 42
F
famossd 30
fieldless 43
fpcon 29
fpoly 29
frame 33, 42
frameRect 33, 42
fuse 34, 37
G
gap 57
gate 34, 43
grid 22
H
Hspice 8
I
ICcraftsman 6
infix 10
iterated 16, 18
Iterated Pin Creation 6, 16, 18
Iterated Selection 6, 16, 18
L
label 34
layers 12, 28
Layout 10
leadframe 27
li1 29
licon1 30
LVS 8
M
mask 33, 45
mask layers 39
maskAdd 34, 40
maskDrop 34, 40
mcon 28
met1 29
met2 29
met3 29
met4 29
met5 29
metop 38
moduleCut 33, 42
N
net 35
net labels 36
netlist 8
netText 36
npn 32, 41
NSDM 48
nwell 28
O
option 34, 38
P
P2L 13, 27
pad 29
partialSelect 10
pcell 11
photoresist 39
pimp 29
pin 6, 16, 35
Pin Check and Fix 6, 24
pin2lay 13
PINfixTool 18, 24
Pins/Labels from Schematic 6, 13
pinText 35
pitch matched 6
Place Bus 6, 22
placeBus 22
Placement 12
pnp 32, 41
poly 28
PSDM 49
pwell 28
pwpm 29
R
regular 16, 18
res 33, 37
resistor 37
rimp 32
ring 43
route 22
routing 22
S
Schematic to Layout 12
SDL 6, 12
seal 33, 42
select 18
Select Instances 12
Select Net Instances 12
serifs 40, 46
short 33, 38
Silicon Ensemble 6
snap spacing 10
standard cell 6
stretch 10
symbolic 11
T
tap 28
target 32, 37
TDR 7
terminal 35
Timemill 9
V
via 29
via2 29
via3 29
via4 29
Virtuoso 10
X
xSnapSpacing 10
Y
ySnapSpacing 10

Layout Design Entry, Verification, and Automation User Guide

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Layout Design Entry, Verification, and Automation User Guide

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Layout Design Entry,

Verification, and Automation

Layout Design Entry,

Chapter 1: Overview of the Layout Design Flow

Section 1: Overview of the Design Flow

Figure 1.1.1: Layout Design Flowchart

DRC Simulate Extremely

Created Layer Move On to the

Section 2: Generate Layout

Tool Name Description

Pins/Labels from Sch... Speeds pin placement in the layout.

Section 3: Check Nets and Pins

Section 6: Netlist and Simulate

❒ Extract the full chip for a Timemill simulation.

Section 1: Suggested Settings

Section 2: The Device Library

SDL Utilities Function

SDL has the following capabilities.

Section 5: Pins/Labels from Schematic

Section 6: Iterated Pin Creation

Figure 2.6.1: Iterated Pin Creation from Cypress Menu

Figure 2.6.2: Iterated Pin Creation Form

Section 7: Iterated Selection

(defun YourSKILLSelection(arg “l”)

Figure 2.7.3: Objects Captured with Iterated Selection

Section 8: Place Bus

Key features include:

Creating a basic metal-2 route within a layout

Section 9: Pin Check and Fix

Figure 2.9.1: Pin Check and Fix from Cypress Menu

Figure 2.9.2: PINfixTool GUI Form with a selected set

Section 10: Leadframe Tool

Chapter 3: Design Entry Layers

Section 1: Opus 4.4 Layer List

V4.4 Purpose Purpose

V4.4 Purpose Purpose

Section 3: Net Labels

Figure 3.5.1: Example Fuse Layout

Section 8: Mask Layers

❒ Created Drawing Purpose Layers

❒ Created maskAdd and maskDrop Purpose Layers

Figure 3.8.1: Example Serif Usage

Section 9: BJT Devices

Section 10: Special Areaid Layers

Purpose LSW Description

Section 11: Unusual Transistors

Section 12: Boundary Layers

These layers are used to control routing for IC Craftsman.

Chapter 4: Created Layers

Section 2: Modifying Created Layers Directly

Section 3: Created Layers Algorithms

poly added layer

Figure 4.3.3: Created Layers Notch Example

Figure 4.3.4: NSDM/PSDM Example

Section 4: Waffling procedure

Chapter 5: VCR User’s Guide

❒ What VCR can do?

Must Join Pins Weak Connected Pins Strong Connected Pins

These terms are about identical pin connection requirments.

Must Join identical pins of a cell requires to be connected by exter-

Section 2: VCR Design Flow

Figure 5.2.1: Typical VCR design flow: