DQ_V1.

41 Circuit Diagram

J.W.Hwang

2004 02 02
1 TC8 1 TC9
C25 C23 C35 C33 C32 C22 C30 C20 C31 C26 C34 C36 C29 C19 C24 C21 C3 C6 C4 C2 C1 C7 C5

0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF

2 10uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF
2 10uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF

V1.41(DS0402001)

1 8
2 7
3 6

4 5

DR_CLK

PWR SEQUENCING,
PLACE CLOSE BY

S D 1 2 FLASH PROGRAMMING
MBRS140
G
6
VCC

2
RSTN
3 1
WPN RDY_BSYN
11 14 3
CSN SO
12
SCK
13
SI
2
GND

1
7

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 DQ_V1.41 Circuit Diagram

J.W.Hwang

2004 02 02

C77 29 30 14 24 3 8 40 42 44

0.1uF 1 TC11 C85 C84 C83 C71 C76 C80 C79 C78

2 47uF 0.1uF 1uF 1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF

V1.41(DS0402001)
R106
5.6/2012_1608

R104
5.6/2012_1608 PR-MS-110-T
PS1 1 2

J3
R100
1 9 3
5.6/2012_1608
4

R118

DNE/2012_1608
R103 1 1
R120 C104 3 11 2
5.6/2012_1608
2 14 2
0 22uF

4 16
6
5 5
2 8
1
7 7

1500pF/2012_1608
R116
PS3 PR-MS-110-T

DNE/2012_1608
DNE/2012_1608
R114
6 RJ11

C102
8

R90 R96 C101

680pF/2012_1608

34.8/2012_1608 0/2012_1608 0.027uF/3225/2012

150pF

150pF
150pF
150pF
C92

6 5
R98
C96

C112

C111

C109

C110
0.082uF/3225/2012 402/2012_1608

R84
R86

0/2012_1608

F F
DNE/2012_1608 10 1
R94
0/2012_1608
C94 0.082uF/3225/2012
C108

R88 0.022uF/polycap
R80 C88 R92 C98

49.9/2012_1608 0.01uF/2012_1608 34.8/2012_1608 0/2012_1608 0.027uF/3225/2012

R108

49.9/2012_1608
R110

DNE/2012_1608
R112

49.9/2012_1608
2

3 3 3 3
1

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 DQ_V1.41 Circuit Diagram

J.W.Hwang

2004 02 02

4 5
3 6
2 7
1 8

8
F
4 5 F
3 6
2 7 V1.41(DS0402001)

1
1 8

3.3VD_DSP

C57 OPTION
DEBUG PORT
0.01uF/2KV

RESET_N

C65 0.1uF

C64 0.1uF

2 F

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 DQ_V1.41 Circuit Diagram

J.W.Hwang

2004 02 02

J1 1 4
POWER_JACK
1 1 2
3
PR-MS-110-T 2 3
2

USB_DATA_N

USB_DATA_P USB +5V

3
2 V1.41(DS0402001)
4
CONST_CK
5
6

1
F 1 2

1 2

1 2

3 TAB 2 1 2
IN OUT

1
1 1

ADJ 2
2 1 2

1 2
1N4OO1
2

1
1

3 TAB 2
IN OUT

ADJ 2

1
4 2
OUT VCC

3 1
GND VIN GND

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