Digital Design I

Lab #2
William Taylor
9/30/2019
wjtaylor@uark.edu
Abstract

In this lab I used Quartus Prime to create a Schematic of the logic function :

F= Á ∙ B́+ Ć ∙ D́ . After creating the schematic, I compiled it to make sure it compiled. The next
step was to give each input the correct name, so the FPGA could understand the software. Next, I
turned on and setup the hardware so that it can run the schematic on the board. In the end the
circuit board displayed the NAND circuit above. If A and B were both ‘0’ or if C and D were
both ‘0’ the LED lit up.

Introduction

In this lab we need to know how to understand basic logic functions, like AND, OR, and
NAND functions. We also need a basic idea of how to draw schematic functions. The name of
the hardware we are using is called an “FPGA”. The name of the software we are using is
“Quartus Prime”. Other than this information the rest of what we need to know is learned
through the lab.

The purpose of this lab is to implement the function F= Á ∙ B́+ Ć ∙ D́ onto an FPGA. A
sub task is to gain experience using Quartus Prime by creating a schematic, compiling the
schematic, learning where to save files, learning how to add hardware, and learning how to sync
a FPGA and Quartus Prime together. The expect result of this lab is to have the FPGA’s LED
light up when A and B are both ‘0’ or if C and D are both ‘0’. This is also known as a NAND
gate.

Design and Implementation

First, we have to create a new project. This is done by selecting “new project wizard” on
the home screen of Quartus Prime. Next, create a new folder to store this file and future files.
Since a template isn’t needed, I made a new file. The program will prompt us to select a device. I
selected ‘5CSEMA5F31C6’ because this is the device, we are supposed to use. After this the
new file is created and a summary report will pop up.
 In order to finish compiling the schematic has to be drawn into the file.

F= Á ∙ B́+ Ć ∙ D́ is the function we are trying to implement. After creating a new block
diagram/Schematic file I added two NAND gates and an OR gate. A and B went into one NAND
gate. C and D went into another. These two gates will only be active high when both of their
respective inputs are ‘0’. The two outputs are inputted into a OR gate so the LED will light up if
only one of the gates is active high. Active high is when the load in a line is ‘1’, active low is
when the load in a line is ‘1’. The truth table and Schematic are below.

A B C D F
1 1 1 1 0
1 1 1 0 0
1 1 0 1 0
1 1 0 0 1
1 0 1 1 0
1 0 1 0 0
1 0 0 1 0
1 0 0 0 1
0 1 1 1 0
0 1 1 0 0
0 1 0 1 0
0 1 0 0 1
0 0 1 1 1
0 0 1 0 1
0 0 0 1 1
0 0 0 0 1

After the schematic is done it is important to assign the pins to values the FPGA can
understand. The inputs are PIN_AB12, PIN_AC12, PIN_AF9, and PIN_AF10. The output is
PIN_V16. After the pins are assigned the program will compile, the following is my Compilation
report.

Now that the schematic part is done, we need to setup JTAG mode. This is what will
enable the FPGA to run the schematic. It is important to use 5CSEMA5 instead of 5CSEBA5
because the FPGA might not work with the wrong one selected. It is also important to delete the
default file in the program and replace it with the schematic. After the correct file is inserted and
the correct hardware is detected the FPGA can be turned on and will run the schematic.

Results

The results of this lab were exactly as expected. When switch 1 and 2 (PIN_AB12 &
PIN_AC12) were off (active low) and switch 3 and 4 (PIN_AF9, & PIN_AF10) were on (active
high) the LED lit up because switch 1 and 2 were off so switch 3 and 4 were irrelevant. When
switch 3 and 4 were off the LED was on as well because now in this case switches 1 and 2 didn’t
matter. However when switch 1,2,3, and 4 were all active high the LED was off because neither
of the NAND gates had what they needed to make a active high.

This approach worked just as well as the next. There really weren’t very many other
approaches other than replacing NAND gates with AND gates with their inputs inverted, this
would cause the program to nanoseconds longer. As far as accuracy goes this lab was all or
nothing, leaving very little room for the FPGA “kind of working”. In total this lab took about an
hour and fifteen minutes, this is because of my inexperience in Quartus. If I had to do this lab
again it could be done in less than 10 minutes, excluding the time used to compile.

As mentioned before most problems were caused by inexperience. The biggest problem
was programming the pins with the correct locations, this is just because I have never done this
before. Another problem was getting JTAG to detect the FPGA. The fix to this was to simply
turn the device off and wait for a minute before trying to auto detect again. The only other
problem was creating the folder to hold the file. I originally named it “new folder” and when I
went to open my file, I couldn’t find my folder. I fixed this by starting over and naming the file
“Lab”

Conclusion
In this lab we were assigned with the task of implementing the function:
F= Á ∙ B́+ Ć ∙ D́ . By approaching this problem logically one can see that this function can easily
be written with two NAND gates and an OR gate. The harder part is using Quartus Prime to get
the function to show on a FPGA. My approach solved this problem because when testing the
FPGA switches you can see that it represents the function. You can also compare the truth tables
of the FPGA and what the function should be.

This Lab gave me some much-needed experience in Quartus Prime. I am sure that I am
going to need this experience moving forward, both in this class and in other classes. The
experience will probably be useful even after school. This lab also helped solidify my abilities
with different types of logic gates. Specifically NAND and OR gates. The possibilities that
Quartus is capable of will most definitely branch out way past Digital Design. The circuit in this
lab is probably close to the floor in the scale of what can be done in Quartus and other programs
like it and I can’t wait to push these technologies to their limits.