8PSK Demodulation For New Generation DVB-S2
H u a n g zhijie, Yi zhiqiang, Zhang Ming, Wang h a n g
Dept. of Information and Electronic Engineering, Zhejiang University Hangzhou,3 10027,China
E-mail:hzhijie@2 1cn.com
Abstrnct- Through the research of 8PSK demodulation
algorithm including carrier phase recovery and clock timing
recovery, an all-digital 8PSK demodulator adaptive to next
generation Digital Satellite Television Standard DVB-S2 is
proposed. The carrier recovery algorithm consists of a
frequency detector (FD) loop and a modified phase-frequency
detector (PFD) loop. Its tracking range exceeds one time
symbol-rate. The Gardner TED algorithm is used in clock
timing recovery loop. All algorithms are prone to hardware
implementation. By means of analysis and computer fixed
point simulation, the optimal parameter of each loop has been
determined. The symbol error performance under AWGN is
also presented. The result of simulations indicates that the
demodulator performance of SER (symbol error rate) is close
to theoretical value and the architecture is realizable.
Keywords: DVB-S2, 8PSK, SER
I. INTRODUCTION
Recently, with the continuous development of digital
technology, the business of digital video broadcasting has
been making great progress. One of the most important
ways is satellite digital television broadcasting. DVB-S
(Digital Video Broadcasting - Satellite), the main standard
of satellite digital television broadcasting, has been
adopted by most country widely. However, the frequency
resource is more and more rare, QPSK is faced with
challenge for its frequent efficiency is not high. Therefore
the DVB standard organization is proposing DVB-S2
standard, the new satellite digital television standard,
which consists of SPSK modulation and LDPC
(low-density-parity-code) encode. Comparing with DVB-S,
DVB-S2 has many advantages, e.g. the thirty percent
increase in channel capacity, the more reliable
performance, and the more efficient usage of transponders.
Through the research of SPSK demodulation algorithms,
!- tuner
Fig. I BPSK demodulation architecture
0-7803-8647-7/04/$20.00 0 2004 IEEE.
we proposed an all-digital realization architecture. The
second section introduces the realization architecture and
the keystone of demodulation, the carrier recovery and
timing recovery algorithms. In the third section the optimal
parameter of each loop has been analyzed, by means of
computer fixed point simulation, the symbol error
performance under AWGN is also presented. Conclusion is
got in final.
II.8PSK REALIZATION ARCHITECTURE
The SPSK realization architecture is shown in Fig.1.
The signal sampled by ADCs after tuner is demodulated,
then put to the FEC (forward error correct). The
demodulation is composed of a timing recovery loop, a FD
(frequency detector) loop, a PFD (phase and frequency'..
detector) loop and two AGC (auto gain control) loops.
Here we only discuss the first three loops.
A . Carrier Recovery Algorithm
Due to the temperature drift and the frequency
instability, the LNB (low-noise block) in front-end will
introduce large frequency offset, e.g. f 2 MHz, which
must be removed by carrier recovery blocks. Meanwhile
the mix and other process in front-end will result in some
phase noise, which also must be cancelled by carrier
recovety blocks.
The i2 MHz frequency offset is about one time
symbol rate (UT) for ZMbauds, which requires large
acquisition range of carrier recovery algorithm, so we must
make use of some assistant methods, such as frequency
sweep and FD. Because the frequency sweep can not
combine the stability and acquisition time well under large
frequency offset, we adopt FD algorithm. The residual
frequency offset is eliminated by PFD. Fig.2 shows the
diagram of carrier recovery loop.
A A ~
*matched -b timing
-+ f i l t e r + recwerT
*
+
PFD
mix
- to
_+pm
1447
 frE?
,CDA
-

mix
-- - timing
recovery
+
KD
mix
*t
p
0
detector, which requires 2SPS for its operation. One of the
samples coincides with the decision instant. The algorithm
can provide the same timing-error information irrespective
of carrier frequency and phase. Therefore, the timing
recovery can be achieved prior to carrier recovery. To
SPSK, the signals of I and Q must be considered together,
the expression is:

4Fh=F7
e ( ! ) =~ ( l - T / Z ) ( I ( f ) - I ( t - T ) ) + Q ( f - T / 2 ) ( Q ( t ) - Q ( l - T ) )
(4)

timnr
Fig2 Canier recovery loop diagram interpolat ion matched
error
filter filter
detlCt0Y
Much work has been done for FD algorithms, e.g. the
maximum-likelihood based GFD[’’ proposed by Gardner, number e(()
1QOD
and it’s reduced version of RCFDt2]. The two algorithms controlled
oscil lrtor
filer
need the matched filter to be modified, which will result in
higher complexity. Another general frequency detector Fig. 3 Timing recovery loop
algorithm is balanced quadricorrelator, which has been
expounded in [3] and [4]. We adopt its reduced algorithm,
which replaces the differentiator with the T/2 delay. The
m.SIMULATION
ANDANALYSIS
In this section, the optimal parameter of each loop has
expression is as follows. been determined by means of analysis and computer fixed
e(t) = sign(Q(t))I(r- T / 2 )-sign(I(t))Q(t - T / 2 ) point simulation. The symbol error performance under
(1) AWGN is also presented.
The maximum acquisition range of this algorithm is
+ ( l + a ) / T with roll-off f a c t o r a , which satisfies the A . FD Loop
demand of large frequency offset. The FD loop will be FD loop adopts one order loop filter, and the loop
paused after stabilization, and the residual offset is in the bandwidth is decided by gain. With symbol rate IOMbauds
range of 3A/100T, which will be removed by PFD loop. and frequency offset 12MH2, Fig. 4(a), (b), (c)
As well known, MPSK modulated signal can be corresponds to 0.5, 1, 2 of the loop filter gain, respectively.
demodulated by Mth-power Costas loop, whose hardware We can see that the convergence accelerates in larger gain
realization is rather complex for SPSK, so we give it up. condition, however the loop jitter worsens, i.e. the loop
Instead, the polarity-type Costas loop has been adopted”’, stability error increases, vice versa. Considering the
whose expression is tradeoff of convergence speed and stability error, we select
4)= signU(O)Q(t)- s i g n ( Q ( W ( t ) (2) the gain with 1. Then the FD loop can converge soon, and
which is suitable to QPSK. The modifications must be the residual frequency offset doesn’t exceed the range of
done for SPSK as follow, +1/1OOT after leveling off. Meanwhile we can see that
If ImJ leal
>=
e(t)= sign(f(t))Q(t)- sign(Q(t))l(t)K
the acquisition range exceeds * I / T .
o. d
else I
e(t) = si n(f(t))Q(t)K- sign(Q(t))f(t) ( 3 )
with K = & - 1 .
It’s a simple PD (phase detector) algorithm, which must
be improved to PFD for better acquisition performance.
The PD is transformed into a PFD by using a track and
hold logic at the output of the detector. If the constellation
is in the given windows, we get the error by PD, otherwise
we hold the error last time. The theory acquisition range is
in the range of f 1 / 1 6 T . .ma
.c*.~~
,D 11 (1 IL
I in‘

B. Timing Recovery Algorithm Fig. 4(a) gain = 0.5

After anti-alias filters, the timing recovery is processed,
which consists of a timing error detector, a loop filter, a
number controlled oscillator and an interpolation filter. Its
diagram is shown in Fig.3.
The Gardner TED algorithm[’] is used as the timing error

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 Fig. 4@) gain = 1
Flg. 6(a) BW = 8c-4

Fig. 4(c) gain = 2

B. PFD Loop
The phase error and the residual frequency offset canbe Fig. 6(b) BW =4*4
cancelled by PFD loop after FD loop stops. Under the
condition of AWGN, the loop convergence accelerates but - $3'
1
BER performance deteriorates with the iwrease of BW
(landwidth). Meanwhile the BW must be larp enough to
confront, with phase noise. So we must consider the
tradeoff of the convergence Speed and stability emor,
including the ability of resisting t k white noise and phase
noise.
The PFD loop adopts a second order loop filter, and the
gain of loop filter is determined according to t k BW.
The compare of BWs in the ability of resisting the phase
noise is shown in Fig 5(a) and (b). We can conclude thaI
the BW of 4e-4 is better.
rl
^ -111
rp
^1--1^-,
-
4.
7
i
-:j .* Fig. 6(c) BW = 2e-4
!

Fig. S(a) BW = 2e-4 Fig. S(b) BW = 6 4

Fig. 6(a), (b) and (c) show the compare results of BWs
in convergence speed and the ability of resisting the white
noise. We can see that BW of 4e-4 is the best for its
considerate speed and dithering

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 At the same time, the acquisition range of the loop REFERENCES
approaches i1116T with BW equal 4e-4, as show in Fig.
7 with symbol rate IOMbauds and frequency offset [ I ] F.M.Gardner, “Frequency detectors for digital
O.6MHz. So 4e-4 is the optimal BW of PFD loop. demodulators via maximum-likelihood derivation”,
ESA Final Rep: Part 2, ESTEC Contract
C. liming Recovery Loop 8022/88/NL/DG, June 1990.
The timing recovery loop also adopts a second order (21 GKaram and HSari, “A Reduced-Complexity
loop filter, which is similar with PFD loop, so we only Frequency Detector Derived from the
present the loop convergence and the constellation after Maximum-Likelihood Principle,” IEEE Trans.
timing lock, which are shown in Fig. 8(a) and 8(b) Commun., vol. 43, No.10, Oct 1995.
respectively. [3] F.M.Gardner, “Properties of frequency difference
detectors,” IEEE Trans. Commun., vol. COM-33,
pp.13 1-138, Feb.1985.

141 A.N.d’Andrea and U.Mengali, “Design of

quadricorrelators for automatic frequency control
systems,” IEEE Trans. Commun., vo1.41, pp.988-997,
June 1993.
[SI R.v.d.Wal and L.Montreuil, “QPSK and BPSK
demodulator chip-set for satellite applications,” IEEE
Trans. Consumer Electronics, vo1.41, No.1, Feb 1995.
Fig. 8(a) Fig. 8(b)
[6] HSari and S.Moridi, “New Phase and Frequency
IPEX ?En Detectors for Carrier Recovery in PSK and QAM
Systems,” IEEE Trans. Commun., vo1.36, No.9, Sept
.......... .... .._.. . 1988.
I . ,

[7] F.M.Gardner, “Interpolation in digital modem--

Part 1: Fundamentals,” IEEE Trans. Commun, vol. 41,
. . . . pp.502-508, Mar.1993.
~
!
,
!
.
I
.. .
[8] Lars and F.M.Gardner, “Intelpolation in Digital
Modems - ~ Part 11: Implementation and
Performance,’’ IEEE Trans. Commun, ~01.41,June
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[9] EM.Gardner, “A BPSWQPSK timing-error detector
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vol.COM-34, pp.423-429, May 1986.

Fig. 9 SER curve

D.System Performance Simulation
The SER (symbol error rate) curve of demodulator
under AWGN is shown in Fig. 9. In general SNR
(8dB-I2dB), SER curve of fixed point simulation results
approaches the theory one, whose performance loss is
about 0.2dB, and the demodulator can work under rather
low SNR, e.g. 7dB.

n! CONCLUSION
By means of computer fixed point simulation and
analysis, the SER performance approaches the theoretical
value, meanwhile the architecture and algorithms of 8PSK
demodulator is simple and feasible. So this architecture
and algorithms can be adopted in the realization of
DVB-S2 demodulation.

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