DESIGN FOR TEST REPORT

I. Introduction to DFT

1.1. Important of testing.

Testing is one of the most expensive parts of chips Testing is one of the most expensive
parts of chips:
> Logic verification accounts for > 50% of design effort for many chips effort for
many chips.
> Debug time after fabrication has enormous opportunity cost opportunity cost.
> Shipping defective parts can sink a company.
Following the so-called Moore’s law [Moore 1965], the scale of ICs has doubled every 18
months so the defection is unavoidable. The reduction in feature size increases the
probability that a manufacturing defect in the IC will result in a faulty chip. A very small
defect can easily result in a faulty transistor or interconnecting wire when the feature size is
less than 100 nm.

1.2. What is the DFT?

DFT is a technique, which facilitates a design to become testable after production.

DFT makes test generation and test application easier and cost effective. It is the extra logic
which we put in the normal design, during the design process, which helps its post-
production testing. Post-production testing is necessary because, the process of
manufacturing is not 100% error free. There are defects in silicon which contribute towards
the errors introduced in the physical device. Of course a chip will not work as per the
specifications if there are any errors introduced in the production process. But the question
is how to detect that. Since, to run all the functional tests on each of say a million physical
devices produced or manufactured, is very time consuming, there was a need to device
some method, which can make us believe without running full exhaustive tests on the
physical device, that the device has been manufactured correctly. DFT is the answer for
that. It is a technique which only detects that a physical is faulty or is not faulty. After the
post-production test is done on a device, if it is found faulty, trash it, don’t ship to
customers, if it is found to be good, ship it to customers. Since it is a production fault, there
is assumed to be no cure. So it is just a detection, not even a
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localization of the fault. That is our intended purpose of DFT. For the end customer, the
Simulation
DFT logic present on the device isFigure
a redundant logic.
1. VLSI Design.

II. DFT example to DFT architecture

2.1. DFT example explanation

Before the chip is manufactured, the designer must analyze the "test" strategy (plan)
of the chip to determine if the current design is capable of testing physical errors at
the chip level. Basically, the two main activities of DFT analysis and design are:

> Modeling physical errors (fault modeling) to predict errors may occur and
provide solutions to detect them.
 > Logical design supports the detection of physical errors if necessary. Note,
adding DFT logic is to make testing at the chip level easier, but in some
cases, DFT logic does not need to be added but can still be tested.

a) A simple combinational logic circuit:

Example 1. Design a circuit, with the following table and make the device testable

Verilog code: assign a12 = ~ (in1 & in2);

assign a13 = ~ (in1 & in 3); assign out_z = ~ (a12 & a13 & a23);

assign a23 = ~ (in2 & in 3);

in1 in2 in3 a12 a13 a23 out_z

0 0 0 1 1 1 0

0 0 1 1 1 1 0

0 1 0 1 1 1 0

0 1 1 1 1 0 1

1 0 0 1 1 1 0

1 0 1 1 0 1 1

1 1 0 0 1 1 1

1 1 1 0 0 0 1
Table 1. Truth table
 Figure 2. Circuit Diagram

If a physical error occurs such as a GND and VCC connection. This line’s value may
be stuck at level logic “0” (stuck- at 0) hoac “1” (stuck_at 1). These are fault models.
*) Test fault model for a12: At chip level, the control and monitoiring of internal
signals(lines) such as a12, a13, a23, is only possible through the pins(ports) chip,
such as in1, in2, in3, out_z. A connection line inside the chip is only tested when
it can be controlled to the desired value (controllable) and can
monitored(observable).
a12 is controlled to the expected value by in1 and in2; is monitored by out_z.
Stuck- at 1: Drive a12 driven to logic 0 and check a12. If a12 is equal to "0" then the
conclusion that a12 will not be stuck-at-1 error.
> Test-pattern 1: in1 = in2 = 1 to a12 = 0 and in3 = 0 to a13 = a23 = 1, the out_z
output will be monitored and checked with the desired value of out_z = 1. If
only test-pattern 1 is used, the result is not sufficient to confirm that "a12 does
not have a struck-at-1 error" because out_z = 1 may be due to a13 = 0 or a23 =
0 if either of these lines is stuck-at -0. So we need to add test- pattern to
confirm that a13 and a23 are not stuck-at-0.
> Test-pattern 2: ini = in2 = in3 = 0 to a12 = a13 = a23 = 1 and monitor the
output out_z = 0. The result of this test-pattern can confirm that a13 and a23
 cannot be stuck-at-0 because out_z = 0 only if a12 = a13 = a23 = 1.

Stuck- at 0: Drive a12 driven to logic 0 and check a12. If a12 is equal to "0" then the
conclusion that a12 will not be stuck-at-1 error.

Test-pattern in1= in2= in3= 0:

- out_z = 0. If out_z= 0 => “a12 will not be stuck- at 0”.
- Out_z = 1. We cannot conclude that a12 stuck- at 0 because the fault may
arise from a13 or a23.

Fault simulation is a simulation of a design under fault conditions. This simulation

step is used to evaluate how many errors can be detected on a specific number of
test-patterns. The number of detected errors will be indicated by the fault coverage
parameter.

fault coverage (%) = (total number of detected errors / total number of detected
errors) * 100

Fault coverage evaluates the error detection capability of a test-pattern set for a given
fault model, such as a stuck-at fault model.

Example 2. Design a multiplexer circuit, with the following table and make the
device test-able.
i0 i1 sel z

0 0 0 0

0 0 1 0

0 1 0 1

0 1 1 0

1 0 0 0
 1 0 1 1

1 1 0 1

1 1 1 1
Table 2. Truth table

Figure 3. Circuit diagram

b) Example 2: A basic 3 bit counter

 □
reset — CLK
men
t LK
KKU V-CLK tFt I □eU LI'J:
enable LK

Here we have not given any intended function of this sequential

circuit which has got 3 filpflops inside it. Since from DFT point of
view, the intended functionality does not matter at all. Given that we
already know how to do production-test-patterns for a
combinational logic, we try to break the given circuit into two parts,
its combinational logic blocks and its flip-flops. The Fig 4 shows
three combinational blocks which are encircled. Out of those 3
combinational blocks one has a dark 'bold' circle around it. We shall
first try to concentrate upon the combinational logic inside this dark
'bold' circle. This has got 3 inputs i0, i1, i2 and one output co2. Had
we got access to i0, i1, i2, we could have easily done PFT for this
block. So we shall now try to make i0, i1, i2 control- able via the
chip boundary, and co2 observable via the chip boundary. We will
do similar kind of arrangements for all inputs and outputs to all the
combinational blocks identified in the design. For this we replace all
the flip-flops in the counter, with special flip-flops, which are just
identical to the one we had replaced, but now with a multiplexer
inside the flip flop, and two more input pins called TE (Test enable)
and TI (Test Input) for the flip- flop. As shown in Fig 5 The
multiplexer can select between TI and D to be clocked and produced
to Q when the relevant edge of clock arrives. Now we connect these
Flip-flops to from a shift register, as shown by RED color in Fig 5.
Three more pins are added to the circuit i). scan_in : it is the serial
input for the so-formed shift register, ii). scan_out: it is the serial
output for the so-formed shift register, iii). scan_enable: it is the
control which enables to so-formed shift register. The patterns for
the Sequential Shift Register. A known data can be shifted inside the
shift register using the pin 'scan_in' on the chip boundary, while
'scan_enable' is held '1', shifted out, using the 'scan_out',
'scan_enable' is still '1' and then compared against what was shifted
in. This will help us to determine that the shift register or so-called
scan chain is working fine. The patterns for the combinational logic.
Using the shift register or scan chain, we can control every node
inside our design, and we can also observe the effect of controlling
each node inside the design. The control and observation both are
now done using the pins present at the chip boundary. We shall now
try to generate a set of input values which will be able to detect a
stuck at ‘0’ fault at net ‘n4’, shown in the Fig 5. To detect a stuck at
‘0’ fault at net ‘n4’ we need to Drive ‘n4’ to logic ‘1’, which means
drive i0 = 1, i1 = 1 so that we have a control over ‘n4’. Drive i2 =
‘0’, so that the effect of our control is observable at ‘co2’ To put i0 =
1, we should have ‘n2’ = 1, which is a function of chip pin ‘enable’
and ‘net0’. net0 is a direct output from FF0. So in the shift-register
the FF0 should be = ‘1’ To put i1 = 1. Since i1 = net1, which is a
direct output from FF1, in the scan-chain, the FF1 should be = ‘1’
To put i3 = 0. Since i3 = net2, which is a direct output from FF2, in
the scan- chain, the FF2 should be = ‘0’clock figure J| bfc : A basic 3 bit sequential
circuit made Dl- I -able

stm in scan aiablf

t scan tnsUcicm in^can on

:lock COUNTER qOqlql

Figure 5. A basic 3 bit DFT-able sequential circuit box

Fig 6 gives a diagram, where we have attempted to generate PFT, which can detect a stuck at
‘0’ fault at the node ‘n4’ as shown in Fig 4 and also Fig 5. The output q0, which is also the
‘scan_out’ from the design, is drawn in green, and red color. Green means, no fault was
reported, as it will be in pre-production fault simulation, or in post-production testing, if
there was no stuck at ‘0’ fault detected in the physical device. Red shows an error, and is only
possible in post-production test.
 Figure 6. Fault Simulation to evaluate stuck at ‘0’ fault at net ‘n4’

Summary:

> The circuit given to us in Fig 2 was modified in order to make the internal nodes in
the design ‘controllable’ and ‘observable’, so that we can now perform fault-
simulation, before production of the device, then save those sets of PFT to be used by
a Tester, on physical device after production. We can now say that we have added
DFT circuit to our original design, to make it DFT-able. The resulting DFT- able of
Fig2 is Fig 3.
> This method of DFT will only be able to detect stuck at faults in the design.
 >
> Any sequential design may be made DFT-able to detect the stuck-at faults in the
design, by the method shown above.
> The process of DFT is independent of the functional specification of the circuit. c)
Example of complex Digital chip (loading...)

Boundary Scan
DIGITAL

Memory

MBistControl [do
update retain

1FD

IFA
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Figure 7. Digital Block

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 2.2) DFT technique
- Ad-hoc (difficult to use in large circuit)

DFT technique

1 ■■

Scan (Partial scan, boundary scan)

- BIST (Build- in- self- test)

Scan design (basic idea)

Scan Design: is a design technique that makes it easy to test a sequential circuit by
replacing the flip-flops with scan registers. (Convert each flip- flop to a scan register). All
FFs controllable and observable via serial access(chain). Test problem simplified to testing
combination logic so it is the best overall DFT approach ever developed.
Scan has two modes:
> Normal mode: flip- flops behave as usual.
> Scan mode (test mode): flip- flops behave as shift register.
 >
To convert a traditional flip-flop to a scan flip- flop, we can simply add a multiplexer on da
input to the FF:
> Scan(Scan-enable): signal selects normal functional data input, or a new scan data
input to the FF.
> Scan inputs are chained to output of other FF (an element in a scan chain).
> Same clocks are used for both scan and functional operation (2 modes).
Figure 9. FF to Scan FF
ramary Combinational Primary Primary Combinational Primary
Logic
Logic Inputs Outputs
Inputs Outputs
Figure 10. DFF-cell to Scan DFT- DFF-cell
Scan
Data
Out
FFs
Scan
Data In
Scan C k
Scan
Mode
Scan FF Mode

Many different types of scan FF. The following example to convert DFF to Scan DFF.
Scan Design Testing Sequence:

Step 1: Shift some patterns(PFT) through scan chain.

Step 2: Scan-in test vector (scan-mode =1).

Step 3: Apply test vector at PIs (Primary inputs).

Step 4: Observe results at POs (Primary outputs).

Step 5: Apply Clock to capture results in scan chain (Scan mode =0).

Step 6: Scan-out results and scan-in next test vector (Scan mode =1).

Step 7: Go to Step 3 unit all test vectors processed. a) Partial scan

example
Specialized software such as DFT compiler (Synopsys) will do this. Each library of
technology used to synthesize supports two types of FFs, the normal-function type
(non-scan FF) and the type of scanning support function (FF scan)

Figure 11. Partial scan

b) Boundary scan

Testing boards is also difficult. Boundary scan build capability of observing and controlling
pins into each chip to make board test easier.
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