12 Bit Pattern Generator

1 Block Diagram

Figure 1: System Overview

1.1 Load and Mode Control Bits

First of all we will set the Clock Frequency and then play with Load, Mode, DI[12] - DI[01] Bits. How to set
the clock frequency is discussed in next section.

1. If Load = 1
12 bit Digital Output = 12 Bit Digital Input; DO[12] - DO[01] = DI[12] - DI[01];

If Load = 0
Check for Mode Pin status.

2. If Load = 0 and Mode = 0

Free Running Up Counter (Refer Table Number 1)

3. If Load = 0 and Mode = 1

Free Running Up-Down Counter (Refer Table Number 2)

1.2 Setting the Time delay ”Tdelay”

”Tdelay” is the time delay between two consecutive steps i.e. between 0 to 1; 1 to 2; 4091 to 4092; etc. (Refer
Table Number 3 to understand concept of ”Tdelay” in detail.)

”Tdelay” is variable time delay and can be set by using Control Bits S[3] - S[1]. (Refer Table Number 4 to
understand setting of ”Tdelay”.)

Hence according to Tdelay we have to choose Clock Frequency.

1
DO[12] DO[11] DO[10] - - - - - - DO[03] DO[02] DO[01] Decimal Equivalent
0 0 0 - - - - - - 0 0 0 0
0 0 0 - - - - - - 0 0 1 1
0 0 0 - - - - - - 0 1 0 2
0 0 0 - - - - - - 0 1 1 3
0 0 0 - - - - - - 1 0 0 4
- - - - - - - - - - - - -
- - - - - - - - - - - - -
- - - - - - - - - - - - -
- - - - - - - - - - - - -
1 1 1 - - - - - - 0 1 0 4091
1 1 1 - - - - - - 0 1 1 4092
1 1 1 - - - - - - 1 0 0 4093
1 1 1 - - - - - - 1 0 1 4094
1 1 1 - - - - - - 1 1 1 4095
0 0 0 - - - - - - 0 0 0 0
0 0 0 - - - - - - 0 0 1 1
0 0 0 - - - - - - 0 1 0 2
0 0 0 - - - - - - 0 1 1 3
0 0 0 - - - - - - 1 0 0 4
- - - - - - - - - - - - -
- - - - - - - - - - - - -
- - - - - - - - - - - - -
- - - - - - - - - - - - -
1 1 1 - - - - - - 0 1 0 4091
1 1 1 - - - - - - 0 1 1 4092
1 1 1 - - - - - - 1 0 0 4093
1 1 1 - - - - - - 1 0 1 4094
1 1 1 - - - - - - 1 1 1 4095
0 0 0 - - - - - - 0 0 0 0
0 0 0 - - - - - - 0 0 1 1
- - - - - - - - - - - - -
- - - - - - - - - - - - -
- - - - - - - - - - - - -
- - - - - - - - - - - - -

Table 1: Load = 0 and Mode = 0; Free Running Up Counter

2
DO[12] DO[11] DO[10] - - - - - - DO[03] DO[02] DO[01] Decimal Equivalent
0 0 0 - - - - - - 0 0 0 0
0 0 0 - - - - - - 0 0 1 1
0 0 0 - - - - - - 0 1 0 2
0 0 0 - - - - - - 0 1 1 3
0 0 0 - - - - - - 1 0 0 4
- - - - - - - - - - - - -
- - - - - - - - - - - - -
- - - - - - - - - - - - -
- - - - - - - - - - - - -
1 1 1 - - - - - - 0 1 0 4091
1 1 1 - - - - - - 0 1 1 4092
1 1 1 - - - - - - 1 0 0 4093
1 1 1 - - - - - - 1 0 1 4094
1 1 1 - - - - - - 1 1 1 4095
1 1 1 - - - - - - 1 0 1 4094
1 1 1 - - - - - - 1 0 0 4093
1 1 1 - - - - - - 0 1 1 4092
1 1 1 - - - - - - 0 1 0 4091
- - - - - - - - - - - - -
- - - - - - - - - - - - -
- - - - - - - - - - - - -
- - - - - - - - - - - - -
0 0 0 - - - - - - 1 0 0 4
0 0 0 - - - - - - 0 1 1 3
0 0 0 - - - - - - 0 1 0 2
0 0 0 - - - - - - 0 0 1 1
0 0 0 - - - - - - 0 0 0 0
0 0 0 - - - - - - 0 0 1 1
0 0 0 - - - - - - 0 1 0 2
0 0 0 - - - - - - 0 1 1 3
0 0 0 - - - - - - 1 0 0 4
- - - - - - - - - - - - -
- - - - - - - - - - - - -
- - - - - - - - - - - - -
- - - - - - - - - - - - -
1 1 1 - - - - - - 0 1 0 4091
1 1 1 - - - - - - 0 1 1 4092
1 1 1 - - - - - - 1 0 0 4093
1 1 1 - - - - - - 1 0 1 4094
1 1 1 - - - - - - 1 1 1 4095
1 1 1 - - - - - - 1 0 1 4094
1 1 1 - - - - - - 1 0 0 4093
1 1 1 - - - - - - 0 1 1 4092
1 1 1 - - - - - - 0 1 0 4091
- - - - - - - - - - - - -
- - - - - - - - - - - - -
- - - - - - - - - - - - -
- - - - - - - - - - - - -
0 0 0 - - - - - - 1 0 0 4
0 0 0 - - - - - - 0 1 1 3
0 0 0 - - - - - - 0 1 0 2
0 0 0 - - - - - - 0 0 1 1
0 0 0 - - - - - - 0 0 0 0
- - - - - - - - - - - - -
- - - - - - - - - - - - -
- - - - - - - - - - - - -
- - - - - - - - - - - - -

Table 2: Load = 0 and Mode = 1; Free Running Up-Down Counter

3
DO[12] DO[11] DO[10] - - - - - - DO[03] DO[02] DO[01] Decimal Equivalent
0 0 0 - - - - - - 0 0 0 0
Tdelay
0 0 0 - - - - - - 0 0 1 1
Tdelay
0 0 0 - - - - - - 0 1 0 2
Tdelay
0 0 0 - - - - - - 0 1 1 3
Tdelay
0 0 0 - - - - - - 1 0 0 4
Tdelay
- - - - - - - - - - - - -
- - - - - - - - - - - - -
- - - - - - - - - - - - -
- - - - - - - - - - - - -
Tdelay
1 1 1 - - - - - - 0 1 0 4091
Tdelay
1 1 1 - - - - - - 0 1 1 4092
Tdelay
1 1 1 - - - - - - 1 0 0 4093
Tdelay
1 1 1 - - - - - - 1 0 1 4094
Tdelay
1 1 1 - - - - - - 1 1 1 4095
Tdelay
0 0 0 - - - - - - 0 0 0 0
Tdelay
0 0 0 - - - - - - 0 0 1 1
Tdelay
0 0 0 - - - - - - 0 1 0 2
Tdelay
0 0 0 - - - - - - 0 1 1 3
Tdelay
0 0 0 - - - - - - 1 0 0 4
Tdelay
- - - - - - - - - - - - -
- - - - - - - - - - - - -
- - - - - - - - - - - - -
- - - - - - - - - - - - -
Tdelay
1 1 1 - - - - - - 0 1 0 4091
Tdelay
1 1 1 - - - - - - 0 1 1 4092
Tdelay
1 1 1 - - - - - - 1 0 0 4093
Tdelay
1 1 1 - - - - - - 1 0 1 4094
Tdelay
1 1 1 - - - - - - 1 1 1 4095
Tdelay
0 0 0 - - - - - - 0 0 0 0
Tdelay
0 0 0 - - - - - - 0 0 1 1
Tdelay
- - - - - - - - - - - - -
- - - - - - - - - - - - -
- - - - - - - - - - - - -
- - - - - - - - - - - - -

Table 3: Concept of Tdelay (Applicable to Both Modes)

4
 S[3] S[2] S[1] Time Delay
0 0 0 250 nS
0 0 1 500 nS
0 1 0 750 nS
0 1 1 1000 nS
1 0 0 1250 nS
1 0 1 1500 nS
1 1 0 1750 nS
1 1 1 2000 nS
Tolerance of 30 nS in ”Tdelay” is acceptable

Table 4: Setting of Tdelay using Control Bits S[3] - S[1]