Design and Performance of CPW and

CPW Bandpass Filter on SOI Substrate

Xi Li#1, Yanling Shi#2, Dawei Chen#3, Yanfang Ding#4, Qirong Xiao#5,

Hongbo Ye*6, Hao Huang*7

#
Department of E.E., East China Normal University, Shanghai 200062, China
1
ximeir@hotmail.com
2
ylshi@ee.ecnu.edu.cn (corresponding author)
3
yfding@ee.ecnu.edu.cn
4
David_cdw@hotmail.com
5
51061202038@student.ecnu.edu.cn

* Shanghai IC Research and Development Center, Shanghai 201203, China

6
yehongbo@icrd.com.cn
7
hhao@icrd.com.cn

Abstract—SOI technology gets more and more interests in RF
ICs for its low loss, low crosstalk and other excellent
electromagnetic properties. Well-behaved passive devices on SOI
substrate will contribute a lot to the entire performance of RF
ICs. In this paper, the influence of SOI parameters on
transmission characteristics of coplanar waveguide (CPW) is
researched by HFSS simulation. Based on the fine performance
of a 50 CPW fabricated on an available SOI substrate, a
dual-termination coupled Ka band bandpass filter (BPF) has
been designed and fabricated. It shows -4.23dB insertion loss at
peak transmission of about 32GHz. The CPW and BPF realized
on SOI gain close characteristics respectively to the same
structure on high resistivity (1000·cm) silicon substrate. SOI
shows great potential to be the substrate of RF IC.
0.6nH STP (Single-Turn, multiple metal levels in Parallel)
inductor with peak Q of 52 is obtained at 5GHz. In [9], a 20pF
high-density 3-dimensional VPP (vertical parallel plate)
capacitor with high-Q of 22 at 1GHz is obtained.
Coplanar waveguides (CPW) are widely used as inter
connects and matching network in MMICs. It’s important to
design low loss CPW and fine filter to obtain high
performance MMICs. The research in this paper is restricted
to reducing dielectric loss from parameter optimization of SOI
substrate to realize low loss CPW. Based on transmission line
coupling theories, a dual-termination coupled Ka band
bandpass filter (BPF) has been designed and fabricated.

II. DESIGN PRINCIPLES

I. INTRODUCTION
As operation frequency and integration improved, RF
circuits on low resistivity Si substrate perform poorer because
of high energy loss and serious crosstalk through the substrate
[1, 2]. With its smart structure, SOI offers many advantages
over bulk Si CMOS technology such as low power
consumption, low crosstalk and low parasitic capacitance in
high frequency. Therefore, applying SOI in RF ICs can
contribute to the fabrication of high performance passive
devices and integration of digital, analog and other RF circuits
on a single chip [3, 4]. SOI technology owns cheerful prospect
to replace conventional Si technology [5].
In order to obtain good performance of RF SOC, it’s
important that passive components with low loss and low
parasitic effect are made. In recent years, passive devices on
SOI substrate have got considerable amount of research and
gained some development [6-9]. In [6], the behaviour of 50
thin film microstrip and coplanar waveguide (CPW) on SOI
substrates versus high temperature is researched. In [7], a
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978-1-4244-2193-0/08/$25.00 ©2008 IEEE

SOI substrate owns complicated structure parameters
which may influence CPW transmission characteristics. From
HFSS simulation, it is found that insertion loss increases with
bigger thickness of low-resistivity surface silicon, lower
surface resistivity and lower bottom resistivity respectively.
For Experimental validation, CPW with 50
characteristic impedance is designed. The central line is 39m
wide. The space between ground lines is 87m. The width of
ground lines are 100m respectively. The length of the CPW
is 2mm. Experimental results will be analyzed later.
Based on transmission line coupling theories, the filter
design starts by synthesizing a circuit model prototype
according to the requirements. Ka band bandpass filters can be
implemented by resonators connected with J inverters. The
admittance inverter Ji is determined by characteristic
admittance Y0, the normalized bandwidth w, the prototype
filter cutoff frequency 1’ and the normalized impedances gi:
 G=500μm

W=50μm

L=1925μm
a S=125μm
b=50μm a=25μm
a a

50 CPW Admittance Inverter 50 CPW

Fig. 1 Sketch of the CPW bandpass filter on SOI substrate

J 01 J n , n 1 S w procedure from low resistivity Silicon. It has a 0.138μm thick

and 0.075μm deep buried oxide layer. The resistivity of
Y0 Y0 2 g 0 g1Z1' (1) surface silicon is less than 200·cm. 1μm-thick SiO2 was
J i , i 1 Sw1 firstly deposited by PECVD. Then a 1μm-thick aluminum
i z 0, n  layer was coated by vaporization. After being lithographed
Y0 2Z1'
g i g i 1
and etched, the CPW was completed. CPW bandpass filter
In order to realize the J inverter with CPW, such gap is shares the same procedure with coplanar waveguide. Fig. 3 is
employed in the signal line of CPW as shown in Fig.1, which the photograph of a fabricated dual-termination coupled CPW
is the sketch of the BPF on SOI substrate. The value of BPF.
electrical length  is related to parallel and series capacitances
of the gap.
The BPF is designed by HFSS with 50 input impedance
and a target center frequency of 32GHz. A dual-termination
coupled structure is used to improve the coupling capacitances
between central metal and matching transmission lines for
reducing insertion loss. The total length of the filter is about
/2 with each stub finger 25μm wide. The ground lines are
500μm wide respectively for good RF impedance matching
and power lines’ collection. Series resonators are formed by
coupled line with coplanar structures [10]. The values of the
equivalent capacitance and inductance depend on the gap Fig. 3 Photograph of fabricated dual-termination coupled CPW BPF
spacing between couple lines and the width of the central line.

HR-Si is considered as good substrate for microwave

EXPERIMENTAL PROCEDURE
III.
passive devices [11]. It is valuable to compare the device
Fig. 2 shows the profile of fabricated CPW on SOI performance on SOI with that on HR-Si. In order to evaluate
substrate. The SOI substrate adopted is realized by SIMOX the performance on SOI, transmission line and filter with
same structures are also realized on HR-silicon ( 1000·cm)
substrate with additional 1μm thermal oxide.

IV. RESULTS AND DISCUSSIONS

SOI
substrate
A. Transmission performance of CPW
The measured characteristic impedance of CPW is 49.3.
From 0 to 40GHz, it presents an insertion loss less than
-5dB/cm and shows no obvious increasing trend.
Fig.4 displays the transmission performance of CPW on
Si buried oxide PECVD SiO2 Al SOI and HR-Si substrate. Insertion loss of CPW on
high-resistivity silicon substrate is between -2dB/cm and
Fig. 2 Profile of BPF on SOI substrate -4dB/cm, which is just a little lower than that on SOI substrate.


 As we have discussed above, better performance of SOI CPW buried oxide. And better performance could be imagined by
could be obtained from increasing the substrate resistivity and optimization of SOI substrate.
buried oxide thickness. Fig.6 indicates the measured filter performance
comparison on SOI and HR-Si substrate. At the center
frequency of 32GHz, insertion loss of the filter on HR-Si
0 substrate is -2.21dB. BPF on SOI achieves comparable
performance with it. The transmission characteristic curves of
-5 BPF on different substrates are also close to each other. It is
evidenced that the BPF on SOI substrate can fulfill RF filter’s
S parameter (dB/cm)

S21
-10 performances. The application of SOI into RF passive
components is attractive.
-15
S11 0

-20
-5
-25 SOI

S parameter (dB)
HR Si -10
-30
-15
-35
S21 S11
0 10G 20G 30G 40G
-20
Frequency (Hz)

Fig. 4 Transmission performance on SOI and HR-Si substrate -25

SOI
HR Si
-30
B. Filter performance of bandpass filter
Fig.5 demonstrates the simulated and measured results of -35
0 10G 20G 30G 40G
the designed bandpass filter on SOI substrate. Good
performance is shown from the measured -4.23dB insertion Frequency (Hz)
loss at peak transmission of 31.6GHz. This result agrees well Fig. 6 Filter performance on SOI and HR-Si substrate
with the designed filter by HFSS. The slight deviation to the
designed 32GHz center frequency and –2.76dB larger loss
may be caused by the RF loss by skin effect. BPF on SOI
substrate can achieve fine performance compared with that on CONCLUSIONS V.
low-resistivity silicon because of the loss effect reduction of The influence of SOI parameters on transmission
characteristics of coplanar waveguide is researched by HFSS
simulation in this paper. The fabricated 50 CPW shows a
0 insertion loss less than 5dB/cm up to 40GHz. Based on the
fine transmission performance of the SOI CPW, a
-5 dual-termination coupled CPW structure is applied to realize a
tight coupling bandpass filter on SOI substrate. The BPF has
S parameter(dB)

-10 gained low insertion loss of -4.23dB at operation frequency of

32GHz in Ka band. Compared to the same structure fabricated
-15
S21 on high resistivity ( 1000·cm) silicon substrate, BPF on
SOI has presented close characteristics including transmission
-20 S11 loss and curve trend. It indicates that the buried oxide of SOI
can reduce the loss effect. SOI has good prospects to replace
-25 HFSS Simulation conventional Si technology in RF realm.
Measurement
-30

-35 ACKNOWLEDGMENT
0 10G 20G 30G 40G
Frequency(Hz) This work was supported by Foundation of Shanghai
Science &Technology Committee (075007033, AM0522) and
Fig. 5 Simulated and measured characteristics of 32GHz Natural Science Foundation of China (No. 60676047 ˈ
bandpass filters on SOI substrate
60606010).


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