TOSHIBA TMP86CM25/S25 CMOS &-8it Microcontroller TMP86CM25F, TMP86CS25F ‘The TMP86CM25/S25 are the high-speed, high-performance and low power consumption 8-bit microcomputer, including ROM, RAM, Dot matrix LCD driver, multi-function timer/eounter, serial interface (UARTISIO), & 8-bit AD converter and two clock generators on chip. ProductNe- TOW Ta Package orewco Twpaccwasr_| 32K x Bois 2k xsbits | P.grPio0-1420.0.65q | TwpaGes2sr ‘twpescsasr | 60K x sbits Features -QFP100-1420-0.654 © Shit single chip microcomputer TLCS-870/C series Instruction execution time: 0.25 (at 16 MHz) 122 15 (at 32,768 kHz) 132 types and 731 basic instructions © 20 interrupt sources (External: 5, Internal: 15) \ wo" + InpulOutput ports (42 pins) (Outof which 20 pins are also used as SEG pins.) © 18it timer counter: 1ch 4 Timer, Event counter, Pulse width meansnrement, Frequencymeasurement modes © Sdit timer counter: 4ch © ‘Timer, Event counter, PWM output, Programmable Divider Output, PPG modes © Time Base Timer ‘Twpescaasr ‘TMPBECS25F . Divider output funetion © Watchdog Timer © Interrupt source/internal reset generate (programmable) mm (@ For discussion of how the reliably of microcontrollers can be prediciea, please refer To Secion 13 of the chapter entitled uel and Reliab Asurence/ Handling Precaution, @ TOSHIBA'S Continual warking to. Imarove the quality and reliability of its products. Nevertheless, semiconductor devices general can malfunction or Tal due to their nberent electrical sensitivity and vulnerability to physical res. ies ther rexponay of the buyer, when vilzing TOSMeA, products, fo com wih the standard of safely in making ® Safe design for the entire system, and 0 aval situations im whicn & malfunction or faure ef such TOSMIBA Product aula cau om of naman if bodiy ry Wn camoge fo property [developing your designs, please ensure that TOSHIBA products ore used within specified operating ranges os set forth in the pom recent TOSFIBA, products specifications, Alo, please keep in ming the precautons and cantons Set Forth in the "Handling Guide for Semiconductor Devices," of “TOSHIBA Semiconductor Refbity Handbook ete he TGsHibA products edn ths cocument ae intended for ape In general clecvonc appcatons (comeute, Personal equipment. office equipment, messuring equipment, Indusval. robotes, demesve, appliances ete) These Toshiba products are neither intended nor warranted. for usage’ in equipment that requires exraordinarly high quality andlor reliability or 9, malfunction or falure. of which may ‘cause loss of human’ ife or bouily” injury Pinimeended usoge'). Unintended Usage include atomic energy contra instruments, airplane er spaceship instuments {ransportaton instrument, vale signa instruments, combustion control msvumerts, medical inseuments all types of sleeves, tc. Unintended Usage of TOBRBA product Tnted In this ocument shal be made atte cunome”s QPS een cescrive in sis docomen oe suect tothe freon exnange an foreign trade lows ‘he information contained heen is presented. only es a guide Tor ihe applications of ‘our products, No responsibil is’essumed by TOSHIBA. CORPORATION for ary infangements of intelectual property or other rights of the th artes which may result rom ily Use. No license ik granted. by implication oF otherwise Under any” intellectual Property or other fights of TOSHIBA CORPORATION or eters @ Fhe inidemation contained herein is subject to change without notice ‘86CM25-1 2003-05-15TOSHIBA TMP86CM25/S25 © Serial interface: 2ch © 8-bit UARTISIO: Ich © 8bitSIO: Ich © Sit successive approximation type AD converter © Analoginput: 8ch ‘@ Four Key On Wake Up pins # LCD drivericontroller © Built-in voltage booster for LCD driver © With displaymemory © LCD direct drive capability (60 seg X 16 com, 60 seg X 8 com, 60 seg X 4 com) © 1/16, 1/8, 1/4 duties drive are programmably selectable # Dual clock operation © Single/Dual-clock mode # Nine power saving operating modes © STOP mode: Oscillation stops. Battery/capacitor back-up. Port output hol@/high-impedance. ‘© SLOW 1,2 mode: Low power consumption operation using low-frequency clock (82.768 kHz) © IDLE mode: CPU stops, and peripherals stop except Time-Base-Timer. Release by falling edge of TBICR setting. © IDLE1mode: CPU stops, and peripherals operate using high-frequency clock. Release by interruputs. © IDLE2mode: CPU stops, and peripherals operate using high and low frequency clock. Release by interruputs. © SLEEP Omode: CPU stops, and peripherals stop except Time-Base-Timer. Release by falling edge of TBICR setting. © SLEEP I mode: CPU stops, and peripherals operate using low-frequency clock. Release by interrupts. © SLEEP 2mode: CPU stops, and peripherals operate using high and low frequency clock. Release by interrupts. © Wide operating voltage: 1.8 to 5.5 V at 4.2 MH7/32.768 kHz, 2.7 to.5.5 V at 8 ME2/32.768 kHz, 4.5 to 5.5 V at 16 MH2/32.768 kHz ‘86CM25-2 2003-05-15TOSHIBA TMP86CM25/S25 Pin Assignments (Top View) P-9FP100-1820-0658 coma 6 ee wuuaconsyrae eee oe faa Seen (hulseon rs et es FS stan. twutecon rae <> 26 a (wuacows pr stole SiS Sos nucveonoyora eta 6 abo se fnutzcontsjon eee 99 Sb SS) (chcoMta rs ee 92 a (Giicowg en ee 98 ase mgecn) = wb pete) % SES mets) ” ofc psetec) =O Bios bsgecn » REDS pepe ee « ‘roan tl tesa: “98 Note: Port assigned as MULG to MULO can switch pin assignment by the multifunction register (MULSEL). For functions assigned to each pin, ee the table below. Pinname Function Pinassignment mute [BVO Padre ‘mut _ | PWH,POOS, TCs P31 or P72 ‘mui | PPG, Pwhta, PDO, Ta P32 or P73 ‘muts | PGS, PTE, PDOE, TCs P33 0r P74 mute [iri PiorFaa muis_[ wre P13 or P35 mus [ints Piso P36 86CM25-3 2003-05-15TOSHIBA TMP86CM25/S25 Block Diagram lorxtasnenoupat Conmoncutpts segnertosts rissa) P17 e689) comme epee et a — J is] Sy wena o SET coven OCT o| == evtehmee GES eronwacesy [5p 1 i 1 1 i eee |= See TSH IT ee t t Te reaioran water PRK) 6 (GN GCs prow so ina rae Cos P20 eee) rro(cons) wenn) WoRers ——_UOPors epmentandcommon pa) ‘86CM25-4 2003-05-15TOSHIBA TMP86CM25/S25 Pin Function Pinname _[lopuvOutput Function Piz secss. sex] vOWO) Serial dockinpuvoutpat i UART dats output P16 £658, 720,500) | VOCOutPL*) | aie inpuvourput port withlatch. _ | Serial data output Winen used s input port, an external | Yar date input P1s¢se6s7, Rx0,sio) | vO(uo) _|interruput input, sefial clock input! | Sern date input eutputy serial data inpuvoutout or Lcd segment Pia e656 Mabie) ”"|"6 Gio)” CART data inpuvoutput, the lateh | External interrupt 3 input ar i i most beset 101" ternal interrupt 2 in Pracseqss,muts) | wocwoy,”|murtbeserte ta, |Extemalinterrpt 2 input Pi2(secse, muta) | VOW). |tmepiteemostbesettant™ External interrupt input P11 (secs) iio (outpu P10 sec52) Wo (Outpu0 P22 TOUT) 10 (Output) Resonator connecting pins 32.768 KH) 3:bitinputioutput port with lath, |Forinputing externa lock, XIN sued ard P21 ocr wo (newt) | When used a an input po. the latch | XTOUT is opened must besetto "1" sal interrupt input 5 or STOP made release pzocirs,stoy | wodneus, eae UP IMPUt Sor STOP made rel Pasicou7, muie)_| OW) External interrupt 3 input P35(coMe, mus). | VO(uO)..|7-biVO pore with atch External interrupt 2input Pe When used as input port, an external (coms, Mula) "|" YOO). linterruput input oF timer/eounter [External nterupt input P33(se631, mula)” |” vO(uo). | nguvoutputthe lech must be set to | Tmerleounter Sinpuvoutput | Lcd segment ae outputs 32,5630, MUL)” | YOWO) | yInan used as @ LCD segment output, | Tier/counter&inpuoutput a P31 (Se609, mut) |” vOWO). | teP3LcRmustbeset tot” Timercounter 3inpuvioutput P30 e648, muta)” | Yo (output Divider output [bE inpatvoutput port with atch P57 (sec16) 10 vorourpur) [aren apaoutnet utput) | When used as a CD segment output, | LCD segment outputs PSO (SEG23) the PSLCR must beset to “1” Per ANT. 10P9),.| vOdnen, oPsinen Pee aine,s70P8) "| Cinput|s-bit programmable inpuiourput | 8T0P4 input input) "| Pores (westate) Each Bit of these 7993 input PES (AINS, STOP2)...|. UOANPUY.| Ports ean be individually configured | 70°22 P64 Aine, st0P2) "| ”"vo input) | S5"an input or an output under [S102 input AD converter p63 ans. 70) "|v dnpun, | software control. When wed a5 2ey |exceral interrupt Oinput | emaloainputs Pez cainz,ecnT) |" vOCinput) [interrupt input and timer/courter P61 (AiNi, CIN) "VO (input) input the PECRmustDesetton™. | T™erCounter tInput 60 (INO) VO (ngu) P79 (come) 70,(Ourpun, p71 (conte, avid) | 0 (wo) Divider output P72 (cOMI0, MUL) | YOU)” I seve pore Timercounter 3inputioutput P73 (cons, mUL2)” |" VOCiO) "| When used common output, °7 por | Timercounter &inpuvioutput Pratcomsa, muta, | vo.uo)._| control repster (rch shuid be stl imercunter6inpusoutpur P75 (cont, 511) wo Wwo) Serial data input P76 (conta, sor) | VO (Outpu, Serial date output p77 (connis, sexi) | 10 WO) Serial lock inpuvoutput [E639 t0 SECO ouput | SosaTeT ORE Cone to como LCD common outouts varov {cD voltage | LCD voltage booster pin. Capacitors are required between GD and Ci pin and ViNV2Na) citeeo Boosterpin_|Vapinand GND. input Output | Resonetor connecting pins Tor ighrequency dock For nputting externa dock, XIN Is Pan, xOUT Input Outout | fed and XOUT s opened, Reser Input Reset signal input fest Input [Test pin for out-going text. Be Txedtolow 00, v5, + 5y,0(GND), Power Su vaaee POY Tanclog reference voltage input ‘86CM25-5 2003-05-15TOSHIBA TMP86CM25/S25 Operational Description 4. €PUCore Functions ‘The CPU core consists of a CPU, a system clock controller, and an interrupt controller. ‘This section provides a description of the CPU core, the program memory, the data memory, the external memory interface, and the reset circuit, 1.1 Memory Address Maps ‘The TMP86CM25/S25 memory consist of 4 blocks: ROM, RAM, DBR (Data Buffer Register) and SFR (Special Function Register). ‘They are all mapped in 64 Kbyte address space. Figure 1-1 shows the 'TMP86CM25/S25 memory address maps. ‘The general-purpose registers are not assigned to the RAM address space. 0008 0004 ROM: Read Only Memory includes: ser Gabytes eabytes tose | _S20% fosen |_o Program memory tbaon baat Vector tale RAM: Random Access Memory includes: Datamemory aw. Stock es 2048 bytes 204a yt om ‘Genera: purpose register banks SFR: Specie! Function Register includes 10 ports case ase Peripheral control registers i ; i Peripheral status regiters : : ! System contol registers i : i Interrupt contol registers i i i Program Status Word orcow oF0oH ea: Data Buffer Register includes: OR en | 26mm | Oo, |_256brtes Peripheral control registers oe t ‘ Peripheral Status registers i : LeDetsplay memory 80004 61376 bytes s2704 tes now Freon FrcoH for vector cllinstuctions s2bytes s2bytes roru|_ 20 ror |_ 20M Freon FreoH rm sremn | 22000 | fen [| az0ves |) Mesecict "ae6cs2s rmpascaas Figure 1-1. Memory Address Maps 1.2. Program Memory (ROM) ‘The TMP86CM25 has a 32 Kx 8-bit (address 8000H to FFFFH), and the TMP86CS25 has a 60K X8-bit (address 1000H to FFFFH) of program memory (mask programmed ROM). However, placing program ‘memory on the internal RAM is deregulated if certain procedure is executed (See 2.5.5 Address Trap). ‘86CM25-6 2003-05-15TOSHIBA TMP86CM25/S25 13 Data Memory (RAM) Data memory consists of internal data memory (internal ROM or RAM), ‘The TMP86CM25/S25 have 2 Kbytes of internal RAM. The first 192 bytes (0040H to OOF FH) of the internal RAM are located in the direct area; instructions with shorten operations are available against such an area. ‘The data memory contents become unstable when the power supply is turned on; therefore, the data ‘memory should be initialized by an initialization routine, ‘Example: TMP86CM25/825 RAM CLR LD HL, 0040H ; Start address setup LD AH + initial value (001) setup LD —BC,O7FFH ——_; byte (~1) setup SRAMCLR: LD (HL),A INC HL DEC BC SRS — F,SRAMCLR ‘86CM25-7 2003-05-15TOSHIBA TMP86CM25/S25 1.4 System Clock Controller ‘The system clock controller consists of a clock generator, a timing generator, and a stand-by controller. Timing generator control regiter TaTcR cock 00364 | generator xin fe FL *[rinrequene 3 Hichrequeney Timing Stand-by controller lock oxilator generator xouT TTT xa 6 Juetuoas. vou reauann sytem cocks 3 cuency cose 7 o039H clock oxcator Cascer Src our Glock generator contol system contol egiters, Figure 1-2. System Clock Control 1.4.1 Clock Generator ‘The Clock generator generates the basic clock which provides the system clocks supplied to the CPU core and peripheral hardware. It contains two oscillation circuits: one for the high-frequency clock and cone for the low-frequency clock. Power consumption can be reduced by switching of the standby controller to low-power operation based on the low-frequency clock. ‘The high-frequency (fe) and low-frequency (fs) clocks ean easily be obtained by connecting a resonator between the XIN/KOUT and XTIN/XTOUTT pins respectively. Clock input from an external oseillator is also possible, In this case, external clock is applied to XIN/XTIN pin with XOUT/XOUT pin not connected. ee Tow ewer do O Hi Geo om | o o [sz - a {os costco 0) tramexiinor || (oy (0 txeratono | Figure 1-3. Examples of Resonator Connection ‘Note: The function to monitor the basic clock directly at external is not provided for hardware, however, with disabling all interrupts and watchdog timers, the oscillation frequency can be adjusted by monitoring the pulse which the fixed frequency is outputted to the port by the program. The system to require the adjustment of the oscillation frequency should create the program for the adjustment in advance. ‘86CM25-8 2003-05-15TOSHIBA TMP86CM25/S25 142 Ti 19 Generator ‘The timing generator generates the various system clocks supplied to the CPU core and peripheral hardware from the basic clock (fe or fs). The timing generator provides the following functions. © Generation of main system clock (fin) 2) Generation of divider output (DVO) pulses ® Generation of source clocks for time base timer @ Generation of source clocks for watchdog timer Generation of internal source clocks for timer/counters © Generation of warm-up clocks for releasing STOP mode (1) Configuration of timing generator ‘The timing generator consists ofa 2-stage prescaler, a 21-stage divider, a main system clock generator, and machine cycle counters. An input clock to the 7th stage of the divider depends on the operating mode, DV7CK (bit 4 in TBTCR), that is shown in Figure 1-5. As reset and STOP mode started/eanceled, the prescaler and the divider are cleared to “0”. Mainsystem clock generator |}-feorfs Machine cle counters Divider High-requency Tol ‘lock fe eff alee seliefalfa] Male Low-irequeng iultiplexer Sock plexer el Warming-up controler vracdeg col Timea Tine Serial Divider Figure 1-4. Configuration of Timing Generator (6h) (eee wrgen [oer [aren | ares] rate: 000) stage ofthe divider Note 1 In Single Clock mode, do.not set DVICK to "1™ Note 2: Do not set “1” on DV7CK while the low: trequency clock snot operated stably. Note 3: fe: High-frequency clock [Ha], f: Low-frequency clock Hz)»: Bon teare Noted: In stSlna nd SLEEPi¢modes, the BV setng nefective, and inputto the 7th stage the Note 5: When STOP mode isentered from NORMAL 1/2 mode, the DV7CK setting is neffective dur the worm erlod after release of STOP mode, and the Uh stage ofthe cinders input tthe 7th stage ring ths pod ov7ex [selection of pot to the 7h]: fo Fe Figure 1-5. Timing Generator Control Register ‘86CM25-9 2003-05-15TOSHIBA TMP86CM25/S25 @ Machine cycle Instruction execution and peripheral hardware operation are synchronized with the main system clock, ‘The minimum instruction execution unit is called an “machine cycle”. There are a total of 10 different, types of instructions for the TLCS-870/C Series: ranging from L-eycle instructions which require one machine eyele for execution to 10-cycle instructions which require 10 machine eycles for execution. A machine eycle consists of 4 states ($0 to $3), and each state consists of one main system clock. Tifcor Wet Mains clock 1 i | | mr. swe [= es [ss ~s [ss 1s -$——machine cle Figure 1-6. Machine Cycle 1.43 Operation Mode Control Circuit a ‘The operation mode control circuit starts and stops the oscillation circuits for the high-frequency and low-frequency clocks, and switches the main system clock. ‘There are two operating modes: single-clocke and dual-clock. ‘These modes are controlled by the system control registers (SYSCR1 and SYSCR2).. Figure 1-7 shows the operating mode transition diagram and Figure 1-8 shows the system control registers. Single-clock mode Only the oscillation cireuit for the high-frequency clock is used, and P21 (XTIN) and P22 (XTOUT) pins are used as input/output ports. The main-system clock is obtained from the high-frequency clock. In the single-elock mode, the machine cycle time is 4/fe (s} 1) NORMALI mode In this mode, both the CPU core and on-chip peripherals operate ‘The TMP86CM25/S26 are placed in this mode after reset. g the high-frequency clock. 2 IDLE1 mode In this mode, the internal oscillation circuit remains active. The CPU and the watchdog timer are halted ; however on-chip peripherals remain active (operate using the high-frequency clock), IDLE1 mode is started by SYSCR2, and IDLE1 mode is released to NORMALI mode by an interrupt request from the on-chip peripherals or external interrupt inputs. When the IMF (interrupt ‘master enable flag) is “1” (interrupt enable), the execution will resume with the acceptance of the interrupt, and the operation will return to normal after the interrupt service is completed. When the IMF is “O” (interrupt disable), the execution will resume with the instruction which follows the IDLE1 mode start instru 86CM25-10 2003-05-15TOSHIBA TMP86CM25/S25 @ ® IDLEO mode In this mode, all the cireuit, except oscillator and the Timer-Base-Timer, stops operation, ‘This mode is enabled by setting “1” on bit TGHALT on the system control register 2(SYSCR2). ‘When IDLEO mode starts, the CPU stops and the timing generator stops feeding the clock to the peripheral circuits other than TBT. ‘Then, upon detecting the falling edge of the source clock selected with TBICR, the timing generator starts feeding the clock to all peripheral cireuits, ‘When returned from IDLE0 mode, the CPU restarts operating, entering NORMAL! mode back again. IDLEO mode is entered and returned regardless of how TBTCR is set. When IMF= “1”, ERs (TBT interrupt individual enable flag)= “1”, and TBTCR = “1”, interrupt processing is performed. When IDLE0 mode is entered while TBTCR ="1”, the INTTBT interrupt latch isset after returning to NORMALI mode. Dual-clock mode Both the high-frequency and low-frequency oscillation cireuits are used in this mode, P21 (XTIN) and P22 (XTOUT) pins cannot be used as input/output ports. ‘The main system clock is obtained from the high-frequency clock in NORMAL? and IDLE2 modes, and is obtained from the low-frequency clock in ‘SLOW and SLEEP modes. ‘The machine cycle time is 4ife (s] in the NORMAL? and IDLE2 modes, and 4ifs [s) (122 ys at fs=82.768 kHz) in the SLOW and SLEEP modes. ‘The TLCS-870/C is placed in the signal-clock mode during reset. ‘To use the dual-clock mode, the low- frequency oscillator should be turned on at the start of a program. 1) NORMAL2 mode In this mode, the CPU core operates with the high-frequency clock. On-chip peripherals operate using the high-frequency clock and/or low-frequency clock, 2) SLOW2 mode In this mode, the CPU core operates with the low-frequency clock, while both the high-frequency clock and the low-frequency clock are operated. On-chip peripherals are triggered by the low-frequency clock. ‘As the SYSCK on SYSCR2 becomes “O”, the hardware changes into NORMAL2 mode. As the XEN on SYSCR2 becomes “0”, the hardware changes into SLOW1 mode. Do not clear XTEN to “0” during SLOW2 mode. 3) SLOW1 mode ‘This mode can be used to reduce power-consumption by turning off oscillation of the high-frequency clock. ‘The CPU core and on-chip peripherals operate using the low-frequency clock. ‘Switching back and forth between SLOWI and SLOW2 modes are performed by XEN bit on the system control register 2 (SYSCR2), In SLOW] and SLEEP mode, the inputclock to the Ist stage of the divider is stopped; output from the Ist to 6th stages is also stopped. ® IDLE2 mode In this mode, the internal oscillation circuit remain active. The CPU and the watchdog timer are halted however, on-chip peripherals remain active (operate using the high-frequency clock and/or the low- frequency clock). Starting and releasing of IDLE2 mode are the same as for IDLE1 mode, except that operation returns to NORMAL? mode. 86CM25-11 2003-05-15TOSHIBA TMP86CM25/S25 5) SLEEP mode In this mode, the internal oscillation circuit of the low-frequency clock remains active, The CPU, the ‘watchdog timer, and the internal oseillation circuit of the high-frequency clock are halted ; however, on- chip peripherals remain active (operate using the low-frequency clock). Starting and releasing of SLEEP mode are the same as for IDLE1 mode, except that operation returns to SLOW mode. In SLOW and SLEEP mode, the input clock to the Ist stage of the divider is stopped; output from the Ist to 6th stages also stopped. © SLEEP2 mode ‘The SLEEP2 mode is the idle mode corresponding to the SLOW2 mode. ‘The status under the SLEEP2 ‘mode is same as that under the SLEEP mode, except for the oscillation circuit of the high-frequency lock. 7) SLEEPO mode In this mode, all the cireuit, except oscillator and the Timer-Base-Timer, stops operation, ‘This mode is enabled by setting “1” on bit TGHALT on the system control register 2(SYSCR2). ‘When SLEEPO mode starts, the CPU stops and the timing generator stops feeding the clock to the peripheral circuits other than TBT. ‘Then, upon detecting the falling edge of the source clock selected with TBICR, the timing generator starts feeding the clock to all peripheral cireuits, ‘When returned from SLEEPO mode, the CPU restarts operating, entering SLOWI mode back agai SLEEPO mode is entered and returned regardless of how TBTCR is set. When IMF= “1”, ERs (TBT interrupt individual enable flag)= “1”, and TBTCR = “1”, interrupt processing is performed. When SLEEPO mode is entered while TBTCR="1", the INTTBT interrupt latch is set after returning to SLOW1 mode. (3) STOPmode In this mode, the internal oscillation circuit is turned off, causing all system operations to be halted. ‘The internal status immediately prior to the halt is held with a lowest power consumption during STOP mode. STOP mode is started by the system control register 1 (SYSCR1), and STOP mode is released by a inputting (either level-sensitive or edge-sensitive can be programmably selected) to the STOP pin. After the warming-up period is completed, the execution resumes with the instruction which follows the STOP mode start instruction. 86CM25-12 2003-05-15TOSHIBA TMP86CM25/S25 "LED mode Reretrelease | RESET SYSCRZ = "17 Note? SYSCR2 = "1" S¥Schi SYSCRR ="1" SYSCRR syscar rue NORMAL mode mode interrupt STOP pininput SYSCRR = /syscRa = "1" stoP SYSCR2 = 1" steer2 [p= SEE stowe mode mode interrupt SYSCR2 = "17 syscR2 = "1" SYSCRI ="1" ‘SLEEPH stow! mode 5 mode interrupt STOP pin input ual clock mode (0 Dus lock ms ote? [sscmcronatr> 1 SLEEPO mode Note I: NORMAL! and NORMAL2 modes are generically called NORMAL ; LOW! and SLOW? are called SLOW ; IDLEO, IDLE! and IDLE2 are called IDLE: SLEEPO, SLEEPY and SLEEP2 are called SLEEP. Note 2:The mode i released by falling edge of TBTCRTBTCK.> seting ar = ae Operating Mode os PU core, Ter Onn Toes reioreas_|_cycetine TSE fa fat tem HoHVALT} ox Geet et sae operate side Tous] “ton | sop ope ius vo we = stor —| “fon Ta TORWAT Speaiewth Tighe wets BE] one. mn sowa | von Spats ova owt | Ttowteeg | opr | operate aaa ‘en [ta oat \ ‘sLowt Operate with aii) ona 0 [SLEEPY ° Sie vat we STOP ‘Stop Hatt “! Figure 1-7. Operating Mode Transition Diagram 86CM25-13 2003-05-15TOSHIBA TMP86CM25/S25 ‘System Control Register pose ss gsc) (stor [re [rem [Ouray] wT] (rita value 0000 006) mode art 0: CPU core and peripherasremain acive stop _|stoP meds {CPU cove and peripherals are hated (start STOP made) RELM | Release method forsTOP mode |{) Fége-sensitve release ‘Operating mode after STOP |0: Retumn to NORMALY/2 mode rer | mode {i Return SLOW mode ‘ouTEN |Portoutput during STOP mode |: High Impedance mw puting 3: Ouiputkept Return toNORWAL mode [_ReturntoSLOW mode werming-up ‘easing | Pe Era wor |Warming-up time ateeleasing | °° om on TOPmode STOP mod 0 ax2tite er i re Ps syscrz (033%) [Note 1: Alwaysset RETM to “0” when transiting from NORMAL mode to STOP mode. Always set RETM fo 1" ‘when transiting from SLOW mode to STOP mode. ‘Note 2: When STOP mode is released with RESET pin input, a returns made to NORMAL! regardless of the RETM contents Note 3: f: High frequency clock [Mz 1: Low-frequency clock [Hz *= Don't care ‘Note 4: Bits 1 and’ in SYSCRI are read as undefined data when 3 read instruction is executed. [Note 5: As the hardware becomes STOP mode under QUTEN = "0", input values fixed 0“ ‘ause interrupt request on account of falling edge. [Note 6: When the Key on wake-up isused, the edge release can nat function according to some conditions. Itis recommended tase the level release (RELM = 1") ‘ote 7: Port P20'sused as STOP pin. Therefore, when stop mode isstarted, OUTEN does not affect to P20, and P20 becomes High Z mode. therefore it may ‘System Control Register 2 poe sg KEN] MIEN [S¥SeK | IDLE SHAT (ita value: 1000 +0¥+) fo: Tum off esilation xEN | High-frequency oxilator contol |: Turn off oxcilation fo: Tur off esilation xTEN | Low-frequency oscillator control. | 0: Turn off osiation ‘Main system lock select (write). [0: High-frequency clock SYSCK_|mainsystem clock monitor read) |: Low-frequency dock aw &: CPU and watchdog timer remain active ‘CPU and watchdog timer control rove | Covad watchdog timer 1; CBU and watchdog timer are stopped (OLETE, SKEEPIZ mode) (StartIDLE1/2, SLEEPII2 mode) Teconvel 0: Feeding dock a peripherals rom TS ToHALT mode 1: Stap feeding clock to peripherals except TBT from TG. (O60, SLEEPO mode) (Start OLED, SLEEPO mode) [Note 1: A resets applied if both XEN and XTEW are cleared to “O", XEN cleared to “0” when SYSCK = XTENis cleared to "0" when SYSCK = "1" Note 2: =: Don't care, TG: Timing generator ‘Note 3: Bits3, 1and0 in SYSCRD are always read as undefined value ‘Note 4: Do nat et IDLE and TGHALT to "I simultaneously, ote 5: Because returning from IDLEDISLEEPO to NORMAL /SLOWT i execute by the asynchronous internal lock, the period of IDLEDISLEEPO mode might be shorter than the period setting by TBTCR< TBTCK>. ‘Note 6: When IDLETI2 or SLEEPI/2 mode is released, IDLE is automatically cleared to "0" ‘Note 7: When IDLEO or SLEEPO modes released, TGHALTis automaticaly cleared to “0” ‘Note 8: Before setting TGHALT to "1", be sure tostop peripherals. If peripherals are not stopped, the interrupt latch of peripherals may beset after IDLEO or SLEEPO mode is released. Figure 1-8. System Control Registers 86CM25-14 2003-05-15TOSHIBA TMP86CM25/S25 144 0} Operating Mode Control ‘STOP mode STOP mode is controlled by the system control register 1, the STOP pin input and key wake-up input (STOP2 to STOPS) which is controlled by the STOP mode release control register (STOPCR). ‘The STOP pin is also used both as a port P20 and an INTS (external interrupt input 5) pin. STOP mode is started by setting STOP (bit 7 in SYSCR1) to “1”, During STOP mode, the following status is maintained, Oscillations are turned off, and all internal operations are halted. 2) The data memory, registers, the program status word and port output latches are all held in the status ineffect before STOP mode was entered. }) The prescaler and the divider ofthe timing generator are cleared to “0”. ) The program counter holds the address 2 ahead of the instruction (e.g. [SET (SYSCR1).7)) which started STOP mode. ‘STOP mode includes a level-sensitive mode and an edge-sensitive mode, either of which can be selected with the RELM (bit 6 in SYSCR1). Do not use any STOPx (x: 2 to 5) pin input for releasing STOP mode in edge-sensitive mode, Note 1: STOP pin doesn’t have the control register such as STOPCR, 50 when STOP mode is relesed by STOPx (x: 2 to), STOP pin should be used as STOP function. Note2: During STOP period (rom start of STOP mode to end of warming-up), due to changes in the external interrupt pin signal, interrupt latches may be set t0 “1” and interrupts may be ‘accepted immediately after STOP mode is released. Before starting STOP mode, therefore, disable interrupts. Also, before enabling interrupts after STOP mode is released, clear unnecessary interrupt latches. Level-sensitive release mode (RELM="“1") In this mode, STOP mode is released by setting the STOP pin high or setting the STOPx (x: 2 to 5) pin input which is enabled by STOPCR. This mode is used for capacitor back-up when the main power supply is cut off and long term battery back-up. ‘When the STOP pin input is high or STOPx (x: 2 to 5) pin input which is enabled by STOPCR is low, executing an instruction which starts STOP mode will not place in STOP mode but instead will immediately start the release sequence (warm-up). Thus, to start STOP mode in the level-sensitive release mode, itis necessary for the program to first confirm that the STOP pin input is low and STOPx (x: 2 to 5) pin input which is enabled by STOPCR is high. ‘The following two methods can be used for confirmation. @ Testing a port P20. ® Using an external interrupt input INTS (INTS is a falling edge-sensitive input). Example 1: Starting STOP mode from NORMAL mode by testing a port P20. LD __(SYSCR1),01010000B ; Sets up the level-sensitive release mode SSTOPH: TEST (P2PRD)..0 3 Wait until the STOP pin input goes low level IRS F,SSTOPH SET (SYSCRI).7 5 Starts STOP mode 86CM25-15 2003-05-15TOSHIBA TMP86CM25/S25 Example 2: Starting STOP mode from NORMAL mode with an INTS interrupt. PINTS: TEST (P2PRD).0 3 Toreject noise, STOP mode does not start if IRS. F,SINTS port P20 is athigh LD_ (SYSCR1),01010000B ; Sets up the level-sensitive release mode. SET (SYSCRI).7 5 Starts STOP mode SINTS: RETI STOP pin \ p xourpn I Lg 1 NORMAL __ stop Warmup —ole— NORMAL ‘operation ‘operation P= operation Confirm by program that the ‘STOP mode is released by the hardware. Stsmipuctiowardsan TO, ate ceed ya STOP mode, pin input is high. Figure 1-9. Level-sensitive Release Mode ‘Note 1: Even if the STOP pin input is low or STOP (x: 2 to 5) pin input which is enabled by STOPCR is high after warming up start, the STOP mode is not restarted. Note 2: In this case of changing to the level-sensitive mode from the edge-sensitive mode, the release ‘mode is not switched until arising edge of the STOP pin input is detected, b, Edge-sensitive release mode (RELM="0") In this mode, STOP mode is released by a rising edge of the STOP pin input. This is used in applications where a relatively short program is executed repeatedly at periodic intervals. This periodic signal (for example, a clock from a low-power consumption oscillator) is input to the STOP pin. In the edge- sensitive release mode, STOP mode is started even when the STOP pin input is high level. Do not use any STOPx (x: 2 to 5) pin input for releasing STOP mode in edge-sensitive release mode. Example: Starting STOP mode from NORMAL mode LD (SYSCR1), 100100008 ; Starts after specified to the edge-sensitive release mode NORMAL sto? stor Operation oon —>be Warm-up cperstion — Pe on NORMAL Pe STOP mode started operation, bythe program ‘STOP mode is eleased by the hardware atthe rising edge of STOP pin input Figure 1-10. Edge-sensitive Release Mode 86CM25-16 2003-05-15TOSHIBA TMP86CM25/S25 ‘STOP mode is released by the following sequence. © In the dual-clock mode, when returning to NORMAL or SLOW2, both the high-frequency and low- frequency clock oscillators are turned on ; when returning to SLOW mode, only the low-frequency clock oscillator is turned on. In the signal-clock mode, only the high-frequency clock oscillator is, turned on, ® A warm-up period is inserted to allow oscillation time to stabilize, During warm-up, all internal operations remain halted. Four different warm-up times can be selected with the WUT (bits 2 and 3 in SYSCR1) in accordance with the resonator characteristics. ® When the warm-up time has elapsed, normal operation resumes with the instruction following the STOP mode start instruction. The start is made after the prescaler and the divider of the generator are cleared to “0”. Table 1-1. Warm-up Time Example (at fe= 16.0 MHz, fs = 32.768 kH2) wr Warnvup Time fra) Reyne NORMAL mode. Relurn esl OW mode 0 12.288 750 or 4.096 250 10 3072 585 ms 1.028 195 Note: The warm-up time is obtained by dividing the basic clock by the divider: therefore, the warm-up time may include a certain amount of error if there is any fluctuation of the oscillation frequency when STOP mode is released. Thus, the warm-up time must be considered an approximate value, STOP mode can also be released by inputting low level on the RESET pin, which immediately performs the normal reset operation, Note: When STOP mode is released with a low hold voltage, the following cautions must be observed. The power supply voltage must be at the operating voltage level before releasing STOP ‘mode. The RESET pin input must also be “H” level, rising together with the power supply voltage. In this case, if an external time constant circuit has been connected, the RESET pin input voltage will increase at a slower pace than the power supply voltage. At this time, there isa danger that a reset may occur if input voltage level of the RESET pin drops below the non-inverting high-level input voltage (hysteresis input) 86¢M25-17 2003-05-15‘TMP86CM25/S25 TOSHIBA aseajayuers apo dOIS “11-1 2un61g sea) 990 4015 (@) aE spo Tarver JOSS OS FX a saunoo vielBong ORT) 4nowint, FT waists at = XX eX aX ao X 7 XC sew 7 TE ness = x ao XE a ATU ee [ ToL par 2003-05-15 86CM25-18TOSHIBA TMP86CM25/S25 (2) IDLE1/2 mode, SLEEP1/2 modes IDLE1/2 and SLEEP1/2 modes are controlled by the system control register 2 (SYSCR2) and maskable interrupts. The following status is maintained during these modes, @ Operation of the CPU and watchdog timer (WDT) is halted. On-chip peripherals continue to operate. ® The data memory, CPU registers, program status word and port output latches are all held in the status in effect before these modes were entered. ® The program counter holds the address 2 ahead of the instruction which starts these modes. Z Starting DLEW2 and SLEEPI/2 modes by instruction q (CPU, WOT are halted ) ’ Yes (interrupt release mode) Interrupt processing | Execution ofthe instruction which fllows the IDLE? and SLEEPI/2 modes start instruction + Figure 1-12. IDLE1/2, SLEEP1/2 Modes 86CM25-19 2003-05-15TOSHIBA TMP86CM25/S25 © Start the IDLE1/2 and SLEEPI/2 modes ‘When IDLEL/2 and SLEEPL/2 modes start, set SYSCR2 to“1” © Release the IDLE1/2.and SLEEP1/2 modes IDLE1/2 and SLEEP1/2 modes include a normal release mode and an interrupt release mode. ‘These modes are selected by interrupt master enable flag (IMF). After releasing IDLE1/2 and SLEEP1/2 modes, the SYSCR2 is automatically cleared to “0” and the operation mode is returned to the mode preceding IDLE1/2 and SLEEP1/2 modes. IDLEL/2 and SLEEP1/2 modes can also be released by inputting low level on the RESET pin. Alter releasing reset, the operation mode is started from NORMALI mode. a,_Normal release mode (IMF=“0") IDLE1/2 and SLEEPI/2 modes are released by any interrupt source enabled by the individual interrupt enable flag (EF). After the interrupt is generated, the program operation is resumed from the instruction following the IDLE1/2 and SLEEPL/2 modes start instruction, Normally, the interrupt latches (IL) of the interrupt source used for releasing must be cleared to “O” by load instructions. b, Interrupt release mode (IMF ="1") IDLE1/2 and SLEEPI/2 modes are released by any interrupt source enabled with the individual interrupt enable flag (EF) and the interrupt processing is started. After the interrupt is processed, the program operation is resumed from the instruction following the instruction, which starts IDLEL/2 and SLEEPL/2 modes. Note: When a watchdog timer interrupts is generated immediately before IDLE1/2 and SLEEP1/2 mode are started, the watchdog timer interrupt will be processed but IDLE1/2 and SLEEP1/2 mode will not be started. 86CM25-20 2003-05-15‘TMP86CM25/S25 TOSHIBA aseareuniers @pow 7101 ys 9pou 3 ana, Teo, Tee RADE START ayduierg) wey apou 3701 (©) Tendo, meses ae 2003-05-15 86CM25-21TOSHIBA TMP86CM25/S25 (3) IDLEO, SLEEPO mode (IDLEO,SLEEPO) IDLEO and SLEEPO modes are controlled by the system control register 2 (SYSCR2) and the time base timer control register (TBTCR). ‘The following status is maintained during IDLEO and SLEEPO modes. © Timing generator stops feeding clock to peripherals except TBT. ® The data memory, CPU registers, program status word and port output latches are all held in the status in effect before IDLB0 and SLEEPO modes were entered. ® The program counter holds the address 2 ahead of the instruction which starts IDLEO and SLEEPO modes. Note: Before starting IDLEO or SLEEPO mode, be sure to stop (disable) peripherals. Y “Stopping Peripherals by instruction q ‘Starting OLED, SLEEPO mode by instruction T (CPU, WOT are halted 4 Reset oi (Worm elease mode) Fes interrupt release mode) Interrupt processing —i Execution ofthe instruction when fallow ‘the IDLEO, SLEEPO mode ¥ Figure 1-14, IDLEO, SLEEPO mode 86CM25-22 2003-05-15TOSHIBA TMP86CM25/S25 © Start the IDLE0 and SLEEPO modes Stop (disable) peripherals such as a timer counter. When IDLEO and SLEEPO modes start, set SYSCR2 to“l”. © Release the IDLB0 and SLEEP modes IDLEO and SLEEPO modes include a normal release mode and an interrupt release mode. ‘These modes are selected by interrupt master flag (IMF), individual interrupt enable-flag (EF6) for INTTBT and TBICR. After releasing IDLEO and SLEEPO modes, the SYSCR2 is automatically cleared to “0” and the operation mode is returned to the mode preceding IDLE0 and SLEEPO modes. Before starting the IDLEO or SLEEPO mode, when the TBICR is set to “I”, INTTBT interrupt latch is set to “1”. IDLEO and SLEEPO modes can also be released by inputting low level on the RESET pin, After releasing reset, the operation mode is started from NORMAL1 mode. Note: IDLEO and SLEEPO modes startirelease without reference to TBTCR setting. a._Normal release mode (IMF - EF6-'TBTCR =“0") IDLEO and SLEEPO modes are released by the source clock falling edge, which is setting by the ‘TBTCR. After the falling edge is detected, the program operation is resumed from the instruction following the IDLEO and SLEEPO modes start instruction, b, Interrupt release mode (IMF -EF6- TBTCR =“1") IDLEO and SLEEPO modes are released by the source clock falling edge, which is setting by the ‘TBTCR and INTTBT interrupt processing is started. [Note 1: Because returning from IDLEO, SLEEPO to NORMALI, SLOW1 is executed by the asynchronous internal clock, the period of IDLEO, SLEEPO mode might be the shorter than the period setting by TBTCR. 'Note2: When a watchdog timer interrupt is generated immediately before IDLEO / SLEEPO mode is started, the watchdog timer interrupt will be processed but IDLEO | SLEEPO mode will not bestarted. 86CM25-23 2003-05-15‘TMP86CM25/S25 TOSHIBA (esseippee p asearsysues apow 043315 07IGl “Si-1 aun ssoj1 pow oa "03101 (a) ECE] Wane jo ue aa ERO FICS ORTS 2003-05-15 86CM25-24TOSHIBA TMP86CM25/S25 (3) SLOW mode ‘SLOW mode is controlled by the system control register 2 (SYSCR2).. ‘The following is the methods to switch the mode with the warming-up counter (TC4, 3). ‘Switching from NORMAL? mode to SLOW1 mode First, set SYSCK (bit 5 in SYSCR2) to switch the main system clock to the low-frequency clock for SLOW2 mode. Next, clear XEN (bit 7 in SYSCR2) to turn off high-frequency oscillation. Note: The high-frequency clock oscillation can be continued to return quickly to NORMAL2 mode. ‘When the low-frequency clock oscillation is unstable, wait until oscillation stabilizes before performing the above operations. The timer/counter 4, 3 (C4, TC3) can conveniently be used to confirm that low- frequency clock oseillation has stabilized. Examplel: Switching from NORMAL? mode to SLOW1 mode. SET (SYSCR2).5 ; SYSOR2 <1 (switches the main system clock to the low-frequency clock for SLOW2) CLR (SYSCR2).7 ; SYSCR2 <0 (turns off high-frequency oscillation) Example2: Switching to the SLOW! mode after low-frequency clock has stabilized. LD (TC8CR),48H ——;_ Sets mode for TC4, 703 (16-bit TC, fs for source) LD (TC4CR), 05H LDW (TTREGS),8000H ; Sets warming-up time (depend on oscillator accompanied) DI ; IMF <1 (Switches the main system clock to the low-frequency clock) CLR (SYSCR2).7 ; SYSCR2 <0 (Turns off high-frequency oscillation) RETI VINTTC4: DW PINTTC4 5 INTTC4 vector table 86CM25-25 2003-05-15TOSHIBA ‘TMP86CM25/S25 b. Switching from SLOW1 mode to NORMAL? mode First, set XEN (bit 7 in SYSCR2) to turn on the high-frequency oscillation. When time for stabilization (warm-up) has been taken by the timer/counter 4, 3 (TC4, 3), clear SYSCK (bit 5 in SYSCR2) to switch ‘the main system clock to the high-frequency clock. Note 2: SLOW mode can also be released mode. Note 1: After SYSCK is cleared to “0”, executing the instructions is continued by the low-frequency clock for the period synchronized with low-frequency and high-frequency clocks. Hioh-frequengycleck = FUTUTLPULUnUeouur Low-frequency lock =| Lf Maingystemdoce =| Lonnie sysee ————>____ ‘by inputting low level on the RESET pin, which immediately performs the reset operation. After reset, the TMP86CM25iS25 are placed in NORMALT Example: Switching from the SLOW1 mode to the NORMAL2 mode SET (SYSCR2).7 : LD (TC3CR), 63H; LD (TCACR), 05H LD (TTREG4), OF8H DI SET (EIRE).3 EL SET (TC4CR).3 PINTTCA: CLR (TCACR).3 : CLR (SYSCR2.5 RETI VINTTC4: DW PINTTC4 : (6 MHz, warm-up time is 4.0 ms). SYSCR2 «1 (Starts high-frequency oscillation) Sets mode for TC4, TC3 (16-bit TC, fe for source) Sets warming-up time IMF <0 Enables INTTC4 IMF<1 Starts TC4,3 Stops TC4,3 SYSCR2 <0 (Switches the main system lock to the high-frequency clock) INTTC4 vector table 86CM25-26 2003-05-15‘TMP86CM25/S25 TOSHIBA S2POW MONS PLE ZTYINUON 49 Yoamneq BuNpprIMS “91-1 21nBLy pow ZTWAWON a 02 BPMs (@) opow Mors ‘pou zmrs Buunp dn weg po Saas pou mors pou mors A402 BUNPHINS (2) sou 1_EIVAWON youn Tepe TCT YX wens (wm vss eh sousnb souerbes, 2003-05-15 86¢M25-27TOSHIBA TMP86CM25/S25 41.5 Interrupt Control Circuit ‘The TMP86CM25/S25 area total (Reset is excluded) of 15 interrupt sources for 20 interrupt factors; 4 of the sources are multiplexed. Multiple interrupt with priorities is available. 4 of the internal factors are non-maskable interrupts, andthe restof them are maskable interrupts, Interrupt sources are provided with interrupt latches (IL), which hold interrupt requests, and independent vectors. The interrupt latch is set to “1” by the generation of its interrupt request which requests the CPU to accept its interrupts. Interrupts are enabled or disabled by software using the interrupt master enable flag (IMF) and interrupt enable flag (EF). If more than one interrupts are generated simultaneously, interrupts are accepted in order which is dominated by hardware, However, there are no prioritized interrupt factors among non-maskable interrupts. Table 1-2. Interrupt Sources Interrupt Factors Enable condition | "VeruPt | Vester | priority wer Tse vonmosante | — | een [wah 1 Internal _[INTSWSofeware interrupt Normastabie | _—_|_#FeH z Internal_[INTUNDEF (Executed the Undefined Instruction interrupt) [Non-moskable | — | FFFcH 2 Internal | NTATRAP (Address Trap interrupt) Non-maskable | 2 | FAH 2 Interal_[INTWOT (Watendog Timer intereupd) Non-maskable | ua | FFFBH 2 xterm [INTO (External ierupt) twr=sere=1 | ua | row 5 fsternal_[INT (Exteral interne 1 us| Fran 6 Internal [INTE (Time Base Timerinterup®) ue | FFFaH 7 txternal_[INT2 (External interrupt) | Fron 3 Interal_[INTTCr (18-bTCI interwpd ue | FeEH 2 Fnterat_|IVTRED (UART received inerrap) an "0 interna iNTSI00 (100interupt F internal_| WTO (UART ranamistedineerup®) cluweeneron: | uo | wean y Interna (S101 interrupt) Internal_INTTC#(TCaterupe) in _| een 2 Interal_[ WTTCBCTE6 interrupt) iia |rreoH 8 Interal_[INTADC (AD converter interup®) iui FreaH 14 F exernat_|IN3 (xteral interrupt 3) ua | even 5 Internal” WTTCS (Te interupe) F exernal_[INTS (xteral interrupt 5) us | mm | iwi Internal” [INTTES (1S terupd) Note 1: The following interrupt factors share their interrupt source; the factor is selected on the register INTSEL 1) INTRXD and INTSIO0 share the source whose priority 10 2). INTTXD and INTSION share the source whose priority 1. 3). INT3.and INTTC3 share the source whose priori 15 4) NTS and INTTCS share the source whose priority is 16. Note 2:To.use the addres trap interrupt (NTATRAP), clear WOTCRI to “0” (it sset forthe “reset request” after resets cancelled). For detail se@ 2.4.5 Address Trap. Note 3: To use the watchdog timer interrupt (INTWON), clear WDTCRI to “0” (it sset forthe “reset request” after resets cancelled). For detail e@ 24 Watchdog Timer. 86CM25-28 2003-05-15‘TMP86CM25/S25 TOSHIBA wesBelq ypojg sejjoauoyydnuaiul “1-1 22n61y [anerssnornana 2003-05-15 86CM25-29TOSHIBA TMP86CM25/S25 a Q a) Interrupt Latches (1L15 to IL2) ‘An interrupt latch is provided for each interrupt source, except for a software interrupt. When interrupt request is generated, the latch is set to “I”, and the CPU is requested to accept the interrupt if its interrupts enabled. All interrupt latches are initialized to “O” during reset, ‘The interrupt latches are located on address 003CH and 003DH in SFR area, Except for IL3 and IL2, each latch can be cleared to “0” individually by instruction (However, the read-modify-write instructions such as bit manipulation or operation instructions cannot be used. Interrupt request would be cleared inadequately if interrupt is requested while such instructions are executed.). Thus interrupt request can be canceled/initialized by software. Interrupt latches are not set to “I” by an instruction, Since interrupt latches can be read, the status for interrupt requests can be monitored by software. Note: When manipulating It, clear IMF (to disable interrupts) beforehand. Example 1: Clears interrupt latches DI > IMF atExecutionof >) atExecutionof > at Execution of ‘aninterrupt Pusi instruction PoP instruction an RETlinstuetion ) Using data transfer instructions ‘To save only a specific register without nested interrupts, data transfer instructions are available. Example: Savelstore register using data transfer instructions PINTxx: LD (GSAVA),A 3 Save A register (interrupt processing) LD__A,(GSAVA) 3 Restore A register RET 3 RETURN Main tase Interrupt terrupt Reepidnce service tank [TTT soving registers [TTT] Restoring registers Tnterruptreturn Savingirestoring general-purpose registers using PUSHIPOP instruction Figure 1-21. Saving/Restoring General-purpose Registers Under Interrupt Processing 86CM25-34 2003-05-15TOSHIBA TMP86CM25/S25 8) Interrupt return Interrupt return instructions [RETI/[RETN] perform as follows. IRETIVIRETN] Interrupt Return {@ Program Counter (PC) and program status word (@5W, includes MF) are restored from the stack, @ stack pointer (SP)isincremented by 3. As for Address Trap interrupt (INTARTAP), it is required to alter stacked data for program counter (PC) to restarting address, during interrupt service program. Otherwise returning interrupt causes INTATRAP again, When interrupt acceptance processing has completed, stacked data for PCL and PCH are located on address (SP+ 1) and (SP +2) respectively. ‘Example 1: Returning from address trap interrupt (INTATRAP) service program. PINTxx: POP WA. 3 Recover SPby 2 LD _ WA,Return Address; PUSH WA 5 Alterstacked data (interrupt processing) RETN 3 RETURN Example 2; Restarting without returning interrupt (in this case, PSW (includes IMF) before interrupt acceptance is discarded.) PINTxx: INC SP 3 Recover SP by3 INC SP 3 INC SP ; (interrupt processing) LD EIRL, data 5 SetIMF to“1” or elearit to“0” JP Restart Address; Jumpinto restarting address Itis recommended that stack pointer be return to rate before INTATRAP (increment 3 times), if return interrupt instruction [RETN] is not utilized during interrupt service program under INTATRAP (such as Example 2). Interrupt requests are sampled during the final cyele of the instruction being executed. Thus, the next interrupt ean be accepted immediately after the interrupt return instruction is executed. ‘Note: When the interrupt processing time is longer than the interrupt request generation time, the interrupt service task is performed but not the main task. 86CM25-35, 2003-05-15TOSHIBA TMP86CM25/S25 152 153 154 155 Software Interrupt (INTSW) Executing the [SWI] instruction generates a software interrupt and immediately starts interrupt processing (INTSW is highest prioritized interrupt). ‘Use the (SWI instruction only for detection of the address error or for debugging. ) Address error detection FF is read if for some cause such as noise the CPU attempts to fetch an instruction from a non-existent ‘memory address during single chip mode. Code FF is the SWI instruction, so a software interrupt is generated and an address error is detected. The address error detection range can be further expanded by writing FFy to unused areas of the program memory. Address-trap reset is generated in case that an instruction is fetched from RAM or SFR areas. ») Debugging Debugging efficiency can be increased by placing the SWI instruction at the software break point setting address. Undefined instruction Interrupt (INTUNDEF) ‘Taking code which is not defined as authorized instruction for instruction eauses INTUNDEF. INTUNDEF is generated when the CPU fetches such a code and tries to execute it. INTUNDEF is accepted even if non-maskable interruptis in process. Contemporary process is broken and INTUNDEF interrupt process starts, soon after it is requested. ‘Note: The undefined instruction interrupt (INTUNDEF) forces CPU to jump into vector address, as software interrupt (SW/) does. Address Trap interrupt (INTATRAP) Fetching instruction from unauthorized area for instructions (address trapped area) causes reset-output or address trap interrupt (INTATRAP). INTATRAP is accepted even if non-maskable interrupt is in process. Contemporary process is broken and INTATRAP interrupt process starts, soon after it is requested. ‘The address trapped area is alternative: SFR and RAM, or SFR only. ‘Note: The operating mode under address trapped, whether to be reset-output or interrupt, processing, is selected on watchdog timer control register (WDTCR). External Interrupts ‘The TMP86CM25/S25 have five external interrupt inputs. These inputs are equipped with digital noise reject circuits (pulse inputs of less than a certain time are eliminated as noise). Edge selection is also possible with INTI to INT3. The INTO/P63 pin can be configured as either an external interrupt input pin or an input/output port, and is configured as an input port during reset. Edge selection, noise reject control and INT0/P63 pin function selection are performed by the external interrupt control register (EINTCR). 86CM25-36 2003-05-15TOSHIBA TMP86CM25/S25 Table 1-3. External interrupts =a source [Pin | ence, | enatiecondtions | __ eave Digital nove reject Ee ei onea eae INTO. 70 PORAINS | iTOEN = 1 falling edg pulses of less than 1/fs [5] are eliminated as PIISEGSE eliminated as noise. Pulses of 49/fc or 193/fc tt mus eo IMF-EFS= 1 [s] or more are considered to be signals. (ote a) | P3WCOMS ‘In the SLOW or the SLEEP mode, pulses of less rianese roingecge | ay ble cinta ne et (Note ay | _P35/COME Rising edge noise. Pulses of 25/fc [s] or more are Pe ce Ieihe SSW ore SP mode, pus of le use up lr cae na NTS NTS PROSTOP HHLISER =O falling edge pulses of less than 1/fs [5] are eliminated as te a Note 1: If a noiseless signal is input to the external interrupt pin in the NORMAL 1/2 or IDLE 1/2 ‘mode, the maximum time from the edge of input signal until the IL is set is as follows © INT? pin 55ifc [5] (INTINC =1), 199/fc 5] (INTINC =0) @ INT2, INT3 pin 31/fc[s] Note 2: Even if the falling edge of INTO pin input is detected at INTOEN =0, the interrupt latch ILs is notset. ‘Note 3: When data changed and did a change of 110 when used external interrupt ports as a normal ports, interrupt request signal occurs incorrectly. Handling of prohibition of interrupt enable register (EIR) is necessary. Note 4: MUL4 to 6s interrupt input can be changed by the MULSEL register. Note 5: The maximum time from modifying INTINC until a noise reject time is changed is ¢/f. eINTeR 00374) External interrupt control register he Bodh 8 a2 (ital value: 00+ 0000 Pulses of less than 637 [3] are eliminated as noise INTING | Noise reject time select Pulses of less thon 15/fe[s] ore eliminated os noise — P63 inpuVOutput port INTOEN | P63/INTO pin configuration 1: INTO pin (Port P63 should be set to an input mode) RW wae Intaés |inraromtedgesetee | 9: Raingedge INTIES wg econ ‘ote 1: fe: High frequency clock [2], : Don't care ‘Note 2: When the system clock frequency is switched between high and low or when the external interrupt «control register (EINTCR) is overwritten, the noise canceler may not operate normally. Iti recommend that external interrupts are disabled using the interrupt enable register (IR). Figure 1-22. External Interrupt Control Register 86¢M25-37 2003-05-15TOSHIBA ‘TMP86CM25/S25 1.6 Reset Circuit ‘The TMP86CM25/S25 have four types of reset generation procedures: an external reset input, an address trap reset, a watchdog timer reset and a system clock reset. Table 1-4 shows on-chip hardware initialization by reset action. ‘The malfunction reset circuit such as watchdog timer reset, address trap reset and system clock reset is not initialized when power is turned on, The reset operation might occur for the maximum 24/fe(s] (1.5 sat 16.0 MHz) when power is turned on, Table 1-4. Initializing Internal Status by Reset Action onahiphadnare alate Onchphardware alate gamcourr acre tack oo (| Wotiniaized recat and der fing 3 cee purpi ear Totinilzed —fpererater WAB.CO.E4. Fompattag Ge)| tinted — waraogine cae erg ae Notiniaed ea og (c1| inated at aya (ae | tite sign. 9 : (5H)| _Notinitiaized | MPuIatenes oF O Pores overtow ap wer] tinted nieruptmntrenaiefag —wer[ — 0 veraptndil erble fas ° const registers feteroeniot aa as w] 2 RAM Netinialized 1.6.1. External Reset Input ‘The RESET pin contains a Schmitt trigger (hysteresis) with an internal pull-up resistor. ‘When the RESET pin is held at “L” level for at least 3 machine cycles (12ife [s]) with the power supply voltage state i alized. in the operating voltage range and oscillation stable, a reset applied and the internal ‘When the RESET pin input goes high, the reset operation is released and the program execution starts at the vector address stored at addresses FFFE to FFF. m Resetinput Watchdog timer reset MaHfunction| reset output Address trap reset reuit System dock reset Figure 1-23. Reset Circuit 86CM25-38 2003-05-15TOSHIBA TMP86CM25/S25 1.6.2 Address-Trap-Reset If the CPU should start looping for some cause such as noise and an attempt be made to fetch an instruction from the on-chip RAM (when WDTOR1 is set to “I”) or the SFR area, address- trap-reset will be generated. The reset time is about 8ife to 24/fe(s) (0.5 to 1.5 us at 16.0 MHz). er ances 7 Adder soccured : { lena eet at i i Y eiteto2aitets) f ate 1 t6ffels) ‘ satel Note 1: Address “a” isin the SFRor on-chip RAM (WOTCRI = “1°) space NNote2: During eset release, reset vector “?”s readout, and an instruction at address “ris fetched and decoded. Figure 1-24. Address-Trap-Reset ‘Note: The operating mode under address trapped is alternative of reset or interrupt. The address trap area is alternative. 1.6.3 Watchdog Timer Reset Refer to Section “2.4 Watchdog Timer”. 1.6.4. System-Clock-Reset Clearing both XEN and XTEN (bits 7 and 6 in SYSCR2) to “0”, clearing XEN to “O” when SYSCK= or clearing XTEN to “O” when SYSCK="1" stops system clock, and causes the microcomputer to deadlock. This can be prevented by automatically generating a reset signal whenever XEN=XTEN="0", XEN=SYSCK=“0", or XTEN=“0"/SYSCK="1" is detected to continue the oscillation. ‘The reset time is about 8/fe to 24fe [s] (0.6 to 1.5 s at 16.0 MHz). 86CM25-39 2003-05-15TOSHIBA TMP86CM25/S25 2. On-Chip Peripherals Functions 2.4 Special Function Registers (SFRs) ‘The TMP86CM25/825 adopt the memory mapped 1/0 system, and all peripheral control and data transfers are performed through the special function register (SFR). ‘The SFR is mapped on address 0000H to 003FH, DBR ismapped on address OF OOH to OFFFH. Figure 2-1 (a), (b) indicate the special function register (SFR) and data buffer register (DBR) for ‘TMP86CM25/S25. ‘Address Read write ‘address Read write ‘0004 ae omen RG ommesT = ot Biba rom otis 21 [adcbaa Ab convener reper?) = o P20K162 Pot att at 2 ered 3 Froalea ron canta 23 ere 06 ALCA 63 Pore con eps 24 eres 05 roa es ron opti 25 Se ee th 5 PiORee Por ott nn) 26 < [ARTCC cee 0 Broa Gr ron oaptiah ” GSE Leb conareaser (08 ia femal ap) 2 22 SET LCD Corral rege’ 2) (09 |." mmo 62 Fermi. = 29 PUGRO Con egae) (on) o¥ao ea feral ap). 5 2a Biches convo ene) (08 |. SIND 65 fermaal anu = 22 PEK Convo rense) oc| Fen pers novieaipicil 2 west ier egies) (0 rH Termaat ape | - 20] Futced timer repre 8) of [ANGER no consi, 2 REGS Timer ee) oF occ (Ab conalroger?) 2 Pies imerregier) 10 TEEGTAL 30 Reserved n Taeeian ine aaiter A 31 eared 2 Tieoiai 32 ered 3 aes i ogi 33 Reece 4 TOVeH mar Courant) 34 = Pw i ' Sonne ara 3 Mira eosiora 16 [Heise a, . 36 ieieAaHieo vo ome), 7 ieee 37 ENT eral intergecoe 18 Geter Courter ese 38 Sree Sytem cart). 9 GH ine Courter dear 329 Src Sten etl) val ESE merous sea 3a Ec nerogcoabi ont) 8 Gees ner Courter Geo 3 Ei nerrapt raise) 1c ‘ree ime og) 5c ‘Cmte 10| EHkcce (mer oper) 30] rere ate 1 ‘HReGs ime ogte) 3 ine diversi ali ra Fikece mor roger) Fd 0 Grogam Saturwor) Figure 2-1 (a). The Special Function Register (SFR) for TMP86CM25/S25 86CM25-40 2003-05-15TOSHIBA TMP86CM25/S25 LCD Data Buffer (Write/Read) ‘OFOOR__OFTOH = OF20H = OF3OH.|_OFAOH 7 OFSOR_|_OFGOH | OF7OR | como oFoiH oFtIH oF2iH” Fat oF@iH | Orsi” oF6IHoF7H | com ‘orazH “oFt2H oFzaH”oF32H"oraan orsen oFeaH oFM2H| come oFoaHOF13H 0F23H”OF33H OF«aH OFS3H” OFeaH 0F734 | coma ‘roa “"oFtaH orzeH orsaHoraait © orsah oFeaH or7aH | coma foros OFISH”0F25H”OF35H"“OrasH | OFSSH”OFESHOF78H | cOMS ‘ros oFi6H”oF26H”oF36H"“oraGh oFS6H”oF6GHoF76H"| coms ‘ram oFt7H oFa7H” ora7H rand ors7H" orem or77H | com” oFoeHoFTBH”oF2—H”oF36HOraBh oFSeH”OF6BH oF7@H | come ‘Foo oFi9H" 029i” or39H"”“oraoHoFS9H"OFesH0F79H1"| cOM® ‘Oraan“OFiaH or2a” OF3ai! OraaHOFSAH| OFGAH'”OF7AH'| COMO foe oF18H" oF2—N” OF30H OF4BH” OFseH”or6aH 0F78H | commit aFoch’ oFicH*“oF3c”oF3cH””“orachl "oFscH"”” oFech!oF7cH | coma {F00H “OFIDH’ oF2DHOF20HOF4DHOFSDH|OF6DHOF7OH'| COMI oFoeHoFteH oF2eH” OF3EH OFdEH OFSEH” OF6EH OF7eH | coma OFOFHOFIFH”OF2FHOF3FHOFAFHOFSFH”OF6FHOFTFH | COMI SEG? SEGIS SEG23. SEG3I SECS SEGA7 SESS seG59 ‘SECO SEGB SEIS SEG24 SEG32. SEGA SEGHB SEGSE Address Read write ‘oFa0r TORRE, ai Signa sioo euler) a sioner io ute) Fe Ione 10 ater) oa Slonse si exter) Fy Slots 00 eter) 4 Sioasr tio exter) Fy SIotGh 10 ater) ry = roach si ale 99 i Seats egiier once lon carr regster2) ol : Srores on oan ete ‘98 RS ar ewe tain avr Wart warm ac cata ate 9c} serve 90 Reeres o eves cy Fees aq ‘igi io elec) a Sioish si ater) a SIO10R2 1% outer?) aa lola si ater) aa as a Siotars 10% outer a] Sioiah Gi exter) aq 2 oicr si arlreiti ‘ao isis Sar gutn)"”” fioter lot conutracter 2) | eres a series | ‘HULSE iin one See Regie) q eres FF isa Figure 2-1 (b). The Data Buffer Register (DBR) for TMPB6CM25/S25, 86CM25-81 2003-05-15TOSHIBA TMP86CM25/S25 2.2 OPorts ‘The TMP86CM25/S25 have 6 parallel jputloutput ports (42 pins) as follows, Primary Function Secondary Functions PorePt[a-bitvOport [External interrupt input, serial interface input/output, UART input/output and segment output, Portp2 | 3-bitvOport _ | Low-frequency resonator connections, external interrupt input, STOP mode release signal input. Pores |7-bit/Oport _|Timer/Counter input/output and divider output and /segment/common output. PortPs [8-bitvOport | Segment output. Porters [s-bit/Oport | Analog input, external interrupt input, timercounter input and STOP mode release signal input PortP7 [s-bitvOport [Common output. Timer/Counter input/output and divider output. Each output port contains a latch, which holds the output data. All input ports do not have latches, s0 the external input data should be externally held until the input data is read from outside or reading should be performed several timer before processing. Figure 2-2 shows inpuoutput timing examples. External data is read from an VO port in the SI state of the read cycle during execution of the read instruction, This timing eannot be recognized from outside, so that transient input such as chattering ‘must be processed by the program. Output data changes in the S2 state of the write eycle during execution of the instruction which writes toan 10 port. Fetcheycle | Fetcheycle | Read gle ja fetchovce 1 Fetchaycle | Reedley 50 St 82 $3 50 Si 82 53 50 S12 83 Instruction execution cycle te AO ovipnt - a — en: (oh mputining je fithonle Fhoyde | wiearte Digsaieswn ns Output strobe -..,- LL ba ouput, oe coe (©) Outputtiming Note: The postions ofthe read and write cycles may vary, depending onthe instruction. Figure 2-2. Input/Output Timing (Example) 86CM25-02 2003-05-15TOSHIBA TMP86CM25/S25 2.2.4 PortP1 (P17 to P10) Port P1 is an 8-bit input/output port which is also used as an external interrupt input, serial interface inpu¥output, UART input/output and segment output of LCD. When used as a segment pins of LCD, the respective bit of PILCR should be set to “I”, ‘When used as an input port or a secondary function (except for segment) pins, the respective output lateh (PLDR) should be set to “1” and its corresponding PLLCR bit should be set to“0”. When used as an ‘output port, the respective PILCR bit should be set to “0”. During reset, the output latch is initialized tol”, PI port output latch (PIDR) and PI port terminal input (PIPRD) are located on their respective address, ‘When read the output latch data, the PIDR should be read and when read the terminal input data, the PIPRD register should be read. Ifthe terminal input data which is configured as LCD segment output is read, unstable data is read. Contor input Terminal inpu(P1eRO) <<} -J PrLeRi 28 PILCRI input ‘Output latch data (P1DR) ata output 10x) ———=[5_@ }-+-4 +1] Ps utpatiateh conto output Note: 1=7t00 i ——{ >»—_ ouren {co data ourut ae ?7 6 s «4 3 2 1 0 pion [P17 Tig | P15 | pra] pis] pz | pit | P10. (oor |5€c59| sec58| sec57 secs6| secss| secse]|se653|s€652] aiialvaluer 1111 1111) RA | SCKO | TxD | AxD | mus | MULS | MULE 500 | 'sio 00234) vr tmgmantoupaiee : Finpayoipat por or secondary Tncon PILCR [etter each indkadully (expect for segment nw 1: Segment ostput piero [Pi7 | pie | #5 | Pe [Pa | em [en] P10 (008) Read only Note: With ports assigned as MULE to MULO, assigned pins canbe switched by the mult function register (MULSEL) The assigned functions are a follow: muta: BVO mua: rt ‘Mutt: POOR, POO, 73 ‘Muu: inT2 ‘MuL2: PGE PANE, POO rcs MULB: INT -MUL3: PGE, PHIM, PDO, Tos Figure 2-3. Port1 86CM25-03 2003-05-15TOSHIBA TMP86CM25/S25 2.2.2 Port P2(P22 to P20) Port P2 isa -bitinputoutput port. Itis also used as an external interrupt, a STOP mode release signal input, and low-frequency erystal oscillator connection pins. When used as an input port or a secondary function pins, respective output, latch (P2DR) should be set to “I”. During reset, the P2DR is initialized to”. A low-frequency crystal oscillator (32.768 kHz) is connected to pins P21 (XTIN) and P22 (XTOUT) in the dual-clock mode. In the single-clock mode, pins P21 and P22 ean be used as normal inpuvoutput, ports, Itis recommended that pin P20 should be used as an external interrupt input, a STOP mode release signal input, or an input port, Ifitis used as an output port, the interrupt atch is seton the falling edge of the output pulse. 2 port output latch (P2DR) and P2 port terminal input (P2PRD) are located on their respective address. ‘When read the output latch data, the P2DR should be read and when read the terminal input data, the P2PRD register should be read. Ifa read instruction is executed for port P2, read data of bits 7 to 3 are unstable, ata input (°20°RO) —s Data input(P20) Date output (P20) > @ 1] 20 ans, sroP) ourpatiaieh 4 onto input | Data input (P21PRO) Ky Datainpur 21) Ore enable Data outout°21) >a O)e2rom outpatTateh Data input (22°80) -< Datainpur(e22) Data output °22) >a ai {1 p22 ecroun outpataten 78S a P20 Pea] Pat | 20 (o0024) ixrour| xtin | INTs | Initial value: ss 4111) Rw STOP P2eRD fo Le [oa T p20] (0008) Read only Figure 2-4. Port2 ‘Note: Port P20 is used as STOP pin. Therefore, when stop mode is started, OUTEN does not affect to. P20, and P20 becomes High-Z mode. 86CM25-04 2003-05-15TOSHIBA TMP86CM25/S25 2.2.3 Port P3 (P36 to P30) Port P8 is a 7-bit input/output port, It is also used as a External interrupt input, timer/counter inputoutput, divi common/segment output. ‘When used as an input port or a secondary function pins, after setting segment/eommon output control (PBLCR) to “0” respective output latch (PSDR) should be set to “I”. During reset, the PSDR is initialized to “1”, and segment output control (P3LCR) is initialized by “O”. In using it as LCD segment! common output, it sets the bit to which P3LCR corresponds to “I”. 3 port output latch (P3DR) and P3 port terminal input (PSPRD) are located on their respective address, ‘When read the output latch data, the PSDR should be read and when read the terminal input data, the PSPRD register should be read. If a read instruction is executed for port P3, read data of bit 7 is sr output and LCD unstable. Cont inp Terminal inpute30R0) <<} ] ac ary Lc input ‘Output atch data (P3DR) ata output (30m) ———>[_@} +4 On outpatateh conto outpat Note: 1=6t00 ex ———d_ > ouren {co dat output 26 os 4 3 2 1 0 aon a6 ] #35] Poa ] p33 | Pa] Pa | Pa (ant conn | cont |covs| sees |seesostcua|stee2| arises e111 110 ow wie | Mts | wita | ucs fase uD sauce (int value: 60000000) oboe) 0: P3 inputoutput port oF function except LCD Segment or common output Rw 1: LCD segment outputcommon output Por.P3 control PBLCR | (et foreach bit individually) ze, [ese [35 [ ose [ ps [ese [rat | 30 | Resd only Note: With ports asigned as MUL6 to MULO,asigned pins canbe switched by the mult function register (MULSEL). The assigned functions areas follow: Muto: DVO muta: int ‘MULL: POT, POO, r3 uts: iNT Mul: PEGE PINE, POOH, rca MUL6: INT [MUL3: PPGE, PWM, PDOE, Tos Figure 2-5. Port3 86CM25-05, 2003-05-15TOSHIBA TMP86CM25/S25 2.2.4 Port P5 (P57 to P50) Port P5 is an 8-bit input/output port which is also used as a segment pins of LCD. ‘When used as input port, the respective output lateh (P5DR) should be set to “1”. ‘During reset, the PSDR is initialized to “1”. ‘When used as a segment pins of LCD, the respective bit of P5LCR should be set to “I”, When used as an ‘output port, the respective PSLCR bit should be set to “0”. 5 port output latch (P5DR) and P5 port terminal input (PSPRD) are located on their respective address, ‘When read the output latch data, the P5DR should be read and when read the terminal input data, the P5PRD register should be read. If the terminal input data which is configured as LCD segment output isread, unstable data is read. —at onsen) =| Data input (PSDR) Tos outputtaten stor ouren PSLCR: P5LCR input Psi Note: i=7t00 Leo data output 7 6 5 4 3 2 1 0 sor [P57 | ps6 | pss | ps4 ] p53 | P52 ] P51] P50) icsivaiues 10111110) (oonsty | seca | secas | secas | seas | secas | sear | secar | secao | (initial valu RW Psicr (Initial value: 0000.0000) (o2aH Por P5isegment output select 0: PSinputfoutput port PSLER | (et for eachitindvidualy) 1: LeD segment output fw pseno [P57] pss | pss] rsa | pss ] ps2 | psi | ps0 0008) Read only Figure 2-6. Port 86CM25-06 2003-05-15TOSHIBA TMP86CM25/S25 2.2.5 Port PG (P67 to P60) Port P6 is an 8-bit input/output port which can be configured as an input or an output in one-bit unit. Port P6 is also used as an analog input, Key on Wake up input, timer/counter input and external interrupt input, Input/output mode is specified by the P6 control register (P6CR), the P6 output latch (PDR), and AINDS (bit 4 in ADCCR1). During reset, P6CR and PGDR are initialized to “0” and AINDS is set to “1”, At the same time, the input data of pins P67 to P60 are fixed to “0". To use port P6 as an input port, external interrupt input, timer/eounter input or key on wake up input, set data of PGDR to“1" and P6CR to “0”. ‘To use it as an output port, set data of PECR to “1”, To use it as an analog. input, set data of PEDR to “0” and P6CR to “O”, and start the AD. Itis the penetration electric current, ‘measures by the analog voltage. ins not used for analog input ean be used as VO ports. During AD conversion, output instructions should not be executed to keep a precision. In addition, a variable signal should not be input to a port, adjacent to the analog input during AD conversion, ‘When the AD converter is in use (PéDR=0), bits mentioned above are read as “O” by executing input instructions. STOP|EN Key on Wake up we Analog input AINDS sain scr SCR input Data input (P6DR) Note 1: 1=7t00,) =7t0s Note2: STOP sb? in SYSCRI atsourouson) —a[> 1) os: towed: Samsorote inancera a Noted: STOPEN stato 7 9STORCR 76 5s 4 3 2 1 0 son ey pes pen PE PEI PD Pa] (Greer [Zi Ale ANS Atte Aki Ait aii Ano] Cnilvaue: 00000000) tar es op sos oss: NiD FeNt: ec wr) 8S to (cose Cri ve: 00006000 TANDS= NAD une) “ANDS =A wed) seen | Yor for port Pioneer| paoke | one o™ | woORETT | (pected oreocnd) ["STinput"o" Fed | Tnpstmede | ADinpot —[ Inputmode 1 Outputmee Ouputmode ‘Note 1: Do not set output mode to pin which s used for an analog input NNote2: When used as an INTO, ECNT and ECIN pins ofa secondary function, the respective bit ofPSCR shouldbe set ta "0" and the Pé should set to"! Note 3: When used as an STOP2 to STOPS pins f Key on Wake up. the respective bit of PCR should beset to “0. ote: When a read instruction for port PEs executed, the bit of Analog input mode becomes read data "0". Figure 2-7. Port6 and P6CR ‘Note: Although P6DR isa read/writer register, because itis also used as an input mode control function, read. modify-write instructions such as bit manipulate instructions cannot be used. Read-modify-write instruction writes the all data of 8-bit after data is read and modified. Because a bit setting Input mode read data of terminal, the output latch is changed by these instruction. 50 P6 port can not input data. 86CM25-47 2003-05-15TOSHIBA TMP86CM25/S25 2.2.6 PortP7 (P77 to P70) PortP7 isan 8-bit input/output port which is also used as an external interrupt input, a divider outputa segment pins of LCD. ‘When used as input port or a secondary function pins, the respective output latch (P7DR) should be set tol”, ‘During reset, the P7DR is initialized to “1”. ‘When used as a segment pins of LCD, the respective bit of PTLCR should be set to “I”, When used as an ‘output port, the respective PTLCR bit should be set to “0”. P7 port output latch (P7DR) and P7 port terminal input (P7PRD) are located on their respective address, ‘When read the output latch data, the P7DR should be read and when read the terminal input data, the PTPRD register should be read. If the terminal input data which is configured as LCD segment output isread, unstable data is read Contor input Terminal input(?7e80) <_<} _] Preri 28 P7LeRi input Output latch data (P7DR) ata output (708) ———»[o_ }- +f outpatTaieh contro! output i ——d_ > ouren 100 Leo data output ——__________] 7 6 5 4 3 2 4 pron [P77] 76 | P75] Pra | PU] PD] Ph] PTO (0074) |cows|come| cons |comt2| cow |comto| coms | come | initial value: 1111 1111) rw | seer | soo | sit | mus | murz | muti | Muto ence [TTT titi vate: 0000 00000 o0261) Por Prisegment outputselect 0: Prinput/Output part PTLCR [set foreach bit individually) 1: segmentoutput prea [77 [ p76 | #75 | 7 | p73 | pm | ri [ 70 | (000%) Read only Note: With ports asigned as MUL6 to MULO,asigned pins can be switched by the mult function register (MULSEL) The assigned functions areas follow: Muto: DVO sauta: nr ‘MULI: POE, PDO, 13 mus: iNT Mute: PEGE PHONE, POO, rca MUL6: INT IMUL3: PPGE, PHT; PDOB, 7¢6 Figure 2-8. Port7 86CM25-08 2003-05-15TOSHIBA ‘TMP86CM25/S25 23° Multi Function Register With function pins assigned as MUL to MULO, the portto be used can be switched by MULSEL. 2 6 5 4 3 2 1 06 WES Duce [urs Toca us [vce [MUTT [ MULT] ive 00 0000 wus nts untonpinstec ope suis |e panas, Dos Tes tuncionpinslec | 22 www rat waa |r, naa POO, Tea tuntonpinseten [OPE oa wart [pw p08 testurcionpinwwece [OH — 0: 20 wwuio | Bw tuncion nsete 0: an Figure2-, MultiFunction Register s6cMns.49 2003.05.15,TOSHIBA TMP86CM25/S25 2.4 Time Base Timer (T8T) ‘The time base timer generates time base for key scanning, dynamic displaying, ete. It also provides a time base timer interrupt (INTTBT). An INTTBY is generated on the first falling edge of source clock (the divider output of the timing generator) after the time base timer has been enabled. ‘The divider is not cleared by the program ; therefore, only the first interrupt may be generated ahead of the set interrupt period (Figure 2-10 (b)) ‘The interrupt frequency (TBTCK) must be selected with the time base timer disabled (the interrupt frequency must not be changed with the disable from the enable state). Both frequency selection and ‘enabling can be performed simultaneously. Mex fe2? or 28 > fea" or aa" > {2° or waa" >| fo or fant fea? or a 54 fen? or a >| fea" or we 5 for ora [Hs {+ nrrerinterrupt request 3 rT aren Taree Time bare Umer control register Source dock Falling edge detector [ IDLEOISLEEPO release request (0) Configuration sourceclock —_| l TeTen TT wwrret ll Interrupt period enable 727 (MPX: Multiplexer (©) Timebase timer interrupt Figure 2-10. Time Base Timer Example: Sets the time base timer frequency to fe2"* [Hz] and enables an INTTBT interrupt. LD —(TBTCR),00000010B |; TRICK — 010, LD —(TBTCR),000010108—; TBTEN<1 SET (BIRL).6 86CM25-50 2003-05-15TOSHIBA TMP86CM25/S25 7 6 5 4 3 2 1 0 ES, Gon] oe [ove ier Tere Chal alu: 00 or) aren | Time base timer 0: Disable BTEN | enable/disable 1: Enable NORWALI®, DIET mode Pode Dv7CK= 6 | OVICK= 1 | SLOW. SLEEP mont 00 ‘en a2" a Time basetimerinterrupt | 903 ta fa" fe mw rave | frequency select [Ha] oro fen oe 2 on fen" fa = 100 12” we - 101 fen fu - 110 fen" we = un fon? 2 = Note: fe: High-frequency clock [2], 1: Low-frequency lock [Ha], +: Don’tcare Figure 2-11. Time Base Timer Control Register 12.768 kH2) Table 2-1, Time Base Timer Interrupt Frequency (Example: fe= 16.0 MHz, fs Time bare timer interrupt frequency Ma] rote NORMALY/2, DLEI/2 mode SLOW, SLEEP, DICK mode 206, 137 1 7 ‘oo 76 a 4 10) 214 ie. * ont 576.56 Sin 5 100) i953 13 ioza 5 ‘01 3906 25, 2088 = 110) 78128 096. = si i250 ‘gaa = 86CM25-51 2003-05-15TOSHIBA TMP86CM25/S25 2.5. Watchdog Timer (WDT) ‘The watchdog timer is a fail-safe system to rapidly detect the CPU malfunctions such as endless looping caused by noise or the like, or deadlock and resume the CPU to the normal state. ‘The watchdog timer signal for detecting malfunction can be selected either a reset generate or a non- maskable interrupt request. However, selection is possible only once after reset, At first the reset generate is selected. ‘When the watchdog timer is not being used for malfunction detection, it can be used as a timer to generate an interrupt at fixed intervals. Note: Care must be given in system design so as to protect the Watchdog Timer from disturbing noise. Otherwise the Watchdog Timer may not fully exhibit its functionality. 2.5.1 Watchdog Timer Configuration ne Reset lene inal fromT.G fe? or 2% ofA Binary counters Geo ae Up fare eer le yp Sek Overiow wor outgut fa ora [Dg ife a} resetrequet con A Lari ynyon Internal reset @ An wolf), iting Writing wort disablecode | clear code worour controller 03a 35H ‘WOTCRT WOTCR2 ‘Watchdog timer control registers MPx: Multiplexer Figure 2-12. Watchdog Timer Configuration 86CM25-52 2003-05-15TOSHIBA TMP86CM25/S25 2.5.2 Watchdog Timer Control Figure 2-13 shows the watchdog timer control registers (WDTCR1, WDTCR2). The watchdog timer is automatically enabled after reset. (1) Malfunction detection methods using the watchdog timer ‘The CPU malfunction is detected as follows. © Setting the detection time, selecting output, and clearing the binary counter. (® Repeatedly clearing the binary counter within the setting detection time If the CPU malfunctions such as endless looping or deadlock oceur for any cause, the watchdog timer ‘output will become active at the rising of an overflow from the binary counters unless the binary counters are cleared. At this time, when WDTOUT=1 a reset is generated, to reset the internal hardware. When WDTOUT=0, a watchdog timer interrupt (INTWDT) is generated, ‘The watchdog timer temporarily stops counting in STOP mode including warm-up or IDLE mode, and automatically restarts (continues counting) when the STOP/IDLE mode is released. Note: The watchdog timer consists of an internal divider and a two-stage binary counter. When clear code 4Ey is written, only the binary counter is cleared, not the internal divider. Depending on the timing at which clear code 4Ey is written on the WDTCR2 register, the overflow time of the binary counter may be at minimum 3/4 of the time set in WOTCRI . Thus, write the clear code using a shorter cycle than 3/4 of the time set in WOTCRY . Example: Sets the watchdog timer detection time to 2"/fe(s) and resets the CPU malfunction. LD(WDTCR2), 4EH LD(WDTCR1), 000011018 LD(WDTCR®), 42H Clears the binary counters WDTT <10, WDTOUT <1 Clears the binary counters Within 9/4 of WOT (always clear immediately before and after detection time changing WDTT) LD(WDTCR2), AEH 5 Clears the binary counters ‘Within 3/4 of WOT detection time LD(WDTCR2), 4EH 5 Clears the binary counters 86CM25-53 2003-05-15TOSHIBA TMP86CM25/S25 ‘Watchdog Timer Register! WOTCR! co 2ong Sue S 4 3 2 to (oo3any (itil value: +611 1001) Watchdog timer 0: Disable tis necettary to write the dnable code to WOTCRA) WOTEN | cnableldeable 1: Enable NORWALIE mode TOW mode! DwreK=0 Dv7ce=7—|_ SLOW med Watchdog timer Pie 2s ie Write WOT | detection time(s] of 2e 2s ite only wo | 2 2H 2s ni | ame 2s Die Watchdog timer 0; Interrupt request WOTOUT | output selec 1: Reset generates ‘Note 1» WDTOUT cannotbe set to "T™ by program after clearing WOTOUT to [Note 2: fe: High-frequency cock [2], 16: Low-frequency clock [Hz], +: Don'tcare ‘ote 3: WOTCRT isa write-only register and must not be used with any of read modlfy-write instructions. [Note 4: The watchdog timer must be dsabled or the counter must be cleared immediately before entering to the STOP mode. When the counters cleared, the counter must be cleared again immediately after ‘easing the STOP mode. ‘Note 5: Toddsable the watchdog timer, always write “AEH” (clear code) to WOTCR? for clearing the binary Figure 2-13, Watchdog Timer Control Registers (2) Watchdog timer enable "The watchdog timer is enabled by setting WDTEN (bit 3 in WDTCRI) to “1”. WDTEN is initialized to “T" during reset, so the watchdog timer operates immediately after reset is released. (3) Watchdog timer disable ‘To disable the watchdog timer, write “4BH" (clear code) to WDTCR2 for clearing the binary counter before writing “0” to WDTEN, and then write “B1H" (disable code) to WDTCR2. The watchdog timer is not disabled if this procedure is reversed and the disable code is written to WDTCR2 before WDTEN is cleared to “0”. AAlso, immediately before these procedure, disable the interrupt master flag (IMF) by DI instruction, During disabling the watchdog timer, the binary counters are cleared to “0”, Example: Disables watchdog timer DI : IMF=X 2K FH overtiow INTWOT interrupt Internal reset Preset generates Writes ach to WOTCRE Figure 2-14. Watchdog Timer interruptReset 86CM25-55 2003-05-15TOSHIBA TMP86CM25/S25 2.5.5 Address Trap ‘The Watchdog ‘Timer Control Register 1, 2 shares its addresses with the control registers in case of address trap. ‘These control registers for address trap are shown on Figure 2-15, Watchdog Timer Control Register WOTERE go oonsaond 24 sa 3 ° Coosa ES Crit vale: 414 1001) 0: Noaddress trap Selection of address trap in |1: Address trap ATAS internal RAM (ter setting ATAS to 71", itis necessary to write the | write control code D2H to WOTCR2) only [Selection of operation at | interupt ATOUT | aadresetrap 1: Reset watchdog Timer Control Register2 poe sa worcr (ooase) () ritiat votes eee oo 2H: Address trapped area valid toset (TRAP control code) Jwatchdog timer control | 48H: Watchdog timer binary counter clear write worcr2 |code and Address trapped (wor clear code) ‘only area control code BIH: Watchdog timer disable (WOT disable code) others: _Invalia Figure 2-15. Watchdog Timer Control Registers (1) Selection of address trap in internal RAM (ATAS) Using WDTCR1, address trap or no address trap can be selected for the internal RAM area. ‘To execute an instruction in the internal RAM area, set “0” in WDTCRI. Setting in WDTCRI becomes valid after control code D2H is written in WDTCR2. Executing an instruction in the SFR/DBR area generates an address trap unconditionally regardless of the setting in WDTCRI. (2) Selection of operation at address trap (ATOUT) ‘As the operation at address trap either interrupt generation or reset generation ean be selected by WDTCRI. 86CM25-56 2003-05-15