Active-HDL Student Edition

Active-HDL PDF Export

SEQUENCE_DETECTOR workspace

Active-HDL Student Edition

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All Rights Reserved.
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 Contents
1 Table of Contents
2 Sequence_detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2.1 Example_60.vhd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2.2 Sim_Sequence_detector.awc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Active-HDL Student Edition

2 Sequence_detector

2.1 Example_60.vhd
-----------------------------------------------------------------------------
--
--
-- Title : SeqDet
-- Design : Sequence_detector
-- Author : Jose Miguel Magaña Gutierrez
-- Company : INSTITUTO TECNOLOGICO DE CIUDAD GUZMAN
--
-----------------------------------------------------------------------------
--
--
-- File : c:\My_Designs\SEQUENCE_DETECTOR\Sequence_detector\src\Exampl
e_60.vhd
-- Generated : Wed Oct 7 22:30:48 2020
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-----------------------------------------------------------------------------
--
--- Description
--
-----------------------------------------------------------------------------
--{{ Section below this comment is automatically maintained
-- and may be overwritten
--{entity {SeqDet} architecture {SeqDet}}

library IEEE;
use IEEE.std_logic_1164.all;
entity SeqDet is
port(
CLK : in STD_LOGIC;
CLR : in STD_LOGIC;
DIN : in STD_LOGIC;
DOUT : out STD_LOGIC
); end SeqDet; --}} End of
automatically maintained section
architecture SeqDet of SeqDet is type
state_type is (S0, S1, S2, S3, S4); signal
present_state, next_state:state_type; begin
sreg: process (CLK, CLR)
begin
if CLR = '1' then
present_state <= S0; elsif
(CLK'event and CLK = '1') then
present_state <= next_state;
end if;
end process sreg;
C1: process (present_state, DIN)
begin
case present_state is
when S0 =>

1
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Active-HDL Student Edition
if DIN = '1' then
next_state <= S1;
else next_state
<= S0; end if;
when S1 => if DIN =
'1' then
next_state <= S2;
else next_state
<= S0; end if;
when S2 => if DIN =
'0' then
next_state <= S3;
else next_state
<= S2; end if;
when S3 => if DIN =
'1' then
next_state <= S4;
else next_state
<= S0; end if;
when S4 => if DIN =
'0' then
next_state <= S0;
else next_state
<= S2; end if;
when others => null;
end case; end process
C1;

C2: process (present_state)

begin
if present_state = S4 then
DOUT <= '1';
else
DOUT <= '0';
end if; end process
C2; end SeqDet;

2
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Active-HDL Student Edition
2.2 Sim_Sequence_detector.awc