A Unique Project Report on

LISSAJOUS CURVE BASED

KEYPAD DRIVEN
SYSTEM ANALYZER
USING FPGA

Bedir Halcı 150716002

Medet Hasan Uğurlu 150715004
Orhan Öztürk 150716055
Purpose
To design a video graphic Lissajous Curve Monitoring Machine using Verilog hardware
description and implementing it using Xilinx Zybo Zynq - 7000 FPGA kit.

Design

Figure 1: Monitor - FPGA - Keypad - Circuitry

System has four main parts which unify to form LICK (Lissajous Curve Based Keypad
Driven System Analyzer) as whole, as it can be seen in Figure 1. Relevant parts are Monitor,
FPGA, Keypad & Circuitry.

a) Monitor
Monitor is the visual interface between LICK and user where user can see relevant outputs.
The outputs that are shown in this part are coming from FPGA as outputs of user-selected and
system-driven inputs.

b) FPGA
FPGA is the main brain of the LICK where inputs are processed and outputs are generated,
accordingly. It also is a visual interface too as Monitor is in a class that shows acknowledgement
LEDs to user. Relevant inter-relations and processes can be found under ‘Methodology’ title.
 c) Keypad
Keypad is the tactual interface between LICK and user where user can command what
needs to be done. Keypad works with inputs and outputs because of its own design; this keypad
has four columns and four rows which makes it a four-input four-output apparatus. Also, as a result
of this simplified design; its usage is a bit complicated: One needs to feed every column to see a
response in rows and, after that, columns need to be fed one-by-one to catch the appropriate unique
output element of this matrix-like apparatus. So, it is done, as it should be.

d) Circuitry
Circuitry is the system which drives LICK to show relevant data via two analog signals.
Relevant circuitry needs to create at least one alternating output to show a Lissajous Curve of 1D,
and, at least two alternating outputs to show a Lissajous Curve of 2D. If analog outputs are non-
alternating signals, then relevant output which will be shown is a Lissajous Curve of 0D which is
just a point.

Methodology

Figure 2: Overall Schematic

LICK has 9-bit input and 26-bit output, as it can be seen in Figure 2. Inputs can be classified
as; clk-clock, {{s0,vn0},{s1,vn1}}-analog inputs & r-rows of keypad. Also, outputs can be
classified as; {R,G,B,H,V}-vga, ack-acknowledgement LEDs & c-columns of keypad. Relevant
figure also shows that two main modules are being used: ‘gelabi’ & ‘meow’.
 a) gelabi

Figure 3: gelabi module

To use with XADC logic, gelabi has 5-bit input and 24-bit output, as it can be seen in
Figure 3. Inputs can be classified as; clk-clock & {{s0,vn0},{s1,vn1}}-analog inputs. Also,
outputs can be classified as; o0-output 1 & o1-output 2. Relevant figure also shows that it uses
XADC to convert analog inputs to digital outputs. It is done by simultaneous ADC selection to
have two digital outputs which will be processed to have Lissajous Curves.

b) meow

Figure 4: meow module

To digitally process and have Lissajous Curves, meow has 29-bit input and 26-bit output,
as it can be seen in Figure 4. Inputs can be classified as; clk-clock, {f,g}-digital inputs & r-rows
of keypad. Also, outputs can be classified as; {R,G,B,H,V}-vga, ack-acknowledgement LEDs &
c-columns of keypad. Relevant figure also shows that it uses a RAM in between to store and get
processed data.
The sub-modules ‘ethics’, ‘nietzsche’, ‘selector’, ‘tip’, ‘ww3’, ‘zeus’, ‘monk’, ‘fog’,
‘regaib’ & ‘runner’ are inter-units that set clock or communicate with one-another to change
behavior or act as state-driver feedback regulator to prepare needed circumstances and act as
a proper user interface.
Further knowledge can be acquired from the Verilog Description & Constraints in the
Appendix.

Results & Discussion

Figure 5: Implemented Device Map

After Implementation, device using 3/4 sectors of itself, as it can be seen in Figure 5, to
comprehend such task.

Figure 6:LUTs, FFs, BRAMs & DSPs Usage

 And, it uses 442 LUTs, 183 FFs, 30 BRAMs & 2 DSPs, as it can be seen in Figure 6.

Figure 7:Two-Potentiometer-Based Circuitry Lissajous Curve

First official trial usage of LICK has done with Two-Potentiometer-Based circuitry where
resistor of potentiometer increases, voltage signal coming from relevant signal pin decreases to
zero.
It is obvious that such linear alternation causes linear diffraction on the intersection point
of sampled analog signals where this linear diffraction causes a base directive movement of point,
and, as a result of RAM-based storing, such 1D Lissajous Curve can be generated as is told before.
Figure 6 is result of two potentiometers as the name ‘Two-Potentiometer-Based’ suggests.
Appendix-1 (Verilog Description)
module mazi(clk,vn0,vn1,s0,s1,r,c,ack,R,G,B,V,H);
input clk,vn0,vn1,s0,s1;
input [3:0] r;
output [3:0] c;
output [4:0] R;
output [5:0] G;
output [4:0] B;
output H,V;
output [3:0] ack;
wire [11:0] f,g;
gelabi gitabi(clk,vn0,vn1,s0,s1,f,g);
meow cat(clk,f,g,r,c,ack,R,G,B,V,H);
endmodule

module gelabi(clk,vn0,vn1,s0,s1,o0,o1);
input clk,vn0,vn1,s0,s1;
output reg [11:0] o0,o1;
wire [15:0] out;
reg [6:0] got;
initial
begin
got=7'h1E;
o0=12'd0;
o1=12'd0;
end
always@(posedge clk)
begin
if(got==7'h1E)
begin
got<=7'h16;
o0=out[12:1];
end
if(got==7'h16)
begin
got<=7'h1E;
o1=out[15:4];
end
end
xadc_wiz_0 yin(
.di_in(16'b0), // input wire [15 : 0] di_in
.daddr_in(got), // input wire [6 : 0] daddr_in
.den_in(1'b1), // input wire den_in
.dwe_in(0), // input wire dwe_in
.drdy_out(0), // output wire drdy_out
.do_out(out), // output wire [15 : 0] do_out
.dclk_in(clk), // input wire dclk_in
.reset_in(0), // input wire reset_in
.vp_in(0), // input wire vp_in
.vn_in(0), // input wire vn_in
.vauxp6(s1), // input wire vauxp6
.vauxn6(vn1), // input wire vauxn6
.vauxp14(s0), // input wire vauxp14
.vauxn14(vn0), // input wire vauxn14
.channel_out(0), // output wire [4 : 0] channel_out
.eoc_out(1'b1), // output wire eoc_out
 .alarm_out(0), // output wire alarm_out
.eos_out(0), // output wire eos_out
.busy_out(0) // output wire busy_out
);
endmodule

module meow(clk,f,g,r,c,ack,R,G,B,V,H);
input [11:0] f,g;
input clk;
input [3:0] r;
output [3:0] c;
output [4:0] R;
output [5:0] G;
output [4:0] B;
output H,V;
output [3:0] ack;
wire [15:0] a1,a2,a,ares,add,d,di,o,fi,gi;
wire tc,we,e,s;
runner usain(clk,r,c,ack,d,tc);
fog frog(ack[1],d,di);
ethics transcendental(ack[3:2],f,g,fi,gi);
nietzsche kant(clk,fi,gi,a1);
monk jss(~we,ack[1],e);
blk_mem_gen_0 meme(clk,e,add,di,o);
regaib RGB(clk,o,R,G,B,H,V,a2,we);
selector ego(clk,ack[0],s);
tip ik(s,a1,a2,a);
ww3 putin(ack[1],tc,ares);
zeus odyssey(ack[1],a,ares,add);
endmodule

module runner(clk,r,c,ack,d,tc);
input clk;
input [3:0] r;
output [3:0] c,ack;
output [15:0] d;
output tc;
wire [3:0] n;
chinese kisschun(clk,r,c,ack,n,tc);
colour rgb(n,d);
endmodule

module chinese(clk,r,c,ack,n,t);
input clk;
input [3:0] r;
output [3:0] c,n,ack;
output t;
wire [3:0] n;
slow turtle(clk,t);
mektep karakoy(t,r,c,ack[2],n,ack[1],ack[0]);
assign ack[3]=~ack[2];
endmodule

module slow(i,o);
input i;
output reg o;
parameter s=9'd0;
parameter n=9'd500;
reg [8:0] w;
initial
begin
w=s;
o=1'b1;
end
always@(posedge i)
if(w<n-1)
w<=w+1'b1;
else
begin
w<=s;
o<=~o;
end
endmodule

module mektep(t,r,c,ad,s,rst,hld);
input t;
input [3:0] r;
output [3:0] c;
output [3:0] s;
output ad,rst,hld;
wire [4:0] w;
wire z,f,g;
nazi schrodinger(rst,hld,f,g,t,r,c,w,z);
wwe undertaker(z,w,ad,s,rst,hld,f,g);
endmodule

module nazi(rst,hld,f,g,t,r,c,o,z);
input rst,hld,f,g,t;
input [3:0] r;
output [3:0] c;
output [4:0] o;
output z;
wire [2:0] s;
detect batman(rst,hld,f,g,t,r,s,o,z);
feed pokemon(s,c);
endmodule

module detect(rst,hld,f,g,t,r,s,o,z);
input rst,hld,f,g,t;
input [3:0] r;
output reg [2:0] s;
output reg [4:0] o;
output reg z;
wire p=r[3]|r[2]|r[1]|r[0];
parameter A=3'b000;
parameter B=3'b001;
parameter C=3'b010;
parameter D=3'b011;
parameter E=3'b100;
initial
begin
s=3'b000;
o=4'd11;
z=1'b0;
end
always @ (posedge t)
begin
z<=~z;
if(((rst==1'b0)&(hld==1'b0)&(g==1'b0))|(f==1'b1))
case(s)
A:
begin
if(p==1)
s<=B;
else
s<=A;
end
B:
begin
if(p==1)
begin
s<=A;
if(r[3]==1)
o<=4'd14;
if(r[2]==1)
o<=4'd7;
if(r[1]==1)
o<=4'd4;
if(r[0]==1)
o<=4'd1;
end
else
s<=C;
end
C:
begin
if(p==1)
begin
s<=A;
if(r[3]==1)
o<=4'd0;
if(r[2]==1)
o<=4'd8;
if(r[1]==1)
o<=4'd5;
if(r[0]==1)
o<=4'd2;
end
else
s<=D;
end
D:
begin
if(p==1)
begin
s<=A;
if(r[3]==1)
o<=4'd15;
if(r[2]==1)
o<=4'd9;
if(r[1]==1)
o<=4'd6;
if(r[0]==1)
o<=4'd3;
end
else
s<=E;
end
E:
begin
if(p==1)
begin
s<=A;
if(r[3]==1)
o<=4'd13;
if(r[2]==1)
o<=4'd12;
if(r[1]==1)
o<=4'd11;
if(r[0]==1)
o<=4'd10;
end
else
s<=A;
end
endcase
else
begin
if(rst==1'b1)
o<=4'd11;
if(g==1'b1)
o<=4'd12;
if(hld==1'b1)
o<=5'd16;
end
end
endmodule

module feed(s,f);
input [2:0] s;
output reg [3:0] f;
initial
f=4'b1111;
always@(*)
case(s)
3'b000: f=4'b1111;
3'b001: f=4'b1000;
3'b010: f=4'b0100;
3'b011: f=4'b0010;
3'b100: f=4'b0001;
endcase
endmodule

module wwe(t,i,ad,s,rst,hld,f,g);
input t;
input [4:0] i;
output reg ad,rst,hld,f,g;
output reg [3:0] s;
reg [18:0] count;
initial
begin
count<=19'b0;
ad=1'b0;
rst=1'b0;
hld=1'b0;
s=4'b0;
f=1'b0;
g=1'b0;
end
always@(posedge t)
begin
if(rst==1'b1)
begin
count<=count+1'b1;
if(count[18]==1)
begin
rst<=1'b0;
count<=1'b0;
end
end
else
if((hld==1'b1)&(count>0))
begin
count<=count-1;
end
else
begin
if(f==1'b0)
begin
if(i==4'd10)
ad<=1'b0;
if(i==4'd12)
g<=1'b0;
if(i==4'd13)
ad<=1'b1;
if(i==4'd14)
rst<=1'b1;
if(i==4'd15)
begin
hld<=1'b1;
count<=19'd20;
end
if(i<4'd10)
s<=i;
if(i==5'd16)
f<=1'b1;
end
if((f==1'b1)&(i==4'd15))
begin
hld<=1'b0;
f<=1'b0;
g<=1'b1;
end
end
end
endmodule

module colour(n,c);
input [3:0] n;
output [15:0] c;
assign c=n*n*n*n;
endmodule

module fog(s,i,o);
input s;
input [15:0] i;
output [15:0] o;
assign o=i&{16{~s}};
endmodule

module ethics(s,i1,i2,o1,o2);
input [1:0] s;
input [15:0] i1,i2;
output [15:0] o1,o2;
assign o1=(i1&{16{s[1]}})|(i2&{16{s[0]}});
assign o2=(i2&{16{s[1]}})|(i1&{16{s[0]}});
endmodule
module nietzsche(clk,f,g,o);
input clk;
input [11:0] f,g;
output [15:0] o;
parameter w=9'd256;
wire [7:0] x,y;
map mx(clk,g,x);
map my(clk,f,y);
wire [15:0] as=y*w;
assign o=as+x;
endmodule

module map(clk,i,o);
input clk;
input [11:0] i;
output reg [7:0] o;
reg [19:0] k;
parameter w=8'd255;
parameter u=12'd4095;
initial
k=20'b0;
always@(posedge clk)
begin
k<=i*w;
o<=k/u;
end
endmodule
module monk(i,is,o);
input i,is;
output o;
assign o=(i&(~is))|is;
endmodule

module regaib(clk,d,R,G,B,H,V,a,t);
input clk;
input [15:0] d;
output [4:0] R,B;
output [5:0] G;
output H,V;
output [15:0] a;
output t;
birinci cehalet(clk,t);
beraat kandil(t,d,R,G,B,H,V,a);
endmodule

module birinci(clk,t);
input clk;
output reg t;
parameter s=2'd0;
parameter n=2'd2;
reg [1:0] w;
initial
begin
w=s;
t=1'b1;
end
always@(posedge clk)
if(w<n-1)
w<=w+1'b1;
else
begin
w<=s;
t<=~t;
end
endmodule

module beraat(t,d,R,G,B,H,V,a);
input t;
input [15:0] d;
output reg [4:0] R;
output reg [5:0] G;
output reg [4:0] B;
output reg H,V;
output reg [15:0] a;
parameter sx=9'd256;
parameter sy=9'd256;
localparam HDISP=640;
localparam HFP=16;
localparam HPW=96;
localparam HLIM=800;
localparam VDISP=480;
localparam VFP=10;
localparam VPW=2;
localparam VLIM=525;
parameter [10:0] rxo=HDISP/2;
parameter [10:0] ryo=VDISP/2;
parameter [10:0] rx1=rxo-sx/2;
parameter [10:0] rx2=rxo+sx/2-1;
parameter [10:0] ry1=ryo-sy/2;
parameter [10:0] ry2=ryo+sy/2-1;
reg [10:0] hcount=0;
reg [10:0] vcount=0;
reg enable=0;
initial
begin
R=5'b00000;
G=6'b000000;
B=5'b00000;
H=1'b0;
V=1'b0;
a=16'b0000000000000000;
end
always@(posedge t)
begin
if (hcount < HLIM-1)
hcount <= hcount+1'b1;
else
begin
hcount<=0;
if (vcount < VLIM-1)
vcount <= vcount+1'b1;
else
vcount <= 0;
end
if ((vcount < ry1)|(ry2 < vcount))
begin
a<=-1;
enable <= 0;
end
else
begin
if ((rx1-1 < hcount)&(hcount < rx2+1))
begin
enable <= 1;
a<=a+1;
end
else
enable <= 0;
end
if (enable==1)
begin
R <= d[4:0];
G <= d[10:5];
B <= d[15:11];
end
else
begin
R <= 5'b00000;
G <= 6'b000000;
B <= 5'b00000;
end
if (hcount > (HDISP+HFP)-1 && hcount <=(HDISP+HFP+HPW)-1)
H <= 0;
else
H <= 1;
if (vcount >= (VDISP+VFP)-1 && vcount < (VDISP+VFP+VPW)-1)
V <= 0;
else
V <= 1;
end
endmodule

module selector(clk,hld,o);
input clk,hld;
output o;
assign o=clk|hld;
endmodule

module tip(clk,a1,a2,a);
input clk;
input [15:0] a1,a2;
output [15:0] a;
wire t;
romania dig(clk,t);
mux ptt(a1,a2,t,a);
endmodule
module romania(clk,t);
input clk;
output reg t;
initial
t=1'b1;
always@(posedge clk)
t<=~t;
endmodule

module mux(i,j,c,a);
input [15:0] i,j;
input c;
output reg [15:0] a;
reg r;
initial
r=1'b1;
always@(posedge c)
begin
r<=~r;
a<=(j&{16{~r}})|(i&{16{r}});
end
endmodule

module ww3(f,t,n);
input f,t;
output reg [15:0] n;
initial
n=-1;
always@(posedge t)
if(f==0)
n<=0;
else
n<=n+1;
endmodule

module zeus(s,i,r,a);
input s;
input [15:0] i,r;
output [15:0] a;
assign a=(i&{16{~s}})|(r&{16{s}});
endmodule
Appendix-2 (Constraints)
## This file is a general .xdc for the ZYBO Rev B board
## To use it in a project:
## - uncomment the lines corresponding to used pins
## - rename the used signals according to the project

##Clock signal
set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { clk }];
#IO_L11P_T1_SRCC_35 Sch=sysclk
create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { clk }];

##Switches
#set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports { f[5] }];
#IO_L19N_T3_VREF_35 Sch=SW0
#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { f[6] }];
#IO_L24P_T3_34 Sch=SW1
#set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports { f[7]
}]; #IO_L4N_T0_34 Sch=SW2
#set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { f[8] }];
#IO_L9P_T1_DQS_34 Sch=SW3

##Buttons
#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { btn[0]
}]; #IO_L20N_T3_34 Sch=BTN0
#set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS33 } [get_ports { btn[1]
}]; #IO_L24N_T3_34 Sch=BTN1
#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { btn[2]
}]; #IO_L18P_T2_34 Sch=BTN2
#set_property -dict { PACKAGE_PIN Y16 IOSTANDARD LVCMOS33 } [get_ports { btn[3]
}]; #IO_L7P_T1_34 Sch=BTN3

##LEDs
set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { ack[0]
}]; #IO_L23P_T3_35 Sch=LED0
set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 } [get_ports { ack[1]
}]; #IO_L23N_T3_35 Sch=LED1
set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { ack[2]
}]; #IO_0_35=Sch=LED2
set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { ack[3]
}]; #IO_L3N_T0_DQS_AD1N_35 Sch=LED3

##I2S Audio Codec

#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports
ac_bclk]; #IO_L12N_T1_MRCC_35 Sch=AC_BCLK
#set_property -dict { PACKAGE_PIN T19 IOSTANDARD LVCMOS33 } [get_ports
ac_mclk]; #IO_25_34 Sch=AC_MCLK
#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports
ac_muten]; #IO_L23N_T3_34 Sch=AC_MUTEN
#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports
ac_pbdat]; #IO_L8P_T1_AD10P_35 Sch=AC_PBDAT
#set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVCMOS33 } [get_ports
ac_pblrc]; #IO_L11N_T1_SRCC_35 Sch=AC_PBLRC
#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports
ac_recdat]; #IO_L12P_T1_MRCC_35 Sch=AC_RECDAT
#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports
ac_reclrc]; #IO_L8N_T1_AD10N_35 Sch=AC_RECLRC
##Audio Codec/external EEPROM IIC bus
#set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVCMOS33 } [get_ports ac_scl];
#IO_L13P_T2_MRCC_34 Sch=AC_SCL
#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports ac_sda];
#IO_L23P_T3_34 Sch=AC_SDA

##Additional Ethernet signals

#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports
eth_int_b]; #IO_L6P_T0_35 Sch=ETH_INT_B
#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports
eth_rst_b]; #IO_L3P_T0_DQS_AD1P_35 Sch=ETH_RST_B

##HDMI Signals
#set_property -dict { PACKAGE_PIN H17 IOSTANDARD TMDS_33 } [get_ports
hdmi_clk_n]; #IO_L13N_T2_MRCC_35 Sch=HDMI_CLK_N
#set_property -dict { PACKAGE_PIN H16 IOSTANDARD TMDS_33 } [get_ports
hdmi_clk_p]; #IO_L13P_T2_MRCC_35 Sch=HDMI_CLK_P
#set_property -dict { PACKAGE_PIN D20 IOSTANDARD TMDS_33 } [get_ports {
hdmi_d_n[0] }]; #IO_L4N_T0_35 Sch=HDMI_D0_N
#set_property -dict { PACKAGE_PIN D19 IOSTANDARD TMDS_33 } [get_ports {
hdmi_d_p[0] }]; #IO_L4P_T0_35 Sch=HDMI_D0_P
#set_property -dict { PACKAGE_PIN B20 IOSTANDARD TMDS_33 } [get_ports {
hdmi_d_n[1] }]; #IO_L1N_T0_AD0N_35 Sch=HDMI_D1_N
#set_property -dict { PACKAGE_PIN C20 IOSTANDARD TMDS_33 } [get_ports {
hdmi_d_p[1] }]; #IO_L1P_T0_AD0P_35 Sch=HDMI_D1_P
#set_property -dict { PACKAGE_PIN A20 IOSTANDARD TMDS_33 } [get_ports {
hdmi_d_n[2] }]; #IO_L2N_T0_AD8N_35 Sch=HDMI_D2_N
#set_property -dict { PACKAGE_PIN B19 IOSTANDARD TMDS_33 } [get_ports {
hdmi_d_p[2] }]; #IO_L2P_T0_AD8P_35 Sch=HDMI_D2_P
#set_property -dict { PACKAGE_PIN E19 IOSTANDARD LVCMOS33 } [get_ports
hdmi_cec]; #IO_L5N_T0_AD9N_35 Sch=HDMI_CEC
#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports
hdmi_hpd]; #IO_L5P_T0_AD9P_35 Sch=HDMI_HPD
#set_property -dict { PACKAGE_PIN F17 IOSTANDARD LVCMOS33 } [get_ports
hdmi_out_en]; #IO_L6N_T0_VREF_35 Sch=HDMI_OUT_EN
#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports
hdmi_scl]; #IO_L16P_T2_35 Sch=HDMI_SCL
#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports
hdmi_sda]; #IO_L16N_T2_35 Sch=HDMI_SDA

##Pmod Header JA (XADC)

set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { s0 }];
#IO_L21P_T3_DQS_AD14P_35 Sch=JA1_R_p
#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { ja_p[1]
}]; #IO_L22P_T3_AD7P_35 Sch=JA2_R_P
#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { ja_p[2]
}]; #IO_L24P_T3_AD15P_35 Sch=JA3_R_P
set_property -dict { PACKAGE_PIN K14 IOSTANDARD LVCMOS33 } [get_ports { s1 }];
#IO_L20P_T3_AD6P_35 Sch=JA4_R_P
set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { vn0 }];
#IO_L21N_T3_DQS_AD14N_35 Sch=JA1_R_N
#set_property -dict { PACKAGE_PIN L15 IOSTANDARD LVCMOS33 } [get_ports { ja_n[1]
}]; #IO_L22N_T3_AD7N_35 Sch=JA2_R_N
#set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS33 } [get_ports { ja_n[2]
}]; #IO_L24N_T3_AD15N_35 Sch=JA3_R_N
set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { vn1 }];
#IO_L20N_T3_AD6N_35 Sch=JA4_R_N

##Pmod Header JB
set_property -dict { PACKAGE_PIN T20 IOSTANDARD LVCMOS33 } [get_ports { r[0] }];
#IO_L15P_T2_DQS_34 Sch=JB1_p
set_property -dict { PACKAGE_PIN U20 IOSTANDARD LVCMOS33 } [get_ports { c[0] }];
#IO_L15N_T2_DQS_34 Sch=JB1_N
set_property -dict { PACKAGE_PIN V20 IOSTANDARD LVCMOS33 } [get_ports { r[1] }];
#IO_L16P_T2_34 Sch=JB2_P
set_property -dict { PACKAGE_PIN W20 IOSTANDARD LVCMOS33 } [get_ports { c[1] }];
#IO_L16N_T2_34 Sch=JB2_N
set_property -dict { PACKAGE_PIN Y18 IOSTANDARD LVCMOS33 } [get_ports { r[2] }];
#IO_L17P_T2_34 Sch=JB3_P
set_property -dict { PACKAGE_PIN Y19 IOSTANDARD LVCMOS33 } [get_ports { c[2] }];
#IO_L17N_T2_34 Sch=JB3_N
set_property -dict { PACKAGE_PIN W18 IOSTANDARD LVCMOS33 } [get_ports { r[3] }];
#IO_L22P_T3_34 Sch=JB4_P
set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports { c[3] }];
#IO_L22N_T3_34 Sch=JB4_N

##Pmod Header JC
#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { f[0] }];
#IO_L10P_T1_34 Sch=JC1_P
#set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports { f[1]
}]; #IO_L10N_T1_34 Sch=JC1_N
#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { f[2] }];
#IO_L1P_T0_34 Sch=JC2_P
#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { f[3] }];
#IO_L1N_T0_34 Sch=JC2_N
#set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS33 } [get_ports { f[4]
}]; #IO_L8P_T1_34 Sch=JC3_P
#set_property -dict { PACKAGE_PIN Y14 IOSTANDARD LVCMOS33 } [get_ports { f[5] }];
#IO_L8N_T1_34 Sch=JC3_N
#set_property -dict { PACKAGE_PIN T12 IOSTANDARD LVCMOS33 } [get_ports { f[6] }];
#IO_L2P_T0_34 Sch=JC4_P
#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { f[7] }];
#IO_L2N_T0_34 Sch=JC4_N
##Pmod Header JD
#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { g[0] }];
#IO_L5P_T0_34 Sch=JD1_P
#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { g[1] }];
#IO_L5N_T0_34 Sch=JD1_N
#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { g[2] }];
#IO_L6P_T0_34 Sch=JD2_P
#set_property -dict { PACKAGE_PIN R14 IOSTANDARD LVCMOS33 } [get_ports { g[3]
}]; #IO_L6N_T0_VREF_34 Sch=JD2_N
#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { g[4]
}]; #IO_L11P_T1_SRCC_34 Sch=JD3_P
#set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports { g[5]
}]; #IO_L11N_T1_SRCC_34 Sch=JD3_N
#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { g[6]
}]; #IO_L21P_T3_DQS_34 Sch=JD4_P
#set_property -dict { PACKAGE_PIN V18 IOSTANDARD LVCMOS33 } [get_ports { g[7]
}]; #IO_L21N_T3_DQS_34 Sch=JD4_N

##Pmod Header JE
#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { f[8] }];
#IO_L4P_T0_34 Sch=JE1
#set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports { f[9]
}]; #IO_L18N_T2_34 Sch=JE2
#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { f[10]
}]; #IO_25_35 Sch=JE3
#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { f[11]
}]; #IO_L19P_T3_35 Sch=JE4
#set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { g[8]
}]; #IO_L3N_T0_DQS_34 Sch=JE7
#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { g[9]
}]; #IO_L9N_T1_DQS_34 Sch=JE8
#set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports { g[10]
}]; #IO_L20P_T3_34 Sch=JE9
#set_property -dict { PACKAGE_PIN Y17 IOSTANDARD LVCMOS33 } [get_ports { g[11]
}]; #IO_L7N_T1_34 Sch=JE10

##USB-OTG overcurrent detect pin

#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports otg_oc];
#IO_L3P_T0_DQS_PUDC_B_34 Sch=OTG_OC

##VGA Connector
set_property -dict { PACKAGE_PIN M19 IOSTANDARD LVCMOS33 } [get_ports { R[0] }];
#IO_L7P_T1_AD2P_35 Sch=VGA_R1
set_property -dict { PACKAGE_PIN L20 IOSTANDARD LVCMOS33 } [get_ports { R[1] }];
#IO_L9N_T1_DQS_AD3N_35 Sch=VGA_R2
set_property -dict { PACKAGE_PIN J20 IOSTANDARD LVCMOS33 } [get_ports { R[2] }];
#IO_L17P_T2_AD5P_35 Sch=VGA_R3
set_property -dict { PACKAGE_PIN G20 IOSTANDARD LVCMOS33 } [get_ports { R[3] }];
#IO_L18N_T2_AD13N_35 Sch=VGA_R4
set_property -dict { PACKAGE_PIN F19 IOSTANDARD LVCMOS33 } [get_ports { R[4] }];
#IO_L15P_T2_DQS_AD12P_35 Sch=VGA_R5
set_property -dict { PACKAGE_PIN H18 IOSTANDARD LVCMOS33 } [get_ports { G[0] }];
#IO_L14N_T2_AD4N_SRCC_35 Sch=VGA_G0
set_property -dict { PACKAGE_PIN N20 IOSTANDARD LVCMOS33 } [get_ports { G[1] }];
#IO_L14P_T2_SRCC_34 Sch=VGA_G1
set_property -dict { PACKAGE_PIN L19 IOSTANDARD LVCMOS33 } [get_ports { G[2] }];
#IO_L9P_T1_DQS_AD3P_35 Sch=VGA_G2
set_property -dict { PACKAGE_PIN J19 IOSTANDARD LVCMOS33 } [get_ports { G[3] }];
#IO_L10N_T1_AD11N_35 Sch=VGA_G3
set_property -dict { PACKAGE_PIN H20 IOSTANDARD LVCMOS33 } [get_ports { G[4] }];
#IO_L17N_T2_AD5N_35 Sch=VGA_G4
set_property -dict { PACKAGE_PIN F20 IOSTANDARD LVCMOS33 } [get_ports { G[5] }];
#IO_L15N_T2_DQS_AD12N_35 Sch=VGA=G5
set_property -dict { PACKAGE_PIN P20 IOSTANDARD LVCMOS33 } [get_ports { B[0] }];
#IO_L14N_T2_SRCC_34 Sch=VGA_B1
set_property -dict { PACKAGE_PIN M20 IOSTANDARD LVCMOS33 } [get_ports { B[1] }];
#IO_L7N_T1_AD2N_35 Sch=VGA_B2
set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS33 } [get_ports { B[2] }];
#IO_L10P_T1_AD11P_35 Sch=VGA_B3
set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { B[3] }];
#IO_L14P_T2_AD4P_SRCC_35 Sch=VGA_B4
set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS33 } [get_ports { B[4] }];
#IO_L18P_T2_AD13P_35 Sch=VGA_B5
set_property -dict { PACKAGE_PIN P19 IOSTANDARD LVCMOS33 } [get_ports H];
#IO_L13N_T2_MRCC_34 Sch=VGA_HS
set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports V];
#IO_0_34 Sch=VGA_VS