R.M.K.

ENGINEERING COLLEGE
RSM Nagar, Kavaraipettai – 601 206

6th Semester – B.E. / B.Tech.

Electronics and Communication Engineering

UNIT II TEST Max: 50 marks

EC8095- VLSI DESIGN 15 th April 2020

Part-A (10 x 2 = 20 Marks)

1. Calculate logical effort and parasitic delay

2. What is Symmetric2 NOR Concept?

3. Why it is essential to go for footed logic?

4. Calculate the average logical effort and average parasitic delay of NAND 2 Pseudo nmos

5. Draw generic CVSL family

6. Calculate the average logical effort for HI SKEW NAND 2

7. What is the purpose of keepers?

8. Justify why Single phase Dynamic logic structures cannot be cascaded?

9. What is Domino logic?

10. What is monotonicity problem and how to overcome it?

Part – B ( 2 x 15=30Marks)

1. Explain Ratioed circuit in detail

2. What is the advantage of Dynamic circuit family and explain in brief