Types of Shift Register Data I/Os

Module 56

LCST – Logic Circuits and Switching

th
Theory
Source: Digital Fundamentals by Floyd, T. 11 Edition

Module 56 – Types of Shift Register Data I/Os 1

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Introduction

 In this module, four types of shift registers based on data input

and output (inputs/outputs) are discussed: serial in/serial out,
serial in/parallel out, parallel in/serial out, and parallel
in/parallel out.

Module 56 – Types of Shift Register Data I/Os 2

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Learning Objectives
 After completing this module, the learners
should be able to:

1. Describe the operation of four types of shift registers

2. Explain how data bits are entered into a shift register

3. Describe how data bits are shifted through a register

4. Explain how data bits are taken out of a shift register

5. Develop and analyze timing diagrams for shift registers

Module 56 – Types of Shift Register Data I/Os 3

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Serial In/Serial Out Shift Registers

 The serial in/serial out shift register accepts data serially—that

is, one bit at a time on a single line.

 It produces the stored information on its output also in serial

form.

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Serial In/Serial Out Shift Registers cont’d

Module 56 – Types of Shift Register Data I/Os 5

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Serial In/Serial Out Shift Registers cont’d

 EXAMPLE 7–11

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Serial In/Serial Out Shift Registers cont’d

 EXAMPLE 8–1
 Show the states of the 5-bit register in Figure 8–4(a) for the
specified data input and clock waveforms. Assume that the
register is initially cleared (all 0s).

Module 56 – Types of Shift Register Data I/Os 7

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Serial In/Serial Out Shift Registers cont’d

Module 56 – Types of Shift Register Data I/Os 8

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Serial In/Serial Out Shift Registers cont’d

 A traditional logic block symbol

Module 56 – Types of Shift Register Data I/Os 9

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Serial In/Parallel Out Shift Registers

 Data bits are entered serially (least-significant bit first) into a

serial in/parallel out shift register in the same manner as in
serial in/serial out registers.

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Serial In/Parallel Out Shift Registers cont’d

 A traditional logic block symbol

The register contains 0110

after four clock pulses.

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IMPLEMENTATION:
8-BIT SERIAL IN/PARALLEL OUT SHIFT REGISTER cont’d

 A traditional logic block symbol

Module 56 – Types of Shift Register Data I/Os 12

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Serial In/Parallel Out Shift Registers

 Fixed-Function Device

Module 56 – Types of Shift Register Data I/Os 13

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Serial In/Parallel Out Shift Registers cont’d

 A traditional logic block symbol

Module 56 – Types of Shift Register Data I/Os 14

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Serial In/Parallel Out Shift Registers cont’d

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Serial In/Parallel Out Shift Registers cont’d

 Programmable Logic Device (PLD)

 The 8-bit serial in/parallel out shift register can be described
using VHDL and implemented as hardware in a PLD.

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Serial In/Parallel Out Shift Registers cont’d

 Programmable Logic Device (PLD)

 The 8-bit serial in/parallel out shift register can be described
using VHDL and implemented as hardware in a PLD.

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Parallel In/Serial Out Shift Registers

 For a register with parallel data inputs, the bits are entered
simultaneously into their respective stages on parallel lines
rather than on a bit-by-bit basis on one line as with serial data
inputs.

 The serial output is the same as in serial in/serial out shift

registers, once the data are completely stored in the register.

 For parallel data, multiple bits are transferred at one time.

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Parallel In/Serial Out Shift Registers cont’d

Module 56 – Types of Shift Register Data I/Os 19

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Parallel In/Serial Out Shift Registers cont’d

Module 56 – Types of Shift Register Data I/Os 20

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Parallel In/Serial Out Shift Registers cont’d

 Programmable Logic Device (PLD)

 The 8-bit serial in/parallel out shift register can be described
using VHDL and implemented as hardware in a PLD.

Module 56 – Types of Shift Register Data I/Os 21

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Parallel In/Serial Out Shift Registers cont’d

Module 56 – Types of Shift Register Data I/Os 22

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IMPLEMENTATION:
8-BIT PARALLEL LOAD SHIFT REGISTER

 Fixed-Function Device

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IMPLEMENTATION:
8-BIT PARALLEL LOAD SHIFT REGISTER cont’d

 Programmable Logic Device (PLD)

 The 8-bit parallel load shift register is a parallel in/serial out
device and can be implemented in a PLD with the following
VHDL code:

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IMPLEMENTATION:
8-BIT PARALLEL LOAD SHIFT REGISTER cont’d

Module 56 – Types of Shift Register Data I/Os 25

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IMPLEMENTATION:
8-BIT PARALLEL LOAD SHIFT REGISTER cont’d

Module 56 – Types of Shift Register Data I/Os 26

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Parallel In/Parallel Out Shift Registers

Module 56 – Types of Shift Register Data I/Os 27

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IMPLEMENTATION:
4-BIT PARALLEL-ACCESS SHIFT REGISTER cont’d

 Fixed-Function Device

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IMPLEMENTATION:
4-BIT PARALLEL-ACCESS SHIFT REGISTER cont’d

 Fixed-Function Device
 The 74HC195 can be used for parallel
in/parallel out operation.
 Because it also has a serial input, it
can be used for serial in/serial out
and serial in/parallel out operations.
 It can be used for parallel in/serial
out operation by using Q3 as the
output.

 When the SHIFT/LOAD’ input

(SH/LD’) is LOW, the data on the
parallel inputs are entered
synchronously on the positive
transition of the clock.
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IMPLEMENTATION:
4-BIT PARALLEL-ACCESS SHIFT REGISTER cont’d

 Fixed-Function Device

 When (SH/LD’) is HIGH, stored data

will shift right (Q0 to Q3)
synchronously with the clock.

 Inputs J and K’ are the serial data

inputs to the first stage of the
register (Q0); Q3 can be used for
serial output data.
 The active-LOW clear input is
asynchronous.

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IMPLEMENTATION:
4-BIT PARALLEL-ACCESS SHIFT REGISTER cont’d

 Fixed-Function Device

Module 56 – Types of Shift Register Data I/Os

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 IMPLEMENTATION:
4-BIT PARALLEL-ACCESS SHIFT REGISTER cont’d

 Programmable Logic Device (PLD)

 The VHDL code for a 4-bit parallel

in/parallel out shift register is as
follows:

Module 56 – Types of Shift Register Data I/Os

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Mastery Exercises

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Mastery Exercises cont’d

Module 56 – Types of Shift Register Data I/Os 34

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Mastery Exercises cont’d

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Mastery Exercises cont’d

Module 56 – Types of Shift Register Data I/Os 36

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