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A B C D E

Model Name : AIVP1/AIVP2


File Name :

1 1

Compal Confidential
2 2

AIVP1/AIVP2 UMA M/B Schematics Document

Intel Bay Trail M

2015-01-15
3 3

REV:0.2

14@
DA1 PCB
Part Number Description
4 DA6001DH000 REV0.1 M/B 4

15@
DA2 PCB
Security Classification Compal Secret Data Compal Electronics, Inc.
Part Number Description
2014/11/07 2015/11/07 Title
DA6001DH000 REV0.1 M/B
Issued Date Deciphered Date Cover Page
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-C771P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, January 15, 2015 Sheet 1 of 34
A B C D E
A B C D E

Compal Confidential
Model Name : AIVP1/AIVP2
Memory Bus
A-ch DDR3L-SO-DIMM X1
Project Name :
DDR3L 1333MHz (1.35V)
P13
1 1

USB3.0 x1 Left USB3.0 x1


USB2.0 x1 USB30 Port 0
P22

USB2.0 x1 Left USB2.0 x1


eDP X1 USB20 Port 1
(2 Lanes) P22
eDP Conn.
P14
USB2.0 x1 Int. Camera
USB 2.0 Port 2
P14 Reserve
DDI X1
Intel VLV-M
(4 Lanes) SOC USB2.0 x1 (wtih HUB)
HDMI Conn. USB HUB USB2.0 x1 USB/B
P15 USB 2.0 Port 3 USB 2.0 X1
25mm X 27mm P23
2
Sub-board 2

PCIe X1
LAN PCIe X1
(1 Lanes)
RJ45 Conn. RTL8107E-CG (1 Lanes)
P16 10/100 WLAN
PCIe Port 2 USB2.0 x1 for BT PCIe Port 3
Aditya11ttt
P16
(without USB HUB) USB2.0 x1 for BT
(with USB Hub)
P18

LED Card Reader PCIe X1 SATA X1 HDD Conn.


P21 (1 Lanes) SATA Port 0
Realtek
RTS5220-GRT P22

DC to DC PCIe Port 1 P17 SATA X1 ODD Conn.


SATA Port 1
P24
3
P22 3

RTC Audio Codec


HDA Realtek
P8 Reserve
ALC233VB2
P19
LPC SPI
Sub-board
14" 15" TCM EC SPI ROM
Nationz Nuvoton 8MB Int. MIC Conn. Int. Speaker Conn. Audio Combo Jack
Power/B Z32H320TC NPCE388N HP & MIC
Power button P20
LID switch P21

P21

Touch Pad Int. KBD


P21 P21
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


2014/11/07 2015/11/07 Title
Issued Date Deciphered Date Block Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-C771P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, January 14, 2015 Sheet 2 of 34
A B C D E
A B C D E

Voltage Rails
Power Plane Description S0 S3 S4/S5
BOM Option Table
VIN 19V Adapter power supply ON ON ON
BATT+ 12V Battery power supply
Item BOM Structure
ON ON ON
B+ AC or battery power rail for power circuit. (19V/12V) ON ON ON
Unpop @
Connector ME@
1 1
+RTCVCC RTC Battery Power ON ON ON XDP (Debug Port) XDP@
+1.0VALW +1.0v Always power rail ON ON ON EMC requirement EMI@
EMC requirement unpop @EMI@
+1.8VALW +1.8v Always power rail ON ON ON ESD requirement ESD@
+3VALW +3.3v Always power rail ON ON ON ESD requirement unpop @ESD@
+5VALW +5.0v Always power rail ON ON ON TCM requirement TCM@
+1.35V +1.35V power rail for DDR3L ON ON OFF
NTCM SKU NTCM@
+SOC_VCC Core voltage for SOC ON OFF OFF
Camera requirement CMOS@
+SOC_VNN GFX voltage for SOC ON OFF OFF ODD requirement ODD@
+0.675VS +0.675V power rail for DDR3L Terminator ON OFF OFF USB HUB requirement HUB@
+1.0VS +1.0v system power rail ON OFF OFF Port 80(Debug Port) DB@
+1.05VS +1.05v system power rail ON OFF OFF Bluetooth requirment BT@
+1.35VS +1.35v system power rail ON OFF OFF 14" 14@
2
+1.8VS +1.8v system power rail ON OFF OFF 15" 15@ 2

+3VS +3.3v system power rail ON OFF OFF


+5VS +5.0v system power rail ON OFF OFF

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

EC SM Bus1 address EC SM Bus2 address 43 level BOM table

Device Address Device Address


43 Level Description BOM Structure
3 3

Smart Battery 0001 011X b


Charger 0b00010010 (0x12H)

SOC SM Bus address

Aditya11ttt
Device Address
SO-DIMM A (JDIMM1) A0h

UC4 UC4 UC4


N3540@ N2940@ N2840@

S IC FH8065301919700 SR1YW C0 2.16G C38! S IC FH8065301919600 SR1YV C0 1.83G C38! S IC FH8065301903600 SR1YJ C0 2.16G C38!
Part Number = SA00007ZH30 Part Number = SA00007ZI30 Part Number = SA00007ZJ30

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


2014/11/07 2015/11/07 Title
Issued Date Deciphered Date Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-C771P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, January 14, 2015 Sheet 3 of 34
A B C D E
5 4 3 2 1

EVT Power Sequence


2015_0115_ AC

Power On S3 S3 Resume Power Off


Plug in
+3VLP
D +3VLP → 44.06us D
EC_ON
EC_ON
+3VALW
→ 3.21ms
+3VALW
+5VALW
→ 3.55ms
+5VALW
+1.05VALW
→ 7.04ms
+1.05VALW
+1.8VALW
→ 7.92ms
+1.8VALW
ON/OFF#
ON/OFF#
EC_RSMRST#
EC_RSMRST# → 103.4ms

104ms → 60ms
PBTN_OUT# PBTN_OUT#
← →

PMC_SLP_S4# → 21.84ms → 21.9ms


PMC_SLP_S4#

PMC_SLP_S3# 24us → 14.8ms →
C PMC_SLP_S3# C
31.24us

SYSON 163.4ms → 183.9ms SYSON

+1.35V → 508us 302.4us +1.35V


→ 106.4ns DDR_PWROK
DDR_PWROK 4.397ms →

→ 139.2ms

VR_ON → 138.7ms 2.192us 2.192us
→ VR_ON
→ 2.399ms 4.20ms → 3.3ms
+CORE_VNN → 2.369ms → +CORE_VNN
→ 9us → 12.40ms 12.1ms
+CORE_VCC → 16.5us → +CORE_VCC

→ 2.6ms 2.41us
→ → 2.452us
VGATE → 2.58ms → VGATE


→ → 1.037us
B
17.8ms 17.98ms B
SUSP# SUSP#
(SUSP) → 32.8us → 4.32ms → 48us → 2.8ms
+1.05VS +1.05VS
(82K/0.1u) → 2.76ms 19.30ms → 2.88ms → 16.5ms
+1.8VS → +1.8VS
(100K/0.1u) → 3.39ms 21.2ms → 3.56ms → 16.4ms
+3VS → +3VS
(120K/0.1u) → 4.23ms 37.8ms → 4.52ms → 43.2ms
+5VS → +5VS
(47K/0.1u) → 1.76ms → 17.68ms → 1.828ms → 11.7ms
+1.35VS +1.35VS
(0R) → 5.7ms → 4us → 2.3ms
+0.675VS 5.6us → +0.675VS
→ →

1.036us → → 132.9ms →
→ 51.16ms → 51.16ms
KBRST# 132.9ms KBRST#
→ 102.3ms 16.69ms → 102.3ms 15.61ms
PMC_CORE_PWROK → → PMC_CORE_PWROK

A A

→ 6.24ms 6.24ms →
PMC_PLTRST# PMC_PLTRST#

Security Classification Compal Secret Data Compal Electronics, Inc.


2014/11/07 2015/11/07 Title
Issued Date Deciphered Date Power Sequence
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-C771P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, January 15, 2015 Sheet 4 of 34
5 4 3 2 1
5 4 3 2 1

UC4A UC4B
[13] DDR_A_MA[0..15] K45 M36 DDR_A_D[0..63] [13] AY45 BG38
DDR_A_MA0 DDR_A_D0
DDR_A_MA1 H47 DRAM0_MA_0 DRAM0_DQ_0 J36 DDR_A_D1 BB47 DRAM1_MA_0 DRAM1_DQ_0 BC40
DDR_A_MA2 L41 DRAM0_MA_1 DRAM0_DQ_1 P40 DDR_A_D2 AW41 DRAM1_MA_1 DRAM1_DQ_1 BA42
DDR_A_MA3 H44 DRAM0_MA_2 DRAM0_DQ_2 M40 DDR_A_D3 BB44 DRAM1_MA_2 DRAM1_DQ_2 BD42
DDR_A_MA4 H50 DRAM0_MA_3 DRAM0_DQ_3 P36 DDR_A_D4 BB50 DRAM1_MA_3 DRAM1_DQ_3 BC38
DDR_A_MA5 G53 DRAM0_MA_4 DRAM0_DQ_4 N36 DDR_A_D5 BC53 DRAM1_MA_4 DRAM1_DQ_4 BD36
D DRAM0_MA_5 DRAM0_DQ_5 DRAM1_MA_5 DRAM1_DQ_5 D
DDR_A_MA6 H49 K40 DDR_A_D6 BB49 BF42
DDR_A_MA7 D50 DRAM0_MA_6 DRAM0_DQ_6 K42 DDR_A_D7 BF50 DRAM1_MA_6 DRAM1_DQ_6 BC44
DDR_A_MA8 G52 DRAM0_MA_7 DRAM0_DQ_7 B32 DDR_A_D8 BC52 DRAM1_MA_7 DRAM1_DQ_7 BH32
DDR_A_MA9 E52 DRAM0_MA_8 DRAM0_DQ_8 C32 DDR_A_D9 BE52 DRAM1_MA_8 DRAM1_DQ_8 BG32
DDR_A_MA10 K48 DRAM0_MA_9 DRAM0_DQ_9 C36 DDR_A_D10 AY48 DRAM1_MA_9 DRAM1_DQ_9 BG36
DDR_A_MA11 E51 DRAM0_MA_10 DRAM0_DQ_10 A37 DDR_A_D11 BE51 DRAM1_MA_10 DRAM1_DQ_10 BJ37
DDR_A_MA12 F47 DRAM0_MA_11 DRAM0_DQ_11 C33 DDR_A_D12 BD47 DRAM1_MA_11 DRAM1_DQ_11 BG33
DDR_A_MA13 J51 DRAM0_MA_12 DRAM0_DQ_12 A33 DDR_A_D13 BA51 DRAM1_MA_12 DRAM1_DQ_12 BJ33
DDR_A_MA14 B49 DRAM0_MA_13 DRAM0_DQ_13 C37 DDR_A_D14 BH49 DRAM1_MA_13 DRAM1_DQ_13 BG37
DDR_A_MA15 B50 DRAM0_MA_14 DRAM0_DQ_14 B38 DDR_A_D15 BH50 DRAM1_MA_14 DRAM1_DQ_14 BH38
DRAM0_MA_15 DRAM0_DQ_15 F36 DDR_A_D16 DRAM1_MA_15 DRAM1_DQ_15 AU36
[13] DDR_A_DM[0..7] G36 DRAM0_DQ_16 G38 BD38 DRAM1_DQ_16 AT36
DDR_A_DM0 DDR_A_D17
DDR_A_DM1 B36 DRAM0_DM_0 DRAM0_DQ_17 F42 DDR_A_D18 BH36 DRAM1_DM_0 DRAM1_DQ_17 AV40
DDR_A_DM2 F38 DRAM0_DM_1 DRAM0_DQ_18 J42 DDR_A_D19 BC36 DRAM1_DM_1 DRAM1_DQ_18 AT40
DDR_A_DM3 B42 DRAM0_DM_2 DRAM0_DQ_19 G40 DDR_A_D20 BH42 DRAM1_DM_2 DRAM1_DQ_19 BA36
DDR_A_DM4 P51 DRAM0_DM_3 DRAM0_DQ_20 C38 DDR_A_D21 AT51 DRAM1_DM_3 DRAM1_DQ_20 AV36
DDR_A_DM5 V42 DRAM0_DM_4 DRAM0_DQ_21 G44 DDR_A_D22 AM42 DRAM1_DM_4 DRAM1_DQ_21 AY42
DDR_A_DM6 Y50 DRAM0_DM_5 DRAM0_DQ_22 D42 DDR_A_D23 AK50 DRAM1_DM_5 DRAM1_DQ_22 AY40
DDR_A_DM7 Y52 DRAM0_DM_6 DRAM0_DQ_23 A41 DDR_A_D24 AK52 DRAM1_DM_6 DRAM1_DQ_23 BJ41
DRAM0_DM_7 DRAM0_DQ_24 C41 DDR_A_D25 DRAM1_DM_7 DRAM1_DQ_24 BG41
M45 DRAM0_DQ_25 A45 DDR_A_D26 AV45 DRAM1_DQ_25 BJ45
[13] DDR_A_RAS# M44 DRAM0_RAS# DRAM0_DQ_26 B46 AV44 DRAM1_RAS# DRAM1_DQ_26 BH46
DDR_A_D27
[13] DDR_A_CAS# H51 DRAM0_CAS# DRAM0_DQ_27 C40 BB51 DRAM1_CAS# DRAM1_DQ_27 BG40
DDR_A_D28
[13] DDR_A_WE# DRAM0_WE# DRAM0_DQ_28 B40 DRAM1_WE# DRAM1_DQ_28 BH40
DDR_A_D29
K47 DRAM0_DQ_29 B48 DDR_A_D30 AY47 DRAM1_DQ_29 BH48
[13] DDR_A_BS0 K44 DRAM0_BS_0 DRAM0_DQ_30 B47 AY44 DRAM1_BS_0 DRAM1_DQ_30 BH47
DDR_A_D31
[13] DDR_A_BS1 D52 DRAM0_BS_1 DRAM0_DQ_31 K52 BF52 DRAM1_BS_1 DRAM1_DQ_31 AY52
DDR_A_D32
[13] DDR_A_BS2 DRAM0_BS_2 DRAM0_DQ_32 K51 DRAM1_BS_2 DRAM1_DQ_32 AY51
DDR_A_D33
P44 DRAM0_DQ_33 T52 DDR_A_D34 AT44 DRAM1_DQ_33 AP52
[13] DDR_A_CS0# DRAM0_CS_0# DRAM0_DQ_34 T51 DRAM1_CS_0# DRAM1_DQ_34 AP51
DDR_A_D35
P45 DRAM0_DQ_35 L51 DDR_A_D36 AT45 DRAM1_DQ_35 AW51
[13] DDR_A_CS2# DRAM0_CS_2# DRAM0_DQ_36 L53 DRAM1_CS_2# DRAM1_DQ_36 AW53
DDR_A_D37
DRAM0_DQ_37 R51 DDR_A_D38 DRAM1_DQ_37 AR51
C47 DRAM0_DQ_38 R53 DDR_A_D39 BG47 DRAM1_DQ_38 AR53
[13] DDR_A_CKE0 D48 DRAM0_CKE_0 DRAM0_DQ_39 T47 BE46 DRAM1_CKE_0 DRAM1_DQ_39 AP47
C DDR_A_D40 C
F44 RESERVED_D48 DRAM0_DQ_40 T45 DDR_A_D41 BD44 RESERVED_BE46 DRAM1_DQ_40 AP45
[13] DDR_A_CKE2 E46 DRAM0_CKE_2 DRAM0_DQ_41 Y40 BF48 DRAM1_CKE_2 DRAM1_DQ_41 AK40
DDR_A_D42
RESERVED_E46 DRAM0_DQ_42 V41 DDR_A_D43 RESERVED_BF48 DRAM1_DQ_42 AM41
T41 DRAM0_DQ_43 T48 DDR_A_D44 AP41 DRAM1_DQ_43 AP48
[13] DDR_A_ODT0 DRAM0_ODT_0 DRAM0_DQ_44 T50 DRAM1_ODT_0 DRAM1_DQ_44 AP50
DDR_A_D45
P42 DRAM0_DQ_45 Y42 DDR_A_D46 AT42 DRAM1_DQ_45 AK42
[13] DDR_A_ODT2 DRAM0_ODT_2 DRAM0_DQ_46 AB40 DRAM1_ODT_2 DRAM1_DQ_46 AH40
DDR_A_D47
DRAM0_DQ_47 V45 DDR_A_D48 DRAM1_DQ_47 AM45
M50 DRAM0_DQ_48 V47 DDR_A_D49 AV50 DRAM1_DQ_48 AM47
[13] DDR_A_CLK0 M48 DRAM0_CKP_0 DRAM0_DQ_49 AD48 AV48 DRAM1_CKP_0 DRAM1_DQ_49 AF48
DDR_A_D50
[13] DDR_A_CLK0# DRAM0_CKN_0 DRAM0_DQ_50 AD50 DRAM1_CKN_0 DRAM1_DQ_50 AF50
DDR_A_D51
DRAM0_DQ_51 V48 DDR_A_D52 DRAM1_DQ_51 AM48
P50 DRAM0_DQ_52 V50 DDR_A_D53 DRAM1_DQ_52 AM50
[13] DDR_A_CLK2 P48 DRAM0_CKP_2 DRAM0_DQ_53 AB44 AT50 DRAM1_DQ_53 AH44
DDR_A_D54
[13] DDR_A_CLK2# DRAM0_CKN_2 DRAM0_DQ_54 Y45 AT48 DRAM1_CKP_2 DRAM1_DQ_54 AK45
DDR_A_D55
DRAM0_DQ_55 V52 DDR_A_D56 DRAM1_CKN_2 DRAM1_DQ_55 AM52
DRAM0_DQ_56 W51 DDR_A_D57 DRAM1_DQ_56 AL51
DDR_A_RST# P41 DRAM0_DQ_57 AC53 DDR_A_D58 DRAM1_DQ_57 AG53
[13] DDR_A_RST# DRAM0_DRAMRST# DRAM0_DQ_58 AC51 AT41 DRAM1_DQ_58 AG51
DDR_A_D59
DRAM0_DQ_59 W53 DDR_A_D60 DRAM1_DRAMRST# DRAM1_DQ_59 AL53
+DDR_SOC_VREF DRAM0_DQ_60 Y51 DDR_A_D61 DRAM1_DQ_60 AK51
AF44 DRAM0_DQ_61 AD52 DDR_A_D62 DRAM1_DQ_61 AF52
DRAM_VREF 0.675V DRAM0_DQ_62 DRAM1_DQ_62
AD51 DDR_A_D63 AF51
DRAM0_DQ_63 DRAM1_DQ_63
100K_0402_1% 1 2 RC1 DDR_TERMN0 AF42 J38 DDR_A_DQS0 BF40
100K_0402_1% 1 2 RC2 DDR_TERMN1 AH42 ICLK_DRAM_TERMN_AF42 DRAM0_DQSP_0 K38 DDR_A_DQS#0 DRAM1_DQSP_0 BD40
ICLK_DRAM_TERMN_AH42 DRAM0_DQSN_0 C35 DDR_A_DQS1 DRAM1_DQSN_0 BG35
DRAM0_DQSP_1 B34 DDR_A_DQS#1 DRAM1_DQSP_1 BH34
Need confirm with PWR for this net name DRAM0_DQSN_1 DRAM1_DQSN_1
D40 DDR_A_DQS2 BA38
DDR_PWROK AD42 DRAM0_DQSP_2 F40 DDR_A_DQS#2 DRAM1_DQSP_2 AY38
[29] DDR_PWROK AB42 DRAM_VDD_S4_PWROK DRAM0_DQSN_2 B44 DRAM1_DQSN_2 BH44
DDR_A_DQS3
[8] DDR_CORE_PWROK DRAM_CORE_PWROK DRAM0_DQSP_3 C43 DRAM1_DQSP_3 BG43
DDR_A_DQS#3
DRAM0_DQSN_3 N53 DDR_A_DQS4 DRAM1_DQSN_3 AU53
23.2_0402_1% 1 2 RC3 DDR_RCOMP0 AD44 DRAM0_DQSP_4 M52 DDR_A_DQS#4 DRAM1_DQSP_4 AV52
29.4_0402_1% 1 2 RC4 DDR_RCOMP1 AF45 DRAM_RCOMP_0 DRAM0_DQSN_4 T42 DDR_A_DQS5 DRAM1_DQSN_4 AP42
B DRAM_RCOMP_1 DRAM0_DQSP_5 DRAM1_DQSP_5 B
162_0402_1% 1 2 RC5 DDR_RCOMP2 AD45 T44 DDR_A_DQS#5 AP44
DRAM_RCOMP_2 DRAM0_DQSN_5 Y47 DDR_A_DQS6 DRAM1_DQSN_5 AK47
DRAM0_DQSP_6 Y48 DDR_A_DQS#6 DRAM1_DQSP_6 AK48
Follow CRB v1.15 DRAM0_DQSN_6 DRAM1_DQSN_6
AF40 AB52 DDR_A_DQS7 AH52
AF41 RESERVED_AF40 DRAM0_DQSP_7 AA51 DDR_A_DQS#7 DRAM1_DQSP_7 AJ51
AD40 RESERVED_AF41 DRAM0_DQSN_7 DRAM1_DQSN_7
AD41 RESERVED_AD40
RESERVED_AD41 DDR_A_DQS[0..7] [13]
1 OF 13 2 OF 13
DDR_A_DQS#[0..7] [13]
FH8065301546401_FCBGA131170 FH8065301546401_FCBGA131170
DDR_A_RST# CPU@ CPU@

DDR_PWROK

1 1
ESD@ ESD@
CC20 CC94
100P_0402_50V8J 100P_0402_50V8J
2 2
close to CPU
0105 added for ESD

Close To SOC Pin

+1.35V +DDR_SOC_VREF
A A
1 2
RC6 1
4.7K_0402_1%
CC1
1 2 .1U_0402_16V7K
RC7 2
4.7K_0402_1%

Security Classification Compal Secret Data Compal Electronics, Inc.


2014/11/07 2015/11/07 Title
Issued Date Deciphered Date VLV-M(1/8) Memory DDR3L
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-C771P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, January 14, 2015 Sheet 5 of 34
5 4 3 2 1
5 4 3 2 1

UC4C

AV3 AG3
[15] HDMI_TX2+ DDI0_TXP_0 DDI1_TXP_0 EDP_TXP0 [14]
AV2 1.0V 1.0V AG1
[15] HDMI_TX2- DDI0_TXN_0 DDI1_TXN_0 EDP_TXN0 [14]
AT2 AF3
[15] HDMI_TX1+ DDI0_TXP_1 DDI1_TXP_1 EDP_TXP1 [14]
AT3 AF2
[15] HDMI_TX1- DDI0_TXN_1 DDI1_TXN_1 EDP_TXN1 [14]
AR3 AD3
[15] HDMI_TX0+ DDI0_TXP_2 DDI1_TXP_2
AR1 AD2
[15] HDMI_TX0- DDI0_TXN_2 DDI1_TXN_2
AP3 AC3
[15] HDMI_CLK+
AP2 DDI0_TXP_3 DDI1_TXP_3 AC1 eDP Panel +1.8VS
D
HDMI [15] HDMI_CLK- DDI0_TXN_3 DDI1_TXN_3 D

AL3 1.0V AK3 EDP_AUXP [14]


DDI0_AUXP DDI1_AUXP

5
AL1 1.0V AK2 EDP_AUXN [14] @ UC5
DDI0_AUXN DDI1_AUXN 1

P
D27 K30 NC 4 1 @ 2
[15] HDMI_HPD# DDI0_HPD 1.8V 1.8V DDI1_HPD EDP_HPD# [14] +1.8VS Y BKOFF# [14]
DDI1_ENBKL 2 RC8 0_0402_5%
A

G
C26 1.8V 1.8V P30 DDI1_ENABLE RC9 1 2 2.2K_0402_5%
[15] HDMI_DDCDATA DDI0_DDCDATA DDI1_DDCDATA
C28 1.8V 1.8V G30 NL17SZ07DFT2G_SC70-5
[15] HDMI_DDCCLK

3
DDI0_DDCCLK DDI1_DDCCLK SA00004BV00
B28 1.8V N30 DDI1_ENVDD
C27 DDI0_VDDEN DDI1_VDDEN J30 DDI1_ENBKL
DDI0_BKLTEN 1.8V DDI1_BKLTEN
B26 1.8V M30 DDI1_PWM RC10 1 RS@ 2
DDI0_BKLTCTL DDI1_BKLTCTL SOC_ENBKL [20]
0_0402_5%
AH3
1 RC11 2 DDI0_RCOMPP AK12 VSS_AH3 AH2
DDI0_RCOMP_P VSS_AH2
Follow CRB v1.15 0ohm till to GND
402_0402_1% DDI0_RCOMPN AK13
AM14 DDI0_RCOMP_N AH14
AM13 RESERVED_AM14 RESERVED_AH14 AH13
AM3 RESERVED_AM13 RESERVED_AH13 AF14
AM2 VSS_AM3 RESERVED_AF14 AF13 +1.8VS
Follow CRB v1.15 0ohm till to GND VSS_AM2 RESERVED_AF13
BA3
VGA_RED

5
AY2 @ UC6
VGA_BLUE BA1 1

P
VGA_GREEN AW1 NC 4 1 @ 2
VGA_IREF Y ENVDD [14]
AY3 DDI1_ENVDD 2 RC12 0_0402_5%
VGA_IRTN A

G
C C
3.3V BD2 NL17SZ07DFT2G_SC70-5

3
VGA_HSYNC BF2 SA00004BV00
3.3V VGA_VSYNC
3.3V BC1
VGA_DDCCLK BC2 RC13 1 RS@ 2 0_0402_5%
3.3V VGA_DDCDATA SOC_ENVDD [20]
T2 T7
T3 RESERVED_T2 RESERVED_T7 T9
AB3 RESERVED_T3 RESERVED_T9 AB13 +1.8VS
AB2 RESERVED_AB3 RESERVED_AB13 AB12
Y3 RESERVED_AB2 RESERVED_AB12 Y12
RESERVED_Y3 RESERVED_Y12

5
Y2 Y13 UC7
W3 RESERVED_Y2 RESERVED_Y13 V10 1

P
W1 RESERVED_W3 RESERVED_V10 V9 NC 4
RESERVED_W1 RESERVED_V9 Y INVT_PWM_SOC [14]
V2 T12 DDI1_PWM 2
RESERVED_V2 RESERVED_T12 A

G
V3 T10
R3 RESERVED_V3 RESERVED_T10 V14 NL17SZ07DFT2G_SC70-5

3
R1 RESERVED_R3 RESERVED_V14 V13 SA00004BV00
+1.8VS AD6 RESERVED_R1 RESERVED_V13 T14
AD4 RESERVED_AD6 RESERVED_T14 T13
AB9 RESERVED_AD4 RESERVED_T13 T6
RESERVED_AB9 RESERVED_T6
1

AB7 T4 +3VS
@ Y4 RESERVED_AB7 RESERVED_T4 P14 RPC1
RC14 Y6 RESERVED_Y4 RESERVED_P14 BKOFF# 5 4
10K_0402_5% V4 RESERVED_Y6 F34 ENVDD 6 3
V6 RESERVED_V4 GPIO_S0_NC_15 M32 INVT_PWM_SOC 7 2
2

B GPIO_NC13 A29 RESERVED_V6 GPIO_S0_NC_16 D28 8 1 B


GPIO_NC14 C29 GPIO_S0_NC_13 GPIO_S0_NC_17 J28
T1 GPIO_S0_NC14 GPIO_S0_NC_18
1

AB14 K34 4.7K_0804_8P4R_5%


GPIO_NC12 B30 RESERVED_AB14 GPIO_S0_NC_19 D34
T2 GPIO_S0_NC_12 GPIO_S0_NC_20
RC15 C30 F32 RPC2
10K_0402_5% RESERVED_C30 GPIO_S0_NC_21 F28 DDI1_ENBKL 8 1
GPIO_S0_NC_22 K28 DDI1_ENVDD 7 2
2

GPIO_S0_NC_23 J34 DDI1_PWM 6 3


GPIO_S0_NC_24 N32 5 4
GPIO_S0_NC_25 D32
Follow CRB v1.15 3 OF 10 GPIO_S0_NC_26 100K_0804_8P4R_5%

FH8065301546401_FCBGA131170 CPU@ CC2


100P_0402_50V8J
GPIO_S0_NC[13]: DDI1_ENBKL 2 1
Multiplexed with Hardware Straps Pin:MDSI_DDCDATA ESD@
CC3
100P_0402_50V8J
DDI1_ENVDD 2 1
ESD@
CC4
100P_0402_50V8J
DDI1_PWM 2 1
ESD@
CC5
100P_0402_50V8J
EDP_HPD# 2 1
A A
ESD@

Security Classification Compal Secret Data Compal Electronics, Inc.


2014/11/07 2015/11/07 Title
Issued Date Deciphered Date VLV-M(2/8) Display
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
LA-C771P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, January 14, 2015 Sheet 6 of 34
5 4 3 2 1
5 4 3 2 1

UC4D

BF6 AY7
[22] SATA_PTX_DRX_P0 BG7 SATA_TXP_0 PCIE_TXP_0 AY6
[22] SATA_PTX_DRX_N0 SATA_TXN_0 PCIE_TXN_0
HDD
AU16 AT14
[22] SATA_PRX_DTX_P0 SATA_RXP_0 PCIE_RXP_0
AV16 AT13
[22] SATA_PRX_DTX_N0 SATA_RXN_0 PCIE_RXN_0
D D
BD10 AV6 PCIE_PTX_DRX_P1 .1U_0402_16V7K 1 2 CC6
[22] SATA_PTX_DRX_P1 SATA_TXP_1 PCIE_TXP_1 PCIE_PTX_C_DRX_P1 [17]
BF10 AV4 PCIE_PTX_DRX_N1 .1U_0402_16V7K 1 2 CC7
[22] SATA_PTX_DRX_N1 SATA_TXN_1 PCIE_TXN_1 PCIE_PTX_C_DRX_N1 [17]
ODD Card reader
AY16 AT10 PCIE_PRX_DTX_P1
[22] SATA_PRX_DTX_P1 BA16 SATA_RXP_1 PCIE_RXP_1 AT9 PCIE_PRX_DTX_N1 PCIE_PRX_DTX_P1 [17]
[22] SATA_PRX_DTX_N1 SATA_RXN_1 PCIE_RXN_1 PCIE_PRX_DTX_N1 [17]
BB10 AT7 PCIE_PTX_DRX_P2 .1U_0402_16V7K 1 2 CC8
BC10 VSS_BB10 PCIE_TXP_2 AT6 PCIE_ATX_C_GRX_P0 [16]
Follow CRB V1.15 0ohm till to GND PCIE_PTX_DRX_N2 .1U_0402_16V7K 1 2 CC9
VSS_BC10 PCIE_TXN_2 PCIE_ATX_C_GRX_N0 [16]
PCIE LAN
EC_SCI# BA12 AP12 PCIE_GTX_C_ARX_P0
[20] EC_SCI# AY14 SATA_GP0 / GPIO_S0_SC_0 PCIE_RXP_2 AP10 PCIE_GTX_C_ARX_P0 [16]
DEVSLP_SOC PCIE_GTX_C_ARX_N0
T3 SATA_GP1 / SATA_DEVSLP_0 / GPIO_S0_SC_1 PCIE_RXN_2 PCIE_GTX_C_ARX_N0 [16] +1.8VS
Follow CRB v1.15 AY12
SATA_LED# / GPIO_S0_SC_2 AP6 PCIE_PTX_DRX_P3 .1U_0402_16V7K 1 2 CC10 RPC3
PCIE_TXP_3 PCIE_PTX_C_DRX_P3 [18]
1 RC16 2 SATA_RCOMPP AU18 AP4 PCIE_PTX_DRX_N3 .1U_0402_16V7K 1 2 CC11 LAN_CLKREQ# 1 8
+1.8VS AT18 SATA_RCOMP_P PCIE_TXN_3 PCIE_PTX_C_DRX_N3 [18] 2 7
402_0402_1% SATA_RCOMPN WLAN WLAN_CLKREQ#
SATA_RCOMP_N AP9 PCIE_PRX_DTX_P3 VGA_CLKREQ# 3 6
PCIE_RXP_3 PCIE_PRX_DTX_P3 [18]
AP7 PCIE_PRX_DTX_N3 Card_CLKREQ# 4 5
PCIE_RXN_3 PCIE_PRX_DTX_N3 [18]
1

AT22
RC17 MMC1_CLK / GPIO_S0_SC_16 BB7 10K_0804_8P4R_5%
AV20 VSS_BB7 BB5
10K_0402_5%
MMC1_D0 / GPIO_S0_SC_17 VSS_BB5
Follow CRB V1.15 0ohm till to GND
AU22
AV22 MMC1_D1 / GPIO_S0_SC_18 BG3 VGA_CLKREQ#
2

AT20 MMC1_D2 / GPIO_S0_SC_19 PCIE_CLKREQ_0# / GPIO_S0_SC_3 BD7 Card_CLKREQ#


MMC1_D3 / GPIO_S0_SC_20 PCIE_CLKREQ_1# / GPIO_S0_SC_4 Card_CLKREQ# [17]
EC_SCI# AY24 BG5 LAN_CLKREQ# Check OD pin or not in Device side
AU26 MMC1_D4 / GPIO_S0_SC_21 PCIE_CLKREQ_2# / GPIO_S0_SC_5 BE3 LAN_CLKREQ# [16]
WLAN_CLKREQ#
AT26 MMC1_D5 / GPIO_S0_SC_22 PCIE_CLKREQ_3# / GPIO_S0_SC_6 BD5 WLAN_CLKREQ# [18]
C
AU20 MMC1_D6 / GPIO_S0_SC_23 SD3_WP / GPIO_S0_SC_7 C
MMC1_D7 / GPIO_S0_SC_24 1
AP14 PCIE_RCOMPP 1 RC18 2 ESD@
AV26 PCIE_RCOMP_P AP13 PCIE_RCOMPN 402_0402_1% CC95
BA24 MMC1_CMD / GPIO_S0_SC_25 PCIE_RCOMP_N 100P_0402_50V8J
MMC1_RST# / SATA_DEVSLP_0 / GPIO_S0_SC_26 BB4 2
AY18 RESERVED_BB4 BB3
MMC1_RCOMP RESERVED_BB3 RPC4
AV10 HDA_SYNC 8 1 HDA_SYNC_AUDIO [19]
BA18 RESERVED_AV10 AV9 HDA_SDOUT 7 2
SD2_CLK / GPIO_S0_SC_27 RESERVED_AV9 HDA_SDOUT_AUDIO [19]
AY20 HDA_BIT_CLK 6 3
SD2_D0 / GPIO_S0_SC_28 HDA_BITCLK_AUDIO [19]
BD20 BF20 HDA_RCOMP 49.9_0402_1% 1 2 RC19 HDA_RST# 5 4 HDA_RST_AUDIO# [19]
BA20 SD2_D1 / GPIO_S0_SC_29 HDA_LPE_RCOMP BG22 HDA_RST#
BD18 SD2_D2 / GPIO_S0_SC_30 HDA_RST# / LPE_I2S0_CLK / GPIO_S0_SC_8 BH20 HDA_SYNC 33_0804_8P4R_5%
BC18 SD2_D3_CD# / GPIO_S0_SC_31 HDA_SYNC / LPE_I2S0_FRM / GPIO_S0_SC_9 BJ21 HDA_BIT_CLK
SD2_CMD / GPIO_S0_SC_32 HDA_CLK / LPE_I2S0_DATAOUT / GPIO_S0_SC_10 BG20 HDA_SDOUT
HDA_SDO / LPE_I2S0_DATAIN / GPIO_S0_SC_11 BG19 HDA_SDIN0
HDA_SDI0 / LPE_I2S1_CLK / GPIO_S0_SC_12 BG21 HDA_SDIN0 [19]
HDA_SDI1 / LPE_I2S1_FRM / GPIO_S0_SC_13 T4
AY26 BH18
AT28 SD3_CLK / GPIO_S0_SC_33 HDA_DOCKRST# / LPE_I2S1_DATAOUT / GPIO_S0_SC_14 BG18 T5
BD26 SD3_D0 / GPIO_S0_SC_34 HDA_DOCKEN# / LPE_I2S1_DATAIN / GPIO_S0_SC_15 T6
GPIO_S0_SC_63: GPIO_S0_SC_65:
AU28 SD3_D1 / GPIO_S0_SC_35 BF28
SD3_D2 / GPIO_S0_SC_36 LPE_I2S2_CLK / SATA_DEVSLP_1 / GPIO_S0_SC_62 BIOS/EFI Boot Strap (BBS) Security Flash Descriptors
BA26 BA30 GPIO_S0_SC_63 BIOS Boot Selection 0 = Override
BC24 SD3_D3 / GPIO_S0_SC_37 LPE_I2S2_FRM / GPIO_S0_SC_63 BD28 +1.05VS
AV28 SD3_CD# / GPIO_S0_SC_38 LPE_I2S2_DATAIN / GPIO_S0_SC_64 BC30 GPIO_S0_SC_65
0 = LPC 1 = Normal Operation
BF22 SD3_CMD / GPIO_S0_SC_39 LPE_I2S2_DATAOUT / GPIO_S0_SC_65 1 = SPI (Internal PU)
SD3_1P8EN / GPIO_S0_SC_40

2
BD22 P34 +1.8VS +1.8VS
SD3_PWREN# / GPIO_S0_SC_41 RESERVED_P34 N34 RC20 EC programing :
B B
BF26 RESERVED_N34
SD3_RCOMP 69.8_0402_1% "High"for Flash BIOS

1
AK9
RESERVED_AK9 AK7

1
RESERVED_AK7 RC21 RC22 RS@
C24 10K_0402_5% 10K_0402_5% RC23
PROCHOT# H_PROCHOT# [20]
4 OF 10 Internal PD 2K 0_0402_5%

2
GPIO_S0_SC_63 GPIO_S0_SC_65 2 1
FH8065301546401_FCBGA131170

1
D
2
ME_EN [20]
G
@ S QC1

3
BSS138W-7-F_SOT323-3

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


2014/11/07 2015/11/07 Title
Issued Date Deciphered Date VLV-M(3/8) SATA/PCI-E/HDA
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-C771P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, January 14, 2015 Sheet 7 of 34
5 4 3 2 1
5 4 3 2 1

XTAL_25M_IN +1.8VS +3VS


+1.8VALW
Check power rail

1
RC24
YC1 1M_0402_5% +3VALW

2
G
25MHZ_10PF_7V25000014 @ RC25 BSS138W-7-F_SOT323-3

5
UC8 4.7K_0402_5%

2
1 3 XTAL_25M_OUT 1.8V 1 1.8V/3.3V PMC_PLTRST# 3 1 PLT_RST_BUF#

P
PLT_RST_BUF# [16,17,18,20,21]

2
1 3 RC27 +1.8VALW B 4 PLT_RST_BUF#

D
1 GND GND 1 Y
10K_0402_5% PMC_PLTRST# 2 QC2
A

G
CC12 CC13 @
10P_0402_25V8J 2 4 10P_0402_25V8J TC7SH08FUF_SSOP5 1 RS@ 2 PMC_PLTRST#_R
PMC_PLTRST#_R [20]

3
2 2 RC48 0_0402_5%

2
Change To 10pF for Vendor Suggest.

G
D
0701 @ PLT_RST Buffer D

1 3 PMC_PCIE_WAKE#
[18] SOC_PCIE_WAKE#

S
QC3
BSS138W-7-F_SOT323-3
+1.8VALW
+1.8VALW

UC4E

1
2

2
XTAL_25M_IN AH12 AU34
XTAL_25M_OUT AH10 ICLK_OSCIN SIO_UART1_RXD / GPIO_S0_SC_70 AV34 SKU_Strap1 RC28 RC29 RC81 RC26
ICLK_OSCOUT SIO_UART1_TXD / GPIO_S0_SC_71 BA34 SKU_Strap2 2.2K_0402_5%
SIO_UART1_RTS# / GPIO_S0_SC_72 10K_0402_5% 10K_0402_5% 10K_0402_5%
AD9 AY34 SKU_Strap3 @ @ @

2
RESERVED_AD9 SIO_UART1_CTS# / GPIO_S0_SC_73 DC1

1
RC30 1 2 4.02K_0402_1% ICLK_ICOMP AD14 BF34 PMC_ACIN 2 1
VCIN1_AC_IN [20,27]
RC31 1 2 47.5_0402_1% ICLK_RCOMP AD13 ICLK_ICOMP SIO_UART2_RXD / GPIO_S0_SC_74 BD34
ICLK_RCOMP SIO_UART2_TXD / GPIO_S0_SC_75 BD32 RB751V40_SC76-2
AD10 SIO_UART2_RTS# / GPIO_S0_SC_76 BF32 @
RESERVED_AD10 SIO_UART2_CTS# / GPIO_S0_SC_77 1

2
AD12
RESERVED_AD12 RC32 RC33 RC34 CC14
AF6 10K_0402_5% 10K_0402_5% 10K_0402_5% 100P_0402_50V8J
AF4 PCIE_CLKN_0 D26 @ @ @ 2
PCIE_CLKP_0 PMC_SUSPWRDNACK / GPIO_S5_11 ESD@
G24

1
AF9 PMC_SUSCLK_0 / GPIO_S5_12 F18
[17] CLK_PCIE_Card# AF7 PCIE_CLKN_1 PMC_SLP_S0IX# / GPIO_S5_13 F22
[17] CLK_PCIE_Card PCIE_CLKP_1 PMC_SLP_S4# D22 PMC_SLP_S4# [20]
Card PMC_SLP_S3# PMC_SLP_S3# [20]
J20 GPIO_S5_14
[16] CLK_PCIE_LAN#
AK4
PCIE_CLKN_2
GPIO_S5_14
PMC_ACPRESENT
D20 PMC_ACIN 0108 remove
LAN AK6 F26 PMC_PCIE_WAKE#
[16] CLK_PCIE_LAN PCIE_CLKP_2 PMC_WAKE_PCIE_0# / GPIO_S5_15 K26 +1.8VALW
PMC_BATLOW#
AM4 PMC_BATLOW# J26 PBTN_OUT# RPC5
[18] CLK_PCIE_WLAN# AM6 PCIE_CLKN_3 PMC_PWRBTN# / GPIO_S5_16 BG9 PBTN_OUT# [20] 1 8
WLAN XDP_RSTBTN# T7 PMC_PCIE_WAKE#
[18] CLK_PCIE_WLAN PCIE_CLKP_3 PMC_RSTBTN# F20 2 7
PMC_PLTRST# PMC_BATLOW#
AM9 PMC_PLTRST# J24 GPIO_S5_17 T8 GPIO_S5_14 3 6
C RESERVED_AM9 GPIO_S5_17 C
AM10 G18 PBTN_OUT# 4 5
RESERVED_AM10 PMC_SUS_STAT# / GPIO_S5_18
Close To SOC <1000mil
+1.8VALW 10K_0804_8P4R_5%

RC38 1 XDP@ 2 51_0402_5% XDP_H_PRDY# C11 RTC_TEST#


BH7 ILB_RTC_TEST# C12 RTC_RST#
RPC6 BH5 PMC_PLT_CLK_0 / GPIO_S0_SC_96 ILB_RTC_RST# XDP_RSTBTN# 1 2
4 5 XDP_H_TDI BH4 PMC_PLT_CLK_1 / GPIO_S0_SC_97 CC15 XDP@
3 6 XDP_H_TMS BH8 PMC_PLT_CLK_2 / GPIO_S0_SC_98 B10 EC_RSMRST# .1U_0402_16V7K
2 7 BH6 PMC_PLT_CLK_3 / GPIO_S0_SC_99 PMC_RSMRST# B7 EC_RSMRST# [20]
XDP_H_TCK PMC_CORE_PWROK
1 8 XDP_H_TRST# BJ9 PMC_PLT_CLK_4 / GPIO_S0_SC_100 PMC_CORE_PWROK
PMC_PLT_CLK_5 / GPIO_S0_SC_101 +1.05VS
RTC domain
51_0804_8P4R_5% C9 ILB_RTC_X1 EC_RSMRST# 1 2
XDP@ XDP_H_TCK D14 ILB_RTC_X1 A9 ILB_RTC_X2 RC37 100K_0402_5%
TAP_TCK ILB_RTC_X2

1
XDP_H_TRST# G12 B8 ILB_RTC_EXTPAD 1 2
F14 TAP_TRST# ILB_RTC_EXTPAD P22 CC16
XDP_H_TMS CC17 RC39
XDP_H_TDI F12 TAP_TMS RTC_VCC_P22 .1U_0402_16V7K 73.2_0402_1% 1 2
+1.8VALW TAP_TDI +RTCVCC
XDP_H_TDO G16
XDP_H_PRDY# D18 TAP_TDO

2
XDP_H_PREQ_BUF# F16 TAP_PRDY# B24 VR_SVID_ALERT#_SOC RC40 1 2 20_0402_1% 100P_0402_50V8J
RC45 1 XDP@ 2 200_0402_5% XDP_H_PREQ_BUF# AT34 TAP_PREQ# SVID_ALERT# A25 VR_SVID_DATA_SOC VR_SVID_ALERT# [32] ESD@
RC41 1 2 16.9_0402_1%
RESERVED_AT34 SVID_DATA C25 VR_SVID_DATA [32]
RC46 1 XDP@ 2 51_0402_5% XDP_H_TDO C23 SVID_CLK VR_SVID_CLK [32]
SOC_SPI_CS0#
C21 PCU_SPI_CS_0#
T9
PCU_SPI_CS_1# / GPIO_S5_21
0901:for ESD change to 100pF
RC35 1 2 10K_0402_5% EC_LID_OUT# SOC_SPI_MISO B22 AU32
SOC_SPI_MOSI A21 PCU_SPI_MISO SIO_PWM_0 / GPIO_S0_SC_94 AT32
RC36 2 1 10K_0402_5% EC_KBRST# SOC_SPI_CLK C22 PCU_SPI_MOSI SIO_PWM_1 / GPIO_S0_SC_95
PCU_SPI_CLK ILB_RTC_X1
ILB_RTC_X2
EC_KBRST# B18 1 2
[20] EC_KBRST# B16 GPIO_S5_0 K24 RC42
C18 GPIO_S5_1 / PMC_WAKE_PCIE_1 GPIO_S5_22 N24 XDP_OBSDATA_A0 T10 10M_0402_5%
A17 GPIO_S5_2 / PMC_WAKE_PCIE_2 GPIO_S5_23 M20 XDP_OBSDATA_A1 T11
EC_LID_OUT# C17 GPIO_S5_3 / PMC_WAKE_PCIE_3 GPIO_S5_24 J18 XDP_OBSDATA_A2 T12 32.768KHZ_12.5PF_Q13FC135000040
C16 GPIO_S5_4 GPIO_S5_25 M18 XDP_OBSDATA_A3 T13 YC2 1 2
B GPIO_S5_5 / PMU_SUSCLK_1 GPIO_S5_26 B
B14 K18
RPC7 C15 GPIO_S5_6 / PMU_SUSCLK_2 GPIO_S5_27 K20
GPIO_S5_7 / PMU_SUSCLK_3 GPIO_S5_28 1 1
SPI_CS0# 1 8 SOC_SPI_CS0# M22 RC83
SPI_MISO 2 7 SOC_SPI_MISO GPIO_S5_29 M24 0_0402_5% CC18 CC19
SPI_MOSI 3 6 SOC_SPI_MOSI GPIO_S5_30 RTC_RST# 1 2
CLR_CMOS# [20] 15P_0402_50V8J 15P_0402_50V8J
SPI_CLK 4 5 SOC_SPI_CLK C13 2 2
A13 GPIO_S5_8 RC84
22_0804_8P4R_5% C19 GPIO_S5_9 AV32 0_0402_5%
EMI@ GPIO_S5_10 SIO_SPI_CS# / GPIO_S0_SC_66 BA28 RTC_TEST# 1 2
SIO_SPI_MISO / GPIO_S0_SC_67
@ Change To 15pF for Vendor Suggest.
AY28 0701
RPC8 GPIO_RCOMP N26 SIO_SPI_MOSI / GPIO_S0_SC_68 AY30
SPI_CS0# 1 8 GPIO_RCOMP 5 OF 13 SIO_SPI_CLK / GPIO_S0_SC_69
EC_CS0# [20]
2

SPI_MISO 2 7
3 6 EC_SDIO [20]
SPI_MOSI RC44 FH8065301546401_FCBGA131170 CPU@
4 5 EC_SDI [20]
SPI_CLK +RTCVCC 0529 update
EC_SCK [20] 49.9_0402_1%
22_0804_8P4R_5% W=20mils RC47
1

EMI@ 20K_0402_1%
1 2 RTC_TEST#

1
Close To SPI ROM +3VALW +1.35VS
RC54
@ 0_0402_5%

1
1 2 RTC_RST# RC43

2
RC49 10K_0402_5%

5
CC24

CC25
1 20K_0402_1% 1 1 Check Intel UC9

1
3.3V 1 1.35V

2
NC

1
CC23 SP@ SP@ 4
2 Y DDR_CORE_PWROK [5]

ESD@ CC21
.1U_0402_16V7K CLRP2 CLRP1

100P_0402_50V8J
1U_0402_6.3V6K

1U_0402_6.3V6K
[20] PMC_CORE_PWROK 1

2
A

G
+1.8VALW 2 2 2 SHORT PADS SHORT PADS

2
SPI ROM ( 8MByte ) 1.8V
NL17SZ07DFT2G_SC70-5

3
Clear CMOS SA00004BV00
+1.8VALW CC22 1 2 .1U_0402_16V7K 2
RTC_RST
UC10 close to KB door
A A
RC50 1 2 3.3K_0402_5% SPI_CS0# 1 8 RC51 1 2 3.3K_0402_5%
SPI_MISO 2 CS# VCC 7 SPI_HOLD#
RC52 1 2 3.3K_0402_5% SPI_WP# 3 DO(IO1) HOLD#(IO3) 6 SPI_CLK
4 WP#(IO2) CLK 5 SPI_MOSI
GND DI(IO0)
W25Q64FWSSIG_SO8 Reserve for EMI(Near SPI ROM)

1 2 2 1 SPI_CLK Security Classification Compal Secret Data Compal Electronics, Inc.


CC26 @EMI@ RC53 @EMI@ 2014/11/07 2015/11/07 Title
10P_0402_50V8J 33_0402_5%
Issued Date Deciphered Date VLV-M(4/8) CLK/PMU/SPI/RTC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-C771P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, January 14, 2015 Sheet 8 of 34
5 4 3 2 1
5 4 3 2 1

D D
UC4F

G2 M10
GPIO_S5_31 RESERVED_M10 M9
RESERVED_M9
Bluetooth (Reserved) M3 P6
L1 GPIO_S5_32 RESERVED_P6 P7
RC80 1 RS@ 2 0_0402_5%
BT_OFF#_R K2 GPIO_S5_33 RESERVED_P7
[18] BT_OFF# K3 GPIO_S5_34
M2 GPIO_S5_35 M7
N3 GPIO_S5_36 RESERVED_M7 M12 USB3_REXT0 1 2
P2 GPIO_S5_37 USB3_REXT0 RC55
L3 GPIO_S5_38 P10 1.24K_0402_1%
GPIO_S5_39 RESERVED_P10 P12
RESERVED_P12
M4
J3 RESERVED_M4 M6
P3 GPIO_S5_40 RESERVED_M6
H3 GPIO_S5_41 D4
GPIO_S5_42 USB3_RXP0 PCH_USB3_RX0_P [22]
B12 E3 PCH_USB3_RX0_N [22]
GPIO_S5_43 USB3_RXN0
K6
USB3 Port 0
M16 USB3_TXP0 K7 PCH_USB3_TX0_P [22]
[22] USB20_P0 K16 USB_DP0 USB3_TXN0 PCH_USB3_TX0_N [22]
USB2 Port 0 (USB3.0 P0) [22] USB20_N0 USB_DN0
J14
[22] USB20_P1 G14 USB_DP1
Left USB Port [22] USB20_N1 USB_DN1
K12
[14] USB20_P2 J12 USB_DP2
Int. Camera [14] USB20_N2 USB_DN2
K10
[23] USB20_P3 H10 USB_DP3 H8
Bluetooth or USB HUB (Reserved) [23] USB20_N3 USB_DN3 RESERVED_H8 H7
RESERVED_H7
C C
1K_0402_1% 1 2 RC56 ICLK_USB_TERMP D10
1K_0402_1% 1 2 RC57 ICLK_USB_TERMN F10 ICLK_USB_TERMP H4
ICLK_USB_TERMN RESERVED_H4 H5 +1.8VS
RESERVED_H5
USB_OC0# C20
[22,23] USB_OC0# USB_OC_0# / GPIO_S5_19

1
USB_OC1# B20 @
USB_OC_1# / GPIO_S5_20 RC58
+1.8VALW 10K_0402_5%

RC59 1 2 10K_0402_5% USB_OC0# RC60 1 2 USB_RCOMP D6 BD12 GPIO_S0_SC_56:

2
RC61 1 2 10K_0402_5% USB_OC1# 45.3_0402_1% C7 USB_RCOMPO GPIO_S0_SC_55 BC12 GPIO_S0_SC_56
USB_RCOMPI GPIO_S0_SC_56 A16 Swap Override
BD14 DBG_UART_TXD T14
GPIO_S0_SC_57 / PCU_UART_TXD 0 = Enable

1
BC14 @
RC62 1 @ 2 USB_PLL_MON M13 GPIO_S0_SC_58 BF14 RC63 1 = Disable
USB_PLL_MON GPIO_S0_SC_59 BD16
0_0402_5% 10K_0402_5% Reference EDS Page 216
GPIO_S0_SC_60 BC16 DBG_UART_RXD T15
GPIO_S0_SC_61 / PCU_UART_RXD

2
B4
B5 USB_HSIC0_DATA BH12 HDA_SPKR
USB_HSIC0_STROBE ILB_8254_SPKR / GPIO_S0_SC_54 HDA_SPKR [19]

E2
D2 USB_HSIC1_DATA
NOTE: Ref checklist rev1.0 p.25 USB_HSIC1_STROBE BH22
USB_HSIC_RCOMP must NOT float if they are not being used. SIO_I2C0_DATA / GPIO_S0_SC_78 BG23
1 2 HSIC_RCOMP A7 SIO_I2C0_CLK / GPIO_S0_SC_79
RC64 45.3_0402_1% USB_HSIC_RCOMP
BG24
SIO_I2C1_DATA / GPIO_S0_SC_80 BH24
49.9_0402_1%1 2 RC65 LPC_RCOMP BF18 SIO_I2C1_CLK / GPIO_S0_SC_81
BH16 LPC_RCOMP / VGA_RCOMP
[20,21] LPC_AD0 BJ17 ILB_LPC_AD_0 / GPIO_S0_SC_42 BG25
[20,21] LPC_AD1 BJ13 ILB_LPC_AD_1 / GPIO_S0_SC_43 SIO_I2C2_DATA / GPIO_S0_SC_82 BJ25
ILB_LPC_CLK_0 : Output of 25MHz, [20,21] LPC_AD2 ILB_LPC_AD_2 / GPIO_S0_SC_44 SIO_I2C2_CLK / GPIO_S0_SC_83
Need Check with EC BG14
[20,21] LPC_AD3 BG17 ILB_LPC_AD_3 / GPIO_S0_SC_45
B [20,21] LPC_FRAME# ILB_LPC_FRAME# / GPIO_S0_SC_46 B
22_0402_5% 1 EMI@ 2 RC66 LPC_CLK_0 BG15 BG26
[20] LPC_CLK_EC ILB_LPC_CLK_0 / GPIO_S0_SC_47 SIO_I2C3_DATA / GPIO_S0_SC_84
ILB_LPC_CLK_1 is for CLK_0 feedback.(Input) 22_0402_5% 1 EMI@ 2 RC67 LPC_CLK_1 BH14 BH26
[21] LPC_CLK_TCM BG16 ILB_LPC_CLK_1 / GPIO_S0_SC_48 SIO_I2C3_CLK / GPIO_S0_SC_85
Set to Outpot for Normal Usage LPC_CLKRUN#
BG13 ILB_LPC_CLKRUN# / GPIO_S0_SC_49
[20,21] EC_SERIRQ ILB_LPC_SERIRQ / GPIO_S0_SC_50 BF27
SIO_I2C4_DATA / GPIO_S0_SC_86 BG27
SIO_I2C4_CLK / GPIO_S0_SC_87
+1.8VS +3VS
BH28 SOC_I2C0_DATA T16
PCU_SMB_DATA BG12 SIO_I2C5_DATA / GPIO_S0_SC_88 BG28 SOC_I2C0_CLK T17
PCU_SMB_DATA / GPIO_S0_SC_51 SIO_I2C5_CLK / GPIO_S0_SC_89
2

NTCM@ TCM@ PCU_SMB_CLK BH10


PCU_SMB_ALERT# BG11 PCU_SMB_CLK / GPIO_S0_SC_52
RC82 RC68 Check Intel for PU PCU_SMB_ALERT# / GPIO_S0_SC_53
8.2K_0402_5% 8.2K_0402_5% 2 1 LPC_CLK_0 BJ29
SIO_I2C6_DATA / GPIO_S0_SC_90 BG29
CC27 @EMI@
SIO_I2C6_CLK / GPIO_S0_SC_91 / SD3_WP
0705 : Reserved
10P_0402_50V8J
1

LPC_CLKRUN#
2 1 LPC_CLK_1 BH30 GPIO_S0_SC_92 T18
GPIO_S0_SC_092 BG30 GPIO_S0_SC_93
CC28 @EMI@
GPIO_S0_SC_093
T19 PDA (Platform Debug Assistant) Test Points
10P_0402_50V8J 6 OF 13

FH8065301546401_FCBGA131170 CPU@

+1.8VS +1.8VS
RPC9
5 4 PCU_SMB_CLK
6 3 PCU_SMB_DATA
7 2 PCU_SMB_ALERT#
8 1
A Pull High at EC side A
4.7K_0804_8P4R_5%
2
G

1 3 PCU_SMB_CLK
[13,20] EC_SMB_CK2
DDR(15,16) QC4
D

S
2
G

BSS138W-7-F_SOT323-3
Minicard(21)
1 3 PCU_SMB_DATA
EC(24) [13,20] EC_SMB_DA2
QC5
Compal Electronics, Inc.
D

BSS138W-7-F_SOT323-3 Security Classification Compal Secret Data


2014/11/07 2015/11/07 Title
Issued Date Deciphered Date VLV-M(5/8) USB/LPC/SMBus
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-C771P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, January 14, 2015 Sheet 9 of 34
5 4 3 2 1
5 4 3 2 1

For EVT measurement +1.35V


12A +SOC_VCC UC4G 20mil PJ1 JP@
AA27 AD38 DRAM_VDD_S4_CLK RC69 1 EMI@ 2 BLM15AX601SN1D
AA29 CORE_VCC_S0iX_AA27 DRAM_VDD_S4_AD38 AF38
AA30 CORE_VCC_S0iX_AA29 DRAM_VDD_S4_AF38 JUMP_43X118
D D
AC27 CORE_VCC_S0iX_AA30 A48 CC29 1 2 1U_0402_6.3V6K PJ2 JP@
CORE_VCC_S0iX_AC27 DRAM_VDD_S4_A48

MPZ2012S101AT000_2P 1U_0402_6.3V6K

MPZ2012S101AT000_2P 1U_0402_6.3V6K
AC29 AK38 CC30 1 2 .1U_0402_16V7K 2 2
CORE_VCC_S0iX_AC29 DRAM_VDD_S4_AK38

@EMI@

@EMI@
AC30 AM38
CORE_VCC_S0iX_AC30 DRAM_VDD_S4_AM38 AV41 JUMP_43X118
AD27 DRAM_VDD_S4_AV41 AV42
CORE_VCC_S0iX_AD27 DRAM_VDD_S4_AV42
1250mA
AD29 BB46 1 1

CC31

CC32
AD30 CORE_VCC_S0iX_AD29 DRAM_VDD_S4_BB46 BD49 +1.35V_SOC
AF27 CORE_VCC_S0iX_AD30 DRAM_VDD_S4_BD49 BD52
AF29 CORE_VCC_S0iX_AF27 DRAM_VDD_S4_BD52 BD53
CORE_VCC_S0iX_AF29 DRAM_VDD_S4_BD53

1
AG27 BF44 +1.35V_SOC
CORE_VCC_S0iX_AG27 DRAM_VDD_S4_BF44

@EMI@

@EMI@
AG29 BG51
AG30 CORE_VCC_S0iX_AG29 DRAM_VDD_S4_BG51 BJ48 CC33 2 1 2.2U_0402_6.3V6M
P26 CORE_VCC_S0iX_AG30 DRAM_VDD_S4_BJ48 C51 CC34 2 1 2.2U_0402_6.3V6M
P27 CORE_VCC_S0iX_P26 DRAM_VDD_S4_C51 D44 CC35 2 1 2.2U_0402_6.3V6M
U27 CORE_VCC_S0iX_P27 DRAM_VDD_S4_D44 F49 CC36 2 1 2.2U_0402_6.3V6M

2
CORE_VCC_S0iX_U27 DRAM_VDD_S4_F49

L1
U29 F52
CORE_VCC_S0iX_U29 DRAM_VDD_S4_F52

L2
V27 F53
V29 CORE_VCC_S0iX_V27 DRAM_VDD_S4_F53 H46
V30 CORE_VCC_S0iX_V29 DRAM_VDD_S4_H46 M41
Y27 CORE_VCC_S0iX_V30 DRAM_VDD_S4_M41 M42 CC37 1 2 10U_0603_6.3V6M
Y29 CORE_VCC_S0iX_Y27 DRAM_VDD_S4_M42 V38 CC38 1 2 10U_0603_6.3V6M
Y30 CORE_VCC_S0iX_Y29 DRAM_VDD_S4_V38 Y38
CORE_VCC_S0iX_Y30 DRAM_VDD_S4_Y38

T20 TP2_CORE_VCC_S0iX AA22


TP2_CORE_VCC_S0iX
C +1.35VS C
14A +SOC_VNN
420mA
AM22 AG18
AK32 UNCORE_VNN_S3_AM22 ICLK_V1P35_S3_F2_AG18 AJ19
AK30 UNCORE_VNN_S3_AK32 ICLK_V1P35_S3_F1_AJ19
AK29 UNCORE_VNN_S3_AK30
AK27 UNCORE_VNN_S3_AK29 BD1 VGA_V1P35_S3_F1 1 RS@ 2
AK25 UNCORE_VNN_S3_AK27 VGA_V1P35_S3_F1_BD1 RC70 0_0402_5%
AK24 UNCORE_VNN_S3_AK25
AK22 UNCORE_VNN_S3_AK24 CC39 1 2 10U_0603_6.3V6M
AJ24 UNCORE_VNN_S3_AK22 AD36 @
AJ22 UNCORE_VNN_S3_AJ24 DRAM_V1P35_S0iX_F1_AD36
+SOC_VNN +SOC_VCC AG24 UNCORE_VNN_S3_AJ22 AG32
AG22 UNCORE_VNN_S3_AG24 UNCORE_V1P35_S0iX_F2_AG32 V36
AF24 UNCORE_VNN_S3_AG22 UNCORE_V1P35_S0iX_F3_V36 U36
AF22 UNCORE_VNN_S3_AF24 UNCORE_V1P35_S0iX_F4_U36
UNCORE_VNN_S3_AF22
1

AD22 AA25
AC24 UNCORE_VNN_S3_AD22 UNCORE_V1P35_S0iX_F5_AA25
RC71 RC72 AC22 UNCORE_VNN_S3_AC24
100_0402_1% 100_0402_1% AA24 UNCORE_VNN_S3_AC22
AD24 UNCORE_VNN_S3_AA24
2

UNCORE_VNN_S3_AD24
AF19 CC40 1 2 10U_0603_6.3V6M
BB8 UNCORE_V1P35_S0iX_F6_AF19 AG19 CC41 1 2 1U_0402_6.3V6K
[32] VGFX_VSNS P28 UNCORE_VNN_SENSE UNCORE_V1P35_S0iX_F1_AG19 1 2
@ CC42 1U_0402_6.3V6K
[32] VCORE_VSNS CORE_VCC_SENSE_P28 7 OF 13
N28 CC43 1 2 1U_0402_6.3V6K
[32] VCORE_GSNS CORE_VSS_SENSE_N28 1 2
B CC44 1U_0402_6.3V6K B
1

CC45 1 2 1U_0402_6.3V6K
FH8065301546401_FCBGA131170 CPU@ CC46 1 2 1U_0402_6.3V6K
RC73 CC47 1 2 1U_0402_6.3V6K
100_0402_1% CC48 1 2 1U_0402_6.3V6K
CC49 1 2 1U_0402_6.3V6K
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


2014/11/07 2015/11/07 Title
Issued Date Deciphered Date VLV-M(6/8) Power1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-C771P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, January 14, 2015 Sheet 10 of 34
5 4 3 2 1
5 4 3 2 1

D D

Follow CRBv1.15
UC4H +1.05VS
+1.05VALW 325mA 1000mA
U22 AC32 +1.05VS_SOC RC75 1 RS@ 2 0_0402_5%
V22 UNCORE_V1P0_G3_U22 CORE_V1P0_S3_AC32 Y32
CC51 1 2 1U_0402_6.3V6K C5 UNCORE_V1P0_G3_V22 CORE_V1P0_S3_Y32
UNCORE_V1P0_G3 1uF*4 CC50 1 2 1U_0402_6.3V6K B6 UNCORE_V1P0_G3_C5 AA33
CC52 1 2 1U_0402_6.3V6K UNCORE_V1P0_G3_B6 CORE_V1P05_S3_AA33 AF33
CC53 1 2 1U_0402_6.3V6K Y19 CORE_V1P05_S3_AF33 AG33 CC54 1 2 0.47U_0402_6.3V6K
C3 USB3_V1P0_G3_Y19 CORE_V1P05_S3_AG33 AG35
USB3_V1P0_G3 0.01uF*1 CC55 1 2 0.01U_0402_16V7K USB3_V1P0_G3_C3 CORE_V1P05_S3_AG35 U33 CC56 1 2 1U_0402_6.3V6K
CORE_V1P05_S3_U33 U35 CC57 1 2 1U_0402_6.3V6K CORE_V1P05_S3 1uF*3
+1.05VS CORE_V1P05_S3_U35 V33 CC58 1 2 1U_0402_6.3V6K
2750mA CORE_V1P05_S3_V33
V32
1 RS@ 2 BJ6 SVID_V1P0_S3_V32 +1.8VALW
RC74 0_0402_5% AD35 VGA_V1P0_S3_BJ6
AF35 DRAM_V1P0_S0iX_AD35 U24
CC59 1 2 1U_0402_6.3V6K AF36 DRAM_V1P0_S0iX_AF35 UNCORE_V1P8_G3_U24 V25
CC60 1 2 1U_0402_6.3V6K AA36 DRAM_V1P0_S0iX_AF36 PCU_V1P8_G3_V25 N20 CC61 1 2 1U_0402_6.3V6K PMC_V1P8_G3 1uF*1
DRAM_V1P0_S0iX 1uF*4 1 2 AJ36 DRAM_V1P0_S0iX_AA36 USB_V1P8_G3_N20 U25
CC62 1U_0402_6.3V6K
DRAM_V1P0_S0iX_AJ36
65mA PMU_V1P8_G3_U25
CC63 1 2 1U_0402_6.3V6K AK35 AA18
AK36 DRAM_V1P0_S0iX_AK35 UNCORE_V1P8_G3_AA18
Y35 DRAM_V1P0_S0iX_AK36 +1.8VS
1 2 Y36 DRAM_V1P0_S0iX_Y35
CC64 1U_0402_6.3V6K
DRAM_V1P0_S0iX_Y36
10mA
CC65 1 2 1U_0402_6.3V6K AK19 AM30
C DDI_V1P0_S0iX 1uF*4 CC66 1 2 1U_0402_6.3V6K AK21 DDI_V1P0_S0iX_AK19 UNCORE_V1P8_S3_AM30 AN32 CC67 1 2 1U_0402_6.3V6K UNCORE_V1P8_S3 1uF*4 C

CC68 1 2 1U_0402_6.3V6K AJ18 DDI_V1P0_S0iX_AK21 UNCORE_V1P8_S3_AN32 U38 CC69 1 2 1U_0402_6.3V6K


AM16 DDI_V1P0_S0iX_AJ18 UNCORE_V1P8_S3_U38 CC70 1 2 1U_0402_6.3V6K
AN29 DDI_V1P0_S0iX_AM16 CC71 1 2 1U_0402_6.3V6K +1.8VS
AN30 VIS_V1P0_S0iX_AN29
VIS_V1P0_S0iX_AN30
58mA
CC72 1 2 10U_0603_6.3V6M V24 AM32
UNCORE_V1P0_S0iX 10uF*3 CC73 1 2 10U_0603_6.3V6M Y22 VIS_V1P0_S0iX_V24 HDA_V1P5_S3_AM32 CC74 1 2 1U_0402_6.3V6K HDA_LPE_V1P5V1P8_S3 1uF*1
1uF*2 CC75 1 2 10U_0603_6.3V6M Y24 VIS_V1P0_S0iX_Y22 +3VALW
CC76 1 2 1U_0402_6.3V6K AF16 VIS_V1P0_S0iX_Y24
CC77 1 2 1U_0402_6.3V6K AF18 UNCORE_V1P0_S3_AF16 N22 +3VALW_SOC 1 RS@ 2 For EVT measurement
UNCORE_V1P0_S3_AF18
Y18
UNCORE_V1P0_S3_Y18
50mA PCU_V3P3_G3_N22 RC76 0_0603_5%
PCIE_SATA_V1P0_S3 1uF*1 CC78 1 2 1U_0402_6.3V6K G1 N18 CC79 1 2 .1U_0402_16V7K USB_V3P3_G3 0.1uF*1
UNCORE_V1P0_S3 1uF*1 CC80 1 2 1U_0402_6.3V6K AK18 UNCORE_V1P0_S3_G1 USB_V3P3_G3_N18 P18 CC81 1 2 1U_0402_6.3V6K USB_ULPI_V1P8_S3 1uF*1
PCIE_V1P0_S3 1uF*1 CC82 1 2 1U_0402_6.3V6K AM18 PCIE_V1P0_S3_AK18 USB_V3P3_G3_P18 CC83 1 2 1U_0402_6.3V6K PCU_V3P3_G3 1uF*1
VGA_V1P0_S3 1uF*1 @ CC84 1 2 1U_0402_6.3V6K AM21 PCIE_V1P0_S3_AM18 +3VS
USB_V1P0_S3 0.1uF*1 1 2 AN21 PCIE_V1P0_S3_AM21
CC85 .1U_0402_16V7K
PCIE_V1P0_S3_AN21
33mA
USB3DEV_V1P0_S3 0.01uF*1 CC86 1 2 0.01U_0402_16V7K AN18 AN24 +3VS_SOC 1 RS@ 2 For EVT measurement VGA_V3P3_S3 1uF*1
GPIO_V1P0_S3 1uF*1 CC87 1 2 1U_0402_6.3V6K AN19 PCIE_SATA_V1P0_S3_AN18 VGA_V3P3_S3_AN24 RC77 0_0603_5%
SVID_V1P0_S3 1uF*1 CC88 1 2 1U_0402_6.3V6K AF21 SATA_V1P0_S3_AN19 AN27 CC89 1 2 .1U_0402_16V7K @ESD@
@ESD@ CC90 1 2 .1U_0402_16V7K AG21 UNCORE_V1P0_S0iX_AF21 SD3_V1P8V3P3_S3_AN27 CC91 1 2 1U_0402_6.3V6K @
@ESD@ CC92 1 2 .1U_0402_16V7K M14 UNCORE_V1P0_S0iX_AG21 AM27 +3VS
U18 USB_V1P0_S3_M14 LPC_V1P8V3P3_S3_AM27 +1.8VS
U19 USB_V1P0_S3_U18 +3VS_1.8VS_SOC RC78 1 TCM@ 2 0_0402_5%
AN25 USB_V1P0_S3_U19 RC79 1 2 0_0402_5%
GPIO_V1P0_S3_AN25
35mA
V18 NTCM@
USB_HSIC_V1P2_G3_V18 +1.05VALW
B B
F1 AD16 CC93 1 2 1U_0402_6.3V6K USB_HSIC_V1P2_G3 1uF*1
RESERVED_F1 VSS_AD16 AD18 @
TP_CORE_V1P05_S4 AF30 VSS_AD18
T21
TP_CORE_V1P05_S4_AF30
Pop when use +1.2VALW
Disable HSIC
8 OF 13 If the USB HSIC is not used, pin V18 can be connected
FH8065301546401_FCBGA131170 CPU@
to either +V1P2A or +V1P0A.

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


2014/11/07 2015/11/07 Title
Issued Date Deciphered Date VLV-M(7/8) Power2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-C771P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, January 14, 2015 Sheet 11 of 34
5 4 3 2 1
5 4 3 2 1

D D

UC4I UC4J UC4K UC4L UC4M

A11 AC36 AG38 AH47 AT24 AY36 BF30 E8 K9 U3


A15 VSS_A11 VSS_AC36 AC38 AH4 VSS_AG38 VSS_AH47 AH48 AT27 VSS_AT24 VSS_AY36 AY4 BF36 VSS_BF30 VSS_E8 F19 L13 VSS_K9 VSS_U3 U30
A19 VSS_A15 VSS_AC38 AD19 AH41 VSS_AH4 VSS_AH48 AH50 AT30 VSS_AT27 VSS_AY4 AY50 BF4 VSS_BF36 VSS_F19 F2 L19 VSS_L13 VSS_U30 U32
A23 VSS_A19 VSS_AD19 AD21 AH45 VSS_AH41 VSS_AH50 AH51 AT35 VSS_AT30 VSS_AY50 AY9 BG31 VSS_BF4 VSS_F2 F24 L27 VSS_L19 VSS_U32 U40
A27 VSS_A23 VSS_AD21 AD25 AH7 VSS_AH45 VSS_AH51 AH6 AT38 VSS_AT35 VSS_AY9 BA14 BG34 VSS_BG31 VSS_F24 F27 L35 VSS_L27 VSS_U40 U42
A31 VSS_A27 VSS_AD25 AD32 AH9 VSS_AH7 VSS_AH6 AM44 AT4 VSS_AT38 VSS_BA14 BA19 BG39 VSS_BG34 VSS_F27 F30 M19 VSS_L35 VSS_U42 U43
A35 VSS_A31 VSS_AD32 AD33 AJ1 VSS_AH9 VSS_AM44 AM51 AT47 VSS_AT4 VSS_BA19 BA22 BG42 VSS_BG39 VSS_F30 F35 M26 VSS_M19 VSS_U43 U45
A39 VSS_A35 VSS_AD33 AD47 AJ16 VSS_AJ1 VSS_AM51 AM7 AT52 VSS_AT47 VSS_BA22 BA27 BG45 VSS_BG42 VSS_F35 F5 M27 VSS_M26 VSS_U45 U46
A43 VSS_A39 VSS_AD47 AD7 AJ21 VSS_AJ16 VSS_AM7 AN1 AU1 VSS_AT52 VSS_BA27 BA32 BG49 VSS_BG45 VSS_F5 F7 M34 VSS_M27 VSS_U46 U48
A47 VSS_A43 VSS_AD7 AE1 AJ25 VSS_AJ21 VSS_AN1 AN11 AU24 VSS_AU1 VSS_BA32 BA35 BJ11 VSS_BG49 VSS_F7 G10 M35 VSS_M34 VSS_U48 U49
AA1 VSS_A47 VSS_AE1 AE11 AJ27 VSS_AJ25 VSS_AN11 AN12 AU3 VSS_AU24 VSS_BA35 BA40 BJ15 VSS_BJ11 VSS_G10 G20 M38 VSS_M35 VSS_U49 U5
AA16 VSS_AA1 VSS_AE11 AE12 AJ29 VSS_AJ27 VSS_AN12 AN14 AU30 VSS_AU3 VSS_BA40 BA53 BJ19 VSS_BJ15 VSS_G20 G22 M47 VSS_M38 VSS_U5 U51
AA19 VSS_AA16 VSS_AE12 AE14 AJ3 VSS_AJ29 VSS_AN14 AN22 AU38 VSS_AU30 VSS_BA53 BB19 BJ23 VSS_BJ19 VSS_G22 G26 M51 VSS_M47 VSS_U51 U53
AA21 VSS_AA19 VSS_AE14 AE3 AJ30 VSS_AJ3 VSS_AN22 AN3 AU51 VSS_AU38 VSS_BB19 BB27 BJ27 VSS_BJ23 VSS_G26 G28 N1 VSS_M51 VSS_U53 U6
AA3 VSS_AA21 VSS_AE3 AE4 AJ32 VSS_AJ30 VSS_AN3 AN33 AV12 VSS_AU51 VSS_BB27 BB35 BJ31 VSS_BJ27 VSS_G28 G32 N16 VSS_N1 VSS_U6 U8
C
AA32 VSS_AA3 VSS_AE4 AE40 AJ33 VSS_AJ32 VSS_AN33 AN35 AV13 VSS_AV12 VSS_BB35 BC20 BJ35 VSS_BJ31 VSS_G32 G34 N38 VSS_N16 VSS_U8 U9 C
AA35 VSS_AA32 VSS_AE40 AE42 AJ35 VSS_AJ33 VSS_AN35 AN36 AV14 VSS_AV13 VSS_BC20 BC22 BJ39 VSS_BJ35 VSS_G34 G42 N51 VSS_N38 VSS_U9 V12
AA38 VSS_AA35 VSS_AE42 AE43 AJ38 VSS_AJ35 VSS_AN36 AN38 AV18 VSS_AV14 VSS_BC22 BC26 BJ43 VSS_BJ39 VSS_G42 H19 P13 VSS_N51 VSS_V12 V16
AA53 VSS_AA38 VSS_AE43 AE45 AJ53 VSS_AJ38 VSS_AN38 AN40 AV19 VSS_AV18 VSS_BC26 BC28 BJ47 VSS_BJ43 VSS_H19 H27 P16 VSS_P13 VSS_V16 V19
AB10 VSS_AA53 VSS_AE45 AE46 AK10 VSS_AJ53 VSS_AN40 AN42 AV24 VSS_AV19 VSS_BC28 BC32 BJ7 VSS_BJ47 VSS_H27 H35 P19 VSS_P16 VSS_V19 V21
AB4 VSS_AB10 VSS_AE46 AE48 AK14 VSS_AK10 VSS_AN42 AN43 AV27 VSS_AV24 VSS_BC32 BC34 C14 VSS_BJ7 VSS_H35 J1 P20 VSS_P19 VSS_V21 V35
AB41 VSS_AB4 VSS_AE48 AE50 AK16 VSS_AK14 VSS_AN43 AN45 AV30 VSS_AV27 VSS_BC34 BC42 C31 VSS_C14 VSS_J1 J16 P24 VSS_P20 VSS_V35 V40
AB45 VSS_AB41 VSS_AE50 AE51 AK33 VSS_AK16 VSS_AN45 AN46 AV35 VSS_AV30 VSS_BC42 BD19 C34 VSS_C31 VSS_J16 J19 P32 VSS_P24 VSS_V40 V44
AB47 VSS_AB45 VSS_AE51 AE53 AK41 VSS_AK33 VSS_AN46 AN48 AV38 VSS_AV35 VSS_BD19 BD24 C39 VSS_C34 VSS_J19 J22 P35 VSS_P32 VSS_V44 V51
AB48 VSS_AB47 VSS_AE53 AE6 AK44 VSS_AK41 VSS_AN48 AN49 AV47 VSS_AV38 VSS_BD24 BD27 C42 VSS_C39 VSS_J22 J27 P38 VSS_P35 VSS_V51 V7
AB50 VSS_AB48 VSS_AE6 AE8 AM12 VSS_AK44 VSS_AN49 AN5 AV51 VSS_AV47 VSS_BD27 BD30 C45 VSS_C42 VSS_J27 J32 P4 VSS_P38 VSS_V7 Y10
AB51 VSS_AB50 VSS_AE8 AE9 AM19 VSS_AM12 VSS_AN5 AN51 AV7 VSS_AV51 VSS_BD30 BD35 C49 VSS_C45 VSS_J32 J35 P47 VSS_P4 VSS_Y10 Y14
AB6 VSS_AB51 VSS_AE9 AF10 AM24 VSS_AM19 VSS_AN51 AN53 AW13 VSS_AV7 VSS_BD35 BE19 D12 VSS_C49 VSS_J35 J40 P52 VSS_P47 VSS_Y14 Y16
AC16 VSS_AB6 VSS_AF10 AF12 AM25 VSS_AM24 VSS_AN53 AN6 AW19 VSS_AW13 VSS_BE19 BE2 D16 VSS_D12 VSS_J40 J53 P9 VSS_P52 VSS_Y16 Y21
AC18 VSS_AC16 VSS_AF12 AF25 AM29 VSS_AM25 VSS_AN6 AN8 AW27 VSS_AW19 VSS_BE2 BE35 D24 VSS_D16 VSS_J53 K14 T40 VSS_P9 VSS_Y21 Y25
AC19 VSS_AC18 VSS_AF25 AF32 AM33 VSS_AM29 VSS_AN8 AN9 AW3 VSS_AW27 VSS_BE35 BE8 D30 VSS_D24 VSS_K14 K22 U1 VSS_T40 VSS_Y25 Y33
AC21 VSS_AC19 VSS_AF32 AF47 AM35 VSS_AM33 VSS_AN9 AP40 AW35 VSS_AW3 VSS_BE8 BF12 D36 VSS_D30 VSS_K22 K32 U11 VSS_U1 VSS_Y33 Y41
AC25 VSS_AC21 VSS_AF47 AG16 AM36 VSS_AM35 VSS_AP40 AT12 AY10 VSS_AW35 VSS_BF12 BF16 D38 VSS_D36 VSS_K32 K36 U12 VSS_U11 VSS_Y41 Y44
AC33 VSS_AC25 VSS_AG16 AG25 AM40 VSS_AM36 VSS_AT12 AT16 AY22 VSS_AY10 VSS_BF16 BF24 E19 VSS_D38 VSS_K36 K4 U14 VSS_U12 VSS_Y44 Y7
AC35 VSS_AC33 VSS_AG25 AG36 M28 VSS_AM40 VSS_AT16 AT19 AY32 VSS_AY22 VSS_BF24 BF38 E35 VSS_E19 VSS_K4 K50 U21 VSS_U14 VSS_Y7 Y9
B2 VSS_AC35 9 OF 13VSS_AG36 B52 VSS_M28 10 OF 13 VSS_AT19 VSS_AY32 11 OF 13
VSS_BF38 VSS_E35 12 OF 13 VSS_K50 VSS_U21 13 OF 13 VSS_Y9
A6 VSS_B2 VSS_B52 B53
A52 VSS_A6 VSS_B53 BE1 FH8065301546401_FCBGA131170 FH8065301546401_FCBGA131170 FH8065301546401_FCBGA131170 FH8065301546401_FCBGA131170
A51 VSS_A52 VSS_BE1 BE53
A5 VSS_A51 VSS_BE53 BG1
VSS_A5 VSS_BG1 CPU@ CPU@ CPU@ CPU@
A49 BJ2
A3 VSS_A49 VSS_BJ2 BJ3
B B
BH53 VSS_A3 VSS_BJ3 BJ5
BH52 VSS_BH53 VSS_BJ5 BJ49
BH2 VSS_BH52 VSS_BJ49 BJ51
BH1 VSS_BH2 VSS_BJ51 BJ52
BG53 VSS_BH1 VSS_BJ52 C1
E53 VSS_BG53 VSS_C1 C53
VSS_E53 VSS_C53 E1
VSS_E1
U16
AN16 USB_VSSA_U16
VSSA_AN16

FH8065301546401_FCBGA131170

CPU@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


2014/11/07 2015/11/07 Title
Issued Date Deciphered Date VLV-M(8/8) GND
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-C771P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, January 14, 2015 Sheet 12 of 34
5 4 3 2 1
A B C D E

+DDR_A_VREF_DQ +1.35V +1.35V Signal voltage level = 0.675 V


JDIMM1 PLACE TWO 4.7K RESISTORS CLOSE TO
1 2
3 VREF_DQ VSS1 4 DDR_A_D4 DIMMS ON DIMM_VREF_CA / DIMM_VREF_DQ
5 VSS2 DQ4 6 DDR_A_DQS#[0..7] [5] Decoupling caps are needed; one 0.1 µF placed close to VREF pins of each DDR3 SODIMM.
DDR_A_D0 DDR_A_D5
DDR_A_D1 7 DQ0 DQ5 8
9 DQ1 VSS3 10 DDR_A_DQS[0..7] [5]
DDR_A_DQS#0
DDR_A_DM0 11 VSS4 DQS#0 12 DDR_A_DQS0
13 DM0 DQS0 14 DDR_A_D[0..63] [5]
DDR_A_D2 15 VSS5 VSS6 16 DDR_A_D6 +1.35V +DDR_A_VREF_DQ
17 DQ2 DQ6 18 DDR_A_MA[0..15] [5]
DDR_A_D3 DDR_A_D7
19 DQ3 DQ7 20 1 2
21 VSS7 VSS8 22 DDR_A_DM[0..7] [5]
DDR_A_D8 DDR_A_D12 RD1
DDR_A_D9 23 DQ8 DQ12 24 DDR_A_D13 4.7K_0402_1%
DQ9 DQ13 1
25 26 1 2
DDR_A_DQS#1 27 VSS9 VSS10 28 DDR_A_DM1 RD2 CD1
1 DQS#1 DM1 1
DDR_A_DQS1 29 30 DDR_A_RST# [5] 4.7K_0402_1% .1U_0402_16V7K
31 DQS1 RESET# 32 2
DDR_A_D10 33 VSS11 VSS12 34 DDR_A_D14
DDR_A_D11 35 DQ10 DQ14 36 DDR_A_D15
37 DQ11 DQ15 38
DDR_A_D16 39 VSS13 VSS14 40 DDR_A_D20 ESD@
DDR_A_D17 41 DQ16 DQ20 42 DDR_A_D21 DDR_A_RST# 1 2 +1.35V +DDR_A_VREF_CA
43 DQ17 DQ21 44 CD2
DDR_A_DQS#2 45 VSS15 VSS16 46 DDR_A_DM2 100P_0402_50V8J 1 2
DDR_A_DQS2 47 DQS#2 DM2 48 RD3
49 DQS2 VSS17 50 DDR_A_D22 4.7K_0402_1%
VSS18 DQ22 1
DDR_A_D18 51 52 DDR_A_D23 1 2
DDR_A_D19 53 DQ18 DQ23 54 RD4 CD3
55 DQ19 VSS19 56 DDR_A_D28 4.7K_0402_1%
All VREF traces should DDR_A_D24 57 VSS20 DQ28 58 DDR_A_D29 FOR EMI/ESD Require 01/15 2
.1U_0402_16V7K
Layout Note: have 10 mil trace width DDR_A_D25 59 DQ24 DQ29 60
Place near JDIMM1 61 DQ25 VSS21 62 DDR_A_DQS#3
DDR_A_DM3 63 VSS22 DQS#3 64 DDR_A_DQS3
65 DM3 DQS3 66
DDR_A_D26 67 VSS23 VSS24 68 DDR_A_D30
+1.35V DDR_A_D27 69 DQ26 DQ30 70 DDR_A_D31
71 DQ27 DQ31 72
CD4 1 2 10U_0603_6.3V6M VSS25 VSS26
CD5 1 2 10U_0603_6.3V6M
CD6 1 2 10U_0603_6.3V6M
CD7 1 2 10U_0603_6.3V6M 73 74
[5] DDR_A_CKE0 CKE0 CKE1 DDR_A_CKE2 [5]
75 76
77 VDD1 VDD2 78 DDR_A_MA15
79 NC1 A15 80 DDR_A_MA14
[5] DDR_A_BS2 BA2 A14
81 82
DDR_A_MA12 83 VDD3 VDD4 84 DDR_A_MA11
CD8 1 2 .1U_0402_16V7K DDR_A_MA9 85 A12/BC# A11 86 DDR_A_MA7
CD9 1 2 .1U_0402_16V7K 87 A9 A7 88
CD10 1 2 .1U_0402_16V7K DDR_A_MA8 89 VDD5 VDD6 90 DDR_A_MA6
CD11 1 2 .1U_0402_16V7K DDR_A_MA5 91 A8 A6 92 DDR_A_MA4
2 A5 A4 2
CD12 1 2 .1U_0402_16V7K 93 94
CD13 1 2 .1U_0402_16V7K DDR_A_MA3 95 VDD7 VDD8 96 DDR_A_MA2
CD14 1 2 .1U_0402_16V7K DDR_A_MA1 97 A3 A2 98 DDR_A_MA0
CD15 1 2 .1U_0402_16V7K 99 A1 A0 100
101 VDD9 VDD10 102
[5] DDR_A_CLK0 CK0 CK1 DDR_A_CLK2 [5]
103 104
[5] DDR_A_CLK0# CK0# CK1# DDR_A_CLK2# [5]
105 106
DDR_A_MA10 107 VDD11 VDD12 108
A10/AP BA1 DDR_A_BS1 [5]
109 110
[5] DDR_A_BS0 BA0 RAS# DDR_A_RAS# [5]
0604 Change for layout space limit 111 112
113 VDD13 VDD14 114
[5] DDR_A_WE# WE# S0# DDR_A_CS0# [5]
115 116
[5] DDR_A_CAS# CAS# ODT0 DDR_A_ODT0 [5]
117 118
DDR_A_MA13 119 VDD15 VDD16 120
121 A13 ODT1 122 DDR_A_ODT2 [5]
[5] DDR_A_CS2# S1# NC2
123 124
125 VDD17 VDD18 126
NCTEST VREF_CA +DDR_A_VREF_CA
127 128
DDR_A_D32 129 VSS27 VSS28 130 DDR_A_D36
DDR_A_D33 131 DQ32 DQ36 132 DDR_A_D37
133 DQ33 DQ37 134
DDR_A_DQS#4 135 VSS29 VSS30 136 DDR_A_DM4
DDR_A_DQS4 137 DQS#4 DM4 138
139 DQS4 VSS31 140 DDR_A_D38
DDR_A_D34 141 VSS32 DQ38 142 DDR_A_D39
DDR_A_D35 143 DQ34 DQ39 144
145 DQ35 VSS33 146 DDR_A_D44
DDR_A_D40 147 VSS34 DQ44 148 DDR_A_D45
DDR_A_D41 149 DQ40 DQ45 150
151 DQ41 VSS35 152 DDR_A_DQS#5
DDR_A_DM5 153 VSS36 DQS#5 154 DDR_A_DQS5
155 DM5 DQS5 156
DDR_A_D42 157 VSS37 VSS38 158 DDR_A_D46
DDR_A_D43 159 DQ42 DQ46 160 DDR_A_D47
+0.675VS 161 DQ43 DQ47 162
3 VSS39 VSS40 3
DDR_A_D48 163 164 DDR_A_D52
CD16 1 2 10U_0603_6.3V6M DDR_A_D49 165 DQ48 DQ52 166 DDR_A_D53
167 DQ49 DQ53 168
DDR_A_DQS#6 169 VSS41 VSS42 170 DDR_A_DM6
CD17 1 2 1U_0402_6.3V6K DDR_A_DQS6 171 DQS#6 DM6 172
CD18@1 2 1U_0402_6.3V6K 173 DQS6 VSS43 174 DDR_A_D54
DDR_A_D50 175 VSS44 DQ54 176 DDR_A_D55
DDR_A_D51 177 DQ50 DQ55 178
179 DQ51 VSS45 180 DDR_A_D60
DDR_A_D56 181 VSS46 DQ60 182 DDR_A_D61
DDR_A_D57 183 DQ56 DQ61 184
185 DQ57 VSS47 186 DDR_A_DQS#7
DDR_A_DM7 187 VSS48 DQS#7 188 DDR_A_DQS7
189 DM7 DQS7 190
DDR_A_D58 191 VSS49 VSS50 192 DDR_A_D62
DDR_A_D59 193 DQ58 DQ62 194 DDR_A_D63
Layout Note: 195 DQ59 DQ63 196
Place near JDIMM1.203,204 197 VSS51 VSS52 198
199 SA0 EVENT# 200
+3VS VDDSPD SDA EC_SMB_DA2 [20,9]
201 202
203 SA1 SCL 204 EC_SMB_CK2 [20,9]
+0.675VS VTT1 VTT2 +0.675VS
205 206
G1 G2
1
LCN_DAN06-K4406-0102
2

CD19 ME@
.1U_0402_16V7K RD5 RD6
2 0_0402_5%
RS@
0_0402_5%
RS@
SP07000LB00 Channel A
1

<Address: SA1:SA0=00 (A0H)>


4
DIMM_1 STD H:4mm 4

Security Classification Compal Secret Data Compal Electronics, Inc.


2014/11/07 2015/11/07 Title
Issued Date Deciphered Date DDR3L DIMMA
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-C771P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, January 14, 2015 Sheet 13 of 34
A B C D E
A B C D E

LCD POWER CIRCUIT


+3VS
+LCDVDD
W=60mils UX1
W=60mils
5 1
IN OUT
2 1
GND
1 1 4 3 CX1 1
EN OC 4.7U_0603_6.3V6K
CX2 SY6288C20AAC_SOT23-5 2
1U_0402_6.3V6K
2

eDP PANEL Conn.


[6] ENVDD

1 RS@ 2 +3VS_CMOS
[20] EC_ENVDD
RX1 0_0402_5% JEDP1
1 2 USB20_N2_R
3 1 2 4 USB20_P2_R
5 3 4 6
CX3 1 2 .1U_0402_16V7K EDP_AUXN_C 7 5 6 8
[6] EDP_AUXN 7 8 INVT_PWM_SOC [6]
CX4 1 2 .1U_0402_16V7K EDP_AUXP_C 9 10 DISPOFF#
[6] EDP_AUXP 9 10
11 12 EDP_HPD_CONN
CX5 1 2 .1U_0402_16V7K EDP_TXP0_C 13 11 12 14 +3VS
[6] EDP_TXP0 1 2 .1U_0402_16V7K 15 13 14 16
CX6 EDP_TXN0_C
[6] EDP_TXN0 17 15 16 18 +LCDVDD
1 2 .1U_0402_16V7K EDP_TXP1_C 19 17 18 20
W=60mils
CX7
+LCDVDD [6] EDP_TXP1 1 2 .1U_0402_16V7K 21 19 20 22
CX8 EDP_TXN1_C
[6] EDP_TXN1 23 21 22 24
25 23 24 26 +INVPWR_B+
25 26

1
27 28 W=60mils
+1.8VS @ 29 27 28 30
RX2 29 30
31 32

33P_0402_50V8K

33P_0402_50V8K
100K_0402_5%
GND GND
1

2 2
2

@EMI@

@EMI@
EDP_AUXN_C ACES_87242-3001-09_30P

CX14

CX15
RX3 EDP_AUXP_C ME@
2 10K_0402_5% 2
1

1 1
2

@ SP02000NB00
[6] EDP_HPD#
RX4
1

100K_0402_5%
D
2

QX1 2 EDP_HPD_CONN
2N7002K_SOT23-3 G
1

S
3

RX5 Intel recommends having a pull-up


100K_0402_5% resistor of 100 kΩ for AUXN and a
pull-down resistor of 100 kΩ for AUXP
2

between the AC capacitor and the


connector, to assist source detection
by the sink device.

+INVPWR_B+ B+

RX6 1 @ 2 0_0402_5% DISPOFF# W=60mils W=60mils


Camera [6] BKOFF#
RX9

2
+3VS +3VS_CMOS RX7 1 RS@ 2 0_0402_5%
[20] EC_BKOFF# 1 RS@ 2
RX8
100K_0402_1%
CMOS@ 1 0_0805_5%
QX2 @ SM010014520 3000ma
1U_0402_6.3V6K

1
DMG2301U-7 1P SOT23-3 CX9
2 RX10 W=20mils 220ohm@100mhz
CX10

@ESD@

W=20mils 4.7U_0805_25V6-K
3 1 1 RS@ 2 2 DCR 0.04
S

+3VS_R_CMOS
3 1 1 3
1 CMOS@ 0_0603_5%
CX11 CX12 @
G
2

.1U_0402_16V7K 10U_0603_6.3V6M
RX11 2 2
150K_0402_5%
4.7V
[20] CMOS_ON#
CMOS@ 1
CX13 CMOS@
.1U_0402_16V7K
2

RX12 1 RS@ 2 0_0402_5%

LX1 @CMOS_EMI@
1 2 USB20_P2_R
[9] USB20_P2

Camera 4 3 USB20_N2_R
[9] USB20_N2
HCM1012GH900BP_4P

RX13 1 RS@ 2 0_0402_5%


4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


2014/11/07 2015/11/07 Title
Issued Date Deciphered Date eDP CONN.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-C771P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, January 14, 2015 Sheet 14 of 34
A B C D E
A B C D E

Near HDMI CONN +1.8VS

1
+5VS +HDMI_5V_OUT
[6] HDMI_TX1- CY1 2 1 .1U_0402_16V7K HDMI_C_TX1- RY1 1 2 619_0402_1% W=40mils RY2
CY2 2 1 .1U_0402_16V7K HDMI_C_TX1+ RY3 1 2 619_0402_1% 10K_0402_5%
[6] HDMI_TX1+
CY3 2 1 .1U_0402_16V7K HDMI_C_TX2- RY4 1 2 619_0402_1%
[6] HDMI_TX2-
CY4 2 1 .1U_0402_16V7K HDMI_C_TX2+ RY5 1 2 619_0402_1%
[6] HDMI_TX2+ UY1

2
HDMI_GND
[6] HDMI_HPD#
[6] HDMI_TX0- CY5 2 1 .1U_0402_16V7K HDMI_C_TX0- RY6 1 2 619_0402_1%

6
1 [6] HDMI_TX0+ CY6 2 1 .1U_0402_16V7K HDMI_C_TX0+ RY8 1 2 619_0402_1% 3 1
CY7 2 1 .1U_0402_16V7K HDMI_C_CLK- RY7 1 2 619_0402_1% OUT QY1B
D
2 HDMI_HPD
1
G
[6] HDMI_CLK-
CY8 2 1 .1U_0402_16V7K HDMI_C_CLK+ RY9 1 2 619_0402_1% 1 DMN66D0LDW-7_SOT363-6
[6] HDMI_CLK+
S
IN

1
CY9

1
2 .1U_0402_16V7K RY10
GND 2
100K_0402_5%

3
5
D

+3VS
G QY1A AP2330W-7_SC59-3

2
S DMN66D0LDW-7_SOT363-6

4
RY11 1 EMI@ 2 8.2_0402_1% HDMI_R_CK+

LY1 @EMI@

2
HDMI_C_CLK+ 1 2
RY12
150_0402_5%
HDMI_C_CLK- 4 3
+1.8VS EMI@ HDMI connector
RPY1

1
2 HCM1012GH900BP_4P 2
HDMI_DDCDATA 5 4 +HDMI_5V_OUT RY13 1 EMI@ 2 8.2_0402_1% HDMI_R_CK- +HDMI_5V_OUT
HDMI_DDCCLK 6 3
HDMI_SDATA 7 2 JHDMI1
HDMI_SCLK 8 1 HDMI_HPD 19
RY14 1 EMI@ 2 8.2_0402_1% HDMI_R_D0+ 18 HP_DET
2.2K_0804_8P4R_5% 17 +5V
LY2 @EMI@ HDMI_SDATA 16 DDC/CEC_GND

CY10

CY11
HDMI_C_TX0+ 4 3 HDMI_SCLK 15 SDA
2 2 SCL

@EMI@

@EMI@
14
RY15 13 Reserved
HDMI_C_TX0- 1 2 HDMI_R_CK- 12 CEC 20

.1U_0402_16V7K

.1U_0402_16V7K
150_0402_5% CK- GND
+1.8VS 1 1 11 21
EMI@ CK_shield GND
HCM1012GH900BP_4P HDMI_R_CK+ 10 22

1
RY16 1 EMI@ 2 8.2_0402_1% HDMI_R_D0- 9 CK+ GND 23
HDMI_R_D0- 8 D0- GND
.1U_0402_16V7K

HDMI_R_D0+ 7 D0_shield
ESD@ CY12

1 D0+
HDMI_R_D1- 6
RY17 1 EMI@ 2 8.2_0402_1% HDMI_R_D1+ 5 D1-
HDMI_R_D1+ 4 D1_shield
2 LY3 @EMI@ HDMI_R_D2- 3 D1+
D2-
2

2
G

HDMI_C_TX1+ 1 2 2
RY18 HDMI_R_D2+ 1 D2_shield
3 1 HDMI_SCLK D2+
[6] HDMI_DDCCLK 150_0402_5%
QY2 HDMI_C_TX1- 4 3
S

EMI@ LOTES_AHDM0006-P004A_19P
2
G

BSS138W-7-F_SOT323-3 ME@

1
HCM1012GH900BP_4P
3 1 HDMI_SDATA RY19 1 EMI@ 2 8.2_0402_1% HDMI_R_D1-
[6] HDMI_DDCDATA DC232002A00
QY3
S

BSS138W-7-F_SOT323-3
HDMI_R_D2+
RY20 1 EMI@ 2 8.2_0402_1%

2
LY4 @EMI@
HDMI_C_TX2+ 4 3 RY21
3 150_0402_5% 3
EMI@
HDMI_C_TX2- 1 2

1
HCM1012GH900BP_4P
RY22 1 EMI@ 2 8.2_0402_1% HDMI_R_D2-

ESD
@ESD@ DY1 @ESD@ DY2 @ESD@ DY3
HDMI_SDATA 9 10 1 1 HDMI_SDATA HDMI_R_CK+ 9 10 1 1 HDMI_R_CK+ HDMI_R_D0- 9 10 1 1 HDMI_R_D0-

HDMI_SCLK 8 9 2 2 HDMI_SCLK HDMI_R_CK- 8 9 2 2 HDMI_R_CK- HDMI_R_D0+ 8 9 2 2 HDMI_R_D0+

HDMI_HPD 7 7 4 4 HDMI_HPD HDMI_R_D1+ 7 7 4 4 HDMI_R_D1+ HDMI_R_D2- 7 7 4 4 HDMI_R_D2-

6 6 5 5 HDMI_R_D1- 6 6 5 5 HDMI_R_D1- HDMI_R_D2+ 6 6 5 5 HDMI_R_D2+

3 3 3 3 3 3

8 8 8

4 L05ESDL5V0NA-4_SLP2510P8-10-9 L05ESDL5V0NA-4_SLP2510P8-10-9 L05ESDL5V0NA-4_SLP2510P8-10-9 4

Security Classification Compal Secret Data Compal Electronics, Inc.


2014/11/07 2015/11/07 Title
Issued Date Deciphered Date HDMI CONN.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-C771P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, January 14, 2015 Sheet 15 of 34
A B C D E
5 4 3 2 1

RJ-45 CONN.
+3VALW +3V_LAN

W=60mil RS@
D RL1 1 2 0_0603_5% D
W=60mil JLAN1 ME@
2 RJ45_TX0+ 1
PR1+
CL1 RJ45_TX0- 2
1U_0402_6.3V6K +LAN_VDD +3VS PR1-
1 RJ45_RX1+ 3
PR2+

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

1
4
RL2 PR3+

1U_0402_6.3V6K
1 1 1 1 1
1K_0402_5% 5
PR3-

CL6
CL2 CL3 CL4 CL5
RJ45_RX1- 6

2
2 2 2 2 2 ISOLATE# PR2-
7 9
PR4+ GND 10
8 GND
RL3 PR4-
15K_0402_5% SANTA_130452-S
Close to Pin3, Pin8, Pin22, Pin30, Pin22 DC234005N10

Rising time (10%~90%) 要>1mS and <100mS LANGND

+3V_LAN
0.1U_0402_16V7K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
0.1U_0402_16V7K

1 1 1 1
@ @
CL7 CL8 CL9 CL10
2 2 2 2 UL1 These components close to Pin 17, 18
C C
+LAN_VDD +LAN_VDD

+3V_LAN

W=60mils 1 2PCIE_GTX_C_ARX_P0
PCIE_GTX_C_ARX_P0 [7]
LAN_MDIP0 1 17 PCIE_PRX_DTX_P0_C CL11 0.1U_0402_16V7K
LAN_MDIN0 2 MDIP0 HSOP 18 PCIE_PRX_DTX_N0_C 1 2PCIE_GTX_C_ARX_N0
MDIN0 HSON PCIE_GTX_C_ARX_N0 [7]
CL7 close to Pin 11 3 19 PLT_RST_BUF# CL12 0.1U_0402_16V7K
LAN_MDIP1 4 AVDD10 PERSTB 20 ISOLATE# PLT_RST_BUF# [17,18,20,21,8]
LAN_MDIN1 5 MDIP1 ISOLATEB 21 PCIE_LAN_WAKE#
CL8 close to Pin 32 6 MDIN1 LANWAKEB 22 PCIE_LAN_WAKE# [18,20]
7 MDIP2 DVDD10 23
+3V_LAN 8 MDIN2 VDDREG 24 +3V_LAN
9 AVDD10 REGOUT 25 TPL1@
10 MDIP3 LED2 26 LED1_GPIO 1 @ 2
11 MDIN3 LED1/GPIO 27 RL4 10K_0402_5%
LAN_CLKREQ# 12 AVDD33 LED0 28 XTLO TPL2@
[7] LAN_CLKREQ# PCIE_ATX_C_GRX_P0 13 CLKREQB CKXTAL1 29 XTLI RL5 1 RS@ 2 0_0402_5% LANGND
[7] PCIE_ATX_C_GRX_P0 PCIE_ATX_C_GRX_N0 14 HSIP CKXTAL2 30
[7] PCIE_ATX_C_GRX_N0 CLK_PCIE_LAN 15 HSIN AVDD10 31 2.49K_0402_1% 2 1 RL6 RL7 1 RS@ 2 0_0402_5%
[8] CLK_PCIE_LAN CLK_PCIE_LAN# 16 REFCLK_P RSET 32
[8] CLK_PCIE_LAN# REFCLK_N AVDD33 33
GND reserved GPIO pin
LANGND

RTL8107E-CG QFN 32P E-LAN CTRL


SA000086300

B TL1 B

LAN_MDIN1 1 16 RJ45_RX1-
CL13 2 RD+ RX+ 15
LAN_MDIP1 RJ45_RX1+ RL8 CL14
1 2

10P_0402_50V8J
XTLO
ESD 3
4
5
RD-
RDCT
NC
RX-
RXCT
NC
14
13
12
1

75_0805_5%
2 1 2

10P_0603_50V
LANGND

6 NC NC 11 2 1
TDCT TXCT
1

LAN_MDIN0 7 10 RJ45_TX0-
YL1 @ESD@ LAN_MDIP0 8 TD+ TX+ 9 RJ45_TX0+ DL1 LANGND
OSC

NC

DL2 TD- TX- BS4200N-C-LV_SMB-F2


25MHZ_10PF _X1E000311000900
LAN_MDIN0 1 4 LAN_MDIP1 1 @EMI@
I/O1 I/O3 300UH_NS681612A
OSC

CL15
NC

0.01U_0402_16V7K
2 5 2
2

GND VDD
CL16
1 2 XTLI
LAN_MDIP0 3 6 LAN_MDIN1
10P_0402_50V8J I/O2 I/O4
AZC099-04S.R7G_SOT23-6
SC300001G00

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


2014/11/07 2015/11/07 Title
Issued Date Deciphered Date LAN_RTL8107E
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-C771P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, January 14, 2015 Sheet 16 of 34
5 4 3 2 1
5 4 3 2 1

D D

+AV12 +DV12S
+3VS
1 1 1 1
CR1 CR2 CR3 CR4
CR5 1 @ 2 4.7U_0603_6.3V6K
2 2 2 2

0.1U_0402_16V7K

0.1U_0402_16V7K
4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
CR6 1 2 0.1U_0402_16V7K UR1
9
+DV33_18 15 3V3_IN
+AV12 7 DV33_18
+Card_3V3 +DV12S 11 AV12
LR1 DV12_S
+Card_3V3 1 2 +Card_3V3_R 10
PBY160808T-301Y-N_0603 Card_3V3 25
1 2 8 GND
RR1 6.2K_0402_1% RREF Close to UR1
PCIE_PTX_C_DRX_P1 1 12 SD_D1_R RR2 RS@ 1 2 0_0402_5% SD_D1
[7] PCIE_PTX_C_DRX_P1 HSIP SP1
PCIE_PTX_C_DRX_N1 2 13 SD_D0_R RR3 RS@ 1 2 0_0402_5% SD_D0
[7] PCIE_PTX_C_DRX_N1 HSIN SP2
PCIE_PRX_DTX_P1 CR7 1 2 0.1U_0402_16V7K PCIE_PRX_DTX_P1_C 5 14 SD_CLK_R RR4 2 EMI@ 1 33_0402_5% SD_CLK
[7] PCIE_PRX_DTX_P1 1 2 0.1U_0402_16V7K 6 HSOP SP3 16 1 2
PCIE_PRX_DTX_N1 CR8 PCIE_PRX_DTX_N1_C SD_CMD_RRR5 RS@ 0_0402_5% SD_CMD
[7] PCIE_PRX_DTX_N1 HSON SP4 17 1 2
SD_D3_R RR6 RS@ 0_0402_5% SD_D3
SP5 18 SD_D2_R RR7 RS@ 1 2 0_0402_5% SD_D2
C SP6 1 C
[8] CLK_PCIE_Card CLK_PCIE_Card 3 @EMI@
CLK_PCIE_Card# 4 REFCLKP CR9
[8] CLK_PCIE_Card# REFCLKN
+DV33_18 5.6P 50V D NPO 0402
PLT_RST_BUF# 23 20 SD_WP 2
[16,18,20,21,8] PLT_RST_BUF# PERST# SP7
Card_CLKREQ# 24 21 SD_CD#

1U_0402_6.3V6K
2 [7] Card_CLKREQ# CLK_REQ# SD_CD#
CR10
2 1 SD_GPIO1 19 22
+3VS GPIO NC
RR8 10K_0402_5%
1 RTS5220-GRT_QFN24_4X4

SD/SDXC
+Card_3V3
JSD1 ME@
B SD_D0 7 4 B
D0 VDD
SD_D1 8 11 SD_WP
D1 WP
SD_D2 9 CR11

0.1U_0402_16V7K
D2 1 1
10 SD_CD# CR12

4.7U_0603_6.3V6K
SD_D3 1 CD2
D3/CD1 3
VSS1 6 2 2
SD_CLK 5 VSS2
CLK 12
SD_CMD 2 GND 13
CMD GND
FOX_WK21921-R93-9H
SP070014L00

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


2014/11/07 2015/11/07 Title
Issued Date Deciphered Date Card Reader_RTS5220
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-C771P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, January 14, 2015 Sheet 17 of 34
5 4 3 2 1
A B C D E

+3VS_WLAN

+3VS_WLAN

2
RM18
10K_0402_5%

2
2 RM19 1
+1.8VALW
10K_0402_5% RM20

1
10K_0402_5% WLAN_BT_OFF#
1 [9] BT_OFF# 1
2 3

1
QM1B
DMN2400UV-7 2N SOT-563-6
1 6 5 +3VS +3VS_WLAN
RM1
DMN2400UV-7 2N SOT-563-6 1 RS@ 2 1
4 CM1
QM1A
0_0805_5% @
0.1U_0402_16VK7
2

+3VS_WLAN

RM2 1 @ 2 0_0402_5% JWLAN1 ME@


[16,20] PCIE_LAN_WAKE#
RM3 1 @ 2 0_0402_5% WAKE#_R 1 2
[8] SOC_PCIE_WAKE# 1 2
3 4
WLAN_BT_OFF# 5 3 4 6
RM4 1 RS@ 2 0_0402_5% WLAN_CLKREQ#_R 7 5 6 8
[7] WLAN_CLKREQ# 7 8
9 10
11 9 10 12
[8] CLK_PCIE_WLAN# 13 11 12 14
[8] CLK_PCIE_WLAN 15 13 14 16
15 16

17 18
19 17 18 20 RM5 1 RS@ 2 0_0402_5%
2 21 19 20 22 1 RS@ 2 0_0402_5% EC_WL_OFF# [20] 2
WL_RST# RM6
21 22 PLT_RST_BUF# [16,17,20,21,8]
23 24
[7] PCIE_PRX_DTX_N3 23 24
25 26
[7] PCIE_PRX_DTX_P3 27 25 26 28
29 27 28 30
31 29 30 32
[7] PCIE_PTX_C_DRX_N3 31 32
33 34
[7] PCIE_PTX_C_DRX_P3 35 33 34 36 USB20_BT_R_N RM17 1 BT@ 2 0_0402_5%
+3VS_WLAN 37 35 36 38 USB20_BT_N [23]
USB20_BT_R_P RM16 1 BT@ 2 0_0402_5% with out USB Hub (Reserved)
37 38 USB20_BT_P [23]
39 40
41 39 40 42
43 41 42 44 RM14 1 HUB@2 0_0402_5%
43 44 USB_HUB_BT_N3 [23]
45 46 RM15 1 HUB@2 0_0402_5% with USB Hub (Reserved)
47 45 46 48 USB_HUB_BT_P3 [23]
RM11 1 DB@ 2 0_0402_5% 49 47 48 50
[20,21] E51TXD_P80DATA 49 50
[20,21] E51RXD_P80CLK RM12 1 2 0_0402_5% 51 52
DB@ 53 51 52 54
G1 G2
WLAN_BT_OFF# 1 2
RM21 0_0402_5% BELLW_80019-1021
DC040004X00
2

RM13
100K_0402_5%
1

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


2014/11/07 2015/11/07 Title
Issued Date Deciphered Date Mini Card-WLAN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-C771P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, January 14, 2015 Sheet 18 of 34
A B C D E
A B C D E

+3VS +3VDD_CODEC +IOVDD_CODEC +1.8VS

600ohms @100MHz 2A
RS@ RS@
P/N: SM01000EE00 +5VDDA_CODEC +5VS 1 2 0_0603_5% RA2 1 2 0_0603_5%
RA1

1U_0402_6.3V6K
0.1U_0402_16VK7

0.1U_0402_16VK7
+5VS Place near Pin25 Place near Pin26 1 1

1
CA1

CA2

CA3
RS@ RS@
RA3 1 2 0_0603_5% +5VS_PVDD RA4 1 2 0_0603_5%

0.1U_0402_16VK7

0.1U_0402_16VK7
4.7U_0603_6.3V6K

2
+1.8VS 2 2
2 1 1 Place RA4 on AGND/DGND moat

1U_0402_6.3V6K
0.1U_0402_16VK7
CA5

CA6
RS@ 1 1
+1.8VS_AVDD2 1 2

CA4

CA7

CA8
RA5 0_0603_5% Place near Pin1 Place near Pin9
1 2 2
+IOVDD_CODEC 2 2
Combo Jack
CA9 1 2 1U_0402_6.3V6K
1

Place near Pin40


(Normal Open) 1

+3VDD_CODEC
+3VLP wide 60MIL ME@ JHP1
HGNDB 7
HGNDA 5
HPOUT_L RA8 1 RS@ 2 0_0402_5% HPOUT_L1 4
3
HPOUT_R RA9 1 RS@ 2 0_0402_5% HPOUT_R1 1
2

41

46

26

40

20
1

9
UA1
PLUG_IN 6

VDD33 STB
DVDD

DVDD-IO

PVDD1

PVDD2

AVDD1

AVDD2
SANTA_311108-1
DC230009N00
LINE1-L 22
wide 40MIL LINE1-R 21 LINE1-L(PORT-C-L)
LINE1-R(PORT-C-R) SPK-OUT-L-
SPK-OUT-L+
43
42
SPK_L1-
SPK_L2+
LINE2-L 24
LINE2-R 23 LINE2-L(PORT-E-L) 45
RA6 LINE2-R(PORT-E-R) SPK-OUT-R+ 44
SPK-OUT-R-

2
+MIC2-VREFO
1 2 2.2K_0402_5% EXT_MIC_RING2 17
1 2 2.2K_0402_5% EXT_MIC_SLEEVE 18 MIC2-L(PORT-F-L) /RING2 DA3 DA5
RA7 MIC2-R(PORT-F-R) /SLEEVE 32 HP_OUTL ESD@ @ESD@
31 HPOUT-L(PORT-I-L) 33 HP_OUTR
+LINE1-VREFO-L
30 LINE1-VREFO-L HPOUT-R(PORT-I-R) Headphone
+LINE1-VREFO-R LINE1-VREFO-R 10 HDA_SYNC_AUDIO HDA_SYNC_AUDIO [7] L03ESDL5V0CC3-2_SOT23-3 L03ESDL5V0CC3-2_SOT23-3
2 SYNC 6 HDA_BITCLK_AUDIO SCA00002900 SCA00002900
GPIO0/DMIC-DATA BCLK HDA_BITCLK_AUDIO [7]
3
RA10 1 @ 2 10K_0402_5% GPIO1/DMIC-CLK RA11 1 @EMI@ 2 33_0402_5% @EMI@ CA10 22P_0402_50V8J

1
RS@
RA12 1 2 0_0402_5% 47 5 HDA_SDOUT_AUDIO
[7]
[20] EC_MUTE#
HDA_RST_AUDIO#
11
4
PDB
RESETB
ALC233-VB2-CG SDATA-OUT
SDATA-IN
8 HDA_SDIN0_AUDIO RA13 1 2 33_0402_5%
HDA_SDOUT_AUDIO
HDA_SDIN0 [7]
[7]

DC DET 15
2 SPDIFO/FRONT JD(JD3)/GPIO3 +MIC2-VREFO 2
PC_BEEP 12 48
PCBEEP SPDIF-OUT/GPIO2
14 16 CA12 2 1 2.2U_0402_6.3V6M
PLUG_IN_R 13 MIC2/LINE2 JD(JD2) MONO-OUT
HP/LINE1 JD(JD1) 29 CA13 2 1 2.2U_0402_6.3V6M
37 MIC2-VREFO
CA15 2 1 1U_0402_6.3V6K 35 CBP 7 LDO3 CA16 2 1 2.2U_0402_6.3V6M
CBN LDO3-CAP 39 LDO2
LDO2-CAP 27 LDO1 2 1
36 LDO1-CAP RA14 100K_0402_5%
+3VDD_CODEC CPVDD
CA18 2 @ 1 4.7U_0603_6.3V6K
28 CA20 1 2 1U_0402_6.3V6K
VREF

CA21 2 1 2.2U_0402_6.3V6M 19 34 CPVEE


MIC-CAP CPVEE
2
49 25 CA22
Thermal PAD AVSS1 38
AVSS2 1 1U_0402_6.3V6K
ALC233-VB2-CG_MQFN48_6X6

EMI Close to JHP1

W=40mils EXT_MIC_SLEEVE RA17 1 2 TAI-TECH FCM1608CF-121T03 0603 HGNDB


W=40mils EXT_MIC_RING2 RA18 1 2 TAI-TECH FCM1608CF-121T03 0603 HGNDA
HP_OUTL RA19 1 2 47_0402_5% HPOUT_L HGNDB CA111 2 470P_0402_50V7K
HP_OUTR RA20 1 2 47_0402_5% HPOUT_R EMI@
+3VS
HGNDA CA141 2 470P_0402_50V7K
EMI@
2

2
3 Place close to Codec chip RA15 LINE1-L CA23 2 1 1U_0402_6.3V6K HPOUT_L CA171 2 470P_0402_50V7K 3

RA22

RA23
EMI@

10K_0402_5%

10K_0402_5%
100K_0402_5%
LINE1-R CA24 2 1 1U_0402_6.3V6K @ @
+LINE1-VREFO-R HPOUT_R CA191 2 470P_0402_50V7K
1

EMI@

1
RA25 1 2 4.7K_0402_5%
2

RA27 PLUG_IN_R RA16 1 2 200K_0402_1% PLUG_IN


2.2K_0402_5% (Vendor)for audio performance 1201
+LINE1-VREFO-L
1

MIC1 RA29 1 2
1 LINE2-MIC 1 2 LINE2-L 4.7K_0402_5% For Universal Audio Jack
2 GNDA CA25 2.2U_0402_6.3V6M
1 @ 2 LINE2-R
KECG2242PFL-B4
45@ RA32 0_0402_1%

LINE2-MIC & LINE 2 wide 40MIL For EMI


@EMI@ JSPK1 ME@
wide 60MIL SPK_L1-
SPK_L2+
LA1
LA2
1
1
2 FCM1608CF-121T03 0603
2 FCM1608CF-121T03 0603
SPK_L1-_CONN
SPK_L2+_CONN
1
2 1
2
@EMI@

3
follow vendor suggest LA1 LA2 4 G1

1000P_0402_50V7K

1000P_0402_50V7K
G2
& reserver default design 0_0603_5% 0_0603_5%
E-T_3806K-F02N-03R_2P
PC Beep For EMI EMI@ EMI@ 1 1

EMI@ CA28

EMI@ CA29
SP02E005320

2
2 2
DA4
CA30 1 2 0.1U_0402_16V4Z CA31 RA21 1 RS@ 2 0_0402_5% @ESD@
4
EC Beep [20] BEEP#
1 RA30 2 1 2 PC_BEEP L03ESDL5V0CC3-2_SOT23-3 4
CA32 1 2 0.1U_0402_16V4Z DVT, NO.31 SCA00002900
SOC Beep [9] HDA_SPKR
1K_0402_5% 0.1U_0402_16V7K RA24 1 RS@ 2 0_0402_5%
1

RA26 1 RS@ 2 0_0402_5%

1
@
RA31
10K_0402_5% RA28 1 RS@ 2 0_0402_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
2

2014/11/07 2015/11/07 Title


GND GNDA
Issued Date Deciphered Date Audio Codec_ALC233VB2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-C771P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, January 14, 2015 Sheet 19 of 34
A B C D E
A B C D E

RB2 1 @ 2 0_0603_5% +3VALW_EC +3VLP L3


TCM@ +3VALW FBM-11-160808-601-T_0603
1 2 0_0402_5% EC_SERIRQ_R RB4 1 RS@ 2 0_0603_5% 1 2 +3VALW_EC
[21] TCM_SERIRQ RB1 +3VLP +3VALW_EC +EC_VCCA
1 1
1 2 0_0402_5% +1.8VALW CB2 LID_SW# RB5 1 2 47K_0402_5%
[21,9] EC_SERIRQ RB3 CB1 @
1 1 1 1

0.1U_0201_10V6K
CB3

0.1U_0201_10V6K
CB4

1000P_0402_50V7K
CB5

1000P_0402_50V7K
CB6
NTCM@ .1U_0402_16V7K 1000P_0402_50V7K

2
1 2 2 ECAGND 2
1

2
RB6 @ CB7 L4
2 2 @ 2 @ 2 0_0402_5% RB7 100P_0402_50V8J FBM-11-160808-601-T_0603
@ 0_0402_5% @
2 ECAGND TP_CLK RB8 1 2 4.7K_0402_5%
RS@ +5VS

1
TP_DATA RB9 1 @ 2 4.7K_0402_5%
+3VALW_EC

1
RB10 2 1 47K_0402_5% EC_RST# +VCC_SPI
1 1
RB11 1 TCM@ 20_0402_5% +VCC_LPC EC_MUTE# RB12 1 @ 2 10K_0402_5%
CB8 2 1 .1U_0402_16V7K +3VLP +EC_VCCA
RB13 1 NTCM@ 20_0402_5% +VCC_LPC +VCC_SPI TP_CLK RB14 1 2 4.7K_0402_5%
+1.8VALW TP_DATA RB15 1 2 4.7K_0402_5%
+3VS

2 2

111
125

.1U_0402_16V7K

.1U_0402_16V7K
22
33
96

67
9

CB13

CB14
UB1

VCC5/SPI
VCC2
VCC3
VCC4
VSBY
VCC1/LPC

AVCC
close UB1 pin125 1 1 close UB1 pin 9

+3VALW_EC 1 21
2 GPIO85/GA20 GPIO15/A_PW M 23 VGATE [32]
RPB1
1 8 EC_SMB_CK1
[8] EC_KBRST#
EC_SERIRQ_R 3 GPIO86/KBRST#
SERIRQ/GPIOF0 PWM Output
GPIO21/B_PW M
GPIO32/D_PW M
26 BEEP# [19] Board ID
2 7 EC_SMB_DA1 4 27 Analog Board ID definition,
3 6 [21,9] LPC_FRAME# 5 LFRAME#/GPIOF6 GPIO45/E_PW M
EC_SMB_CK2
4 5 [21,9] LPC_AD3 7 LAD3/GPIOF4 Please see page 3.
EC_SMB_DA2
+3VS [21,9] LPC_AD2 LAD2/GPIOF3
8 63
[21,9] LPC_AD1 10 LAD1/GPIOF2 GPIO90/AD0 64 VCIN1_BATT_TEMP [26,27]
2.2K_0804_8P4R_5%
+3VALW_EC [21,9] LPC_AD0 LAD0/GPIOF1 LPC & MISC GPIO91/AD1 65 VCIN1_BATT_DROP [28]
12 GPIO92/AD2 66 ADP_I [26,27]
[9] LPC_CLK_EC LCLK/GPIOF5 AD Input GPIO93/AD3
PLT_RST_BUF#_R 13 75

RB18 1 @ 2 10K_0402_5% EC_SCI#


[7] EC_SCI#
EC_RST# 37
20
38
LRESET#/GPIOF7
ECRST#
GPIO54/ECSCI#
GPIO05/AD4
GPIO04/AD5
76
1125 Remove for EC
GPIO11/CLKRUN# 68 EC_CLEAR_CMOS
GPIO94/DA0 70
GPIO95/DA1 71
DA Output GPIO96/DA2
KSI0 55 72 EC_WL_OFF#
56 KBSIN0/GPIOA0 GPIO97/DA3 EC_WL_OFF# [18]
TCM@ KSI1
1 2 PLT_RST_BUF#_R KSI2 57 KBSIN1/GPIOA1
2
[16,17,18,21,8] PLT_RST_BUF# RB29 0_0402_5% KSI3 58 KBSIN2/GPIOA2 83 EC_MUTE# 2
1 2 KSI4 59 KBSIN3/GPIOA3 GPIO31/SCL3/PSCLK1 84 EC_MUTE# [19]
[8] PMC_PLTRST#_R RB30 0_0402_5% KSI5 60 KBSIN4/GPIOA4/N2TCK GPIO23/SDA3/PSDAT1 85 USB_EN# [22,23] +3VALW_EC
NTCM@ KSI6 61 KBSIN5/GPIOA5/N2TMS GPIO47/SCL4/PSCLK2 86
KBSIN6/GPIOA6 PS2 Interface GPIO53/SDA4/PSDAT2 CMOS_ON# [14]
KSI7 62 87 TP_CLK
KBSIN7/GPIOA7 GPIO50/PSCLK3 TP_CLK [21]
CB10 1 2 KSO0 39 88 TP_DATA
KBSOUT0/GPIOB0/SOUT_CR/JENK# GPIO52/PSDAT3 TP_DATA [21]
100P_0402_50V8J KSO1 40
KBSOUT1/GPIOB1/TEST#

2
ESD@ KSO2 41
KSI[0..7] KSO3 42 KBSOUT2/GP(I)OB2/TRIST# 97 @ @
[21] KSI[0..7] KBSOUT3/GP(I)OB3/XORTR# GPIO02 SOC_ENBKL [6]
KSO4 43 98 RB20 RB21
KSO[0..17] KSO5 44 KBSOUT4/GPIOB4/SDP_VIS# GPIO75 99 10K_0402_5% 10K_0402_5%
[21] KSO[0..17] KBSOUT5/GPIOB5/TDO GPIO GPIO76 ME_EN [7]
KSO6 45 109 VCIN0_PH1
VCIN0_PH1 [26]

1
KSO7 46 KBSOUT6/GPIOB6/RDY# VCIN1/GPIO16 VCIN0_PH1
KBSOUT7/GPIOB7 Int. K/B
KSO8 47 VCIN1_ADP_PROCHOT
KSO9 48 KBSOUT8/GPIOC0 Matrix 119
49 KBSOUT9/GPIOC1 F_SDI&F_SDIO1/GPO80 120 EC_SDIO [8]
KSO10
KBSOUT10&P80_CLK/GPIOC2 F_SDIO&F_SDIO0/GPIOC6 EC_SDI [8]
KSO11 50 126
KBSOUT11&P80_DAT/GPIOC3 F_CLK/GPIOC4 EC_SCK [8]
KSO12 51 SPI Flash ROM F_CS0#/GPIOC5 128
52 KBSOUT12/GPIO64/TCK EC_CS0# [8]
KSO13
KBSOUT13/GPIO63/TMS CLR_CMOS# [8]
KSO14 53
KSO15 54 KBSOUT14/GPIO62/TDI 73
KBSOUT15/GPIO61/XOR_OUT GPIO03/AD6/CIRRXM

1
KSO16 81 74
GPIO60/KBSOUT16 GPIO07/AD7/CIRTX1 EC_ENVDD [14]
KSO17 82 89 D QB1
GPIO57/KBSOUT17 GPIO67/N2TMS 90 EC_CLEAR_CMOS 2
GPIO51/N2TCK 91 BATT_CHG_LED# [21]
CAPS_LED# [21] G
GPIO36

2
77 GPIO 92 S 2N7002K_SOT23-3
[26,27] EC_SMB_CK1 GPIO17/SCL1/N2TCK GPIO40/F_PW M PWR_LED# [21]
Charger and BATT 78 93
[26,27]2 EC_SMB_DA1 BATT_LOW_LED# [21]

3
@ 1 EC_SMB_R_CK2 79 GPIO22/SDA1/N2TMS GPIO35 95 RB31
[13,9] EC_SMB_CK2 GPIO73/SCL2 GPIO06/IOX_DOUT SYSON [29]
RB16 2 @ 1 0_0402_5% EC_SMB_R_DA2 80 SM Bus 121 10K_0402_5%
[13,9] EC_SMB_DA2 GPIO74/SDA2 GPIO81/F_W P# SOC_ENVDD [6]
RB17 0_0402_5% 127

1
GPIO84/IOX_SCLK

3
EC no use 1201 +1.05VS
3
6 100
14 GPIO24 GPIO26/RSMRST# 101 EC_RSMRST# [8]
15 GPIO10/LPCPD# GPIO20/TA2/IOX_DIO 102 VCIN1_ADP_PROCHOT
[28,30,31] 3V/5VALW_PG 16 GPIO65/SMI# VC_IN2/GPIO72 103 VCIN1_ADP_PROCHOT [26]
VCOUT1_PROCHOT#
GPIO34/1_W IRE/CIRRXL VC_OUT2/GPIO37 VCOUT1_PROCHOT# [26,27]
17 104 NUVOTON_VTT RB23 1 @ 2 0_0402_5%
GPIO01/TB2 VC_OUT1/GPIO25 VCOUT0_MAIN_PWR_ON [28]
18 GPIO 105
19 GPIO43 GPIO77 106 EC_BKOFF# [14]
[16,18] PCIE_LAN_WAKE# GPIO42/CIRTX2 GPIO GPIO44 PMC_SLP_S3# [8]
25 107
28 GPIO13/C_PW M GPIO12 108 RB32 1 2 10K_0402_5%
GPIO56/TA1 GPIO30/F_W P# VR_ON [32]
29
30 GPIO14/TB1
[18,21] E51TXD_P80DATA 31 GPIO83/SOUT_CR/P80_DATA 110
[18,21] E51RXD_P80CLK GPIO87/SIN_CR/P80_CLK AC_IN/GPIO41/F_W P# VCIN1_AC_IN [27,8]
32 112
[8] PMC_CORE_PWROK 34 GPIO27/RSMRST# EC_ON/GPIO71 114 EC_ON [28]
[22] NOVO# GPIO66/G_PW M GPIO ON_OFFBTN#/GPIO70 ON/OFF# [21]
36 115 LID_SW# VCOUT1_PROCHOT# RB24 1 RS@ 2 0_0402_5%
GPIO33/H_PW M GPO82/IOX_LDSH/LIDIN LID_SW# [21]
116
GPIO46/CIRRXM/PLCIN 117 NUVOTON_VTT SUSP# [24,29]
VTT 118 2 RB25 @1 RB26 1 RS@ 2 0_0402_5%
PECI PECI [32] VR_HOT# H_PROCHOT# [7]
122 0_0402_5%
[8] PBTN_OUT# GPIO00/EXTCLK
RB22 1 2 EC_SLP_S4#_R2 123 124 +V18R
[8] PMC_SLP_S4# GPIO55/CLKOUT/IOX_DIO VCORF
0_0402_5% RS@ 1
AGND
GND1
GND2
GND3
GND4
GND5

1
CB11 @
+3VALW 4.7U_0603_6.3V6K CB12
2 47P_0402_50V8J
11
24
35
94
113

69

NPCE388NA0DX_LQFP128_14X14 2

ECAGND
1 2 PCIE_LAN_WAKE#
RB27 10K_0402_5%

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


2014/11/07 2015/11/07 Title
Issued Date Deciphered Date EC-NPCE388N
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-C771P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, January 14, 2015 Sheet 20 of 34
A B C D E
A B C D E

+3VS R1 1 RS@ 2 0_0402_5%

+5VS R2 1 2 0_0402_5%
+3VALW @
@
C1

KB For 14" KB For 15" +3VLP C2 1 2 0.1U_0603_6.3V6M


.1U_0402_16V7K

JKB1 JKB2
For TP
KSI1 1
1
KSI1 1
1
PWR/B conn. ESD@
JTP1

2
KSI7 2 KSI7 2 TP_VCC 1
KSI6 3 2 KSI6 3 2 TP_DATA 2 1
3 3 [20] TP_DATA 2
KSO9 4 KSO9 4 R3 TP_CLK 3
4 4 [20] TP_CLK 3
KSI4 5 KSI4 5 100K_0402_5% JPWRB1 1 1 4
KSI5 6 5 KSI5 6 5 1 @ @ 5 4

1
KSO0 7 6 KSO0 7 6 2 1 C4 C3 6 5
1 7 7 2 6 1
KSI2 8 KSI2 8 3 100P_0402_50V8J 100P_0402_50V8J
KSI3 9 8 KSI3 9 8 ON/OFF# 4 3 2 2 7
9 9 [20] ON/OFF# 4 GND

3
KSO5 10 KSO5 10 5 8
KSO1 11 10 KSO1 11 10 LID_SW# 6 5 D1 TP_R GND
11 KSI[0..7] 11 [20] LID_SW# 6
KSI0 12 KSI0 12 @ESD@ TP_L ACES_88058-060N
12 KSI[0..7] [20] 12
KSO2 13 KSO2 13 7 ME@
KSO4 14 13 KSO[0..17] KSO4 14 13 8 GND YSLC05CH_SOT23-3 SP010010T00
14 KSO[0..17] [20] 14 GND
15 15

C5

C6
KSO7 KSO7

.1U_0402_16V7K

.1U_0402_16V7K
KSO8 16 15 KSO8 16 15 ACES_88058-060N
16 16 1 1
KSO6 17 KSO6 17 ME@
KSO3 18 17 KSO3 18 17 SP010010T00

1
18 18

2
KSO12 19 KSO12 19 D2 @ @
For TP module(TM-02978)
KSO13
KSO14
KSO11
20
21
22
19
20
21
KSO13
KSO14
KSO11
20
21
22
19
20
21
ESD@
SCA00001G00 SCA00002900
ESD 2 2

KSO10 23 22 KSO10 23 22 L30ESD24VC3-2 @ESD@ 1 6 VCC


KSO15 24 23 KSO15 24 23 D3

1
25 24 KSO16 25 24
26 25 KSO17 26 25 2 5 DAT
27
28
29
26
27
28 31
27
28
29
26
27
28 31 ESD L R 3 4 CLK
30 29 GND 32 30 29 GND 32
30 GND 30 GND
ACES_88514-3001 ACES_88514-3001 SW3 SW4 4 3 GND
ME@ ME@ SMT1-05_4P SMT1-05_4P

5
6

5
6
SP010011A00 SP010011A00
PWR_LED# C9 1 2 .1U_0402_16V7K 4 2 4 2 5 2 R
TP_L TP_R
@EMI@ 3 1 3 1
6 1 L
ON/OFF# C10 1 2 .1U_0402_16V7K

@EMI@

LID_SW# C11 1 2 .1U_0402_16V7K

@EMI@

2 2

LED1
R6
PWR_LED# 1 2 1 2 +3VALW
Power (White) [20] PWR_LED#
300_0402_5%
VL For EC debug. Place to anywhere.
19-217-T1D-DP1Q2QY-3T_WHITE
SC50000A300 C12 1 2 0.1U_0603_6.3V6M

ESD@

LED2 JP1
R7 1
1 2 1 2 2 1
Battery (Amber) [20] BATT_LOW_LED#
620_0402_5%
+3VLP [18,20] E51TXD_P80DATA
3 2
[18,20] E51RXD_P80CLK 3
4
19-217/S2C-FM2P1VY/3T 0603 ORANGE 4
SC500005T00 ACES_85205-0400
R12 1 @ 2 0_0402_5% ME@

LED3
J1: TOP
R13 J2: BOT J1
R15 1 RS@ 2 0_0402_5% 1 2 1 2
Battery (White) [20] BATT_CHG_LED#
330_0402_5%
VL
1 2

19-217-T1D-DP1Q2QY-3T_WHITE SHORT PADS


SC50000A300
J2
1 2 ON/OFF#

LED4 SHORT PADS


R14
1 2 1 2
CAPS (white) [20] CAPS_LED#
330_0402_5%
+5VS

19-217-T1D-DP1Q2QY-3T_WHITE
SC50000A300

3 3

@ @ @ @
TCM(TPM) FD1 FD2 FD3 FD4

RW1 +3VS

1
TCM@
+3VS_TCM 1 2
1 1 1
0.1U_0201_10V6K

CW1

0.1U_0201_10V6K

CW2

0.1U_0201_10V6K

CW3

0_0402_5%

2 2 2
TCM@

TCM@

TCM@

UW1
H1 @ H2 @ H9 @ H10 @ H11 @ H12 @
1 24 HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
2 NC 3V 10
3 NC 3V 19
7 NC 3V

1
PP 22 LPC_FRAME#
LFRAME# LPC_FRAME# [20,9]
6 28
9 NC LPCPD# TCM@
NC 21 TCM_LPC_CLK 1 2 33_0402_5%
LCLK LPC_CLK_TCM [9]
4 27 TCM_SERIRQ H_3P0 H_3P0 H_3P8 H_3P8 H_3P8 H_3P8
11 GND SIRQ RW2
18 GND 26 LPC_AD0
GND LAD0 LPC_AD0 [20,9]
25 23 LPC_AD1
GND LAD1 LPC_AD1 [20,9]
20 LPC_AD2
LAD2 LPC_AD2 [20,9]
5 17 LPC_AD3 H3 @ H8 @ H14 @
NC LAD3 LPC_AD3 [20,9]
8 HOLEA HOLEA HOLEA
12 NC 15
13 NC CLKRUN# 16
NC LRESET# PLT_RST_BUF# [16,17,18,20,8]
14

1
NC

Z32H320TC-LPC-T28-233_TSSOP28
TCM@
H_3P0 H_3P0 H_3P0
+3VALW_EC +3VS
1

H4 @ H5 @ H6 @ H7 @ H13 @
HOLEA HOLEA HOLEA HOLEA HOLEA
RW3 RW4
4
0_0402_5% 0_0402_5% 4
@ TCM@
2

1
+1.8VALW +1.8VALW
1

RW7
1

1 RW6 2.2K_0402_5% H_3P0 H_3P0 H_3P1X3P6 H_3P0 H_3P0


RW5 0_0402_5% @ RW9 RW8
CW4 2.2K_0402_5% UW2 TCM@ 0_0402_5% 10K_0402_5%
2

0.1U_0201_10V6K @ 1 6 1 @ 2 TCM@
TCM@ 2 VCCA VCCB
2

2 5
GND EO
3 4 TCM_SERIRQ
[20,9] EC_SERIRQ A B TCM_SERIRQ [20]
G2129TL1U_SC70-6 Security Classification Compal Secret Data Compal Electronics, Inc.
TCM@ 2014/11/07 2015/11/07 Title
Issued Date Deciphered Date KB/TP/LED/TCM/Screw Hole
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-C771P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, January 14, 2015 Sheet 21 of 34
A B C D E
A B C D E

SATA HDD Conn.


FOR 15" Near Connector JHDD1

1
CO2 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_P0 2 GND
1 +5VS +5V_ODD SATA ODD Conn. [7]
[7]
SATA_PTX_DRX_P0
SATA_PTX_DRX_N0 CO3 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_N0 3
4
A+
A-
1

1 RS@ 2 CO7 1 2 0.01U_0402_16V7K SATA_PRX_C_DTX_N0 5 GND


RO1 0_0805_5%
80mils [7] SATA_PRX_DTX_N0 CO1 1 2 0.01U_0402_16V7K SATA_PRX_C_DTX_P0 6 B-
+5V_ODD [7] SATA_PRX_DTX_P0 7 B+
JODD1 ME@ GND

ODD@ 1 8
CO4 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_P1 2 GND 1 RS@ 2 +3V_HDD 9 V33
[7] SATA_PTX_DRX_P1 A+ +3VS V33
CO5 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_N1 3 RO2 0_0805_5% 10
[7] SATA_PTX_DRX_N1 A- V33
ODD@ 4 11
CO6 1 ODD@
2 0.01U_0402_16V7K SATA_PRX_C_DTX_N1 5 GND 12 GND
[7] SATA_PRX_DTX_N1 B- GND
1 CO8 1 2 0.01U_0402_16V7K SATA_PRX_C_DTX_P1 6 13
[7] SATA_PRX_DTX_P1 B+ GND
ODD@ 7 +5VS
1 RS@ 2 +5VS_HDD 14
CO9 ODD@ GND RO4 0_0805_5% 15 V5
10U_0603_6.3V6M 16 V5
2 RO5 1 @ 2 0_0402_5% ODD_DETECT#_R 8 17 V5
9 DP 18 GND
10 +5V 14 19 Reserved
T22 11 +5V GND 15 +5VS 20 GND
12 MD GND 21 V12 24
13 GND 22 V12 GND 23
Place CAP close to JODD GND 100mils V12 GND

10U_0603_6.3V6M
CO10

1U_0402_6.3V6K
CO11

.1U_0402_16V7K
CO12
SANTA_201304-1 1 1 1
DC01000AV00 SDAN_603015-022041
ME@
@ +3V_HDD CO13 1 2 0.1U_0603_6.3V6M
2 2 2
ESD@
+5VS_HDD CO14 1 2 0.1U_0603_6.3V6M

ESD@

2 2

RS6 2 RS@ 1 0_0402_5%

+3VLP
LS1
[9] PCH_USB3_TX0_P
2 1 PCH_USB3_TX0_P_C 1 2 U3TXDP0
CS1 .1U_0402_16V7K

[9] PCH_USB3_TX0_N 2 1 PCH_USB3_TX0_N_C 4 3 U3TXDN0

NOVO BTN CS2 .1U_0402_16V7K DS1 @ESD@


USB3.0_Port
100K_0402_5%
2

PANASONIC EXC24CH900U U3RXDN0 1 1 10 9 U3RXDN0


@EMI@
2 2 9 8
R16

U3RXDP0 U3RXDP0
RS7 2 RS@ 1 0_0402_5%
SW5 4 4
U3TXDN0 7 7 U3TXDN0
1

NTC325-EA1J-A160C_3P SF000002Y00
1 U3TXDP0 5 5 6 6 U3TXDP0
[20] NOVO# 2 220U 6.3V OSCON
3 3 3
RS8 2 RS@ 1 0_0402_5%
ESR 17mohm@100Khz
3

8
4
5
6
7

D4 W=100mils +USB3_VCCA
@ESD@ LS2 L05ESDL5V0NA-4_SLP2510P8-10-9
PCH_USB3_RX0_P 1 2 U3RXDP0 SC300002C00
[9] PCH_USB3_RX0_P
L03ESDL5V0CC3-2_SOT23-3 JUSB1 ME@
SCA00002900 1
PCH_USB3_RX0_N 4 3 U3RXDN0 USB20_N0_L 2 VBUS
[9] PCH_USB3_RX0_N D-
USB20_P0_L 3
PANASONIC EXC24CH900U 4 D+
1

U3RXDN0 5 GND
@EMI@
3
RS9 2 RS@ 1 0_0402_5% ESD U3RXDP0

U3TXDN0
6
7
8
STDA_SSRX-
STDA_SSRX+
GND
3

U3TXDP0 9 STDA_SSTX-
DS2 @ESD@ STDA_SSTX+
+USB3_VCCA USB20_N0_L 6 3 10
@EMI@ I/O4 I/O2 11 GND
2 1 0_0402_5% 12 GND
W=80mils RS1
GND
W=80mils 13
+5VALW 5 2 GND
+USB3_VCCA LS3 EMI@ VDD GND SINGA_2UB4039-200011F_9P
1 2 USB20_P0_L
[9] USB20_P0
1 2 US1
CS3 @ESD@ 1 USB20_P0_L 4 1
.1U_0402_16V7K 5 OUT 4 3 USB20_N0_L I/O3 I/O1
IN [9] USB20_N0
2 RS2 AZC099-04S.R7G_SOT23-6
USB_EN# 4 GND 0_0402_5% HCM1012GH900BP_4P SC300001G00
[20,23] USB_EN# EN 3 1 @ 2
OCB USB_OC0# [23,9]
SY6288D20AAC_SOT23-5 RS3 2
@EMI@
1 0_0402_5%
USB2.0_Port
220U_6.3V_M
CS4

1
+USB3_VCCA
1
+ @
CS5 @EMI@ W=80mils
2 2
470P_0402_50V7K RS4 2 1 0_0402_5%
ESD 1
JUSB2 ME@
5
LS4 EMI@ VBUS SHLD1
1 2 USB20_P1_L DS3 @ESD@ USB20_N1_L 2 6
[9] USB20_P1 +USB3_VCCA D- SHLD2
USB20_N1_L 6 3
I/O4 I/O2 USB20_P1_L 3 7
4 3 USB20_N1_L D+ SHLD3
[9] USB20_N1
4 8
HCM1012GH900BP_4P 5 2 GND SHLD4
VDD GND

RS5 2 1 0_0402_5% SDAN_608050-004041


USB20_P1_L 4 1
@EMI@ I/O3 I/O1
AZC099-04S.R7G_SOT23-6
4 SC300001G00 4

Security Classification Compal Secret Data Compal Electronics, Inc.


2014/11/07 2015/11/07 Title
Issued Date Deciphered Date HDD/ODD/USB
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-C771P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, January 14, 2015 Sheet 22 of 34
A B C D E
A B C D E

USB2.0 HUB
+5VALW +5V_HUB +3V_HUB
1 1
1
RS15 HUB@20_0603_5% +5V_HUB
1 1 1
1 HUB@
HUB@ CS7 HUB@ CS8 CS9
HUB@ CS10 .1U_0402_16V7K .1U_0402_16V7K 10U_0603_6.3V6M +5V_HUB
2 2 2
4.7U_0603_6.3V6M
2

1
USB S/B CONN

19
20
25
US2 HUB@ RS10
HUB@ 10K_0402_5%

VSS
VD33F
VDD5
USB SB (Reserved) USB_HUB_P1 12

2
USB_HUB_N1 11 DP1 1 HUB_OVCJ
10 DM1 OVCJ 2 +USB_SB
DP2 TESTJ 1
9 3 HUB_XOUT
8 DM2 XOUT 4 HUB_XIN HUB@ CS11
[18] USB_HUB_BT_P3 DP3 XIN
Bluetooth (Reserved) 7 5 0.01U_0402_16V7K
[18] USB_HUB_BT_N3 18 DM3 DM4 6 2 JSB1 ME@
HUB_BUSJ
HUB_VBUSM 17 BUSJ DP4 21 1
HUB_XRSTJ 16 VBUSM DRV 22 YS1 HUB@ 2 1
RS16 1 HUB@2 0_0402_5% USB20_R_P3 15 XRSTJ LED1 23 4 1 HUB_XIN USB_HUB_P1 3 2
[9] USB20_P3 DPU LED2 3
RS17 1 HUB@2 0_0402_5% USB20_R_N3 14 24 USB_HUB_N1 4
[9] USB20_N3 13 DMU PWRJ 5 4
REXT 6 5
6

1
FE1.1S-BQFN24B_WQFN24_4X4 HUB_XOUT3 2
SA00005E810 7
2
RS18 0_0402_5% 2.7K_0402_1% HUB@ 12MHZ_18PF_7V12000001 8 GND 2
1 BT@ 2 RS11 GND
[18] USB20_BT_P Part Number = SJ10000C210
1 BT@ 2
[18] USB20_BT_N

2
PCB Footprint = Y_CRG3201212_4P
RS19 0_0402_5%

W=80mils
W=80mils +5VALW
+3V_HUB
+USB_SB

afix
Vin
RS12 1 HUB@2 100K_0402_5% HUB_XRSTJ
1 2 US3 HUB@
RS13 1 HUB@2 100K_0402_5% HUB_BUSJ CS13 @ESD@ 1
.1U_0402_16V7K 5 OUT
RS14 1 HUB@2 10K_0402_5% HUB_VBUSM IN 2 RS20
USB_EN# 4 GND 0_0402_5%
CS12 1 2 0.01U_0402_16V7K [20,22] USB_EN# EN 3 1 @ 2
OCB USB_OC0# [22,9]
HUB@ SY6288D20AAC_SOT23-5

220U_6.3V_M
CS14
1
1
+ @
CS6
3 HUB@ 470P_0402_50V7K 3
2 2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


2014/11/07 2015/11/07 Title
Issued Date Deciphered Date USB 2.0 HUB
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-C771P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, January 14, 2015 Sheet 23 of 34
A B C D E
A B C D E

+3VALW
VIH=1.2~5.5V Rise Time:
3.3V@100k/0.1uF=3.538ms 1 2 3.3V@330pF = 889.68us
CQ1 @ UQ1 PJ3 JP@
3.3V@120k/0.1uF=4.272ms 1U_0402_6.3V6K 1 14 +3VS_OUT
5.0V@330pF = 1348us
VIN1 VOUT1 +3VS
RQ1 2 13
100K_0402_5% VIN1 VOUT1 CQ2 JUMP_43X118
1 SUSP# 2 1 3VS_ON 3 12 2 1 330P_0402_50V7K 1
ON1 CT1 CQ3 2 1@ .1U_0402_16V7K
CQ4 2 1 +5VALW 4 11
.1U_0402_16V7K VBIAS GND CQ5 2 1@ .1U_0402_16V7K
1 2 5VS_ON 5 10 2 1
RQ2 ON2 CT2 330P_0402_50V7K
0701 update 120K_0402_5% 6 9 CQ6 PJ4 JP@
+5VALW VIN2 VOUT2
1 2 7 8 +5VS_OUT +5VS
CQ7 VIN2 VOUT2
.1U_0402_16V7K 1 2 15 JUMP_43X118
CQ8 @ GPAD
1U_0402_6.3V6K AOZ1331 TDFN2X3

+1.8VALW
VIH=1.2~5.5V Rise Time:
3.3V@82k/0.1uF=3.042ms 1 2 1.8V@330pF = 485.28us
CQ9 @ UQ2 PJ5 JP@
3.3V@47k/0.1uF=1.893ms 1U_0402_6.3V6K 1 14 +1.8VS_OUT 1.35V@330pF = 363.96us
VIN1 VOUT1 +1.8VS
RQ3 2 13
82K_0402_5% VIN1 VOUT1 CQ10 JUMP_43X79
SUSP# 2 1 1.8VS_ON 3 12 2 1 330P_0402_50V7K
ON1 CT1 CQ11 2 1@ .1U_0402_16V7K
CQ12 1 2 4 11
2 +5VALW VBIAS GND 2
0701 update .1U_0402_16V7K CQ13 2 1@ .1U_0402_16V7K
2 1 1.35VS_ON 5 10 2 1
RQ4 ON2 CT2 330P_0402_50V7K
47K_0402_5% 6 9 CQ14 PJ6 JP@
+1.35V VIN2 VOUT2
1 2 7 8 +1.35VS_OUT
VIN2 VOUT2 +1.35VS
CQ15
.1U_0402_16V7K 1 2 15 JUMP_43X79
CQ16 @ GPAD
1U_0402_6.3V6K AOZ1331 TDFN2X3

+1.05VALW TO +1.05VS +5VALW


+0.675VS

1
+1.05VALW UQ3 +1.05VS RQ5
ME4856_SO8 100K_0402_5% @
8 1 RQ6
2 7 2 2 22_0603_5%

1
CQ17 6 3 CQ18 2 SUSP

2
3 4.7U_0603_6.3V6K 5 4.7U_0603_6.3V6K 3
CQ19 +0.675VS_R

1
1 1
.1U_0402_16V7K
4

1
1 D
@ESD@
@ 2 D
[20,29] SUSP# 2
RQ7 G Q2 SUSP

1
470_0603_5% S 2N7002K_SOT23-3 G
+5VALW RQ8 @ Q3 S
1

3
10K_0402_5% 2N7002K_SOT23-3

3
2 1 1.05VS_GATE +1.05VS_R
1

RQ9

2
10K_0402_5% 1@ D
1

CQ20 2 SUSP
D .1U_0402_16V7K G
SUSP 2 S Q4 @
G 2 2N7002K_SOT23-3
3

Q5 S
2N7002K_SOT23-3
3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


2014/11/07 2015/11/07 Title
Issued Date Deciphered Date DC-DC Interface
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-C771P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, January 14, 2015 Sheet 24 of 34
A B C D E
5 4 3 2 1

Version Change List ( P. I. R. List )


Item Page# Title Date Request Owner Issue Description Solution Description Rev.
1 22 HW 2014/11/18 COMPAL added NOVO BTN function SW5, R16 connected to EC for NOVO function 0.1

2 18 HW 2014/11/19 COMPAL reserver level shift for BT Reserver QM1, RM18, Rm19and RM20 for BT level shift 0.1

D 3 9 HW 2014/11/19 COMPAL added TCM, NTCM BOM option added RC82 reserve for LPC_CLKRUN# PU 1.8VS 0.1 D

4 21 HW 2014/11/19 COMPAL Move the hall sensor to power S/B remove hall sensor circiut 0.1

5 8, 20 HW 2014/11/21 COMPAL reserver EC clean CMOS reserver QB1, RB31, RC83, and RC84 0.1
6 14 EMI 2014/11/24 COMPAL for EMI request reserver CX14 and CX15 0.1
7 20 HW 2014/11/25 COMPAL EC vendor implement Added NUVOTON_VTT RB32 PD 0.1
8 23 HW 2014/11/25 COMPAL Reserve USB 2.0 HUB for external USB CONN Added page 23 for USB 2.0 HUB 0.1
9 20 EC 2014/11/25 COMPAL Change and remove EC pin define PMC_SLP_S3# 97 pin -> 106 pin Remove 0.1
PCIE_LAN_WAKE# 123 pin -> 19 pin BRDID
EC_SLP_S4# 85 pin -> 123 pin EC_BT_OFF#
VR_ON 121 pin -> 108 pin HDD_DETECT#
SOC_ENVDD? 1 pin -> 121 pin EC_LID_OUT#
EC_ENVDD? 76 pin -> 74 pin
VGATE 16 pin -> 21 pin
SOC_ENBKL 18 pin -> 97 pin

10 23 HW 2014/11/27 COMPAL Change USB S/B from 2 port to 1port Change JSB1 0.1

11 22 EMC 2014/11/28 COMPAL Reserve ESD diode Reserve D4 and DA5 0.1

12 19 HW 2014/12/01 COMPAL for Audio vendor review change change RA27 form 4.7K to 2.2K 0.1

13 20 HW 2014/12/01 COMPAL Reserver SMbus resistor from CPU to EC Reserve RB16 and RB17 0.1
14 21 HW 2014/12/02 COMPAL Change LED form green to white Change LED1, LED2, and LED3 form SC590KGK020 to SC50000A300,
C
and change R6 from 100 to 300 ohm
0.1 C

15 23 HW 2014/12/02 COMPAL Reserve USB power switch for S/B on M/B side Reserve US3, CS13, CS14, CS6 and RS20 0.1
16 18 HW 2014/12/03 COMPAL For support BT funciton WLAN card Add RM21 for support BT WLAN CARD, reserve RM11, RM12, RM13 for debug 0.1
17 21 HW 2014/12/22 COMPAL JTP1 pin swap for Tp module imformation error Swap JTP1 pin define 0.2
Change DL1, LS1 and LS2 Bom structure from EMI@ to @EMI@
18 16, 22 EMI 2014/12/22 COMPAL For EMI requested 0.2
and chage RS6, RS7, RS8, and RS9 from @EMI@ to EMI@
19 23 HW 2014/12/22 COMPAL BT function fail, pin connected error Swap USB20_BT_P & USB20_BT_N 0.2
20 15 HW 2014/12/22 COMPAL HDMI function fail, pin connected error Swap HDMI_R_CK- & HDMI_R_CK+, HDMI_R_D1+ & HDMI_R_D1- 0.2
21 22, 23 HW 2014/12/24 COMPAL ME Z-high interfere Change CS4, CS14 from SF000006900 to SF000006R00 0.2
22 HW 2014/12/24 COMPAL change o ohm to short pad change RX9, RX10, RL1, RM1, RA3, RA4, RA1, RA2, RA5, RB7, RB4, RO1, RO4, RX7, RC76, RC77, 0.2
RC48, RC70, RC74, RC80 to short pad
change RX12, RX13, RL5, RL7, RA21, RA24, RA26, RA28, RS6, RS7, RS8, RS9 to short pad
23 EMI 2015/01/05 COMPAL change o ohm to short pad for EMI requested 0.2
Change LY1, LY2, LY3 and LY4 BOM structure form EMI@ to @EMI@
24 15 EMI 2015/01/05 COMPAL change BOM structure Change RY12, RY15, RY18, and RY21 form @EMI@ to EMI@
Change RY11, RY13, RY14, RY16, RY17, RY19, RY20, RY22 form 0 ohm @EMI@ to 8.2 ohm EMI@ 0.2
25 5, 7 ESD 2015/01/05 COMPAL add ESD cap for ESD requested Add CC20, CC94, CC95 and change CD2 form 0.1U to 100P for ESD 0.2
26 8 HW 2015/01/07 COMPAL prevent the power leakage issue. Chaneg RC29 and RC33 bom structure form 14@ to @ 0.2
27 20 HW 2015/01/09 COMPAL prevent the antenna effect Add CB13, CB14 0.1u 0402 0.2
28 22 DFB 2015/01/10 COMPAL add test point for DFB requested Add T22 (JODD1.11) 0.2
B B
29 21 HW 2015/01/14 COMPAL add screw hole conneted to GND add H13, H14 conneted to GND 0.2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


2014/11/07 2015/11/07 Title
Issued Date Deciphered Date HW RIR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-C771P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, January 14, 2015 Sheet 25 of 34

5 4 3 2 1
5 4 3 2 1

HCB2012KF-121T50_0805
@EMI@ PL100 HCB2012KF-121T50_0805
1 2
VIN EMI@ PL102
1 2
PF100 HCB2012KF-121T50_0805 VMB
JDCIN1 7A_24VDC_429007.WRML EMI@ PL101 VMB2 PF101 HCB2012KF-121T50_0805
1 APDIN 1 2 APDIN1 1 2 JBATT1 7A_24VDC_429007.WRML EMI@ PL103
1

1000P_0402_50V7K

1000P_0402_50V7K
100P_0402_50V8J

100P_0402_50V8J
2 1 VMB2 1 2 1 2
2 1 BATT+

@EMI@ PC100

EMI@ PC101

EMI@ PC102

@EMI@ PC103
3 2
3 4 2 3
4 3

1
5 4 EMI@ PC104 @EMI@ PC105
5 4 5 1000P_0402_50V7K 0.01U_0402_25V7K
ACES_88299-0510 5 6

2
D @CONN@ 6 7 D
7 8
8 9
GND 10
GND 11
GND 12 PR102
GND 100_0402_1%
SUYIN_125022HB008M200ZL EC_SMDA 1 2
EC_SMB_DA1 [20,27]
@CONN@ PR104
100_0402_1%
EC_SMCA 1 2
EC_SMB_CK1 [20,27]
@ PR105
@PR105
200K_0402_1%
1 2
+3VALW
PR107
200K_0402_1%
1 2
+3VLP
PR109
10K_0402_5%
1 2
VCIN1_BATT_TEMP [20,27]

PH7 under CPU botten side :


CPU thermal protection at 93 +-3 degree C
C Recovery at 56 +-3 degree C C

+EC_VCCA
[20,27] ADP_I

16.5K_0402_1%
1
[20,27] VCOUT1_PROCHOT#

10K_0402_1%

PR110
1

2
30K_0402_1%
PR111

PR112

2
@ [20] VCIN0_PH1

1
[20] VCIN1_ADP_PROCHOT PH100

2
100K_0402_1%_TSM0B104F4251RZ

PR113

2
100K_0402_1%

1
B
RTC ECAGND

B
VCIN1 setting
Trigger point is 1.0V at 65W
+CHGRTC Recovery point is 0.692V at 45W
PR115
1K_0603_5%
1 2
PD100
+3VLP
S SCH DIO BAS40CW SOT-323
2 +CHGRTC_R
+RTCVCC 1 JRTC1
3 PR116
1K_0603_5%
1 2 1 2
+ -
ADP_SET1 ADP_SET2

LOTES_AAA-BAT-054-K01 45W adapter


CONN@ 0 0

60W adapter
1 0

90W adapter
A
0 1 A

135W adapter 1 1

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2011/06/15 Deciphered Date 2013/09/17 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P36-PWR-One Shut
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Bay Trail M LA-C771P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, January 15, 2015 Sheet 26 of 26
5 4 3 2 1
5 4 3 2 1

1
D
Rds(on) = 35mohm max
PR200 2
1 2 G
Vgs = 20V
S PQ200 max Power loss 0.22W for 90W;0.12W for 65W system B+ Vds = 30V
BA+

3
1M_0402_1% PR201 2N7002KW _SOT323-3 PQ203
P3 CSR rating: 1W ID = 7.7A (Ta=70C) AO4406L_SO8
1 2 VACP-VACN spec < 80.64mV
3M_0402_5% 8 1
PQ201 PQ202 7 2
MDU1512RH_POW ERDFN56-8-5 AON7506_DFN33-8-5 PR202 6 3
1 1 0.01_1206_1% EMI@ PL200 5
2 2 1UH_NRS4018T1R0NDGJ_3.2A_30%
5 3 3 5 1 4 1 2
VIN

4
PC201
2 3
1 2

0.047U_0603_25V7M
4

4
D D
Rds(on) typ=35mohm max

1000P_0603_50V7

2200P_0402_50V7K
PC202
0.022U_0603_25V7K

68P_0402_50V8J
Vgs=20V

4.02K_0402_1%
1

10U_0805_25V6K

10U_0805_25V6K
PC200

EMI@ PC203
PR211

EMI@ PC204

PC205

PC206
1

1
Vds=30V

PR210
4.7_0603_1%

1
Id=10.6A (Ta=70C)

4.02K_0402_1%
2

PC207 PC208 PC209

PR212

PR213
2

10_0402_1%
0.1U_0603_25V7M 0.01U_0402_25V7K

2
1 2 1 2 1 2

2
0.1U_0402_25V6

BATDRV

BATSRC
PR209
1 2 ACDRV

4.02K_0402_1%

CMSRC

VIN PR214
ACP ACN
PD1
10_1206_5% @ PC210
VIN 3 1 2
422K_0402_1%
1

1 1 2 Rds(on) = 30mohm max

AON7408L_DFN8-5
PR215

2 ACDRV 1000P_0402_50V7K
BA+ 1U_0603_25V6K PC211
Vgs = 20V
1 2 BQ24780VDD PC213 Vds = 30V
S SCH DIO BAS40CW SOT-323 ID = 7A (Ta=70C)
2

5
C C
PU1 2.2U_0805_25V6K Support max discharge 6A(55W)
1 2 Power loss: 0.36W

ACDRV

ACP

ACN
28 CSR rating: 1W
VCC

PQ204
2200P_0402_50V7K
66.5K_0402_1%

PR217 VSRP-VSRN spec < 81.28mV


1

1
PC212

CMSRC 3 24
CMSRC REGN PR220 PC214 1 2 4
PR216

6 0_0603_5% 0.047U_0603_25V7M 7X7X3


BATT+
2

@ PR218 0_0402_5% ACDET 25 BST_CHG 1 2 1 2 0_0603_5%


BTST Isat: 6.5A
[20,26] EC_SMB_DA1 1 2 EC_SMB_DA1_1 11 DCR: 33mohm
2

SDA
Power loss:0.297W

3
2
1
[20,26] EC_SMB_CK1 @ PR219 0_0402_5% 12 26 DH_CHG PR221
1 2 EC_SMB_CK1_1 SCL HIDRV PL201 0.01_1206_1%
support Turbo boost : 2200P VCIN1_AC_IN 5 4.7UH_PCMB063T-4R7MS_5.5A_20%
[20,26] ADP_I ACOK 27 LX_CHG 1 2CHG 1 4
no support Tirbo boost : 0.1u PHASE
1 2 7
IADP 2 3

AON7408L_DFN8-5
5
100P_0603_50V8 PC215 DCHG_I 8 23 DL_CHG
IDCHG LODRV

1
PC217 0.1U_0402_25V6

4.7_1206_5%
1 2 1 2 PMON 9
PMON

PQ205

PR223
@ PR224 0_0402_5% PR222 316K_0402_1%
100P_0603_50V8 @ PC216 1 2 10 22 1 2 SRP SRN

10U_0805_25V6K

10U_0805_25V6K
/PROCHOT GND +3VLP 4

2
PR225 100K_0402_1% @

1
1 2

PC218

PC220
13 21

680P_0603_50V7K
CMPIN ILIM

1
PMON:

3
2
1

2
[20,26] VCOUT1_PROCHOT# 14

PC219
BQ24780 need contact capacitor to GND PR226 10_0402_1%
CMPOUT 20 1 2
BQ24780S need contact the pull down resistance (TBD)

2
SRP PR227 10_0402_1%
[20,26] VCIN1_BATT_TEMP 15 19 1 2 @
BQ24780VDD /BATPRES SRN
B /BATPRES B

logic high: above 2.1V 16 18 PC221


/TB_STAT BATDRV
logic low: under 0.8V
1

29 17 1 2
PR228 PWPD BATSRC
100K_0402_1% 0.1U_0402_25V6

BATDRV
BATSRC
BQ24780RUYR_W QFN28_4X4
2

[20,8] VCIN1_AC_IN VCIN1_AC_IN


**Design Notes**

0.1U_0402_25V6

0.1U_0402_25V6
1

1
PC222

PC223
PR229 For 65 /90W system, 3S1P/3S2P battery
120K_0402_1%
Maximum Charging current 3A

2
Maximum Battery discharge power 55W
#Register Setting
Module model information
2

1. 0X12 bit2 set 1 (default 0) to enable turbo boost function


2. Disable turbo when AC only
#Circuit Design BQ24780_V1.mdd for dual layer
1. ILIM pull high voltage need base on 3/5V enable control Vin Dectector
2. Use 7X7 choke and 3X3 H/L side MOSFET Min. Typ Max.
Charge current 3A L-->H 17.16V 17.63V 18.12V
Power loss : 1.79W (H/S=0.227W,L/S=1.2738W,Choke=0.297W)
H-->L 16.76V 17.22V 17.70V
Power density : 0.61 (23X16)
#Protect function
1. ACOVP : VCC voltage > 24V VILIM = 20*ILIM*Rsr
2. Charger timeout : No communication within 175s(default) ILIM = 3.3*100/(316+100)/20/0.01
3. ACOC : 3.33 X Input current DAC setting (default:Disable) = 3.966 A
4. CHGOCP : based on charge current setting
A A
5. BATOVP : 103-106%
6. BATLOWV : 2.6V
7. TSHUT : 155C
8. IFAULT HI : 750mV (default:Disable)
9. IFAULT LOW : 230mV (default)
Security Classification Compal Secret Data Compal Electronics, Inc.
Title
Issued Date 2013/11/05 Deciphered Date 2015/11/05
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BQ24780
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Bay Trail M LA-C771P
Date: Thursday, January 15, 2015 Sheet 27 of 27
5 4 3 2 1
A B C D E

1 1

PR301
499K_0402_1%
ENLDO_3V5V 1 2
3.3V LDO 150mA~300mA B+

1
150K_0402_1%
PU301 PC302 PR302
B+

PR303
EMI@ PL301 7 1 3V5V_EN 0.01U_0402_25V7K 1K_0402_5%
HCB2012KF-121T50_0805 EN2 EN1 1 2 1 2

2200P_0402_50V7K
1 2 3V_VIN 8 3 3V_FB
IN FB PR304 PC304

2
10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6
6 1
BST_3V 2 1 2
BS

1
EMI@ PC303

PC306
2.2_0603_5%
@EMI@ PC301

PC305
0.1U_0603_25V7K PL302
1.5UH_PCMC063T-1R5MN_9A_20%
2

2
@ 10 LX_3V 1 2
LX +3VALWP

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
9 4
GND OUT

@EMI@ PR305
1

1
PC307

PC308

PC309

PC310
680P_0603_50V7K 4.7_1206_5%
2 5
[20,30,31] 3V/5VALW_PG PG LDO +3VLP

1
SYX196BQNC_QFN10_3X3

2
1 2 PC311
+3VLP

1 3V_SN
4.7U_0603_6.3V6M

2
Check pull up resistor of SPOK at HW side PR314 100K_0402_5%

@EMI@ PC312
2 2

2
PR306
2.2K_0402_5%
Vout is 3.234V~3.366V
1 2
[20] EC_ON TDC=6A
@PR307
@ PR307
1 2
[20] VCOUT0_MAIN_PWR_ON 0_0402_5%
@PJ301
@ PJ301
+3VALWP 1 2 +3VALW
1 2
JUMP_43X118
3V5V_EN
1M_0402_1%

4.7U_0402_6.3V6M
1

1
PR308

PC313
2
2

B+ EMI@ PL303 EN1 and EN2 dont't floating


HCB2012KF-121T50_0805
1 2 5V_VIN

Vout is 4.998V~5.202V
2200P_0402_50V7K
10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6

PU302 PC317 PR309


8 1 3V5V_EN 6800P_0402_25V7K 1K_0402_5%
TDC=6A
IN EN 1 2 1 2
1

1
PC314

PC315

EMI@ PC316

@EMI@ PC319

3 3 5V_FB PR310 PC318 3


FB 2.2_0603_5% 0.1U_0603_25V7K
6 BST_5V 1 2 1 2
2

@ BS
PL304
1.5UH_PCMC063T-1R5MN_9A_20%
9 10 LX_5V 1 2 +5VALWP
GND LX

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
VCC_3.3V 5 4
VCC OUT
1

680P_0603_50V7K 4.7_1206_5%

1
@EMI@ PC326 @EMI@ PR311

PC321

PC322

PC323

PC324
2 7
PG LDO VL
1

PC320
4.7U_0603_6.3V6M

SYX196C1QNC_QFN10_3X3

2
1 5V_SN

@ PJ302
2

2
1

PC325
4.7U_0603_6.3V6M

+5VALWP 1 2 +5VALW
1 2
JUMP_43X118
2

5V_VIN
2
1

PR312 5V LDO 150mA~300mA


560K_0402_5%
2

VCIN1_BATT_DROP [20]
1

4 PR313 PC327 4
1000P_0402_25V8J
2

105K_0402_1%
2

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+3VALW/+5VALW
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Bay Trail M LA-C771P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, January 15, 2015 Sheet 28 of 28
A B C D E
A B C D

Module model information


RT8207P_V1.mdd For Single layer
RT8207P_V2.mdd For Dual layer

1 1

Pin19 need pull separate from +1.35VP.


If you have +1.35V and +0.675V sequence question, 0.675Volt +/- 5%
B+
EMI@ PL401
HCB2012KF-121T50_0805
you can change from +1.35VP to +1.35VS. TDC 0.7A
1 2 +12.6VB_DDR PR401 Peak Current 1A
2.2_0603_5%
BST_DDR_R 1 2 BST_DDR

0.1U_0402_25V6

10U_0805_25V6K

10U_0805_25V6K
2200P_0402_50V7K
+1.35VP

1
@EMI@ PC401

EMI@ PC402

PC403

PC404
UG_DDR +0.675VSP

2
LX_DDR

10U_0603_6.3V6M

10U_0603_6.3V6M
1

1
PC405

5
0.1U_0603_25V7K

PC406

PC407
16

17

18

19

20
2
PU303

2
VLDOIN
BOOT

VTT
PHASE

UGATE
PQ401 21
PAD
AON7408L_DFN8-5 4 LG_DDR 15 1
LGATE VTTGND

14 2
PL402 PR402 PGND VTTSNS

1
2
3
1UH_11A_20%_7X7X3_M 27K_0402_1%
2 1 2 1 2 CS_DDR 13 3 2

+1.35VP PC408 CS RT8207PGQW_WQFN20_3X3 GND


1

1U_0402_10V6K

5
1 2 12 4 VTTREF_DDR
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

@EMI@ PR403 PR404 VDDP VTTREF


1

4.7_1206_5% 5.1_0603_5%
PC409

PC410

PC411

PC412

PC413

PC414

1 2 VDD_DDR 11 5
+5VALW +1.35VP
1 2

VDD VDDQ

1
PGOOD
2

PQ402 4 PC415
+5VALW PR405

TON
1
@EMI@ PC417 0.033U_0402_16V7K

FB
S5

S3

2
680P_0402_50V7K AON7406L_DFN8-5 PC416 1 2
2

1U_0402_10V6K 5.1_0603_5%

10

6
1
2
3
1 2
+1.35VP

FB_DDR
EN_DDR

EN_0.675VSP
TON_DDR
PR406 100K_0402_5%
PR407
[5] DDR_PWROK 1 2 +1.35VP
PR408 470K_0402_1%
+12.6VB_DDR 1 2
8.06K_0402_1%
MOSFET: 3x3 DFN

1
H/S Rds(on): 27mohm(Typ), 34mohm(Max)
Idsm: 7.5A@Ta=25C, 5.5A@Ta=70C @ PR410 PR409
0_0402_5% 10K_0402_1%
1 2
[20] SYSON

2
Mode Level +0.675VSP VTTREF_1.35V L/S Rds(on): 19mohm(Typ), 23.5mohm(Max)
S5 L off off Idsm: 11A@Ta=25C, 8.8A@Ta=70C

1
@ PC418
S3 L off on 0.1U_0402_10V7K
S0 H on on

2
Choke: 7x7x3
Rdc=6.7mohm(Typ), 7.4mohm(Max)
Note: S3 - sleep ; S5 - power off @ PR411
0_0402_5%
Switching Frequency:540kHz 1 2 @ PJ401
[20,24] SUSP# +1.35VP 1 2 +1.35V
Ipeak=8A 1 2

1
3
Iocp~9.6A JUMP_43X118 3

@ PC419 @ PJ402
OVP: 113%~120% 0.1U_0402_10V7K 1 2

2
1 2
VFB=0.75V, Vout=1.3545V JUMP_43X118

PJ403
@
1 2
+0.675VSP 1 2 +0.675VS
JUMP_43X39

4 4

Security Classification Compal Secret Data


Issued Date 2011/06/15 Deciphered Date 2013/09/17 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-DDR(RT8207)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Bay Trail M LA-C771P
Date: Thursday, January 15, 2015 Sheet 29 of 29
A B C D
5 4 3 2 1

D D

C C

@ PJ501

1 2
+1.05VALWP 1 2 +1.05VALW
JUMP_43X79

+3VALW @ PR501
0_0402_5%
+1.05VSP_ON 1 2
3V/5VALW_PG [20,28,31]
1

0.1U_0402_16V7K

1
@ PR502
PC501
1

100K_0402_5% PR503
1M_0402_5%
@
Note:Iload(max)=2.5A
2

PU501
9
1 PGND 8
FB SGND
@ PJ502 2 7
PG EN PL403
+3VALW 1 2 3 6 LX_1.05V 1 2
1 2 IN LX 1UH_2.8A_30%_4X4X2_F +1.05VALWP
1

4 5
68P_0402_50V8J

JUMP_43X79 PGND NC
1

PC502
@EMI@ PR504
4.7_0603_5%

PR505
PC503
22U_0603_6.3V6M

1
SY8003ADFC_DFN8_2X2
Rup 22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
15K_0402_1%
PC504

PC505

PC506

PC507
2

B B
2

2
FB_1.05V
1
@EMI@ PC508
1

FB=0.6V PR506
680P_0402_50V7K

Note:Iload(max)=3A 20K_0402_1%
Rdown
2

Note:
When design Vin=5V, please stuff snubber
to prevent Vin damage
Vout=0.6V* (1+Rup/Rdown)

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2011/06/15 Deciphered Date 2013/09/17 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.05VS/1.0VALW
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Bay Trail M LA-C771P
Date: Thursday, January 15, 2015 Sheet 30 of 30
5 4 3 2 1
A B C D

+3VALW +5VALW

1
1 1

1
PC601

1
1U_0402_6.3V6K
JUMP_43X79

2
@ PJ601

2
2
PU601
AP7175SP-13 SO-8EP

1
PC602 6
4.7U_0603_6.3V6K 5 VCNTL 3
PR601 9 VIN VOUT 4
+1.8VALWP

2
100_0402_5% VIN VOUT

12.7K_0402_1%

0.01U_0402_25V7K
1 2 8
[20,28,30] 3V/5VALW_PG EN

1
1 2 7 2
+3VS

GND
POK FB

22U_0603_6.3V6M
PR603

PC604
1

0.1U_0402_16V7K
@ PR602 Rup

1
PC603
PR604 100K_0402_5%

PC605
47K_0402_5%

2
2 2

10K_0402_1%
PR605
Rdown

2
Vout=0.8V* (1+Rup/Rdown)

PJ602
3
@ 3

+1.8VALWP 1 2 +1.8VALW
1 2
JUMP_43X79

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2011/07/08 Deciphered Date 2013/09/17 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-1.8VALW
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Bay Trail M LA-C771P
Date: Thursday, January 15, 2015 Sheet 31 of 31
A B C D
A B C D

+SOC_VNN

PC702 1 2 10U_0603_6.3V6M
PC703 1 2 10U_0603_6.3V6M
Module model information

1
@ PC705 PC704 1 2 10U_0603_6.3V6M
1000P_0402_50V7K
[10] VGFX_VSNS PC706 1 2 1U_0402_6.3V6K
ISL95833-BTM_V1A.mdd for IC portion Design for BT-M 4.5W CPU

2
PC707 1 2 1U_0402_6.3V6K
PC708 1 2 1U_0402_6.3V6K

1
ISL95833-BTM_V1B.mdd for SW portion [10,32] VCORE_GSNS PC709 @ PC710 1 2 0.1U_0402_16V7K
0.01UF_0402_25V7K @ PC711 1 2 0.1U_0402_16V7K

2
@ PC712 1 2 0.1U_0402_16V7K

CPU_B+

PC713 PC714
1
100P_0402_50V8J 470P_0402_50V7K +SOC_VNN 1
PC716 1 2 1 2 1 2
6800P_0402_25V7K PR701 PC715 1 2 10U_0603_6.3V6M

10U_0805_25V6K

10U_0805_25V6K
PC719 499_0402_1% PC717 1 2 10U_0402_6.3V6M

2200P_0402_50V7K
1 2 1000P_0402_50V8-J PC718 1 2 10U_0603_6.3V6M

EMI@ PC720
1

1
1 2 1 2 1 2 PC723 1 2 10U_0603_6.3V6M

2K_0402_1%

PC721

PC722
PR702 PR703

PR704

1
137K_0402_1% 2.05K_0402_1%
Close GFX choke

2
PR708
PH702 PR706 0_0603_5%

21K_0402_1%
PR705

1
10K_0402_1%_B25/50 3370K 316_0402_1% 1 2UGATEG1-1

PR707
2K_0402_1%
VSUMG- 1 2 UGATEG1

1 2
1
PC725 PR709 0.36uH DCR= 1.4±5% m ohm

1
0.1U_0402_25V6 2.2_0603_5%
PC724 1 2 1 2 BOOTG PL702
+3VALW

D1

D1

D1

G1
2
330P_0402_50V7K 0.36UH_PDME064T-R36MS_24A_20% +SOC_VNN

2
11K_0402_1%

0.047U_0402_25V7K
1 2

0.1U_0402_25V6K
10 9 PHASEG 1 4

2.61K_0402_1%

1.91K_0402_1%
D1 D2/S1

1
PC727
PR711

PC726
2 3
PR15 and PR27
PR710

BOOTG PQ701

G2
S2

S2

S2
2

1
AON7934_DFN3X3A-8-10
27.4K ohm for 100 degree 1 1

2
UGATEG1-1 PR713
2

1
@EMI@ @ PC786 + + PC785
61.9K ohm for 110 degree VSUMG+ PHASEG 4.7_1206_5% PR714 330U_D2_2V_Y
LGATEG 3.65K_0603_1% 330U_D2_2V_Y

PR712

1 2
2 2
Close GFX L/S MOS LGATEG +5VALW PC731

2
PR715 PU602 @EMI@

33

32

31

30

29

28

27

26

25
Alert assert 27.4K_0402_1% 680P_0402_50V7K

2
+SOC_VNN

VSUMG+
threshold: 100C

VSUMG-
PAD

ISUMPG

ISUMNG

RTNG

FBG

COMPG

PGOODG

BOOTG

UGATEG
1 2 NTCG_1

1U_0402_6.3V6K
PH703 PR716 PC732 1 2 22U_0603_6.3V6M

1
470K_0402_5%_B25/50 4700K 3.83K_0402_1% PC734 1 2 22U_0603_6.3V6M

1
1 2 1 2 NTCG 1 24 PR718 PR719 PC735 1 2 22U_0603_6.3V6M
@ PR717 NTCG PHASEG @ 0_0402_5% 1_0402_5% PC736 1 2 22U_0603_6.3V6M

PC733
1 2 2 23

2
[20] VR_ON VR_ON LGATEG

2
0_0402_5% 1 PR720 2 VR_SVID_CLK_R 3 22
2 2
[8] VR_SVID_CLK SCLK VCCP
20_0402_1%
PR721 VR_SVID_ALERT# 4 ISL95833HRTZ-T_TQFN32_4X4 21 CPU_B+
[8] VR_SVID_ALERT# ALERT# VDD
16.9_0402_1% EMI@ PL701
1 2 VR_SVID_DATA_R 5 20 HCB2012KF-121T50_0805
[8] VR_SVID_DATA SDA PWM2 PC738 1 2 B+

1
6 19 LGATE1 1U_0402_6.3V6K
[20] VR_HOT# VR_HOT# LGATE1
1

0.1U_0402_25V6
10U_0805_25V6K

10U_0805_25V6K
NTC 7 18 PHASE1

@EMI@ PC740
2
NTC PHASE1 +
For VR_HOT#, already @ PR722 PC701 +SOC_VNN
3.83K_0402_1%
1

1
33U_25V_NC_6.3X4.5

PGOOD
1 2 8 17

PC739

PC741
BOOT1
pull high at PWR side.
ISUMN
ISUMP

COMP
ISEN2 UGATE1
ISEN1

@ PC742 1 2 22U_0603_6.3V6M
0_0402_5% RTN
1

@ PC744 2 PC743 1 2 22U_0603_6.3V6M


FB
499_0402_1%

73.2_0402_1%

73.2_0402_1%

2
1

47P_0402_50V8J PC745 1 2 22U_0603_6.3V6M


PR723

UGATE1-1 PC746 1 2 22U_0603_6.3V6M


PR724

PR725

PR726

+5VALW
2

10

11

12

13

14

15

16
NTC_1 PC747 1 2 22U_0603_6.3V6M
470K_0402_5%_B25/50 4700K

BOOT1 PR728 @ PC748 1 2 22U_0603_6.3V6M


0_0603_5% @ PC749 1 2 22U_0603_6.3V6M
2

@ PR122 UGATE1 1 2 UGATE1-1


VGATE [20]
0_0402_5% PR727
PH704

1 2 27.4K_0402_1%
+1.05VS 1 2 +3VALW PC751 PR730 0.36uH DCR= 1.4±5% m ohm

1
0.1U_0402_25V6 2.2_0603_5%
2

2
1

@ PR123 1.91K_0402_1% PR729 1 2 1 2 BOOT1


VR_Hot# assert

D1

D1

D1

G1
@ PC750 PL703 +SOC_VCC
0_0402_5% 0.1U_0402_16V7K 0.36UH_PDME064T-R36MS_24A_20%
threshold: 100C
2

1 2 10 9 PHASE1 1 4
+1.05VALW D1 D2/S1

1
2 3
Close CPU L/S MOS PQ702 PR731

G2
S2

S2

S2
AON7934_DFN3X3A-8-10 @EMI@ 1 1
4.7_1206_5%

8
PC752 PR733 PR732 + PC787 + @ PC782

2
330P_0402_50V7K 2K_0402_1% 64.9K_0402_1% VSUM+ 330U_D2_2V_Y 330U_D2_2V_Y

1
1 2 1 2 1 2 LGATE1

2.61K_0402_1%
1
PR735 2 2

1
PC755 3.65K_0603_1%

PR734
11K_0402_1% @EMI@
3
PC756 PC757 680P_0402_50V7K 3
2K_0402_1%

0.047U_0402_25V7K

2
1

470P_0402_50V7K 100P_0402_50V8J
PR737

2
1

1
0.1U_0402_25V6K

1 2 1 2 1 2
PC758
280_0402_1%

PR736
PR738

PC759

499_0402_1%
1

Close CPU choke


2

PC760 PH701 VSUM+


PR739
2

PR740 10K_0402_1%_B25/50 3370K


6800P_0402_25V7K
1

1.78K_0402_1% 1000P_0402_50V8-J
PC761

1 2 1 2 1 2
2

PR741 VSUM-
2

137K_0402_1%
VSUM-
@ PC762
330P_0402_50V7K
1 2

[10] VCORE_VSNS 1 2

PC763
0.01UF_0402_25V7K
[10,32] VCORE_GSNS

+SOC_VCC
+SOC_VCC +SOC_VCC
PC764 1 2 22U_0603_6.3V6M
+SOC_VCC @ PC765 1 2 22U_0603_6.3V6M PC766 1 2 10U_0603_6.3V6M PC767 1 2 22U_0603_6.3V6M
PC768 1 2 22U_0603_6.3V6M PC769 1 2 22U_0603_6.3V6M
PC770 1 2 10U_0603_6.3V6M @ PC771 1 2 22U_0603_6.3V6M PC772 1 2 4.7U_0603_10V6K PC773 1 2 22U_0603_6.3V6M
4
PC774 1 2 10U_0603_6.3V6M @ PC775 1 2 22U_0603_6.3V6M PC776 1 2 4.7U_0603_10V6K 4

PC777 1 2 10U_0603_6.3V6M PC778 1 2 22U_0603_6.3V6M


PC779 1 2 10U_0603_6.3V6M PC780 1 2 22U_0603_6.3V6M PC781 1 2 2.2U_0402_6.3V6M
PC783 1 2 22U_0603_6.3V6M PC784 1 2 2.2U_0402_6.3V6M

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-CPU_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Bay Trail M LA-C771P
Date: Thursday, January 15, 2015 Sheet 32 of 32
A B C D
5 4 3 2 1

Version change list (P.I.R. List)


Item Reason for change PG# Modify List Date Phase

1
PR601_0_0402 change PR601_100_0402 31 HW 需需 SIT

2 修修PC207 from1uF to 0.1uF,修修PC209 from 0.1u to 0.01uF 27 線線修修 SIT

3 pc203改EMI@上上 27 EMI 需需
SIT
D
4 unpop cap from PC785 to PC786 32 ME 需需 SIT D

5 change PR410,PR411,PR501,PR218,PR219,PR224 to short pad 27,29,30 HW 需需 SIT

6 change PC715、PC718、PC723、PC770、PC774、PC777、PC779 From 0402 to 0603 線線修修 SIT


32

7
8

10

11

12

13

14 33

C C
15 38

16 38

17 31

18 31

19 35

20 35

21 38

22 35

B B

23 32 2014/4/4 SVT

33

34

24 38 2014/4/14 SVT

25 38 2014/4/14 SVT

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2011/06/15 Deciphered Date 2013/09/17 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PIR (PWR)
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Bay Trail M LA-B261P
Date: Thursday, January 15, 2015 Sheet 33 of 33
5 4 3 2 1
5 4 3 2 1

1
+3VLP UA1,EC, RTC
100mA (4mils)
JPWRB1.LED

+3VALW
JP1,JPWRB1.LED 100mA (4mils)

LED,TP, 100mA (4mils)


+3VALW_SOC HDD
RC76 SOC 50mA
D D

Card 400mA (16mils)


T=6613mA (265mils)
+3V_LAN Reader
4538mA (182mils) RL1 LAN 370mA (15mils)
100mA (4mils)
1000mA (40mils) CPU 33mA (4mils)
975mA (40mils) +3VALW_EC DDR 25mA (4mils) I/O port
RB1 EC 100mA (4mils)
2 PU301 +3VS_WLAN CPU
PU501 4075mA (165mils) UQ3 JWLAN1 1500mA (60mils)
SYX196BQNC 5 RM1
AC (EC_ON) +1.05VALW +1.05VS 21
Adapter 19V 3V/5VALW_PG 6
3V5V_EN EN Vin
360mA +3VDD_CODEC
EN 3750mA (150mils) CODEC 750mA (30mils)
3 RA1 750mA (30mils)
+3VALW
SY8003DFC SUSP 180mA (8mils)
Vin EN P23 1500mA ( 60mils)
Vin P29 +3VS_TCM
RW1 TCM(TPM) 50mA (4mils)
PGOOD P28
UQ1
24 +3VS 4538mA (182mils) QX2, +3VS_CMOS INT.
DC +3VALW 180mA (8mils)
Battery
3V/5VALW_PG RX10 Camera
Vin1
PU1 5
Charger B+
19
SUSP# +LCDVDD
ON1 UX1 LCD 1500mA ( 60mils)
C BQ24780RUYR C

P27 TPS22966DPUR 25
+5VALW +5VS
Vin1 +5VS_HDD
RO4 HDD 2000mA (80mils)
SUSP# 6800mA (272mils) /245mils
ON1
P23 +5V_ODD
19 ODD 2000mA (80mils)
RO1

+5VALW
US2 84mA (4mils) +HDMI_5V_OUT
UY1 HDMI 1000mA (40mils)
+5VALW 2800mA
USB2.0*2 1500mA (60mils) +5VS_PVDD
CODEC 1050mA (42mils) (112mils)
RA3
T=11050mA (442mils)
+USB3_VCCA
USB2.0*1 2750mA (110mils) +5VDDA_CODEC
8300mA (332mils) /280 mils US1 CODEC 750mA (30mils)
USB3.0*1 RA4
2750mA (110mils)
810mA (32mils) 810mA (32mils)
+5VALW 4 T=975mA (40mils) TP_VCC
165mA (7mils) UA1 Touch 8mA (30mils)
PU601 EC R2 Pad
2 +1.8VALW UQ2 +1.8VS
PU302
7 Vin1
Vin
B
(EC_ON) SYX196CQNC B
APL5930KA 19
23
3V5V_EN 3V/5VALW_PG SUSP#
EN EN ON1
P30
5 TPS22966DPUR
Vin +1.35V +1.35VS
VL Vin1
PGOOD P28 420mA (17mils)
LED 300mA (12mils)
SUSP# 22
ON1 P23
T=5670mA (267mils)
14
PU303 DDR 4000mA (160mils) 19
+1.35V 1250mA (50mils)
Vin DDR

Aditya11ttt
13 RT8207PGQW 20 8 ON/OFF#
SYSON DDR 1000mA (40mils)
EN PGOOD P28 +0.675VS 9 EC_RSMRST#
SUSP#

19 15 10 PBTN_OUT#
DDR_PWROK 17
PU602
11 PMC_SLP_S4#
+SOC_VCC 12000mA (480mils)
Vin ISL95833HRTZ
A
12 PMC_SLP_S3# A

VR_ON (CPU-CORE) +SOC_VNN 14000mA (560mils)


EN
PGOOD P31 26 KBRST#
16 16

18 27 PMC_CORE_PWROK
VGATE
Security Classification Compal Secret Data Compal Electronics, Inc.
+INVPWR_B+ 28 PMC_PLTRST# Issued Date 2012/04/03 Deciphered Date 2014/12/31 Title
LCD 2000mA (80mils) Power Block Diagram
RX9 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-C771P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, January 14, 2015 Sheet 34 of 34
5 4 3 2 1

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