The University of Chakwal

3rd Semester Mid Examination 2K19 in Electronics Engineering

Paper: EE-213 Digital Logic Design

Time: 60 Mins Max Marks: 40

NOTE: Attempt all questions and attempt all parts of a question in a sequence.

Q # 1: Covers CLO-01, C3.

i) Solve the following SOP expression to find an equivalent POS expression. (5)

A'B'C' + A'BC' + A'BC + AB'C + ABC

ii) Change the following function F into its complement. (5)

F = x(y'z' + yz)

Q # 2: Analyze the combinational circuit shown in figure, (CLO-02, C4) (15)

(i) Derive the Boolean expression for T1 through T4. Evaluate the outputs F1 and F2 function of
the four inputs.

(ii) List the truth table with 16 binary combinations of the four input variables. Then list the
binary values for T1 through T4 and outputs F1 and F2 in the table.

(iii) Plot the Boolean output functions obtained in part (ii) on maps, and show that the
simplified Boolean expressions are equivalent to the ones obtained in part (i).

Q # 3: Design a combinational circuit with three inputs x, y, z and three outputs A, B, C. When
the binary input is 0, 1, 2, or 3, the binary output is two greater than the input. When the binary
input is 4, 5, 6 or 7, the binary output is three less than the input. (CLO-03, C5) (15)

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