Resolver-Based Motor Control Reference Design With A BLDC Motor and C2000™ MCU

TI Designs: TIDA-01507
Resolver-Based Motor Control Reference Design With a

BLDC Motor and C2000™ MCU
Description Features
The TIDA-01507 reference design is a generic • Up to 200-W Power Stage With Sensorless Field-
development platform for motor-control applications. Oriented Control (FOC)-Based InstaSPIN™
Control for the system comes from the C2000™ Solution or Sensored FOC-Based Resolver for
TMS320F28069M microcontroller (MCU). The 3-phase Brushless DC Motor, Efficiency: > 90% Over Full
BLDC gate driver, DRV8305-Q1 drives a BLDC motor Input Range
whereas the resolver-to-digital converter PGA411-Q1 • 10-, to 18-V Input Voltage Range, 40-A Peak
senses the motor shaft position and velocity. Power Output Current Capability
management integrated circuit (PMIC) TPS65381A-Q1 • Full Protection Features, Includes Overcurrent
supplies the MCU and additional circuits on the board. Protection (OCP), Overvoltage and Undervoltage
Additionally, an isolated Controlled Area Network Protection (OVP, UVP), Overload, Lost Phase,
(CAN) interface allows connection to various host Phase Imbalance, Stall, Start-up Failed, Reverse
systems. Polarity Protection
The implementation of multiple subsystems on a single • Automatic Motor Parameters Identification
printed-circuit board (PCB) allows instant development
start and validation of the in-system performance of • High-Performance Speed Control Includes High
TI's motor control solutions. This reduces learning Trajectory Changes and Speed Reversal Capability
time, speeds up practical development, and reduces Using the InstaSPIN-FOC™ Solution
time-to-market. • Cycle-by-Cycle Overcurrent Limit With Configurable
Threshold for Motor Stall Protection
Resources • Manual, Digital or External Control From Arbitrary-
Waveform Generator (AWG)
TIDA-01507 Design Folder
DRV8305-Q1 Product Folder
• Motor Shaft Angle and Velocity Real-Time
Monitoring Using an Oscilloscope
PGA411-Q1 Product Folder
TPS65381A-Q1 Product Folder Applications
TMS320F28069M Product Folder
• HEV/EV - Inverter & Motor Control
TCAN1042HGV-Q1 Product Folder
• Engine Management - Actuators - eTurbo/Charger
• Engine Management - Actuators - Engine Fan
ASK Our E2E Experts • Electric Power Steering (EPS)
170-W BLDC RESOLVER

ISO
X, Y, Z CAN UART
3 EXC, SIN,
3 CAN UART 6
COS
X, Y, Z
4 4
P12V SPI SPI P5V
6 4
P3V3 PWM GPIO P3V3
6
ADC MCU Resolver
BLDC Driver
P1V8 F28069M Front-End
DRV8305-Q1 4
(C2000) 4×SW PGA411-Q1
P3V3
14 4
JTAG LEDs
12
ADC SPI, ADC
GPIO, BNC
RESET R2R D/A
Converter
10 50Ÿ
Manual External
Control Control
BNC
External
Monitor
P3V3
KL30 (12 V) PMIC P5V

TPS65381A-Q1 P1V8
P12V
TIDUDO9 – July 2018 Resolver-Based Motor Control Reference Design With a BLDC Motor and 1
Submit Documentation Feedback C2000™ MCU
Copyright © 2018, Texas Instruments Incorporated
System Description www.ti.com
An IMPORTANT NOTICE at the end of this TI reference design addresses authorized use, intellectual property matters and other
important disclaimers and information.
1 System Description
Increasing popularity of Hybrid Electric Vehicles (HEV) and Electric Vehicles (EV) calls for highly-efficient
motor drives in various applications. Making all systems more efficient helps to extend the operating range
of the electric vehicle or further reduces fuel consumption in the case of the hybrid electric vehicle.
To achieve tight performance requirements, the designer usually selects the FOC method for controlling a
synchronous or induction motor. The FOC achieves superior dynamic performance including fast
acceleration and deceleration, operates smoothly over the full speed range and generates full torque at
zero speed. This makes it the best fit for automotive applications such as traction inverters where dynamic
performance has direct impact on the driving experience of the vehicle.
The main principle of the FOC scheme is decoupling magnetizing flux and torque into two components
that can be visualized as a vector.
The FOC also has some drawbacks. The control scheme is quite complex and requires mathematical
transformations to be carried out quickly. Additionally, the control loop must determine rotor position using
sensors or rotor position prediction mechanisms. Similar to other closed-loop systems, control loop low
time latency and jitter are the key to success. For the detailed FOC theory of operation and applications,
see Sensorless Field Oriented Control of 3-Phase Permanent Magnet Synchronous Motors, Sensored
Field Oriented Control of 3-Phase Induction Motors, Sensorless Field Oriented Control of 3-Phase
Permanent Magnet Synchronous Motors Using F2833x, and Sensored Field Oriented Control of 3-Phase
Permanent Magnet Synchronous Motors.
Figure 1 shows a typical 3-phase motor control system. The position of current sense resistors (shunts)
may differ. In this case, all shunts are on the low side. This allows for inexpensive operational amplifiers
(op amps) configured as a non-inverting amplifier. Current is estimated (calculated) for control phases
when the bottom switch is open and no current flows through the shunt. Such solution is typical for lower-
power, low-voltage applications.
TIDA-01507
VIN Motor Resolver
DCLINK
PMIC 3× PWM Top
V
MOSFET
Driver W
MCU 3× PWM
Bottom
C I
A S 3x ISENSE
N O AFE
POS. Sensing
Figure 1. Typical 3-Phase Motor Control System
High-end systems use in-phase current sensing. Figure 2-A shows a shunt located in series with the
motor terminal. Current is read-out during all motor control phases but more expensive current-sense
amplifiers (CSA) or isolated amplifiers (see Figure 2-B) are required due to high common-mode voltage
changes during the operation.
2 Resolver-Based Motor Control Reference Design With a BLDC Motor and TIDUDO9 – July 2018
C2000™ MCU Submit Documentation Feedback
www.ti.com System Description
A B C
Shunt Shunt
W W W
+
CSA
To Differential
To ADC ADC or To ADC
Difference AMP
+VCC AGND
Figure 2. Different Variants of Current Sensing in Motor Drive Applications
Alternatively to shunts, an indirect current sensing based on magnetic sensors is used as Figure 2-C
shows. Magnetic sensors provide intrinsic galvanic isolation needed for high-voltage (HV) systems and
eliminate power dissipation on shunts. Drawbacks are lower accuracy, the need for magnetic simulations,
and eventually shielding or a custom magnetic core.
As previously discussed, for the best results the FOC control loop requires a rotor position sensor. Motor
drives use various sensors such as Quadrature Encoder (QEP), Incremental encoder, or Hall-based
sensing, The automotive industry prefers resolvers in most cases due to its robustness, reliability, and
performance.
VR
, VR
VS VS
VC
VC
Figure 3. Resolver as a Rotating Transformer
A resolver uses the principle of a rotating transformer with a single primary winding and two secondary
windings positioned in right angles from each other (see Figure 3). The generated sinewave, VR, excites
the primary winding and creates magnetic flux Φ that is distributed through secondary windings with
respect to the rotor angle ϴ. The rotor angle ϴ is then calculated from the ratio of voltages VS, VC on the
secondary windings as per Equation 1.
System Description www.ti.com
VS sin T u VR u TS (1)
VC cos T u VR u TS (2)
sin T u VR u TS sin T VS
cos T u VR u TS cos T VC (3)
VS V
tan T oT arctan S
VC VC (4)
See Automotive Resolver-to-Digital Converter for Safety Applications or EMC Compliant Single-Chip
Resolver-to-Digital Converter (RDC) Reference Design for more details on resolvers.
Implementation of the power stage depends on the output power capabilities. Lower-power or low-voltage
systems use typical N-FET transistors due to very low on-resistance (RDS(on)) in mΩ or sub-mΩ range.
High-power and high-voltage applications use insulated-gate bipolar transistors (IGBT) being step-by-step
replaced by silicon carbide (SiC) or gallium nitride (GaN) transistors. All these switching components
require external drive circuitry (a driver). The driver usually implements other features too, such as current
sensing, galvanic isolation or diagnostics for safety-relevant applications.
Although the TIDA-01507 has limited output power capabilities, the system architecture, principles and
control algorithms remain practically the same, independent of the output power. For this reason, the
TIDA-01507 is a very convenient tool to start with high-performance motor control development.
1.1 Key System Specifications

Table 1 lists the key system specifications.
Table 1. Key System Specifications

PARAMETER SPECIFICATIONS
DC input voltage 10-18 V, typically 12 V
Maximum input DC current 15 A
Maximum peak output current 40 A
Rated output power 180 W
Inverter switching frequency Typically 15 kHz
Inverter efficiency ≥ 95% (theoretical) at rated load
Power supply for MCU 3.3 V ±5%
Protection Overcurrent, overtemperature, overvoltage, undervoltage, overload, over

speed, lost phase, phase imbalance
ADC voltage reference Internal 3.3 V, external 2.048 V
MCU clock Crystal 20 MHz, PLL 90 MHz
Discrete digital-to-analog converter (DAC) voltage
From 5-V voltage rail
reference
Motor power rating < 200 W
Recommended motor BLDC
Code Composer Studio™ software debug interface, 3 × LED, 1 × manual
User interface
control
Supported resolvers Typically 4 or 7 VRMS, 10-20 kHz
PCB size 100 mm × 80 mm
WARNING
Texas Instruments does not claim any safety specifications for this
design. Components intended for safety-related applications are
used in this design for demonstration purposes only.
www.ti.com System Overview
2 System Overview
The TIDA-01507 is a complete test setup which allows debugging and exploring motor control without a
need for expensive equipment. The main idea is to implement the most important subsystems for motor
control on a single board. Figure 4 shows the design concept using an acrylic base carrier for the PCB
and the motor-resolver assembly. It is possible to use various motor-resolver combinations with minimal or
no design modifications. Section 4.4 describes selected test setups used at Texas Instruments during
development.
Figure 4. System Overview
The PCB-implemented subsystems follow:

• BLDC driver uses the DRV8305-Q1 for motor control. The brushless DC (BLDC) motor can be any
appropriate 3-phase model which operates on 12-V winding voltages. Resolver, Hall effect, or encoder
position sensors can be used to determine motor commutation, but these sensors are not needed if
InstaSPIN or an equivalent sensorless commutation algorithm is used.
• C2000™ Microcontroller adds intelligence to the system and runs the control loop. The subsystem
benefits from the TMS320F28069M microcontroller with the InstaSPIN-MOTION™solution. This device
also implements InstaSPIN-FOC technology which is a subset of InstaSPIN-MOTION devices.
• PGA411-Q1 Resolver Front-end determines the position of the motor shaft. The motor control loop
optionally uses the shaft position for motor commutation. Additional to the position sensing, the
PGA411-Q1 also provides information about velocity.
• TPS65381A-Q1 Power Management Integrated Circuit provides bias supply to all other subsystems
including monitoring, diagnostics, and reset circuitry. The PMIC communicates with the MCU over four-
wire SPI and additional GPIOs.
• Isolated CAN interface allows for communication with a host system. The subsystem uses the
TCAN1042-Q1 CAN transceiver and the ISO7731-Q1 digital isolator. The SN6501-Q1 transformer
push-pull driver with the TPS76350 linear post-regulator form a low-power isolated power supply. The
SW implementation of the CAN protocol (CAN stack) is not a part of the TI Design.
• R-2R Digital-to-Analog converter connects directly to the parallel interface of the resolver front-end.
System Overview www.ti.com
Logic signals on the parallel interface represents the binary value of the angle or velocity registers in
the PGA411-Q1. The R-2R resistor ladder converts the binary number into analog value. This solution
allows for real-time monitoring of the angle or velocity using an oscilloscope.
Figure 5 shows a detail of the PCB and highlights important interfaces.
D/A Converter Analog Control
Output (J7) Input (J2)
BLDC Motor
Resolver Terminal (J4)
Terminal (J5)
Serial Interface
(UART) Connector (J3)
TI 14-Pin JTAG
Connector (J200)
Manual Control
(R1)
Status LEDs
(D200íD202)
DIP Switch
Configuration (S200)
CAN Interface
Connector (J6)
Power Supply Input Micro USB

Terminal (J8) Connector (J1)
Figure 5. TIDA-01507 PCB
Motor-resolver assembly options:

• Maxon™ EC40 BLDC with Maxon RES26 resolver – Texas Instruments recommends this setup as it
comes pre-assembled from the manufacturer with pre-defined parameters. The motor also implements
Hall sensors which are further used for experimenting with the motor control algorithm. All
measurements in Section 3.2 use this motor-resolver assembly, unless otherwise noted.
• RS2306 BLDC multirotor motor or a similar motor for Radio-Controlled (RC) models + a
resolver – A low-cost BLDC motor. Use one of the available resolvers. This cost-effective solution is
ideal for educational or demonstration purposes. However, any mechanical misalignment between the
motor shaft and resolver adds error to the system. For this reason, performance may vary and cannot
be guaranteed.
The software may link the universal analog input J1 (unprotected!) or manual control using the
potentiometer P1 to various system variables such as acceleration or velocity. This is beneficial for real-
time debugging. The DIP switch allows for additional settings or modes of operation. The LED diodes
signal the board status. Alternatively, the UART and CAN periphery can extend configuration and
diagnostic possibilities.
Software provided as a part of the TI design is a motor control example based on a modified MotorWare™
Project. The software example is intended to be a basis for your own development and does not provide
any complex functionality. Texas Instruments recommends controlSUITE ™ and MotorWare software
where you can find many motor control software examples including libraries and source codes. Software
developed for InstaSPIN-FOC devices runs on InstaSPIN-MOTION deceives without any modifications.
2.1 InstaSPIN-FOC™ for PMSM

TI InstaSPIN-FOC technology enables designers to identify, tune, and fully control any type of three-
phase, variable-speed, sensorless synchronous, or asynchronous motor control system. This new
technology removes the need for a mechanical motor rotor sensor to reduce system costs and improve
operation using TI's new software encoder (sensorless observer) software algorithm, FAST™ (flux, angle,
speed, and torque), embedded in the read-only memory (ROM) of Piccolo™ devices. This ROM enables
premium solutions that improve motor efficiency, performance, and reliability in all variable-speed and
variable-torque applications. Figure 6 shows the block diagram of the InstaSPIN-FOC. The resolver
sensor enables the motor to run with a very low speed under heavy load and start-up under full load.
Torque
Mode CTRL_run
Zref CTRL_setup
Traj
User_SpdRef Spdout Iq_ref
Ramp Speed
PI Iq DRV_run
a Iq PI
Z Vq Vr_out Ta
User_IqRef INV Tb PWM
Vd Vt_out SVM
Id_ref PARK Tc Driver
User_IdRef +
+ Id a
Id
PI T FLASH/RAM
Id
Iq PARK
a DRV_acqAdcInt
a EST_run T FLASH/RAM
T DRV_readAdcData
a a Ir_in Ia
\ Irated Ib
Flux It_in CLARKE
a a Ic
T \
Angle
a
Z a FAST¡ •š]u š}Œ Vr_in
Z Va ADC
Speed Flux, Angle, Speed, Torque
Vb Driver
aW aW Motor Parameters ID Vt_in CLARKE
Vc
Torque
a a Vbus
T Z
ROM FLASH/RAM
RDC
a
Rs Enable PowerWarp¡
a
Rr Enable Motor Identification
a
Lsd
a Enable Rs Online Recalibration
Lsq
a Enable Force Angle Startup
\rated
a
Irated Motor Type
Figure 6. InstaSPIN-FOC™ Block Diagram
InstaSPIN-FOC benefits include:

• FAST estimator to measure rotor flux magnitude, rotor flux angle, and motor shaft speed and torque in
a sensorless FOC system
• Automatic torque (current) loop tuning with the option for user adjustments
• Automatic configuration of speed loop gains (Kp and Ki) provides stable operation for most applications
and user adjustments required for optimum transient response

• Automatic or manual field weakening and field boosting
• Bus voltage compensation
• Automatic offset calibration ensures quality samples of feedback signals
2.2 Block Diagram

Figure 7 shows the TIDA-01507 block diagram.
170-W BLDC RESOLVER
ISO
X, Y, Z CAN UART
3 EXC, SIN,
3 CAN UART 6
COS
X, Y, Z
4 4
P12V SPI SPI P5V
6 4
P3V3 PWM GPIO P3V3
6
ADC MCU Resolver
BLDC Driver
P1V8 F28069M Front-End
DRV8305-Q1 4
(C2000) 4×SW PGA411-Q1
P3V3
14 4
JTAG LEDs
12
ADC SPI, ADC
GPIO, BNC
RESET R2R D/A
Converter
10 50Ÿ
Manual External
Control Control
BNC
External
Monitor
P3V3
KL30 (12 V) PMIC P5V

TPS65381A-Q1 P1V8
P12V
Figure 7. TIDA-01507 Block Diagram
2.3 Highlighted Products
2.3.1 DRV8305-Q1
The DRV8305-Q1 device is a gate driver IC for three-phase motor-drive applications. The device provides
three high-accuracy half-bridge drivers, each capable of driving a high-side and low-side N-channel
MOSFET. A charge pump driver supports 100% duty cycle and low-voltage operation for cold-crank
situations. The device can tolerate load dump voltages up to 45 V. The DRV8305-Q1 device includes
three bidirectional current-shunt amplifiers for accurate low-side current measurements that support
variable gain settings and an adjustable offset reference.
2.3.2 PGA411-Q1
The PGA411-Q1 device is a resolver-to-digital converter with an integrated exciter-amplifier and boost-
regulator power supply that is capable of both exciting and reading the sine and cosine angle from a
resolver sensor. The integration of the exciter amplifier and boost supply with protection in the PGA411-
Q1 device enables cost reductions of the bill of materials (BOM) and space reductions on the printed-
circuit board (PCB) because of the elimination of most of the external and passive components.
2.3.3 TPS65381A-Q1
The TPS65381A-Q1 device is a multirail power supply designed to supply microcontrollers (MCUs) in
safety-relevant applications, such as those found in automotive and industrial markets. The device
supports Texas Instruments’ Hercules™ TMS570 MCU and C2000 MCU families, and various other
MCUs with dual-core lockstep (LS) or loosely-coupled architectures (LC).
2.3.4 TMS320F28069M
The F2806x Piccolo family of microcontrollers (MCUs) provides the power of the C28x core and CLA
coupled with highly-integrated control peripherals in low pin-count devices. This family is code-compatible
with the previous C28x-based code, and also provides a high level of analog integration.
An internal voltage regulator allows for single-rail operation. Enhancements have been made to the High-
Resolution Pulse Width Modulator (HRPWM) module to allow for dual-edge control (frequency
modulation). Analog comparators with internal 10-bit references have been added and can be routed
directly to control the ePWM outputs. The ADC converts from 0- to 3.3-V fixed full-scale range and
supports ratio-metric (VREFHI,VREFLO) references. The ADC interface has been optimized for low overhead
and latency.
Devices with F or M suffix have special motor control software located in ROM called InstaSPIN-FOC or
InstaSPIN-MOTION solution. For further details, see the InstaSPIN-FOC™ and InstaSPIN-MOTION™
User's Guide.
2.3.5 TCAN1042HFV-Q1
This CAN transceiver family meets the ISO11898-2 (2016) High-Speed CAN (Controller Area Network)
physical layer standard. All devices are designed for use in CAN FD networks up to 2 Mbps (megabits per
second). Devices with part numbers that include the "G" suffix are designed for data rates up to 5 Mbps,
and versions with the "V" have a secondary power supply input for I/O level shifting the input pin
thresholds and RXD output level. This family has a low-power standby mode with remote wake request
feature. All devices include many protection features to enhance device and network robustness.
2.4 System Design Theory

Each following section represents one subsystem from the block and circuit diagram. This design guide
does not cover the fundamental theory of operation. Passive components selection does not require
special measures, unless otherwise is noted.
2.4.1 BLDC Driver

This subsystem reuses the TI Reference design TIDA-00901 with minor changes. For additional design
theory of operation and test measurements data, see Automotive 12 V 200 W (20 A) BLDC Motor Drive
Reference Design.
See Table 2 for a system interface overview of the BLDC driver block.
Table 2. System Interface for the BLDC Driver

SIGNAL DIRECTION DESCRIPTION
MOT_A Out Motor terminal phase A
MOT_B Out Motor terminal phase B
MOT_C Out Motor terminal phase C
PVDD In Power rail (positive)
P3V3 In 3.3-V bias supply
GND - Common ground
PWM_AH In PWM input, phase A, high-side
PWM_AL In PWM input, phase A, low-side
PWM_BH In PWM input, phase B, high-side
PWM_BL In PWM input, phase B, low-side
PWM_CH In PWM input, phase C, high-side
PWM_CL In PWM input, phase C, low-side
ISNS_A Out Current-sense amplifier output, phase A
ISNS_B Out Current-sense amplifier output, phase B
ISNS_C Out Current-sense amplifier output, phase C
VSEN_A Out Voltage sensing, phase A
VSEN_B Out Voltage sensing, phase B
VSEN_C Out Voltage sensing, phase C
VSEN_PVDD Out Voltage sensing, power rail
SCS In SPI interface, chip select
SCLK In SPI interface, clock
SDO Out SPI interface, data out
SDI In SPI interface, data in
nFAULT_DRV In/Out BLDC fault reporting signal (open collector)
TEMP_DRV Out Temperature sensor output voltage
WAKE_DRV In BLDC driver wake up signal
EN_DRV In BLDC driver enable signal
PWRGD_DRV Out BLDC driver power good signal
Figure 8 shows a schematic of the BLDC driver block.

PVDD
PVDD
PVDD THREE-PHASE MOSFET BRIDGE
P3V3
5
P3V3
GH_A 4 Q100 GH_B 4 Q101 GH_C 4 Q102
SQJ858AEP-T1-GE3 SQJ858AEP-T1-GE3 SQJ858AEP-T1-GE3
C100
10uF C101 C102 C103
1
2
3
1
2
3
1
2
3
10V 1uF 1uF 1uF
GND
25V 25V 25V MOT_A MOT_B MOT_C
BLDC DRIVER MOT_A MOT_B MOT_C
GND C104
1uF
5
25V
U100 C105 GL_A 4 Q103 GL_B 4 Q104 GL_C 4 Q105
GND SQJ858AEP-T1-GE3 SQJ858AEP-T1-GE3 SQJ858AEP-T1-GE3
0.1uF Local DC-Link
C106 15
AVDD CP1H
43
1uF
1
2
3
1
2
3
1
2
3
PVDD 46 42 50V
GND DVDD CP1L
C107 P3V3 SL_A SL_B SL_C
25V 41 PVDD CP2H 39
nFAULT_DRV 8 40 0.1uF
C108 nFAULT_DRV FAULT CP2L
50V R100 NT100 NT101 NT102
12
SCLK SCLK
10uF 10 47 10.0k S1_N S2_N S3_N
35V SDI SDI WAKE WAKE_DRV
C109 C110 C111 Net-Tie R101 Net-Tie R102 Net-Tie R103
11 48
SDO SDO VREG/VREF P3V3 1uF 1uF 1uF 0.007 0.007 0.007
9 13 S1_P S2_P S3_P
SCS SCS PWRGD PWRGD_DRV
25V 25V 25V NT103 NT104 NT105
GND 1
EN_GATE
EN_DRV R104
44
VDRAIN PVDD Net-Tie Net-Tie Net-Tie
100 Low-side current sensing - route differentially
PWM_AH 2
INH_A GHA
36 GH_A
PWM_AH
PWM_AL 3
INL_A SHA
35 MOT_A
PWM_AL
P3V3 GLA
33 GL_A GND
SLA 34 SL_A
VOLTAGE SENSING
2
PWM_BH 4
INH_B
PWM_BH
D100 GHB
29 GH_B
Super Red PWM_BL 5
INL_B
MOT_A MOT_B MOT_C PVDD
PWM_BL
R105 31 SL_B
SLB
1
10.0k
32 GL_B R106 R107 R108 R109
GLB
25.5k 25.5k 25.5k 25.5k
R110 30 MOT_B
SHB
220 VSEN_A VSEN_B VSEN_C VSEN_PVDD
VSEN_A VSEN_B VSEN_C VSEN_PVDD
PWM_CH 6
INH_C
PWM_CH
nFAULT_DRV GHC
28 GH_C
PWM_CL 7 R111 R112 R113 R114
PWM_CL INL_C
27 MOT_C S1_N 4.99k C112 4.99k C113 4.99k C114 4.99k C115
SHC
0.1uF 0.1uF 0.1uF 0.1uF
25 GL_C 50V 50V 50V 50V
GLC
C116
26 SL_C 1000pF
SLC
16V S1_P GND GND GND GND
R115 16 23
ISNS_A SO1 SN1
56.0 SP1
24 S2_N
R116 17 21
ISNS_B SO2 SN2
56.0 22 C117
SP2
1000pF
R117 18 19 16V S2_P
ISNS_C SO3 SN3
56.0 20
SP3
S3_N
37 14 TEMPERATURE MONITORING VOLTAGE SENSING PROTECTION
VCP_LSD GND
C118 GND 45
38 49 C119
C123 PVDD
VCPH PAD
C120 C121 C122 1000pF P3V3 U101 D101
2200pF 2200pF 2200pF 1uF 2.2uF DRV8305 16V S3_P
16V 16V 16V 25V 16V GND 5 3 VSEN_B 1 6
VDD OUT TEMP_DRV P3V3
4
VDD
GND GND GND GND
C124 VSEN_C 2 5 VSEN_A
2 0.1uF
GND
1 50V
GND
3 4 VSEN_PVDD
P3V3
LMT86DCKT
PWM_AH GND
TP100
PWM_AL BAT54CDW-7-F
TP101
PWM_BH
TP102
PWM_BL
TP103
PWM_CH
TP104
PWM_CL
TP105 NOTE: This block is based on ti.com/TOOL/TIDA-00901
Figure 8. BLDC Driver Schematic
The programmable motor driver DRV8305-Q1 (U100) controls the power stage. Capacitors C100 and
C108 are bypassing capacitors for each power rail. Capacitors C104, C106, and C123 are output
capacitors for internal voltage regulators. Capacitors C105, C107, and C118 are required for the
integrated charge pump. Six N-FET transistors, Q100–Q105 are for the 3-phase power stage.
Shunt resistors R101–R103 sense current on the low-side of each phase. Capacitors C116, C117, and
C119 add low-pass filter response to the current measurement. RC networks R115–R117 and C120–122
additionally filter the output of the integrated current sense amplifiers (CSA).
Power dissipation in shunt resistors is important when selecting the shunt resistance values. The
maximum root-mean-square current in a motor is 15 A, so the peak-to-peak current is as per Equation 5:
Ip p IRMS u 2 u 2 15 u 2 u 1.4142136 42.43 A (5)
By selecting a 7-mΩ resistor as the shunt resistor with PGA Gain (GPGA) equal to 10, the power loss in the
resistor at 15 ARMS is:
2
PD Rshunt u IRMS 0.007 u 152 1.575 W (6)
From Equation 6, it can be surmised that it is sufficient to select a power 7-mΩ, 2-W, 1% 2512-package
resistor. In this case, the ADC sensing range for the current measurement is defined as per Equation 7:
VADC REF 3.3
Imax 47.1430 A
Rshunt u GPGA 0.007 u 10
where
• VADC-REF is (integrated) voltage reference for the ADC (7)
The group of capacitors C101–C103 and C109–C111 form a local DC-link capacitor located in the close
proximity to each H-bridge transistor pair. This reduces high di/dt spikes and possible EMI issues.
Resistors R106–R109 and R111–R114 form four resistor dividers for the control-loop feedback. The
system measures the BEMF on the un-energized winding node. BEMF feedback is needed for sensorless
control to estimate the position of the rotor for accurate commutation. The maximum phase voltage
feedback is defined as per Equation 8:
VADC REF u R106 R111 3.3 u 25.5 k 4.99 k
Vmax 20.164 V
R111 4.99 k (8)
Considering a 5% headroom for this value, the maximum voltage input to the system is recommended to
be 20.164 × 0.95 = 19.1 V.
Capacitors C112–C115 add low-pass filter response as per Equation 9:
1 1
fC 381.3 Hz
R106 u R111 25.5 k u 4.99 k
2S u u C112 2S u u 100 n
R106 R111 25.5 k 4.99 k (9)
Diodes network D101 clamps voltage feedback signals to approximately 3.6 V to protect the inputs of the
ADC.
The resistor R110 set the bias current through the LED diode D100 which visually reports the status of the
fault signal. The R105 is a pullup resistor for the nFAULT_DRV signal. The BLDC driver uses inexpensive
integrated sensor LMT86-Q1 (U101) for onboard temperature monitoring. The capacitor C124 is an
optional charge-bucket filter recommended for interfacing with ADCs. For further details, see to the
application and implementation section of LMT86 2.2-V, SC70/TO-92/TO-92S, Analog Temperature
Sensors.
2.4.2 C2000™ Microcontroller

The C2000 microcontroller adds intelligence to the system and performs the motor control loop.
See Table 3 for a system interface overview of the C2000 microcontroller block.
Table 3. System Interface for the C2000™ Microcontroller

MAN_CTRL In Analog input (0 V–3.3 V) for manual control
USB_D+ In/Out Universal Serial Bus (USB) D+
USB_D– In/Out Universal Serial Bus (USB) D–
TXD Out Serial port output
RXD In Serial port input
PWM_AH Out PWM input, phase A, high-side
PWM_AL Out PWM input, phase A, low-side
PWM_BH Out PWM input, phase B, high-side
PWM_BL Out PWM input, phase B, low-side
PWM_CH Out PWM input, phase C, high-side
PWM_CL Out PWM input, phase C, low-side
ISNS_A In Current-sense amplifier measurement, phase A
ISNS_B In Current-sense amplifier measurement, phase B
ISNS_C In Current-sense amplifier measurement, phase C
VSEN_A In Voltage sensing, phase A
VSEN_B In Voltage sensing, phase B
VSEN_C In Voltage sensing, phase C
VSEN_PVDD In Voltage sensing, power rail
TEMP_DRV In Temperature sensor output voltage measurement
nFAULT_DRV In/Out BLDC Fault reporting pin (open collector)
WAKE_DRV Out BLDC driver wake up signal
PWRGD_DRV In BLDC driver enable signal
Table 3. System Interface for the C2000™ Microcontroller (continued)

ACTRL In Analog control (external) signal input
nRST In System reset signal
FAULT_RS In/Out Resolver fault reporting signal (open drain)
FLTRES_RS Out Resolver fault reset signal
OMODE Out Data output mode select signal. Setting OMODE = high enables the parallel output interface
of PGA411-Q1. Emulated encoder output is enabled when OMODE = low.
INHB Out Inhibit function and output data hold for the PGA411-Q1
AMODE Out Setting AMODE = high enables accelerated mode for PGA411-Q1
BMODE0 Out Resolution select for PGA411-Q1. 10-bit angle and velocity resolution when BMODE0 = low.
12-bit angle and velocity resolution when BMODE0=high.
VA0 Out PGA411-Q1 parallel interface data output select 0
VA1 Out PGA411-Q1 parallel interface data output select 1
X_20MHZ Out Optional 20-MHz clock output for the PGA411-Q1
TX_CAN Out CAN interface TX line
RX_CAN In CAN interface RX line
STB_CAN Out CAN interface strobe line
WDT_TRIG Out PMIC watchdog timer trigger signal
DIAG_PMIC In Diagnostic signal from the PMIC
nCS_RES Out SPI interface, chip select (PGA411-Q1)
nCS_PMIC Out SPI interface, chip select (TPS56381A-Q1)
nCS_BLDC Out SPI interface, chip select (DRV8305-Q1)
SCLK Out SPI interface, clock
SDI In SPI interface, data input
SDO Out SPI interface, data output
P1V8 In 1.8-V bias supply for the MCU core
GND – Common ground
Figure 9 shows the C2000 microcontroller block schematic.

JTAG 14-PIN & BOOT OPTIONS INTERNAL V-REG DISABLE VOLTAGE REFERENCE (OPTIONAL) MCU POWER SUPPLY PINS BYPASSING
P3V3
J200
TMS 1 2 nTRST nTRST R200 EMU0 R201
TDI 3 4 GND 4.70k 4.70k VDDA VDD: When using internal VREG, place one 1.2- µF capacitor between each VDD pin and ground. Higher value capacitors may be used.
5 6 VDDIO: Digital I/O and Flash Power Pin. Single supply source when VREG is enabled. Place a 2.2-uF decoupling capacitor on each pin.
P3V3
TDO 7 8 GND VDDA: Analog Power Pin. Tie with a 2.2- F capacitor (typical) close to the pin.
9 10 GND TDO R202 EMU1 R203 P3V3
TCK 11 12 GND 4.70k 4.70k R204 P1V8 U200B
EMU0 13 14 EMU1 R205 4.70k
GND 4.70k 3 27
R206 VDD VREFLO GND
TSM-107-01-L-DV GPIO34 nVREGENZ VREF 14 VDD
4.70k 37
VDD VREFHI
24 VREF
R207 63
3
DNP VDD
4.70k 81
C200 U201 VDD
P3V3 VDDA 91
0.1uF LM4040A20IDBZR VDD
GND VSS
4
R208
2
50V 25 VDDA VSS 15
10.0 VSS 36
5 VDDIO VSS 47
C201 13 62
VDDIO VSS
GND 2.2uF 38 80
VDDIO VSS
U200A 16V 61 92
VDDIO VSS
79
VDDIO
23
ADCINA0 GPIO0/EPWM1A
87 GND 93
VDDIO VSSA
26
VSEN_C PWM_AH
22 ADCINA1 GPIO1/EPWM1B/COMP1OUT 86
VSEN_B PWM_AL
21 84 46
ACTRL ADCINA2/COMP1A/AIO2 GPIO2/EPWM2A PWM_BH P3V3 VDD3VFL
20 ADCINA3 GPIO3/EPWM2B/SPISOMIA/COMP2OUT 83
VSEN_A PWM_BL
P3V3 19
ADCINA4/COMP2A/AIO4 GPIO4/EPWM3A
9
TEMP_DRV PWM_CH
R209 18 10 GND
MAN_CTRL ADCINA5 GPIO5/EPWM3B/SPISIMOA/ECAP1 PWM_CL
49.9 ARES1 17 58
P3V3 ADCINA6/COMP3A/AIO6 GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO VA0
16 57
VSEN_PVDD ADCINA7 GPIO7/EPWM4B/SCIRXDA/ECAP2 VA1
P1V8 GPIO8/EPWM5A/ADCSOCAO
54
AMODE
ARES2 28 ADCINB0 GPIO9/EPWM5B/SCITXDB/ECAP3 49
INHB
GND 29 ADCINB1 GPIO10/EPWM6A/ADCSOCBO 74
P1V8 ISNS_A WAKE_DRV
ARES3 30
ADCINB2/COMP1B/AIO10 GPIO11/EPWM6B/SCIRXDB/ECAP1
73
RXD
31
ADCINB3 GPIO12/TZ1/SCITXDA/SPISIMOB
44 P3V3
ISNS_B TXD
ARES4 32
ADCINB4/COMP2B/AIO12 GPIO13/TZ2/SPISOMIB
95 SW1
ARES5 33
ADCINB5 GPIO14/TZ3/SCITXDB/SPICLKB
96 SW2
GND
DIAG_PMIC_A 34
ADCINB6/COMP3B/AIO14 GPIO15/ECAP2/SCIRXDB/SPISTEB
88 LED3
R210 35 55
P3V3 ISNS_C ADCINB7 GPIO16/SPISIMOA/TZ2 SDO
C202 C203 C204 C205 C206 C207
GND 4.70k GPIO17/SPISOMIA/TZ3 52
SDI
11 51 1uF 1uF 1uF 1uF 1uF 1uF
nRST XRS GPIO18/SPICLKA/SCITXDB/XCLKOUT SCLK
64 25V 25V 25V 25V 25V 25V
GPIO19/XCLKIN/SPISTEA/SCIRXDB/ECAP1 nCS_RES
nVREGENZ 90
VREGENZ GPIO20/EQEP1A/MDXA/COMP1OUT
6 EQEP1A
C208 7 EQEP1B
GPIO21/EQEP1B/MDRA/COMP2OUT
0.1uF nTRST 12 98 EQEP1S GND
TRST GPIO22/EQEP1S/MCLKXA/SCITXDB
50V GPIO23/EQEP1I/MFSXA/SCIRXDB
2 EQEP1I
45 TEST2 GPIO24/ECAP1/EQEP2A/SPISIMOB 97 SW3
GND GPIO25/ECAP2/EQEP2B/SPISOMIB 39 DIAG_PMIC
XIN 60 X1 GPIO26/ECAP3/EQEP2I/SPICLKB/USB0DP 78 P1V8
USB_D+
77
GPIO27/HRCAP2/EQEP2S/SPISTEB/USB0DM USB_D-
XOUT 59
X2 GPIO28/SCIRXDA/SDAA/TZ2
50
BMODE0
43 TEST1
X-TAL OSCILLATOR X_20MHZ
TEST3 1
GPIO29/SCITXDA/SCLA/TZ3
41
GPIO42/EPWM8A/TZ1 /COMP1OUT GPIO30/CANRXA/EQEP2I/EPWM7A RX_CAN
TEST4 8 40 C209 C210 C211 C212 C213 C214
GPIO43/EPWM8B/TZ2 /COMP2OUT GPIO31/CANTXA/EQEP2S/EPWM8A TX_CAN
Y200 56 99 SDA 2.2uF 2.2uF 2.2uF 2.2uF 2.2uF 2.2uF
FLTRES_RS GPIO44/MFSRA/SCIRXDB/EPWM7B GPIO32/SDAA/EPWMSYNCI/ADCSOCAO
NX3225GA-20MHZ-STD-CRA-1 42 100 SCL 16V 16V 16V 16V 16V 16V
STB_CAN GPIO50/EQEP1A/MDXA/TZ1 GPIO33/SCLA/EPWMSYNCO/ADCSOCBO
2 1 XIN 48 68 GPIO34
G FAULT_RS GPIO51/EQEP1B/MDRA/TZ2 GPIO34/COMP2OUT/COMP3OUT
4 3 XOUT 53 71 TDI
G OMODE GPIO52/EQEP1S/MCLKXA/TZ3 GPIO35/TDI
65
GPIO53/EQEP1I/MFSXA GPIO36/TMS
72 TMS GND
nCS_BLDC
20MHz 69
GPIO54/SPISIMOA/EQEP2A/HRCAP1 GPIO37/TDO
70 TDO
WDT_TRIG
GND C215 C216 75 67 TCK
PWRGD_DRV GPIO55/SPISOMIA/EQEP2B/HRCAP2 GPIO38/XCLKIN/TCK
15pF 15pF LED1 85 66
GPIO56/SPICLKA/EQEP2I/HRCAP3 GPIO39 nCS_PMIC
50V 50V LED2 89 GPIO57/SPISTEA/EQEP2S/HRCAP4 GPIO40/EPWM7A/SCITXDB 82 TEST2
SW4 94 GPIO58/MCLKRA/SCITXDB/EPWM7A GPIO41/EPWM7B/SCIRXDB 76
nFAULT_DRV
GND GND
TMS320F28069MPZT
D200 DIP-SWITCH CONFIGURATION PMIC DIAG I2C TESTPOINTS ENCODER TESTPOINTS RESERVE
1 2 R211 LED1
1.50k P3V3 TEST1
TP200
TEST2
TP201
Super Red TEST3
TP202
DIAG_PMIC TEST4
D201 TP203
P3V3 ARES1
R212 R213 R214 R215 R216 TP204
1 2 LED2 EQEP1A ARES2
4.70k 4.70k 4.70k 4.70k TP205 TP206
1.50k EQEP1B ARES3
R217 TP207 TP208
DIAG_PMIC_A EQEP1S ARES4
DIAG_PMIC TP209 TP210
Yellow 1 8 SW1 4.70k EQEP1I ARES5
R218 R219 TP211 TP212
2 7 SW2
D202 3 6 SW3 C217 4.70k 4.70k
1 2 R220 LED3 4 5 SW4 0.1uF
680 50V SDA
S200 TP213
SCL
TP214
Green GND GND
GND
Figure 9. C2000™ Microcontroller Schematic
The TMS320F28069M (U200) is the biggest member from the C2000 real-time control MCU family. The
microcontroller uses the internal 10-MHz oscillator as a clock source which is sufficient in most
applications. Alternatively, use the external oscillator Y200 with recommended capacitors C215 and C216,
if required. Assembling either the R205 or R207 resistor selects the power source for the core. The
internal voltage regulator supplying the microprocessor core is disabled by default and the safety PMIC
supplies power to the core. Capacitors C202–C207 and C209–C214 form the recommended power rail
bypass scheme. Resistor R208 and capacitor C201 decouple the analog circuitry from the noisy digital
power domain. The ADC integrated in the microcontroller can alternatively use external voltage reference
circuitry based on LM4040A-Q1 (U201), bias resistor R204, and capacitor C200. Adjust voltage
measurement feedback dividers and current sense amplifiers in the BLDC driver block accordingly, in
case the voltage reference is different than the default 3.3 V. The programming connector J200 uses a
standard 14-pin TI JTAG pinout compatible with XDS100V2, XDS110, XDS200, or XDS560 debug probes.
Resistors R200–R203 and R206 set the correct booting option. The recommended RC network R210 and
C208 prevents glitches on the reset pin. The 50-Ω resistor, R209, terminates the external control signal
and matches the typical signal generator source impedance.
CAUTION
The ACTRL signal is unprotected. Any voltages above 3.3 V will permanently
damage the microcontroller.
Three LEDs D200–D202 with bias resistors R211, R212, and R220, and DIP-switch S200 with pullup
resistors R213–216, provide a basic configurable user interface. The DIAG_OUT signal from the PMIC
multiplexes both digital and analog signals. For this reason, a digital input and ADC channel monitors the
signal. The RC network R217 and C217 adds a low-pass filter for the analog input. For more information,
refer to the diagnostic MUX and diagnostic output pin section of TPS65381A-Q1 Multirail Power Supply for
Microcontrollers in Safety-Relevant Applications. The PCB board has additional testpoints for debugging
purposes. Testpoints TP200–208, TP210, and TP212 are for general purpose. Use testpoints TP205,
TP207, TP209, and TP211 to interface with the QEP encoder. Testpoints TP213 and TP214 with pullup
resistors R218 and R219 are reserved for additional I2C periphery.
2.4.3 Resolver Front-End

This subsystem reuses TI Reference design TIDA-00796 with minor changes. For additional design theory
of operation and test measurements data, see Automotive Resolver-to-Digital Converter for Safety
Applications.
See Table 4 for a system interface overview of the resolver front-end block.
Table 4. System Interface for the Resolver Front-End

NRESET In System reset signal
NCS In SPI interface, chip select (PGA411-Q1)
FAULT_RS In/Out Resolver fault reporting signal (open drain)
FLTRES_RS In Resolver fault reset signal
OMODE In Data output mode select signal. Setting OMODE = high enables the
parallel output interface of PGA411-Q1. Emulated encoder output is
enabled when OMODE = low.
INHB In Inhibit function and output data hold for the PGA411-Q1
AMODE In Setting AMODE = high enables accelerated mode for PGA411-Q1.
BMODE0 In Resolution select for PGA411-Q1. 10-bit angle and velocity resolution
when BMODE0=low. 12-bit angle and velocity resolution when
BMODE0=high.
VA0 In PGA411-Q1 parallel interface data output select 0
VA1 In PGA411-Q1 parallel interface data output select 1
X_20MHZ In Optional 20 MHz clock input for the PGA411-Q1
P6V In 6.0-V bias supply
P5V In 5.0-V bias supply
EXC– Out Excitation amplifier output (negative)
EXC+ Out Excitation amplifier output (positive)
COS– In Resolver cosine coil input (negative)
COS+ In Resolver cosine coil input (positive)
SIN– In Resolver sine coil input (negative)
SIN+ In Resolver sine coil input (positive)
ORD[0..11] Out PGA411-Q1 parallel interface output
Figure 10 shows the resolver front-end schematic.

DIGITAL & ANALOG DECOUPLING FILTER EXCITER AMPLIFIER BOOST CONVERTER RESOLVER EXCITER OUTPUT + FEEDBACK
P5V QVCC VCCSW L300 V_AMP OE1
EXC+
D300 OE2
R300 EXC-
P5V
10.0 56uH
SS16T3G
C300 C301 C302 C303 C304 C305 C306 IE1 R301
1uF 0.1uF 0.01uF 0.1uF 10uF 0.1uF 10uF 68.0k
25V 50V 50V 50V 35V 50V 35V
C307
C301 close to PIN 60
68pF
GND GND GND IE2 50V R302
68.0k
C308 C309
68pF 68pF
EXCITER BOOST DC-DC VIN SELECTOR 50V 50V
U300
GND GND
R303 4 6
P6V DNP VCCSW VCCSW VCCSW VSW
0
39
R304 QVCC QVCC
C310 22 OE1
P5V
0 58
OE1 RESOLVER ANALOG FRONT-END RESOLVER CONNECTOR
GND VDD
OE2 26 OE2
Either-or 0.1uF 60 QVCC
P5V VCC
50V ORS
9
24
V_AMP VEXT
OSIN
43 OSIN
61 R305
P3V3 VIO
51.0k
P3V3 IZ1
38 IZ1
IZ3 37 IZ3
12 IZ1 R306 IZ1_TVS R307
P3V3 NRESET RESET COS+
COMAFE
35 COMAFE 27.0k 27.0k
C312
C311 31 42 IZ4 68pF
VA0 VA0 IZ4
0.1uF 32 41 IZ2 50V
VA1 VA1 IZ2 R308 R309
50V IZ3 IZ3_TVS
GND COS-
IE1 34 IE1 OCOS 36 OCOS 27.0k 27.0k
IE2 33 IE2
GND 30 AOUT R310
AOUT
1 OUTA C313 C314 20.0k
OUTA
17 2 OUTB 68pF 68pF
NCS NCS OUTB
18
SCLK XOUT
63 XOUT 50V 50V
SCLK
19
SDI OUTZ
64 OUTZ
SDI
20
SDO
GND GND GND
SDO
62 XIN
X_20MHZ
59 15
MONITOR AFE XIN
GND EXTCLKIN PRD
57 ORD0 QVCC
AOUT 16
ORD0
56 ORD1 INPUT / OUTPUT PROTECTION
TP300 FAULT_RS FAULT ORD1
OSIN 55 ORD2
TP301 ORD2
COMAFE 54 ORD3
TP302 ORD3
R311
OCOS 28 53 ORD4
TP303 AMODE AMODE ORD4
51.0k
29 OMODE ORD5 52 ORD5 V_AMP
OMODE
5 BMODE0 ORD6 51 ORD6
BMODE0 R312 R313
C315 R314 7 50 ORD7 IZ2 IZ2_TVS
0.01uF 0 GND BMODE1 ORD7 SIN+
ORD8
49 ORD8 27.0k 27.0k
50V 48 ORD9 C316
5
ORD9
10 47 ORD10 68pF
V_AMP VEXTS ORD10 D301A D301B
ORD11
46 ORD11 50V
GND GND 13 45 ORD12 IZ4 R315 IZ4_TVS R316 OE1 6 OE2 3 BAS40DW-04-TP
INHB INHB ORD12 SIN-
ORD13 44 ORDCLK 27.0k 27.0k
14 FAULTRES
FLTRES_RS
27 ORD[0..11] R317
PBKG ORD[0..11]
4
C317 C318 20.0k
3 68pF 68pF
P3V3 ECLKSEL
DGND
21 50V 50V
11
TEST
QGND
40 GND GND GND GND
PGND 8
25
NC
QVCC U301
23 65
X-TAL OSCILLATOR NC PAD MONITOR INC. ENCODER MONITOR ORD 5
VCC
Y300 GND GND OUTA IZ4_TVS 1 4 IZ1_TVS
PGA411PAP TP304 IO1 IO3
NX3225GA-20MHZ-STD-CRA-1 OUTB ORD12
TP305 TP306
2 1 XIN OUTZ ORDCLK IZ3_TVS 3 6 IZ2_TVS
G TP307 TP308 IO2 IO4
4 3 XOUT
G
20MHz GND
2
GND C319 C320
15pF 15pF TPD4E001QDBVRQ1
50V 50V MONITOR ENCODER GND
GND GND NOTE: This block is inspired by ti.com/TOOL/TIDA-00796 ORD0 ORD3 ORD6
TP309 TP310 TP311
ORD1 ORD4 ORD7
More component optimized version, Symbol is different ORD2
TP312
ORD5
TP313
ORD8
TP314
TP315 TP316 TP317
Figure 10. Resolver Front-End Schematic
The resolver front-end uses the PGA411-Q1 (U300) to interface with various resolvers. The PGA411-Q1
implements most of the circuitry needed for resolver signal processing, calculates velocity and angle, and
outputs the information in digital form. Additionally, the AOUT pin represents the information in the analog
domain. Capacitors C300–C303 and resistor R300 form a filter that bypasses voltage rails and decouples
the sensitive analog voltage rail, QVCC, from the rest of the system.
The integrated step-up converter with external capacitors C304–C306, diode D300, and inductor L300
supply the excitation amplifier. This is required to match the typical resolver excitation signal levels (4 or 7
VRMS). Assembling either resistor R303 or R304 sets the supply rail for the integrated step-up converter to
P5V or P6V. The capacitor C311 bypasses the 3.3-V rail used for digital interfaces. The integrated voltage
regulator requires the capacitor C310. Capacitor C315 and resistor R314 are recommended in PGA411-
Q1 Resolver Sensor Interface. The external 20-MHz oscillator Y300 with recommended capacitors C319
and C320 provide clock source for the PGA411-Q1. Alternatively, use the 20-MHz oscillator from the
microcontroller block. In this case, remove Y300, C319, C320 and assembly resistors R2, R3 to the PCB.
Diode network D301 protects the output of the excitation amplifier from ESD damage on the system level.
Resistors R301, R302 and capacitors C307–C309 provide common mode and differential filtering for the
exciter amplifier feedback. Feedback coils analog front-ends are identical for both channels. Resistors
R305 (R311) and R301 (R317) set input common-mode voltage. Resistors R306, R307 (R312, R313) and
R308, R309 (R315, R316) set DC gain of the integrated difference amplifier. Capacitors C312–C314
(C316–C318) set common mode and differential cut-off frequency of the analog front-end. The ESD
protection array TPD4E001-Q1 (U301) protects both analog front-end channels from ESD damage on the
system level. Signals that are not required for the operation but are beneficial for development purposes
are wired to testpoints TP300–TP317.
For more details on the PGA411-Q1 design, see PGA411-Q1 Resolver Sensor Interface or Automotive
Resolver-to-Digital Converter for Safety Applications.
2.4.4 Isolated CAN Interface

The isolated CAN interface reuses TI reference design TIDA-01255 with minor changes. For additional
design theory of operation and test measurements data, see Automotive Reinforced Isolation CAN
Reference Design .
See Table 5 for a system interface overview of the isolated CAN interface.
Table 5. System Interface for the Isolated CAN

GND_OPT – CAN common ground (optional)
CANL In/Out CAN bus line (low)
CANH In/Out CAN bus line (high)
CAN_GND – CAN common ground (optional)
CAN_V+ Out Isolated 5.0 bias supply for optional CAN devices
TX_CAN In CAN transmit data input
RX_CAN Out CAN receive data output
STB_CAN In CAN strobe input
Figure 11 shows the isolated CAN schematic.

ISOLATED 5V POWER SUPPLY
P3V3 P3V3 U400 1P5V

U401 D400 TPS76350QDBVRQ1
SN6501 1 T400 6 1 5
IN OUT
4
GND D2
3 MBR0520LT1G 3
EN NC
4
C400 C401 2 2 5 GND

VCC D401
10uF 0.1uF C402 C403 C404
2
10V 50V 5 1 10uF 0.1uF 10uF

GND D1
10V 50V 10V
3 4
GND 475uH
GND
1GND
1P5V
ISOLATED INTERFACE CAN TRANSCEIVER
NT400
CAN_V+
Net-Tie
P3V3 P3V3 1P5V 1P5V
R400
0
C405 C406 C407 U402
P3V3
GND 1GND 1GND D402
U403 3 7
3
VCC CANH CANH

0.1uF 0.1uF 0.1uF R401 DNP C408 1
50V 1 16 50V 50V 5 L400 60.4 C409 15pF
VCC1 VCC2 VIO
100uH 50V 3
3 INA OUTA 14 1 TXD
STB_CAN
R402 4700pF 2
4 13 8 6 60.4 50V 1GND DNP C410
TX_CAN INB OUTB STB CANL R403 CANL
4
15pF NUP2105LT1G
0 50V
5 12 4 2
RX_CAN OUTC INC RXD GND
7 10
R405 P3V3 EN1 EN2 1P5V R404
TCAN1042HGVDQ1 1GND
DNP20.0k 0
6 NC NC 11
CAN_GND
2 GND1 GND2 9
8 15
GND GND1 GND2
R406
ISO7731FQDWRQ1
0
GND GND 1GND 1GND
GND_OPT
NOTE: This block is inspired by ti.com/TOOL/TIDA-01255
Figure 11. Isolated CAN Interface Schematic
The ISO7731-Q1 (U403) is a triple-channel digital isolator which galvanically isolates the CAN transceiver.
Capacitors C405 and C406 are required bypass capacitors for U403. The TCAN1042-Q1 transceiver uses
recommended wiring. Resistors R401, R402, and the capacitor C409 are the network termination, this is
important to prevent signal reflections. Optional capacitors C408, C410, and the dual diode D402 prevent
damage during ESD and transient events. Common-mode choke L400 is typical for automotive CAN
networks to increase system reliability with respect to EMC. The TCAN1042-Q1 eliminates the need for
the external common-mode choke in many applications. For this reason, it is possible to assemble
resistors R400, R402, and remove the common-mode choke from the PCB. For more information about
choke-less CAN transceivers, see Simplify CAN bus implementations with chokeless transceivers. The
isolated interface requires a low-power isolated 5-V power supply. The push-pull transformer driver
SN6501-Q1 (U401) drives the transformer T400. Diodes D400 and D401 operate as a rectifier. Capacitors
C402 and C402 filter voltage on the secondary side to approx 7 V. The LDO regulator, TPS76350-Q1
(U400), regulates voltage to 5 V and reduces switching noise due to PSRR. The capacitor C404 is the
required output capacitor for the U400. Local bypass capacitors C400 and C401 are recommended. The
0-Ω resistors R404 and R406 allow for different ground terminal configurations on the CAN connector J6.
2.4.5 R-2R Digital-to-Analog Converter

The simple digital-to-analog converter in this block uses the principle of the R-2R resistor ladder. The
parallel interface of the PGA411-Q1 represents binary information of immediate angle or velocity. The R-
2R DAC buffers the digital information and converts it to an analog value. This allows for monitoring using
an oscilloscope which is beneficial for testing of dynamic performance.
See Table 6 for a system interface overview of the R-2R DAC.
Table 6. System Interface for the R-2R Digital-to-Analog Converter

P5V In 5.0-V Bias supply
DAC_OUT Out Output of the DAC
ORD[0..11] In DAC data input (connected to the parallel interface of the PGA411-Q1)
Figure 12 shows the R-2R DAC schematic.

POWER SUPPLY BIAS R-2R DAC NETWORK
P5V GND 4
GND 10
P5V GND 15
21
GND DAC_OUT
7 28
VCC GND
C500 C501 C502 C503 18 34
VCC GND
0.1uF 0.1uF 0.1uF 0.1uF 31 39
VCC GND R500
50V 50V 50V 50V 42
VCC GND
45 B11
20.0k
U500E
GND GND R501
10.0k
B10 R502
20.0k
R503
10.0k
B9 R504
20.0k
R505
10.0k
B8 R506
20.0k
BUFFER FOR THE DAC R507
10.0k
B7 R508
ORD[0..11] R509
ORD[0..11] GND 20.0k
10.0k
R510
10.0k
1 B6 R511
1OE
20.0k
ORD11 47 1A1 1Y1 2 B11
ORD10 46 3 B10 R512
1A2 1Y2
ORD9 44 5 B9 10.0k
1A3 1Y3
ORD8 43
1A4 1Y4
6 B8
B5 R513
U500A 20.0k
R514
10.0k
48 B4 R515
2OE
20.0k
ORD7 41
2A1 2Y1
8 B7
ORD6 40 9 B6 R516
2A2 2Y2
ORD5 38 11 B5 10.0k
2A3 2Y3
ORD4 37
2A4 2Y4
12 B4
B3 R517
U500B 20.0k
R518
10.0k
25 B2 R519
3OE
20.0k
ORD3 36 3A1 3Y1 13 B3
ORD2 35 14 B2 R520
3A2 3Y2
ORD1 33 16 B1 10.0k
3A3 3Y3
ORD0 32
3A4 3Y4
17 B0
B1 R521
U500C 20.0k
R522
U500D 10.0k
P5V
24 B0 R523
4OE
P5V 20.0k
30 19
4A1 4Y1
29 20 R524
4A2 4Y2
27 22 20.0k
4A3 4Y3
26 4A4 4Y4 23
GND
74ACT16244DL
GND GND GND
Figure 12. R-2R Digital-to-Analog Converter Schematic
The 74ACT16244 16-bit buffer does level translation between the 3.3-V logic and the 5.0-V logic and
drives the R-2R resistor ladder. Capacitors C500–C503 are local bypass capacitors for the P5V voltage
rail which is also the voltage reference for the DAC. The resistor, R509, is a pulldown for the output
enable signal. Unused lines are connected to the ground to maintain the known state. Resistors
R500–R508 and R510–R524 are a part of the R–2R resistor ladder. The output of the DAC is connected
to the BNC connector J7.
2.4.6 Power Management IC

This subsystem covers basic reverse-polarity protection, input filters, and the intelligent power
management IC that supplies the rest of the circuitry.
For a system interface overview of the power management IC, see Table 6.
Table 7. System Interface for the Power Management IC

VPROT Out Reverse polarity protected input voltage
VBCKP Out Backup (reserve) voltage rail, set to +5.0 V, unused
P6V Out 6.0-V Bias supply
P5V Out 5.0-V Bias supply
P3V3 Out 3.3-V Bias supply
P1V8 Out 1.8-V Bias supply
VIN In Input voltage
nRST Out System reset signal
DIAG_PMI Out Diagnostic signal from the PMIC
C
WDT_TRI In Watchdog timer trigger signal
G
EN_DRV Out Driver enable signal. This signal enables DRV8305-Q1 when the PMIC
operates in active mode.
SCS In SPI interface, chip select
Figure 13 shows a schematic of the power management IC.

INPUT FILTER AND REVERSE POLARITY PROTECTION
Q600
BC846B,215
D600
2 3 R600 VCP
10.0k
0603 Diode
1
R601
10.0k
4
L600 VBAT_PROT
GND 1
2 5
VIN
3 2.2uH
Q601
VCORE LIN. REGULATOR
SQJ422EP-T1-GE3 C600 C601 C602 C603
C604 C605 C606 220uF 220uF C607 C608 C609 220uF 220uF
0.01uF 0.1uF 1uF 50V 50V 0.01uF 0.1uF 1uF 50V 50V Q602
50V 50V 50V 50V 50V 50V P6V BUK92150-55A,118 P1V8
Vcore = 1.8 V
4 3
GND
R602 R603
1
68.0k 101
VDD1_G 0.1%
C610
22uF
R604 16V
VDD1_FB 80.6
GND GND 0.1%
GND GND
C611 C612 C613 C614 U600 C615 C616

10uF 0.1uF 0.1uF 0.1uF 4.7uF 4.7uF
35V 50V 50V 50V 22 21 16V 16V
P3V3 VDDIO VDD3/5 P3V3
CONFIGURATION 1 20 DC-DC PRE-REGULATOR
VBAT_PROT VBAT_SAFING VDD5 P5V
C617 VTRACK1
18
GND
TP600 VBAT_PROT 29
VBATP L601 P6V Controlled ESR
27
R605 VDD6 P6V R606
Ignition wake-up (OFF) IGN VCP 0.1uF 50V 2
VCP SDN6
28
20.0k 33uH 0.15
TP601 16 17
P6V VSIN VSOUT1
CAN wake-up (OFF) CANWU R607 11 15 D601 C618 C619 C620 C621
SCLK SCLK VSFB1 MBRS340T3G
20.0k C622 9 0.01uF 0.1uF 22uF 22uF
SDI SDI
0.1uF 10 24 VDD1_FB 50V 50V 16V 16V
SDO SDO VDD1_SENSE
50V 8
CS
R608 SCS
Reset Extension Time RSTEXT VDD1_G
26 VDD1_G
20.0k GND IGN 30 IGN
CANWU 14 CANWU DIAG_OUT 7 GND
DIAG_PMIC
GND
RSTEXT 12
RSTEXT CP1
3
13 C623
WDT_TRIG ERROR/WDI
4 0.01uF
31
CP2
50V EXTRA LDO
SEL_VDD3/5
GND 19
VBAT_PROT 6 NRES GND 23 VBCKP
nRST
5
PGND Vbckp = 5 V
32 25
VPROT EN_DRV ENDRV PGND
33
PAD
P6V
TPS65381AQDAPRQ1 R609
GND 3.32k
P6V
0.1%
P5V
C624
4.7uF
P5V
R610 16V
P3V3 3.32k
0.1%
P3V3
VBCKP GND GND
VBCKP
P1V8
P1V8
GND
GND
Figure 13. Power Management IC Schematic
The diode, D600, transistors Q600, Q601, and resistors R600, R601 provide basic reverse polarity
protection. During the normal condition, the substrate diode of the transistor Q601 conducts and allows
the system to start up. The internal charge pump in U600 generates a voltage on the VCP pin higher than
the input voltage. This voltage opens the source-drain channel of the Q601 with resistance down to RDS(on)
and reduces the voltage drop on the substrate diode. The transistor Q600 starts conducting during the
reverse polarity event and shorts the G-S junction of the Q601. This prevents the transistor Q601 from
opening if the residual charge on the capacitor C617 keeps voltage on the VCP higher than the VTH. The
resistor R601 limits maximum current through the base of the Q600. The diode D600 protects the
transistor Q600 from damage during the normal condition. The resistor R600 prevents the integrated
charge pump from overloading. Capacitors C600–C609 and the inductor L600 form an input π-type filter.
The filter is dimensioned with respect to the BLDC driver. For further details about this circuitry, see
Automotive 12 V 200 W (20 A) BLDC Motor Drive Reference Design. The TPS65381A-Q1 safety PMIC
generates all regulated bias voltages. The system design follows the recommended circuitry from
TPS65381A-Q1 Multirail Power Supply for Microcontrollers in Safety-Relevant Applications. Capacitors
C611–C616 and C622 are bypass capacitors. The internal charge pump requires capacitors C617 and
C623 for proper operation. Resistors R605 and R607 are pullup resistors for ignition and CAN wake-up
signals. Two test-points TP600 and TP601 allow for external control, if needed. The resistor R608 sets the
extension time for the integrated reset circuitry. The PMIC uses a buck converter as a pre-regulator to
reduce the power dissipation inside the device. Resistor R606 artificially increases equivalent series
resistance of the output capacitors C620 and C621. This is important for the hysteretic-based control
because the output voltage ripple must be large enough to overcome the comparator hysteresis. The
inductor L601 and diode D601 make the rest of the step-down converter topology. Capacitors C618 and
C619 suppress-high frequency content from the switching. The output of the integrated linear regulator
VDD1 supplies the MCU core by default. The regulator uses the external N-FET transistor Q602 and
senses the output voltage on the feedback divider R603 and R604. The feedback divider uses 0.1%
tolerance resistors to match the MCU specification. The capacitor C610 is an output capacitor required for
stability. The resistor R602 is recommended in the device data sheet. The TIDA-01507 does not use the
integrated VSOUT1 linear regulator but the regulator is active. 0.1% tolerance resistors R609 and R610
set the output voltage to 5.0 V. The low-ESR ceramic capacitor C624 is required for stability. The output of
the regulator is accessible on the PCB in the area with exposed copper close to the U600.
Hardware, Software, Testing Requirements, and Test Results www.ti.com
3 Hardware, Software, Testing Requirements, and Test Results
3.1 Required Hardware and Software
3.1.1 Hardware
Commissioning the reference design requires only an external 12-V power supply and a debug probe
compatible with the MCU. Texas Instruments recommends XDS110 JTAG Debug Probe (TMDSEMU110-
U). Alternatively you may use a C2000 LaunchPad with the XDS100 debugger and wire out JTAG signals.
Additionally, make sure that the power supply output power capabilities match the system and the motor
used.
3.1.2 Software
3.1.2.1 Download and Install CCS

The reference design uses the MotorWare Software package for the DC brushless motor control and
system controllers. Download the latest version from www.ti.com to get started.
See the Code Composer Studio (CCS) web page at www.ti.com/tool/ccstudio for information on
downloading and using the integrated development environment (IDE) for the C2000 microcontrollers.
3.1.2.2 Import the TI Design Software to CCS

Extract files from the provided firmware package to the preferred location. Import the project to CCS by
clicking “Project->Import CCS Projects…” from “..\sw\solutions\instaspin_servo\boards\TIDA-
01507\f28x\f2806xM\projects\ccs\proj_resolver01b” as Figure 14 shows.
Figure 14. Import TIDA-01507 Project to CCS
The "sw/solutions" directory contains example projects, drivers, and modules for motor control. Figure 15
shows the project content, including some files and folders that are described in the following list:
• src_board folder includes hal.c, drv8305q1.c, pga411q1.c and tps65381a.c for device drivers
• src_device folder includes device-support files
• src_driver folder includes the device peripherals driver files, such ADC, PWM, GPIO, and SCI
• src_lib folder includes instaSPIN-FOC FAST and IQmath supporting libraries
www.ti.com Hardware, Software, Testing Requirements, and Test Results
• src_module folder include instaSPIN-FOC files, such as Park, Clarke, and PID
• project_resolver01b.c file includes major functions and ISR for motor control
• main_resolver.h file includes gMotorVars definition
src_board folder includes hal.c, drv8305q1.c, pga411q1.c and tps65381a.c for devices driver.
Figure 15. TIDA-01507 Project Content in CCS
3.1.2.3 Setup the Hardware Configuration in Project Files

After installation of the CCS software and import of the project_resolver01b project, the next step is
changing hal.c and userResolver.h files based on hardware.
Modify the HAL_setupAdcs(), HAL_setupPwms(). and HAL_setupGpios() in hal.c to configure the
ADC, PWM, and GPIO peripheries based on the hardware board used.
Modify the USER_ADC_FULL_SCALE_VOLTAGE_V, USER_IQ_FULL_SCALE_VOLTAGE_V,
USER_IQ_FULL_SCALE_CURRENT_A, and USER_ADC_FULL_SCALE_CURRENT_A macros
according to Section 2.4.1 and the hardware board used.
NOTE: TIDA-01507 hardware typically does not require changes for initial testing.
3.1.2.4 Faults Protection for Motor Drive

The reference design implements full protection features for motor drive control. The faults include
overcurrent (OC), overvoltage protection (OV), undervoltage protection (UV), overload (OL), lost phase,
phase imbalance, stall, start-up failed, and driver overtemperature (OT). The motor stops immediately if
the system detects any faults.
3.1.2.5 Run the TIDA-01507 Software

The TPS65381A-Q1 power management IC has safety protection mechanisms which require specific
configuration over SPI during the start-up within the given time interval. It is important to pre-load the
firmware binary to FLASH memory in the MCU. The code in FLASH configures the PMIC right after
system powerup and allows for JTAG debugging. Follow the next steps:
1. Change the “build configuration” to “FLASH” in the “Project->Build Configurations->Set Active-> 1
Flash..” menu
2. Select the correct target configuration. The JTAG connection depends on the emulator you are using.
The target device on this TIDA-01507 reference board is TMS320F28069M.
3. Build and debug the project. Ensure the project is active by clicking on the project name. Build the
project by clicking the build icon on the CCS Edit tool bar. Start a debug session by clicking
the debug icon on the CCS Edit tool bar. This downloads the target code to the MCU of the
reference board.
4. Power off the board, disconnect the emulator, and then power on the board. The yellow and red LED
are flashing which means the TPS65381A-Q1 is configured properly. Now, reconnect the JTAG
emulator.
5. Click the debug icon to start debugging the project again. You can use either the “FLASH” or “RAM”
configuration in this step.
6. Run the project from the "Run->Resume" menu.
7. Click “View->Scripting Console” in the CCS Debug window. When the windows appears, click on the
Load Scripting Console Command File icon and select proj_resolver01b.js. This imports variables
necessary for debug to the variable expressions view as Figure 16 shows.
Figure 16. Add Expressions in CCS Debug Window
8. Enable Silicon Real-time mode by clicking the “clock” icon in the CCS Debug toolbar. Click
“Yes” when the dialog in Figure 17 appears. Then click the run icon to run the project. Stop the
motor first and disable “Real time Debug Mode”, if you want to reprogram the code to on-chip flash.
Figure 17. Enable Real-Time Debug Mode

9. Run the motor. Set the gMotorVars.Flag_Run_Identify to 1, and change the value of
gMotorVars.SpeedRef_krpm to target speed.
NOTE: The motor starts spinning and it takes about 10 s for the initial start-up and motor
parameters identification. The process includes the current, voltage and the resolver angle
offset calibration.
3.1.2.6 Motor Parameters Identification Without Load

Open “userResolver.h” from the directory in the project where a definition of motor parameters exists. You
can either create a new header file "userNew.h" or add a new motor definition to "userResolver.h". Add
the following values before execution of the identification routine:
• USER_MOTOR_TYPE -> MOTOR_Type_Pm
• USER_MOTOR_NUM_POLE_PAIRS -> Number of pole pairs of the motor
• USER_MOTOR_RES_EST_CURRENT -> The motor must initially be started in open loop. This value
sets the peak of the current used during initial motor start up. If the motor has high cogging torque or
some kind of load, increase this current value until the motor starts spinning. After motor identification,
this value is never used.
• USER_MOTOR_IND_EST_CURRENT -> For PMSM motors this value can be set to the negative
value of the current used for USER_MOTOR_RES_EST_CURRENT.
• USER_MOTOR_MAX_CURRENT -> Maximum current rating of the motor.
Follow these steps to execute parameter identification:
1. Set "gMotorVars.Flag_enableUserParams" to 0, and then set "gMotorVars. SpeedRef_krpm" to
_IQ(0.0). Set "gMotorVars.Flag_enableUserParams = false".
2. Set "gMotorVars. Flag_Run_Identify" to 1, the identification starts and takes about 9 s to complete the
identification process as Figure 18 shows.
3.1.2.7 Controlling the System With the Potentiometer

By default, the potentiometer on the PCB allows for speed control. Follow these steps to enable manual
control using the potentiometer:
1. Turn the potentiometer anti-clockwise until it reaches the limit position to set the target speed to zero
and stop the motor.
2. Set "gMotorVars.Flag_enableExtSpeedSet" to “true” in the project_resolver.c file
3. Build the project, power on the board, connect the emulator, and download the code into the MCU.
4. Power off the board, disconnect the emulator, and power on the board again.
5. Turn the potentiometer clockwise to start the motor and set a target speed. The green LED on the
board shows status:
a. LED is off -> motor stopped
b. LED lights constantly -> motor stopped, fault detected
c. LED is flashing -> motor is running, flashing period is proportional to motor speed
The following macros in "main_resolver.h" define the relationship between potentiometer position and
target speed:
// The defines for manual control by potentiometer
#define SPEED_EXT_SET_MAX_RPM 1800 // maximum speed = 1800rpm
#define SPEED_EXT_SET_MIN_RPM 30 // minimum speed = 30rpm
#define ADC_SPD_SET_MIN_LOW 100 // the minimum adc input of potentiometer

#define ADC_SPD_SET_MIN_HIGH 300 // the lowest adc input of potentiometer
#define ADC_SPD_SET_MAX_LOW 3900 // the highest adc input of potentiometer
#define ADC_SPEED_SET_SCALE 8388 // the scale coefficient (1800/(3900-300)/1000)*2^24
3.2 Testing and Results
3.2.1 Test Setup

The complete test environment consists of one of the test setups mentioned in Section 4.4, and a
laboratory power supply or AC/DC adapter with a nominal output voltage of 12 V, capable of rated current
corresponding to the motor.
3.2.2 Test Results
3.2.2.1 Motor Parameters Identification Without Load

Figure 18 through Figure 23 show various motor test results.
Ch1 – A phase current of motor, Ch2 – B phase current of motor, Ch3 - DC bus input voltage. Input voltage is 12 VDC.
Figure 18. Motor Parameters Identification in Room Temperature
Ch4 – A phase current of motor, Ch3 – (B-C) phase current of motor.

Figure 19. Motor Running With 30 RPM


Figure 22. Comparison of the FAST Estimated Rotor Angle (Top) and
Resolver Output (Bottom) at 600 RPM
Figure 23. Comparison of the FAST Estimated Rotor Angle (Top) and
Resolver Output (Bottom) at 1500 RPM
www.ti.com Design Files
4 Design Files
4.1 Schematics
Download the schematics from the design files at TIDA-01507.
4.2 Bill of Materials

Download the bill of materials (BOM) from the design files at TIDA-01507.
4.3 PCB Layout Recommendations

The TIDA-01507 PCB layout does not require any unusual considerations. The PCB uses 4-layers with
single-side component placement, typical for inexpensive prototyping services. Signal traces use the top
(layer1) and the bottom (layer 4) layer. Two internal layers (Internal Plane 1 and Internal Plane 2)
distribute power across the PCB.
Figure 24 shows how each subsystem relates to the PCB layout.
R-2R DAC
BLDC
Driver Resolver
Front-End
Power
Management
Isolated CAN
Interface
Input Filter
C2000 MCU
Figure 24. TIDA-01507 Subsystems Distribution Over the PCB
NOTE: Always refer to a device data sheet for the latest design and PCB layout recommendations.
Recommendations in this section may differ due to different design preferences.
Table 8. TIDA-01507 PCB Layout - Selected Design Rules and PCB Properties
SEGMENT DIMENSIONS
General traces (analog, digital) width 6 mil
Power traces – low current < 1-A width 10 mil–30 mil
Preferred via size 28 mil diameter and 12 mil drill
Minimal clearance 6 mil
Components placement Top side only
Passive components package size 0603 (preferred) or larger
Copper plating 18 µm (35 µm after processing) for layer 1 and layer 2; 35 µm for internal plane 1 and
internal plane 2
PCB thickness 1.6 mm
Dimensions 100 mm × 80 mm
Design Files www.ti.com
4.3.1 Internal Planes

Figure 25 shows the inverted internal plane 1. Internal plane 1 distributes common grounds (GND, 1GND).
Observe the cutout for the PMIC (U600). The cutout controls the current return path for the step-down pre-
regulator. This isolates switching currents from the general ground plane and minimizes electromagnetic
interference (EMI).
Cutout for the PMIC

Pre-Regulator
Ground Cutout for the

Isolated CAN Interface
Figure 25. TIDA-01507 Internal Plane 1 (Inverted)
Figure 26 shows inverted internal plane 2. Internal plane 2 distributes positive voltage rails.
QVCC
PVDD
P5V
VAMP
PVDD
VCCSW
P6V
P1V8
1P5V
P3V3
Figure 26. TIDA-01507 Internal Plane 2 (Negative)
4.3.2 BLDC Driver Layout Recommendations

Figure 27 highlights the most important layout recommendations for the BLDC driver based on the
DRV8305-Q1 device. The figure shows only signal layers for simplicity. Current sensing is the most
delicate as it carries signals of a small amplitude. For this reason, the current sensing signals are routed
differentially, using the shortest path to the input of the integrated current sense amplifiers in the
DRV8305-Q1 device. Observe that the filtering capacitors C116, C117, and C119 are as close to the
current sense amplifier inputs as possible. Gate driver signals use differential routing for each gate-source
signal pair. Voltage sensing signals avoid the power stage and go to the ADC. Note that voltage resistor
dividers and filtering are closer to the microcontroller rather than to the power stage. This increases noise
immunity but may cause EMI RF radiation issues. Local DC-link capacitors C101–C103 and C109–C111
are evenly split between each H-bridge.
Motor Terminal
Phase Voltage Sensing
Current Shunt
Local DC-Link
C116, C117, C119
Current Sensing
Gate-Driver Signals
Figure 27. BLDC Driver PCB Layout
4.3.3 C2000™ Microcontroller Layout Recommendations

Figure 28 shows the recommended PCB layout for the C2000 microcontroller subsystem. The figure
shows only layer 1 and internal plane 2 for simplicity. Internal plane 2 distributes P1V8 voltage rail for the
MCU core and P3V3 voltage rail for GPIOs. Note that bypass capacitors are as close to the power pins of
the MCU as possible. The PCB layout does not use the concept of separate analog and digital (or power)
grounds and for that reason, all analog signals refer to the same ground. It is important that all ground
signals use a low-impedance connection to internal plane 1. Voltage and current sensing signals, input
filters as well as analog supply VCCA and voltage reference output avoid noise sources.
GND
P3V3
P1V8
Current
Sensing
Voltage
Reference
Voltage
Sensing
VCCA
Figure 28. C2000™ Microcontroller Subsystem PCB Layout
4.3.4 Resolver Front-End Layout Recommendations

Figure 29 shows the PCB layout for the PGA411-Q1 resolver front-end subsystem. The figure shows only
layer 1 and internal plane 2 for simplicity. Internal plane 2 distributes all required power rails. The PCB
layout of the boost converter is critical. It is important to minimize current loop areas in the switch
topology. Analog front-end components for IZ1, IZ3 and IZ2, IZ4 inputs use symmetrical placement and
layout. Input transient protection is between the each block. Feedback network placement for the exciter
amplifier is less critical but components stay grouped together. The transient protection for the exciter
amplifier uses a low-impedance connection to the clamping voltage rail V_AMP. For more details on PCB
layout for the PGA411-Q1, see PGA411-Q1 PCB Design Guidelines.
Analog Inputs
Transient Protection
QVCC Voltage Rail and

Filter
Analog Front-End Exciter Amp

Feedback Network
Exciter Amp Transient

P5V Voltage Rail Protection
P3V3 Voltage Rail
V_AMP
Voltage Rail
BOOST DC-DC
Figure 29. Resolver Front-End PCB Layout Based on the PGA411-Q1
4.3.5 Isolated CAN Interface Layout Recommendations

Figure 30 highlights the most important PCB layout recommendations for the isolated CAN interface. The
figure shows only layer 1 and internal plane 2 for simplicity. The isolation barrier is clearly defined by
cutouts on both internal planes. Signal layers avoid crossing the isolation barrier too, with a small
exception for the bottom layer.
NOTE: The isolated CAN interface implements functional isolation only.
Isolation Barrier (Internal Plane 1,

Internal Plane 2)
Isolated Power Supply
Linear Regulator
P5V Voltage Rail
GND CAN Transceiver
1P5V Voltage Rail

Digital Isolator
1GND
Figure 30. Isolated CAN Interface PCB Layout
4.3.6 R-2R Digital-to-Analog Converter Layout Recommendations

This block is for evaluation purposes only and does not follow any special recommendations.
4.3.7 Power Management IC Layout Recommendations

Figure 31 shows the PCB layout for the power management. The figure shows only layer 1 and internal
plane 2 for simplicity. The PCB layout of the buck pre-regulator is important. Similarly to the boost
converter in the resolver front-end subsystem, it is important to minimize current loop areas in the switch
topology. A cutout in the ground plane shown in Figure 25 defines the current return path. Bypass
capacitors and output capacitors for the linear regulators are close to the package. Each voltage rail
connects to internal plane 2 through multiple vias.
P6V Voltage Rail
P3V3 Voltage Rail

PVDD Voltage Rail
P5V Voltage Rail
VBCKP Voltage Rail
P1V8 Voltage Rail
Figure 31. Power Management PCB Layout Based on the TPS65381A-Q1
4.3.8 Layout Prints

Download the layer plots from the design files at TIDA-01507.
4.4 Mechanical Construction

The TIDA-01507 test setup uses several acrylic glass and 3D-printed components. All these custom
components were ordered in single quantities from sculpteo.com. The following sections show different
test setups which may inspire you for creating your own.
Download the mechanical CAD data in DXF and STL format from the design files at TIDA-01507.
Table 9 lists the standard components used in test setups in addition to the custom ones.
Table 9. List of Standard Components Used With TIDA-01507 Test Setups

Name Supplier Manufacturer Ordering number
Rubber feet Farnell PD.2115BL
M3 nuts
M3×5 standoffs Farnell 05.13.051
M3×8 screws Farnell M38 BHA2MCS100-
M4×10 screws Farnell D01437
M4×20 screws Farnell 2770746
RS2306 Motors Conrad Elektronik 1550424
Maxon EC40 + RES26 Maxon Motors 401949 (369146+133405)
Cable clips Farnell DTRMWSSEB-1-01A2-RT
Resolver HIROMAX 21BRX709-E23AA Mouser 21BRX709-E23AA
Resolver HIROMAX 21BRX709-E23AA Mouser 21BRX709-E23AA
Threaded inserts M5 Farnell M5-UHBRXPSF
Connector 3-pos Farnell MSTB2,5/3-ST-5,08
Connector 2-pos Farnell 1757019
Washer M3 Farnell 3116
Spacer 3.2 mm, 6 mm × 1.5 mm Farnell 05.53.015
4.4.1 Test Setup With Maxon™ EC40 Motor and RES26 Resolver
The test setup with the Maxon EC40 motor and RES26 shown in Figure 32 provides far best performance
due to the fact that motor and resolver come assembled together from the manufacturer with assured
parameters.
Figure 32. Test Setup With Maxon™ EC40 and RES26
Table 10 lists custom components for the test setup shown in Figure 32.
Table 10. List of Custom Components for the Test Setup With EC40 Motor and
RES26 Resolver
Qty Material Design Data File
1 Acrylic Glass 5 mm base_v1.dxf
1 Acrylic Glass 5 mm EC40-RES26_mount_back_v1.dxf
1 Acrylic Glass 3 mm EC40-RES26_mount_v1.dxf
4.4.2 Test Setup With RS2306 Motor and HAROMAX™ 21BRX709-E23AA Resolver
Figure 33 shows the test setup with RS2306 motor and HAROMAX™ 21BRX709-E233AA resolver. The
setup uses the least-expensive resolver available in single quantities. However, positioning of the rotor
using the 3D printed motor-resolver adapter is not very precise and adds various errors to the angle
readout. TI recommends this test setup for educational purposes only.
Figure 33. Test Setup With RS2306 and HAROMAX™ 21BRX709-E23AA
Table 11. List of Custom Components for the Test Setup With RS2306 and
21BRX709-E23AA Resolver
1 Acrylic Glass 5 mm 21BRX709-E23AA_mount_v1.dxf
1 Acrylic Glass 3 mm 21BRX709-E23AA_inner_ring_v1.dxf
1 Acrylic Glass 5 mm 21BRX709-E23AA_top_lid_v1.dxf
1 3D print SLS, Nylon PA12 120u (white) 21BRX709-E23AA_adapter_M5x12_v4.stl
4.4.3 Test Setup With RS2306 Motor and HAROMAX™ 21BRX701-J42AA Resolver
This test setup shown in Figure 34 is similar to the one described in Section 4.4.2. However, mechanical
dimensions of the resolver are slightly different. For this reason the setup uses a different set of custom
components.
Figure 34. Test Setup With RS2306 and HAROMAX™ 21BRX701-J42AA
Table 12. List of Custom Components for the Test Setup With RS2306 and
21BRX701-J42AA Resolver
1 Acrylic Glass 5 mm 21BRX701-J42AA_mount_v1.dxf
1 POM 2 mm 21BRX701-J42AA_washer_v1.dxf
1 3D print SLS, Nylon PA12 120u (white) 21BRX701-J42AA_adapter_M5x12-7_v3.stl
4.5 Altium Project

To download the Altium project files, see the design files at TIDA-01507.
4.6 Gerber Files

To download the Gerber files, see the design files at TIDA-01507.
4.7 Assembly Drawings

To download the assembly drawings, see the design files at TIDA-01507.
5 Software Files
To download the software files, see the design files at TIDA-01507.
Recommended Changes www.ti.com
6 Recommended Changes
A list of recommended changes follows:
1. If the brightness of the D202 LED is too high, increase R220.
2. The UART interface uses the SCIB periphery for the RXD line and the SCIA periphery for the TXD line.
Use one of the spare testpoint signals (for example, TEST2) to fix this.
3. Add a resistor in series with the EN_DRIVE signal. This allows overriding the EN_DRIVE signal and
using DRV8305-Q1 even when the PMIC TPS65381A-Q1 does not operate in normal state.
4. Add a resistor in series with potentiometer R1. This allows full-range operation in case the voltage
reference is different than 3.3 V.
5. Add protection (clamping) to the ACTRL signal.
6. Add an external pullup resistor for the PGA411-Q1 FAULT signal.
7. Remove R202 and R206 to pullup the TDO and GPIO34 pins to high, this enables the MCU run from
FLASH in default mode during powerup.
8. Change C312, C316 to 220 pF if you observe that the tracking loop of the PGA411-Q1 occasionally
fails to lock. The exact value depends on the resolver impedance, phase shift, and wiring harness.
7 Related Documentation
1. Texas Instruments, InstaSPIN-FOC™ and InstaSPIN-MOTION™ User's Guide
2. Texas Instruments, Sensorless Field Oriented Control of 3-Phase Permanent Magnet Synchronous
Motors Application Report,
3. Texas Instruments, Sensored Field Oriented Control of 3-Phase Induction Motors Application Report
4. Texas Instruments, Sensorless Field Oriented Control of 3-Phase Induction Motors Using F2833x
Application Report
5. Texas Instruments, Sensored Field Oriented Control of 3-Phase Permanent Magnet Synchronous
Motors Application Report
6. Texas Instruments, Automotive Resolver-to-Digital Converter for Safety Applications TI Designs Guide
7. Texas Instruments, EMC Compliant Single-Chip Resolver-to-Digital Converter (RDC) Reference
Design
8. Texas Instruments, Automotive 12 V 200 W (20 A) BLDC Motor Drive Reference Design TI Designs
Guide
9. Texas Instruments, LMT86, LMT86-Q1 2.2-V, SC70/TO-92/TO-92S, Analog Temperature Sensors
Data Sheet
10. Texas Instruments, TPS65381A-Q1 Multirail Power Supply for Microcontrollers in Safety-Relevant
Applications Data Sheet
11. Texas Instruments, PGA411-Q1 Resolver Sensor Interface Data Sheet
12. Texas Instruments, Automotive Reinforced Isolation CAN Reference Design
13. Texas Instruments, Simplify CAN bus implementations with chokeless transceivers White Paper
14. Texas Instruments, PGA411-Q1 PCB Design Guidelines Application Report
7.1 Trademarks
C2000, InstaSPIN, InstaSPIN-FOC, Code Composer Studio, InstaSPIN-MOTION, MotorWare,
controlSUITE, FAST, Piccolo, Hercules are trademarks of Texas Instruments.
HAROMAX is a trademark of DYNAPAR.
Maxon is a trademark of MAXON Computer Inc.
All other trademarks are the property of their respective owners.
www.ti.com Terminology
8 Terminology
PMIC— Power Management Integrated Circuit also referred as System Basis Chip (SBC)
BEMF— Back Electromotive Force
DAC— Digital-to-Analog Converter
I2C— Inter-integrated Circuit also known as TWI - Two Wire Interface
FOC— Field Oriented Control also known as vector control
IGBT— Insulated Gate Bipolar Transistor
FET (N-FET)— Field-Effect Transistor (N -channel)
EMI— Electromagnetic Interference
ADC— Analog-to-Digital Converter
CSA— Current-sense Amplifier
JTAG— Joint Test Action Group
QEP— Quadrature Encoder Pulse
EMC— Electromagnetic Compatibility
LDO— Low-drop Output
PSRR— Power Supply Rejection Ratio
ESR— Equivalent Series Resistance
GPIO— General Purpose Input Output
9 About the Author

JIRI PANACEK is a systems engineer in the Powertrain Automotive Systems team at Texas Instruments
where he develops reference designs. Jiri has five years of field experience in the industrial automation
and most recently the EV/HEV automotive segment. Jiri earned his master's degree in microelectronics
from the Brno University of Technology in the Czech Republic.
Special thanks go out to Yanming Luo for firmware development and Clancy Kangude (Soehren) for
testing and development support.
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Resolver-Based Motor Control Reference Design With A BLDC Motor and C2000™ MCU

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TI Designs: TIDA-01507

Resolver-Based Motor Control Reference Design With a

170-W BLDC RESOLVER

KL30 (12 V) PMIC P5V

Figure 1. Typical 3-Phase Motor Control System

Figure 2. Different Variants of Current Sensing in Motor Drive Applications

Figure 3. Resolver as a Rotating Transformer

1.1 Key System Specifications

Table 1. Key System Specifications

Protection Overcurrent, overtemperature, overvoltage, undervoltage, overload, over

Figure 4. System Overview

The PCB-implemented subsystems follow:

Power Supply Input Micro USB

Figure 5. TIDA-01507 PCB

Motor-resolver assembly options:

2.1 InstaSPIN-FOC™ for PMSM

Figure 6. InstaSPIN-FOC™ Block Diagram

InstaSPIN-FOC benefits include:

and user adjustments required for optimum transient response

2.2 Block Diagram

KL30 (12 V) PMIC P5V

Figure 7. TIDA-01507 Block Diagram

2.3 Highlighted Products

2.4 System Design Theory

2.4.1 BLDC Driver

Table 2. System Interface for the BLDC Driver

Figure 8 shows a schematic of the BLDC driver block.

Figure 8. BLDC Driver Schematic

2.4.2 C2000™ Microcontroller

Table 3. System Interface for the C2000™ Microcontroller

Table 3. System Interface for the C2000™ Microcontroller (continued)

Figure 9 shows the C2000 microcontroller block schematic.

Figure 9. C2000™ Microcontroller Schematic

2.4.3 Resolver Front-End

Table 4. System Interface for the Resolver Front-End

Figure 10 shows the resolver front-end schematic.

Figure 10. Resolver Front-End Schematic

2.4.4 Isolated CAN Interface

Table 5. System Interface for the Isolated CAN

Figure 11 shows the isolated CAN schematic.

P3V3 P3V3 U400 1P5V

C400 C401 2 2 5 GND

10V 50V 5 1 10uF 0.1uF 10uF

VCC CANH CANH

NOTE: This block is inspired by ti.com/TOOL/TIDA-01255

Figure 11. Isolated CAN Interface Schematic

2.4.5 R-2R Digital-to-Analog Converter

Table 6. System Interface for the R-2R Digital-to-Analog Converter

Figure 12 shows the R-2R DAC schematic.

Figure 12. R-2R Digital-to-Analog Converter Schematic

2.4.6 Power Management IC

Table 7. System Interface for the Power Management IC

Figure 13 shows a schematic of the power management IC.

C611 C612 C613 C614 U600 C615 C616

Figure 13. Power Management IC Schematic

3 Hardware, Software, Testing Requirements, and Test Results

3.1 Required Hardware and Software

3.1.2.1 Download and Install CCS

3.1.2.2 Import the TI Design Software to CCS

Figure 14. Import TIDA-01507 Project to CCS

Figure 15. TIDA-01507 Project Content in CCS

3.1.2.3 Setup the Hardware Configuration in Project Files

3.1.2.4 Faults Protection for Motor Drive