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Cxa2061S: Y/C/Rgb/D For NTSC Color Tvs
Cxa2061S: Y/C/Rgb/D For NTSC Color Tvs
Description
The CXA2061S is a bipolar IC which integrates 48 pin SDIP (Plastic)
the luminance signal processing, chroma signal
processing, RGB signal processing, and sync and
deflection signal processing functions for NTSC
system color TVs onto a signal chip. The IC also
includes deflection processing functions for wide
TVs.
Features
• Reduction in peripheral parts
(ceramic oscillator, AKB sample-and-hold capacitor, etc.)
• I2C bus compatible
• Built-in deflection compensation circuit which is capable of supporting variaus wide modes
• Non-adjusting V oscillator frequency with a countdown system
• Non-interlace display support (even/odd selectable)
• Non-adjusting Y/C filter
• Three sets of CV inputs, two sets of Y/C inputs (can serve as both Y/C and CV inputs), one set of Y/C inputs
supports an external combfilter, two sets of RGB inputs, one set of YUV inputs
• It can be outputted YUV on RGB1 inputs
• Built-in dynamic picture and dynamic color circuits
• Built-in AKB and gamma correction circuits
• FSC output
Applications
Color TVs (4:3, 16:9)
Structure
Bipolar silicon monolithic IC
Operating Condition
Supply voltage VCC1, 2 9 ± 0.5 V
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E97538-PS
Block Diagram
R1 IN
EY IN
B2 IN (B-YOUT)
G1 IN
YUV SW
X'tal
Y CLAMP
APED
YS2/YM
GND2
B1 IN
YS1
VCC2
EB-Y IN
APC FIL
R2 IN (YOUT)
FSCOUT
ER-Y IN
G2 IN (R-YOUT)
VM OUT/
V PROT
45 47 46 44 40 8 1 15 39 38 37 36 28 27 26 25 32 31 30 29
YM SW
<PON>
CLAMP
YS2 SW
YS1 SW
<BRIGHT>
R/G/B BLK
<GAMMA>
Y/C MIX
DRIVE AMP
<PICTURE>
<RGB SEL>
<R/G/B ON>
22 R OUT
GAMMA AMP
<DYNAMIC C>
PICTURE AMP
BRIGHT CONT.
<R/G/B DRIVE>
CUTOFF CONT.
DYNAMIC COLOR
–2–
SHARPNESS DL
CHROMA SW SHARPNESS AMP
TV/C2 IN 43 TRAP + EQ
ATT <SHARPNESS> VD SAW FUNC.
<TRAP OFF> 14 VD–
<SHP F0> <VON> <S CORRECTION>
WIDE SAW FUNC.
C1 IN 2 <PRE/OVER> <V SIZE> <V LINEARITY>
<V POSITION> <EHT COMP> 13 VD+
<ASPECT>
CVBS2/Y2 IN 41 Y SW <SCROLL>
Y
<UPPER VLIN> EW PARABOLA FUNC.
COUNT DOWN LINE COUNTER <LOWER VLIN>
CVBS1/Y1 IN 4 VSAW GEN. <H SIZE> <TRAPEZIUM>
<CD MODE> V TIM GEN. <V ZOOM> 11 EW
VTIM <PIN AMP> <EW DC>
V SYNC SEP <INTERLACE> <V UNDER SCAN> <V UNDER SCAN> <CORNERPIN>
COMB-C IN 7 <VSS>
MONITOR SW
H SYNC SEP
COMB-Y IN 9 <HSS>
VIDEO SW PHASE DET.
<H MASK> AFC
H TIM GEN. <H POSITION>
<AFC GAIN> HSAW GEN. HD GEN.
MON OUT 6 <VIDEO SEL> <H BLK> <AFC BOW>
<FH HIGH> <HOSC> IREF REG
<S SEL> <LEFT HBLK> <AFC AMGLE>
<<HLOCK>> (ZAP) <HD W>
<RIGHT HBLK> HPROT
<<HCENT>>
<<HNG>>
20 17 5 18 19 10 12 16 33
HD
SCP
REG
VCC1
I REF
V TIM
GND1
AFC FIL
HP/
HPROTECT
CXA2061S
CXA2061S
Pin Configuration
APED 1 48 NC
C1 IN 2 47 X'tal
ABL IN 3 46 FSCOUT
CVBS1/Y1 IN 4 45 APC FIL
V TIM 5 44 VCC2
MON OUT 6 43 TV/C2 IN
COMB-C IN 7 42 ABL FIL
Y CLAMP 8 41 CVBS2/Y2 IN
COMB-Y IN 9 40 GND2
GND1 10 39 EB-Y IN
EW 11 38 ER-Y IN
I REF 12 37 EY IN
VD+ 13 36 YUV SW
VD– 14 35 SDA
VM OUT/V PROT 15 34 SCL
REG 16 33 VCC1
SCP 17 32 R2 IN
HP/PROTECT 18 31 G2 IN
HD 19 30 B2 IN
AFC FIL 20 29 YS2/YM
IK IN 21 28 R1 IN
R OUT 22 27 G1 IN
G OUT 23 26 B1 IN
B OUT 24 25 YS1
–3–
CXA2061S
Pin Description
Pin
Symbol Equivalent circuit Description
No.
4µA
1k
1 Capacitor connection for black peak hold
1 APED of the dynamic picture (black expansion).
94k
Connect to GND via a 4.7µF capacitor.
–4–
CXA2061S
Pin
Symbol Equivalent circuit Description
No.
1.5k
8 Capacitor connection for luminance signal
8 Y CLAMP clamp.
Connect to GND via a 0.1µF capacitor.
–5–
CXA2061S
Pin
Symbol Equivalent circuit Description
No.
10 GND1 GND (the deflection blocks circuit).
1.2k
11
11 EW V parabola wave output.
300µA
2k
13
13 VD+
300µA
14
14 VD–
300µA
–6–
CXA2061S
Pin
Symbol Equivalent circuit Description
No.
160
500 20k
77k
50µA
–7–
CXA2061S
Pin
Symbol Equivalent circuit Description
No.
147
19
H drive signal output of NPN transistor.
19 HD
Open collector output.
40k
40k
1k
20
AFC Iag-lead filter connection.
20 AFC FIL 100k
Connect CR to GND.
100k
2.5V
150 12k
R, G and B signal outputs. 2.4Vp-p is
22
22 R OUT 527 outputted during 100% white input.
23
23 G OUT PICTURE: 1Fh
24 B OUT 24 DRIVE: 1Fh
1k BRIGHT: 1Fh
–8–
CXA2061S
Pin
Symbol Equivalent circuit Description
No.
26
27 R1, G1 and B1 signal input. Input a 0.7Vp-p
26 B1 IN
28 (no sync, 100 IRE) signal via a 0.01µF
27 G1 IN
1.2k capacitor. The input signal is clamped at
28 R1 IN
the burst timing in SCP.
60k
–9–
CXA2061S
Pin
Symbol Equivalent circuit Description
No.
34
4k
34 SCL I2C Bus protocol SCL (Serial Clock) input.
10k
35
4k
35 SDA I2C Bus protocol SDA (Serial Data) I/O.
10k
YUV SW control.
147
Selects the external YUV input.
36
Vth: 0.7V
36 YUV SW
This switch has a function prohibited
20k forcibly only the external Y input by the
register Y SEL.
37
37 EY IN
1.5k
40k
External Y, R-Y and B-Y signal inputs.
Input the signal via a 0.01µF capacitor.
EY IN: 0.7Vp-p (no sync)
ER-Y IN: 0.735Vp-p (75% Color Bar)
EB-Y IN: 0.931Vp-p (75% Color Bar)
38
38 ER-Y IN
39
39 EB-Y IN
1.5k
65k
– 10 –
CXA2061S
Pin
Symbol Equivalent circuit Description
No.
147
CVBS signal/luminance signal input.
41
Input a 1Vp-p (including sync) signal via a
41 CVBS2/Y2 IN
50k 1µF capacitor. When inputting Y/C
separated signals, input the Y signal.
5.4V
20k
42 Connect a capacitor (4.7µF) to GND to form
42 ABL FIL
the LPF of the ABL control signal.
1.2k
Power supply
44 Vcc2
(mainly for the chroma block circuit).
4.9V
1k 1k
45 Chroma APC lag-lead filter connection.
45 APC FIL
Connect CR to GND.
– 11 –
CXA2061S
Pin
Symbol Equivalent circuit Description
No.
200 16k
46 FSC output.
46 FSC OUT
Output FSC signal by the register FSC SW.
15k
2.5k
47 APC crystal connection.
47 X'tal
X'tal: NTSC crystal (3.579545MHz)
1.333k
48 NC
– 12 –
Electrical Characteristics Measurement Condition
Measure the following after setting the I2C bus registers as shown in "I2C BUS register initial settings". Ta = 25°C, VCC1, VCC2 = 9V, GND1, DND2 = 0V
No. Item Symbol Measurement condition Measurement point Measurement contents Min. Typ. Max. Unit
VCC1, VCC2 = 9V
1 Current consumption ICC 33, 44 Measure the pin inflow current. 45 75 110 mA
Bus data: Initial setting
2 REG voltage VREG 16 Measurement the pin voltage. 7.4 7.6 7.9 V
Sync deflection block items
3 Horizontal freerunning frequency fHFR H OSC = 7h 19 H DRIVE output frequency 15.4 15.7 16.0 kHz
ASPECT = 3Fh
– 13 –
7 EW DRIVE output amplitude VEWp-p V SIZE = 1Fh 11 Measurement the EW DRIVE output Vp-p. 0.4 0.73 0.9 V
PIN AMP = 1Fh
8 EW DRIVE output center VEWdc H SIZE = 1Fh 11 Video center bias 3.7 4 4.3 V
Signal block items
4.7µ
1 APED NC 48 18p
C1 IN 2 C1 IN X'tal 47 NTSC X'tal
0.1µ
ABL IN 3 ABL IN FSCOUT 46
9V 10k 0.47µ
470p
CVBS1/Y1 IN 4 CVBS1/Y1 IN APC FIL 45
100 1µ
V TIM OUT 5 V TIM VCC2 44
1µ
MON OUT 6 MON OUT TV/C2 IN 43 TV/C2 IN
4.7µ
COMB-C IN 7 COMB-C IN ABL FIL 42
1µ 1µ 0.1µ 47µ
8 Y CLAMP CVBS2/Y2 IN 41 CVBS2/Y2 IN
COMB-Y IN 9 COMB-Y IN GND2 40
1µ 0.01µ
10 GND1 EB-Y IN 39
100 0.01µ
E/W 11 EW ER-Y IN 38 EXT YUV IN
10k 0.01µ
51k 12 I REF EY IN 37
V PROT
100
13 VD+ YUV SW 36 YUV SW
VD OUT 100 1k 100
– 14 –
14 VD– SDA 35 SDA
100 100
VM OUT 15 VM OUT/V PROT SCL 34 SCL
0.1µ 47µ
16 REG VCC1 33 VCC + 9V
10µ 0.01µ
HD SCP OUT 17 SCP R2 IN 32
0.01µ
7µs delay 18 HP/PROTECT G2 IN 31 RGB 2 IN
HP GEN 1µ 0.01µ
HP 19 HD B2 IN 30
1µ 4.7k 100
2.2k 20 AFC FIL YS2/YM 29 YS 2/YM
51k 0.01µ 0.01µ
H PROT 21 IK IN R1 IN 28
0.01µ
Quasi 22 R OUT G1 IN 27 RGB 1 IN
0.01µ
CRT 23 G OUT B1 IN 26
100
24 B OUT YS1 25 YS 1
CXA2061S
Application Circuit
4.7µ
1 APED NC 48 18p
2 C1 IN X'tal 47 NTSC X'tal
10k 0.1µ
CVBS/S input 3 ABL IN FSCOUT 46
0.1µ 10k 0.47µ
470p
4 CVBS1/Y1 IN APC FIL 45
100 1µ
V timing pulse output 5 V TIM VCC2 44
1µ
MON output 6 MON OUT TV/C2 IN 43
4.7µ
ABL/high voltage function 7 COMB-C IN ABL FIL 42 CVBS2/S2 input
compansation signal input 1µ 1µ 0.1µ 47µ
COMB 8 Y CLAMP CVBS2/Y2 IN 41
9 COMB-Y IN GND2 40
1µ 0.01µ
10 GND1 EB-Y IN 39
100 0.01µ
V parabora wave output 11 EW ER-Y IN 38
51k 10k 0.01µ External YUV input
V protect signal input 12 I REF EY IN 37
1k 100
13 VD+ YUV SW 36
V sawtooth wave output 100 100
14 VD– SDA 35
– 15 –
100 100 I 2C During C DEC mode
VM output 15 VM OUT/V PROT SCL 34
0.1µ 47µ
10µ 16 REG VCC1 33 VCC + 9V
0.01µ 10k
Sand castle pulse output 17 SCP R2 IN 32 32
1µ 0.01µ
100 External RGB2 10k
H deflection pulse input 18 HP/PROTECT G2 IN 31 31 VCC
2.2k input
0.01µ 10k
HD output 19 HD B2 IN 30 30
51k 1µ 4.7k 100
X-ray protect signal input 20 AFC FIL YS2/YM 29
0.01µ 0.01µ
IK input 21 IK IN R1 IN 28
100 0.01µ
22 R OUT G1 IN 27
100 0.01µ External RGB1 input
RGB output 23 G OUT B1 IN 26
100 100
24 B OUT YS1 25
100
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
CXA2061S
CXA2061S
– 16 –
CXA2061S
– 17 –
CXA2061S
Slave Addresses
88H: Slave Receiver 89H: Slave Transmitter (25pin normal use)
8AH: Slave Receiver 8BH: Slave Transmitter (25pin pull up 7.5V or more)
∗: Don't care
Status Register
1st BYTE HLOCK IKR VNG HNG KILLER ID OFF 0 0 0
2nd BYTE HCENT 0 0 0 1 0 0 1
– 18 –
CXA2061S
Description of Registers
Register name (No. of bits)
VIDEO SEL (2): VIDEO switch selector and input signal selector
Valid when S SEL is either 0 or 3.
0 = TV input signal selected
1 = CVBS1 input signal selected
2 = CVBS2 input signal selected
3 = Mute
– 19 –
CXA2061S
AGING (1): White output aging mode ON/OFF switch (Set to 0 at power-on.)
0 = Aging mode OFF
1 = Aging mode ON
(When there is no input signal, a 60 IRE flat signal is outputted from the Y block.)
AXIS NTSC (1): Color detective axis (JAPAN axis/US axis) selector switch during NTSC mode
But valid only during the register AXIS PAL = 0
0 = Set to JAPAN axis
1 = Set to US axis
AXIS PAL (1): Forced PAL detective axis mode selector switch
0 = Forced axis off mode
1 = Forced PAL axis mode
YUV OUT (1): Switches the R2 IN/G2 IN/B2 IN input pins (Pins 32, 31 and 30) to Y, R-Y and B-Y signal output pins.
0 = R2 IN/G2 IN/B2 IN signal input mode
1 = Pin 30: B-Y output
Pin 31: R-Y output
Pin 32: Y output
(In this case, connect each pin to Vcc via a 10kΩ resistor.)
– 20 –
CXA2061S
ABL VTH (1): ABL control signal detective level (VTH) selector switch
0 = Vth: 3V
1 = Vth: 1V
RGB SEL (1): Disables YS1 switch selection and prohibits external signal input from RGB1.
0 = YS1 normal mode
1 = YS1 forced OFF mode
P ON (1): All blanking switch for RGB output signals with an AKB reference pulse (Set to 0 at power-on.)
0 = RGB outputs blanked (AKB reference pulse also not output)
1 = RGB outputs ON
R ON (1): Blanking switch for R output signal without an AKB reference pulse
0 = R output blanked
1 = R output ON
G ON (1): Blanking switch for G output signal without an AKB reference pulse
0 = G output blanked
1 = G output ON
B ON (1): Blanking switch for B output signal without an AKB reference pulse
0 = B output blanked
1 = B output ON
– 22 –
CXA2061S
VTIM SEL (2): Selector for signal output to VTIM pin (Pin 5)
0 = V retrace timing pulse
1 = Horizontal sync signal
2 = Vertical sync separation signal
3 = Not used
– 23 –
CXA2061S
AFC ANGLE (4): Vertical line slope compensation amount adjustment (Phase control according to HAFC VSAW)
0h = Top of picture delayed 500ns, bottom of picture advanced 500ns with respect to picture center.
7h = No compensation
Fh = Top of picture advanced 500ns, bottom of picture delayed 500ns with respect to picture center.
LEFT HBLK (4): HBLK width control for left side of picture when H BLK = 1
0h = +1.2µs HBLK width maximum
7h = Center
Fh = –1.2µs HBLK width minimum
RIGHT HBLK (4): HBLK width control for right side of picture when H BLK = 1
0h = +1.2µs HBLK width maximum
7h = Center
Fh = –1.2µs HBLK width minimum
H BLK (1): HBLK width control switch during 4:3 software normal mode on a 16:9 CRT
0 = Control OFF
1 = Control ON
V SIZE (6): Vertical picture size adjustment (VD output gain control)
0h = –15% (Minimum size)
1Fh = 0%
3Fh = +15% (Maximum size)
– 24 –
CXA2061S
V POSITION (6): Vertical picture position adjustment (VD output DC bias control)
0h = –0.1V (Picture position drops)
1Fh = 0V (Center potential: DC 3V)
3Fh = +0.1V (Picture position rises)
S CORRECTION (4): Vertical S distortion correction amount adjustment (VD secondary component gain control)
0h = Secondary component amplitude by adding sawtooth and other signals = 0mVp-p
Fh = Secondary component amplitude by adding sawtooth and other signals = 100mVp-p
V LINEARITY (4): Vertical linearity adjustment (VD secondary component gain control)
0h = 85% (Bottom/top of picture) Top of picture expanded.
1h = 100% (Bottom/top of picture)
3Fh = 115% (Bottom/top of picture) Top of picture compressed.
EHT COMP (4): Vertical picture size high voltage fluctuation compensation amount setting (VD output gain control)
0h = 0%
Fh = –5% (Compensation amount maximum)
H SIZE (6): Horizontal picture size adjustment (EW output DC bias control)
0h = –0.5V (Horizontal picture size decreases.)
1Fh = 0V (Center potential: DC 4V)
3Fh = +0.5V (Horizontal picture size increases.)
PIN AMP (6): Horizontal pin distortion compensation amount adjustment (V parabola wave gain control)
0h = 0.15Vp-p
(Horizontal size for top/bottom of picture increases: Compensation amount minimum.)
1Fh = 0.7Vp-p
3Fh = 1.3Vp-p
(Horizontal size for top/bottom of picture decreases: Compensation amount maximum.)
CORNER PIN (6): Horizontal pin distortion compensation amount adjustment for top/bottom of picture
(V parabola wave top/bottom gain control)
0h = –0.4V
(Horizontal size for top/bottom of picture decreases: Compensation amount maximum.)
3Fh = +0.4V
(Horizontal size for top/bottom of picture increases: Compensation amount minimum.)
TRAPEZIUM (4): Horizontal trapezoidal distortion compensation amount adjustment (Parabola wave phase control)
0h = 1.5ms advance
(Horizontal size for top of picture increases; horizontal size for bottom of picture decreases.)
Fh = –1.5ms delay
(Horizontal size for top of picture decreases; horizontal size for bottom of picture increases.)
– 25 –
CXA2061S
SCROLL (6): Vertical picture scroll control during zoom mode on a 16:9 CRT
0h = Scrolled toward top of screen by 32H and top of picture zoomed.
3Fh = Scrolled toward bottom of screen by 32H and bottom of picture zoomed.
EW DC (1): V parabola wave DC Ievel down mode during 4:3 deflection on a 16:9 CRT
0 = OFF
1 = ON
(DC Ievel down) In this case, the pin distortion must be readjusted by picture distortion
compensation when EW DC = 0.
– 26 –
CXA2061S
5. Status registers
– 27 –
CXA2061S
Description of Operation
1. Power-on sequence
The CXA2061S does not have an Internal power-on sequence. Therefore, all power-on sequence are controlled
by set microcomputer (I2C bus controller).
1) Power-on
The IC is reset and the RGB outputs are all blanked. H drive starts to oscillate, but oscillation is at the
maximum frequency (16kHz or more) and is not synchronized with the input signal in order to prevent FBT
(flyback transformer for generating high voltage) H squealing. Output of vertical signal V TIM start, but V dirve
is DC output. Bus registers whitch are set by power-on reset are as follows.
P ON = 0: RGB all blanked On
HD W = 0: Normal mode
V ON = 0: V output stopped mode
FH HIGH = 0: H oscillator maximum frequency mode
AGING = 0: All white output aging mode OFF
YUV OUT = 0
AKB operation start R ON, G ON, B ON are set to "0", P ON is set to "1" and a reference pulse is output
from ROUT, GOUT and BOUT. Then, the IC waits for the cathode to warm up and the
beam current to start flowing.
Video output R ON, G ON, B ON are set "1" and the video signal is output from ROUT, GOUT and
BOUT.
– 28 –
CXA2061S
The CXA2061S contains bus registers for deflection compensation whitch can be set for various wide mode.
Wide mode setting registers can be used separately from registers for normal picture distortion adjustment,
and once picture distortion adjustment has been performed in fill mode, wide mode setting can be made simply
by changing the corresponding register data.
– 30 –
CXA2061S
Example of various modes are listed below. These modes are described for NTSC using 480 Iines as the
essential number of display scanning lines. Wide mode setting register data is also listed, but adjustment values
may differ slightly due to IC variation.
The standard setting data differs for 16:9 CRTs and 4:3 CRTs.
(Standard values)
ASPECT 0h 2Fh
SCROLL 1Fh 1Fh
V ZOOM 1 0
UPPER VLIN 0h 0h
LOWER VLIN 0h 0h
V UNDER SCAN 0 0
H BLK 0 0
LEFT HBLK 7h 7h
RIGHT HBLK 7h 7h
– 31 –
CXA2061S
Mode settings
SETTING CRT SIZE SOFT SIZE MODE NAME I2C BUS REGISTER
1) -1 16:9 16:9 Full 16:9 CRT Standard value
1) -2 16:9 4:3 Wide Full 16:9 CRT Standard value
ASPECT = 0h: V size 75%
H BLK = 1: HBLK width adjustment ON
4:3 LEFT HBLK = Adjustment
2) 16:9 Normal
16:9 RIGHT HBLK = Adjustment
PIN AMP = Adjustment
EW DC =1
ASPECT = 2Fh: V size 100%
V ZOOM = 1: Zoom ON
(V size limited at 75%)
3) 16:9 4:3 Zoom
SCROLL = 0h: Zoom top of video image
= 1Fh: Zoom center of video image
= 3Fh: Zoom bottom of video image
ASPECT = 2Fh: V size 100%
UP VLIN = Adjustable: Slightly compresses
4:3 top of video image
(16:9 + LO VLIN = Adjustable: Signifficantly
4) 16:9 Subtitle-in
Subtitle compress bottom of
area) video image
V ZOOM = 1: V size limited at 75%
SCROLL = Adjustment
5) 16:9 4:3 Two Display V UNDER SCAN = 1: Compressed
ASPECT = Adjustment: V size 90%
UP VLIN = Adjustable compression of
6) 16:9 4:3 Wide Zoom
LO VLIN = Adjustable top and bottom of
(S CORR = Adjustable) video image
7) 4:3 4:3 4:3 Normal 4:3 CRT standard value
ASPECT = Adjustable
8) 4:3 16:9 V compression V UNDER SCAN = 1: V size 80%
(compressed to 75% total)
The amount of picture distortion compensation in the vertical direction position of the CRT does not change in
respnse to the above modes; as a result, the initial values of each picture distortion register can be used as is.
– 33 –
CXA2061S
3. VIDEO switch
The block diagram from the CXA2061S input to the VIDEO switch is as shown in the diagram below.
The input is selected and switched by the VIDEO SEL and S SEL settings as shown in the table below.
VIDEO SW
INPUT: 1.0Vp-p
+6dB
SELECTOR MON-OUT
TV/C2-IN 2Vp-p
VIDEO MIX
CVBS1/Y1 IN
SELECTOR
CVBS2/Y2 IN
C1-IN
SELECTOR TO-Y
INPUT: 2.0Vp-p
–6dB
COMB-Y IN
–6dB
COMB-C IN
SELECTOR TO-CHROMA
2 to 3 2 to 4
A B C D
I2C : VIDEO SEL I2C : S SEL
4. Signal processing
The CXA2061S is comprised of sync signal processing, H deflection signal processing, V deflection signal
processing, and Y/C/RGB signal processing blocks, all of which are controlled by the I2C bus.
4) Y signal processing
The Y/CVBS signal selected by the video switch is sent to the Y signal processing circuit.
The Y signal passes through the trap filter for eliminating the chroma signal, the delay line, the sharpness
control, the clamp and the black expansion circuits, and then is sent to the RGB signal processing circuit. The Y
signal processing circuit output can also be monitored at Pin 32 (R2 IN) by setting C DECOD register to 1. (In
this case, connect Pin 32 to Vcc via a 10kΩ Ioad resistor.)
The differential waveform of the Y signal, delay for ubout 270ns from Y input is output from Pin 15 as VM OUT.
Set register C TRAP OFF to 0 (trap filter ON) when the CVBS signal is selected, or to 1 (trap filter OFF) when
the Y/C separated Y signal is selected.
The f0 of the internal filter is automatically adjusted within the IC.
– 35 –
CXA2061S
5) C signal processing
The TV, CVBS or chroma signal (specified input level: burst level of 300mVp-p) selected by the video switch
passes through the ACC, chroma band-pass filter, chroma amplifier and demodulation circuits, becomes the R-Y
and B-Y signals, and input to the RGB signal processing circuit.
Like the Y output, the signals (R-Y, B-Y signals) output from this C signal processing circuit can be monitored
at Pins 30 (B2 IN) and 31 (G2 IN) by setting C DECOD register to 1. B-Y is outputted from Pin 30 (B2 IN) and
R-Y is output from Pin 31 (G2 IN). (In this case, connect Pins 30 and 31 to Vcc via a 10kΩ Ioad resister.)
If the burst level goes to –36dB or less with respect to the specified input level, the color killer operates.
In order to adjust the white and black balance, this IC has a drive control function which adjusts the gain
between the RGB outputs and a cut-off control function which adjusts the DC Ievel between the RGB outputs.
These functions can be adjusted with three independent channels by the I2C bus. An auto cut-off function
(AKB) which forms a loop between the IC and CRT and performs adjustment automatically has also been
added. This function can compensate for changes in the CRT with time.
1. R, G and B reference pulses for auto cut-off, shifted 1H each in the order mentioned, appear at the top of
the picture (actually, in the overscan portion). The reference pulse uses 1H in the V blanking interval, and
is output from each R, G and B output pin.
2. The RGB cathode current (lK) is input to Pin 21 (lK IN).
3. The cathode current input to Pin 21 (lK IN) is converted to a voltage within the IC. The reference pulse
interval of this voltage is compared with the reference voltage in the IC, and the current generated by the
resulting error voltage charges the capacitors in the IC. The charge is held during all intervals other than
the reference pulse interval.
4. The loop functions to change the DC Ievel of the R, G and B outputs in accordance with the capacitor
genenated voltage so that the voltage obtained by converting the current input to Pin 21 (IK IN) matches
the reference voltage in the IC.
The reference voltage in the IC can be adjusted independently for R, G and B through cut-off control by the I2C
bus. The cathode signal current flowing during the reference pulse interval is about 13µA when the cathode
current signal is set to cut-off control center. In addition, the cathode leak current flowing during blanking can
be supported up to 100µA. Large currents flowing during the video interval may damage the areas around IK
IN, so be sure to connect a Zener diode of about 4V to the IK IN pin.
– 36 –
CXA2061S
5. Timing chart
VIDEO
H SYNC
4.6µs 4.3µs
0.275V
6µs 3µs
2.9V
SCP
1µs
2V
(HDW = 0) 25µs
HD
19µs
(HDW = 1)
3µs
RGB BLK
15.5µs
12µs
(H POSI = 1Fh)
2µs
HP
(H POSI = 3Fh)
2µs
(H POSI = 0h)
– 37 –
CXA2061S
VIDEO
ODD
input
525 1 2 3 4 5 6 7 8 9 10 11 20 21
EVEN
input
262 263 264 265 266 267 268 269 270 271 272 273 282 283
50µs
VTIM
20µs
VD
EW
VIDEO
REF. PULSE
R OUT
50µs
ODD
G OUT
output
B OUT
VIDEO
REF. PULSE
R OUT
EVEN
G OUT
output
B OUT
– 38 –
CXA2061S
6. Notes on operation
Because the RGB signals and deflection signals output from the CXA2061S are DC direct connected, the
board pattern must be designed with consideration given to minimizing interference from around the power
supply and GND.
Do not separate the GND patterns around each pin; a solid earth is ideal. Locate the power supply side of the
by-pass capacitor which is inserted between the power supply and GND as near to the pin as possible. Also,
locate the crystal oscillator and IREF resistor as near this pin as possible, and do not wire signal lines near this
pin. Drive the Y, external Y/color difference and external RGB signals at sufficiently low impedance, as these
signals are clamped via the input capacitor.
Use a resistor (such as a metal film resistor) with an error of 1% or less for the IREF pin.
Read type (HC-49/U type) is used for X'tal oscillator.
Make sure that capture range, color response and others have no problems shown in Application Circuit.
– 39 –
CXA2061S
V-SIZE V POSITION
4.5 4.5
4 4
V [V]
V [V]
3.5 3.5
3 3
V SIZE = 0 V POSITION = 0
V SIZE = 1F V POSITION = 1F
V SIZE = 3F V POSITION = 3F
2.5 2.5
0 4 8 12 16 0 4 8 12 16
Time [ms] Time [ms]
S-CORRECTION V-LINEARITY
4.5 4.2
4 3.8
3.6
V [V]
V [V]
3.5 3.4
3.2
3 3
S-CORR = 0 V-LIN = 0
S-CORR = 7 V-LIN = 7
S-CORR = F 2.8 V-LIN = F
2.5 2.6
0 4 8 12 16 0 4 8 12 16
Time [ms] Time [ms]
ASPECT SCROLL
4.2 4.5
3.8 4
3.6
V [V]
V [V]
3.4 3.5
3.2
3 3
ASPECT = 0 SCROLL = 0
ASPECT = 1F SCROLL = 1F
2.8 ASPECT = 3F SCROLL = 3F
2.6 2.5
0 4 8 12 16 0 4 8 12 16
Time [ms] Time [ms]
– 40 –
CXA2061S
UP-VLIN LO-VLIN
4.2 4.2
4 4
3.8 3.8
3.6 3.6
V [V]
V [V]
3.4 3.4
3.2 3.2
3 3
UP-VLIN = 0 LO-VLIN = 0
UP-VLIN = 7 LO-VLIN = 7
2.8 UP-VLIN = F 2.8 LO-VLIN = F
2.6 2.6
0 4 8 12 16 0 4 8 12 16
Time [ms] Time [ms]
4
4
3.8
3.5
3.6
V [V]
V [V]
3.4
3
3.2
2.5 PIN AMP = 0 PIN TRAPEZIUM = 0
PIN AMP = 1F 3 PIN TRAPEZIUM = 7
PIN AMP = 3F PIN TRAPEZIUM = F
2 2.8
0 4 8 12 16 0 4 8 12 16
Time [ms] Time [ms]
CORNER PIN
4.5
3.5
V [V]
2.5
CORNER PIN = 0
CORNER PIN = 1F
CORNER PIN = 3F
2
0 2 4 6 8 10 12 14 16
Time [ms]
– 41 –
CXA2061S
H-SIZE H POSITION
6
4.5
5
4
4
Time [µs]
V [V]
SYNC center
3.5
3
t [µs]
18 PIN : HP
3 H-SIZE = 0 2
H-SIZE = 1F
H-SIZE = 3F
2.5 1
0 4 8 12 16 0 7 F 17 1F 27 2F 37 3F
Time [ms] DATA
0
5
–5
–10
0
Gain [dB]
Gain [dB]
–15
–5
–20
–25
–10
–30 TRAP OFF = 0 SHARPNESS = 0
TRAP OFF = 1 SHARPNESS = 7
SHARPNESS = F
–35 –15
0 1 2 3 4 5 6 –2 0 2 4 6 8 10 12 14
Furequency [MHz] Furequency [MHz]
PICTURE COLOR
10 10
5 0
0 –10
Gain [dB]
Gain [dB]
–5 –20
–10 –30
–15 –40
0 7 F 17 1F 27 2F 37 3F 0 7 F 17 1F 27 2F 37 3F
DATA DATA
– 42 –
CXA2061S
Potential difference between Rch reference pulse level and black level
BRIGHT DRIVE
0.2 3
0 2
–0.2 1
Gain [dB]
–0.4 0
[Vp-p]
–0.6 –1
–0.8 –2
–1 –3
–1.2 –4
0 7 F 17 1F 27 2F 37 3F 0 7 F 17 1F 27 2F 37 3F
DATA DATA
GAMMA
2.5
1.5
Rch output [V]
0.5
GAMMA = 3
0 GAMMA = 0
–0.5
0 10 20 30 40 50 60 70 80 90 100
YIN input amplitude [IRE]
– 43 –
CXA2061S
+ 0.1 5
0.0
+ 0.4
0.25 –
43.2 – 0.1
48 25
+ 0.3
13.0 – 0.1
0° to 15°
15.24
1 24
1.778
+ 0.4
4.6 – 0.1
0.5 MIN
3.0 MIN
0.5 ± 0.1
0.9 ± 0.15
PACKAGE STRUCTURE
PACKAGE MATERIAL EPOXY RESIN
SOLDER/PALLADIUM
SONY CODE SDIP-48P-02 LEAD TREATMENT PLATING
EIAJ CODE SDIP048-P-0600 LEAD MATERIAL COPPER / 42 ALLOY
– 44 –