+15 V

100n/63

to DSP Board
5CL1310 22n/63 C28 47n/63 +33V +33V
1k0 8
Guitar 2 3 MC33078P
3 +U
C3 220 22µ/40 W1.1
4 R1 C1 1 C6
Input INL

1,5n/63
1 1 Q3

1k5

100
+15 V R8
2 22µ/40 C59

R14

R15
J1 -U INR

C7
4 2
U2 AGND C7/C8 not assembled! BD238

1M0

10k
100

ZPD2,7
3 TIP132

R5

R7

D1
OUTL 150p

10k
R16 39
4

68p
R4
9 OUTR

C8
4k7 R20
5 C9
FCC5

220p
BC546B BC546B Q5

2k7
R2

ZPD2,7

R17

C10
POWERAMP_RIGHT BD679
100p 220n/63

D2
4k7
22µ/40

10k 5 R2
17
C4

R6
18

0,47/5W
C2 R10 C5

47µ/16

R52
22k
P10

C12

R25
R18

3k9
10k log ks
BF245 B Q1 Q2 Q4

47k
21

1k5
R3
W2 PT10h10k

R9
(Output R+)
AGND Q7 TR1
1 L2 R L

4k7

R27
AGND JP6

22µ/40
MC33078P 2

560
5

C57

R26
AGND
3 Fast.L 4,8

0,47/5W
47µ/40
to Send/Return

47/1W
7 AGND

1k5

R19

C11

R21

R29
4 4,7µ/40 bi.

4M7
6

R11
SEND_L

3k9

ZPD6,8
R28
5 4,7µ/40 bi.
C60

D3
U2 SEND_R

22n/63
6 Q6

+15 V
C58

C14
+15V 10
7

1k5
-15 V

R24
-15V
8
R23
RETURN_R 47n/63 TIP137
9
RETURN_L
C13 (Output COM)
10 -33V -33V
JP7
JP1 FCC10 POWERAMP_LEFT

4,7µ/63
30V~1
C17/C18 not assembled! Fast.L 6,3

C56
Fast.L 4,8 47n/63 +33V
+33V
SB2000mA

R51 D9
F3

C16

1,5n/63
100k 1N4007
+33V

1k5

100
C17

R32

R33
100k
Q10

4M7
R12

R50
R
1N5406 L7815
AC1 100/5Ws 1 100

+15 V
3 BD238 TIP132
IN OUT
GND

10k log ks
150p 39
D5 R49 R34 41

68p
2

C18
P10
U3
2,2µ Tan
C19 R38
1N5406

R31

4k7
220µ/25

100n/63

C29

220p
L BC546B BC546B Q12

2k7
4700µ/40
220n/250

C25

C26

C27

R35

C20
BD679
D6
C55

220n/63
GND
JP2

0,47/5W
AGND C15

47µ/16

R22
TR2

22k
C22

R43
R36

3k9
Fast.L 6,3 BF245 B Q8 Q9 PT10v10k Q11

47k

R13
2,2µ Tan
220µ/25

100n/63

1N5406 Q14 R L (Output L+)

4700µ/40

AC2
C32

C31

C30

C33

4k7

R45
JP8
D7

560

R44
U4
SB2000mA

1
1N5406 100/5W Fast.L 4,8
-15 V

0,47/5W
47µ/40

47/1W
75 -15V
F4

1k5
IN OUT

R37

C21

R39

R47
2 3
JP3 D8 R48
L7915

3k9

ZPD6,8
30V~2

R46
D4
Q13

22n/63
Fast.L 4,8 -33V

C24
10
JP4 B80C1500

1k5
SB630mA

R42
R41
10VAC1 10nk 10nk PolySwitch RXE 500mA
F1
Fast.L 4,8 VCC_STAGE 47n/63 TIP137
C49 C50 F2 -33V
C23 -33V

L78S05
1 3
DGND IN OUT +5V
GND
2 JP9
100n/63

100n/63

U1 U5
2200µ/25

330/1W
-15 V
C36

1
C35

C51

10nk 10nk
R30 2 Power LED Option Drawn by:
JP5 M. Bohlender
10VAC2 C48 C47 3
GND_STAGE Title: Date:
Fast.L 4,8 04-Dec-2001
JST3 ZenAmp
Drawing-Nr.:
POWERAMP, POWER SUPPLY, INPUT SECTOR HU0100-SP-R01-1C
DGND
Filename: Checked by: Page:
Michael Bohlender
HU0100-SP-R01-1C-041201.big 04-Dec-2001 1/3
 +3,3V
-15 V
+15 V
W1.2
+15V
1
-15V
2
GAIN
3

P1
R BASS
4
10k lin k

P2
MID

R
5

10k lin k
GAIN

P3
TREBLE

R
BASS
6

10k lin k

P4
PRESENCE
L

R
MID
7

10k lin k

P5
VOLUME
L

R
8

10k lin k
TREBLE

P6
REVERB

R
9

10k lin k

P7
PRESENCE
FX PARAMETER

R
10

10k lin k

P8
VOLUME
DELAY

R
11

10k lin k

P9
REVERB
DGND

R
12

10k lin k
+5V

FX PARAMETER
13

DELAY
GND_STAGE

L
14
VCC_STAGE

L
15
100nk

100nk

100nk

100nk

100nk

100nk

100nk

100nk

100nk
FCC15
C45

C44

C43

C42

C41

C39

C38

C37

C40

+5V
W3
To Chassis Ground

100nk
54 16
+5V W1.3
C34 15 TAPLED
1
100nk 14 TAPKEY
14 2
13 HDATA0
C52 3
100nk 12 HDATA1
32 4
11 HDATA2
C53 5
10 HDATA3
6
100nk 9 HDATA4
Chassis 7
8 HDATA5
C46 8
100nk 7 HDATA6
9
6 HDATA7
Fast.L 6,3 to (Rotary) Switches to DSP-Module
C54 10
100nk 5 CS0
JP10 11
4 CS1
C61 12
100nk 3 CS2
13
2 DGND
C62 14
1 +3,3V
15
FCC16 FCC15

Drawn by:
M. Bohlender

Title: Date:
04-Dec-2001
ZenAmp
Drawing-Nr.:
POWERAMP, POWER SUPPLY, INPUT SECTOR HU0100-SP-R01-1C

Filename: Checked by: Page:

Michael Bohlender
HU0100-SP-R01-1C-041201.big 04-Dec-2001 2/3
VCC_STAGE Jump VCC_STAGE ChassisJump Chassis
BR9 BR12

+5V Jump +5V DGND Jump DGND

BR10 BR17

43 Jump 43 AGND Jump Chassis

BR8 BR18

DGND Jump DGND

BR11

21 Jump 21
BR3

+15V Jump +15V

BR13

AGND Jump AGND

BR5

AGND Jump AGND

BR4

+15V Jump +15V

BR6

DGND Jump DGND

BR2

-15V Jump -15V

BR7

DGND Jump DGND

BR14

ENDSTUFEL Jump ENDSTUFEL

BR16

ENDSTUFER Jump ENDSTUFER

BR15

-15V Jump -15V

BR1

Hole3.2 Hole3.2
AGND Chassis
HO5 2
Hole3.2 Hole3.2
AGND Chassis
HO3 3

Drawn by:
M. Bohlender

Title: Date:
04-Dec-2001
ZenAmp
Drawing-Nr.:
POWERAMP, POWER SUPPLY, INPUT SECTOR HU0100-SP-R01-1C

Filename: Checked by: Page:

Michael Bohlender
HU0100-SP-R01-1C-041201.big 04-Dec-2001 3/3
 1 2 3 4 5 6 7 8

C5
R7 U1B
T J1 J3 T 5
+
+ C1 C2 TS TS +15V 7

2u2/35V-T

2u2/35V-T
W1 1 1K0
Send-L 1u/63V_RM5 6
-

VCC
from poweramp pcb

+
2 Return-L C3 OP275

8
R3 U1A
3 SS SS 3 R8 R9
+ R10
4 S S 1 47K 22K
1K0
5 Send-L RM122-02 RM122-02 1u/63V_RM5 2
- 22K
6 Send-R OP275

VEE
4
7 T J2 J4 T C6
+15V
D 8 TS TS R4 R5 D
-15V
9 Return-R Send-R 47K 22K -15V
10 Return-L Return-R 47pF/100V-K
R6
AWG24-10-2.54 SS SS
S S
22K
R1 R2 RM122-02 RM122-02
47R 47R C4

47pF/100V-K

R12

18K

+15V
+15V

VCC
C7 C8 U3A

4
R22

VCC
12 U2D C10 3 MC33079P(MOT)

4
+ U2A + R25
14 3 1 5 U3B
+ MC33079P(MOT) R17 1K2 + R28
22n/63V_RM5 22n/63V_RM5 13 1 12 U3D 2 7
- + - 1K5
R11 220n/63V_RM5 2 14 6

VEE
- 10K - 4K7

11
220K MC33079P(MOT) R15 13 JP1

VEE
- MC33079P(MOT) R27

11
8K2 MC33079P(MOT) R26
R30
2
-15V 10K 3
-15V R19 10K 220R
1
Rec Out L
C C13 C
22K 33n/63V_RM5
C15 U3C
C12 9 XLR/M-RX90602
3n3/63V_RM5 - R29
8
R18 10 4K7
R14
22pF/100V-K
+
11K MC33079P(MOT)
12K R20
C9 C11 R49
R21 R23 47R/1W C23
9K1 100n/63V-K
10n/63V_RM5 1n/63V_RM5 36K 39K
C14
R13 R16
3n3/63V_RM5
4K7 18K
-15V R24
11

C18 C20 82K

VEE

U4D
R31 R35
2 6 12 JP3
- - +
2K2 1 9K1 7 C21
14 FASTON-4.8-LG
10n/63V_RM5 3 1n/63V_RM5 5 R41 13
+ + 9 -
R32 R37 -
VCC

U4A U4B 8
4

2K2 3K9 39K MC33079P(MOT)

MC33079P(MOT) MC33079P(MOT) 3n3/63V_RM5 10
R42
+ Chassis
+15V U4C
R38 3K9
MC33079P(MOT)
C33 C34
220R 100n/63V-K
100n/63V-K

R34
B B
18K

+15V

VCC
C16 C17 U5A

4
U2C R43 MC33079P(MOT)
10 C19 3 U5B
+ U2B + R44
8 5 1K2 1 5
+ R39 U5D + R47
22n/63V_RM5 22n/63V_RM5 9 7 12 2 1K5 7
- + -
R33 220n/63V_RM5 6 14 6

VEE
- 10K - 4K7

11
220K MC33079P(MOT) R36 13 JP2
MC33079P(MOT) - R46
8K2 MC33079P(MOT) R45 2
MC33079P(MOT) R48
-15V 10K 3
BR2 R40 10K 220R
1
Rec Out R
0R0 C22
22K 33n/63V_RM5 U5C
C31
C28 9 XLR/M-RX90602
3n3/63V_RM5 - R64
8
R58 10 4K7
R53
22pF/100V-K
+
11K R66
R59 MC33079P(MOT) 47R/1W C32
C25 12K C27 100n/63V-K
9K1 R61 R62

10n/63V_RM5 1n/63V_RM5 36K 39K

C30
R52 R57

4K7 18K
3n3/63V_RM5 Title:
-15V R63 HU0100 - zenAmp Combo
FX-Loop / Redbox
11

A C24 C26 82K A

VEE

U6D
R50 R54 66606 St. Wendel / Germany
2 6 12
- - +
1 7 14
2K2 9K1 C29 Number: HU0100-SP-R03-2A Version: 2 Revision: A
10n/63V_RM5 3 1n/63V_RM5 5 R60 13
+ + 9 -
R51 R55 -
VCC

U6A U6B 8 Drawn by: M. Bohlender Date: 12.03.2002 Page: 1

4

2K2 3K9 39K MC33079P(MOT)

MC33079P(MOT) MC33079P(MOT) 3n3/63V_RM5 10
+
U6C Checked by: M. Bohlender Date: 13.03.2002 1 Pages
+15V
R56 R65 MC33079P(MOT)
Material: Surface:
220R 3K9
All rights reserved. No part of this schematic may be reproduced, stored in a retrieval system, transmitted in any form or by any means, electronic, mechanical, photocopying, recording or otherwise, without the prior permission of the author. Filename: HU0100-SP-R03-2A.sch

1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

Codec
Codec.sch
AINL
AINR
AOUTL
AOUTR CODECBUS
PeripheralsPowerAndJTAG
D PeripheralsPowerAndJTAG.sch D
CODECBUS

/HBR
/HBG
FPBUS
SPORTBUS1 SHARCRST
INTSBUS
Hostcontrollerunit
Hostcontrollerunit.sch
Analog-Input
CODECBUS INTSBUS
Analog-Input.sch
STAGEV1 VREFHI VREFHI LLSBUS
STAGEV2 APORT APORT
DSPandSDRAM
AVDD
DSPandSDRAM.sch
ASEL0
ASEL1 MEMCTRLBUS
Main-Connector
AVALOG_IN PER_BUS ADDRESSBUS ADRESSBUS
Main-Connector.sch
HOSTADRBUS DATABUS DATABUS
AINL HOSTDATABUS SHCS
AINR HOSTCTRLBUS
AOUTL
AOUTR
Testpoints
GNDSTAGE
Testpoints.sch
VSTAGE ANALOG_IN
TAPLED DATABUS
TAPKEY HOSTCTRLBUS HOSTCTRLBUS
C MEMCTRLBUS C
PER_BUS
SBUS

FlashMemAndResetCircuit
FlashMemAndResetCircuit.sch
HOSTCTRLBUS
HOSTDATABUS
HOSTADRBUS
HOSTRST

RS232-Transceiver
RS232-Transceiver.sch
LLSBUS
SBUS

B B

Title:
zenAmp
A 66606 St. Wendel / Germany A

Number: HU0100-SP-R05-1A Version: 1 Revision: A

Drawn by: M. Bohlender Date: 03.09.2001 Page: 1

Checked by: A. Peter Date: 04.09.2001 10 Pages

Material: Surface:

All rights reserved. No part of this schematic may be reproduced, stored in a retrieval system, transmitted in any form or by any means, electronic, mechanical, photocopying, recording or otherwise, without the prior permission of the author. Filename:HU0100-SP-R05-1A.sch

1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

C46 330n

Analog Filters and Voltage Converters R41

0..5V Stageboard outputs R43
0..3V DSP Module 6k2
10k
SVOLT1 L2 R40
STAGEV1 R42 Emergency Shutdown
2

100n
100uH 10k 1 6 R82
APORT0
3 10k 7
D 5 +5V 1k D
MC33078D
IC15 MC33078D

D1
Voltage Conversion IC15B

BAR43
C45

BAR43
Filter

D3
220R
R50
DGND DGND DGND Imax = 12mA Imax = 15mA

100n
3.0V VRH
C48 330n

ZMM003
330R
R51

D4
BAR43
R45

D7

BAR43
DGND

C49
R47

D2
6k2
10k
SVOLT2 L3 R44
STAGEV2 2 R46
DGND DGND
100n

100uH 10k 1 6 R83

APORT1
3 10k 7
5 1k
MC33078D
IC16 MC33078D +5V
IC16B
C47

+5V +5V
VREFHI

180R
R48
C DGND DGND DGND C

R110
R98

1k

1k
AVDD

100n
T1 3.2V AVDD

ZMM003,3
BC847

330R
R49
R111
ASEL0 T2
ASEL0

D8
BC847

C39
1k
R112
ASEL1
ASEL1
1k
DGND DGND
AVALOG_IN IC19
ANALOG[0..8] DGND DGND
L4
ANALOG0 12 13 APORT2
X0 X
+15V ANALOG1 14 X1 100uH
ANALOG2 15
X2
ANALOG3 11 X3
100n

100n

100n

100n

1 3
100n

100n

Y0 Y
5
Y1
2
10u/30V

10u/30V

Y2
+

4
C100

Y3
C99

6
C50

C51

C52

C53

INH
8

10 Analog Multiplexer
C62

C65

A
9 B
B IC15P IC16P B
MC33078D MC33078D
100n

100n

DGND DGND DGND DGND DGND 74HCT4052

10u/30V

10u/30V

L5
+

+
4

DGND ANALOG4 APORT3

C101

C102

100uH
C63

C64

L7
ANALOG5 APORT4
100uH
L8
ANALOG6 APORT5

-15V 100uH
L9
ANALOG7 APORT6
100uH
L10
ANALOG8 APORT7
100uH
+5VA

APORT
100n

100n

100n

100n

100n

APORT[0..7]
VDD
100n

100n
16

Title:
zenAmp
C57

C56

C55

C54

C58

IC19P
A A
C67

C68

66606 St. Wendel / Germany

8

VSS VEE
DGND DGND Number: HU0100-SP-R05-1A Version: 1 Revision: A
DGND DGND DGND
Drawn by: M. Bohlender Date: 03.09.2001 Page: 2
DGND
Checked by: A. Peter Date: 04.09.2001 10 Pages

Material: Surface:

All rights reserved. No part of this schematic may be reproduced, stored in a retrieval system, transmitted in any form or by any means, electronic, mechanical, photocopying, recording or otherwise, without the prior permission of the author. Filename:Analog-Input.sch
1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

LINE INPUT BUFFERS

R5 OUTPUT BUFFERS
R6

N$6
N$4
4k7 R23 N$38 R22 N$30 R19 N$33 IC4
N$50

N$7
4k7 MC33078D
C8 100p 3k3 12k 3k3
C7 100p 3 R18

N$2
R24 N$39 R21 R16 1 AOUTL
N$23 N$24

AOUTL
N$1
Left Channel Input 2
100R
D D

100p
R7

470p

470p

470p

470p
3k3 12k 3k3
AINL 6 R2 R3
AINL

12k R4
7 2

R20

R17
15k

15k
5 22R 4k7 1
22R AUDIO CODEC
MC33078D 3

C19

C18

C17

C16

C15
820p
+5VA IC2B MC33078D IC1
CS4224 N$25
IC2

N$11
R8
N$8 20 25
AINL+ AOUTL+
10k AGND AGND AGND AGND AGND

C9
N$6 19 26 N$49
AINL- AOUTL-
R12
R13

N$5
R32 R31 R28 N$44
N$16

4k7 N$15 N$47 N$45 N$43 IC4B

N$9
17 AINR+ AOUTR+ 24
4k7 MC33078D
C10 100p 3k3 12k 3k3
C11 100p 5 R27
N$3

7 AOUTR
R33 N$46 R30 N$40 R25 N$41

AOUTR
N$5 16 23 N$48 6

N$13
Right Channel Input AINR- AOUTR- 100R

100p
R14

470p

470p

470p

470p
3k3 12k 3k3
AINR 6 R9 R10
SCLK 5
AINR

12k 7 2 R11 SCLK

R29

R26
15k

15k
5 22R 4k7 1 LRCLK N$17
4 3
3 22R LRCLK XTI
MC33078D

C24

C23

C22

C21

C20
820p
C IC3B MC33078D SDIN 9 C
SDIN N$42
IC3

N$11
SDOUT 8
SDOUT

C12
100n

Q1 AGND AGND AGND AGND AGND

SCL 10 SCL/CCLK N$10
2 1 2
10u/16V

XTO
+

SDA 11
R15

SDA/CDIN
10k
C13

11.28MHz
AD0 12

40p

40p
C14

AD0/CS
NC@4 28
/RST 27 15
/RST NC@3
CODECBUS NC@2 14
SCLK,LRCLK,SDIN,SDOUT,SCL,SDA,AD0,/RST 18 I2C/SPI NC@1 1
Serial Interface Bus

C25

C26
AGND AGND AGND
Connects Codec with DSP

R35

1k
Mastermode
DGND DGND DGND

DGND DGND

+15V

Power supply for Op.Amps.

B B

100n

100n

100n

10u/30V

10u/30V

10u/30V
+

+
C91

C92

C93
8

8
Isolated analog and digital power

C31

C32

C33
supply for codec.
IC2P IC3P IC4P
+15V MC33078D MC33078D MC33078D

100n

100n

100n
+5VA +5V
IC18

10u/30V

10u/30V

10u/30V
7805

+
4

C98

C97

C96
1 3
VI VO AGND

C27

C28

C29
GND
2

+3,3V
3.3V digital I/O
21

13
6
100n

100n

100n

100n

-15V
VA VD VL
IC1P
10u/16V

10u/16V

10u/16V

Title:
+

ANALOG DIGITAL
CS4224 zenAmp
C5

C1

C3
C30

A AGND DGND A
C6

C2

C4

66606 St. Wendel / Germany

7
22

Number: HU0100-SP-R05-1A Version: 1 Revision: A

R34
Drawn by: M. Bohlender Date: 03.09.2001 Page: 3
0R Checked by: A. Peter Date: 04.09.2001 10 Pages

DGND Material: Surface:

AGND AGND AGND
All rights reserved. No part of this schematic may be reproduced, stored in a retrieval system, transmitted in any form or by any means, electronic, mechanical, photocopying, recording or otherwise, without the prior permission of the author. Filename:Codec.sch
1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

D D
+15V
+5V +3,3V

X1
AINL
1
AINL
MAINBAORD CONNECTOR AINR
2
AINR
AGND
3 AOUTL
4
AOUTL
AOUTR
5
AOUTR
+15V
6 -15V
7
ANALOG_IN
ANALOG0 ANALOG[0..8]
8 ANALOG1
9 ANALOG2
10 ANALOG3
11 ANALOG4
12 ANALOG5 X2
13 ANALOG6 STW10
14 ANALOG7 VSTAGE
15
SBUS 1
ANALOG8 MISO,MOSI,SSCLK,/SS,CONNECT MOSI
16 2
DGND SVOLT1 STAGEBOARD
17 3
+5V MISO CONNECTOR
18 4
GNDSTAGE SVOLT2
19
GNDSTAGE 5
VSTAGE SSCLK
20
VSTAGE 6
TAPLED HSENSE
21
TAPLED 7
TAPKEY /SS
22
TAPKEY PER_BUS 8
C PBUS0 PBUS[0..7] GNDSTAGE C
23 9
PBUS1 n/c
24 10
PBUS2
25 PBUS3
26 PBUS4
27 PBUS5 TEST SERIAL RS232
28 PBUS6 INTERFACE
29 PBUS7
30
HOSTCTRLBUS
CS0 CS[0..2],CSD,CSP[0..1],R/W,LSTRB,/R/W
31 CS1
32 CS2
33 DGND
34 +3,3V
35
PINHD-1X35
DGND
-15V
AGND

B B

LINEAR -LOW DROP- 3.3V REGULATOR

+5V +3,3V
IC12
LM3940IT-3.3
1 3
VI VO
GND
2
470n

33u/16V

+
C82
C59

DGND DGND DGND Title:

zenAmp
A 66606 St. Wendel / Germany A

Number: HU0100-SP-R05-1A Version: 1 Revision: A

Drawn by: m. Bohlender Date: 03.09.2001 Page: 4

Checked by: A. Peter Date: 04.09.2001 10 Pages

Material: Surface:

All rights reserved. No part of this schematic may be reproduced, stored in a retrieval system, transmitted in any form or by any means, electronic, mechanical, photocopying, recording or otherwise, without the prior permission of the author. Filename:Main-Connector.sch
1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

/RAS,/CAS,/SDWE,DQM,SDCLK0,SDCLK1,SDCKE,SDA10,/RD,/WR,/SW,/MS[0..3],/BMS
MEMCTRLBUS
ADDR[0..23]
R127 ADRESSBUS
ADDR8
DATA[0..31]
R126 10k DATABUS
ADDR9
10k R125
ADDR10 SDRAM
R124 10k SHARC data and address pins Low Word
ADDR11
10k R123 IC6 IC7
D ADDR12 ADSP21065L MT48LC4M16 D
R122 10k ADDR13 ADDR0 195 82 DATA0 SDCLK0 38
ADDR0 DATA0 CLK
ADDR1 194 83 DATA1
10k R121 ADDR1 DATA1
ADDR14 ADDR2 193 84 DATA2 ADDR0 23 2 DATA0
ADDR2 DATA2 A0 DQ0
ADDR3 190 86 DATA3 ADDR1 24 4 DATA1
R120 10k ADDR3 DATA3 A1 DQ1
ADDR15 ADDR4 189 87 DATA4 ADDR2 25 5 DATA2
ADDR4 DATA4 A2 DQ2
ADDR5 188 88 DATA5 ADDR3 26 7 DATA3
10k R119 ADDR5 DATA5 A3 DQ3
ADDR16 ADDR6 185 90 DATA6 ADDR4 29 8 DATA4
ADDR6 DATA6 A4 DQ4
ADDR7 184 91 DATA7 ADDR5 30 10 DATA5
R118 10k ADDR7 DATA7 A5 DQ5
ADDR17 ADDR8 183 92 DATA8 ADDR6 31 11 DATA6
ADDR8 DATA8 A6 DQ6
ADDR9 180 96 DATA9 ADDR7 32 13 DATA7
10k R117 ADDR9 DATA9 A7 DQ7
ADDR18 ADDR10 179 97 DATA10 ADDR8 33 42 DATA8
ADDR10 DATA10 A8 DQ8
ADDR11 178 98 DATA11 ADDR9 34 44 DATA9
R116 10k ADDR11 DATA11 A9 DQ9
ADDR19 ADDR12 175 100 DATA12 SDA10 22 45 DATA10
ADDR12 DATA12 A10 DQ10
ADDR13 174 101 DATA13 ADDR11 35 47 DATA11
10k R115 ADDR13 DATA13 A11 DQ11
ADDR20 ADDR14 173 104 DATA14 48 DATA12
ADDR14 DATA14 DQ12
ADDR15 171 107 DATA15 ADDR12 20 50 DATA13
R114 10k ADDR15 DATA15 BA0 DQ13
ADDR21 ADDR16 170 108 DATA16 ADDR13 21 51 DATA14
ADDR16 DATA16 BA1 DQ14
ADDR17 169 109 DATA17 53 DATA15
10k R113 ADDR17 DATA17 DQ15
ADDR22 ADDR18 166 111 DATA18 SDCKE 37
ADDR18 DATA18 CKE
ADDR19 165 112 DATA19 /MS0 19
R99 10k ADDR19 DATA19 /CS
ADDR23 ADDR20 164 113 DATA20 /SDWE 16
ADDR20 DATA20 /WE
ADDR21 162 116 DATA21 /CAS 17
10k ADDR21 DATA21 /CAS
ADDR22 161 117 DATA22 /RAS 18
ADDR22 DATA22 /RAS
DGND +3,3V +3,3V +3,3V +3,3V ADDR23 160 118 DATA23 DQM 15
ADDR23 DATA23 DQML
121 DATA24 39
DATA24 DQMH
122 DATA25
C DATA25 C
123 DATA26 +3,3V +3,3V +3,3V +3,3V +3,3V +3,3V +3,3V +3,3V
DATA26
126 DATA27
DATA27
127 DATA28
R73

R72

R71

R70

DATA28
4k7

4k7

4k7

4k7

128 DATA29 SDRAM

DATA29
132 DATA30 optional high word

R62

R63

R64

R65

R66

R67

R68

R69
DATA30

4k7

4k7

4k7

4k7

4k7

4k7

4k7

4k7
28 133 DATA31
/BR2 DATA31
27 /BR1 IC8
42 /RAS MT48LC4M16
/RAS
143 43 /CAS
ID0 /CAS
Single Processor ID 144 44 /SDWE SDCLK1 38
ID1 /SDWE CLK
46 DQM
DQM
37 SDCLK0 ADDR0 23 2 DATA16
SDCLK0 A0 DQ0
34 SDCLK1 ADDR1 24 4 DATA17
SDCLK1 A1 DQ1
DGND 47 SDCKE ADDR2 25 5 DATA18
SDCKE A2 DQ2
48 SDA10 ADDR3 26 7 DATA19
SDA10 A3 DQ3
ADDR4 29 8 DATA20
A4 DQ4
59 /RD ADDR5 30 10 DATA21
/RD A5 DQ5
n/c 69 58 /WR ADDR6 31 11 DATA22
ACK /WR A6 DQ6
64 /SW ADDR7 32 13 DATA23
/SW A7 DQ7
56 ADDR8 33 42 DATA24
/SBTS A8 DQ8
70 /MS0 ADDR9 34 44 DATA25
/MS0 A9 DQ9
/SHCS 55 71 /MS1 SDA10 22 45 DATA26
SHCS /CS /MS1 A10 DQ10
74 /MS2 ADDR11 35 47 DATA27
/MS2 A11 DQ11
75 /MS3 48 DATA28
/MS3 DQ12
152 153 /BMS ADDR12 20 50 DATA29
BSEL /BMS BA0 DQ13
ADDR13 21 51 DATA30
BA1 DQ14
Host booting enabled 53 DATA31
DQ15
B SDCKE 37 B
CKE
DGND /MS0 19 /CS
/SDWE 16 /WE
/CAS 17 /CAS
/RAS 18 /RAS
DQM 15 DQML
39 DQMH

+3,3V
43

49

14

27

43

49

14

27
3

1
100n

100n

100n

100n

VDD VDD VDD VDD

Title:
IC7P IC8P zenAmp
ISOLATED ISOLATED
MT48LC4M16 MT48LC4M16
A A
C35

C36

C37

C38

VSS VSS VSS VSS 66606 St. Wendel / Germany

Number: HU0100-SP-R05-1A Version: 1 Revision: A

6

6
12

41

12

41
46

52

28

54

46

52

28

54

Drawn by: M. Bohlender Date: 03.09.2001 Page: 5

Checked by: A. Peter Date: 04.09.2001 10 Pages

Material: Surface:
DGND
All rights reserved. No part of this schematic may be reproduced, stored in a retrieval system, transmitted in any form or by any means, electronic, mechanical, photocopying, recording or otherwise, without the prior permission of the author. Filename:DSPandSDRAM.sch
1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

D D
HOSTDATABUS
HDATA[0..15] +3,3V
FLASH
HOSTADRBUS
HADDR[0..19] IC22 Reset Controller
AM29LV800BB-12

HOSTCTRLBUS IC11 -- might be replaced during layout

100n
CS[0..2],CSD,CSP[0..1],R/W,LSTRB,/R/W HADDR1 25 29 HDATA0
A0 D0
HADDR2 24 31 HDATA1 3
A1 D1 VCC
HADDR3 23 33 HDATA2 1
A2 D2 RESET HOSTRST
HADDR4 22 35 HDATA3 2 /HOSTRST
A3 D3 GND
HADDR5 21 38 HDATA4

C44
A4 D4
HADDR6 20 40 HDATA5 MAX809S
A5 D5
HADDR7 19 42 HDATA6
A6 D6
HADDR8 18 44 HDATA7
A7 D7 TP124
HADDR9 8 30 HDATA8
A8 D8
HADDR10 7 32 HDATA9
A9 D9
HADDR11 6 34 HDATA10
A10 D10
HADDR12 5 36 HDATA11 DGND
A11 D11
HADDR13 4 39 HDATA12
A12 D12
HADDR14 3 41 HDATA13
A13 D13
HADDR15 2 43 HDATA14
A14 D14
+3,3V +3,3V HADDR16 1 45 HDATA15
A15 D15/A-1
HADDR17 48 A16
HADDR18 17 A17
HADDR19 16 A18
C C
R84

R81
10k

10k

26 15 n/c
/CE RY/BY
/R/W 28 /OE
R/W 11
/WE
12 /RESET
47
/BYTE
CS_FLSH

DEBUG
IC21 SRAM
CY62126VLL-70Z
CSP0
HADDR1 5 7 HDATA0
A0 D0
HADDR2 4 8 HDATA1 +3,3V
JP1 A1 D1
HADDR3 3 9 HDATA2
A2 D2
1 2 HADDR4 2 10 HDATA3
A3 D3
3 4 CSD HADDR5 1 13 HDATA4
A4 D4
HADDR6 44 14 HDATA5
A5 D5
HADDR7 43 15 HDATA6
PINHD-2X2 A6 D6
HADDR8 HDATA7

37

11

33
42 16

100n

100n

100n
A7 D7

5
HADDR9 27 29 HDATA8
A8 D8
HADDR10 26 30 HDATA9 IC22P
A9 D9
HADDR11 25 31 HDATA10 IC21P IC21T IC13P
A10 D10
HADDR12 24 32 HDATA11 AM29LV800BB-12 CY62126VLL-70Z CY62126VLL-70Z SN74AHC1G125DB
A11 D11
HADDR13 21 35 HDATA12

C81

C90

C69
A12 D12
HADDR14 20 36 HDATA13
A13 D13

3
12
27

46

34
HADDR15 19 37 HDATA14
A14 D14
B HADDR16 18 38 HDATA15 B
A15 D15
LSTRB
39 /BLE
HADDR0 40 /BHE
/R/W 41 /OE
R/W 17 In der Serie nicht bestückt! DGND
/WE
CS_SR 6 /CE

IC13
SN74AHC1G125DB

/SHCS 1 /OE
4 /WR
Y
R/W 2 A

Title:
zenAmp
A 66606 St. Wendel / Germany A

Number: HU0100-SP-R05-1A Version: 1 Revision: A

Drawn by: M. Bohlender Date: 03.09.2001 Page: 6

Checked by: A. Peter Date: 04.09.2001 10 Pages

Material: Surface:

All rights reserved. No part of this schematic may be reproduced, stored in a retrieval system, transmitted in any form or by any means, electronic, mechanical, photocopying, recording or otherwise, without the prior permission of the author. Filename:FlashMemAndResetCircuit.sch
1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

LLSBUS
LMOSI,LSCLK,L/SS,LMISO

+5V +3,3V IC9 HOSTADRBUS

MC68HC812 HADDR[0..19]
PINHD-1X5
5 SHSOUT 97 52 HADDR0 IC17B
PS0 RxD0 PB0 ADDR0
D 4 SHSIN 98 53 HADDR1 HADDR0 11 9 ADDR0 D
PS1 TxD0 PB1 ADDR1 A1 Y1
3 ORXD 99 54 HADDR2 HADDR1 13 7 ADDR1
PS2 RxD1 PB2 ADDR2 A2 Y2
2 OTXD 100 55 HADDR3 HADDR2 15 5 ADDR2
PS3 TxD1 PB3 ADDR3 A3 Y3
1 LMISO 101 56 HADDR4 HADDR3 17 3 ADDR3 ADDRESS
PS4 SDI/MISO PB4 ADDR4 A4 Y4
LMOSI 102 57 HADDR5 BUS
PS5 SDO/MOSI PB5 ADDR5
JP6 LSCLK 103 58 HADDR6 19 BRIDGE
PS6 SCK PB6 ADDR6 G
L/SS 104 59 HADDR7

SHSOUT
PS7 /SS PB7 ADDR7
DGND HADDR8

SHSIN
PA0 ADDR8 60
44 61 HADDR9 74LCX244
n/c XFC PA1 ADDR9
62 HADDR10
PA2 ADDR10 IC17A
/RESET 40 63 HADDR11
INTSBUS /RESET PA3 ADDR11
SHSIN,SHSOUT,SHSCLK,SHFS 64 HADDR12 HADDR4 2 18 ADDR4
PA4 ADDR12 A1 Y1
47 65 HADDR13 HADDR5 4 16 ADDR5
XTAL PA5 ADDR13 A2 Y2
66 HADDR14 HADDR6 6 14 ADDR6
PA6 ADDR14 A3 Y3

Q2
HADDR15 HADDR7 ADDR7
5MHz
46 67 8 12
1
EXTAL PA7 ADDR15 A4 Y4

R100
11 HADDR16
PG0 ADDR16

1M
BKGD 19 12 HADDR17 1
BKGD /TAGHI PG1 ADDR17 G
2

13 HADDR18
PG2 ADDR18 ADDRESSBUS
16 HADDR19 ADDR[0..23]
22p

22p

PG3 ADDR19 74LCX244

17 FPC7 +3,3V
PG4 ADDR20
PBUS0 75 18 FPC8
PH0 PG5 ADDR21 IC10
PBUS1 76 PH1
PBUS2 77 20 HDATA0 HDATA0 2 18 DATA0
PH2 PD0/KWD0 DATA0 A1 B1
PBUS3 78 21 HDATA1 HDATA1 3 17 DATA1
C86

C87

PH3 PD1/KWD1 DATA1 A2 B2

PBUS4 81 22 HDATA2 HDATA2 4 16 DATA2
PH4 PD2/KWD2 DATA2 A3 B3
PBUS5 82 23 HDATA3 HDATA3 5 15 DATA3 DATA
PH5 PD3/KWD3 DATA3 A4 B4
DGND DGND PBUS6 83 24 HDATA4 HDATA4 6 14 DATA4 BUS
PH6 PD4/KWD4 DATA4 A5 B5
PBUS[0..7] PBUS7 84 25 HDATA5 HDATA5 7 13 DATA5 BRIDGE
C PER_BUS PH7 PD5/KWD5 DATA5 A6 B6 C
26 HDATA6 HDATA6 8 12 DATA6
CODECBUS PD6/KWD6 DATA6 A7 B7
SCLK,LRCLK,SDIN,SDOUT,SCL,SDA,AD0,/RST SCL 105 27 HDATA7 HDATA7 9 11 DATA7
PT0 IOC0 PD7/KWD7 DATA7 A8 B8
SDA 106 28 HDATA8
PT1 IOC1 PC0 DATA8
AD0 107 29 HDATA9 1
PT2 IOC2 PC1 DATA9 DIR
/RST 108 30 HDATA10 19
PT3 IOC3 PC2 DATA10 G
ASEL0 109 31 HDATA11
PT4 IOC4 PC3 DATA11
ASEL1 110 32 HDATA12
PT5 IOC5 PC4 DATA12 74LVX245
SHARCRST 111 33 HDATA13
PT6 IOC6 PC5 DATA13
TAPLED 112 34 HDATA14
PT7 IOC7 PC6 DATA14 IC14
35 HDATA15 +3,3V
PC7 DATA15
/HBG 3 HDATA8 2 18 DATA8
PJ0 KWJ0 A1 B1
REDY 4 68 CS0 HDATA9 3 17 DATA9
PJ1 KWJ1 CS0 PF0 A2 B2
TAPKEY 5 69 CS1 HDATA10 4 16 DATA10
PJ2 KWJ2 CS1 PF1 A3 B3
SHSIN 6 70 CS2 HDATA11 5 15 DATA11
PJ3 KWJ3 CS2 PF2 A4 B4
SHSOUT 7 71 /SHCS HDATA12 6 14 DATA12
PJ4 KWJ4 CS3 PF3 A5 B5
SHFS 8 72 CSD HDATA13 7 13 DATA13
PJ5 KWJ5 CSD PF4 A6 B6
SHSCLK 9 73 CSP0 HDATA14 8 12 DATA14
PJ6 KWJ6 CSP0 PF5 A7 B7
SENSE 10 74 CSP1 HDATA15 9 11 DATA15
PJ7 KWJ7 CSP1 PF6 A8 B8
APORT R107
APORT[0..7] APORT0 87 36 1
PAD0 XIRQ PE0 DIR DATABUS
APORT1 88 37 REDY /SHCS 19 DATA[0..31]
PAD1 IRQ PE1 4k7 G
APORT2 89 38 R/W
PAD2 R/W PE2
APORT3 90 39 LSTRB
PAD3 LSTRB PE3 74LVX245
APORT4 91 48 /HBR
PAD4 ECLK PE4
APORT5 92 49
PAD5 MODA PE5
APORT6 93 50
PAD6 MODB PE6
APORT7 94 51 TEST
PAD7 ARST PE7
B HOSTDATABUS B
VRH 85 HDATA[0..15]
VREFHI VRH
86 HOSTCTRLBUS
100n

VRL
CS[0..2],CSD,CSP[0..1],R/W,LSTRB,/R/W

/R/W
R/W
+

BKGD PINHD-1X2
R101
C89

+3,3V DGND +3,3V +3,3V

10u

2
1 IC5 TEST
C88

4k7 TP132
NC7S04
PINHD-1X3 X4
JP3
3 1 2 BAR43 1

100n
R103 R106

5
DGND DGND /HOSTRST PINHD-1X2

R108
2 n/c 3 4 R102 2 4

1k
1 n/c 5 6 2
1k D5 100R
1 IC5P
4k7
JP5 /RESET NC7S04
PINHD-2X3

D6
JP4

C66

LTL907
+3,3V DEBUG INTERFACE DGND

3
DGND DGND
AVDD
AVDD

VCC VCC VCC

DGND DGND
42

79

14

43

95
2
100n

100n

100n

100n

100n

100n

100n

100n
20

20

20

VDD AVDD
IC9P
+

Title:
C106

C105

C104

C103

DIGITAL ANLG.
IC14P IC10P IC17P
MC68HC812 zenAmp
1u

1u

1u

1u

C85

C84

C61

C60

C43

C42

C41

C40
10

10

10

VSS AVSS
A 66606 St. Wendel / Germany A
1

41

15
80

45

96

GND GND GND Number: HU0100-SP-R05-1A Version: 1 Revision: A

Drawn by: M. Bohlender Date: 03.09.2001 Page: 7

Checked by: A. Peter Date: 04.09.2001 10 Pages

DGND DGND
Material: Surface:

All rights reserved. No part of this schematic may be reproduced, stored in a retrieval system, transmitted in any form or by any means, electronic, mechanical, photocopying, recording or otherwise, without the prior permission of the author. Filename:Hostcontrollerunit.sch
1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

+3,3V

R97

R96

R95

R94
10k

10k

10k

10k
/RST
SDA
SCL

AD0
D SPORTS D

CODECBUS INTSBUS
SCLK,LRCLK,SDIN,SDOUT,SCL,SDA,AD0,/RST SHSIN,SHSOUT,SHSCLK,SHFS
IC6S
ADSP21065L

+3,3V +3,3V +3,3V +3,3V +3,3V +3,3V SHSIN 5 11 SHSOUT

DR00 DT00
n/c 6 DR01 DT01 12 n/c

8 SHSCLK
TCLK0
RCLK0 4 n/c
7 SHFS

R80

R78

R77

R76

R75

R74
SHARCRST TFS0

4k7

4k7

4k7

4k7

4k7

4k7
Host SPORT RFS0 2
SHARC Masterclock +3,3V IC6I
33MHz for KS264 ADSP21065L R36 n/c 16 DR10 DT10 22 n/c R37
SDOUT 100R SDIN
30MHz for KS240 17 DR11 DT11 23
205 197 SCL CODEC control
/IRQ0 FLAG0 100R R38 100R
206 198 SDA optional by SHARC or Host 19 SCLK
/IRQ1 FLAG1 TCLK1
207 199 AD0 15
8

/IRQ2 FLAG2 RCLK1 R39 100R

201 /RST 18 LRCLK
100n

FLAG3 TFS1
VCC

SHARCRST 157 138 FPC4 Connections between SHARC and Host 13

HO-25B 30MHz /RESET FLAG4 RFS1
137 FPC5 for future purposes. CODEC SPORT
FLAG5
5 30 136 FPC6
OUT CLKIN FLAG6
134 FPC7
FLAG7
FPC8
GND

Y1 80
C80

FLAG8
79 FPC9
FLAG9 SPORTBUS1
78 FPC10 SCLK,LRCLK,SDIN,SDOUT,SCL,SDA,AD0,/RST
FLAG10
4

C +3,3V n/c 31 76 FPC11 C

/XTAL FLAG11
+3,3V
26 n/c
/PWMEVENT0
/PWMEVENT1 24 n/c

DGND
R128

330R
38 50 n/c

R85
/DMAR1 /DMAG1
10k

39 /DMAR2 /DMAG2 51 n/c

TCK,TMS,TDI,/TRST,TDO,/EMU
/HBR 40 52 /HBG
/HBR /HBR /HBG /HBG
65 63 REDY IC6J
/CPA REDY
BMSTR 53 ADSP21065L
+3,3V
TCK 151 TCK
TMS 149 146 TDO
TMS TDO
TDI 148 145 /EMU
TDI /EMU
/TRST 147 /TRST
R86

R87

R88

R89

R90

R91

R92

R93
10k

10k

10k

10k

10k

10k

10k

10k
FPC10

FPC11
FPC4

FPC5

FPC6

FPC7

FPC8

FPC9
FPBUS JTAG Interface
FPC[4..11]
JP2
1 2 /EMU
+3,3V nc 3 4 nc
B nc 5 6 TMS B
R61
7 8 TCK
9 10 /TRST
4k7 TDI
nc 11 12
13 14 TDO

PINHD-2X7

DGND

+3,3V
SHARC Power Supply
105
110
120
124
130
131
140
141
156
158
163
172
176
182
191
192
200
20
21
29
32
36
45
54
61
66
67
77
85
93
95

100n

100n

100n

100n
1
9

VDD
IC6P
ADSP21065L Title:
GND
zenAmp
C76

C77

C78

C79
3
10
14

41

81

106
114
119
125
129
135
139
150
154
155
159
167
168
177
181
186
187
196
25
33
35

49
57
60
62
68
72
73

89
94
99

204

A 66606 St. Wendel / Germany A

Number: HU0100-SP-R05-1A Version: 1 Revision: A

DGND Drawn by: M. Bohlender Date: 03.09.2001 Page: 8

Checked by: A. Peter Date: 04.09.2001 10 Pages

Material: Surface:

All rights reserved. No part of this schematic may be reproduced, stored in a retrieval system, transmitted in any form or by any means, electronic, mechanical, photocopying, recording or otherwise, without the prior permission of the author. Filename:PeripheralsPowerAndJTAG.sch
1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

D D

RS232 Transceiver
Stage- or Switchboard
Nullmodem Port

IC20
MAX3243CAI
C71 100n C73 100n
+3,3V +3,3V 28 27
C1+ V+
24 C1-
C72 100n C74 100n
1 C2+ V- 3

R59

R58
4k7

4k7
2 C2-
23 DGND
FON

R109
22
/FOFF

4k7
n/c 21 /INVALID
n/c 20 SBUS
R2BOUT
LLSBUS R52 47R MISO,MOSI,SSCLK,/SS,CONNECT
LMOSI,LSCLK,L/SS,LMISO LMOSI 19 4 MOSI
R1OUT R1IN
LSCLK 18 5
R2OUT R2IN R53 47R
C L/SS 17 6 SSCLK C
R3OUT R3IN
16 R4OUT R4IN 7 R54 47R
SENSE 15 8 HSENSE /SS
R5OUT R5IN
LMISO 14 9
T1IN T1OUT
13 T2IN T2OUT 10 R56 47R
12 11 n/c MISO
T3IN T3OUT

DGND

+3,3V

B B

26

100n
IC20P
MAX3243CAI

C75
25

DGND

Title:
zenAmp
A 66606 St. Wendel / Germany A

Number: HU0100-SP-R05-1A Version: 1 Revision: A

Drawn by: M. Bohlender Date: 03.09.2001 Page: 9

Checked by: A. Peter Date: 04.09.2001 10 Pages

Material: Surface:

All rights reserved. No part of this schematic may be reproduced, stored in a retrieval system, transmitted in any form or by any means, electronic, mechanical, photocopying, recording or otherwise, without the prior permission of the author. Filename:RS232-Transceiver.sch

1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

+15V
TESTPIN +5V +5VA +3,3V

/RAS DATA0
TP1 TP21 TP77

/CAS DATA1
TP2 TP22 TP78

/SDWE DATA2
TP3 TP23

DQM DATA3
TP4 TP24 TP80

D SDCLK0 DATA4 D
TP5 TP25 TP81

SDCLK1 DATA5
TP6 TP26

SDCKE DATA6
TP7 TP27 TP83

SDA10 DATA7
TP8 TP28

/RD DATA8
TP9 TP29 -15V
/WR DATA9
TP10 TP30

/SW DATA10
TP11 TP31

/MS0 DATA11
TP12 TP32

/MS1 DATA12
TP13 TP33

/MS2 DATA13
TP14 TP34

/MS3 DATA14
TP15 TP35

/BMS DATA15
TP16 TP36

/HBR DATA16
TP17 TP37

/HBG DATA17
TP18 TP38
C C
/SHCS DATA18 CS0
TP19 TP39 TP121

DATA19 CS1
TP40 TP122

DATA20 CS2
TP41 TP123

DATA21 /SHCS
TP42 TP125

DATA22 CSD
TP43 TP126

DATA23 CSP0
TP44 TP127

DATA24 CSP1
TP45 TP128

DATA25 R/W
TP46 TP129

DATA26 /R/W
TP47 TP130

DATA27 LSTRB
TP48 TP131

DATA28
TP49

DATA29
TP50

DATA30
TP51

DATA31
TP52
B B

HOSTCTRLBUS
CS[0..2],CSD,CSP[0..1],R/W,LSTRB,/R/W

DATABUS
DATA[0..31]
MEMCTRLBUS
/RAS,/CAS,/SDWE,DQM,SDCLK0,SDCLK1,SDCKE,SDA10,/RD,/WR,/SW,/MS[0..3],/BMS

Z1
DGND HALTEBOLZEN-LG

Title:
Kondensator nicht bestückt
zenAmp
C?
A 66606 St. Wendel / Germany A
100n

Number: HU0100-SP-R05-1A Version: 1 Revision: A

Drawn by: M. Bohlender Date: 03.09.2001 Page: 10

Checked by: A. Peter Date: 04.09.2001 10 Pages

Material: Surface:

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Schurter CE30.6100.151 Power Switch Voltage Selector Power Transformer

115V 23V/2,0A

230V
115V
100V
Length for Power Switch 100V
Cables = 200mm 5 white

red 6 0V
L A 3 7 brown
black 0V
8 red 115V

white 9 blue
23V/2,0A
N B 4
blue 10 10V/1,5A
black

0V
0V

Faston 4,8mm insulated Title: Drawing Number. :

ZenTrix Power Transformer 100/115/230V wiring
ZT_SO01_01
Faston 4,8mm insulated,
with 2nd 4,8mm pin Magdeburger Straße 8 Drawn: Revision: Checked: Date :
66606 St. Wendel
Germany Alexander Peter 1 11-May-01
Pin 1

D-SUB 9pol Buchse (DIN 41 652)

(z.B. Repro 09 66 118 7500)

Zugentlastungsbügel
(z.B. Repro 09 66 108 0000)

Farbader

Flachbandleitung AWG28/7, grau,

RM 1.27mm, 9 oder 10polig (wählbar),

150mm
rote Farbmarkierung für Pin 1

z.B.
Repro
09 18 009 700

bzw.

09 18 010 700

Harting SEK18 (DIN 41 651) 10pol

(z.B. Repro 09 18 510 7 803)

Pin 1

Bezeichnung: Zeichnungsnummer :
Zentrix Stagboardschnittstellenkabel, 9pol DSUB auf 10pol Pfostenfeld
ZT_SO02_01
Magdeburger Straße 8 Gezeichnet von: Revision: Geprüft: Datum :
66606 St. Wendel
Germany Alexander Peter 1 11. Mai 2001