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PRC G.811 EN 300 462-6-1 Measurement TIE (10-5τ + 0.29) µs for τ > 1000 s
a clock with respect to a Device 0.1
SONET/SDH Equipment Clock G.813 EN 300 462-5-1 • Measures over long periods Reference Signal
0.01
0.01 1 100 10000 1000000 1E+08
• Uses raw data to calculate G.813-Input Wander Tolerance (MTIE) for Option 1 10
Frequency synchronization Devices having the same number of bits over a period of time MTIE Measurement xi
Time
N − n+1 n +j −1
MTIE (S) = max max ( x i) − min (x i)
n +j −1
2 20 < τ ≤ 400 0.25
Phase synchronization Devices will shift exactly at the same time from one clock pulse to another x (t)
Observation Interval τ (s)
T1306500-95
1588v2 General Flow State IEEE-1588v2 Architectures Synchronous Ethernet SSM Format
Master Clock Slave Clock Data at Delay Request-Response Model (ITU-T G.8264/Y.1364)
Slave Clock
• The master and slave(s) exchange messages directly
IEEE Assigned OUI and SPS QL TLV Format
• The slave is the only one that calculates the clock offset:
- Mean Path Delay = [ [ T2-T1] + [ T4-T3] ] / 2
Annou Organizational Unique Identifier 0x0019A7 8 bits Type: 0x01
nce - Clock Offset = [T2-T1] – Mean Path Delay
Slow Protocol Subtype 0x0A 16 bits Length: 0x04
t1
Sync
Leap second offset Delay_req
4 bits 0 (unused)
(t1)
Master Slave Sync, Follow-up, 4 bits SSM code
Delay_resp
Follow t2 T2 (and T1 T1, tagged
Sync M
Switch/Router Laser
- up (t1 for 1-step) ESMC PDU Format SSM Message for SyncE
) Follow-up T2, tagged / T1, received
(T1), received
Delay_
respo
Peer-to-Peer Model 16-18 3 octets ITU-OUI = 00-19-A7 (hex)
nse (t4 19-20 2 octets ITU subtype
) • Each node in the network measures the port-to-port propagation time (i.e., the link delay
between two communicating ports that support the peer delay mechanism) 21 4 bits Version
T1, T2, T3, T4
1 bit Event flag
• The sum of all path delays is added to the sync message
3 bits Reserved
Time
Time
OffsetDELAY_REQ = T4 - T3
T2p tagged
Pdelay_req T1p tagged
P1
Pdelay_resp T2s
Synchronous Ethernet (SyncE)
Assuming path symmetry, therefore T3p tagged PDelay_resp
Pdelay_req
S
One-Way Path Delay = RTD
Applies to
each leg
Pdelay_resp SyncE is the scheme that transports frequency at the Ethernet physical layer
T4p tagged
P2
PDelay_resp_ (T3p-T2p) received
(T3p) received
Slave Clock Error = (T2 - T1) - RTD follow-up
Clock offset = [T2s-T1m] - ∑ (link delays)
in the sync message MAC PHY PHY MAC
Notes
1. One-way delay cannot be calculated exactly, but there is a bounded error. Ethernet
2. The protocol transfers TAI (Atomic Time). UTC time is TAI + leap second offset from the announce message. Bits
Number of Bytes Offset
7 6 5 4 3 2 1 0 ±100 ppm ±100 ppm
flagField 2 6
PTP is a synchronization scheme that provides high clock accuracy in a packet correctionField 8 8 EEC
SyncE SyncE
EEC
processor processor
network by continuously exchanging packets with appropriate timestamps.
reserved 4 16 SyncE
A grandmaster clock is a very precise clock source that generates timestamp sourcePortIdentity 10 20 MAC PHY PHY MAC
announcements and responds to timestamp requests from boundary clocks and sequenceID 2 30 ±4.6 ppm ±4.6 ppm
slave clocks. Clock card Line card Line card Clock card
controlField 1 32
NE NE
Slave/client clocks are clocks that receive synchronization from the grandmaster clock. logMessageInterval 1 33
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