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Network Synchronization Technologies Poster

Synchronization Standards MTIE Performance Masks


1000

100

ITU-T ETSI TIE Measurement Signal Under Test MTIE


MTIE ( µs)
10

(0.275 x 10 τ + 0.025) µs for 0.1s < τ ≤ 1000 s


-3
• Measures the phase of 1

PRC G.811 EN 300 462-6-1 Measurement TIE (10-5τ + 0.29) µs for τ > 1000 s
a clock with respect to a Device 0.1

SSU/BITS G.812 EN 300 462-4-1 reference clock

SONET/SDH Equipment Clock G.813 EN 300 462-5-1 • Measures over long periods Reference Signal
0.01
0.01 1 100 10000 1000000 1E+08

(hours or days) Observation Period (s)

• Uses raw data to calculate G.813-Input Wander Tolerance (MTIE) for Option 1 10

MTIE and TDEV 5.0

Types of Synchronization MTIE Limit (µs) Observation Interval τ (s) 2.0

0.25 0.1 < τ ≤ 2.5 MTIE (µs) 1.0


Time synchronization Devices synchronized to the same time information
0.1 τ 2.5 < τ ≤ 20

Frequency synchronization Devices having the same number of bits over a period of time MTIE Measurement xi
Time
N − n+1 n +j −1
MTIE (S) = max max ( x i) − min (x i)
n +j −1
2 20 < τ ≤ 400 0.25

Delay j= 1 i=j i =j 0.1


0.005 τ 400 < τ ≤ 1000
• Measures the maximum T − (N −1) τo
0.1 1.0 2.5 10 20 100 400 1000

Phase synchronization Devices will shift exactly at the same time from one clock pulse to another x (t)
Observation Interval τ (s)
T1306500-95

phase deviation over a


measurement window 100
S − (n −1) τ0 G.812-Input Wander Tolerance (MTIE) for Type I
• Predicts clock frequency Node Clock
Acronyms stability over time MTIE Limit (µs) Observation Interval τ (s) 10
xppj Type I
BITS Building integrated timing supply GPS Global positioning system SEC SONET/SDH equipment clock 0.75 0.1 < τ ≤ 7.5
5
MTIE ( µs) 2
EEC Ethernet equipment clock MTIE Maximum time interval error SSU Synchronization supply unit t − i τo (log scale)
0.1 τ 7.5 < τ ≤ 20 1
0.75 Types II, III
ESMC Ethernet synchronization PRC Primary reference clock SyncE Synchronous Ethernet 0 1 2 3 i
2 20 < τ ≤ 400
messaging channel PRS Primary reference source TDEV Time deviation
0.3
j j + n −1 N 0.005 τ 400 < τ ≤ 1000 0.1
PTP Precise time protocol TIE Time interval error 10 m 0.1 1 10 100 1K 10
5 1000 < τ ≤ 10 000 50 m 7,5 20 280
400
Observation Interval τ (s) T1313260-98/d03
(log scale)

1588v2 General Flow State IEEE-1588v2 Architectures Synchronous Ethernet SSM Format
Master Clock Slave Clock Data at Delay Request-Response Model (ITU-T G.8264/Y.1364)
Slave Clock
• The master and slave(s) exchange messages directly
IEEE Assigned OUI and SPS QL TLV Format
• The slave is the only one that calculates the clock offset:
- Mean Path Delay = [ [ T2-T1] + [ T4-T3] ] / 2
Annou Organizational Unique Identifier 0x0019A7 8 bits Type: 0x01
nce - Clock Offset = [T2-T1] – Mean Path Delay
Slow Protocol Subtype 0x0A 16 bits Length: 0x04
t1
Sync
Leap second offset Delay_req
4 bits 0 (unused)
(t1)
Master Slave Sync, Follow-up, 4 bits SSM code
Delay_resp
Follow t2 T2 (and T1 T1, tagged
Sync M
Switch/Router Laser

- up (t1 for 1-step) ESMC PDU Format SSM Message for SyncE
) Follow-up T2, tagged / T1, received
(T1), received

T1, T2 Delay_req Octet SSM


T3, tagged Size Field Clock Message Code
T4, tagged
Number
1-6 6 octets Destination address = EEC1 QL-EEC1 1011
t3 T1, T2, T3 Delay_resp 01-80-C2-00-00-02 (hex)
st EEC2 QL-EEC2 1010
reque
T4, received

Delay_ 7-12 6 octets Source address


t4 S 13-14 2 octets Slow protocol Ethertype = 88-09 (hex)
15 1 octet Slow protocol subtype = 0A (hex)

Delay_
respo
Peer-to-Peer Model 16-18 3 octets ITU-OUI = 00-19-A7 (hex)
nse (t4 19-20 2 octets ITU subtype
) • Each node in the network measures the port-to-port propagation time (i.e., the link delay
between two communicating ports that support the peer delay mechanism) 21 4 bits Version
T1, T2, T3, T4
1 bit Event flag
• The sum of all path delays is added to the sync message
3 bits Reserved
Time

Time

Port 1 Port 2 22-24 3 octets Reserved


T1p tagged
Pdelay_req 25-1532 36-1490 Data and padding
The process is repeated up to 128 times per second. T2p tagged octets
Announce rate is lower than sync rate. PDelay_resp
T1m Last 4 4 octets FCS
T3p tagged Sync: T1m, ∑(link delays)
Pdelay_req
T4p tagged
Round-Trip Delay (T3p-T2p) Received
PDelay_resp_
M
(T3p) Received Pdelay_resp
RTD = (T2 – T1) + (T4 – T3) follow-up
P1
Pdelay_req

Offset (slave clock error and one-way path delay)


Pdelay_resp P2 Pdelay_req
OffsetSYNC = T2 - T1 Port 1 Port 2

OffsetDELAY_REQ = T4 - T3
T2p tagged
Pdelay_req T1p tagged

P1
Pdelay_resp T2s
Synchronous Ethernet (SyncE)
Assuming path symmetry, therefore T3p tagged PDelay_resp
Pdelay_req
S
One-Way Path Delay = RTD
Applies to
each leg
Pdelay_resp SyncE is the scheme that transports frequency at the Ethernet physical layer
T4p tagged
P2
PDelay_resp_ (T3p-T2p) received
(T3p) received
Slave Clock Error = (T2 - T1) - RTD follow-up
Clock offset = [T2s-T1m] - ∑ (link delays)
in the sync message MAC PHY PHY MAC
Notes
1. One-way delay cannot be calculated exactly, but there is a bounded error. Ethernet

2. The protocol transfers TAI (Atomic Time). UTC time is TAI + leap second offset from the announce message. Bits
Number of Bytes Offset
7 6 5 4 3 2 1 0 ±100 ppm ±100 ppm

transportSpecific messageType 1 0 Line card Line card


NE NE
reserved versionPTP 1 1
messageLength 2 2
SSU SSU
domainNumber 1 4
PTP/IEEE 1588v2 reserved 1 5
Direction of clock path

flagField 2 6
PTP is a synchronization scheme that provides high clock accuracy in a packet correctionField 8 8 EEC
SyncE SyncE
EEC
processor processor
network by continuously exchanging packets with appropriate timestamps.
reserved 4 16 SyncE
A grandmaster clock is a very precise clock source that generates timestamp sourcePortIdentity 10 20 MAC PHY PHY MAC

announcements and responds to timestamp requests from boundary clocks and sequenceID 2 30 ±4.6 ppm ±4.6 ppm
slave clocks. Clock card Line card Line card Clock card
controlField 1 32
NE NE
Slave/client clocks are clocks that receive synchronization from the grandmaster clock. logMessageInterval 1 33
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TECHNOLOGIES POSTER
NETWORK SYNCHRONIZATION

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