DEGREE PROJECT, IN ELECTRONIC AND COMPUTER SYSTEMS (IL120X) ,

FIRST LEVEL
STOCKHOLM, SWEDEN 2015

System Level Modeling and

Verification of All-digital Phase-locked
Loop

CHI ZHANG

KTH ROYAL INSTITUTE OF TECHNOLOGY

INFORMATION AND COMMUNICATION TECHNOLOGY

System Level Modeling and Verification of
All-Digital Phase-locked Loop

Chi Zhang

May 2015

BACHELOR THESIS

School of Information and Communication Technology

Royal Institute of Technology ( KTH )

 ii

Abstract

In wireless communication systems, a local oscillator (LO) aims at demodulating radio-frequency

signals into baseband signals. The performance of these signals determines the quality of com-
munications which is highly affected by the phase accuracy of local oscillators. Therefore, eval-
uating jitter/phase noise should be an essential part when designing wireless communication
systems. Typically, LO is achieved by traditional analog PLL. These prototypes have several
drawbacks including low integration, narrow bandwidth and high phase noise. With the devel-
opment of digital techniques, approaches towards an All-digital Phase-Locked Loop have been
forwarded against the traditional analogy type.

The thesis mainly deals with the modeling and verification of an All-digital Phase-Locked Loop
concerning its architecture, functionality and phase noise modeling and analysis. It starts with
a comparison of current frequency synthesizers including direct analog/digital synthesis and
indirect synthesis using PLL/ADPLL. The advantage and analogy of ADPLL versus traditional
PLL in radio-frequency applications has been discussed. In order to gain overall understanding
of ADPLL, a behavioral theory in both time and phase domain has been conducted in detail.
Analysis shows that the restrictive factors of proposed ADPLL lie in TDC and DCO phase noise.
It is also proved that the bandwidth and settling time of ADPLL is determined by proportional
and integrating parameter of loop filter.

Upon the completion of ADPLL theory analysis, a model based on simulink has been put for-
ward. The phase noise level of TDC is specified and mode switch is implemented in order to im-
prove the speed of ADPLL. The reason for choosing 2nd-order MASH-1-1 type ߢ modulator is
briefly discussed. The phase noise of DCO is generated in time-domain using filtered Gaussian
distribution and the free-running DCO achieves -20dB/dec spectrum from 10Hz to 500kHz.

The results verified the feasibility of proposed ADPLL by achieving -50dBc/Hz in-band noise.
Other results including how fractional precision, SDM clock and precision contributed to ADPLL
phase noise has been presented. A tradeoff between phase noise shaping quality and settling
time was evaluated. Ultimately, global parameters setup for the fulfillment of best performance
is demonstrated.
 iii

Acknowledgment

I would like to thank my examiner professor Lirong Zheng and my supervisor Jia Mao for their
great willingness and kind help during my research and implementation in System Level Model-
ing and Verification of All-digital Phase-locked Loop. Additionally, I would like to thank senior
researcher Zhuo Zou and Lebo Wang for their great help.

May 2015

(Chi Zhang)
Contents

Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii
Acknowledgment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii

1 Introduction 1
1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3 Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.4 Hypothesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.5 Structure of the Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Frequency Synthesizer review 4

2.1 Direct Analogy Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2 Direct Digital Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.3 Traditional Indirect Synthesis using Phase-locked Loop . . . . . . . . . . . . . . . . 5
2.4 Towards an ALL-Digital PLL Approach . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3 ADPLL Bahavioral Theory 7

3.1 System Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2 Time-domain analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2.1 Retimed Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2.2 Time-to-digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2.3 Phase detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2.4 Digital Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2.5 Sigma-Delta modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2.6 DCO normalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2.7 Digital Controlled Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

iv
CONTENTS v

3.3 Phase-domain analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.3.1 Phase-domain model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3.2 Phase domain analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4 Modeling and Verification 23

4.1 General Idea . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.2 Sub-block implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.2.1 Time-to-digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.2.2 Phase detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.2.3 Mode switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.2.4 Sigma-Delta modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.2.5 Digital Controlled Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5 Results 32
5.1 In-band phase noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.2 Out-band phase noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.3 Settling time and Loop bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.4 Tradeoff evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.5 Block parameters setup for fulfillment of best performance . . . . . . . . . . . . . . 41

6 Discussion and future work 42

Bibliography 43
List of Figures

2.1 DDS block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.2 PLL block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3.1 ADPLL System Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.2 Retimed Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.3 Retimed Clock demo with N = 1.75 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.4 Fractional Phase error estimation[1] . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.5 Time-to-digital converter[1] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.6 Phase detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.7 Digital Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.8 First-order sigma-delta modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.9 LC tank model[1] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.10 Practical DCO phase noise spectrum[2] . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.11 Phase domain model diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.12 Bode plot of HT DC , HDCO and Hr e f , K p = 2°5 , K i = 2°11 , f r e f = 40k H z . . . . . . . . 18
3.13 Step Response of different damping factor . . . . . . . . . . . . . . . . . . . . . . . . 20
3.14 Bode diagram approximation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.15 Bode plot of Hol with ≥ = 1 and f r e f =40kHz . . . . . . . . . . . . . . . . . . . . . . . . 21

4.1 Alternative phase detector architecture[1] . . . . . . . . . . . . . . . . . . . . . . . . 25

4.2 Procedure of DCO mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.3 2nd-order MASH-1-1 ߢ modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.4 First-order ߢ modulation characteristic . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.5 Free-running DCO spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

vi
LIST OF FIGURES vii

5.1 In-band phase noise spectrum given different inverter delays, FCW=81.25, f r e f =
40kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.2 In-band phase noise spectrum at different fractional precision FCW=81.25, f r e f =
40kHz, t i nv = 30ns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.3 Out-band phase noise, FCW=81.25, f r e f = 40kHz, t i nv = 30ns . . . . . . . . . . . . . 34
5.4 Effect of phase noise spectrum with SDM on and off, FCW=81.25, K p = 2°5 , t i nv =
30ns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.5 Effect of phase noise spectrum with different SDM clock, FCW=81.25, K p = 2°5 ,
t i nv = 30ns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.6 Effect of phase noise spectrum with different SDM input word length, FCW=81.25,
K p = 2°5 , t i nv = 30ns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.7 Phase noise spectrum of different K p , FCW=81.25, f r e f = 40kHz, t i nv = 30ns, ≥ =
0.707 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.8 OTW in tracking mode, FCW=81.25, f r e f = 40kHz, t i nv = 30ns, ≥ = 0.707 . . . . . . 38
5.9 OTW in tracking mode, FCW=81.25, f r e f = 40kHz, t i nv = 30ns, ≥ = 1 . . . . . . . . . 39
5.10 OTW in tracking mode, FCW=81.25, f r e f = 40kHz, t i nv = 30ns, ≥ = 2 . . . . . . . . . 39
LIST OF FIGURES viii

Terminology

Abbreviation Explanation
ADPLL All-digital Phased-locked Loop
PLL Phase-Locked Loop
DCO Digital Controlled Oscillator
CDMA Code Division Multiple Access
FCW Frequency Command Word
NTW Normalized Tuning Word
OTW Oscillator Tuning Word
PVT Process Voltage Temperature
ACQ Acquisition
TRK Tracking
SDM Sigma-Delta Modulation/Modulator
TDC Time-to-digital Converter
CKR Retimed Clock
CKV Variable Clock
RF Radio Frequency
LO Local Oscillator
LF Loop Filter
Chapter 1

Introduction

1.1 Background

The earliest PLL technique, abbreviation for Phase Locked Loop, dated back to 1923 by Edward
Appleton when he found a way to correct the signal applied to the oscillator automatically.[3][4]
Nowadays, PLL has various applications as demodulation, bit and symbol synchronization,
clock recovery, deskewing, clock generation, spread spectrum, etc. Since the basic purpose of
PLL is to synchronize circuits, the accuracy of PLL has to reach high level which is dominated by
phase noise. PLL is classified into several types as shown in table 1.1.

PLL type Phase detector Loop filter Voltage-controlled oscillator

Analog PLL (APLL) Analog Analog Analog
Digital PLL (DPLL) Digital Analog Analog
All-digital PLL Digital Digital Digital

Table 1.1: Category of PLL[5]

The analog implementation has several drawbacks which mainly focus on the low integration,
narrow bandwidth and high phase noise. On the contrary, the digital circuits provide stable per-
formance and large integration with today’s CMOS technology, such as Synopsys 32/28nm[6]
and TSMC 20nm[7]. Thus a highly integrated System-on-chip all-digital Phase-locked Loop be-
comes possible to realize.

1
CHAPTER 1. INTRODUCTION 2

1.2 Objectives

This bachelor thesis was conducted in Electronic and Computer System Lab in KTH, during
which a new version of transceiver was under research and implementation. The objective of
this thesis is to model and verify the functionality and performance of an ADPLL embedded
in this transceiver. In this model, we evaluate its phase noise characteristics to provide best
performance in practice.

1.3 Method

The simulation of ADPLL has been carried out before using a event-driven simulation technique
in master’s thesis Modeling and Characterization of All-Digital Phase-Locked Loop[2] by Fredrik
Andersson and Alfred Johnson. In this thesis, a brand new method is introduced based on the
platform simulink, which provides runtime phase noise analysis.

In order to get an overall understanding of the behavioral model of ADPLL, a corresponding

phase domain model has been proposed.

The phase noise bandwidth is too narrow compared to the oscillator running frequency so that
a scaling method (see Chapter 4 for detailed discussion) is included in order to lower the sample
frequency of the simulation system.

Based on the model and simulation outcome, phase noise performance will be carefully inves-
tigated and system specifications will be put forward.

1.4 Hypothesis

• We have assumed that the frequency scaling ADPLL has the same performance with the
original one. However, this is not always true in practice.

• In order to simplify the model, we have ignored 1/ f 3 flicker noise and 1/ f electronic noise.
Thus in free-running DCO phase noise spectrum, a 20dB/dec slope and a 0dB/dec flat will
be presented.
CHAPTER 1. INTRODUCTION 3

• In practice, the inaccuracy of LC tank capacitor will not be a limiting factor so we didn’t
include it. But the inaccuracy of inverter delays will incur extensive phase noise deteriora-
tion. Besides the stationarity of inverter chains will also cause spurious in ADPLL output
spectrum. In this model, we ignored both of them and get the fractional phase error by di-
rectly measuring the simulation time between positive edges and then add quantization
errors which is defined by specific inverter delay.

1.5 Structure of the Thesis

• In Chapter 2, a review of different frequency synthesizers will be presented and an all-

digital approach is to be put forward.

• In Chapter 3, basic theory of each sub-blocks in ADPLL is carefully evaluated and a phase
domain model will be raised in order to grasp high-level understanding of ADPLL system.

• In Chapter 4, proposed ADPLL specifications and how each sub-blocks are implemented
in simulink will be presented. Also theoretical phase noise level from TDC will also be
illustrated.

• In Chapter 5, a bunch of results concerning in-band noise, out-band noise, settling time
and loop bandwidth will be elaborately discussed.

• In Chapter 6, some discussion and future work is included.

Chapter 2

Frequency Synthesizer review

2.1 Direct Analogy Synthesis

The direct analogy synthesis[8] technique is also referred to as mix-filter-divide. Literally it uti-
lizes mixer, filter and divider to produces new frequency. One of its most significant drawback
lies in the excessive phase noise which the analog devices produces. In order to get rid of that,
stages of filter is required which adds to large cost. With highly integrated circuits prevailing,
this method is substituted by other forms of synthesizer.

2.2 Direct Digital Synthesis

With the widespread of digital techniques, a frequency synthesis method named Direct Digital
Synthesis (DDS) has been formulated from early 1970s. It is based on phase accumulator, Phase-
to-amplitude converter, DAC and Low-pass filter. Typically, phase-to-amplitude converter is
composed of Programmable ROM containing Lookup-table for output signal. The performance
of DDS is limited by the reference clock, DAC resolution and LPF. Assume that the clock fre-
quency is f c , frequency command word is M and phase accumulator is n bits long. Then

M · fc
fo = (2.1)
2n

and the frequency resolution is

fc
f r es = (2.2)
2n
In practice, the best advantage of DDS against PLL is its super short frequency switching inter-
val. However, it is too costly to build a DDS simply to generate sinusoidal signal as local oscil-

4
CHAPTER 2. FREQUENCY SYNTHESIZER REVIEW 5

Figure 2.1: DDS block diagram[9]

lator or reference clock where the settling time requirement is comparatively loose. Therefore,
the DDS is fundamentally not the best choice for generating local frequency for RF signals.

2.3 Traditional Indirect Synthesis using Phase-locked Loop

Figure 2.2: PLL block diagram[10]

The indirect synthesis utilizes a PLL to lock the output of VCO, which has massive phase noise at
free-running mode. The Error Detector, typically known as phase detector compares the current
phase accumulated by reference clock and VCO divided by N. Then through a charge pump, it
converts the phase difference to corresponding voltage signals. The loop filter is to ensure the
CHAPTER 2. FREQUENCY SYNTHESIZER REVIEW 6

stability of the system at cost of extending settling time. Often times, the feedback divider is
programmable and able to generate fractional division.
The transfer function of traditional PLL is

N K d K V Z (s)
µo = µRE F (2.3)
s(N + K d )

The classic PLL is only suitable for narrowband RF signals as the bandwidth of the input signal
is within the loop bandwidth of PLL.

2.4 Towards an ALL-Digital PLL Approach

The structure of ADPLL is basically resembled with classic PLL, but is implemented with all
digital sub-blocks. First the VCO is substituted by a DCO which is controlled by digital tuning
word. It is commonly realized by LC-tank arrays which save massive area on chip. The phase
detector compares the phase difference between reference clock and DCO by accumulate clock
edges and fractional error from time-to-digital converter. The loop filter is implemented in a
digital type. Detailed discussion will be presented in following chapters.
Chapter 3

ADPLL Bahavioral Theory

3.1 System Diagram

Figure 3.1: ADPLL System Diagram

The system is consist of several blocks including Retimed Clock, Time-to-digital converter,
Phase detector, Digital Loop Filter, DCO gain normalization, Sigma-Delta Modulator and Digital-
controlled Oscillator. In this chapter, basic behavioral and structural introduction in both time
and phase domain will be discussed.

7
CHAPTER 3. ADPLL BAHAVIORAL THEORY 8

3.2 Time-domain analysis

3.2.1 Retimed Clock

It is well known that for a digital system, the clock signal is of great importance such that it
synchronizes all the sub-blocks and defines the data stream direction. In this ADPLL, it is obvi-
ous that the free-running DCO and reference clock is not entirely synchronized. It is also worth
considering that the ADPLL is actually not working on pipelining mode. On the contrary, there
should be slight difference between the rising edges of clock sent to each sub-block.

(a) diagram (b) waveform[11]

Figure 3.2: Retimed Clock

By using a posedge triggered D flip-flop, we could make sure that the data stream moves almost
every reference clock and always at the positive edge of the CKV so that the DCO will alter its
frequency at phase zero. The concept is shown in figure 3.2(b) and an example of N = 1.75 has
been demonstrated.

tV = i · T V

tR = k · T R + t0

tR = k · T R + t 0
1 2 3
[1] = [2] = [3] = [4] = 0
4 4 4

Figure 3.3: Retimed Clock demo with N = 1.75

CHAPTER 3. ADPLL BAHAVIORAL THEORY 9

3.2.2 Time-to-digital Converter

The time-to-digital converter measures the fractional error between DCO output and reference
signal. Since the Oscillator phase accumulator provides the number of CKV edges during one
reference clock for phase detector, the TDC would provide the time from the last CKV positive
edge to the next reference clock edge.
It is worth noticing that the direct output of CKV does not represent the fractional error, we
still need the period normalization, which divides ¢t r by the period of CKV. In order to get the
period of CKV, the TDC also measures the time from last negative edge of CKV to the clock edge
of reference. The concept is shown in Fig 3.4.

Figure 3.4: Fractional Phase error estimation[1]

¢t r
≤ = 1° (3.1)
TV

T v = 2|¢t r ° ¢t f | (3.2)

The structure of time-to-digital converter is based on inverter lines. Conceptually, it sends a

digital signal into a chain of inverters and sample the signals from inverter lines by the same ref-
erence clock. The outputs of register arrays form a pseudo-themometer code. In this example,
CHAPTER 3. ADPLL BAHAVIORAL THEORY 10

¢t r = 6 · t i nv , ¢t f = 2 · t i nv .

Figure 3.5: Time-to-digital converter[1]

In this implementation, two parameters, the number of inverter stages and t i nv need to be spec-
ified. First, we can determine the stages L by the maximum TV and minimum t i nv as

max (TV )
L= (3.3)
min(t i nv )

Second, t i nv actually stands for the resolution of TDC which is 30ps for a typical 0.13°µm CMOS
technology. Since the TDC converts analogy parameters into digital ones during which gener-
ates quantization error, it must contribute to the DCO phase noise which will be discussed later.

3.2.3 Phase detector

The diagram of phase detector is shown in Fig 3.6. We could see that within each reference clock,

Rr [k] = Rr [k ° 1] + F CW (3.4)

R v[k] = R v[k ° 1] + ¢R v[k] (3.5)

¡E [k] = Rr [k] ° Rv[k] ° ≤[k] (3.6)

where Rr [k] is the estimation of reference phase, Rv[k] is the estimation of variable phase, ≤[k]
is the fractional error correction and ¡E [k] is the phase error, all elements in reference cycle k.
CHAPTER 3. ADPLL BAHAVIORAL THEORY 11

Figure 3.6: Phase detector

k RV [k] R R [k] ≤[k] ¡E [k]

0 0 0 0 0
1 0 0 0 0
2 2 1.75 -0.25 0
3 2 1.75 -0.25 0
4 4 3.5 -0.5 0
5 4 3.5 -0.5 0
6 6 5.25 -0.75 0
7 7 7 0 0

Table 3.1: Numerical Example of Phase Detector when N = 1.75

Table 3.1 shows the phase detector outputs corresponding to Fig 3.3.

3.2.4 Digital Loop Filter

The digital loop filter is an essential part in ADPLL since it guarantees the stability of the whole
system. In fact, it is a typical PI controller. A first-order digital loop filter diagram is shown in Fig
3.7.
The proportional part is K p while the integrated part is K i . The transfer function is

z °1
H (z) = K p + K i (3.7)
1 ° z °1

More detailed discussion of how the choice of K p , K i affect the system stability and loop band-
width will be presented in phase-domain section.
CHAPTER 3. ADPLL BAHAVIORAL THEORY 12

Figure 3.7: Digital Loop Filter

3.2.5 Sigma-Delta modulator

Sigma-Delta modulation is typically used in Analog-to-Digital Converter in order to reduce the

in-band quantization noise and reach high resolution. In a PLL, a fraction-N modulo counter is
involved to achieve fraction-N synthesis. Accordingly, in an ADPLL, since the resolution of DCO
is fixed, in order to represent fractional part of OTW, dithering method is introduced which is
achieved by ߢ modulation.

Fractional dithering

Assume the ¢ f LSB is the frequency step if we add one bit to the least-significant bit of DCO. In
a reference cycle, if we would like to add fractional step, we need to dither the fractional part
between 0 and 1. For example, if we would like to represent 6/11, we can use a chain of 0 and 1’s.

6/11 = 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 1 . . . (3.8)

Then, the question comes as why ߢ modulation could generate digital data stream such that
their average converges to the fraction number. In order to answer the question, let’s first present
the structure of first-order sigma-delta modulator.
CHAPTER 3. ADPLL BAHAVIORAL THEORY 13

Figure 3.8: First-order sigma-delta modulator

First-order ߢ modulator

For the first-order SDM, the relay is a 1-bit quantizer, the first adder is ß part and the transfer
function of the filter between the ß part and quantizer is

z °1
H (z) = (3.9)
1 ° z °1

Suppose the relay is an additive noise source with noise function e(k), then we can write the
differential equation of the system as

y(k) = x(k ° 1) + e(k) ° e(k ° 1) (3.10)

where y(0) = 0, e(0) = 0. Assume that the input is a DC signal value x, let’s calculate the average
value of y(k),
1 n°1
X 1Xn 1Xn
y(k) = x(k ° 1) + (e(k) ° e(k ° 1)) (3.11)
n 0 n 1 n 1
1 1
)y =x+ (e(n) ° e(0)) = x + e(n) (3.12)
n n
Since e(n) is bounded by [0, 1], x = x, we get

1
lim y = x + lim e(n) = x (3.13)
n!1 n!1 n

Eq 3.13 shows that the low-term average value of SDM output converges to the input fractional
number. Since we have proved the convergence of SDM, the nature question arrives as how fast
it converges and what’s the order and type of SDM should we choose. These detailed aspects
will be included in the modeling section.
CHAPTER 3. ADPLL BAHAVIORAL THEORY 14

3.2.6 DCO normalization

For a digital-controlled oscillator, K DCO represents the frequency step when we add one bit to
the LSB of DCO oscillating tuning word. However, for a LC-tank based DCO, usually K DCO is not
a constant and we need to find another way to calculate the OTW from NTW.

1
f = p (3.14)
2º L(C f +C v )

where L and C f are fixed value calculated given the bandwidth of ADPLL. Often times, NTW
represents the current ¢ f from last cycle measurement. If we take derivatives from Eq 3.14, we
get
d f = °2º2 L f 3 dC (3.15)

If ADPLL enters tracking mode, ¢ f and ¢C are typically small value (compared to f and C ) and
thus we can do the approximation.
¢f
¢C = ° (3.16)
2º2 L f 3
If C tank is uniform-weighed, we get ¢OT W = C¢C
LSB

3.2.7 Digital Controlled Oscillator

In this design, we choose DCO instead of VCO in order to avoid adding a complementary DAC.
Compared to voltage-controlled oscillator, DCO is more stable and more importantly, it occu-
pies less area on chip which is suitable for integrating.

LC tank

The DCO is controlled by digital signal which is implemented by varactor capacitance[1]. The
capacitor is able to switch its capacitance when the control voltage holds at two different levels.

C [k] = C 0 [k] + d [k] · ¢C [k] (3.17)

where d [k] is 1-bit digital signal chosen from 0 and 1, C 0 [k] is low-level capacitance and C 0 [k] +
¢C [k] is high-level capacitance.
CHAPTER 3. ADPLL BAHAVIORAL THEORY 15

Figure 3.9: LC tank model[1]

In this model, we could calculate the total capacitance as

NX
°1 NX
°1 NX
°1
C t ot al = C 0 [k] + d [k] · ¢C [k] = C 0,t ot al + d [k] · ¢C [k] (3.18)
0 0 0

Thus the output frequency is given by

1
f = p (3.19)
2º LC t ot al

Phase noise

In reality, an oscillator does not provide pure frequency. Its power will spread away and create
"skirt" aside the center frequency. In mathematical, it is illustrated as

y(t ) = A c sin (2º f c t + ¡(t )) (3.20)

The phase noise is composed of flicker-noise (1/ f 3 ), thermal-noise (1/ f 2 ) and electronic-noise
(1/ f 0 ) whose spectrum has 30dB/dec, 20dB/dec and 0dB/dec characteristic, respectively. The
technique of generating such power spectrum will be discussed in the modeling part.

DCO resolution

Another important feature of DCO is frequency resolution which is directly determined by TDC
resolution and loop filter proportional gain K p .

¢t r es 1
¢ f V,r es = K p ( ) (3.21)
TV N · T R
CHAPTER 3. ADPLL BAHAVIORAL THEORY 16

Figure 3.10: Practical DCO phase noise spectrum[2]

where N is the number of reference cycle in one observation interval. Obviously, increasing N
or decreasing K p would improve ADPLL accuracy yet at cost of sacrificing settling time and loop
bandwidth. In real application, these parameters have to be well evaluated in order to achieve
optimal performance.

3.3 Phase-domain analysis

In time domain, we are able to grasp the structure and functionality of each sub-block except for
the frequency response. In order to work out the transfer function and characteristics of ADPLL,
a phase-domain model is necessary.

3.3.1 Phase-domain model

Figure 3.11: Phase domain model diagram

CHAPTER 3. ADPLL BAHAVIORAL THEORY 17

Linear s-domain approximation

If we transform z-domain operation into s-domain, we get

z = e s/ f (3.22)

If the interested f r e f is much lower than f sampl e , we get the approximation from Eq 3.22 as

z = e s/ f r e f º 1 + s/ f r e f (3.23)

Phase detector

fr e f
The phase detector subtracts the DCO phase from the reference phase. Since s produces the
reference phase, we could treat it as X (s). Thus the output of phase detector is

F CW · X (s) ° Y (s). (3.24)

Loop Filter

The loop filter is actually a PI controller with proportional coefficient Kp and integral coefficient
Ki. The transfer function is

z °1 fr e f
Hl (z) = K p + K i · °1
º K p +Ki · = Hl (s) (3.25)
1°z s

DCO

The DCO part is consist of DCO gain normalization and DCO oscillator. In order to simplify the
ˆ = K DCO . Thus the DCO transfer function is
model, we assume that K DCO

2º f r e f
Hd (s) = (3.26)
s

Let ¡p and ¡t be the additive phase noise from DCO and TDC. Thus from Eq 3.23-3.26, we get

Y (s) = Hr e f X (s) + HDCO ¡p + HT DC ¡t (3.27)

where
F CW ·Hl (s) f r e f K p f r e f s+K i f r2e f
Hr e f = s+Hl (s) f r e f = F CW · s 2 +K p f s+K i f r2e f
re f
CHAPTER 3. ADPLL BAHAVIORAL THEORY 18

s s2
HDCO = Hl (s) f r e f +s
= s 2 +K p f 2
r e f s+K i f r e f

Hl (s) f r e f K p f r e f s+K i f r2e f

HT DC = Hl (s) f r e f +s = s 2 +K p f r e f s+K i f r2e f

3.3.2 Phase domain analysis

From Eq 3.27, we could see Hr e f = F CW · HT DC , HDCO = 1 ° HT DC . So the frequency response

of Hr e f and HT DC will only differ in amplitude and the passband characteristics of HT DC and
HDCO will be opposite. We could conclude that TDC noise transfer function is low-pass while

Figure 3.12: Bode plot of HT DC , HDCO and Hr e f , K p = 2°5 , K i = 2°11 , f r e f = 40k H z

DCO transfer function is high-pass. Thus the phase noise in ADPLL will be dominated by TDC
noise in low frequency stage and by DCO phase noise in high frequency stage. If we compare
HT DC to a classical two-pole transfer function,

2≥!n s + !2n
H (s) = (3.28)
s 2 + 2≥!n s + !2n
CHAPTER 3. ADPLL BAHAVIORAL THEORY 19

where ≥ is damping factor and !n is natural frequency. Fit HT DC in, we get

p
!n = f r e f Ki (3.29)

Kp
≥= p (3.30)
2 Ki
The system has one zero and two poles as

Ki fr e f
s =° (Zero) (3.31)
Kp
s
Kp fr e f Kp fr e f
s 1,2 = ° ± ( )2 ° K i f r2e f (Two poles) (3.32)
2 2
The zeros will affect the amplitude and phase characteristics of the system while the poles in-
fluence on the stability and response type.

stability

The real part of two poles are always less than zero since K p , K i and f r e f are all positive numbers
and the system is unconditionally stable theoretically.

step response

When ≥ > 1, it is a over-damped system, ≥ = 1, critical damped system, ≥ < 1, a under-damped

system. It is clear that in a under-damped system, there would be ringing which would delay
the settling time. In a over-damped system, the overshot and settling time is decreased when
≥ grows larger. However, if ≥ is too big and that would lead to one of the pole approaching to
zero. In a real system, such systems could become unstable if other noise source is introduced.
In these cases, we could set a safety bound, such that
s
Kp fr e f K p2 f r2e f
° + ° K i f r2e f < k (k < 0, ≥ > 1) (3.33)
2 4

!n k 2
)≥<° ( + 1) (3.34)
2k !2n
where k is the safety boundary.
CHAPTER 3. ADPLL BAHAVIORAL THEORY 20

Figure 3.13: Step Response of different damping factor

Loop bandwidth

The loop bandwidth of a system is defined as the frequency such that the amplitude of open
loop transfer function is 1 (0dB) and thus the amplitude of close loop transfer function would
be p1 (-3dB).
2
Hol
HT DC = (3.35)
1 + Hol
f r e f (K p s + K i f r e f ) Kp 1
) Hol = = K i f r2e f · ( s + 1) · (3.36)
s2 Ki fr e f s2
Eq 3.36 tells that the open loop transfer function contains a proportion, differentiation and a
2nd-order integrating element. Based on bode plot approximation (see Fig 3.14), we get band-
width approximation as
8
< !n = f r e f · K p , ≥ ∑ 1/2
2≥
BW approximation = (3.37)
: f
re f · Kp , ≥ > 1/2

If we fix ≥ = 1, we could plot loop bandwidth versus K p . (Fig 3.15)

CHAPTER 3. ADPLL BAHAVIORAL THEORY 21

Figure 3.14: Bode diagram approximation

Figure 3.15: Bode plot of Hol with ≥ = 1 and f r e f =40kHz

CHAPTER 3. ADPLL BAHAVIORAL THEORY 22

It is obvious that the loop bandwidth increases when K p grows and this result is quite useful if
the system works on several modes. When the current output is far from objective, increasing
K p could shorten the converging time. When the difference is tiny, decreasing K p to limit the
bandwidth could improve the accuracy.

Settling time

The settling time is a key characteristic that defines how fast the ADPLL could be locked. It
depends on the damping factor ≥ and K p . By using the MATLAB inline function "stepinfo", we
could get the following table indicating the number of reference cycles when the system has
settled.
HH p
H ≥
H 0.5 p1 1 2 2
Kp HH 2
2°6 481 443 753 1022 1293
2°5 241 222 389 511 647
2°4 121 111 392 256 324
2°3 61 56 392 128 162
2°2 31 28 392 64 81

Table 3.2: # of reference cycles to settle

From table above, empirically, if we double K p , the settling time would divide. Fixed K p , the
smaller difference between ≥ and 1 would produce less settling time. This result would guide
our choice of K p and K i when designing loop filter.
Chapter 4

Modeling and Verification

4.1 General Idea

This ADPLL is used for LO which has frequency range of 2.9-3.6GHz. The derived phase noise
mask is specified as

offset frequency derived phase noise

¢ f < 1k H z -50dBc/Hz
1k H z < ¢ f < 500k H z -27.5dB/dec
¢ f > 500k H z -105dBc/Hz

Table 4.1: Phase noise mask specification

The phase noise mask is set according to the free-running DCO phase noise level and TDC phase
noise level which is shown in Table 4.2 and 4.3.

Scaling Method

The general idea of verification is to build this model in simulink and test whether its phase noise
meets specifications. The feasibility is guaranteed by high-rate oversampling in time domain.
However, the offset frequency band is too narrow compared to the center frequency. In order
to make them compatible, it is assumed that the phase noise spectrum will not change with the
moving of oscillator center frequency. Thus a scaler could be added to the specified reference
clock and oscillator output frequency. The parameters are specified as

23
CHAPTER 4. MODELING AND VERIFICATION 24

Scaler = 1000
reference clock 40kHz
output frequency range 2.9-3.6MHz
TDC resolution 10ns, 20ns, 30ns
DCO phase noise frequency vector [1e1, 1e2, 1e3, 1e4, 1e5, 5e5, 1e6]Hz
DCO phase noise level vector [-10, -30, -50, -70, -90, -110, -110]dBc/Hz

Table 4.2: ADPLL parameter specifications

4.2 Sub-block implementation

4.2.1 Time-to-digital Converter

We have demonstrated that the TDC would provide fractional error to phase detector as

¢t r [k] 1
≤[k] = 1 ° b c · ¢t r es · (4.1)
¢t r es TC K V

In simulink implementation, the ¢t r [k] is directly obtained by measuring time difference be-
tween positive edges of corresponding reference clock and CKV. Then the quantization error is
added according to Eq 4.1. In previous section, it has been showed that the DCO phase noise
at low frequency will be dominated by TDC noise, which is determined by inverter delay. We
directly give out the result as
(2º)2 ¢t r es 2 1
L= ( ) [1] (4.2)
12 TC K V f r e f
where ¢t r es is the inverter delay, TC K V is the period of DCO output frequency and f r e f is the
reference frequency. Table 4.3 provides phase noise level at different TDC resolution.
2
¢t r es (ns) L = (2º) ( ¢tr es )2 f 1 (dBc)
12 TC K V re f
30 -61.07
20 -64.59
10 -70.61

Table 4.3: TDC noise level, F CW = 81.25, f r e f = 40k H z

4.2.2 Phase detector

If we rewrite Eq 3.4, 3.5, 3.6,

¡E [k] = Rr [k] ° R v[k] ° ≤[k] = Rr [k ° 1] + F CW ° R v[k ° 1] ° ¢Rv[k] ° ≤[k] (4.3)

CHAPTER 4. MODELING AND VERIFICATION 25

¡E [k ° 1] = Rr [k ° 1] ° Rv[k ° 1] ° ≤[k ° 1] (4.4)

Thus
¡E [k] = ¡E [k ° 1] + F CW ° ¢R v[k] ° (≤[k] ° ≤[k ° 1]) (4.5)

Based on this idea, we could have access to both ¡E [k] and ¡E [k ° 1] at cycle k. There are two

Figure 4.1: Alternative phase detector architecture[1]

advantages of this implementation. First, it’s easier to maintain status since the previous value
of phase detector hasn’t been vanished. Second, there is no accumulation of FCW and RV [k].
Given the fact that R R [k] has fixed word length, it won’t overflow in which case avoids modulo
arithmetics. Clearly, it is very common that the phase detector produces negative number so 2’s
complement is introduced.

4.2.3 Mode switch

For a typical ADPLL[1], there are three modes which are known as PVT (process-voltage-temperature),
ACQ (Acquisition) and TRK (tracking). In this implementation, we simplify the process by skip-
ping PVT mode. The ACQ and TRK LC bank are all 8-bits binary-weighed bank. ߢ modulation
is second-order MASH 1-1 which will provide TRK integer dithering between [-1,0,1,2]. In ACQ
mode, since the frequency interval is not linear, we use binary search which would take 8 ref-
erence cycles. In TRK mode, the frequency interval is small enough to use Eq. 3.16 to calculate
¢OT W .
CHAPTER 4. MODELING AND VERIFICATION 26

Figure 4.2: Procedure of DCO mode operation

4.2.4 Sigma-Delta modulator

In this design, ߢ modulator is implemented as second-order MASH 1-1.

2nd-order MASH-1-1

The transfer function of 2nd-order MASH-1-1 is

H (z) = z °2 X (z) + (1 ° z °1 )2 E 2 (z) (4.6)

where E 2 (z) is the quantization error of the relay in second stage. Apart from converging to
the fractional number, the dithering integer serves to increase the randomness of SDM in order
to avoid unnecessary spurious frequency. Accordingly, lack of randomness becomes the major
drawback of the first-order ߢ modulator which is illustrated in Fig 4.4.
For the original form of high-order ߢ in series, the limiting factor is the critical path which
contains at least two accumulator stages. This restricts the operational frequency of SDM which
is unacceptable in high-speed ADPLL.

Convergence time

Typically, the convergence time is determined by the structure of ߢ modulator. Empirically,

the fastest SDM clock could reach f C K V /4 which means that during one reference cycle, there
CHAPTER 4. MODELING AND VERIFICATION 27

Figure 4.3: 2nd-order MASH-1-1 ߢ modulator

are approximately 19 cycles for ߢ modulator to approach its fractional value. For MASH-1-1, if
we fix the input to be 0.1236, the simulation outcome is depicted as followed

# of cycles average
19 0.1053
128 0.1172
1024 0.1240

Obviously, the longer the SDM runs, the more accurate the output produces. From another
point of view, it is absolutely not a limiting factor as long as the SDM keeps running since the
input varies slow. Thus the output responds to the input quite well. In the long run, SDM will
ultimately produce a good average.

Resolution improvement

Lastly, let’s focus on how finer of ADPLL resolution the SDM could improve. Actually, it depends
on the word-length of fraction M. Combined with Eq.3.21, we get the total resolution of ADPLL
as
¢t r es 1 1
¢ f V,r es = K p ( ) (4.7)
TV N · T R 2 M
CHAPTER 4. MODELING AND VERIFICATION 28

(a) Quantization error

(b) output spectrum

Figure 4.4: First-order ߢ modulation characteristic

CHAPTER 4. MODELING AND VERIFICATION 29

Obviously, longer the fractional word length, higher the resolution and better the phase noise
performance. In practice, if M has reached certain threshold, increasing M will not improve the
system performance any longer and yet, this threshold becomes our final setting for fractional
word length.

4.2.5 Digital Controlled Oscillator

In order to determine LC tank, we first specify the property of DCO.

Mode Frequency range center frequency frequency span OTW integer bits ¢ f LSB
ACQ 700kHz 3.25MHz 2.9MHz-3.6MHz 8 2.73kHz
TRK 4kHz f cA f cA ± 2k H z 8 15.625Hz

Table 4.4: Property of different mode of DCO

LC tank
frequency range
f mod e,max = f mod e,c + (4.8)
2
frequency range
f mod e,mi n = f mod e,c ° (4.9)
2
1
C mod e,max = (4.10)
L(2º f mod e,mi n )2
1
C mod e,mi n = (4.11)
L(2º f mod e,max )2
According to Eq.4.8-4.11, we could calculate the specific capacitance and inductance as

L 1nH
C 0,t ot al 1.93µF
¢C LSB,ACQ 4.38nF
¢C LSB,T RK 17.10pF

Table 4.5: LC tank specifications

In real model, the capacitor won’t act the exact way as calculated, there must be some percent
of inaccuracy for each individual capacitor. For example, if the inaccuracy H is set to 20%, it
means that most of capacitance generated should lie between 0.8-1.2. It’s natural to model it as
Gaussian distribution and we know that 99.74% number of a Gaussian distribution lie between
[°3æ + µ, 3æ + µ], thus 3æ = H . So at the initiation of each modeling, the random number and
capacitance array will be generated and stay the same since then.
CHAPTER 4. MODELING AND VERIFICATION 30

Phase noise

For an oscillator, phase noise is the most important feature that defines its performance. In
previous part, we have shown that the phase noise is defined as

y(t ) = A c sin(2º f c t + ¡(t )) (4.12)

If we rewrite the formula above

y(t ) = A c sin(2º( f c + N (t ))t + ¡0 ) (4.13)

where N (t )·t +¡0 = ¡(t ). In Eq 4.13, we could concluded that DCO spectrum would be the same
as f c + N (t ), where N (t ) follows certain distribution such that the probability density function
is the interpolation of phase noise frequency and phase noise level vectors. So the problem
has become designing a digital filter such that it shapes the gaussian noise distribution to be
the same as the expected phase noise level. Let X ( f ) and Y ( f ) denote the input and output
frequency spectrum. Assuming that the digital filter has frequency response as H ( f ), we get
Y (f )
H(f ) = X (f )
. Thus we can get the coefficients of digital filter by

1. Generated a array of Gaussian random number X(n)

2. Calculate the input frequency spectrum X(f)

3. Calculate the output frequency spectrum Y(f) by interpolating expected phase noise fre-
quency vector.

4. The impulse response of the digital filter H ( f ) = Y ( f )/X ( f )

5. Do IFFT to get the coefficients of the proposed digital filter.

CHAPTER 4. MODELING AND VERIFICATION 31

Simulation results

If we set OTW to a constant, we are able to get DCO free-running spectrum as shown in Fig 4.5.
There is a -20dB/dec slope from 10Hz to 500kHz and approximately -105dBc/Hz@500kHz.

Figure 4.5: Free-running DCO spectrum

Chapter 5

Results

5.1 In-band phase noise

As mentioned before, the ADPLL in-band noise is determined by TDC phase noise level.
2
¢t r es (ns) L = (2º) ¢t r es 2 1
12 ( TC K V ) f simulated phase noise level
re f
30 -61.07 dBc/Hz º °60 dBc/Hz
20 -64.59 dBc/Hz º °62 dBc/Hz
10 -70.61 dBc/Hz º °70 dBc/Hz

Table 5.1: TDC noise level, F CW = 81.25, f r e f = 40k H z

Figure 5.1: In-band phase noise spectrum given different inverter delays,
FCW=81.25, f r e f = 40kHz

32
CHAPTER 5. RESULTS 33

The result shown in Fig 5.1 basically corresponds to the TDC phase noise level, yet a slight in-
band fluctuation is inevitable since the DCO phase noise also contributes to the in-band noise
with a 20dB/dec characteristics. Also, the FFT resolution limits how detailed the spectrum is
particularly in low frequency band.
In order to get high-performance in-band noise shaping, the fractional quantization error must
be eradicated from limiting factors such that the fractional bits precision is required to reach
certain threshold which is 17 bits according to Fig 5.2. Higher precision will not improve low-
frequency band performance any more and unacceptable noise shaping deterioration occurs
when fractional precision is under 14 bits.

Figure 5.2: In-band phase noise spectrum at different fractional precision

FCW=81.25, f r e f = 40kHz, t i nv = 30ns

5.2 Out-band phase noise

According to the phase-domain analysis, the decisive factor of out-band phase noise is DCO
phase noise distribution. Fig 5.3 illustrates the difference between free-running DCO and AD-
CHAPTER 5. RESULTS 34

PLL output. The ADPLL output is fully masked by phase noise requirement.

Figure 5.3: Out-band phase noise, FCW=81.25, f r e f = 40kHz, t i nv = 30ns

ߢmodulation

How ߢ modulation affects the out-band noise varies with its structure and clock. Since SDM is
aimed at increasing DCO resolution by dithering fractional OTW, the clock should be as fast as
possible. In reality, the SDM clock is limited by its critical path as

T > t p!q,max + t combi nat i onal ,max + t set up,max (5.1)

where the combinational logic is basically accumulator stages. Fig 5.4 demonstrates how SDM
affects the phase noise spectrum for a specific FCW. In fact, it’s difficult to depict a whole picture
of how SDM influences ADPLL output since it varies with different frequency command word.
CHAPTER 5. RESULTS 35

Figure 5.4: Effect of phase noise spectrum with SDM on and off,
FCW=81.25, K p = 2°5 , t i nv = 30ns

As can be seen from Fig 5.5, there is no obvious low-frequency band phase noise improvement
with higher SDM clock. It is probably because for both clock=CKV/4 and clock=CKV/8, the sim-
ulation interval is long enough for them to produce a good average.
Another important feature is SDM input word length. In practice, we avoid truncation and set it
the same as fractional word length. In fact, the performance of a 10-bit SDM input word doesn’t
deteriorate too much according to Fig 5.6.
CHAPTER 5. RESULTS 36

Figure 5.5: Effect of phase noise spectrum with different SDM clock,
FCW=81.25, K p = 2°5 , t i nv = 30ns

Figure 5.6: Effect of phase noise spectrum with different SDM input word length,
FCW=81.25, K p = 2°5 , t i nv = 30ns
CHAPTER 5. RESULTS 37

5.3 Settling time and Loop bandwidth

Basically, the loop filter parameters K p and K i decide the ADPLL convergence mode, loop band-
width and settling time. In this model, the "convergence" is defined as the OTW sandwiched by
certain deviation bound from expected oscillator tuning word.

Figure 5.7: Phase noise spectrum of different K p ,

FCW=81.25, f r e f = 40kHz, t i nv = 30ns, ≥ = 0.707

Fig 5.7 illustrates that the loop bandwidth of ADPLL with K p = 2°5 and K p = 2°7 is approximately
200Hz and 100Hz, respectively. It corresponds to the theoretical values quite well. Actually, in
this model, with damping factor p1 , feasible K p is limited from 2°7 to 2°4 . Low K p induces un-
2
acceptable settling time and loop bandwidth while high K p causes massive ringing which might
exceed the OTW range.
Table 5.2 summarizes how damping factor and K p influence simulated loop bandwidth and set-
tling time.
Fig 5.8-5.10 demonstrates the convergence mode and settling time given different loop filter
parameters. The fast dithering is caused by ߢ modulation.
CHAPTER 5. RESULTS 38

≥ = 0.707 ≥=1
Kp Loop bandwidth settling time Kp Loop bandwidth settling time
2°4 200Hz 2.35ms 2°4 200Hz 2.83ms
2°5 100Hz 4.68ms 2 °5
100Hz 6.37ms
2°6 50Hz 9.55ms 2°6 50Hz 14.03ms
2°7 25Hz 19.9ms 2 °7
25Hz 29.08ms
≥=2
Kp Loop bandwidth settling time
2°4 200kHz 1.38ms
2°5 100Hz 3.03ms
°6
2 50Hz 7.83ms
°7
2 25Hz 15.63ms

Table 5.2: Simulated loop bandwidth and settling time at different loop filter paramters

Figure 5.8: OTW in tracking mode, FCW=81.25, f r e f = 40kHz, t i nv = 30ns, ≥ = 0.707

CHAPTER 5. RESULTS 39

Figure 5.9: OTW in tracking mode, FCW=81.25, f r e f = 40kHz, t i nv = 30ns, ≥ = 1

Figure 5.10: OTW in tracking mode, FCW=81.25, f r e f = 40kHz, t i nv = 30ns, ≥ = 2

CHAPTER 5. RESULTS 40

5.4 Tradeoff evaluation

The ADPLL is a multidimensional feedback control system which is determined by bunches

of factors. However, once the inverter delay, fraction precision, reference clock and frequency
command word is settled, ADPLL performance is dominated by loop filter parameters K p and
Ki .

Damping factor

As shown in Fig 5.8-5.10, the convergence mode is determined by damping factor. The thresh-
old of ringing is 1 which satisfies phase-domain analysis. The ringing is expected because it im-
proves the phase noise shaping by dithering. Besides, it’s clear that high damping factor makes
the system unstable as can be seen when ≥ = 2 and K p = 2°4 . The step of OTW may be out of
range when the initial tracking OTW is near the edge of intervals.

Proportional factor

Another important parameter is K p which is the proportional gain factor of loop filter. It can
be concluded from Fig 5.8-5.10 and table 5.2 that high K p induces fast tracking and wide band-
width. Also if K p is too low, the phase noise could stretch out the phase noise mask as shown in
Fig 5.7. However, high K p results in higher fluctuation when the ADPLL has been locked. High
fluctuation causes more capacitor switches that will cause enormous phase noise in actually LC-
tank. Also, the periodic oscillation might make the system unstable if outside jitter penetrates
the system.
CHAPTER 5. RESULTS 41

5.5 Block parameters setup for fulfillment of best performance

All data are summarized from discussion above. Actually, parameters setup is of critical impor-
tance since they can’t be changed once the ADPLL is built on chip.

ADPLL settings
f r e f = 40k H z
Integer Word Length = 17 bits
General
Fractional Word Length = 17 bits
FCW Input Range = 72 - 90
¢t r es = 30ns
TDC Inverter Inaccuracy = 0%
Precision = 17 bits
Kp TRK = 2°5
LF Ki TRK = 2°11 (≥ = 0.707)
Precision = 34 bits
Input Word Length = 17 bits
SDM Output Word Precision = 2 bits
Clock division Rate = 4
ACQ range = 700kHz
TRK range = 4kHz
DCO
Phase noise frequency vector = [1e1, 1e2, 1e3, 1e4, 1e5, 5e5, 1e6] Hz
Phase noise level vector = [-10, -30, -50, -70, -90, -110, -110] dBc/Hz

Table 5.3: Proposed settings for ADPLL

Chapter 6

Discussion and future work

The simulation is based on Simulink and the outcome is basically consistent with phase-domain
theoretical model which validates the feasibility of this ADPLL model. The parameter setups re-
quires deep understanding of the phase-domain model which needs substantial investigation
of each separate sub-block. However, it is after all a model built on software and future imple-
mentation on chip is required to draw certain conclusions.

The model is simplified in many aspects such as frequency scaling, inverter delay inaccuracy,
DCO flicker and thermal noise. The mode switch ACQ part is idealized such that it only per-
forms binary search in order to focus on the tracking process. A more comprehensive model
concerning all ignored parts should be the concentration in future work.

Another defect lies in the approach to find optimal settings which is based on limited tests. In
fact, with all sub-blocks settled, it’s very hard to find a overall optimal system operating point
because of the comprehensiveness of ADPLL system and testing seems to be the most effective
way in restricted time.

MASH-1-1 is chosen as SDM in this implementation. The argument may seem not persuasive
enough since we haven’t tried higher-order MASH type or other types of SDM. Actually, the ef-
fect of SDM imposing on ADPLL varies with FCW and reference clock which makes the task even
more mysterious. A more detailed model should be conducted in this area in future work.

This model ultimately aims at ADPLL behavioral simulation and verification. In this process,
much optimization and improvement work could be included such as inserting an IIR filter be-

42
CHAPTER 6. DISCUSSION AND FUTURE WORK 43

fore loop filter to better restrain high-frequency noise and it is supposed to be carefully investi-
gated in future work.
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