A New Adaptive Driving Technique for
High Current Gate Controlled Devices
S . Musumeci, A. Raciti, A. Testa
Universita' di Catania
Dipartimento Elettrico Elettronico e Sistemistico
Viale Andrea Doria, 6 - 95 125 Catania, Italy
Abstract - MOSFETs and IGBTs devices are
increasingly used in electronic circuits due to both the
easy driving and the capability to handle high currents
and voltages at high switching frequencies. This paper
deals with a new driver circuit that allows to optimise
the switching speed, to reduce the energy losses during
the switching time, and to limit the Electro Magnetic
Interference (EMI). Firstly an analysis of voltage and
current switching waveforms of gate insulated devices is
performed. Hence, how to control voltage and current
slopes independently it is shown, by using a suitable
adaptive driving technique, based on a PLL approach.
Such a technique has been adopted in order to correctly
generate the gate signals regardless of tlie operiiting
conditions. Finally practical tests of tlie proposed
driving circuit obtained using a single switch converter
and IGBT devices are reported.
1. INTRODUCTION
By increasing the switching speed it is possible to
reduce the power dissipation of a power device, although at
the cost of an increased generation of electro-magnetic
interferences (EMI). In fact, by increasing the slope of the
current during the switching transients, the level of EM1 is
increased, so that, a reasonable compromise betiveen
device features, power losses and EM1 must be found in the
design of any power converter.
The switching speed of a MOSFET device is strictly
related to the rate of the charge supplied to the gate input
capacitance [ 11 [ 2 ] . Moreover, by suitably shaping the gate
current. it is possible to control independently the slopes of
drain voltage and current. The behavior of an IGBT
device is siinilar to that of a MOSFET. excepting for the
current tail present on the falling edge of the collector
current.
0-7803-1456-5194 $4.00 0 1994 IEEE
A. Galluzzo, M. Melito
SGS- Thomson
Co.Ri.M.Me Research Center
Stradale Primosole, 50 - 95 100 Catania, Italy
The aim of the present paper is to illustrate a new
driver strategy and a circuit topology that allow to obtain
an acceptable compromise between switching speed, power
dissipation and electromagnetic radiation, by suitably
shaping the gate current during the switching transients.
The description of the new driving strategy starts with an
analysis of voltage and current switching waveforms of
gate insulated devices, pointing on those characteristics
that influence the drain current slope. As a result of such
an analysis a driving strategy that allows to independently
control voltage and current slopes is developed. A suitable
adaptive driver circuit implementing the new driving
strategy, based on a PLL approach, is then shown and
practically tested.
2. SWITCHING TRANSIENTS
Insulated gate devices are faster than BJTs (Bipolar
Junction Transistors) since the only charges involved
during turn-on and turn-off transients are related to stray
capacitances and depletion layer capacitance [ 3 ] . A simple
circuital approach to analize the switching transients, may
be performed by considering only two of such parasitic
capacitances. namely tlie gate-source capacitance C, and
the gate-drain capacitance C,,, being ininfluent the drain
source capacitance. Moreover, by considering gate bias,
driving impedance, and stray circuit inductances, the
device characteristics in terms of switching speed and
power losses may be defined.
In Fig. 1 a schematic representation of the gate-charge
curve of MOSFETs and IGBTs is reported.
By injecting a constant current into the gate terminal,
the C,, and c,d capacitances start to increase their
voltages. The drain current Id, controlled by the Vgs
voltage, remains equal to the zero gate voltage drain
current Idas (few mA) until V,, reaches the threshold
480
voltage V, (region 0-1). After that it increases reaching voltage changes with a rate given by the following
the load current peak Id,,,, (region 1-2). The Miller effect is equations:
evidentiated by the constant voltage region (2-3) of the V,
curve. During this period the device input capacitance
appears to be infinite, since the input generator supplies
charge to the gate and V, holds the Miller voltage VMillrr.
The gate-source voltage V begins to increase again only
?f
after that the Miller region IS passed (region 3-4), reaching
the final value.

C,,, and C,d, are dependent on the drain-source voltage

v, [31.
In practical circuits, must be noted that some parasitic
inductances are present due to the wiring connection (Lsl,
L,, , and Ls3), as shown in Fig. 2.

Fig. 1 - Dynamic curves of insulated gate devices during a

turn-on transient.

During the turn-off transient in a Power MOSFET the L

gate charge curves are the mirror image of the turn-on
ones, wliile IGBTs present a different behavior related to

J
the inner BJT structure. In fact, as the gate voltage goes
below tlie threshold level, tlie electrons current ceases in
the MOSFET structure while tlie holes current in the BJT I L=2
decays with a tail, strongly dependent on the used
technology.
The above switcliing waveforms are generated using a
constant current generator supplying the gate terminal of
tlie device. This is not a coninion case since IGBTs and
Power MOSFETs are normally driven by voltage pulses.
By considering a step voltage vd applied to the input Fig.2 - Parasitic inductances influencing the switching
terminals the drain current slopes during turn-on and transient.
turn-off may be calculated by mean of the following
equation: Such inductances affect the switching transient,
particularly the driving voltage is dropped by the presence
I/ -v.--I d of L,, in tlie gate source path. Equation (1) must be
consequently rearranged accounting for the parasitic
voltage drop as follows:

481
the transconduttance depend on the specific device, while
the step voltage v d and stray inductance L,, are fixed by
the circuit.
3 . GATE DRIVING STRATEGIES
From the previous considerations clearly arises that the
simplest driving strategy consists in supplying a positive
voltage to the gate terminal at turn-on, and a negative
voltage at turn-off.
The positive gate voltage pulse applied to the input
terminals must be suitably selected to have low drain-
source on state voltage Vh(onl.
The negative step gate voltage, that would be
unnecessary to obtain the forward blocking state during the
turn-off transient, is however useful to prevent spurious
turn-on caused by dv/dt reported in the input circuit trough
c,d and also to speed-up the switching transients.
It can be observed that the term L,, in equation (4)
acquires a great relevance in comparison with the term
(R,Ciss)/g,,,, so that, in order to obtain the desiderate dId/dt,
a particular care in the wiring layout is needed, to
minimize the stray inductances.
By analyzing the switching transient, the following
considerations can be drawn:
- power losses niainly depend on the rate of increase of
drain current, that acts also on the peak current due to
the diode recovery, and on the dynamic saturation
voltage phenomenon;
- switching transients generate conducted EM1 with
amplitudes directly related to the time variation of the
drain current dId/dt [ 5 ] .
According to equation (4) the dId/dt may be controlled
by the gate resistance value R,. Such value have to match
two divergent goals: low power consumption, that requires
a low Rg, and low EM1 generation, requiring high values
of the gate resistance [6].
In power circuits design a compromise is thus generally
found on the value of R, in order to match reasonable low
power losses and acceptable EM1 levels.
In the present paper an alternative approach is used,
consisting in reducing the switching times by
compensating the Miller effect. In such a way in fact it is
possible to accelerate the voltage drain variation, and thus
the switching speed, without increasing the drain current
slopes and the EM1 levels.
The proposed driving strategy is based on an
independent control of the slopes of drain voltage and
current by suitably shaping the gate current. In fact, by
supplying gate current pulses at the raising of the Miller
effect. it is possible to fastly charge the input capacitance,
speeding up the variation of the drain voltage, without
482
changing the slope of the drain current.
4. THE DRIVING CIRCUIT
The novel strategy can be practically realized using the
circuit shown in Fig. 3.
@
Current
5
-
Fig. 3 Schematic of the proposed circuit.
Such circuit is composed of a standard push-pull output
stage with two separated turn-on and turn-off paths. An
additional current generator and a current sinker are
respectively present on the turn-on and the rum-off paths
to supply suitable gate current pulses. The current pulses
must be correctly triggered at the raising of the Miller
effect in order to not change the slope of the drain current.
As the firing times of the gate current pulses must change
according with the operating condition and the device
features, two PLL circuits have been developed in order to
on line adapt the trigger signals of the current generator
and the current sinker.
At turn-on the proposed driving circuit works as
follows. The initial gate current is fixed by adjusting R,
in agreement with both device electric specifications and
EM1 requirements. When the collector current reaches its
maximum value, the collector voltage starts to decrease,
and the Miller effect appears evident on the gate-emitter
voltage. This condition is detected by mean of a Miller
effect sensing circuit based on a RC network. The output
of such sensing circuit is then processed by a PLL circuit
that generates suitable triggering signals for the current
pulse generator.
The current generator increases the gate current
accelerating the collector voltage fall, and so eliminating
the dynamic saturation voltage phenomenon.
In Figs. 4 and 5 two turn-on switching transients of an
IGBT device are shown. In the first case a traditional
driver circuit is used while in the second test the power
device is driven by the proposed circuit.
 construction technology, its effects cannot be reduced by
I I I I I I I I I I I I I means of the driving circuit. Turn-off losses of IGBT
I I I I I I I I I I I I
c 4-1- + 4-4-4-I- + 4-4-4 devices can only be reduced during both Miller effect and
l l l l l l l l l l l l
PMOS turn-off phases. Moreover in order to reduce losses,
I I I I I !
it is necessary to decrease the R, value [SI. As a
consequence of the gate resistance value reduction, dVddt
I I I I I I
increases and thus losses decrease. It is also necessaly to
pay attention to not exceed the RBSOA limits, in fact, the
I
I
I
I
I
I
I
I
I
I
I
I I I I I I I I I
latching current and the RBSOA are strongly related with
-I- r -I- r T -1- -I-T i r
- 7-1- ~ -I i r the dVd/dt, i.e. with RgoEvalue [ 9 ] .
-
I I I I I I l l l l l l l l l l l l

l-7
l l l l l l l l l l l l l l l l l l l l I 1
I I
7 -1
I I
I I

Fig. 4 - Turn-on switching waveforms with the traditional

I I
7-1
I I
driving circuit. I I
I 1
vgs[5V/div], v d [75V/diV],Id [5A/div], t [2001is/div] 7-1
I I
I 1
I 1
T -1
I I
I I
I 1
7-1
I I
I I
Lt"t
I I
I I
1_I
I 1
U

Fig. 6- Turn-On switching energy with the traditional

driving circuit.
t [ 200ns/div]

Fig. 5 - Turn-on switching waveforms with the proposed

driving circuit.
Vgs [jV/diV],Vd [75V/div], Id [SA/div], t [200ns/div]

As can be observed in Fig.5 the gate voltage variation

is noticeably speed-up with respect to the case with the
traditional driving circuit, while the gate current slope is
practically the same (100 A/p).In order to better evaluate
the benefits of the proposed circuit in Figs. 6 and 7 the
switching energies involved in the two transients are
reported. Using the proposed circuit the lost energy is Fig. 7- Turn-on switching energy with the proposed
reduced of more than 35%. driving circuit.
The structural difference between Power MOSFETs t [ 200ns/div]
and IGBTs influences their behaviour at turn-off 171. In
fact. IGBTs shows a tail during the fall of the collector At turn-off the proposed circuit allows to improve the
current due to the time required for the excess carriers in switching behaviour of IGBT devices, while maintaining
the epitaxial drain region to decay. Such tail is responsible the same dV,/dt, by reducing the turn-off delay time and
for major losses and is strongly related to the device making the current fall faster due to the PMOS part of the

483
IGBT structure. Taking care of the absence of the current
tail and of the latching phenomenon, the previous
considerations are valid for Power MOSFET too and the
proposed circuit acts in the manner just described.
The above mentioned PLL circuits, shown in Fig. 3, are
used to synchronise the driving current pulses, either at
turn-on and at turn-off, with the raising of the Miller
effect. This is mandatory in order to obtain the best results
and cannot be simply achieved by imposing a fixed delay
between the driving signal and the current generator. In
fact such delay must be continuously changed according
with the operating conditions.
As it is not convenient to directly use the derivative of
the gate voltage to enable the current generators, due to
noises, to the fact that the shape of the gate voltage
changes with the operating conditions, and to the need to
use expensive very fast devices, a PLL approach has been
selected to generate the driving current pulses.
A scheme of the PLL circuit operating at turn-on is
shown in Fig. 8, where are evidentiated:
- the Miller effect sensing block, based on a RC network
described in the following;
- a phase comparator detecting the phase shift between the
output of the RC network V,, and the signal enabling
the current generator Vy;
- a low pass-filter producing a variable threshold Vt:
- two time delaying blocks used to conipensate propagation
delays;
VRC \i*T
Comparator
@ Delay
Compensator
Shift
U Ramp Generator
Fig. 8 - Block diagraiii of the PLL circuit operating at turn-on.
- a ramp generator triggered by the command signal Vh;
- a voltage comparator producing the enabling signal for
the current generator V,.
The PLL circuit operating at turn-off owns a similar
structure.
The Miller effect sensing block is based on an RC
network, as the time derivative of the gate voltage can be
used to detect the beginning of the Miller zone. The main
constraints to face in the design of such RC network are:
- the capacitance C must be smaller than the input
capacitance of the device Cissto not affect the dynamic of
the gate voltage;
- the resistance R must be small in order to obtain a high
bandwidth but big enough to not interfere with the
driving circuit and to produce a sufficiently large signal.
The following expression can be used to calculate the
amplitude of the signal across the resistor of the RC
network at turn-on, in according to the parameters of the
used devices:
In Fig. 9 the gate voltage V, and the RC network
output V,, used to detect the Miller zones are shown .
Phase
--+
Low Pass Filter
Current Gencrstor
Delay
I
vt
r-+- Buffer
484
 I I I I I I I I

I l l
I l l / I l l
T - - 7--1---1-

I
l l l l l l l
J
Fig. 11 -Signal enabling the current generator Vq and
input of phase comparator Vcpd.
Fig. 9 - Turn-on and turn-off transient of IGBT: V [SV/div], t [200ns/div]
a) Gate voltage;
b) RC network output. The signal enabling the current pulses V, in fact is
t [ 5 ps/div] generated, as shown in Figs 8 and 12, by comparing the
variable threshold Vt with a ramp Vr triggered by the
In order to synchronise the signal enabling the current command signal Vi*,.
generator V, with the raising of the Miller effect at turn-
I I I I I I I I I I I I I I I I I
on, the output of the RC filter V,, amplified and squared, .-4-I- t -e 4- c t 4 4-c 4-I- c + 4-I- t
I I I I I I I I I I I I I I I I I
is used to set a flip-flop FF as shown in Fig. 8. A suitable I I I I I I I I I I I I I I I I I
I I I I I I I
reset signal is used to disable the flip-flop at turn-off to
avoid incorrect operations. I I
The output VRof FF is then phase compared with Vcpd
obtained by delaying the signal enabling the current
generator as shown in Fig. 10 and 11. Such delay must be I I I I I I

I I I I I I I
suitably settled in order to compensate any propagation i -I- t +I -II-I- I t
I I I I
delay. I I I I I I I
The output of the phase comparator is processed by mI I I I I I I
mean of a low-pass filter generating a variable threshold I I I I I I I
V,. Such threshold is used to modify the firing times of the 1-I_ L 11-1- L
I I I I I I I
current pulses at turn-on in order to match the raising of
the Miller effect.
Fig. 12 - Voltage comparator inputs.
V [5V/div], t [2001is/div]

Any phase difference detected by the phase comparator

Fig. 10 - Phase comparator inputs at different frequencies.
V [SV/div], t [200ms/divj
modifies the time delay between the command signal and
the gate current pulses in such a way to reduce the phase
difference in the nest switching. After a suitable number
of cycles, related to the characteristics of the low pass
filter, the signal triggering the current pulses is correctly
sychronised with the rising of the Miller effect as shown in
Fig 13.
Using MOSFET devices similar considerations can be
made for the PLL circuit operating at turn-off.
In power circuits using IGBT devices, as yet observed,
the presence of the current tail largely reduces the
advantages of the proposed driving strategy, so that the
PLL circuit at turn-off can be avoided. However using a

485
double gate current pulse it is possible to significantly
reduce the power losses during the P-MOS turn-off phase
and the Miller zone of the IGBT turn-off transient [lo].
Fig. 13 - Voltage signal enabling current generator V,,
and gate votage.
V [SV/div], t [200ns/div]
5 . CONCLUSION
The development and the experimental evaluation of an
adaptive driving circuit based on a PLL approach for gate
controlled devices have been presented. An esperinieiital
evaluation of the device performances has been carried out
with both traditional and new driving circuit, aiming to
demonstrate the advantages of the new one. The most
important results obtained can be suniinarized as follows: the
automatic detection of the Miller effect makes the driving
circuit not dipendent on drived device arid operating
conditions. At turn-on arid turn-off the circuit permits to
separately control the voltage and current gradients, so
allowing the reduction of both power losses and EMI; i n
addition the turn-off delay time can easily be controlled. In
conclusion, on basis of the obtained results, it has been found
that the new driving circuit allows to get from the devices
better performances, and hence an increase of efficiency arid
reliability. The increased complexity and related cost suggest
to use the proposed circuit in high power applications.
486
ACKNOWLEDGMENTS
This work has been supported by the Italian Ministry of
University and Scientific Research (MURST 40 W).
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